[coreboot] coreboot+seabios+gpxe

Myles Watson mylesgw at gmail.com
Thu Mar 5 16:01:22 CET 2009

On Thu, Mar 5, 2009 at 7:41 AM, Piotr Brostovski <p.brostovski at levigo.de> wrote:
> Hello,
> i tried recently also to combine coreboot+seabios+gpxe.
> Sadly it didn't work.
> Are my addresses correct?
> 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78)
> 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01)
> #define OPTIONROM_BDF_1 0x0100
> #define OPTIONROM_MEM_1 0x1FF80000
> #define OPTIONROM_BDF_2 0x0060
> #define OPTIONROM_MEM_2 0x1FF70000
> i have a 512KB rom.
> i put the vga rom in first place, then the gpxe rom and after them the coreboot rom.
> (cat video.rom  gpxe-via.rom coreboot.rom > cb_seagpxe.rom)
> 64k video.rom bios and 64k gpxe-via.rom

They look wrong to me.  Using the example below as a guide, I would
have expected you to have:
#define OPTIONROM_BDF_1 0x0100
#define OPTIONROM_MEM_1 0xFFF80000
#define OPTIONROM_BDF_2 0x0060
#define OPTIONROM_MEM_2 0xFFF80000 + 64*1024
#define OPTIONROM_MEM_2 0xFFF90000

>> It's now possible to use a helper function when setting the BDF
>> values, so an equivalent of the above is:
>> #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0)
>> #define OPTIONROM_MEM_1 0xfffc0000
>> #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0)
>> #define OPTIONROM_MEM_2 0xfffcf800
>> To find the PCI addresses, look at the lspci and find the device ids.
>> On my machine they are from:
>> For the memory addresses, I have a 256KiB chip, and the first rom is
>> located at the start of the chip - so it is 0x100000000 - 0x40000 =
>> 0xfffc0000.


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