[coreboot] coreboot+seabios+gpxe

Piotr Brostovski p.brostovski at levigo.de
Thu Mar 5 16:50:22 CET 2009

ups, yes, thx!

But something seem to be still wrong:

Initializing VGA
found VGA: vid=1106, did=3344
rom base, size: fff80000
bus/devfn = 0x100
biosint: INT# 0xd
biosint: eax 0x5f0b ebx 0x10100 ecx 0x44 edx 0x110
biosint: ebp 0x1df44 esp 0xfbe edi 0x44 esi 0x9bd7
biosint:  ip 0xffff   cs 0xf000  flags 0x16
biosint: Oops, exception 13
Stack contents: 0xffff 0xf000 0x0016 0xb9c2 0xc000 0x0006 0x0142 0xbee0 0x0142 0x0044
0x0044 0x9bd7 0xdf44 0x0fe2 0x0100 0x0110 0x0044 0
biosint: Bailing out
elfboot: Attempting to load payload.
rom_stream: 0xfffa0000 - 0xfffeffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000
(cleaned up) New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000
Payload is overwriting Coreboot tables.
Dropping non PT_LOAD segment
Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000
Jumping to boot code at 0xfe2a7
Start bios
CPU Mhz=798
bios_table_addr: 0x000f7950 end=0x000f8150
SMBIOS table addr=0x000f7950
Ram Size=0x1e000000
Scan for option roms
Found option rom with bad checksum: loc=000c0000 len=55808 sum=000000e4
Changing serial settings was 00000003/00000002 now 00000003/00000000
enter handle_19:


Myles Watson schrieb:
> On Thu, Mar 5, 2009 at 7:41 AM, Piotr Brostovski <p.brostovski at levigo.de> wrote:
>> Hello,
>> i tried recently also to combine coreboot+seabios+gpxe.
>> Sadly it didn't work.
>> Are my addresses correct?
>> 0000:00:12.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 78)
>> 0000:01:00.0 VGA compatible controller: VIA Technologies, Inc.: Unknown device 3344 (rev 01)
>> #define OPTIONROM_BDF_1 0x0100
>> #define OPTIONROM_MEM_1 0x1FF80000
>> #define OPTIONROM_BDF_2 0x0060
>> #define OPTIONROM_MEM_2 0x1FF70000
>> i have a 512KB rom.
>> i put the vga rom in first place, then the gpxe rom and after them the coreboot rom.
>> (cat video.rom  gpxe-via.rom coreboot.rom > cb_seagpxe.rom)
>> 64k video.rom bios and 64k gpxe-via.rom
> They look wrong to me.  Using the example below as a guide, I would
> have expected you to have:
> #define OPTIONROM_BDF_1 0x0100
> #define OPTIONROM_MEM_1 0xFFF80000
> #define OPTIONROM_BDF_2 0x0060
> #define OPTIONROM_MEM_2 0xFFF80000 + 64*1024
> or
> #define OPTIONROM_MEM_2 0xFFF90000
>>> It's now possible to use a helper function when setting the BDF
>>> values, so an equivalent of the above is:
>>> #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0)
>>> #define OPTIONROM_MEM_1 0xfffc0000
>>> #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0)
>>> #define OPTIONROM_MEM_2 0xfffcf800
>>> To find the PCI addresses, look at the lspci and find the device ids.
>>> On my machine they are from:
>>> For the memory addresses, I have a 256KiB chip, and the first rom is
>>> located at the start of the chip - so it is 0x100000000 - 0x40000 =
>>> 0xfffc0000.
> Thanks,
> Myles

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