[coreboot] [v2] r4024 - in trunk/coreboot-v2/src: mainboard/asus/m2v-mx_se southbridge/via/k8t890

svn at coreboot.org svn at coreboot.org
Sat Mar 21 12:50:21 CET 2009


Author: ruik
Date: 2009-03-21 12:50:20 +0100 (Sat, 21 Mar 2009)
New Revision: 4024

Modified:
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
   trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c
Log:
To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-03-20 18:29:49 UTC (rev 4023)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb	2009-03-21 11:50:20 UTC (rev 4024)
@@ -34,7 +34,8 @@
 default _ROMBASE     = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
 
 ##WARNING enable caching of whole ROM during CAR
-default XIP_ROM_SIZE =  ROM_SIZE
+##for 512KB flash
+default XIP_ROM_SIZE =  0x80000
 default XIP_ROM_BASE =  0xffffffff + 1 - XIP_ROM_SIZE
 
 arch i386 end 

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-03-20 18:29:49 UTC (rev 4023)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c	2009-03-21 11:50:20 UTC (rev 4024)
@@ -21,8 +21,22 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <boot/tables.h>
 #include "chip.h"
 
+/* in arch/i386/boot/tables.c */
+extern uint64_t high_tables_base, high_tables_size;
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+#if HAVE_HIGH_TABLES == 1
+	printk_debug("Adding high table area\n");
+	lb_add_memory_range(mem, LB_MEM_TABLE,
+		high_tables_base, high_tables_size);
+#endif
+	return 0;
+}
+
 #if CONFIG_CHIP_NAME == 1
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("ASUS M2V-MX SE Mainboard")

Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c	2009-03-20 18:29:49 UTC (rev 4023)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c	2009-03-21 11:50:20 UTC (rev 4024)
@@ -91,6 +91,17 @@
 		(proposed_base < ((uint64_t) 0xffffffff) )) {
 		resmax = res;
 	}
+#if HAVE_HIGH_TABLES==1
+/* in arch/i386/boot/tables.c */
+extern uint64_t high_tables_base, high_tables_size;
+
+	if ((high_tables_base) && ((high_tables_base > proposed_base) &&
+			(high_tables_base < (res->base + res->size)))) {
+		high_tables_base = proposed_base - high_tables_size;
+		printk_debug("Moving the high_tables_base pointer to "
+				"new base %llx\n", high_tables_base);
+	}
+#endif
 }
 
 





More information about the coreboot mailing list