[coreboot] [v2] r4030 - in trunk/coreboot-v2/src: devices northbridge/amd/amdfam10 northbridge/amd/amdk8

[svn at coreboot.org]

Author: ruik
Date: 2009-03-26 22:45:26 +0100 (Thu, 26 Mar 2009)
New Revision: 4030

Modified:
   trunk/coreboot-v2/src/devices/pci_ops.c
   trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
Log:
During the suspend/resume programming I came to an issue that first 4KB of
memory must be clear with 0s because otherwise the resources of K8 will be
totally messed up.

res = probe_resource(dev, 0x100 + (reg | link));

This is called with dev = NULL and this is no good for probe_resource at all.
The attached patch fixes the potential problems and of course the problem
itself. On one particular place was missing test if the device really exists.
This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
The rest of the patch is just very paranoid and do all checkings.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Myles Watson <mylesgw at gmail.com>
--This line, and those below, will be igno
red--

M    src/devices/pci_ops.c
M    src/northbridge/amd/amdk8/northbridge.c
M    src/northbridge/amd/amdfam10/northbridge.c


Modified: trunk/coreboot-v2/src/devices/pci_ops.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_ops.c	2009-03-25 17:38:40 UTC (rev 4029)
+++ trunk/coreboot-v2/src/devices/pci_ops.c	2009-03-26 21:45:26 UTC (rev 4030)
@@ -27,7 +27,13 @@
 
 static struct bus *get_pbus(device_t dev)
 {
-	struct bus *pbus = dev->bus;
+	struct bus *pbus;
+
+	if (!dev)
+		printk_alert("get_pbus: dev is NULL!\n");
+
+	pbus = dev->bus;
+
 	while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
 		if (pbus == pbus->dev->bus) {
 			printk_alert("%s in endless loop looking for a parent "

Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-03-25 17:38:40 UTC (rev 4029)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c	2009-03-26 21:45:26 UTC (rev 4030)
@@ -338,6 +338,8 @@
 	for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) {
 		device_t dev;
 		dev = __f0_dev[nodeid];
+		if (!dev)
+			continue;
 		for(link = 0; !res && (link < 8); link++) {
 			res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1,
 		}

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-03-25 17:38:40 UTC (rev 4029)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-03-26 21:45:26 UTC (rev 4030)
@@ -291,9 +291,11 @@
 	unsigned nodeid, link;
 	int result;
 	res = 0;
-	for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
+	for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
 		device_t dev;
 		dev = __f0_dev[nodeid];
+		if (!dev)
+			continue;
 		for(link = 0; !res && (link < 3); link++) {
 			res = probe_resource(dev, 0x100 + (reg | link));
 		}
@@ -760,14 +762,15 @@
 		mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
 		mem_hole.node_id = -1;
 
-		for (i = 0; i < 8; i++) {
+		for (i = 0; i < FX_DEVS; i++) {
 			uint32_t base;
 			uint32_t hole;
 			base  = f1_read_config32(0x40 + (i << 3));
 			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 				continue;
 			}
-
+			if (!__f1_dev[i])
+				continue;
 			hole = pci_read_config32(__f1_dev[i], 0xf0);
 			if(hole & 1) { // we find the hole
 				mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
@@ -834,15 +837,15 @@
 	limit = f1_read_config32(0x44 + (i << 3));
 	f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 	dev = __f1_dev[i];
-	hoist = pci_read_config32(dev, 0xf0);
-	if(hoist & 1) {
-		pci_write_config32(dev, 0xf0, 0);
+	if (dev) {
+		hoist = pci_read_config32(dev, 0xf0);
+		if(hoist & 1) {
+			pci_write_config32(dev, 0xf0, 0);
+		} else {
+			base = pci_read_config32(dev, 0x40 + (i << 3));
+			f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
+		}
 	}
-	else {
-		base = pci_read_config32(dev, 0x40 + (i << 3));
-		f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
-	}
-
 }
 
 static uint32_t hoist_memory(unsigned long hole_startk, int i)
@@ -878,7 +881,7 @@
 		base |= (4*1024*1024)<<2;
 		f1_write_config32(0x40 + (i<<3), base);
 	}
-	else
+	else if (dev)
 	{
 		hoist = /* hole start address */
 			((hole_startk << 10) & 0xff000000) +
@@ -1020,7 +1023,7 @@
 		#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 			uint32_t basek_pri;
-			for (i = 0; i < 8; i++) {
+			for (i = 0; i < FX_DEVS; i++) {
 				uint32_t base;
 				uint32_t basek;
 				base  = f1_read_config32(0x40 + (i << 3));
@@ -1045,7 +1048,7 @@
 #endif
 
 	idx = 0x10;
-	for(i = 0; i < 8; i++) {
+	for(i = 0; i < FX_DEVS; i++) {
 		uint32_t base, limit;
 		unsigned basek, limitk, sizek;
 		base  = f1_read_config32(0x40 + (i << 3));