[coreboot] DL145G3

samuel samuel.verstraete at gmail.com
Fri Mar 27 08:59:43 CET 2009

All this talking about a single pin that is causing this is making me
think about something...
This mainboard has 2 jumpers. Each next to each other...
One is "BIOS RESET" and the other is "CRISIS PARK"... Could that
CRISIS PARK maybe connect to pin 8 to disable the flashrom writes??? I
guess if i measure the voltage and/or ohm that should tell me?

On Fri, Mar 27, 2009 at 8:55 AM, Peter Stuge <peter at stuge.se> wrote:
> samuel wrote:
>> >>Do you have access to a continuity tester? Please check this
>> >>connection.
>> I do not have access to a continuity tester.
> ..
>> >> * You can insulate the #TBL pin of the flash chip from the
>> >>   corresponding socket contact, and connect #TBL to Vdd. According
>> >>   to the datasheet of SST49LF080A, providing Vih(=Vdd) to #TBL
>> >>   disables write protection on the boot block.
>> I guess i can try this... I suppose it won't hurt?
> Yep, it's a good idea. Bend pin 8 up and make sure it doesn't have
> contact with the socket, then connect it to pin 32 or 25. (Both VDD)
>> >>Correct. It is most likely the cause. But - it would also be
>> >>interesting if you could measure the voltage Samuel, on pin 8
>> >>after having run flashrom in any mode.
>> I will get a volt meter... What pin should i use as ground? I tried
>> having a look at page 7 of the LPC data sheet but i didn't see a
>> ground pin...
> 16, VSS is ground.
> Maybe that volt meter also has an ohm meter function. That works
> well as a continuity tester too - if two points are connected the
> resistance will be 0.00 ohm.
> //Peter
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