[coreboot] DL145G3

[Sven Kapferer]

Peter Stuge schrieb:
> Sven Kapferer wrote:
>>> Any chance to find out what hardware is listening at 0xcd6/0xcd7?
>> The hardware listening on these ports is the BCM5785 (HT1000
>> southbridge).
>> Basically, the code just controls 2 GPIO pins that are connected to
>> WP and TBL of the BIOS chip.
> 
> Sure - but what determines the port - or rather, where can it be
> probed?
> 
> Data from Samuel suggests that the ports are configured by the BIOS,
> because the PNP0c02 device owns them ("system peripheral: other")
> according to ACPI tables.
> 
> Do you know if the base port is readable from a fixed register such
> as one in PCI config space?

According to the datasheet the ports are fixed.

- Sven

-- 
Sven Kapferer
University of Heidelberg - Computer Architecture Group
Address : B6 26, 68131 Mannheim, Germany
Web     : http://www.cag.uni-hd.de
Email   : sven.kapferer at ziti.uni-heidelberg.de
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