From mylesgw at gmail.com  Fri May  1 00:22:14 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 16:22:14 -0600
Subject: [coreboot] [PATCH] Remove warnings for s2892
Message-ID: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>

Remove warnings from compilation of the s2892 with and without CBFS.

I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.

For shadowed variable declarations I renamed the inner-most variable.

The one in src/pc80/keyboard.c might need help.  I didn't change the
functionality but it looks like a bug.

I boot tested it on s2892.

Abuild is about half way done.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From rminnich at gmail.com  Fri May  1 00:38:32 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 30 Apr 2009 15:38:32 -0700
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
Message-ID: <13426df10904301538x60784487kc28073604c121c00@mail.gmail.com>

Thanks for this fine work.

That pc80 thing is incredible.

Assuming it passes abuild,
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Fri May  1 00:45:41 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 00:45:41 +0200
Subject: [coreboot] [v2] r4240 - in trunk/coreboot-v2: src/arch/i386/boot
	src/arch/i386/include/arch/smp src/arch/i386/smp src/boot
	src/cpu/amd/dualcore src/cpu/x86/lapic src/cpu/x86/pae
	src/include src/lib src/mainboard/tyan/s2892
	src/northbridge/amd/amdk8 src/pc80
	src/southbridge/nvidia/ck804 util/cbfstool util/options
Message-ID: <mailman.3133.1355071532.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-05-01 00:45:41 +0200 (Fri, 01 May 2009)
New Revision: 4240

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/arch/i386/boot/tables.c
   trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h
   trunk/coreboot-v2/src/arch/i386/smp/mpspec.c
   trunk/coreboot-v2/src/boot/hardwaremain.c
   trunk/coreboot-v2/src/boot/selfboot.c
   trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c
   trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
   trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c
   trunk/coreboot-v2/src/include/cbfs.h
   trunk/coreboot-v2/src/lib/cbfs.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h
   trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
   trunk/coreboot-v2/src/pc80/keyboard.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/coreboot-v2/util/cbfstool/cbfstool.h
   trunk/coreboot-v2/util/cbfstool/util.c
   trunk/coreboot-v2/util/options/build_opt_tbl.c
Log:
Remove warnings from compilation of the s2892 with and without CBFS.

I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.

For shadowed variable declarations I renamed the inner-most variable.  

The one in src/pc80/keyboard.c might need help.  I didn't change the
functionality but it looks like a bug.

I boot tested it on s2892 and abuild tested it.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -428,7 +428,7 @@
 	printk_debug("Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
-	lb_forward(head, rom_table_end);
+	lb_forward(head, (struct lb_header*)rom_table_end);
 	lb_table_fini(head, 0);
 
 	low_table_end = (unsigned long)head;

Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/tables.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/arch/i386/boot/tables.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -66,7 +66,7 @@
 {
 	unsigned long low_table_start, low_table_end;
 	unsigned long rom_table_start, rom_table_end;
-#if HAVE_MP_TABLE == 1
+#if HAVE_MP_TABLE == 1 && HAVE_LOW_TABLES == 1
 	unsigned long new_low_table_end;
 #endif
 
@@ -114,16 +114,16 @@
 	 */
 #if HAVE_ACPI_TABLES == 1
 #if HAVE_HIGH_TABLES == 1
+#if HAVE_LOW_TABLES == 1
 	unsigned long high_rsdp=ALIGN(high_table_end, 16);
+	unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address);
+	acpi_write_rsdp(rom_table_end, rsdt_location);
+	rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16);
+#endif
 	if (high_tables_base) {
 		high_table_end = write_acpi_tables(high_table_end);
 		high_table_end = (high_table_end+1023) & ~1023;
 	}
-#if HAVE_LOW_TABLES == 1
-	unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address);
-	acpi_write_rsdp(rom_table_end, rsdt_location);
-	rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16);
-#endif
 #else
 #if HAVE_LOW_TABLES == 1
 	rom_table_end = write_acpi_tables(rom_table_end);

Modified: trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h	2009-04-30 22:45:41 UTC (rev 4240)
@@ -1,6 +1,7 @@
 #ifndef __ASM_MPSPEC_H
 #define __ASM_MPSPEC_H
 
+#include <device/device.h>
 /*
  * Structure definitions for SMP machines following the
  * Intel Multiprocessing Specification 1.1 and 1.4.

Modified: trunk/coreboot-v2/src/arch/i386/smp/mpspec.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/smp/mpspec.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/arch/i386/smp/mpspec.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -1,5 +1,4 @@
 #include <console/console.h>
-#include <device/device.h>
 #include <device/path.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
@@ -23,9 +22,6 @@
 
 void *smp_write_floating_table(unsigned long addr)
 {
-	struct intel_mp_floating *mf;
-	void *v;
-	
 	/* 16 byte align the table address */
 	addr = (addr + 0xf) & (~0xf);
 	return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN);

Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -99,9 +99,9 @@
 	lb_mem = write_tables();
 #if CONFIG_CBFS == 1
 # if USE_FALLBACK_IMAGE == 1
-	void (*pl)(void) = cbfs_load_payload(lb_mem, "fallback/payload");
+	cbfs_load_payload(lb_mem, "fallback/payload");
 # else
-	void (*pl)(void) = cbfs_load_payload(lb_mem, "normal/payload");
+	cbfs_load_payload(lb_mem, "normal/payload");
 # endif
 #else
 

Modified: trunk/coreboot-v2/src/boot/selfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/selfboot.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/boot/selfboot.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -302,7 +302,6 @@
 {
 	struct segment *new;
 	struct segment *ptr;
-	u8 *data;
 	int datasize;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
@@ -352,7 +351,7 @@
 
 		case PAYLOAD_SEGMENT_ENTRY:
 			printk_info("Entry %p\n", (void *) ntohl((u32) segment->load_addr));
-			*entry =  (void *) ntohl((u32) segment->load_addr);
+			*entry =  ntohl((u32) segment->load_addr);
 			return 1;
 		}
 		segment++;
@@ -392,15 +391,13 @@
 	
 	offset = 0;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		unsigned long skip_bytes, read_bytes;
 		unsigned char *dest, *middle, *end, *src;
-		byte_offset_t result;
 		printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
 		
 		/* Compute the boundaries of the segment */
 		dest = (unsigned char *)(ptr->s_dstaddr);
-		src = ptr->s_srcaddr;
+		src = (unsigned char *)(ptr->s_srcaddr);
 		
 		/* Copy data from the initial buffer */
 		if (ptr->s_filesz) {
@@ -451,13 +448,11 @@
 		}
 	}
 	return 1;
- out:
-	return 0;
 }
 
 int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 {
-	void *entry;
+	u32 entry=0;
 	struct segment head;
 	unsigned long bounce_buffer;
 
@@ -481,11 +476,11 @@
 	/* Reset to booting from this image as late as possible */
 	boot_successful();
 
-	printk_debug("Jumping to boot code at %p\n", entry);
+	printk_debug("Jumping to boot code at %x\n", entry);
 	post_code(0xfe);
 
 	/* Jump to kernel */
-	jmp_to_elf_entry(entry, bounce_buffer);
+	jmp_to_elf_entry((void*)entry, bounce_buffer);
 	return 1;
 
  out:

Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -62,9 +62,6 @@
 	unsigned nb_cfg_54;
         int bsp_apic_id = lapicid(); // bsp apicid
 
-        int disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-
         get_option(&disable_siblings, "dual_core");
 
         //get the nodes number

Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -252,8 +252,8 @@
 	} else {
 		// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 		stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
-#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
-		#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
+#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
+		#warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n"
 #endif
 		if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 			printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);

Modified: trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -59,11 +59,11 @@
 	 pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, 
 	 and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config
 	*/
-	struct pg_table *pgtbl = 0x100000; //1M
+	struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M
 
 	unsigned x_end = 0x100000 + sizeof(struct pg_table) * CONFIG_MAX_CPUS;
-#if (0x100000+20480*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
-                #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPU)\n"
+#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
+                #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
 #endif
 	if(x_end > (CONFIG_LB_MEM_TOPK<<10)) {
                         printk_debug("map_2M_page: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", x_end>>10);

Modified: trunk/coreboot-v2/src/include/cbfs.h
===================================================================
--- trunk/coreboot-v2/src/include/cbfs.h	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/include/cbfs.h	2009-04-30 22:45:41 UTC (rev 4240)
@@ -49,6 +49,7 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
+#include <boot/coreboot_tables.h>
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
     payloads.  Of course, other LAR users can use whatever

Modified: trunk/coreboot-v2/src/lib/cbfs.c
===================================================================
--- trunk/coreboot-v2/src/lib/cbfs.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/lib/cbfs.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -20,7 +20,6 @@
 #include <types.h>
 #include <string.h>
 #include <console/console.h>
-#include <boot/coreboot_tables.h>
 #include <cbfs.h>
 
 #ifndef CONFIG_BIG_ENDIAN

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -90,8 +90,6 @@
 
 static void sio_setup(void)
 {
-
-	unsigned value;
 	uint32_t dword;
 	uint8_t byte;
 
@@ -102,7 +100,6 @@
 	dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 	dword |= (1<<0);
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
 }
 
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout	2009-04-30 22:45:41 UTC (rev 4240)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -65,7 +65,7 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	printk_info("Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h	2009-04-30 22:45:41 UTC (rev 4240)
@@ -244,7 +244,6 @@
 #include "raminit.h"
 //struct definitions
 
-#if RAMINIT_SYSINFO==1
 struct link_pair_st {
         device_t udev;
         uint32_t upos;
@@ -267,9 +266,7 @@
         uint32_t sblk;
         uint32_t sbbusn;
 } __attribute__((packed));
-#endif
 
-
 #endif
 
 #endif /* AMDK8_H */

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -218,8 +218,6 @@
 }
 
 static int k8acpi_write_HT(void) {
-	device_t dev;
-	uint32_t dword;
 	int len, lenp, i;
 
 	len = acpigen_write_name("HCLK");

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -3,6 +3,10 @@
  *
  */
 
+#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+#endif
+
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -11,6 +11,10 @@
 	#define K8_HT_FREQ_1G_SUPPORT 0
 #endif
 
+#ifndef RAMINIT_SYSINFO
+	#define RAMINIT_SYSINFO 0
+#endif
+
 #ifndef K8_SCAN_PCI_BUS
 	#define K8_SCAN_PCI_BUS 0
 #endif
@@ -79,7 +83,6 @@
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
 {
 	device_t dev;
-	uint32_t id;
 
 	//actually, only for one HT device HT chain, and unitid is 0
 #if HT_CHAIN_UNITID_BASE == 0
@@ -90,6 +93,7 @@
 
 	/* Check if is already collapsed */
 	if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) {
+		uint32_t id;
 		dev = PCI_DEV(bus, 0, 0);
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 		if (!((id == 0xffffffff) || (id == 0x00000000) ||
@@ -556,7 +560,9 @@
 
 	} while (last_unitid != next_unitid );
 
+#if HT_CHAIN_END_UNITID_BASE != 0x20
 out:
+#endif
 end_of_chain: ;
 
 #if HT_CHAIN_END_UNITID_BASE != 0x20

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -288,7 +288,7 @@
 	device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
 {
 	struct resource *res;
-	unsigned nodeid, link;
+	unsigned nodeid, link=0;
 	int result;
 	res = 0;
 	for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
@@ -648,16 +648,16 @@
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
 			unsigned nodeid, link;
-			device_t dev;
+			device_t reg_dev;
 			nodeid = limit & 7;
 			link   = (limit >> 4) & 3;
-			dev = __f0_dev[nodeid];
-			if (dev) {
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
 				/* Reserve the resource  */
-				struct resource *resource;
-				resource = new_resource(dev, 0x100 + (reg | link));
-				if (resource) {
-					resource->flags = 1;
+				struct resource *reg_resource;
+				reg_resource = new_resource(reg_dev, 0x100 + (reg | link));
+				if (reg_resource) {
+					reg_resource->flags = 1;
 				}
 			}
 		}
@@ -1222,20 +1222,20 @@
 	/* Find which cpus are present */
 	cpu_bus = &dev->link[0];
 	for(i = 0; i < sysconf.nodes; i++) {
-		device_t dev, cpu;
+		device_t cpu_dev, cpu;
 		struct device_path cpu_path;
 
 		/* Find the cpu's pci device */
-		dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
-		if (!dev) {
+		cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+		if (!cpu_dev) {
 			/* If I am probing things in a weird order
 			 * ensure all of the cpu's pci devices are found.
 			 */
-			int j;
+			int local_j;
 			device_t dev_f0;
-			for(j = 0; j <= 3; j++) {
-				dev = pci_probe_dev(NULL, dev_mc->bus,
-					PCI_DEVFN(0x18 + i, j));
+			for(local_j = 0; local_j <= 3; local_j++) {
+				cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
+					PCI_DEVFN(0x18 + i, local_j));
 			}
 			/* Ok, We need to set the links for that device.
 			 * otherwise the device under it will not be scanned
@@ -1243,19 +1243,19 @@
 			dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
 			if(dev_f0) {
 				dev_f0->links = 3;
-				for(j=0;j<3;j++) {
-					dev_f0->link[j].link = j;
-					dev_f0->link[j].dev = dev_f0;
+				for(local_j=0;local_j<3;local_j++) {
+					dev_f0->link[local_j].link = local_j;
+					dev_f0->link[local_j].dev = dev_f0;
 				}
 			}
 
 		}
 
 		e0_later_single_core = 0;
-		if (dev && dev->enabled) {
-			j = pci_read_config32(dev, 0xe8);
+		if (cpu_dev && cpu_dev->enabled) {
+			j = pci_read_config32(cpu_dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\n", dev_path(dev), j);
+			printk_debug("  %s siblings=%d\n", dev_path(cpu_dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
@@ -1308,7 +1308,7 @@
 			cpu = find_dev_path(cpu_bus, &cpu_path);
 
 			/* Enable the cpu if I have the processor */
-			if (dev && dev->enabled) {
+			if (cpu_dev && cpu_dev->enabled) {
 				if (!cpu) {
 					cpu = alloc_dev(cpu_bus, &cpu_path);
 				}
@@ -1318,7 +1318,7 @@
 			}
 
 			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!dev || !dev->enabled)) {
+			if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
 				cpu->enabled = 0;
 			}
 

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -805,7 +805,6 @@
 	};
 
 	uint32_t map;
-	uint32_t dch;
 
 	map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
 	map &= ~(0xf << (index * 4));
@@ -1491,19 +1490,19 @@
 
 		/* Loop through and find a fast clock with a low latency */
 		for(index = 0; index < 3; index++, latency++) {
-			int value;
+			int spd_value;
 			if ((latency < 2) || (latency > 4) ||
 				(!(latencies & (1 << latency)))) {
 				continue;
 			}
-			value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
-			if (value < 0) {
+			spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+			if (spd_value < 0) {
 				goto hw_error;
 			}
 
 			/* Only increase the latency if we decreas the clock */
-			if ((value >= min_cycle_time) && (value < new_cycle_time)) {
-				new_cycle_time = value;
+			if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) {
+				new_cycle_time = spd_value;
 				new_latency = latency;
 			}
 		}
@@ -1527,7 +1526,7 @@
 		int latencies;
 		int latency;
 		int index;
-		int value;
+		int spd_value;
 		if (!(dimm_mask & (1 << i))) {
 			continue;
 		}
@@ -1554,13 +1553,13 @@
 		}
 
 		/* Read the min_cycle_time for this latency */
-		value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
-		if (value < 0) goto hw_error;
+		spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+		if (spd_value < 0) goto hw_error;
 
 		/* All is good if the selected clock speed
 		 * is what I need or slower.
 		 */
-		if (value <= min_cycle_time) {
+		if (spd_value <= min_cycle_time) {
 			continue;
 		}
 		/* Otherwise I have an error, disable the dimm */

Modified: trunk/coreboot-v2/src/pc80/keyboard.c
===================================================================
--- trunk/coreboot-v2/src/pc80/keyboard.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/pc80/keyboard.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -112,11 +112,11 @@
 		outb(0x60, 0x64);
 		if (!kbc_input_buffer_empty()) return;
 		outb(0x20, 0x60);	/* send cmd: enable keyboard and IRQ 1 */
-		u8 resend = 10;
+		u8 broken_resend = 10;
 		if ((inb(0x64) & 0x01)) {
 			regval = inb(0x60);
 		}
-		--resend;
+		--broken_resend;
 	} while (regval == 0xFE && resend > 0);
 
 	/* clean up any junk that might have been in the keyboard */

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -171,7 +171,7 @@
 
 	pci_write_config32(dev, 0x44, 0xfed00001);
 	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
-	printk_debug("Enabling HPET @0x%x\n", hpet_address);
+	printk_debug("Enabling HPET @0x%lx\n", hpet_address);
 }
 
 unsigned pm_base=0;
@@ -184,7 +184,7 @@
 	lpc_common_init(dev);
 
 	pm_base = pci_read_config32(dev, 0x60) & 0xff00;
-	printk_info("%s: pm_base = %lx \n", __func__, pm_base);
+	printk_info("%s: pm_base = %x \n", __func__, pm_base);
 
 #if CK804_CHIP_REV==1
 	if (dev->bus->secondary != 1)

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -22,7 +22,7 @@
 	struct resource *res;
 
 	res = find_resource(dev, 0x10);
-	base = res->base;
+	base = (uint8_t*)(unsigned long)res->base;
 
 #define NvRegPhyInterface  0xC0
 #define PHY_RGMII          0x10000000
@@ -76,8 +76,8 @@
 	if (!eeprom_valid) {
 		unsigned long mac_pos;
 		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
-		mac_l = readl(mac_pos) + nic_index;
-		mac_h = readl(mac_pos + 4);
+		mac_l = readl((uint8_t*)mac_pos) + nic_index;
+		mac_h = readl((uint8_t*)mac_pos + 4);
 	}
 #if 1
 	/* Set that into NIC MMIO. */

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -11,6 +11,10 @@
 #include <device/pci_ops.h>
 #include "ck804.h"
 
+#ifndef CK804_SATA_RESET_FOR_ATAPI
+#define CK804_SATA_RESET_FOR_ATAPI 0
+#endif
+
 #if CK804_SATA_RESET_FOR_ATAPI
 static void sata_com_reset(struct device *dev, unsigned reset)
 // reset = 1 : reset

Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/cbfstool.h	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/util/cbfstool/cbfstool.h	2009-04-30 22:45:41 UTC (rev 4240)
@@ -58,7 +58,7 @@
 /* util.c */
 int open_rom(struct rom *rom, const char *filename);
 int create_rom(struct rom *rom, const unsigned char *filename, int size,
-	       const unsigned char *bootblockname, int bootblocksize,
+	       const char *bootblockname, int bootblocksize,
 	       int align);
 int size_and_open(const char *filename, unsigned int *size);
 int copy_from_fd(int fd, void *ptr, int size);

Modified: trunk/coreboot-v2/util/cbfstool/util.c
===================================================================
--- trunk/coreboot-v2/util/cbfstool/util.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/util/cbfstool/util.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -168,7 +168,7 @@
 }
 
 int create_rom(struct rom *rom, const unsigned char *filename,
-	       int romsize, const unsigned char *bootblockname,
+	       int romsize, const char *bootblockname,
 	       int bootblocksize, int align)
 {
 	unsigned char null = '\0';
@@ -226,7 +226,6 @@
 	unsigned int size;
 	int fd = size_and_open(filename, &size);
 	int ret;
-	struct cbfs_header tmp;
 
 	if (fd == -1)
 		return -1;

Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c
===================================================================
--- trunk/coreboot-v2/util/options/build_opt_tbl.c	2009-04-30 16:46:12 UTC (rev 4239)
+++ trunk/coreboot-v2/util/options/build_opt_tbl.c	2009-04-30 22:45:41 UTC (rev 4240)
@@ -487,6 +487,7 @@
 
 	/* See if we want to output a C source file */
 	if(option) {
+		int err=0;
 		strncpy(tmpfilename, dirname(option), TMPFILE_LEN);
 	        strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN);
 		tmpfile = mkstemp(tmpfilename);
@@ -510,13 +511,13 @@
         	}
 		/* write the array values */
 		for(i=0;i<(ct->size-1);i++) {
-			if(!(i%10)) fwrite("\n\t",1,2,fp);
+			if(!(i%10) && !err) err=fwrite("\n\t",1,2,fp);
 			sprintf(buf,"0x%02x,",cmos_table[i]);
-			fwrite(buf,1,5,fp);
+			if(!err) err=fwrite(buf,1,5,fp);
 		}
 		/* write the end */
 		sprintf(buf,"0x%02x\n",cmos_table[i]);
-		fwrite(buf,1,4,fp);
+		if(!err) err=fwrite(buf,1,4,fp);
         	if(!fwrite("};\n",1,3,fp)) {
         	        perror("Error - Could not write image file");
         	        fclose(fp);




From mylesgw at gmail.com  Fri May  1 00:47:32 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 16:47:32 -0600
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <13426df10904301538x60784487kc28073604c121c00@mail.gmail.com>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
	<13426df10904301538x60784487kc28073604c121c00@mail.gmail.com>
Message-ID: <2831fecf0904301547m1024bcb9o73d4370dbcf0ed2a@mail.gmail.com>

On Thu, Apr 30, 2009 at 4:38 PM, ron minnich <rminnich at gmail.com> wrote:
> Thanks for this fine work.
>
> That pc80 thing is incredible.
Should we take it out or enable it?  It's dead code right now.

> Assuming it passes abuild,
Yes.

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Rev 4240.

Thanks,
Myles



From peter at stuge.se  Fri May  1 01:46:57 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 May 2009 01:46:57 +0200
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
Message-ID: <20090430234657.25468.qmail@stuge.se>

Myles Watson wrote:
> +++ cbv2/src/pc80/keyboard.c	2009-04-30 15:47:16.000000000 -0600
> @@ -112,11 +112,11 @@
>  		outb(0x60, 0x64);
>  		if (!kbc_input_buffer_empty()) return;
>  		outb(0x20, 0x60);	/* send cmd: enable keyboard and IRQ 1 */
> -		u8 resend = 10;
> +		u8 broken_resend = 10;
>  		if ((inb(0x64) & 0x01)) {
>  			regval = inb(0x60);
>  		}
> -		--resend;
> +		--broken_resend;
>  	} while (regval == 0xFE && resend > 0);

This does not look right to me. I think the good fix is to not rename
things but only remove the u8 (re)declaration on line 115. Very good
find!


//Peter



From kevin at koconnor.net  Fri May  1 01:47:00 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 19:47:00 -0400
Subject: [coreboot] SeaBIOS and hp dl145g3
In-Reply-To: <2831fecf0904300824o7b9b2d99pa111e144ff25d635@mail.gmail.com>
References: <bc122a250904290753i5749390fn7c9e25f572bcc11a@mail.gmail.com>
	<20090430004304.GA7329@morn.localdomain>
	<bc122a250904300807r6855facaube47b4ca8718c6af@mail.gmail.com>
	<2831fecf0904300824o7b9b2d99pa111e144ff25d635@mail.gmail.com>
Message-ID: <20090430234700.GA20152@morn.localdomain>

On Thu, Apr 30, 2009 at 09:24:22AM -0600, Myles Watson wrote:
> On Thu, Apr 30, 2009 at 9:07 AM, samuel <samuel.verstraete at gmail.com> wrote:
> > On Thu, Apr 30, 2009 at 2:43 AM, Kevin O'Connor <kevin at koconnor.net> wrote:
> >> On Wed, Apr 29, 2009 at 04:53:13PM +0200, samuel wrote:
> >>> lspci -vnn : http://merlin.ugent.be/~samuel/dl145g3/info/lspci-vnn.txt
> 
> 01:0e.0 RAID bus controller [0104]: Broadcom BCM5785 [HT1000] SATA
> (Native SATA Mode) [1166:024a] (prog-if 05)
[...]
> This forces SeaBIOS to see it as a PATA controller, but it's in SATA mode.
> 
> Is there an easy way to add SATA support to SeaBIOS?  It sounds like a
> bit of work.  It looks like you could force the device to be in PATA
> mode, but once it's booted that's not ideal.

SeaBIOS only supports PATA mode.  To the best of my knowledge, filo
also only supports PATA mode drives (or SATA drives connected to a
PATA compatible controller).

I'm not against adding support, but I don't have the knowledge to do
it at this time.

-Kevin



From mylesgw at gmail.com  Fri May  1 02:11:51 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 18:11:51 -0600
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <20090430234657.25468.qmail@stuge.se>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
	<20090430234657.25468.qmail@stuge.se>
Message-ID: <1A47A0881D6B4D92965C1C9468E9C3F2@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Peter Stuge
> Sent: Thursday, April 30, 2009 5:47 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] Remove warnings for s2892
> 
> Myles Watson wrote:
> > +++ cbv2/src/pc80/keyboard.c	2009-04-30 15:47:16.000000000 -0600
> > @@ -112,11 +112,11 @@
> >  		outb(0x60, 0x64);
> >  		if (!kbc_input_buffer_empty()) return;
> >  		outb(0x20, 0x60);	/* send cmd: enable keyboard and IRQ
1 */
> > -		u8 resend = 10;
> > +		u8 broken_resend = 10;
> >  		if ((inb(0x64) & 0x01)) {
> >  			regval = inb(0x60);
> >  		}
> > -		--resend;
> > +		--broken_resend;
> >  	} while (regval == 0xFE && resend > 0);
> 
> This does not look right to me. I think the good fix is to not rename
> things but only remove the u8 (re)declaration on line 115. 
I didn't do that because it would change the behavior and I wouldn't be able
to tell breakage by building.  I don't know enough about keyboard
controllers to test this part of the code.

> Very good
> find!
Luckily the compiler did most of the work :)

Thanks,
Myles





From peter at stuge.se  Fri May  1 02:29:22 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 May 2009 02:29:22 +0200
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <1A47A0881D6B4D92965C1C9468E9C3F2@chimp>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
	<20090430234657.25468.qmail@stuge.se>
	<1A47A0881D6B4D92965C1C9468E9C3F2@chimp>
Message-ID: <20090501002922.4716.qmail@stuge.se>

Myles Watson wrote:
> > This does not look right to me. I think the good fix is to not rename
> > things but only remove the u8 (re)declaration on line 115. 
> 
> I didn't do that because it would change the behavior and I wouldn't
> be able to tell breakage by building.  I don't know enough about
> keyboard controllers to test this part of the code.

The semantics of the changed code are pretty simple and looking at
other parts of the same file shows that it is a common construct.

It's used to retry keyboard communication a few times in case the
keyboard is slow or just generally crappy.

If you make a patch it is

Acked-by: Peter Stuge <peter at stuge.se>

:)


//Peter



From joe at settoplinux.org  Fri May  1 02:43:49 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 30 Apr 2009 20:43:49 -0400
Subject: [coreboot] unexpected exception errors loading vga rom
In-Reply-To: <13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>
References: <833def118eec581027d3ad14707ae547@imap.1and1.com>
	<13426df10904291636y5ba2eb3dvba3f151aaa60ddb@mail.gmail.com>
	<f74e88d00bd9fe848ba95b21b53e99ec@imap.1and1.com>
	<13426df10904292113p5b0260y873e665f121a6083@mail.gmail.com>
	<b44eeb59ad0fe940fb215727ae6f8793@imap.1and1.com>
	<13426df10904300755r19a6ca9cy93d37cb62c83ae23@mail.gmail.com>
	<13426df10904301010s4af19a2bh3e45e3b8a2aaa913@mail.gmail.com>
	<37dbdb96d1d380a6d8fc29ef01faafee@imap.1and1.com>
	<13426df10904301334p1622d571u216754cc42f11635@mail.gmail.com>
	<d81426ec15d6af5e49e3f98fcd0d5133@imap.1and1.com>
	<13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>
Message-ID: <fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>




On Thu, 30 Apr 2009 14:55:59 -0700, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Apr 30, 2009 at 2:01 PM, Joseph Smith <joe at settoplinux.org>
wrote:
> 
>> Right the INT lines A,B,C, and D are hard wired. But you can asign any
> PIRQ
>> to a function and any available IRQ to the PIRQ these are software
>> controlled.
>>>
> 
> The 3d register lists what functions can assert what interrupt lines.
> what is the value of 3d for each of these four device functions? You
> can use setpci to see.
> setpci -s bus:dev.fn 3d.b
> 
> 
> 
>> Hmm. That is another way of looking at it. The doc does say the "device"
>> acts as a interrupt router (which is INTA in this case). So the other
> three
>> are directly connected to it? Like the attached image?
> 
> I doubt that is exactly it but I think it's closer to my internal
> picture. 
I wish you could make your internal picture external, so I could see what
it is then.
So to test this I theory I should just be able to pluck out oh lets say
function 2 on INTB. If everythings works great except USB2 than that theory
is correct. On the otherhand if we loose USB2, USB3, and EHCI than we know
they are routed through each other. Correct?
Like this:
{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x00000}, {0x62, 0x1ef8},
{0x6b, 0x01ef8}}, 0x0, 0x0},


> What the 3d register will tell you is what INT is wired to
> each function. So, e.g., I would guest that 3d is like this:
> 
> USB1 1
> USB2 2
> USB3 3
> EHCI 4
> 
Yup.
00:1d.0 USB Controller #1 - 0x3d = 0x01
00:1d.1 USB Controller #2 - 0x3d = 0x02
00:1d.2 USB Controller #3 - 0x3d = 0x03
00:1d.7 USB Controller EHCI - 0x3d = 0x04

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From kevin at koconnor.net  Fri May  1 03:00:59 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 21:00:59 -0400
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090430030432.GA31307@localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
Message-ID: <20090501010059.GA20735@morn.localdomain>

On Wed, Apr 29, 2009 at 11:04:32PM -0400, Ward Vandewege wrote:
> I tried exactly that today (gmta ;), but that didn't seem to work for me -
> and SeaBIOS complained about an option rom checksum mismatch on the
> sgabios.bin option rom.

That's odd - it works fine for me.  Can you confirm the sgabios build
and then forward me the SeaBIOS log with it in CBFS?

> Since every other component in the boot process already does serial - how
> hard would it be to make SeaBIOS do serial too?

Well, SeaBIOS does support serial.  What you're looking for is the
ability to forward vgabios requests over serial.  SeaBIOS doesn't have
any vgabios capabilities today, so it would be a bit of work.  Since
sgabios is already designed to do this, I'm not sure what the value
would be in duplicating it in SeaBIOS.

> > >   serial --unit=0 --speed=115200 --word=8 --parity=no --stop=1
> > >   terminal --timeout=5 serial console
> > 
> > The only thing I can think of is that SeaBIOS may be setting the
> > serial port settings to something that grub doesn't like.  You can try
> > disabling the code in debug_serial_setup() in src/output.c.  However,
> > if you've already tried disabling CONFIG_DEBUG_SERIAL, then I don't
> > think this will do much.  It could be a conflict with coreboot serial
> > setup and grub I suppose.
> 
> Hmm. Suggestions for debugging?

You could try disabling serial in both coreboot and seabios.  It seems
like a "long shot" though.

You could change grub to dump the serial registers and then run it
from both the proprietary bios and from coreboot/seabios - just to see
if there is a serial port difference.

Maybe there is a debugging mode of grub that you could activate?

-Kevin



From joe at settoplinux.org  Fri May  1 03:05:37 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 30 Apr 2009 21:05:37 -0400
Subject: [coreboot] unexpected exception errors loading vga rom
In-Reply-To: <fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
References: <833def118eec581027d3ad14707ae547@imap.1and1.com>
	<13426df10904291636y5ba2eb3dvba3f151aaa60ddb@mail.gmail.com>
	<f74e88d00bd9fe848ba95b21b53e99ec@imap.1and1.com>
	<13426df10904292113p5b0260y873e665f121a6083@mail.gmail.com>
	<b44eeb59ad0fe940fb215727ae6f8793@imap.1and1.com>
	<13426df10904300755r19a6ca9cy93d37cb62c83ae23@mail.gmail.com>
	<13426df10904301010s4af19a2bh3e45e3b8a2aaa913@mail.gmail.com>
	<37dbdb96d1d380a6d8fc29ef01faafee@imap.1and1.com>
	<13426df10904301334p1622d571u216754cc42f11635@mail.gmail.com>
	<d81426ec15d6af5e49e3f98fcd0d5133@imap.1and1.com>
	<13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>
	<fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
Message-ID: <0baa932274e3090cd567092c608a843a@imap.1and1.com>


>> What the 3d register will tell you is what INT is wired to
>> each function. So, e.g., I would guest that 3d is like this:
>>
>> USB1 1
>> USB2 2
>> USB3 3
>> EHCI 4
>>
> Yup.
> 00:1d.0 USB Controller #1 - 0x3d = 0x01
> 00:1d.1 USB Controller #2 - 0x3d = 0x02
> 00:1d.2 USB Controller #3 - 0x3d = 0x03
> 00:1d.7 USB Controller EHCI - 0x3d = 0x04
> 
FYI, here is what the ICH4 data sheet says about these 0x3d registers.
Looks like the PIRQ is internally specific.

USB 1,2, & 3 0x3d
Interrupt Pin (INT_PN) ? RO. The values of 01h, 02h, and 03h in function
0, 1, and 2, respectively,
indicate to software that the corresponding ICH4 UHCI USB controllers drive
the INTA#, INTB#, and
INTC# PCI signals.
Note that this does not determine the mapping to the ICH4 PIRQ inputs.
Function 0 will drive PIRQA.
Function 1 will drive PIRQD. Function 2 will drive PIRQC. Function 1 does
not use the corresponding
mapping in order to spread the interrupts with AC97, which has historically
been mapped to PIRQB.

EHCI 0x3d
Interrupt Pin (INT_PN) ? RO. The value of 04h indicates that the USB EHCI
function within the
ICH4?s multi-function USB device will drive the fourth interrupt pin from
the device (INTD# in PCI
terms). The value of 04h in function 7 is required because the PCI
specification does not recognize
more than 4 interrupts and older APM-based OSs require that each function
within a multi-function
device has a different Interrupt Pin Register value.
NOTE: Internally the USB EHCI controller uses PIRQ[H]#.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From ward at gnu.org  Fri May  1 03:18:45 2009
From: ward at gnu.org (Ward Vandewege)
Date: Thu, 30 Apr 2009 21:18:45 -0400
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090501010059.GA20735@morn.localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
	<20090501010059.GA20735@morn.localdomain>
Message-ID: <20090501011845.GA15113@localdomain>

On Thu, Apr 30, 2009 at 09:00:59PM -0400, Kevin O'Connor wrote:
> On Wed, Apr 29, 2009 at 11:04:32PM -0400, Ward Vandewege wrote:
> > I tried exactly that today (gmta ;), but that didn't seem to work for me -
> > and SeaBIOS complained about an option rom checksum mismatch on the
> > sgabios.bin option rom.
> 
> That's odd - it works fine for me.  Can you confirm the sgabios build
> and then forward me the SeaBIOS log with it in CBFS?

Will do tomorrow.

> > Since every other component in the boot process already does serial - how
> > hard would it be to make SeaBIOS do serial too?
> 
> Well, SeaBIOS does support serial.  What you're looking for is the
> ability to forward vgabios requests over serial.  SeaBIOS doesn't have
> any vgabios capabilities today, so it would be a bit of work.  Since
> sgabios is already designed to do this, I'm not sure what the value
> would be in duplicating it in SeaBIOS.

So - here's the problem with the sgabios approach. Unless I'm
misunderstanding how this works, using sgabios means that I'd have to disable
serial in any payload started from grub, as well?

I'm trying to get as minimal a changeset as possible between proprietary
bios/coreboot.

> > > >   serial --unit=0 --speed=115200 --word=8 --parity=no --stop=1
> > > >   terminal --timeout=5 serial console
> > > 
> > > The only thing I can think of is that SeaBIOS may be setting the
> > > serial port settings to something that grub doesn't like.  You can try
> > > disabling the code in debug_serial_setup() in src/output.c.  However,
> > > if you've already tried disabling CONFIG_DEBUG_SERIAL, then I don't
> > > think this will do much.  It could be a conflict with coreboot serial
> > > setup and grub I suppose.
> > 
> > Hmm. Suggestions for debugging?
> 
> You could try disabling serial in both coreboot and seabios.  It seems
> like a "long shot" though.
> 
> You could change grub to dump the serial registers and then run it
> from both the proprietary bios and from coreboot/seabios - just to see
> if there is a serial port difference.
> 
> Maybe there is a debugging mode of grub that you could activate?

Will investigate tomorrow...

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From joe at settoplinux.org  Fri May  1 03:32:55 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 30 Apr 2009 21:32:55 -0400
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
Message-ID: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>

This is a patch to use another IRQ besides IRQ12 to fix conflicts with
i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took me
this long to catch this because I usually use a USB mouse.

Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
-------------- next part --------------
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From peter at stuge.se  Fri May  1 03:40:13 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 May 2009 03:40:13 +0200
Subject: [coreboot] PCI interrupts
In-Reply-To: <fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
References: <f74e88d00bd9fe848ba95b21b53e99ec@imap.1and1.com>
	<13426df10904292113p5b0260y873e665f121a6083@mail.gmail.com>
	<b44eeb59ad0fe940fb215727ae6f8793@imap.1and1.com>
	<13426df10904300755r19a6ca9cy93d37cb62c83ae23@mail.gmail.com>
	<13426df10904301010s4af19a2bh3e45e3b8a2aaa913@mail.gmail.com>
	<37dbdb96d1d380a6d8fc29ef01faafee@imap.1and1.com>
	<13426df10904301334p1622d571u216754cc42f11635@mail.gmail.com>
	<d81426ec15d6af5e49e3f98fcd0d5133@imap.1and1.com>
	<13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>
	<fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
Message-ID: <20090501014013.22184.qmail@stuge.se>

Joseph Smith wrote:
> I wish you could make your internal picture external, so I could
> see what it is then.

Interrupts are a little complex. I'll try to add some things.


The PCI bus allows each PCI device (by device I mean chip, with a
device id, and possibly with several functions) to use at most four
interrupt signals. They are called INTA, INTB, INTC and INTD.

Each PCI device is allowed to use (=activate) zero or more of them.
Devices with several functions can benefit from using more interrupt
signals, because then each function can get it's own interrupt
signal, which helps throughput. When multiple bus INTx signals are
connected to a device, how the device INTx pins are connected
internally in the device to the various functions is described by the
mapping in register 3d for each function, as Ron mentioned.

Many devices only generate one interrupt signal, and that will always
be INTA on the device. Some generate more than one signal.

The mainboard designer can swizzle interrupt signals between devices,
in order to spread out interrupt load so that four devices all
signalling on "their" INTA do not have to share the INTA bus signal.

The four PCI bus interrupt signals do not (and should not!) connect
to all PCI devices in parallell. The PCI bus INTA may be connected to
device 1 INTA, and device 2 INTB. This routing is what irq_tables.c
expresses, and unfortunately it cannot be probed. It's really a small
part of the mainboard netlist.

There's one device per line in irq_tables.c. How many of the four
fields in irq_tables.c which require values depends on how many
interrupt signals that are connected to that device.

So much for the PCI bus.

Between the bus and the CPU there's more logic. Different chipsets
have different complexity. This is the PIC/XPIC/APIC/IOAPIC. It needs
to be configured by firmware to pass on the PCI bus interrupt signals
to the CPU, and it can usually map the four bus interrupts onto any
of the 16 first CPU interrupts. The original PC had the same PIC
which remains today.

The PIC mapping determines which CPU interrupts can be assigned to
the devices and have them actually work.

Originally it was hoped that operating systems would do interrupt
assignment, but that did not work out. The firmware has to do most
if not all of this work with mapping the system and telling devices
about which CPU interrupts they are generating.

Register 3c is not really used by hardware, it just stores the
interrupt assignment for each device, it is written by the resource
allocator and read by the operating system device driver.

There's no connection between register 3c and the PIC mapping either,
so the resource allocator has to keep track of the PCI bus as well as
the PIC mapping in order to assign working interrupts to devices.


http://tldp.org/LDP/tlk/dd/pci.html has more info about the PCI bus.

I hope this helps. :)

//Peter



From kevin at koconnor.net  Fri May  1 03:52:00 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 21:52:00 -0400
Subject: [coreboot] Random extra option ROMs in CBFS
In-Reply-To: <64847D14E39B45F5BC22E9C35521F48C@chimp>
References: <20090430091504.11431.qmail@stuge.se>
	<64847D14E39B45F5BC22E9C35521F48C@chimp>
Message-ID: <20090501015200.GB20735@morn.localdomain>

On Thu, Apr 30, 2009 at 06:05:29AM -0600, Myles Watson wrote:
> > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> > On Behalf Of Peter Stuge
> > Kevin O'Connor wrote:
> > > Add sgabios.bin to the CBFS system using a PCI vendor:device of a
> > > device in your system that doesn't already have an option rom and
> > > isn't a vga or ide device.
> > I think it's important to improve this situation. The PCI ids are
> > clearly not relevant to this option ROM, so we should not require
> > them.
> Kevin already added an img/ path for payloads.  I guess he could add
> a path for ROM-style images (ones that will return.)  They'd have to
> be numbered so that they were executed in order, but that doesn't
> seem like too much of a problem.

That sounds like a good idea.  Latest SeaBIOS git will launch any
option rom in the CBFS directory "genroms/".  For example, one can add
"genroms/sgabios.rom" or the lzma compressed
"genroms/sgabios.rom.lzma".  The rom(s) will be run after the vga and
PCI roms are run.

Adding ordering support is a bit of a pain.  Lets see if it is needed.

-Kevin



From svn at coreboot.org  Fri May  1 04:24:40 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 04:24:40 +0200
Subject: [coreboot] [v2] r4241 - trunk/coreboot-v2/src/pc80
Message-ID: <mailman.3134.1355071532.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-05-01 04:24:40 +0200 (Fri, 01 May 2009)
New Revision: 4241

Modified:
   trunk/coreboot-v2/src/pc80/keyboard.c
Log:
The semantics of the changed code are pretty simple and looking at
other parts of the same file shows that it is a common construct.

Remove the shadowed variable.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>

Modified: trunk/coreboot-v2/src/pc80/keyboard.c
===================================================================
--- trunk/coreboot-v2/src/pc80/keyboard.c	2009-04-30 22:45:41 UTC (rev 4240)
+++ trunk/coreboot-v2/src/pc80/keyboard.c	2009-05-01 02:24:40 UTC (rev 4241)
@@ -112,11 +112,10 @@
 		outb(0x60, 0x64);
 		if (!kbc_input_buffer_empty()) return;
 		outb(0x20, 0x60);	/* send cmd: enable keyboard and IRQ 1 */
-		u8 broken_resend = 10;
 		if ((inb(0x64) & 0x01)) {
 			regval = inb(0x60);
 		}
-		--broken_resend;
+		--resend;
 	} while (regval == 0xFE && resend > 0);
 
 	/* clean up any junk that might have been in the keyboard */




From kevin at koconnor.net  Fri May  1 04:26:56 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 22:26:56 -0400
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090501011845.GA15113@localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
	<20090501010059.GA20735@morn.localdomain>
	<20090501011845.GA15113@localdomain>
Message-ID: <20090501022656.GC20735@morn.localdomain>

On Thu, Apr 30, 2009 at 09:18:45PM -0400, Ward Vandewege wrote:
> So - here's the problem with the sgabios approach. Unless I'm
> misunderstanding how this works, using sgabios means that I'd have
> to disable serial in any payload started from grub, as well?

It seems to work fine under qemu.  In any case, a seabios
implementation would have the same issues as sgabios - it would need
to do exactly what sgabios does.

> > > > >   serial --unit=0 --speed=115200 --word=8 --parity=no --stop=1
> > > > >   terminal --timeout=5 serial console

I've reproduced this problem under qemu.  If I boot
qemu/coreboot/seabios/grub, then grub wont use the serial console.
However, if I boot qemu/seabios/grub, then grub seems to work fine.
The above is true regardless of whether SeaBIOS has serial port
debugging on or off.  I guess coreboot is initialzing the serial port
in some way that grub doesn't like.

What's really odd, is that if I have sgabios on, then grub does work
okay.  I didn't catch this last night because I was also playing with
sgabios at the same time.  As a guess, sgabios is reinitializing the
serial port back to a way grub is okay with.  This may be specific to
qemu, but it's something to look into.

-Kevin



From mylesgw at gmail.com  Fri May  1 04:28:52 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 20:28:52 -0600
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <20090501002922.4716.qmail@stuge.se>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com><20090430234657.25468.qmail@stuge.se><1A47A0881D6B4D92965C1C9468E9C3F2@chimp>
	<20090501002922.4716.qmail@stuge.se>
Message-ID: <193110C6B248493ABCC9ED01372787EF@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Peter Stuge
> Sent: Thursday, April 30, 2009 6:29 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] Remove warnings for s2892
> 
> Myles Watson wrote:
> > > This does not look right to me. I think the good fix is to not rename
> > > things but only remove the u8 (re)declaration on line 115.
> >
> > I didn't do that because it would change the behavior and I wouldn't
> > be able to tell breakage by building.  I don't know enough about
> > keyboard controllers to test this part of the code.
> 
> The semantics of the changed code are pretty simple and looking at
> other parts of the same file shows that it is a common construct.
> 
> It's used to retry keyboard communication a few times in case the
> keyboard is slow or just generally crappy.
> 
> If you make a patch it is
> 
> Acked-by: Peter Stuge <peter at stuge.se>
Rev 4241.

Thanks,
Myles




From mylesgw at gmail.com  Fri May  1 04:34:31 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 20:34:31 -0600
Subject: [coreboot] Random extra option ROMs in CBFS
In-Reply-To: <20090501015200.GB20735@morn.localdomain>
References: <20090430091504.11431.qmail@stuge.se>
	<64847D14E39B45F5BC22E9C35521F48C@chimp>
	<20090501015200.GB20735@morn.localdomain>
Message-ID: <99C905A376A040E1A2273DA3560F827F@chimp>



> -----Original Message-----
> From: Kevin O'Connor [mailto:kevin at koconnor.net]
> Sent: Thursday, April 30, 2009 7:52 PM
> To: Myles Watson
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Random extra option ROMs in CBFS
> 
> On Thu, Apr 30, 2009 at 06:05:29AM -0600, Myles Watson wrote:
> > > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> bounces at coreboot.org]
> > > On Behalf Of Peter Stuge
> > > Kevin O'Connor wrote:
> > > > Add sgabios.bin to the CBFS system using a PCI vendor:device of a
> > > > device in your system that doesn't already have an option rom and
> > > > isn't a vga or ide device.
> > > I think it's important to improve this situation. The PCI ids are
> > > clearly not relevant to this option ROM, so we should not require
> > > them.
> > Kevin already added an img/ path for payloads.  I guess he could add
> > a path for ROM-style images (ones that will return.)  They'd have to
> > be numbered so that they were executed in order, but that doesn't
> > seem like too much of a problem.
> 
> That sounds like a good idea.  Latest SeaBIOS git will launch any
> option rom in the CBFS directory "genroms/".  For example, one can add
> "genroms/sgabios.rom" or the lzma compressed
> "genroms/sgabios.rom.lzma".  The rom(s) will be run after the vga and
> PCI roms are run.

That was fast!

> Adding ordering support is a bit of a pain.  Lets see if it is needed.

Sure.  So right now they're run in the order they're found?

Thanks,
Myles




From kevin at koconnor.net  Fri May  1 04:39:31 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 22:39:31 -0400
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090501022656.GC20735@morn.localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
	<20090501010059.GA20735@morn.localdomain>
	<20090501011845.GA15113@localdomain>
	<20090501022656.GC20735@morn.localdomain>
Message-ID: <20090501023931.GA28467@morn.localdomain>

On Thu, Apr 30, 2009 at 10:26:56PM -0400, Kevin O'Connor wrote:
> What's really odd, is that if I have sgabios on, then grub does work
> okay.  I didn't catch this last night because I was also playing with
> sgabios at the same time.  As a guess, sgabios is reinitializing the
> serial port back to a way grub is okay with.  This may be specific to
> qemu, but it's something to look into.

Oops - if qemu/coreboot/seabios/sgabios/grub, then sgabios forwards
the grub screen over serial - grub itself still wont talk to the
serial directly.  (If I run qemu/seabios/sgabios/grub then I get two
copies of the grub messages - one from grub serial and one from grub
screen via sgabios.)

-Kevin



From mylesgw at gmail.com  Fri May  1 04:40:16 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 20:40:16 -0600
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090501022656.GC20735@morn.localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
	<20090501010059.GA20735@morn.localdomain>
	<20090501011845.GA15113@localdomain>
	<20090501022656.GC20735@morn.localdomain>
Message-ID: <2831fecf0904301940j33c30948xcef3d533a13f369e@mail.gmail.com>

On Thu, Apr 30, 2009 at 8:26 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> On Thu, Apr 30, 2009 at 09:18:45PM -0400, Ward Vandewege wrote:
>> So - here's the problem with the sgabios approach. Unless I'm
>> misunderstanding how this works, using sgabios means that I'd have
>> to disable serial in any payload started from grub, as well?
>
> It seems to work fine under qemu. ?In any case, a seabios
> implementation would have the same issues as sgabios - it would need
> to do exactly what sgabios does.
>
>> > > > > ? serial --unit=0 --speed=115200 --word=8 --parity=no --stop=1
>> > > > > ? terminal --timeout=5 serial console
>
> I've reproduced this problem under qemu. ?If I boot
> qemu/coreboot/seabios/grub, then grub wont use the serial console.
> However, if I boot qemu/seabios/grub, then grub seems to work fine.
> The above is true regardless of whether SeaBIOS has serial port
> debugging on or off. ?I guess coreboot is initialzing the serial port
> in some way that grub doesn't like.

I wonder if this is the same reason the serial console doesn't work
from Linux sometimes when I do Linux-as-Bootloader kernels in the ROM.
 I gave up on that method because it was too hard to debug without
serial output.

Thanks,
Myles



From rminnich at gmail.com  Fri May  1 04:43:58 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 30 Apr 2009 19:43:58 -0700
Subject: [coreboot] PCI interrupts
In-Reply-To: <20090501014013.22184.qmail@stuge.se>
References: <f74e88d00bd9fe848ba95b21b53e99ec@imap.1and1.com>
	<b44eeb59ad0fe940fb215727ae6f8793@imap.1and1.com>
	<13426df10904300755r19a6ca9cy93d37cb62c83ae23@mail.gmail.com>
	<13426df10904301010s4af19a2bh3e45e3b8a2aaa913@mail.gmail.com>
	<37dbdb96d1d380a6d8fc29ef01faafee@imap.1and1.com>
	<13426df10904301334p1622d571u216754cc42f11635@mail.gmail.com>
	<d81426ec15d6af5e49e3f98fcd0d5133@imap.1and1.com>
	<13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>
	<fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
	<20090501014013.22184.qmail@stuge.se>
Message-ID: <13426df10904301943o29e8f09ft8398cbc0b1375d9@mail.gmail.com>

Good writeup. Might be worth putting on the wiki!

ron



From kevin at koconnor.net  Fri May  1 05:00:59 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 30 Apr 2009 23:00:59 -0400
Subject: [coreboot] Random extra option ROMs in CBFS
In-Reply-To: <99C905A376A040E1A2273DA3560F827F@chimp>
References: <20090430091504.11431.qmail@stuge.se>
	<64847D14E39B45F5BC22E9C35521F48C@chimp>
	<20090501015200.GB20735@morn.localdomain>
	<99C905A376A040E1A2273DA3560F827F@chimp>
Message-ID: <20090501030059.GA28929@morn.localdomain>

On Thu, Apr 30, 2009 at 08:34:31PM -0600, Myles Watson wrote:
> > From: Kevin O'Connor [mailto:kevin at koconnor.net]
> > Adding ordering support is a bit of a pain.  Lets see if it is needed.
> Sure.  So right now they're run in the order they're found?

Yes.  (And only after vga and pci roms are run.)

-Kevin



From svn at coreboot.org  Fri May  1 05:04:21 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 05:04:21 +0200
Subject: [coreboot] [v2] r4242 - in trunk/coreboot-v2/src/mainboard:
	rca/rm4100 thomson/ip1000
Message-ID: <mailman.3135.1355071532.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-01 05:04:20 +0200 (Fri, 01 May 2009)
New Revision: 4242

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c
Log:
Trivial cosmetic fixes to IP1000 and RM4100 irq_tables.c Signed-off-by: Joseph Smith <joe at settoplinux.org> Acked-by: Joseph Smith <joe at settoplinux.org>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c	2009-05-01 02:24:40 UTC (rev 4241)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c	2009-05-01 03:04:20 UTC (rev 4242)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,13 +34,13 @@
 	0xcd,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */
-		{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
-		{0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
-		{0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
-		{0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */
-		{0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */
-		{0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */
+		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
+		{0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
+		{0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
+		{0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
+		{0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
+		{0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
+		{0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
 	}
 };
 

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c	2009-05-01 02:24:40 UTC (rev 4241)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c	2009-05-01 03:04:20 UTC (rev 4242)
@@ -34,13 +34,13 @@
 	0xcd,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */
-		{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
-		{0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
-		{0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
-		{0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */
-		{0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */
-		{0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */
+		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
+		{0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
+		{0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
+		{0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
+		{0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
+		{0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
+		{0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
 	}
 };
 




From joe at settoplinux.org  Fri May  1 05:28:15 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 30 Apr 2009 23:28:15 -0400
Subject: [coreboot] [PATCH] Change default rom emulator to VM86 on IP1000
	and RM4100
Message-ID: <f8cb0c518597a6938802694975d116d8@imap.1and1.com>

This patch changes the default rom emulator to VM86 on IP1000 and RM4100
(it is much faster than x86emu or YABEL).

Signed-off-by: Joesph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From joe at settoplinux.org  Fri May  1 05:52:03 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 30 Apr 2009 23:52:03 -0400
Subject: [coreboot] [PATCH]i82830 custom vga driver
Message-ID: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>

This patch allows a custom vga driver that will give the flexibility to run
code after vga is initialized for tv-out. It is one of many patches to
come, including code to manipulate the graphics mmio registers, enable the
graphics i2c data lines, and tv encoder drivers.

Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From hansolofalcon at worldnet.att.net  Fri May  1 05:53:33 2009
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Thu, 30 Apr 2009 23:53:33 -0400
Subject: [coreboot] Set Top Boxes and composite (!) video out
Message-ID: <0308DA1EDA4F454EB28B3797E58A046B@who8>

Hello!
Joseph I've been following your progress regarding these examples, both on
your site, and here.

I have some to ask question: First; have you gotten to the point of being
able to present any composite video out on that connector?

Second; where did you obtain these units? Every time I check Amazon for them
I get shocked by the prices they are quoting, it's as if they are trying to
sell me a brand new never been opened first edition of something.

And yes I'll accept an answer off list if you feel that's best.
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 






From mylesgw at gmail.com  Fri May  1 06:03:00 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 22:03:00 -0600
Subject: [coreboot] [PATCH] Change default rom emulator to VM86 on
	IP1000 and RM4100
In-Reply-To: <f8cb0c518597a6938802694975d116d8@imap.1and1.com>
References: <f8cb0c518597a6938802694975d116d8@imap.1and1.com>
Message-ID: <2831fecf0904302103s68f0d246s27cf4aaf74746ac2@mail.gmail.com>

On Thu, Apr 30, 2009 at 9:28 PM, Joseph Smith <joe at settoplinux.org> wrote:
> This patch changes the default rom emulator to VM86 on IP1000 and RM4100
> (it is much faster than x86emu or YABEL).
>
> Signed-off-by: Joesph Smith <joe at settoplinux.org>
Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



From mylesgw at gmail.com  Fri May  1 06:06:26 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 22:06:26 -0600
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
Message-ID: <2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>

On Thu, Apr 30, 2009 at 9:52 PM, Joseph Smith <joe at settoplinux.org> wrote:
> This patch allows a custom vga driver that will give the flexibility to run
> code after vga is initialized for tv-out. It is one of many patches to
> come, including code to manipulate the graphics mmio registers, enable the
> graphics i2c data lines, and tv encoder drivers.

Should it be conditionally included via a config option?  Are there
other boards with the same chipset that won't want to use this TV-out
initialization?

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



From mylesgw at gmail.com  Fri May  1 06:09:58 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 22:09:58 -0600
Subject: [coreboot] SeaBIOS and hp dl145g3
In-Reply-To: <20090430234700.GA20152@morn.localdomain>
References: <bc122a250904290753i5749390fn7c9e25f572bcc11a@mail.gmail.com>
	<20090430004304.GA7329@morn.localdomain>
	<bc122a250904300807r6855facaube47b4ca8718c6af@mail.gmail.com>
	<2831fecf0904300824o7b9b2d99pa111e144ff25d635@mail.gmail.com>
	<20090430234700.GA20152@morn.localdomain>
Message-ID: <C2516455701A43CB9B798C02F19DB629@chimp>



> -----Original Message-----
> From: Kevin O'Connor [mailto:kevin at koconnor.net]
> Sent: Thursday, April 30, 2009 5:47 PM
> To: Myles Watson
> Cc: samuel; coreboot
> Subject: Re: SeaBIOS and hp dl145g3
> 
> On Thu, Apr 30, 2009 at 09:24:22AM -0600, Myles Watson wrote:
> > On Thu, Apr 30, 2009 at 9:07 AM, samuel <samuel.verstraete at gmail.com>
> wrote:
> > > On Thu, Apr 30, 2009 at 2:43 AM, Kevin O'Connor <kevin at koconnor.net>
> wrote:
> > >> On Wed, Apr 29, 2009 at 04:53:13PM +0200, samuel wrote:
> > >>> lspci -vnn : http://merlin.ugent.be/~samuel/dl145g3/info/lspci-
> vnn.txt
> >
> > 01:0e.0 RAID bus controller [0104]: Broadcom BCM5785 [HT1000] SATA
> > (Native SATA Mode) [1166:024a] (prog-if 05)
> [...]
> > This forces SeaBIOS to see it as a PATA controller, but it's in SATA
> mode.
> >
> > Is there an easy way to add SATA support to SeaBIOS?  It sounds like a
> > bit of work.  It looks like you could force the device to be in PATA
> > mode, but once it's booted that's not ideal.
> 
> SeaBIOS only supports PATA mode.  To the best of my knowledge, filo
> also only supports PATA mode drives (or SATA drives connected to a
> PATA compatible controller).

The interesting thing is that filo supports this board even though it is in
SATA mode.

> I'm not against adding support, but I don't have the knowledge to do
> it at this time.

No problem.  I mostly wanted your opinion on the cleanest and easiest way
forward for this box.

Thanks,
Myles





From rminnich at gmail.com  Fri May  1 06:17:26 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 30 Apr 2009 21:17:26 -0700
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
Message-ID: <13426df10904302117w10a9ca33v692cad93940ac279@mail.gmail.com>

I don't know enough about boards that use this chip. But I do think
you might want to at least check Myle's suggestion that there be a
conditonal in the Config.lb.

OTOH, how many targets actively use this part (meaning are those
boards in use today or ...)

ron



From joe at settoplinux.org  Fri May  1 06:19:25 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:19:25 -0400
Subject: [coreboot] Set Top Boxes and composite (!) video out
In-Reply-To: <0308DA1EDA4F454EB28B3797E58A046B@who8>
References: <0308DA1EDA4F454EB28B3797E58A046B@who8>
Message-ID: <5f61cf00d0f62e388b088853b80780d4@imap.1and1.com>




On Thu, 30 Apr 2009 23:53:33 -0400, "Gregg C Levine"
<hansolofalcon at worldnet.att.net> wrote:
> Hello!
> Joseph I've been following your progress regarding these examples, both
on
> your site, and here.
> 
> I have some to ask question: First; have you gotten to the point of being
> able to present any composite video out on that connector?
>
Yes we recently made some real break through's with intelfb in Linux, we
figured we should get it running in Linux first and then it will be
coreboot time, and it should be relatively simple to turn it into coreboot
code.
> 
> Second; where did you obtain these units? Every time I check Amazon for
> them
> I get shocked by the prices they are quoting, it's as if they are trying
> to
> sell me a brand new never been opened first edition of something.
> 
> And yes I'll accept an answer off list if you feel that's best.

Funny. I remember when we first started hacking the RM4100, you could buy
them on eBay for less than 5 dollars, too a lot of people they were just
paper weights if they didn't want to pay the outrageous monthly
subscription fee, then word got out that you could run Linux on them and
then prices shot way up. Well, I would say the best places are eBay,
Amazon, and Overstock.com, If you keep your eye out you could probably find
one for under 50 dollars. I won't mention some of the other names they sell
under but if you look on my site you will find them mentioned.

If your interested there is a guy on my site that is selling a box he
started hacking (he just added a vga connector) for 10 dollars plus
shipping:
http://www.settoplinux.org/index.php?title=Special:AWCforum&action=st%2Fid58%2Fmy_RM4100_for_sale.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 06:30:40 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:30:40 -0400
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
Message-ID: <6ae6b6631550cee673469f65921463c2@imap.1and1.com>




On Thu, 30 Apr 2009 22:06:26 -0600, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Apr 30, 2009 at 9:52 PM, Joseph Smith <joe at settoplinux.org>
wrote:
>> This patch allows a custom vga driver that will give the flexibility to
> run
>> code after vga is initialized for tv-out. It is one of many patches to
>> come, including code to manipulate the graphics mmio registers, enable
> the
>> graphics i2c data lines, and tv encoder drivers.
> 
> Should it be conditionally included via a config option?  Are there
> other boards with the same chipset that won't want to use this TV-out
> initialization?
> 
Yup there will be, I hopefully I am going to try to make the code generic
enough so it can be used with other Intel 8xx and 9xx chipsets (alot of the
mmio registers are the same) and put it in a common locattion. Also the
tv-out drivers will open the door for other tv encoder chips, and LVDS
chips for laptops (this means things like blacklight control), etc. Anyways
the idea is to have a global config option for the tv chip, that way it
will know which code to run and if global config option is not defined it
will run just as the patch is now, the default vga init.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 06:32:55 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:32:55 -0400
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
Message-ID: <c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>




On Thu, 30 Apr 2009 21:32:55 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> This is a patch to use another IRQ besides IRQ12 to fix conflicts with
> i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took
> me
> this long to catch this because I usually use a USB mouse.
> 
> Signed-off-by: Joseph Smith <joe at settoplinux.org>
> 
> --
This one too?
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri May  1 06:36:38 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 06:36:38 +0200
Subject: [coreboot] [v2] r4243 - in trunk/coreboot-v2/src/mainboard:
	amd/pistachio amd/serengeti_cheetah arima/hdama asus/a8n_e
	asus/a8v-e_se asus/m2v-mx_se broadcom/blast gigabyte/m57sli
	ibm/e325 ibm/e326 iwill/dk8_htx iwill/dk8s2 iwill/dk8x
	newisys/khepri supermicro/h8dme supermicro/h8dmr tyan/s2735
	tyan/s2875 tyan/s2882 tyan/s2885 tyan/s2895 tyan/s4882
Message-ID: <mailman.3136.1355071533.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-05-01 06:36:38 +0200 (Fri, 01 May 2009)
New Revision: 4243

Modified:
   trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout
   trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout
   trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout
   trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout
   trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout
   trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout
   trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout
Log:
Trivial patch to make #defines generated from cmos.layout have unique names.  Kills a few more compiler warnings.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -67,7 +67,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -45,7 +45,7 @@
     728 256 h 0 user_data
     984 16 h 0 check_sum
 # Reserve the extended AMD configuration registers
-    1000 24 r 0 reserved_memory
+    1000 24 r 0 reserved_memory1
 
 enumerations
 

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -67,7 +67,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -67,7 +67,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -67,7 +67,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -44,7 +44,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout	2009-05-01 03:04:20 UTC (rev 4242)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout	2009-05-01 04:36:38 UTC (rev 4243)
@@ -46,7 +46,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        reserved_memory1
 
 
 




From svn at coreboot.org  Fri May  1 06:37:13 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 06:37:13 +0200
Subject: [coreboot] [v2] r4244 -
	trunk/coreboot-v2/src/northbridge/intel/i82830
Message-ID: <mailman.3137.1355071533.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-01 06:37:13 +0200 (Fri, 01 May 2009)
New Revision: 4244

Added:
   trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
Modified:
   trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb
Log:
This patch allows a custom vga driver that will give the flexibility to run code after vga is initialized for tv-out. 
Signed-off-by: Joseph Smith <joe at settoplinux.org> 
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb	2009-05-01 04:36:38 UTC (rev 4243)
+++ trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb	2009-05-01 04:37:13 UTC (rev 4244)
@@ -23,5 +23,6 @@
 config chip.h
 
 driver northbridge.o
+driver vga.o
 
 default HAVE_HIGH_TABLES=1

Added: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c	2009-05-01 04:37:13 UTC (rev 4244)
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void vga_init(device_t dev) {
+
+	printk_info("Starting Graphics Initialization\n");
+	pci_dev_init(dev);
+	printk_info("Graphics Initialization Complete\n");
+	/* Future TV-OUT code will be called from here. */
+}
+
+static const struct device_operations vga_operations = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = vga_init,
+	.scan_bus         = 0,
+	.enable           = 0,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+	.ops    = &vga_operations,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x3577,
+};


Property changes on: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
___________________________________________________________________
Added: svn:executable
   + *




From hansolofalcon at worldnet.att.net  Fri May  1 06:38:17 2009
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Fri, 1 May 2009 00:38:17 -0400
Subject: [coreboot] Set Top Boxes and composite (!) video out
In-Reply-To: <5f61cf00d0f62e388b088853b80780d4@imap.1and1.com>
Message-ID: <D6B40BDAB8FC42BFA63EF48D6F05BAB4@who8>

Hello!
It is indeed quite reasonable. And I indeed am interested. So what do I do
to obtain it?
--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 


> -----Original Message-----
> From: Joseph Smith [mailto:joe at settoplinux.org]
> Sent: Friday, May 01, 2009 12:19 AM
> To: Gregg C Levine
> Cc: Coreboot
> Subject: Re: [coreboot] Set Top Boxes and composite (!) video out
> 
> 
> 
> 
> On Thu, 30 Apr 2009 23:53:33 -0400, "Gregg C Levine"
> <hansolofalcon at worldnet.att.net> wrote:
> > Hello!
> > Joseph I've been following your progress regarding these examples, both
> on
> > your site, and here.
> >
> > I have some to ask question: First; have you gotten to the point of
being
> > able to present any composite video out on that connector?
> >
> Yes we recently made some real break through's with intelfb in Linux, we
> figured we should get it running in Linux first and then it will be
> coreboot time, and it should be relatively simple to turn it into coreboot
> code.
> >
> > Second; where did you obtain these units? Every time I check Amazon for
> > them
> > I get shocked by the prices they are quoting, it's as if they are trying
> > to
> > sell me a brand new never been opened first edition of something.
> >
> > And yes I'll accept an answer off list if you feel that's best.
> 
> Funny. I remember when we first started hacking the RM4100, you could buy
> them on eBay for less than 5 dollars, too a lot of people they were just
> paper weights if they didn't want to pay the outrageous monthly
> subscription fee, then word got out that you could run Linux on them and
> then prices shot way up. Well, I would say the best places are eBay,
> Amazon, and Overstock.com, If you keep your eye out you could probably
find
> one for under 50 dollars. I won't mention some of the other names they
sell
> under but if you look on my site you will find them mentioned.
> 
> If your interested there is a guy on my site that is selling a box he
> started hacking (he just added a vga connector) for 10 dollars plus
> shipping:
>
http://www.settoplinux.org/index.php?title=Special:AWCforum&action=st%2Fid58
%2Fmy
> _RM4100_for_sale.
> 
> --
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org




From joe at settoplinux.org  Fri May  1 06:38:14 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:38:14 -0400
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
Message-ID: <e9bde33b81849bdf76e491d73fee5693@imap.1and1.com>




On Thu, 30 Apr 2009 22:06:26 -0600, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Apr 30, 2009 at 9:52 PM, Joseph Smith <joe at settoplinux.org>
wrote:
>> This patch allows a custom vga driver that will give the flexibility to
> run
>> code after vga is initialized for tv-out. It is one of many patches to
>> come, including code to manipulate the graphics mmio registers, enable
> the
>> graphics i2c data lines, and tv encoder drivers.
> 
> Should it be conditionally included via a config option?  Are there
> other boards with the same chipset that won't want to use this TV-out
> initialization?
> 
> Acked-by: Myles Watson <mylesgw at gmail.com>
> 
Thanks r4244
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mylesgw at gmail.com  Fri May  1 06:38:22 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 22:38:22 -0600
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
	<c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>
Message-ID: <241E1082E53F44ED80B815B31984BD48@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Joseph Smith
> Sent: Thursday, April 30, 2009 10:33 PM
> To: coreboot
> Subject: Re: [coreboot] [PATCH] i82801xx IRQ Fix Up
> 
> 
> 
> 
> On Thu, 30 Apr 2009 21:32:55 -0400, Joseph Smith <joe at settoplinux.org>
> wrote:
> > This is a patch to use another IRQ besides IRQ12 to fix conflicts with
> > i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took
> > me
> > this long to catch this because I usually use a USB mouse.
> >
> > Signed-off-by: Joseph Smith <joe at settoplinux.org>
> >
> > --
> This one too?
I was going to look up IRQ 4 first.  I don't pretend to know too much about
IRQs.

Myles




From svn at coreboot.org  Fri May  1 06:44:36 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 06:44:36 +0200
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
	src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000
	targets/rca/rm4100 targets/thomson/ip1000
Message-ID: <mailman.3138.1355071533.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-01 06:44:36 +0200 (Fri, 01 May 2009)
New Revision: 4245

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
   trunk/coreboot-v2/targets/rca/rm4100/Config.lb
   trunk/coreboot-v2/targets/thomson/ip1000/Config.lb
Log:
This patch changes the default rom emulator to VM86. 
Signed-off-by: Joseph Smith <joe at settoplinux.org> 
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-05-01 04:37:13 UTC (rev 4244)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-05-01 04:44:36 UTC (rev 4245)
@@ -24,6 +24,7 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_IOAPIC
+uses CONFIG_PCI_OPTION_ROM_RUN_VM86
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
@@ -78,6 +79,7 @@
 default HAVE_OPTION_TABLE = 0
 default CONFIG_CONSOLE_VGA = 0
 default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
 default CONFIG_VIDEO_MB = 0
 default STACK_SIZE = 0x2000
 default HEAP_SIZE = 0x4000

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01 04:37:13 UTC (rev 4244)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01 04:44:36 UTC (rev 4245)
@@ -24,6 +24,7 @@
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_IOAPIC
+uses CONFIG_PCI_OPTION_ROM_RUN_VM86
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
@@ -78,6 +79,7 @@
 default HAVE_OPTION_TABLE = 0
 default CONFIG_CONSOLE_VGA = 0
 default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
 default CONFIG_VIDEO_MB = 0
 default STACK_SIZE = 0x2000
 default HEAP_SIZE = 0x4000

Modified: trunk/coreboot-v2/targets/rca/rm4100/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:37:13 UTC (rev 4244)
+++ trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:44:36 UTC (rev 4245)
@@ -37,6 +37,7 @@
 ##
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_PCI_ROM_RUN = 1
+option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
 
 ##
 ## Choose the amount of memory pre-allocated for VGA

Modified: trunk/coreboot-v2/targets/thomson/ip1000/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/thomson/ip1000/Config.lb	2009-05-01 04:37:13 UTC (rev 4244)
+++ trunk/coreboot-v2/targets/thomson/ip1000/Config.lb	2009-05-01 04:44:36 UTC (rev 4245)
@@ -37,6 +37,7 @@
 ##
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_PCI_ROM_RUN = 1
+option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
 
 ##
 ## Choose the amount of memory pre-allocated for VGA




From mylesgw at gmail.com  Fri May  1 06:45:28 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 30 Apr 2009 22:45:28 -0600
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <241E1082E53F44ED80B815B31984BD48@chimp>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
	<c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>
	<241E1082E53F44ED80B815B31984BD48@chimp>
Message-ID: <2831fecf0904302145h1a38e4abla73e6e632320171a@mail.gmail.com>

On Thu, Apr 30, 2009 at 10:38 PM, Myles Watson <mylesgw at gmail.com> wrote:
>
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Joseph Smith
>> Sent: Thursday, April 30, 2009 10:33 PM
>> To: coreboot
>> Subject: Re: [coreboot] [PATCH] i82801xx IRQ Fix Up
>>
>>
>>
>>
>> On Thu, 30 Apr 2009 21:32:55 -0400, Joseph Smith <joe at settoplinux.org>
>> wrote:
>> > This is a patch to use another IRQ besides IRQ12 to fix conflicts with
>> > i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took
>> > me
>> > this long to catch this because I usually use a USB mouse.
>> >
>> > Signed-off-by: Joseph Smith <joe at settoplinux.org>
>> >
>> > --
>> This one too?
> I was going to look up IRQ 4 first. ?I don't pretend to know too much about
> IRQs.
Acked-by: Myles Watson <mylesgw at gmail.com>


From joe at settoplinux.org  Fri May  1 06:45:26 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:45:26 -0400
Subject: [coreboot] [PATCH] Change default rom emulator to VM86 on
 IP1000 and RM4100
In-Reply-To: <2831fecf0904302103s68f0d246s27cf4aaf74746ac2@mail.gmail.com>
References: <f8cb0c518597a6938802694975d116d8@imap.1and1.com>
	<2831fecf0904302103s68f0d246s27cf4aaf74746ac2@mail.gmail.com>
Message-ID: <a2157ba56719758b96918dff7c55e1a4@imap.1and1.com>




On Thu, 30 Apr 2009 22:03:00 -0600, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Apr 30, 2009 at 9:28 PM, Joseph Smith <joe at settoplinux.org>
wrote:
>> This patch changes the default rom emulator to VM86 on IP1000 and RM4100
>> (it is much faster than x86emu or YABEL).
>>
>> Signed-off-by: Joesph Smith <joe at settoplinux.org>
> Acked-by: Myles Watson <mylesgw at gmail.com>
> 
Thanks r4245
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 06:47:10 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:47:10 -0400
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <241E1082E53F44ED80B815B31984BD48@chimp>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
	<c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>
	<241E1082E53F44ED80B815B31984BD48@chimp>
Message-ID: <3b26d2c23026132b873c8ec8ca7cdd7c@imap.1and1.com>




On Thu, 30 Apr 2009 22:38:22 -0600, "Myles Watson" <mylesgw at gmail.com>
wrote:
> 
> 
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Joseph Smith
>> Sent: Thursday, April 30, 2009 10:33 PM
>> To: coreboot
>> Subject: Re: [coreboot] [PATCH] i82801xx IRQ Fix Up
>>
>>
>>
>>
>> On Thu, 30 Apr 2009 21:32:55 -0400, Joseph Smith <joe at settoplinux.org>
>> wrote:
>> > This is a patch to use another IRQ besides IRQ12 to fix conflicts with
>> > i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It
> took
>> > me
>> > this long to catch this because I usually use a USB mouse.
>> >
>> > Signed-off-by: Joseph Smith <joe at settoplinux.org>
>> >
>> > --
>> This one too?
> I was going to look up IRQ 4 first.  I don't pretend to know too much
> about
> IRQs.
> 
It is shared with COM2, and doesn't seem to cause any conflicts.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 06:50:04 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:50:04 -0400
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <13426df10904302117w10a9ca33v692cad93940ac279@mail.gmail.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<13426df10904302117w10a9ca33v692cad93940ac279@mail.gmail.com>
Message-ID: <d3ae85aa2025462cb7f6068382d664e7@imap.1and1.com>




On Thu, 30 Apr 2009 21:17:26 -0700, ron minnich <rminnich at gmail.com> wrote:
> I don't know enough about boards that use this chip. But I do think
> you might want to at least check Myle's suggestion that there be a
> conditonal in the Config.lb.
> 
> OTOH, how many targets actively use this part (meaning are those
> boards in use today or ...)
> 
Just the IP1000 and RM4100 so far...
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri May  1 06:53:58 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 06:53:58 +0200
Subject: [coreboot] [v2] r4246 -
	trunk/coreboot-v2/src/southbridge/intel/i82801xx
Message-ID: <mailman.3140.1355071533.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-01 06:53:58 +0200 (Fri, 01 May 2009)
New Revision: 4246

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
Log:
This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 - PS/2 Mouse. 
Signed-off-by: Joseph Smith <joe at settoplinux.org> 
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-05-01 04:44:36 UTC (rev 4245)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-05-01 04:53:58 UTC (rev 4246)
@@ -58,14 +58,16 @@
  */
 
 #define PIRQA 0x03
-#define PIRQB 0x05
-#define PIRQC 0x06
-#define PIRQD 0x07
-#define PIRQE 0x09
-#define PIRQF 0x0A
-#define PIRQG 0x0B
-#define PIRQH 0x0C
+#define PIRQB 0x04
+#define PIRQC 0x05
+#define PIRQD 0x06
+#define PIRQE 0x07
+#define PIRQF 0x09
+#define PIRQG 0x0A
+#define PIRQH 0x0B
 
+/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+
 void i82801xx_enable_apic(struct device *dev)
 {
 	uint32_t reg32;




From joe at settoplinux.org  Fri May  1 06:55:22 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 00:55:22 -0400
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <2831fecf0904302145h1a38e4abla73e6e632320171a@mail.gmail.com>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
	<c06b1fa0f8ca234f9fd0b0a1bc3c84bf@imap.1and1.com>
	<241E1082E53F44ED80B815B31984BD48@chimp>
	<2831fecf0904302145h1a38e4abla73e6e632320171a@mail.gmail.com>
Message-ID: <80fd7d1685c240b0ebb4d589cb9a733f@imap.1and1.com>




On Thu, 30 Apr 2009 22:45:28 -0600, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Apr 30, 2009 at 10:38 PM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>>
>>> -----Original Message-----
>>> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org]
>>> On Behalf Of Joseph Smith
>>> Sent: Thursday, April 30, 2009 10:33 PM
>>> To: coreboot
>>> Subject: Re: [coreboot] [PATCH] i82801xx IRQ Fix Up
>>>
>>>
>>>
>>>
>>> On Thu, 30 Apr 2009 21:32:55 -0400, Joseph Smith <joe at settoplinux.org>
>>> wrote:
>>> > This is a patch to use another IRQ besides IRQ12 to fix conflicts
> with
>>> > i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It
> took
>>> > me
>>> > this long to catch this because I usually use a USB mouse.
>>> >
>>> > Signed-off-by: Joseph Smith <joe at settoplinux.org>
>>> >
>>> > --
>>> This one too?
>> I was going to look up IRQ 4 first. ?I don't pretend to know too much
> about
>> IRQs.
> Acked-by: Myles Watson <mylesgw at gmail.com>
> 
> From what I could tell it should be fine.
> 
Thanks again r4246

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From andrew.goodbody at tadpole.com  Fri May  1 09:37:54 2009
From: andrew.goodbody at tadpole.com (Andrew Goodbody)
Date: Fri, 01 May 2009 08:37:54 +0100
Subject: [coreboot] unexpected exception errors loading vga rom
In-Reply-To: <0baa932274e3090cd567092c608a843a@imap.1and1.com>
References: <833def118eec581027d3ad14707ae547@imap.1and1.com>	<13426df10904291636y5ba2eb3dvba3f151aaa60ddb@mail.gmail.com>	<f74e88d00bd9fe848ba95b21b53e99ec@imap.1and1.com>	<13426df10904292113p5b0260y873e665f121a6083@mail.gmail.com>	<b44eeb59ad0fe940fb215727ae6f8793@imap.1and1.com>	<13426df10904300755r19a6ca9cy93d37cb62c83ae23@mail.gmail.com>	<13426df10904301010s4af19a2bh3e45e3b8a2aaa913@mail.gmail.com>	<37dbdb96d1d380a6d8fc29ef01faafee@imap.1and1.com>	<13426df10904301334p1622d571u216754cc42f11635@mail.gmail.com>	<d81426ec15d6af5e49e3f98fcd0d5133@imap.1and1.com>	<13426df10904301455u216e7bddg116238291a7606b6@mail.gmail.com>	<fb4daee094f64fe6580d939b8fe00ecf@imap.1and1.com>
	<0baa932274e3090cd567092c608a843a@imap.1and1.com>
Message-ID: <49FAA6D2.6000500@tadpole.com>

Joseph Smith wrote:
> FYI, here is what the ICH4 data sheet says about these 0x3d registers.
> Looks like the PIRQ is internally specific.

The ICH4 is a southbridge and contains many different PCI devices and 
legacy devices including the PIC and the PIRQ routing hardware to map 
the PIRQs to PIC int lines. As such it is not a good place to try and 
draw inferences from as it has a lot of capabilities not included in a 
normal PCI device.

Andrew



From stepan at coresystems.de  Fri May  1 11:06:13 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 01 May 2009 11:06:13 +0200
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
Message-ID: <49FABB85.7060302@coresystems.de>

Awesome patch!

On 01.05.2009 0:22 Uhr, Myles Watson wrote:
>  	if (!eeprom_valid) {
>  		unsigned long mac_pos;
>  		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
> -		mac_l = readl(mac_pos) + nic_index;
> -		mac_h = readl(mac_pos + 4);
> +		mac_l = readl((uint8_t*)mac_pos) + nic_index;
> +		mac_h = readl((uint8_t*)mac_pos + 4);
>  	}
>   
One could put that slightly simpler as

 	if (!eeprom_valid) {
 		u8 *mac_pos;
 		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
		mac_l = readl(mac_pos) + nic_index;
		mac_h = readl(mac_pos + 4);
 	}

since mac_pos seems never used as unsigned long.

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From stepan at coresystems.de  Fri May  1 11:11:44 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 01 May 2009 11:11:44 +0200
Subject: [coreboot] SeaBIOS and hp dl145g3
In-Reply-To: <20090430234700.GA20152@morn.localdomain>
References: <bc122a250904290753i5749390fn7c9e25f572bcc11a@mail.gmail.com>	<20090430004304.GA7329@morn.localdomain>	<bc122a250904300807r6855facaube47b4ca8718c6af@mail.gmail.com>	<2831fecf0904300824o7b9b2d99pa111e144ff25d635@mail.gmail.com>
	<20090430234700.GA20152@morn.localdomain>
Message-ID: <49FABCD0.6080201@coresystems.de>

On 01.05.2009 1:47 Uhr, Kevin O'Connor wrote:
>> This forces SeaBIOS to see it as a PATA controller, but it's in SATA mode.
>>
>> Is there an easy way to add SATA support to SeaBIOS?  It sounds like a
>> bit of work.  It looks like you could force the device to be in PATA
>> mode, but once it's booted that's not ideal.
>>     
>
> SeaBIOS only supports PATA mode.  To the best of my knowledge, filo
> also only supports PATA mode drives (or SATA drives connected to a
> PATA compatible controller).
>   

If, with SATA mode you mean AHCI, you are right.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Fri May  1 11:15:41 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 01 May 2009 11:15:41 +0200
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
Message-ID: <49FABDBD.2020602@coresystems.de>

On 01.05.2009 3:32 Uhr, Joseph Smith wrote:
> This is a patch to use another IRQ besides IRQ12 to fix conflicts with
> i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took me
> this long to catch this because I usually use a USB mouse.
>   
Good spot!

> Index: src/southbridge/intel/i82801xx/i82801xx_lpc.c
> ===================================================================
> --- src/southbridge/intel/i82801xx/i82801xx_lpc.c	(revision 4240)
> +++ src/southbridge/intel/i82801xx/i82801xx_lpc.c	(working copy)
> @@ -58,14 +58,16 @@
>   */
>  
>  #define PIRQA 0x03
> -#define PIRQB 0x05
> -#define PIRQC 0x06
> -#define PIRQD 0x07
> -#define PIRQE 0x09
> -#define PIRQF 0x0A
> -#define PIRQG 0x0B
> -#define PIRQH 0x0C
> +#define PIRQB 0x04
> +#define PIRQC 0x05
> +#define PIRQD 0x06
> +#define PIRQE 0x07
> +#define PIRQF 0x09
> +#define PIRQG 0x0A
> +#define PIRQH 0x0B
>   


Hard coding these looks like it could work on one board and fail on
another. For the i82801gx I added these to the chip's config structure,
so they can be set in the device tree of the mainboard's config.lb.
Maybe that's what you want here, too?

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Fri May  1 11:22:24 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 01 May 2009 11:22:24 +0200
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
Message-ID: <49FABF50.8050209@coresystems.de>

On 01.05.2009 6:06 Uhr, Myles Watson wrote:
> On Thu, Apr 30, 2009 at 9:52 PM, Joseph Smith <joe at settoplinux.org> wrote:
>   
>> This patch allows a custom vga driver that will give the flexibility to run
>> code after vga is initialized for tv-out. It is one of many patches to
>> come, including code to manipulate the graphics mmio registers, enable the
>> graphics i2c data lines, and tv encoder drivers.
>>     
>
> Should it be conditionally included via a config option?  Are there
> other boards with the same chipset that won't want to use this TV-out
> initialization?
>   
Please, no more CONFIG flags.

- If it's a property of the board / northbridge, it should be a variable
in the chip's config structure

- there's no real code in that function, so there's not much sense to
make anything conditional yet.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Fri May  1 11:36:32 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 01 May 2009 11:36:32 +0200
Subject: [coreboot] [v2] r4245 - in
 trunk/coreboot-v2:	src/mainboard/rca/rm4100
 src/mainboard/thomson/ip1000	targets/rca/rm4100 targets/thomson/ip1000
Message-ID: <49FAC2A0.3010104@coresystems.de>

On 01.05.2009 6:44 Uhr, svn at coreboot.org wrote:
> Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
> ===================================================================
> --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01 04:37:13 UTC (rev 4244)
> +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01 04:44:36 UTC (rev 4245)
> @@ -24,6 +24,7 @@
>  uses CONFIG_CONSOLE_VGA
>  uses CONFIG_COMPRESSED_PAYLOAD_LZMA
>  uses CONFIG_IOAPIC
> +uses CONFIG_PCI_OPTION_ROM_RUN_VM86
>  uses CONFIG_PCI_ROM_RUN
>  uses CONFIG_ROM_PAYLOAD
>  uses CONFIG_ROM_PAYLOAD_START
> @@ -78,6 +79,7 @@
>  default HAVE_OPTION_TABLE = 0
>  default CONFIG_CONSOLE_VGA = 0
>  default CONFIG_PCI_ROM_RUN = 0
> +default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
>  default CONFIG_VIDEO_MB = 0
>  default STACK_SIZE = 0x2000
>  default HEAP_SIZE = 0x4000
>
> Modified: trunk/coreboot-v2/targets/rca/rm4100/Config.lb
> ===================================================================
> --- trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:37:13 UTC (rev 4244)
> +++ trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:44:36 UTC (rev 4245)
> @@ -37,6 +37,7 @@
>  ##
>  option CONFIG_CONSOLE_VGA = 1
>  option CONFIG_PCI_ROM_RUN = 1
> +option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
>  
>  ##
>  ## Choose the amount of memory pre-allocated for VGA
>
>   

Dumb question: Why are you setting CONFIG_PCI_OPTION_ROM_RUN_VM86 to 0
in the mainboard Options.lb file and to 1 in the target Config.lb?

This implies that VM86 should not_ be used by default. Is this the case?

It also means that you're abuild-testing the image with x86emu, but
using an image with VM86.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From c-d.hailfinger.devel.2006 at gmx.net  Fri May  1 12:51:06 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 May 2009 12:51:06 +0200
Subject: [coreboot] LinuxTag 2009 in Berlin, June 24-27
In-Reply-To: <20090429233345.9898.qmail@stuge.se>
References: <20090429221636.23865.qmail@stuge.se> <49F8D6CD.9070008@gmx.net>
	<20090429233345.9898.qmail@stuge.se>
Message-ID: <49FAD41A.8080801@gmx.net>

On 30.04.2009 01:33, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> Thanks for organizing this! I hope the interactions with LinuxTag
>> and Messe Berlin were less frustrating than last year.
>>     
>
> Zero frustration so far!
>   

Nice.


>> If everything goes well, I'll have external flasher support ready
>> in flashrom before LinuxTag. That would certainly be an interesting
>> way to exhibit flashrom.
>>     
>
> Yes indeed! Do you think you'll make it to Berlin this year to show
> it off yourself? :)
>   

I hope so, but my budget and university deadlines keep suggesting a
"no". No idea about the final decision yet.


> It would be great to have some external programmers there! And if
> there's a simple, proven design we might even be able to sell it
> cheap in the booth.
>   

Yes, that would be an awesome way to raise funds. Another possibility
would be to sell pre-modded M2A-VM. (Or my top hat flash for these
boards if that works out.)


> I have mentioned to the expo organizers that we could be interested
> in a booth (or sub-booth) for flashrom as well, but it depends on how
> much staff we can organize. If only a few people can help out at the
> expo I think it's better to stick with a single booth and dedicate a
> part of it to flashrom. (Will still make sure to mention flashrom to
> the expo organizers though, so that it gets it's own info in the
> printed expo material.)
>   

Actually, I'd prefer to have flashrom+coreboot at one single booth. That
way, nobody has to be sent to another booth if one question is too hard
for one of our staff.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Fri May  1 12:53:49 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 12:53:49 +0200
Subject: [coreboot] [flashrom] r447 - trunk
Message-ID: <mailman.3141.1355071533.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-01 12:53:49 +0200 (Fri, 01 May 2009)
New Revision: 447

Modified:
   trunk/flashrom.8
   trunk/flashrom.c
Log:
Since the command line interface for flashrom will change for 1.0
(all-caps or no-caps for short options, exclude range syntax, etc.) we
should tell users in the man page and the usage message about this.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8	2009-04-29 23:22:33 UTC (rev 446)
+++ trunk/flashrom.8	2009-05-01 10:53:49 UTC (rev 447)
@@ -17,6 +17,11 @@
 .B http://coreboot.org
 for details on coreboot)
 .SH OPTIONS
+Please note that the command line interface for flashrom will change before
+flashrom 1.0. Do not use flashrom in scripts or other automated tools without
+checking that your flashrom version won't interpret them in a totally different
+way.
+.PP
 If no file is specified, then all that happens
 is that flash info is dumped and the flash chip is set to writable.
 .TP

Modified: trunk/flashrom.c
===================================================================
--- trunk/flashrom.c	2009-04-29 23:22:33 UTC (rev 446)
+++ trunk/flashrom.c	2009-05-01 10:53:49 UTC (rev 447)
@@ -306,6 +306,10 @@
 	printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n",
 	       name);
 	printf("       [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file]\n");
+	printf("Please  note that the command line interface for flashrom will "
+		"change before flashrom 1.0. Do not use flashrom in scripts or "
+		"other automated tools without checking that your flashrom "
+		"version won't interpret them in a totally different way.\n\n");
 	printf
 	    ("   -r | --read:                      read flash and save into file\n"
 	     "   -w | --write:                     write file into flash\n"




From c-d.hailfinger.devel.2006 at gmx.net  Fri May  1 12:54:24 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 May 2009 12:54:24 +0200
Subject: [coreboot] [PATCH] flashrom: Tell users that the command	line
 interface may change
In-Reply-To: <20090428170049.GA16540@greenwood>
References: <49F5E0C6.4030009@gmx.net>
	<49F7048D.6070509@gmx.net>	<B75ED804674D47079C8D027F877774BF@chimp>	<20090428144446.17043.qmail@stuge.se>
	<49F7180B.3060800@gmx.net> <20090428170049.GA16540@greenwood>
Message-ID: <49FAD4E0.4080501@gmx.net>

On 28.04.2009 19:00, Uwe Hermann wrote:
> On Tue, Apr 28, 2009 at 04:51:55PM +0200, Carl-Daniel Hailfinger wrote:
>   
>>> Right, there is more state at:
>>> http://tracker.coreboot.org/trac/coreboot/ticket/100
>>>
>>> flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e.
>>>   
>>>       
>> Basically, finishing the interface (see also ticket 104) is one of the
>> things holding back flashrom 1.0, and instead of waiting another 6
>> months to get 1.0 done, I thought we'd simply release the current tree,
>>     
>
> Yep.
>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
>   

Thanks, r447.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Fri May  1 13:00:40 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 13:00:40 +0200
Subject: [coreboot] [flashrom] r448 - trunk
Message-ID: <mailman.3142.1355071533.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-01 13:00:39 +0200 (Fri, 01 May 2009)
New Revision: 448

Modified:
   trunk/flashrom.8
Log:
Add Li-Ta (Ollie) Lo to the author list.
He started flashrom back in 2000.

Thanks to Ron for pointing this out.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8	2009-05-01 10:53:49 UTC (rev 447)
+++ trunk/flashrom.8	2009-05-01 11:00:39 UTC (rev 448)
@@ -124,6 +124,8 @@
 .br
 Luc Verhaegen <libv at skynet.be>
 .br
+Li-Ta Lo
+.br
 Markus Boas <ryven at ryven.de>
 .br
 Nikolay Petukhov <nikolay.petukhov at gmail.com>




From joe at settoplinux.org  Fri May  1 13:26:41 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 07:26:41 -0400
Subject: [coreboot] LinuxTag 2009 in Berlin, June 24-27
In-Reply-To: <49FAD41A.8080801@gmx.net>
References: <20090429221636.23865.qmail@stuge.se> <49F8D6CD.9070008@gmx.net>
	<20090429233345.9898.qmail@stuge.se> <49FAD41A.8080801@gmx.net>
Message-ID: <43e8564ca75ab4d5acf81e17628df371@imap.1and1.com>


> (Or my top hat flash for these boards if that works out.)
> 
What is this?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 13:36:49 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 07:36:49 -0400
Subject: [coreboot] [PATCH] i82801xx IRQ Fix Up
In-Reply-To: <49FABDBD.2020602@coresystems.de>
References: <7efcac80f643a969993a9363075bf55c@imap.1and1.com>
	<49FABDBD.2020602@coresystems.de>
Message-ID: <9053c3846a4d15f00653d64a8ac2d27c@imap.1and1.com>




On Fri, 01 May 2009 11:15:41 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> On 01.05.2009 3:32 Uhr, Joseph Smith wrote:
>> This is a patch to use another IRQ besides IRQ12 to fix conflicts with
>> i8042 - PS/2 Mouse, most commonly assigned IRQ12 by the SuperIO. It took
> me
>> this long to catch this because I usually use a USB mouse.
>>
> Good spot!
> 
>> Index: src/southbridge/intel/i82801xx/i82801xx_lpc.c
>> ===================================================================
>> --- src/southbridge/intel/i82801xx/i82801xx_lpc.c	(revision 4240)
>> +++ src/southbridge/intel/i82801xx/i82801xx_lpc.c	(working copy)
>> @@ -58,14 +58,16 @@
>>   */
>>
>>  #define PIRQA 0x03
>> -#define PIRQB 0x05
>> -#define PIRQC 0x06
>> -#define PIRQD 0x07
>> -#define PIRQE 0x09
>> -#define PIRQF 0x0A
>> -#define PIRQG 0x0B
>> -#define PIRQH 0x0C
>> +#define PIRQB 0x04
>> +#define PIRQC 0x05
>> +#define PIRQD 0x06
>> +#define PIRQE 0x07
>> +#define PIRQF 0x09
>> +#define PIRQG 0x0A
>> +#define PIRQH 0x0B
>>
> 
> 
> Hard coding these looks like it could work on one board and fail on
> another. For the i82801gx I added these to the chip's config structure,
> so they can be set in the device tree of the mainboard's config.lb.
> Maybe that's what you want here, too?
> 
That's awsome. I never noticed that. Yes we really should setup all boards
like this and get rid of these defines in i82801xx_lpc.c. I never really
liked it. One question, where do you have the "pirqx_routing" defined? We
should really work on a patch for all mainboards that use i82801xx.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 13:40:16 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 07:40:16 -0400
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <49FABF50.8050209@coresystems.de>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
	<49FABF50.8050209@coresystems.de>
Message-ID: <698e9d70cb8cfc8886cf03c910bae0dd@imap.1and1.com>




On Fri, 01 May 2009 11:22:24 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> On 01.05.2009 6:06 Uhr, Myles Watson wrote:
>> On Thu, Apr 30, 2009 at 9:52 PM, Joseph Smith <joe at settoplinux.org>
> wrote:
>>
>>> This patch allows a custom vga driver that will give the flexibility to
> run
>>> code after vga is initialized for tv-out. It is one of many patches to
>>> come, including code to manipulate the graphics mmio registers, enable
> the
>>> graphics i2c data lines, and tv encoder drivers.
>>>
>>
>> Should it be conditionally included via a config option?  Are there
>> other boards with the same chipset that won't want to use this TV-out
>> initialization?
>>
> Please, no more CONFIG flags.
> 
> - If it's a property of the board / northbridge, it should be a variable
> in the chip's config structure
>
Ok that sound better.
> 
> - there's no real code in that function, so there's not much sense to
> make anything conditional yet.
> 
Right, it doesn't do anything extra yet, I am just setting the stage for
what is to come, because vga.c is going to be where all the code is called
from, kind of like a sub main() if you will.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri May  1 13:50:11 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 07:50:11 -0400
Subject: [coreboot]
 =?utf-8?q?=5Bv2=5D_r4245_-_in_trunk/coreboot-v2=3A=09s?=
 =?utf-8?q?rc/mainboard/rca/rm4100_src/mainboard/thomson/ip1000=09targets/?=
 =?utf-8?q?rca/rm4100_targets/thomson/ip1000?=
In-Reply-To: <49FAC2A0.3010104@coresystems.de>
References: <49FAC2A0.3010104@coresystems.de>
Message-ID: <a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com>




On Fri, 01 May 2009 11:36:32 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> On 01.05.2009 6:44 Uhr, svn at coreboot.org wrote:
>> Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
>> ===================================================================
>> --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01
> 04:37:13 UTC (rev 4244)
>> +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-05-01
> 04:44:36 UTC (rev 4245)
>> @@ -24,6 +24,7 @@
>>  uses CONFIG_CONSOLE_VGA
>>  uses CONFIG_COMPRESSED_PAYLOAD_LZMA
>>  uses CONFIG_IOAPIC
>> +uses CONFIG_PCI_OPTION_ROM_RUN_VM86
>>  uses CONFIG_PCI_ROM_RUN
>>  uses CONFIG_ROM_PAYLOAD
>>  uses CONFIG_ROM_PAYLOAD_START
>> @@ -78,6 +79,7 @@
>>  default HAVE_OPTION_TABLE = 0
>>  default CONFIG_CONSOLE_VGA = 0
>>  default CONFIG_PCI_ROM_RUN = 0
>> +default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
>>  default CONFIG_VIDEO_MB = 0
>>  default STACK_SIZE = 0x2000
>>  default HEAP_SIZE = 0x4000
>>
>> Modified: trunk/coreboot-v2/targets/rca/rm4100/Config.lb
>> ===================================================================
>> --- trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:37:13
> UTC (rev 4244)
>> +++ trunk/coreboot-v2/targets/rca/rm4100/Config.lb	2009-05-01 04:44:36
> UTC (rev 4245)
>> @@ -37,6 +37,7 @@
>>  ##
>>  option CONFIG_CONSOLE_VGA = 1
>>  option CONFIG_PCI_ROM_RUN = 1
>> +option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
>>  
>>  ##
>>  ## Choose the amount of memory pre-allocated for VGA
>>
>>   
> 
> Dumb question: Why are you setting CONFIG_PCI_OPTION_ROM_RUN_VM86 to 0
> in the mainboard Options.lb file and to 1 in the target Config.lb?
> 
> This implies that VM86 should not_ be used by default. Is this the case?
> 
> It also means that you're abuild-testing the image with x86emu, but
> using an image with VM86.
> 
Because, I have some people that use use these boxes in "headless mode" for
LAMP servers, Asterisk servers, etc. So I want to keep all the vga stuff
togethor and an "option" making their boot time as fast as possible. And I
think it was Ron that once said that most options should always be set in
targets Config.lb. Should I update the abuild Config.lb to reflect my
normal Config.lb?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri May  1 14:22:17 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 14:22:17 +0200
Subject: [coreboot] [flashrom] r449 - trunk
Message-ID: <mailman.3143.1355071533.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-01 14:22:17 +0200 (Fri, 01 May 2009)
New Revision: 449

Modified:
   trunk/flash.h
Log:
Some functions take no arguments. Make that explicit in the associated
prototypes.
This avoids a warning on some compilers and is a correctness issue.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/flash.h
===================================================================
--- trunk/flash.h	2009-05-01 11:00:39 UTC (rev 448)
+++ trunk/flash.h	2009-05-01 12:22:17 UTC (rev 449)
@@ -476,7 +476,7 @@
 
 /* udelay.c */
 void myusec_delay(int time);
-void myusec_calibrate_delay();
+void myusec_calibrate_delay(void);
 
 /* PCI handling for board/chipset_enable */
 struct pci_access *pacc;
@@ -538,8 +538,8 @@
 int probe_spi_res(struct flashchip *flash);
 int spi_command(unsigned int writecnt, unsigned int readcnt,
 		const unsigned char *writearr, unsigned char *readarr);
-int spi_write_enable();
-int spi_write_disable();
+int spi_write_enable(void);
+int spi_write_disable(void);
 int spi_chip_erase_60(struct flashchip *flash);
 int spi_chip_erase_c7(struct flashchip *flash);
 int spi_chip_erase_60_c7(struct flashchip *flash);
@@ -548,7 +548,7 @@
 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
 int spi_chip_write(struct flashchip *flash, uint8_t *buf);
 int spi_chip_read(struct flashchip *flash, uint8_t *buf);
-uint8_t spi_read_status_register();
+uint8_t spi_read_status_register(void);
 int spi_disable_blockprotect(void);
 void spi_byte_program(int address, uint8_t byte);
 int spi_nbyte_read(int address, uint8_t *bytes, int len);
@@ -570,7 +570,7 @@
 int write_en29f002a(struct flashchip *flash, uint8_t *buf);
 
 /* ichspi.c */
-int ich_init_opcodes();
+int ich_init_opcodes(void);
 int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
 		    const unsigned char *writearr, unsigned char *readarr);
 int ich_spi_read(struct flashchip *flash, uint8_t * buf);




From c-d.hailfinger.devel.2006 at gmx.net  Fri May  1 14:49:51 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 May 2009 14:49:51 +0200
Subject: [coreboot] [PATCH] flashrom portability fixes and docs
Message-ID: <49FAEFEF.8040300@gmx.net>

Fix compilation on Solaris and tell people how to compile flashrom on
Solaris, Darwin/Mac OS X and DragonFly BSD.

Thanks to Joerg Schilling and Patrick Georgi for the Solaris part.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-portability/flash.h
===================================================================
--- flashrom-portability/flash.h	(Revision 449)
+++ flashrom-portability/flash.h	(Arbeitskopie)
@@ -30,6 +30,14 @@
 #include <stdint.h>
 #include <stdio.h>
 
+/* for iopl and outb under Solaris */
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#include <strings.h>
+#include <sys/sysi86.h>
+#include <sys/psw.h>
+#include <asm/sunddi.h>
+#endif
+
 #if (defined(__MACH__) && defined(__APPLE__))
 #define __DARWIN__
 #endif
@@ -50,6 +58,15 @@
     #define off64_t off_t
     #define lseek64 lseek
 #endif
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+  /* Note different order for outb */
+  #define OUTB(x,y) outb(y, x)
+  #define OUTW(x,y) outw(y, x)
+  #define OUTL(x,y) outl(y, x)
+  #define INB  inb
+  #define INW  inw
+  #define INL  inl
+#else
   #define OUTB outb
   #define OUTW outw
   #define OUTL outl
@@ -57,6 +74,7 @@
   #define INW  inw
   #define INL  inl
 #endif
+#endif
 
 static inline void chip_writeb(uint8_t b, volatile void *addr)
 {
Index: flashrom-portability/flashrom.c
===================================================================
--- flashrom-portability/flashrom.c	(Revision 449)
+++ flashrom-portability/flashrom.c	(Arbeitskopie)
@@ -30,13 +30,6 @@
 #include <stdlib.h>
 #include <getopt.h>
 #include <pci/pci.h>
-/* for iopl */
-#if defined (__sun) && (defined(__i386) || defined(__amd64))
-#include <strings.h>
-#include <sys/sysi86.h>
-#include <sys/psw.h>
-#include <asm/sunddi.h>
-#endif
 #include "flash.h"
 
 char *chip_to_probe = NULL;
Index: flashrom-portability/README
===================================================================
--- flashrom-portability/README	(Revision 449)
+++ flashrom-portability/README	(Arbeitskopie)
@@ -21,7 +21,18 @@
 * pciutils-devel / pciutils-dev / libpci-dev
 * zlib-devel / zlib1g-dev
 
+To compile on Solaris, use the commands below:
+gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2
 
+To compile on DragonFly BSD, use the commands below:
+ln -s /usr/pkg/include/pciutils pci
+gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
+
+To compile and run on Darwin/Mac OS X:
+Install DirectIO from coresystems GmbH.
+DirectIO is available at http://www.coresystems.de/en/directio
+
+
 Usage / Options
 ---------------
 


-- 
http://www.hailfinger.org/

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From mylesgw at gmail.com  Fri May  1 15:02:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 May 2009 07:02:54 -0600
Subject: [coreboot] [PATCH] Remove warnings for s2892
In-Reply-To: <49FABB85.7060302@coresystems.de>
References: <2831fecf0904301522j2285e36aud6b41ab61c416b31@mail.gmail.com>
	<49FABB85.7060302@coresystems.de>
Message-ID: <E9E8B47E119E418C89369C176C680C36@chimp>



> -----Original Message-----
> From: Stefan Reinauer [mailto:stepan at coresystems.de]
> Sent: Friday, May 01, 2009 3:06 AM
> To: Myles Watson
> Cc: coreboot
> Subject: Re: [coreboot] [PATCH] Remove warnings for s2892
> 
> Awesome patch!

Thanks.

> On 01.05.2009 0:22 Uhr, Myles Watson wrote:
> >  	if (!eeprom_valid) {
> >  		unsigned long mac_pos;
> >  		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds.
*/
> > -		mac_l = readl(mac_pos) + nic_index;
> > -		mac_h = readl(mac_pos + 4);
> > +		mac_l = readl((uint8_t*)mac_pos) + nic_index;
> > +		mac_h = readl((uint8_t*)mac_pos + 4);
> >  	}
> >
> One could put that slightly simpler as
> 
>  	if (!eeprom_valid) {
>  		u8 *mac_pos;
>  		mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds.
*/
I think you still need a cast, but it is nicer than two casts.
  		mac_pos = (u8*) 0xffffffd0; /* See romstrap.inc and
romstrap.lds. */

> 		mac_l = readl(mac_pos) + nic_index;
> 		mac_h = readl(mac_pos + 4);
>  	}

I wasn't sure if we wanted to convert types from uint8_t to u8 in old files,
so I didn't do any of that.

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles




From svn at coreboot.org  Fri May  1 16:33:19 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 16:33:19 +0200
Subject: [coreboot] [v2] r4247 -
	trunk/coreboot-v2/src/northbridge/intel/i82830
Message-ID: <mailman.3144.1355071533.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-01 16:33:19 +0200 (Fri, 01 May 2009)
New Revision: 4247

Modified:
   trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
Log:
Trivial removal of svn:executable property from vga.c.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>



Property changes on: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
___________________________________________________________________
Deleted: svn:executable
   - *




From peter at stuge.se  Fri May  1 16:34:06 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 May 2009 16:34:06 +0200
Subject: [coreboot] [v2] r4244
	-	trunk/coreboot-v2/src/northbridge/intel/i82830
Message-ID: <20090501143406.1152.qmail@stuge.se>

svn at coreboot.org wrote:
> Property changes on: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
> ___________________________________________________________________
> Added: svn:executable
>    + *

Please watch out with the executable property when adding files. I
just removed it in r4247.


//Peter



From svn at coreboot.org  Fri May  1 16:49:49 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 16:49:49 +0200
Subject: [coreboot] [flashrom] r450 - trunk
Message-ID: <mailman.3145.1355071533.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-01 16:49:49 +0200 (Fri, 01 May 2009)
New Revision: 450

Modified:
   trunk/flashrom.8
Log:
Fix usage to show that vendor: is optional in the -m parameter.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8	2009-05-01 12:22:17 UTC (rev 449)
+++ trunk/flashrom.8	2009-05-01 14:49:49 UTC (rev 450)
@@ -3,7 +3,7 @@
 flashrom \- read, write, and erase BIOS/ROM/flash chips
 .SH SYNOPSIS
 .B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
-         [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
+         [\fB-m\fR [vendor:]part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
 .SH DESCRIPTION
 .B flashrom
 is a utility for reading, writing, and erasing flash ROM chips.




From svn at coreboot.org  Fri May  1 16:52:51 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 16:52:51 +0200
Subject: [coreboot] [flashrom] r451 - trunk
Message-ID: <mailman.3146.1355071533.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-01 16:52:50 +0200 (Fri, 01 May 2009)
New Revision: 451

Modified:
   trunk/README
   trunk/flashrom.8
Log:
Mention that flashrom can also verify flash contents.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/README
===================================================================
--- trunk/README	2009-05-01 14:49:49 UTC (rev 450)
+++ trunk/README	2009-05-01 14:52:50 UTC (rev 451)
@@ -2,8 +2,8 @@
 flashrom README
 -------------------------------------------------------------------------------
 
-flashrom is a utility for reading, writing, and erasing flash ROM chips.
-It's often used to flash BIOS/coreboot/firmware images.
+flashrom is a utility for reading, writing, verifying and erasing flash ROM
+chips.  It's often used to flash BIOS/coreboot/firmware images.
 
 It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
 TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,

Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8	2009-05-01 14:49:49 UTC (rev 450)
+++ trunk/flashrom.8	2009-05-01 14:52:50 UTC (rev 451)
@@ -1,12 +1,12 @@
 .TH FLASHROM 8 "April 11, 2009"
 .SH NAME
-flashrom \- read, write, and erase BIOS/ROM/flash chips
+flashrom \- read, write, verify and erase BIOS/ROM/flash chips
 .SH SYNOPSIS
 .B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
          [\fB-m\fR [vendor:]part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
 .SH DESCRIPTION
 .B flashrom
-is a utility for reading, writing, and erasing flash ROM chips.
+is a utility for reading, writing, verifying and erasing flash ROM chips.
 It's often used to flash BIOS/coreboot/firmware images.
 .PP
 It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and




From peter at stuge.se  Fri May  1 16:57:17 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 1 May 2009 16:57:17 +0200
Subject: [coreboot] [PATCH] flashrom portability fixes and docs
In-Reply-To: <49FAEFEF.8040300@gmx.net>
References: <49FAEFEF.8040300@gmx.net>
Message-ID: <20090501145717.12341.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> Fix compilation on Solaris and tell people how to compile flashrom on
> Solaris, Darwin/Mac OS X and DragonFly BSD.
> 
> Thanks to Joerg Schilling and Patrick Georgi for the Solaris part.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Acked-by: Peter Stuge <peter at stuge.se>



From joe at settoplinux.org  Fri May  1 17:04:51 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 11:04:51 -0400
Subject: [coreboot]
 =?utf-8?q?=5Bv2=5D_r4244_-=09trunk/coreboot-v2/src/nor?=
 =?utf-8?q?thbridge/intel/i82830?=
In-Reply-To: <20090501143406.1152.qmail@stuge.se>
References: <20090501143406.1152.qmail@stuge.se>
Message-ID: <44d8bd2697b1626d4077491f6f69abb9@imap.1and1.com>




On Fri, 1 May 2009 16:34:06 +0200, Peter Stuge <peter at stuge.se> wrote:
> svn at coreboot.org wrote:
>> Property changes on:
> trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
>> ___________________________________________________________________
>> Added: svn:executable
>>    + *
> 
> Please watch out with the executable property when adding files. I
> just removed it in r4247.
> 
> 
Oops, thanks Peter.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From rminnich at gmail.com  Fri May  1 18:04:44 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 May 2009 09:04:44 -0700
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
	src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000
	targets/rca/rm4100 targets/thomson/ip1000
In-Reply-To: <a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com>
References: <49FAC2A0.3010104@coresystems.de>
	<a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com>
Message-ID: <13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>

On Fri, May 1, 2009 at 4:50 AM, Joseph Smith <joe at settoplinux.org> wrote:

> Because, I have some people that use use these boxes in "headless mode" for
> LAMP servers, Asterisk servers, etc. So I want to keep all the vga stuff
> togethor and an "option" making their boot time as fast as possible. And I
> think it was Ron that once said that most options should always be set in
> targets Config.lb. Should I update the abuild Config.lb to reflect my
> normal Config.lb?

What's the normal usage?

If the most common usage is the headless stuff then it should default 0.

This is always a judgement call. One thing to note: if if has been 0,
and you change it 1, you are going to have to tell any users of
headless that they need to make  new target with this set to 0.

How will the unconditional inclusion of the vga.o (from the other
thread) affect headless users? It still seems to me that it would be
easy to say
if CONFIG_CONSOLE_VGA
        object vga.o
end

to cover that case.

ron



From rminnich at gmail.com  Fri May  1 18:06:13 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 May 2009 09:06:13 -0700
Subject: [coreboot] [PATCH]i82830 custom vga driver
In-Reply-To: <2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
References: <1791d65900592ed8f9f7b1abfe1dfef2@imap.1and1.com>
	<2831fecf0904302106m38076267t3af6b1df9c5dac0@mail.gmail.com>
Message-ID: <13426df10905010906u11368edajd19ad9e2090ed9df@mail.gmail.com>

What's the problem with doing this?

if CONFIG_CONSOLE_VGA
        driver vga.o
end



From svn at coreboot.org  Fri May  1 18:34:32 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  1 May 2009 18:34:32 +0200
Subject: [coreboot] [flashrom] r452 - trunk
Message-ID: <mailman.3147.1355071533.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-01 18:34:32 +0200 (Fri, 01 May 2009)
New Revision: 452

Modified:
   trunk/README
   trunk/flash.h
   trunk/flashrom.c
Log:
Fix compilation on Solaris and tell people how to compile flashrom on
Solaris, Darwin/Mac OS X and DragonFly BSD.

Thanks to Joerg Schilling and Patrick Georgi for the Solaris part.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/README
===================================================================
--- trunk/README	2009-05-01 14:52:50 UTC (rev 451)
+++ trunk/README	2009-05-01 16:34:32 UTC (rev 452)
@@ -21,7 +21,18 @@
 * pciutils-devel / pciutils-dev / libpci-dev
 * zlib-devel / zlib1g-dev
 
+To compile on Solaris, use the commands below:
+gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2
 
+To compile on DragonFly BSD, use the commands below:
+ln -s /usr/pkg/include/pciutils pci
+gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
+
+To compile and run on Darwin/Mac OS X:
+Install DirectIO from coresystems GmbH.
+DirectIO is available at http://www.coresystems.de/en/directio
+
+
 Usage / Options
 ---------------
 

Modified: trunk/flash.h
===================================================================
--- trunk/flash.h	2009-05-01 14:52:50 UTC (rev 451)
+++ trunk/flash.h	2009-05-01 16:34:32 UTC (rev 452)
@@ -30,6 +30,14 @@
 #include <stdint.h>
 #include <stdio.h>
 
+/* for iopl and outb under Solaris */
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+#include <strings.h>
+#include <sys/sysi86.h>
+#include <sys/psw.h>
+#include <asm/sunddi.h>
+#endif
+
 #if (defined(__MACH__) && defined(__APPLE__))
 #define __DARWIN__
 #endif
@@ -50,6 +58,15 @@
     #define off64_t off_t
     #define lseek64 lseek
 #endif
+#if defined (__sun) && (defined(__i386) || defined(__amd64))
+  /* Note different order for outb */
+  #define OUTB(x,y) outb(y, x)
+  #define OUTW(x,y) outw(y, x)
+  #define OUTL(x,y) outl(y, x)
+  #define INB  inb
+  #define INW  inw
+  #define INL  inl
+#else
   #define OUTB outb
   #define OUTW outw
   #define OUTL outl
@@ -57,6 +74,7 @@
   #define INW  inw
   #define INL  inl
 #endif
+#endif
 
 static inline void chip_writeb(uint8_t b, volatile void *addr)
 {

Modified: trunk/flashrom.c
===================================================================
--- trunk/flashrom.c	2009-05-01 14:52:50 UTC (rev 451)
+++ trunk/flashrom.c	2009-05-01 16:34:32 UTC (rev 452)
@@ -30,13 +30,6 @@
 #include <stdlib.h>
 #include <getopt.h>
 #include <pci/pci.h>
-/* for iopl */
-#if defined (__sun) && (defined(__i386) || defined(__amd64))
-#include <strings.h>
-#include <sys/sysi86.h>
-#include <sys/psw.h>
-#include <asm/sunddi.h>
-#endif
 #include "flash.h"
 
 char *chip_to_probe = NULL;




From c-d.hailfinger.devel.2006 at gmx.net  Fri May  1 18:40:10 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 01 May 2009 18:40:10 +0200
Subject: [coreboot] [PATCH] flashrom portability fixes and docs
In-Reply-To: <20090501145717.12341.qmail@stuge.se>
References: <49FAEFEF.8040300@gmx.net> <20090501145717.12341.qmail@stuge.se>
Message-ID: <49FB25EA.9090304@gmx.net>

On 01.05.2009 16:57, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> Fix compilation on Solaris and tell people how to compile flashrom on
>> Solaris, Darwin/Mac OS X and DragonFly BSD.
>>
>> Thanks to Joerg Schilling and Patrick Georgi for the Solaris part.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks, committed in r452.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Fri May  1 19:27:40 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 01 May 2009 13:27:40 -0400
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
 src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/rca/rm4100
 targets/thomson/ip1000
In-Reply-To: <13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>
References: <49FAC2A0.3010104@coresystems.de>
	<a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com>
	<13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>
Message-ID: <625cc333a7931f58afda1b884c051eeb@imap.1and1.com>




On Fri, 1 May 2009 09:04:44 -0700, ron minnich <rminnich at gmail.com> wrote:
> On Fri, May 1, 2009 at 4:50 AM, Joseph Smith <joe at settoplinux.org> wrote:
> 
>> Because, I have some people that use use these boxes in "headless mode"
> for
>> LAMP servers, Asterisk servers, etc. So I want to keep all the vga stuff
>> togethor and an "option" making their boot time as fast as possible. And
> I
>> think it was Ron that once said that most options should always be set
> in
>> targets Config.lb. Should I update the abuild Config.lb to reflect my
>> normal Config.lb?
> 
> What's the normal usage?
> 
A set-top-box of course! The problem with that is it doesn't have a VGA
connector, only tv-out. So unless you are soldering crafty and can solder
on a vga connector, you are limited to serial console or ssh. But, very
soon the tv-out will be working and set-top-box all the way :-)

> If the most common usage is the headless stuff then it should default 0.
> 
> This is always a judgement call. One thing to note: if if has been 0,
> and you change it 1, you are going to have to tell any users of
> headless that they need to make  new target with this set to 0.
> 
Right.
>
> How will the unconditional inclusion of the vga.o (from the other
> thread) affect headless users? It still seems to me that it would be
> easy to say
> if CONFIG_CONSOLE_VGA
>         object vga.o
> end
> 
Hmm, interesting.
I was also thinking about making it a little more user friendly by wrapping
all the vga options into one. Something like in mainboard Options.lb:

#ifdef VGA_ENABLE /* or some other global define */
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1
default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
default CONFIG_VIDEO_MB = 8
#else
default CONFIG_CONSOLE_VGA = 0
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
default CONFIG_VIDEO_MB = 0
#endif

An then all the user would have to do in targets Config.lb is:

## Enable VGA off=0(default) On=1
option VGA_ENABLE = 1

Would that work?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mylesgw at gmail.com  Fri May  1 22:14:37 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 1 May 2009 14:14:37 -0600
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
	src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000
	targets/rca/rm4100 targets/thomson/ip1000
In-Reply-To: <625cc333a7931f58afda1b884c051eeb@imap.1and1.com>
References: <49FAC2A0.3010104@coresystems.de><a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com><13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>
	<625cc333a7931f58afda1b884c051eeb@imap.1and1.com>
Message-ID: <EF7B7254BE234A9DADB3462F78BB94EE@chimp>


> > How will the unconditional inclusion of the vga.o (from the other
> > thread) affect headless users? It still seems to me that it would be
> > easy to say
> > if CONFIG_CONSOLE_VGA
> >         object vga.o
> > end
> >
> Hmm, interesting.
> I was also thinking about making it a little more user friendly by
> wrapping
> all the vga options into one. Something like in mainboard Options.lb:

You have to be careful with #ifdef because our options are always defined.
You probably meant #if VGA == 1.
 
> #ifdef VGA_ENABLE /* or some other global define */
> default CONFIG_CONSOLE_VGA = 1
> default CONFIG_PCI_ROM_RUN = 1
> default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
> default CONFIG_VIDEO_MB = 8
> #else
> default CONFIG_CONSOLE_VGA = 0
> default CONFIG_PCI_ROM_RUN = 0
> default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
> default CONFIG_VIDEO_MB = 0
> #endif

I would think it would be easier to do something like:

default CONFIG_PCI_ROM_RUN = CONFIG_CONSOLE_VGA
default CONFIG_PCI_OPTION_ROM_RUN_VM86 = CONFIG_CONSOLE_VGA
default CONFIG_VIDEO_MB = CONFIG_CONSOLE_VGA * 8 /* A little hackish. */
 
> An then all the user would have to do in targets Config.lb is:
> 
> ## Enable VGA off=0(default) On=1
> option VGA_ENABLE = 1

option CONFIG_CONSOLE_VGA = 1

Thanks,
Myles




From rminnich at gmail.com  Fri May  1 22:50:44 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 1 May 2009 13:50:44 -0700
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
	src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000
	targets/rca/rm4100 targets/thomson/ip1000
In-Reply-To: <EF7B7254BE234A9DADB3462F78BB94EE@chimp>
References: <49FAC2A0.3010104@coresystems.de>
	<a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com>
	<13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>
	<625cc333a7931f58afda1b884c051eeb@imap.1and1.com>
	<EF7B7254BE234A9DADB3462F78BB94EE@chimp>
Message-ID: <13426df10905011350w65aa58d4v2cb38bd7f672eaa4@mail.gmail.com>

On Fri, May 1, 2009 at 1:14 PM, Myles Watson <mylesgw at gmail.com> wrote:

> option CONFIG_CONSOLE_VGA = 1

Yes, I think Myles has the right idea. That CONFIG_CONSOLE_VGA is
there for a reason.

ron



From ebiederm at xmission.com  Fri May  1 22:56:20 2009
From: ebiederm at xmission.com (Eric W. Biederman)
Date: Fri, 01 May 2009 13:56:20 -0700
Subject: [coreboot] [PATCH]More consistent behaviour for printk_*
In-Reply-To: <49F61909.4050802@coresystems.de> (Stefan Reinauer's message of
	"Mon\, 27 Apr 2009 22\:43\:53 +0200")
References: <200904271948.58785.patrick@georgi-clan.de>
	<47AE7833850C412E8522A579FD59722F@chimp>
	<49F61909.4050802@coresystems.de>
Message-ID: <m14ow4wnij.fsf@fess.ebiederm.org>

Stefan Reinauer <stepan at coresystems.de> writes:

> On 27.04.2009 20:16 Uhr, Myles Watson wrote:
>
>
>         section, but then a lot of strings that never surface would be compiled in
>         (and I doubt the compiler is clever enough to figure that out)
>
>
>     We discussed this recently for v3.  Do you have a good idea of how much
>     space this actually saves?
>
>
>
> It's hardly a few kilobytes. But this is no good way of saving space, by
> trimming user messages and introducing side effects.

When this was introduced.  It was the difference between code that met the
size targets and code that doesn't.  Largely because we have so many messages
at the spew level that really are not intended for users to see just developers.

Eric



From ward at gnu.org  Fri May  1 23:15:03 2009
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 1 May 2009 17:15:03 -0400
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
Message-ID: <20090501211503.GA18155@localdomain>

Hi all, 

It seems r4233/4234 broke the tree for h8dme (k8). Here's how my boot hangs,
note the corruption in the serial log:

----------------------------------
....
set DQS timing:RcvrEn:Pass2: 00
 done
Total DQS Training : tsc [00]=000000007acb45c5
Total DQS Training : tsc [01]=000000007c957514
Total DQS Training : tsc [02]=00000000f820fd23
Total DQS Training : tsc [03]=00000000fab0b966
Ram4
v_esp=000cefec
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
src=fffdf000
sdsrtc==00100f0f0f0f80
eU7ncom
pdrsets=s0i0n0gc 8i0m0a0ge
tUon cRoAmMp.res
sing image to RAM.
image length = 00028560
Jumping to image.
coreboot-2.0.0-r4234M_h8dme_Fallback Fri May  1 17:07:03 EDT 2009 booting...
Enumerating buses...
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
malloc Enter, size 1100, free_memi_mpatgre  0l0e1n4g8t0h0 0=
0m0a0l0l2oac6 c001
4J8u0m0p0in
gC PtUo:  iAmPaIgCe:. 01
----------------------------------

Full log available at
http://ward.vandewege.net/coreboot/h8dme/r4234-corruption.log

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From r.marek at assembler.cz  Fri May  1 23:42:17 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 01 May 2009 23:42:17 +0200
Subject: [coreboot] [PATCH] Free VGA BIOS for K8M890
In-Reply-To: <20090426031036.GB21580@skynet.be>
References: <49F317A5.4080401@assembler.cz>	<13426df10904250925v44370982xc92c9fe408319c2c@mail.gmail.com>
	<20090426031036.GB21580@skynet.be>
Message-ID: <49FB6CB9.2000008@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi again,

I'm attaching a rewritten version from VGA ROM, which mimics the BIOS init.

Sadly enough it is still not hitting the all required regs to make powernow
working as it is with orig bios.

The rest register spill is the captured IO as it was. The top of the file is
what bios is doing during the init. Just before it calls ax=0003 and exits the rom.

There is also one interresting place:

<------>write_cr((read_cr(0x36) & ~0x30) | (0x3 << 4), 0x36);
<------>write_cr((read_cr(0x30) & ~0x4), 0x30);

<------>/* just read, hope compiler won't optimize that out */
<------>tmp = inb(0x3da);
<------>tmp = inb(0x3ba);

<------>outb(0x0, 0x3c0);


/* original bios has it but if I compile it in I get blank screen */
//<---->tmp = inb(0x3da);
<------>tmp = inb(0x3ba);

The bios is doing it exactly like this. But if I enable the inb(0x3da) I get no
picture but monitors seems to have some signal. It works fine without those
inbs. Any idea what is doing the code?

Rudolf


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JvYAn2AsPg7iQM1WpV/tISD+3OU3rDiF
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From ward at gnu.org  Fri May  1 23:45:51 2009
From: ward at gnu.org (Ward Vandewege)
Date: Fri, 1 May 2009 17:45:51 -0400
Subject: [coreboot] SeaBIOS, serial output, and grub
In-Reply-To: <20090501023931.GA28467@morn.localdomain>
References: <20090429191023.GA8963@localdomain>
	<20090430020822.GA8144@morn.localdomain>
	<20090430030432.GA31307@localdomain>
	<20090501010059.GA20735@morn.localdomain>
	<20090501011845.GA15113@localdomain>
	<20090501022656.GC20735@morn.localdomain>
	<20090501023931.GA28467@morn.localdomain>
Message-ID: <20090501214551.GB18155@localdomain>

On Thu, Apr 30, 2009 at 10:39:31PM -0400, Kevin O'Connor wrote:
> On Thu, Apr 30, 2009 at 10:26:56PM -0400, Kevin O'Connor wrote:
> > What's really odd, is that if I have sgabios on, then grub does work
> > okay.  I didn't catch this last night because I was also playing with
> > sgabios at the same time.  As a guess, sgabios is reinitializing the
> > serial port back to a way grub is okay with.  This may be specific to
> > qemu, but it's something to look into.
> 
> Oops - if qemu/coreboot/seabios/sgabios/grub, then sgabios forwards
> the grub screen over serial - grub itself still wont talk to the
> serial directly.  (If I run qemu/seabios/sgabios/grub then I get two
> copies of the grub messages - one from grub serial and one from grub
> screen via sgabios.)

Hmm. I'm not seeing that on h8dme. This is my cbfs:

./cbfstool ./coreboot.rom print
coreboot.rom: 1024 kB, bootblocksize 266240, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
normal/payload                 0x0        payload      65635
fallback/payload               0x10090    payload      65635
pci1002,515e.rom               0x20130    0x00000000   45056
genroms/sgabios.rom            0x2b170    0x00000000   3169
pci10de,0373.rom               0x2be10    0x00000000   57344

I've got a vga rom and gpxe in there, in addition to sgabios.

Here's a boot log (seabios head, coreboot r4232 + Myles' serial patch from
4241):

  http://ward.vandewege.net/coreboot/h8dme/seabios20090501-sgabios-gpxe-grub-serial-fails.log

And here's one without gpxe in the cbfs:

  http://ward.vandewege.net/coreboot/h8dme/seabios20090501-sgabios-grub-serial-fails.log

Basically, grub's super slow, trying to write to serial, but as you can see
no grub output ever appears there. Sometimes grub actually displays its menu
on the vga console after the 'press any key to continue' lines (if I bang
enough keys, it seems), but most of the time it just does the default, which
is (nonfunctioning) serial.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From stepan at coresystems.de  Sat May  2 01:14:36 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 02 May 2009 01:14:36 +0200
Subject: [coreboot] [v2] r4245 - in trunk/coreboot-v2:
 src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/rca/rm4100
 targets/thomson/ip1000
In-Reply-To: <EF7B7254BE234A9DADB3462F78BB94EE@chimp>
References: <49FAC2A0.3010104@coresystems.de><a809a6aa1cb133fece9f79e859a25bc6@imap.1and1.com><13426df10905010904t26028594v9405bb3836aa6cfb@mail.gmail.com>
	<625cc333a7931f58afda1b884c051eeb@imap.1and1.com>
	<EF7B7254BE234A9DADB3462F78BB94EE@chimp>
Message-ID: <49FB825C.5050101@coresystems.de>

Myles Watson wrote:
>>> How will the unconditional inclusion of the vga.o (from the other
>>> thread) affect headless users? It still seems to me that it would be
>>> easy to say
>>> if CONFIG_CONSOLE_VGA
>>>         object vga.o
>>> end
>>>
>>>       
>> Hmm, interesting.
>> I was also thinking about making it a little more user friendly by
>> wrapping
>> all the vga options into one. Something like in mainboard Options.lb:
>>     
>
> You have to be careful with #ifdef because our options are always defined.
> You probably meant #if VGA == 1.
>  
>   
>> #ifdef VGA_ENABLE /* or some other global define */
>> default CONFIG_CONSOLE_VGA = 1
>> default CONFIG_PCI_ROM_RUN = 1
>> default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1
>> default CONFIG_VIDEO_MB = 8
>> #else
>> default CONFIG_CONSOLE_VGA = 0
>> default CONFIG_PCI_ROM_RUN = 0
>> default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0
>> default CONFIG_VIDEO_MB = 0
>> #endif
>>     
>
> I would think it would be easier to do something like:
>
> default CONFIG_PCI_ROM_RUN = CONFIG_CONSOLE_VGA
> default CONFIG_PCI_OPTION_ROM_RUN_VM86 = CONFIG_CONSOLE_VGA
> default CONFIG_VIDEO_MB = CONFIG_CONSOLE_VGA * 8 /* A little hackish. */ 
Normally, with coreboot and VGA initialization, you don't want 
CONFIG_CONSOLE_VGA, as that's just the last few boot messages of table 
creation. It's not really good for debugging anymore. In v3 we were 
smart and deleted CONFIG_CONSOLE_VGA completely, leaving any VGA 
_output_ to the payloads.

I think we should do the same thing in v2.






From svn at coreboot.org  Sat May  2 02:50:58 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 May 2009 02:50:58 +0200
Subject: [coreboot] [v2] r4248 - in trunk/coreboot-v2/src/mainboard:
	rca/rm4100 thomson/ip1000
Message-ID: <mailman.3148.1355071533.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-02 02:50:58 +0200 (Sat, 02 May 2009)
New Revision: 4248

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
Log:
Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something. 
Signed-off-by: Joseph Smith <joe at settoplinux.org> 
Acked-by: Joseph Smith <joe at settoplinux.org>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c	2009-05-01 14:33:19 UTC (rev 4247)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c	2009-05-02 00:50:58 UTC (rev 4248)
@@ -1,120 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	device_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
-	/* Set GPIO25 to input and drive GPIO23 to high,
-	 * this enables the LAN controller. 
-	 */
-	udelay(10);
-	set_gpio = 0x0000ffff;
-	set_gpio |= 1 << 25;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
-
-	set_gpio = 0x1b3f0000;
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	outb(0x55, port);		/* Enter the configuration state. */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-	outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
-	outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
-	outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
-	outl(0x00, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
-	outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
-	outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x35); /* GP32 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x36); /* GP33 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
-	outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
-	outl(0x07, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
-	outb(0xaa, port);		/* Exit the configuration state. */
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define PME_DEV			PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
+#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+	device_t dev;
+	uint16_t port;
+	uint32_t set_gpio;
+
+	/* Southbridge GPIOs. */
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+	/* Set GPIO23 to high, this enables the LAN controller. */
+	udelay(10);
+	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+	set_gpio |= 1 << 23;
+	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+	/* Super I/O GPIOs. */
+	dev = PME_DEV;
+	port = dev >> 8;
+
+	/* Enter the configuration state. */
+	outb(0x55, port);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+	pnp_set_enable(dev, 1);
+
+	/* GP21 - LED_RED */
+	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+	/* GP30 - FAN2_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
+
+	/* GP31 - FAN1_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+	/* GP32 - FAN2_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
+
+	/* GP33 - FAN1_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+	/* GP34 - AUD_MUTE_OUT_R */
+	outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+	/* GP36 - KBRST */
+	outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+	/* GP37 - A20GATE */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+	/* GP42 - GPIO_PME_OUT */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
+
+	/* GP50 - SER2_RI */
+	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+	/* GP51 - SER2_DCD */
+	outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+	/* GP52 - SER2_RX */
+	outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+	/* GP53 - SER2_TX */
+	outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+	/* GP55 - SER2_RTS */
+	outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+	/* GP56 - SER2_CTS */
+	outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+	/* GP57 - SER2_DTR */
+	outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+	/* GP60 - LED_GREEN */
+	outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+	/* GP61 - LED_YELLOW */
+	outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+	/* GP3 */
+	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+	/* GP4 */
+	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+	/* FAN1 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+	/* FAN2 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+	/* Fan Control */
+	outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+	/* Fan1 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+	/* Fan2 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+	/* LED1 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+	/* LED2 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+	/* Keyboard Scan Code */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+	/* Exit the configuration state. */
+	outb(0xaa, port);
+}

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-01 14:33:19 UTC (rev 4247)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-02 00:50:58 UTC (rev 4248)
@@ -1,120 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	device_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
-	/* Set GPIO25 to input and drive GPIO23 to high,
-	 * this enables the LAN controller. 
-	 */
-	udelay(10);
-	set_gpio = 0x0000ffff;
-	set_gpio |= 1 << 25;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
-
-	set_gpio = 0x1b3f0000;
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	outb(0x55, port);		/* Enter the configuration state. */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-	outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
-	outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
-	outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
-	outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
-	outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
-	outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
-	outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */
-	outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
-	outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
-	outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
-	outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
-	outb(0xaa, port);		/* Exit the configuration state. */
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define PME_DEV			PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
+#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+	device_t dev;
+	uint16_t port;
+	uint32_t set_gpio;
+
+	/* Southbridge GPIOs. */
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+	/* Set GPIO23 to high, this enables the LAN controller. */
+	udelay(10);
+	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+	set_gpio |= 1 << 23;
+	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+	/* Super I/O GPIOs. */
+	dev = PME_DEV;
+	port = dev >> 8;
+
+	/* Enter the configuration state. */
+	outb(0x55, port);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+	pnp_set_enable(dev, 1);
+
+	/* GP21 - LED_RED */
+	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+	/* GP30 - FAN2_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
+
+	/* GP31 - FAN1_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+	/* GP32 - FAN2_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
+
+	/* GP33 - FAN1_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+	/* GP34 - AUD_MUTE_OUT_R */
+	outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+	/* GP36 - KBRST */
+	outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+	/* GP37 - A20GATE */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+	/* GP42 - GPIO_PME_OUT */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
+
+	/* GP50 - SER2_RI */
+	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+	/* GP51 - SER2_DCD */
+	outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+	/* GP52 - SER2_RX */
+	outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+	/* GP53 - SER2_TX */
+	outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+	/* GP55 - SER2_RTS */
+	outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+	/* GP56 - SER2_CTS */
+	outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+	/* GP57 - SER2_DTR */
+	outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+	/* GP60 - LED_GREEN */
+	outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+	/* GP61 - LED_YELLOW */
+	outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+	/* GP3 */
+	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+	/* GP4 */
+	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+	/* FAN1 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+	/* FAN2 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+	/* Fan Control */
+	outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+	/* Fan1 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+	/* Fan2 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+	/* LED1 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+	/* LED2 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+	/* Keyboard Scan Code */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+	/* Exit the configuration state. */
+	outb(0xaa, port);
+}




From svn at coreboot.org  Sat May  2 02:59:03 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 May 2009 02:59:03 +0200
Subject: [coreboot] [v2] r4249 - in trunk/coreboot-v2/src:
	mainboard/rca/rm4100 southbridge/intel/i82801xx
Message-ID: <mailman.3149.1355071533.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-02 02:59:03 +0200 (Sat, 02 May 2009)
New Revision: 4249

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c
   trunk/coreboot-v2/src/mainboard/rca/rm4100/chip.h
   trunk/coreboot-v2/src/mainboard/rca/rm4100/mainboard.c
   trunk/coreboot-v2/src/mainboard/rca/rm4100/spd_table.h
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
Log:
Trivial, update email address. 
Signed-off-by: Joseph Smith <joe at settoplinux.org> 
Acked-by: Joseph Smith <joe at settoplinux.org>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+## Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org> 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/chip.h	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/chip.h	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org> 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/mainboard.c	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/mainboard.c	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/spd_table.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/spd_table.h	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/spd_table.h	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	2009-05-02 00:50:58 UTC (rev 4248)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c	2009-05-02 00:59:03 UTC (rev 4249)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as




From lionel.broche at gmail.com  Sat May  2 11:29:40 2009
From: lionel.broche at gmail.com (Lionel Broche)
Date: Sat, 2 May 2009 10:29:40 +0100
Subject: [coreboot] Could coreboot work on my laptop?
Message-ID: <28eb2f9d0905020229u5d45bd20we52f18e8c0d3f488@mail.gmail.com>

Hi,

First of all, congratulations for your work! I wish you a great
success with coreboot, it really is an interesting and useful project.
I have a laptop with the following material. Do you think I can
install Coreboot?

Motherboard: Manufacturer: Intel Corporation
	            Product Name: SANTA ROSA CRB
chipsets: Manufacturer: Intel Corporation
	      Product Name: Crestline & ICH8M Chipset
processor: Intel Core 2 Duo

The lspci -tvnn command gives me the following:

-[0000:00]-+-00.0  Intel Corporation Mobile PM965/GM965/GL960 Memory
Controller Hub [8086:2a00]
           +-01.0-[0000:01]----00.0  nVidia Corporation GeForce 8600M
GS [10de:0425]
           +-1a.0  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #4 [8086:2834]
           +-1a.1  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #5 [8086:2835]
           +-1a.7  Intel Corporation 82801H (ICH8 Family) USB2 EHCI
Controller #2 [8086:283a]
           +-1b.0  Intel Corporation 82801H (ICH8 Family) HD Audio
Controller [8086:284b]
           +-1c.0-[0000:02-03]----00.0  Atheros Communications Inc.
AR242x 802.11abg Wireless PCI Express Adapter [168c:001c]
           +-1c.2-[0000:04-05]----00.0  Realtek Semiconductor Co.,
Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller
[10ec:8136]
           +-1c.3-[0000:06-07]--
           +-1d.0  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #1 [8086:2830]
           +-1d.1  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #2 [8086:2831]
           +-1d.2  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #3 [8086:2832]
           +-1d.7  Intel Corporation 82801H (ICH8 Family) USB2 EHCI
Controller #1 [8086:2836]
           +-1e.0-[0000:08]--
           +-1f.0  Intel Corporation 82801HEM (ICH8M) LPC Interface
Controller [8086:2815]
           +-1f.2  Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA
IDE Controller [8086:2828]
           \-1f.3  Intel Corporation 82801H (ICH8 Family) SMBus
Controller [8086:283e]

I don't know what I/O chip is on the mainboard, and superiotool -dV
fails to find anything, and the result of flashrom -V is attached in a
file.

And thanks for your hard work!

Lionel
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From c-d.hailfinger.devel.2006 at gmx.net  Sat May  2 13:46:25 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 02 May 2009 13:46:25 +0200
Subject: [coreboot] [v2] r4248 - in
 trunk/coreboot-v2/src/mainboard:	rca/rm4100 thomson/ip1000
In-Reply-To: <20090502005143.22961gmx1@mx004.gmx.net>
References: <20090502005143.22961gmx1@mx004.gmx.net>
Message-ID: <49FC3291.3010104@gmx.net>

Hi Joe,

there is a small problem with your commit. Both files has their line
endings (newlines) changed from LF (Unix style) to CR+LF (DOS style).

On 02.05.2009 02:50, svn at coreboot.org wrote:
> Author: linux_junkie
> Date: 2009-05-02 02:50:58 +0200 (Sat, 02 May 2009)
> New Revision: 4248
>
> Modified:
>    trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
>    trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
> Log:
> Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something. 
> Signed-off-by: Joseph Smith <joe at settoplinux.org> 
> Acked-by: Joseph Smith <joe at settoplinux.org>
>   

Almost all files in our tree have LF line terminators. Exceptions are:

CR+LF:
src/southbridge/intel/i82801ca/i82801ca_pci.c
src/northbridge/intel/i82830/vga.c
src/cpu/intel/model_f4x/microcode_MBDF410D.h
src/mainboard/thomson/ip1000/gpio.c
src/mainboard/dell/s1850/irq_tables.c
src/mainboard/rca/rm4100/gpio.c

Mix of CR+LF and LF:
src/mainboard/msi/ms9185/Options.lb
src/mainboard/msi/ms9282/Options.lb
src/mainboard/asus/m2v-mx_se/Options.lb

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Sat May  2 14:42:31 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 May 2009 14:42:31 +0200
Subject: [coreboot] [v2] r4250 - in trunk/coreboot-v2: documentation
	src/cpu/intel/model_f4x src/mainboard/asus/m2v-mx_se
	src/mainboard/dell/s1850 src/mainboard/msi/ms9185
	src/mainboard/msi/ms9282 src/mainboard/rca/rm4100
	src/mainboard/thomson/ip1000 src/northbridge/intel/i82830
	src/southbridge/intel/i82801ca targets/intel/xe7501devkit
	util/cbfstool/tools/lzma/C util/cbfstool/tools/lzma/C/7zip
	util/cbfstool/tools/lzma/C/7zip/Common
	util/cbfstool/tools/lzma/C/7zip/Compress/LZ
	util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree
	util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain
	util/cbfstool/tools/lzma/C/7zip/Compress/LZMA
	util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder
	util/cbfstool/tools/lzma/C/Common
Message-ID: <mailman.3150.1355071534.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-05-02 14:42:30 +0200 (Sat, 02 May 2009)
New Revision: 4250

Modified:
   trunk/coreboot-v2/documentation/codeflow.svg
   trunk/coreboot-v2/documentation/hypertransport.svg
   trunk/coreboot-v2/src/cpu/intel/model_f4x/microcode_MBDF410D.h
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
   trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
   trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_pci.c
   trunk/coreboot-v2/targets/intel/xe7501devkit/VERSION
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/InBuffer.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StdAfx.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree2.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree3.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree4.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTreeMain.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HC4.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HCMain.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/StdAfx.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMA.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/StdAfx.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoder.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBitTree.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderOpt.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/StdAfx.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/ICoder.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/IStream.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.cpp
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Defs.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyCom.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyGuidDef.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyInitGuid.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyUnknown.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/NewHandler.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/StdAfx.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Types.h
   trunk/coreboot-v2/util/cbfstool/tools/lzma/C/LGPL.txt
Log:
Run dos2unix on all files:

find . -type f| grep -v svn | xargs dos2unix

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/documentation/codeflow.svg
===================================================================
--- trunk/coreboot-v2/documentation/codeflow.svg	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/documentation/codeflow.svg	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,234 +1,234 @@
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Modified: trunk/coreboot-v2/documentation/hypertransport.svg
===================================================================
--- trunk/coreboot-v2/documentation/hypertransport.svg	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/documentation/hypertransport.svg	2009-05-02 12:42:30 UTC (rev 4250)
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Modified: trunk/coreboot-v2/src/cpu/intel/model_f4x/microcode_MBDF410D.h
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_f4x/microcode_MBDF410D.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/cpu/intel/model_f4x/microcode_MBDF410D.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,1024 +1,1024 @@
-0x00000001, /* Header Version	*/
-0x0000000d, /* Patch ID		*/
-0x11032004, /* DATE		*/
-0x00000f41, /* CPUID		*/
-0xa3430d74, /* Checksum		*/
-0x00000001, /* Loader Version	*/
-0x000000bd, /* Platform ID	*/
-0x00000fd0, /* Data size	*/
-0x00001000, /* Total size	*/
-0x00000000, /* reserved		*/
-0x00000000, /* reserved		*/
-0x00000000, /* reserved		*/
-0x23869663,
-0x00e8d132,
-0xc1efa329,
-0x20662968,
-0xb833cad6,
-0x78012780,
-0x0971cf44,
-0xda1410ae,
-0xece61219,
-0x5ec0a10c,
-0x5a1c529c,
-0x9b5e4fac,
-0x35fee068,
-0x24bb3539,
-0xa6c23421,
-0x0309a01d,
-0x80331c7b,
-0x960d5da2,
-0x56d31115,
-0xdaadb98b,
-0x8d5c0ca8,
-0xc1fc4f86,
-0xef6ee956,
-0x512c9483,
-0x08a9c125,
-0x03b95162,
-0x6499668c,
-0x25e15127,
-0xfb4f0f0b,
-0x10d1b2c3,
-0x542be728,
-0xa0f11cc9,
-0xa5bc6bd2,
-0xf3b7cc86,
-0xe4a91466,
-0x41eceee1,
-0x5beb249b,
-0x6ab82791,
-0x2c5a86ac,
-0x90c2865d,
-0x4702c4a5,
-0xbddad5f1,
-0xb2e224fb,
-0x0ffb50d3,
-0x13c6933c,
-0xc573b9df,
-0x908510f6,
-0xca6f3a9e,
-0x2049f489,
-0xe20b8848,
-0xfd659d6e,
-0xc9afd397,
-0x1432aa70,
-0x62c3e20c,
-0xee6dda59,
-0xe8601135,
-0xa9e30f8e,
-0x691b59e5,
-0x0446816b,
-0xd63a3f0c,
-0x5d1b9d99,
-0xfe8d9637,
-0xee61a0a4,
-0xeeae5aa0,
-0x709d78e6,
-0x5468e7fb,
-0x7e0f2dc3,
-0x632591e1,
-0x990864bb,
-0x413a220b,
-0x5285bdcd,
-0xb7323fa6,
-0xfe0098ce,
-0xd05d24b2,
-0x51ee2e1e,
-0x0078c207,
-0x9d1e1514,
-0x1be23c59,
-0xa80398e4,
-0xe0fa94c8,
-0x2b2f841e,
-0x21144f67,
-0x0a6a1413,
-0xfa30499a,
-0xba49558e,
-0x1607d767,
-0xebd70987,
-0x00cb016d,
-0xac1de18a,
-0xfcde8566,
-0x23f51d05,
-0xb7368509,
-0x9b1947fd,
-0x0d0d3c22,
-0xfbeab67d,
-0xfc963120,
-0x0aeae56b,
-0x0dbe2aeb,
-0x6d4ba825,
-0xab4b8dae,
-0x23bbe7a0,
-0x53d38f2e,
-0x6ee7bed3,
-0x39869966,
-0x8e36076d,
-0x410dca57,
-0x133c4861,
-0xcc2920d0,
-0xb1cfc172,
-0xd3c2e94b,
-0x8cdb7550,
-0xcb14be86,
-0x1c72bb42,
-0x469a6066,
-0x912f65eb,
-0x173ac7b9,
-0xfa02afca,
-0x23fc44f2,
-0xbbf0c89f,
-0xa018ba5f,
-0x950654d1,
-0x1b6d7652,
-0xb2a04767,
-0x86630316,
-0xff3fd7b3,
-0x9c9b3aba,
-0xb7d6115b,
-0x7c7a354c,
-0x1761b195,
-0xc54b49dd,
-0x2e0f5f20,
-0xaf1e90b2,
-0x07056032,
-0x46ccdd94,
-0xcc751ec5,
-0x4774af8a,
-0x24a3dba1,
-0xa388bccc,
-0xacd1c25a,
-0x4ee406c1,
-0x9861931a,
-0x5bae36e2,
-0xafc6e087,
-0x8d36cd1b,
-0x25f894d1,
-0xd749fdaa,
-0x3cef917d,
-0xb85440c2,
-0x4d22a2bf,
-0x19703ee4,
-0xa5fd9e1e,
-0x76062779,
-0x14031f62,
-0x6e309271,
-0x55476f65,
-0xb4fd2411,
-0x554882db,
-0xee9d4d38,
-0x57faf730,
-0x730e0285,
-0xb882d382,
-0xc156852d,
-0xf2db8f7a,
-0xea52f3e4,
-0x323430d1,
-0x51ea5fe9,
-0x0929d601,
-0x8e6740cf,
-0x69c456e1,
-0xd9e2f5c1,
-0x0124bf3b,
-0x0220f415,
-0xfbe91365,
-0x2bc82d06,
-0x0a31f25c,
-0xbeaf32af,
-0x3c2175b7,
-0xe8f67a0e,
-0x177bb8fa,
-0x33b86eb3,
-0x3ba0e579,
-0x368fc48b,
-0xe6665da8,
-0x688bfd43,
-0x48448000,
-0xc5c99d34,
-0xab99cfeb,
-0x1ce9c58d,
-0x773ae448,
-0x3534d849,
-0x6d86470f,
-0x306db8d0,
-0x550c15ff,
-0x7a2c439a,
-0xe6f1b78f,
-0x0bf4cdd7,
-0xfbcab3d7,
-0x402e87ec,
-0xf4ee5874,
-0xc03c70d9,
-0x3b9ed9e6,
-0x04ef67e0,
-0xd04ae924,
-0xf6845607,
-0x5e58c954,
-0xc2fdf283,
-0xc558ae4e,
-0x8300ece1,
-0x7bbaea80,
-0xc5d0b0f1,
-0xfc9e8004,
-0xfcea494a,
-0x04f4eb47,
-0x129f505d,
-0xccbae019,
-0x59c0616f,
-0xaaba53a8,
-0x19d8a002,
-0x361fb171,
-0x00c4aee2,
-0x6bb0dfb0,
-0xc03d6b9a,
-0xabaed6fb,
-0xa23c48fe,
-0x50866e98,
-0xbb499854,
-0xb5730aad,
-0xbe89d93c,
-0xe6d35886,
-0x7ae05c20,
-0xc2708cbd,
-0xf8f18059,
-0xf492c48e,
-0x14121e3d,
-0x9e9dc5a7,
-0xafa3ef3a,
-0x17535114,
-0x08296547,
-0xe1ab5d3c,
-0x2e51d954,
-0x0e6953db,
-0xde0ea136,
-0xd1f37944,
-0x3074f7ed,
-0x3b196093,
-0x0efb3b56,
-0x3b904c2c,
-0xcef179ee,
-0xc854e7f5,
-0x48aa28ce,
-0x1c0cb17e,
-0xae4236b2,
-0x87c5dc18,
-0x7832ec05,
-0xc4212949,
-0xca5a40d2,
-0x8e8f431d,
-0x328df52b,
-0xe4dd2524,
-0x7b8ae78a,
-0x17ba24a3,
-0x25eb59d5,
-0x1a341b63,
-0x45f1e3f2,
-0x0e2d9cf8,
-0xa66c17e8,
-0x515bc934,
-0xfea866d3,
-0xd149deac,
-0x740a7cf5,
-0x2f47375b,
-0xa5fdd0c4,
-0xd8965720,
-0x4ecefd2f,
-0x1916443a,
-0x984995a9,
-0x7b919733,
-0x80f02747,
-0x30fe0d17,
-0x65a68843,
-0xdb0931ad,
-0x0929b113,
-0x1bd4cc0c,
-0x7b2f63fd,
-0x6238656c,
-0x8a1badab,
-0x6565a869,
-0xca48cce2,
-0x7ff6bdc3,
-0x772305d4,
-0x376639d3,
-0x56ed9f11,
-0x75e17cef,
-0x7dffbcf4,
-0xfbafb077,
-0x932aed24,
-0x8b04ebf4,
-0x768ac85f,
-0xb54a99f9,
-0xd4fdf692,
-0x43b09d0a,
-0x32d81423,
-0xcb2a74e6,
-0x59f40d29,
-0x6392b933,
-0x7a3bc72c,
-0xfa647af0,
-0x2c28e15f,
-0xa724e1b0,
-0x6174f8f6,
-0x651672ab,
-0xd8eb376a,
-0x61d18571,
-0xa9bab242,
-0x2ba20ac2,
-0x332c20a9,
-0x21e71331,
-0x7ba9dbe4,
-0x1e61e44d,
-0x07ee9579,
-0xd1846f7a,
-0xca29125b,
-0x11958b89,
-0xb6fe5a2b,
-0x249991b4,
-0x5f28c005,
-0x0b909d87,
-0x673159ab,
-0xf25d3b1a,
-0x2a7f0d31,
-0x2e741145,
-0x60c1525d,
-0x7a2996a7,
-0x5051ead4,
-0xb9473e57,
-0x7c5f9d0e,
-0x51584719,
-0xa25c2246,
-0xceec4103,
-0x813e68be,
-0xabf2eed8,
-0x4fb4988f,
-0x678fba46,
-0x801b82e1,
-0x7fc428dc,
-0xa30bf423,
-0xd1dc03db,
-0x65d1f1fb,
-0xfea39d25,
-0x7b8cfad4,
-0x7eda42af,
-0x4c7cb670,
-0x1ac54e69,
-0x6ecd00ae,
-0x2ff34b4e,
-0x0f7c1999,
-0x14713cb0,
-0x3942aea8,
-0x07832b5c,
-0x5cd3fa0c,
-0x918b4916,
-0xe9420e66,
-0x8bd0f43c,
-0x28e79a91,
-0x999c89a3,
-0x59da832c,
-0x3dd8cb18,
-0x67deb7fe,
-0xa4f503bb,
-0x77f8114f,
-0xe732a72b,
-0x7e8b8835,
-0x10192856,
-0x54da048f,
-0x8ea0f6cd,
-0x722ba57f,
-0x133ad6fc,
-0x7d486fb3,
-0x27764f83,
-0x8c0dff5f,
-0x9f137e77,
-0x5d6b4057,
-0xeef4eee0,
-0xb0e0e900,
-0xf37b72f1,
-0xec1b84f5,
-0x0a454136,
-0xc23a91a3,
-0x0ab3bae8,
-0x715496f9,
-0xc1082181,
-0xccf9217f,
-0x5213635d,
-0x2e29ab5b,
-0xb4574eef,
-0x2bc2fea8,
-0x1ee67ef8,
-0xd567c2b8,
-0xfc19ef2c,
-0xe19af740,
-0x28a28944,
-0x836be662,
-0xb0080f12,
-0xd6f61914,
-0x33c85c03,
-0x326e680f,
-0x87b45aa5,
-0xad7c015b,
-0x63e312a9,
-0x65fb08cf,
-0x5fca6d27,
-0x7b57bef5,
-0x466fa276,
-0x56c21f72,
-0x38fb8f1d,
-0xc1966d08,
-0x15d4c28b,
-0xeec1eade,
-0x905f5218,
-0x5be29b59,
-0xb64aa150,
-0xc8994548,
-0xe4bfb038,
-0xd63e54cf,
-0x98469c03,
-0xb28e3b7b,
-0xf852cae3,
-0xc76b8b09,
-0x16810021,
-0x8ea0bfec,
-0xdfc083e5,
-0x884c8453,
-0x908a80f2,
-0xb6d91870,
-0x56ad6422,
-0x05174668,
-0x380d8035,
-0xeef37603,
-0x38ff195e,
-0x44898288,
-0xb300620f,
-0xa814ec47,
-0xa58d3007,
-0x7d4536f5,
-0x2dfc2f4d,
-0xfa2ae308,
-0x24d4799f,
-0x1423df15,
-0x82dc572b,
-0xa3141ca3,
-0xa1210bb1,
-0xb7eecdc4,
-0x5d9ac524,
-0xb8f4b3fb,
-0x6cd8f8a8,
-0x0e745c45,
-0xb0041dbe,
-0x6ee22101,
-0xc9fb746b,
-0x69909b4d,
-0x9e63a31c,
-0xbc627065,
-0x6b24225b,
-0x1d2b80b1,
-0x4c08e46b,
-0x1f78a68c,
-0x75bc0a34,
-0x74d23ab8,
-0xb16d2786,
-0xfbb6fa5f,
-0xc9bbf303,
-0x69ebae66,
-0xcfa4bf29,
-0xaa69d19e,
-0x5d965c81,
-0x7cebac23,
-0x030b7aca,
-0x7983efba,
-0x03babdb7,
-0xd9d7a8bb,
-0xa939d7e1,
-0x6913d42f,
-0xfce3f3b5,
-0xb9d2a26b,
-0x32e614b2,
-0xbbb00851,
-0x4313ca42,
-0xe17a6d39,
-0x5b9f0631,
-0x90569ece,
-0xf980f983,
-0x13eb7233,
-0xc8da9166,
-0x60dbe5fc,
-0x4621997a,
-0xccd2a527,
-0x061180aa,
-0xa92467da,
-0x3dc79eef,
-0x39f31e91,
-0x9e45191c,
-0x7dcba672,
-0xfc23a8b8,
-0x1a773f6a,
-0x6fc6fa46,
-0x46b50e14,
-0x514bd261,
-0xe6cc3574,
-0x5a88dea2,
-0x9121d758,
-0x7f39e3bf,
-0x9ab043b6,
-0xc1007d0c,
-0xc3c3ff8e,
-0x08411386,
-0x0bd529d7,
-0xcaa9a1d8,
-0x27b19be2,
-0x95703f7e,
-0x44ab493a,
-0xcf1fc404,
-0x3f34062d,
-0xa56d454b,
-0x9464f996,
-0x1346eadf,
-0xdd6e6895,
-0x27b5ba10,
-0xb84c1d0c,
-0x5fa57ca4,
-0xad052de8,
-0xf5b4a3ae,
-0x6a61144d,
-0x48c00092,
-0x4897fad0,
-0x90b7b116,
-0xcdf29b2c,
-0xa41aac9a,
-0x147d09f7,
-0xebf3615d,
-0xb3ddf0b0,
-0xc8edc675,
-0x43cbf71b,
-0xfa0a0b5c,
-0xe0b63692,
-0x6c5870a9,
-0xe0b37be9,
-0xb16acc39,
-0xc55aed8c,
-0xd34fb041,
-0x24735885,
-0x0fff6e94,
-0x834181e8,
-0x56671872,
-0xb3f2e29b,
-0xfa383cd3,
-0xe585e5b6,
-0xa40cb894,
-0x1fe8376a,
-0xf794c60a,
-0xa3efdb18,
-0x0df1f1b4,
-0x54230798,
-0xd2a8ba49,
-0x349ce466,
-0xcbff13b4,
-0x71a63418,
-0x728ae615,
-0xf7c4f811,
-0x0dd072d8,
-0x9aa6fac7,
-0xa44210d0,
-0x2a1a85bf,
-0x1e18a8c6,
-0xbe2bb680,
-0xfed00f0e,
-0x2acc1b4b,
-0x4f049f6f,
-0x6f5aeec1,
-0x2db8f7b4,
-0xd61041a2,
-0x5cc7c861,
-0xb6ed3676,
-0x02aef566,
-0x2b6d41c8,
-0xaba9296e,
-0xf7b032cd,
-0xc290e538,
-0x584ad0f9,
-0x95289bc7,
-0x49b428b8,
-0x84bb41d4,
-0xdf0fcf91,
-0x9bd712a9,
-0xc6f730e1,
-0xe28b78d4,
-0x45b0480d,
-0x29d344bf,
-0xcd0101bb,
-0x18561b59,
-0xcfa84f65,
-0x76e798eb,
-0xac73f8af,
-0x71fe2488,
-0x207dd75d,
-0x198130e5,
-0x3604d44d,
-0xd895dc9b,
-0xf55fe7e2,
-0x4fed2e51,
-0xf434e20a,
-0x7c3204e8,
-0x4d653a59,
-0x6652a556,
-0x8713f1e2,
-0xa69dea42,
-0x2fd0ee37,
-0xe7617993,
-0xc0791c80,
-0x57e14435,
-0x87fcad6e,
-0x96505f56,
-0x838e7a38,
-0x78b228ab,
-0x84411d16,
-0x0b4e1d87,
-0x21f17d96,
-0x72021b3c,
-0xe69f4784,
-0x324fb9b4,
-0x041c7459,
-0x500ffe39,
-0x6e561c0f,
-0xadaf6fd7,
-0x0c91509f,
-0x8be04594,
-0x6a5ead5a,
-0x313c9f9d,
-0xe4754919,
-0x63d7cebc,
-0x02d0ad32,
-0x2dc3cdb7,
-0xd9b2e421,
-0xa1ad018c,
-0xd954f545,
-0x9f3871b2,
-0xf8a9a4a9,
-0x4cdc558d,
-0x300c9685,
-0x639f4b78,
-0x2181680d,
-0xb96442d6,
-0x7821a1a2,
-0x174a9e5b,
-0x79320590,
-0xf580c60c,
-0xba8539ce,
-0x59905669,
-0xc6f39c94,
-0xb57cc9bf,
-0xc2f7ad76,
-0x8d9ebc2d,
-0x6c33e47f,
-0x29294c84,
-0x49a2bef6,
-0x8aa6f79b,
-0x809f0eb5,
-0x3691aa7f,
-0xcf4b0e8f,
-0xec44f802,
-0x16bf83a7,
-0x82c00d36,
-0xa99071b1,
-0xe3815c76,
-0xc0835331,
-0xc794c55f,
-0x041b44af,
-0x2fa75171,
-0x985bd852,
-0xc4391e66,
-0x7bf08eaf,
-0x2b826882,
-0xfb8834dc,
-0x9128681e,
-0x6a2cb9ef,
-0x6d1d20f9,
-0x9f90ee4d,
-0xc48c3ee3,
-0xdd063585,
-0x82454044,
-0xf7077f1a,
-0x47e6e556,
-0xd803f7dd,
-0x98f67f71,
-0x9089e4ac,
-0xe7f09610,
-0xa9e3f93b,
-0x420c1550,
-0xc01f7710,
-0x0905da5e,
-0x02d71f99,
-0xbf36b473,
-0x50a96e32,
-0x2dedb8b9,
-0x9e3051a2,
-0x84c023c4,
-0xd43073b1,
-0x74f23fbb,
-0xd42a4487,
-0x266dfc42,
-0x6be0acdf,
-0xa986294c,
-0x3ee65aa8,
-0x19c1cf4f,
-0x2fdf8308,
-0xa6a64910,
-0xc3fa82e8,
-0x2943c8b8,
-0xf1a60b7b,
-0x4cc9ea04,
-0x3cc95270,
-0x054a8d2b,
-0xae7a4525,
-0x2e2abb62,
-0x24b9522b,
-0xb95a6668,
-0xad8c237d,
-0x1ea73bf8,
-0xff33f0d6,
-0x772a16a3,
-0xfefabdc4,
-0xb181234c,
-0xab59fb47,
-0x96f2c987,
-0xff0d4f54,
-0x6e938aba,
-0x727e6266,
-0xea0d851f,
-0x2ced3474,
-0x8c2e7718,
-0xa576c375,
-0xc97addeb,
-0x2f46a635,
-0xdb669986,
-0xa4333f93,
-0x7042c2c6,
-0x419fda5f,
-0x95b8aa3f,
-0x6ad05dc8,
-0x8b90655a,
-0xd8c77947,
-0x20508480,
-0xfa3cdf6b,
-0xdbb44af2,
-0x235941d0,
-0x3154c107,
-0x566bc32a,
-0x426fb2cd,
-0xd2010afa,
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+0x00000001, /* Header Version	*/
+0x0000000d, /* Patch ID		*/
+0x11032004, /* DATE		*/
+0x00000f41, /* CPUID		*/
+0xa3430d74, /* Checksum		*/
+0x00000001, /* Loader Version	*/
+0x000000bd, /* Platform ID	*/
+0x00000fd0, /* Data size	*/
+0x00001000, /* Total size	*/
+0x00000000, /* reserved		*/
+0x00000000, /* reserved		*/
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+0xe17a6d39,
+0x5b9f0631,
+0x90569ece,
+0xf980f983,
+0x13eb7233,
+0xc8da9166,
+0x60dbe5fc,
+0x4621997a,
+0xccd2a527,
+0x061180aa,
+0xa92467da,
+0x3dc79eef,
+0x39f31e91,
+0x9e45191c,
+0x7dcba672,
+0xfc23a8b8,
+0x1a773f6a,
+0x6fc6fa46,
+0x46b50e14,
+0x514bd261,
+0xe6cc3574,
+0x5a88dea2,
+0x9121d758,
+0x7f39e3bf,
+0x9ab043b6,
+0xc1007d0c,
+0xc3c3ff8e,
+0x08411386,
+0x0bd529d7,
+0xcaa9a1d8,
+0x27b19be2,
+0x95703f7e,
+0x44ab493a,
+0xcf1fc404,
+0x3f34062d,
+0xa56d454b,
+0x9464f996,
+0x1346eadf,
+0xdd6e6895,
+0x27b5ba10,
+0xb84c1d0c,
+0x5fa57ca4,
+0xad052de8,
+0xf5b4a3ae,
+0x6a61144d,
+0x48c00092,
+0x4897fad0,
+0x90b7b116,
+0xcdf29b2c,
+0xa41aac9a,
+0x147d09f7,
+0xebf3615d,
+0xb3ddf0b0,
+0xc8edc675,
+0x43cbf71b,
+0xfa0a0b5c,
+0xe0b63692,
+0x6c5870a9,
+0xe0b37be9,
+0xb16acc39,
+0xc55aed8c,
+0xd34fb041,
+0x24735885,
+0x0fff6e94,
+0x834181e8,
+0x56671872,
+0xb3f2e29b,
+0xfa383cd3,
+0xe585e5b6,
+0xa40cb894,
+0x1fe8376a,
+0xf794c60a,
+0xa3efdb18,
+0x0df1f1b4,
+0x54230798,
+0xd2a8ba49,
+0x349ce466,
+0xcbff13b4,
+0x71a63418,
+0x728ae615,
+0xf7c4f811,
+0x0dd072d8,
+0x9aa6fac7,
+0xa44210d0,
+0x2a1a85bf,
+0x1e18a8c6,
+0xbe2bb680,
+0xfed00f0e,
+0x2acc1b4b,
+0x4f049f6f,
+0x6f5aeec1,
+0x2db8f7b4,
+0xd61041a2,
+0x5cc7c861,
+0xb6ed3676,
+0x02aef566,
+0x2b6d41c8,
+0xaba9296e,
+0xf7b032cd,
+0xc290e538,
+0x584ad0f9,
+0x95289bc7,
+0x49b428b8,
+0x84bb41d4,
+0xdf0fcf91,
+0x9bd712a9,
+0xc6f730e1,
+0xe28b78d4,
+0x45b0480d,
+0x29d344bf,
+0xcd0101bb,
+0x18561b59,
+0xcfa84f65,
+0x76e798eb,
+0xac73f8af,
+0x71fe2488,
+0x207dd75d,
+0x198130e5,
+0x3604d44d,
+0xd895dc9b,
+0xf55fe7e2,
+0x4fed2e51,
+0xf434e20a,
+0x7c3204e8,
+0x4d653a59,
+0x6652a556,
+0x8713f1e2,
+0xa69dea42,
+0x2fd0ee37,
+0xe7617993,
+0xc0791c80,
+0x57e14435,
+0x87fcad6e,
+0x96505f56,
+0x838e7a38,
+0x78b228ab,
+0x84411d16,
+0x0b4e1d87,
+0x21f17d96,
+0x72021b3c,
+0xe69f4784,
+0x324fb9b4,
+0x041c7459,
+0x500ffe39,
+0x6e561c0f,
+0xadaf6fd7,
+0x0c91509f,
+0x8be04594,
+0x6a5ead5a,
+0x313c9f9d,
+0xe4754919,
+0x63d7cebc,
+0x02d0ad32,
+0x2dc3cdb7,
+0xd9b2e421,
+0xa1ad018c,
+0xd954f545,
+0x9f3871b2,
+0xf8a9a4a9,
+0x4cdc558d,
+0x300c9685,
+0x639f4b78,
+0x2181680d,
+0xb96442d6,
+0x7821a1a2,
+0x174a9e5b,
+0x79320590,
+0xf580c60c,
+0xba8539ce,
+0x59905669,
+0xc6f39c94,
+0xb57cc9bf,
+0xc2f7ad76,
+0x8d9ebc2d,
+0x6c33e47f,
+0x29294c84,
+0x49a2bef6,
+0x8aa6f79b,
+0x809f0eb5,
+0x3691aa7f,
+0xcf4b0e8f,
+0xec44f802,
+0x16bf83a7,
+0x82c00d36,
+0xa99071b1,
+0xe3815c76,
+0xc0835331,
+0xc794c55f,
+0x041b44af,
+0x2fa75171,
+0x985bd852,
+0xc4391e66,
+0x7bf08eaf,
+0x2b826882,
+0xfb8834dc,
+0x9128681e,
+0x6a2cb9ef,
+0x6d1d20f9,
+0x9f90ee4d,
+0xc48c3ee3,
+0xdd063585,
+0x82454044,
+0xf7077f1a,
+0x47e6e556,
+0xd803f7dd,
+0x98f67f71,
+0x9089e4ac,
+0xe7f09610,
+0xa9e3f93b,
+0x420c1550,
+0xc01f7710,
+0x0905da5e,
+0x02d71f99,
+0xbf36b473,
+0x50a96e32,
+0x2dedb8b9,
+0x9e3051a2,
+0x84c023c4,
+0xd43073b1,
+0x74f23fbb,
+0xd42a4487,
+0x266dfc42,
+0x6be0acdf,
+0xa986294c,
+0x3ee65aa8,
+0x19c1cf4f,
+0x2fdf8308,
+0xa6a64910,
+0xc3fa82e8,
+0x2943c8b8,
+0xf1a60b7b,
+0x4cc9ea04,
+0x3cc95270,
+0x054a8d2b,
+0xae7a4525,
+0x2e2abb62,
+0x24b9522b,
+0xb95a6668,
+0xad8c237d,
+0x1ea73bf8,
+0xff33f0d6,
+0x772a16a3,
+0xfefabdc4,
+0xb181234c,
+0xab59fb47,
+0x96f2c987,
+0xff0d4f54,
+0x6e938aba,
+0x727e6266,
+0xea0d851f,
+0x2ced3474,
+0x8c2e7718,
+0xa576c375,
+0xc97addeb,
+0x2f46a635,
+0xdb669986,
+0xa4333f93,
+0x7042c2c6,
+0x419fda5f,
+0x95b8aa3f,
+0x6ad05dc8,
+0x8b90655a,
+0xd8c77947,
+0x20508480,
+0xfa3cdf6b,
+0xdbb44af2,
+0x235941d0,
+0x3154c107,
+0x566bc32a,
+0x426fb2cd,
+0xd2010afa,
+0xe2775abe,
+0x6f543a20,
+0x2c626450,
+0x34f193f4,
+0x37ac5908,
+0x58a7eca6,
+0xc4859881,
+0x183393ff,
+0xab9abed9,
+0xde947d21,
+0xffec2b7d,
+0xb21b8788,
+0xb527117f,
+0x199dffe5,
+0xd7ebe4e6,
+0xc89a72b0,
+0x91cc3042,
+0x91bd3463,
+0x736e6f4f,
+0x0cc208bc,
+0x029f21cb,
+0x3f204418,
+0x050db787,
+0x71b56562,
+0xaf07f08f,
+0xaca4701f,
+0x88d4f2f8,
+0xf98fe016,
+0xb47672c6,
+0xed601c94,
+0x285db8b8,
+0x28a81c19,
+0x9e2763ce,
+0xe39741c0,
+0xcd9fce6d,
+0xe9917796,
+0xfdd3ebaf,
+0x99dcb253,
+0xe9aa0db4,
+0x3a65c0b0,
+0xb39c61fb,
+0x1f413c5e,
+0x60576c8c,
+0x48d6df34,
+0x0cbca786,
+0x4caff4b7,
+0x8473e181,
+0x36eed747,
+0x82f486af,
+0x79f02eed,
+0xab6886ed,
+0x06aef911,
+0xad42a654,
+0x5471c813,
+0xc8bbe710,
+0xfc65fd97,
+0x60f467af,
+0xf56b71d8,
+0xc1d6f193,
+0x3a1c42bf,
+0x46ce3b78,
+0x39472626,
+0x04dc137e,
+0xb48dc9dd,
+0xdfd27741,
+0x4718e5a2,
+0x00ba4728,
+0x855b661f,
+0x6d98577f,
+0xc3b48131,
+0x2b0384c1,
+0x8af572fe,
+0x760aa4e3,
+0x2f5b53fb,
+0xb9234297,
+0x401b47f5,
+0x44237cc0,
+0x2f7205f4,
+0x19b63c6e,
+0x7c375e6b,
+0x152c42d8,
+0x603731c7,
+0xc67601fb,
+0xa5d4826c,
+0x9068966f,
+0x864fe2f9,
+0xb37311d9,
+0xe6e4a34a,
+0xd46ee161,
+0xecd76c4a,
+0x90d0328a,
+0x4865b540,
+0xd2e13982,
+0x7e3925f4,
+0xc850a518,
+0x63bffcce,
+0x7cdb918f,
+0xcd8786d3,
+0xcf83df01,
+0x27122e50,
+0x0f014b76,
+0xde1485d7,
+0xa6ff496f,
+0xed0812f7,
+0x34efe965,
+0x12a63465,
+0xb83d9f77,
+0x040efa2e,
+0x4ac576d1,
+0x185430dd,
+0xb4271745,
+0x9bb58be2,
+0x7f55d4bb,
+0xca7dae0b,
+0x0bfe5147,
+0x4a9ade45,
+0x20bdc545,
+0xdf66689d,
+0x22e29493,
+0x31763c1f,
+0x2d021cd2,
+0x06286428,
+0xc7bba5d4,
+0x6bc42a0e,
+0x1c987082,
+0xd6c6c2f9,
+0x2c1ecdd0,
+0x84946249,
+0x42c1c41b,
+0x6d949e60,
+0x9dbb1571,
+0xf6b1df68,
+0x0705ae1a,
+0xa1ec5add,
+0x7e94d7c8,
+0x7d4d451d,
+0xd53c13d4,
+0x0204877b,
+0x0f0e44e0,
+0xdf25570f,
+0xd2a9adaf,
+0x556aeacf,
+0x2f985a30,
+0x706c42c6,
+0x2d5a76a5,
+0xdc428213,
+0xdf2864a2,
+0x0f6788a9,
+0xc764d3a6,
+0x9211d0ca,
+0x59e3f5cc,
+0xd31fd5b6,
+0xfa8b535b,
+0x2cac74bb,
+0xc43f36b2,
+0xf83b5bac,
+0x96c255bf,
+0x45915993,
+0x657d751a,
+0x9b86b994,
+0xddab62fd,
+0x1b6ac108,
+0x559073c9,
+0xe60a0bda,
+0xd65df6de,
+0x41f7e5d4,
+0x825a5701,
+0x377307b6,
+0x08176ce6,
+0x7a8a2c4a,
+0xd7ecb869,
+0x02710179,
+0x75e7517c,
+0xdfaf2c82,
+0x67590275,
+0x6ad621af,
+0xaedaa35c,
+0xfa8fbee3,
+0x9e5dda5f,
+0x09f571fa,
+0xe358dbfe,
+0x1b3300f1,
+0x05567c6b,
+0x5a9d335f,
+0x215114f8,
+0xd5744f0a,
+0x78ecc142,
+0x9b5f60b8,
+0x30f8fed2,
+0x5c013696,
+0x675c84de,
+0xdb50bbcc,
+0x7c504a4e,
+0x3ffc5fda,
+0x24b2c30a,
+0xac00d64a,
+0x97832b52,
+0xb34d9975,
+0x93c6cb4e,
+0x471bfcae,
+0xaabbb6d8,
+0x0bc6a5e5,
+0x6875c630,
+0xf4cce30c,
+0xdab0d64b,
+0x29aba8b9,
+0xe34b3cde,
+0x8654e470,
+0x2c5041f7,
+0xdcf5eff9,
+0x26a88f84,
+0x9d374761,
+0xefa60ac4,
+0xdf0d0fd3,
+0x72e37e59,
+0xa76d26e1,
+0x3ffe2408,
+0x13ecf42d,
+0x46de7cba,
+0x43330219,
+0xc2536a31,
+0xa69c4729,
+0x114990f8,
+0x3f08ed00,
+0xeaa05cae,
+0x08f06e57,
+0x30f4a62f,
+0x963a7557,
+0x631fb75f,
+0x1344a74b,
+0x1e80cef5,
+0x8a4f86dd,
+0x0f7f1c62,
+0xfe9f5809,
+0x710d86de,
+0x8939283d,
+0x19403076,
+0x26ce286b,
+0x6baaf798,
+0xbc1d2808,
+0xea980728,
+0x72288979,
+0x7c92be68,
+0x0a7af91b,
+0x7bb8059b,
+0xe7eca99c,
+0xd3a8819f,
+0xb9182916,
+0x0c48ba1e,
+0xb6aaf63b,
+0x10a740a6,
+0x0aa2e4e7,
+0x0bf27e94,
+0x6d266f86,

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-05-02 12:42:30 UTC (rev 4250)
@@ -94,7 +94,7 @@
 uses SB_HT_CHAIN_ON_BUS0
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USE_PRINTK_IN_CAR
 
 default ROM_SIZE = 512 * 1024
 default FALLBACK_SIZE = 256 * 1024

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/irq_tables.c	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,48 +1,48 @@
-/* This file was generated by getpir.c, do not modify! 
-   (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*17,	 /* there can be total 17 devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x24d0,		 /* Device */
-	0,		 /* Crap (miniport) */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xc4,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-		{0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-		{0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
-		{0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
-		{0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
-		{0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
-		{0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr);
-}
-
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*17,	 /* there can be total 17 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x8086,		 /* Vendor */
+	0x24d0,		 /* Device */
+	0,		 /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xc4,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+		{0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
+		{0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+		{0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
+		{0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
+		{0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+        return copy_pirq_routing_table(addr);
+}
+

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-05-02 12:42:30 UTC (rev 4250)
@@ -220,7 +220,7 @@
 default DCACHE_RAM_BASE=0xcc000
 default DCACHE_RAM_SIZE=0x04000
 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=0
 
 ##
 ## Build code to setup a generic IOAPIC

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-05-02 12:42:30 UTC (rev 4250)
@@ -100,7 +100,7 @@
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USE_PRINTK_IN_CAR
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
@@ -265,7 +265,7 @@
 ## The Serial Console
 ##
 default CONFIG_USE_PRINTK_IN_CAR=1
-
+
 # To Enable the Serial Console
 default CONFIG_CONSOLE_SERIAL8250=1
 

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,143 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	device_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
-	/* Set GPIO23 to high, this enables the LAN controller. */
-	udelay(10);
-	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP21 - LED_RED */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP30 - FAN2_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
-
-	/* GP31 - FAN1_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
-
-	/* GP33 - FAN1_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - AUD_MUTE_OUT_R */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP36 - KBRST */
-	outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20GATE */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP42 - GPIO_PME_OUT */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
-
-	/* GP50 - SER2_RI */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - SER2_DCD */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - SER2_RX */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - SER2_TX */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP55 - SER2_RTS */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - SER2_CTS */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - SER2_DTR */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED_GREEN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED_YELLOW */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP3 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
-	/* Fan2 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
-	/* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define PME_DEV			PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
+#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+	device_t dev;
+	uint16_t port;
+	uint32_t set_gpio;
+
+	/* Southbridge GPIOs. */
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+	/* Set GPIO23 to high, this enables the LAN controller. */
+	udelay(10);
+	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+	set_gpio |= 1 << 23;
+	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+	/* Super I/O GPIOs. */
+	dev = PME_DEV;
+	port = dev >> 8;
+
+	/* Enter the configuration state. */
+	outb(0x55, port);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+	pnp_set_enable(dev, 1);
+
+	/* GP21 - LED_RED */
+	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+	/* GP30 - FAN2_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
+
+	/* GP31 - FAN1_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+	/* GP32 - FAN2_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
+
+	/* GP33 - FAN1_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+	/* GP34 - AUD_MUTE_OUT_R */
+	outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+	/* GP36 - KBRST */
+	outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+	/* GP37 - A20GATE */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+	/* GP42 - GPIO_PME_OUT */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
+
+	/* GP50 - SER2_RI */
+	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+	/* GP51 - SER2_DCD */
+	outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+	/* GP52 - SER2_RX */
+	outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+	/* GP53 - SER2_TX */
+	outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+	/* GP55 - SER2_RTS */
+	outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+	/* GP56 - SER2_CTS */
+	outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+	/* GP57 - SER2_DTR */
+	outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+	/* GP60 - LED_GREEN */
+	outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+	/* GP61 - LED_YELLOW */
+	outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+	/* GP3 */
+	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+	/* GP4 */
+	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+	/* FAN1 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+	/* FAN2 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+	/* Fan Control */
+	outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+	/* Fan1 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+	/* Fan2 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+	/* LED1 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+	/* LED2 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+	/* Keyboard Scan Code */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+	/* Exit the configuration state. */
+	outb(0xaa, port);
+}

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,143 +1,143 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	device_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
-
-	/* Set GPIO23 to high, this enables the LAN controller. */
-	udelay(10);
-	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP21 - LED_RED */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP30 - FAN2_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
-
-	/* GP31 - FAN1_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
-
-	/* GP33 - FAN1_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - AUD_MUTE_OUT_R */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP36 - KBRST */
-	outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20GATE */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP42 - GPIO_PME_OUT */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
-
-	/* GP50 - SER2_RI */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - SER2_DCD */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - SER2_RX */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - SER2_TX */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP55 - SER2_RTS */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - SER2_CTS */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - SER2_DTR */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED_GREEN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED_YELLOW */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP3 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
-	/* Fan2 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
-	/* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define PME_DEV			PNP_DEV(0x2e, 0x0a)
+#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
+#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+	device_t dev;
+	uint16_t port;
+	uint32_t set_gpio;
+
+	/* Southbridge GPIOs. */
+	/* Set the LPC device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
+
+	/* Set GPIO23 to high, this enables the LAN controller. */
+	udelay(10);
+	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
+	set_gpio |= 1 << 23;
+	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
+
+	/* Super I/O GPIOs. */
+	dev = PME_DEV;
+	port = dev >> 8;
+
+	/* Enter the configuration state. */
+	outb(0x55, port);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+	pnp_set_enable(dev, 1);
+
+	/* GP21 - LED_RED */
+	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
+
+	/* GP30 - FAN2_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x33); 
+
+	/* GP31 - FAN1_TACH */
+	outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+	/* GP32 - FAN2_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x35); 
+
+	/* GP33 - FAN1_CTRL */
+	outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+	/* GP34 - AUD_MUTE_OUT_R */
+	outl(0x00, PME_IO_BASE_ADDR + 0x37);
+
+	/* GP36 - KBRST */
+	outl(0x00, PME_IO_BASE_ADDR + 0x39);
+
+	/* GP37 - A20GATE */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
+
+	/* GP42 - GPIO_PME_OUT */
+	outl(0x00, PME_IO_BASE_ADDR + 0x3d); 
+
+	/* GP50 - SER2_RI */
+	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+	/* GP51 - SER2_DCD */
+	outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+	/* GP52 - SER2_RX */
+	outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+	/* GP53 - SER2_TX */
+	outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+	/* GP55 - SER2_RTS */
+	outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+	/* GP56 - SER2_CTS */
+	outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+	/* GP57 - SER2_DTR */
+	outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+	/* GP60 - LED_GREEN */
+	outl(0x01, PME_IO_BASE_ADDR + 0x47);
+
+	/* GP61 - LED_YELLOW */
+	outl(0x01, PME_IO_BASE_ADDR + 0x48);
+
+	/* GP3 */
+	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
+
+	/* GP4 */
+	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
+
+	/* FAN1 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+	/* FAN2 */
+	outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+	/* Fan Control */
+	outl(0x50, PME_IO_BASE_ADDR + 0x58);
+
+	/* Fan1 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x59);
+
+	/* Fan2 Tachometer */
+	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
+
+	/* LED1 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
+
+	/* LED2 */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
+
+	/* Keyboard Scan Code */
+	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+	/* Exit the configuration state. */
+	outb(0xaa, port);
+}

Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,50 +1,50 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-static void vga_init(device_t dev) {
-
-	printk_info("Starting Graphics Initialization\n");
-	pci_dev_init(dev);
-	printk_info("Graphics Initialization Complete\n");
-	/* Future TV-OUT code will be called from here. */
-}
-
-static const struct device_operations vga_operations = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = vga_init,
-	.scan_bus         = 0,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
-	.ops    = &vga_operations,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x3577,
-};
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void vga_init(device_t dev) {
+
+	printk_info("Starting Graphics Initialization\n");
+	pci_dev_init(dev);
+	printk_info("Graphics Initialization Complete\n");
+	/* Future TV-OUT code will be called from here. */
+}
+
+static const struct device_operations vga_operations = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = vga_init,
+	.scan_bus         = 0,
+	.enable           = 0,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+	.ops    = &vga_operations,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x3577,
+};

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_pci.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_pci.c	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_pci.c	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,30 +1,30 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ca.h"
-
-static void pci_init(struct device *dev)
-{
-	// NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
-	/* Enable pci error detecting */
-	uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
-	dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
-	pci_write_config32(dev, PCI_COMMAND, dword);
-}
-
-static struct device_operations pci_ops  = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = pci_init,
-	.scan_bus         = pci_scan_bridge,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
-};
-
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ca.h"
+
+static void pci_init(struct device *dev)
+{
+	// NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
+	/* Enable pci error detecting */
+	uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
+	dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+	pci_write_config32(dev, PCI_COMMAND, dword);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
+};
+

Modified: trunk/coreboot-v2/targets/intel/xe7501devkit/VERSION
===================================================================
--- trunk/coreboot-v2/targets/intel/xe7501devkit/VERSION	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/targets/intel/xe7501devkit/VERSION	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1 +1 @@
-0.1
+0.1

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/InBuffer.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/InBuffer.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/InBuffer.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,76 +1,76 @@
-// InBuffer.h
-
-#ifndef __INBUFFER_H
-#define __INBUFFER_H
-
-#include "../IStream.h"
-#include "../../Common/MyCom.h"
-
-#ifndef _NO_EXCEPTIONS
-class CInBufferException
-{
-public:
-  HRESULT ErrorCode;
-  CInBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
-};
-#endif
-
-class CInBuffer
-{
-  Byte *_buffer;
-  Byte *_bufferLimit;
-  Byte *_bufferBase;
-  CMyComPtr<ISequentialInStream> _stream;
-  UInt64 _processedSize;
-  UInt32 _bufferSize;
-  bool _wasFinished;
-
-  bool ReadBlock();
-  Byte ReadBlock2();
-
-public:
-  #ifdef _NO_EXCEPTIONS
-  HRESULT ErrorCode;
-  #endif
-
-  CInBuffer();
-  ~CInBuffer() { Free(); }
-
-  bool Create(UInt32 bufferSize);
-  void Free();
-  
-  void SetStream(ISequentialInStream *stream);
-  void Init();
-  void ReleaseStream() { _stream.Release(); }
-
-  bool ReadByte(Byte &b)
-  {
-    if(_buffer >= _bufferLimit)
-      if(!ReadBlock())
-        return false;
-    b = *_buffer++;
-    return true;
-  }
-  Byte ReadByte()
-  {
-    if(_buffer >= _bufferLimit)
-      return ReadBlock2();
-    return *_buffer++;
-  }
-  void ReadBytes(void *data, UInt32 size, UInt32 &processedSize)
-  {
-    for(processedSize = 0; processedSize < size; processedSize++)
-      if (!ReadByte(((Byte *)data)[processedSize]))
-        return;
-  }
-  bool ReadBytes(void *data, UInt32 size)
-  {
-    UInt32 processedSize;
-    ReadBytes(data, size, processedSize);
-    return (processedSize == size);
-  }
-  UInt64 GetProcessedSize() const { return _processedSize + (_buffer - _bufferBase); }
-  bool WasFinished() const { return _wasFinished; }
-};
-
-#endif
+// InBuffer.h
+
+#ifndef __INBUFFER_H
+#define __INBUFFER_H
+
+#include "../IStream.h"
+#include "../../Common/MyCom.h"
+
+#ifndef _NO_EXCEPTIONS
+class CInBufferException
+{
+public:
+  HRESULT ErrorCode;
+  CInBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
+};
+#endif
+
+class CInBuffer
+{
+  Byte *_buffer;
+  Byte *_bufferLimit;
+  Byte *_bufferBase;
+  CMyComPtr<ISequentialInStream> _stream;
+  UInt64 _processedSize;
+  UInt32 _bufferSize;
+  bool _wasFinished;
+
+  bool ReadBlock();
+  Byte ReadBlock2();
+
+public:
+  #ifdef _NO_EXCEPTIONS
+  HRESULT ErrorCode;
+  #endif
+
+  CInBuffer();
+  ~CInBuffer() { Free(); }
+
+  bool Create(UInt32 bufferSize);
+  void Free();
+  
+  void SetStream(ISequentialInStream *stream);
+  void Init();
+  void ReleaseStream() { _stream.Release(); }
+
+  bool ReadByte(Byte &b)
+  {
+    if(_buffer >= _bufferLimit)
+      if(!ReadBlock())
+        return false;
+    b = *_buffer++;
+    return true;
+  }
+  Byte ReadByte()
+  {
+    if(_buffer >= _bufferLimit)
+      return ReadBlock2();
+    return *_buffer++;
+  }
+  void ReadBytes(void *data, UInt32 size, UInt32 &processedSize)
+  {
+    for(processedSize = 0; processedSize < size; processedSize++)
+      if (!ReadByte(((Byte *)data)[processedSize]))
+        return;
+  }
+  bool ReadBytes(void *data, UInt32 size)
+  {
+    UInt32 processedSize;
+    ReadBytes(data, size, processedSize);
+    return (processedSize == size);
+  }
+  UInt64 GetProcessedSize() const { return _processedSize + (_buffer - _bufferBase); }
+  bool WasFinished() const { return _wasFinished; }
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,116 +1,116 @@
-// OutByte.cpp
-
-#include "StdAfx.h"
-
-#include "OutBuffer.h"
-
-#include "../../Common/Alloc.h"
-
-bool COutBuffer::Create(UInt32 bufferSize)
-{
-  const UInt32 kMinBlockSize = 1;
-  if (bufferSize < kMinBlockSize)
-    bufferSize = kMinBlockSize;
-  if (_buffer != 0 && _bufferSize == bufferSize)
-    return true;
-  Free();
-  _bufferSize = bufferSize;
-  _buffer = (Byte *)::MidAlloc(bufferSize);
-  return (_buffer != 0);
-}
-
-void COutBuffer::Free()
-{
-  ::MidFree(_buffer);
-  _buffer = 0;
-}
-
-void COutBuffer::SetStream(ISequentialOutStream *stream)
-{
-  _stream = stream;
-}
-
-void COutBuffer::Init()
-{
-  _streamPos = 0;
-  _limitPos = _bufferSize;
-  _pos = 0;
-  _processedSize = 0;
-  _overDict = false;
-  #ifdef _NO_EXCEPTIONS
-  ErrorCode = S_OK;
-  #endif
-}
-
-UInt64 COutBuffer::GetProcessedSize() const
-{ 
-  UInt64 res = _processedSize + _pos - _streamPos;
-  if (_streamPos > _pos) 
-    res += _bufferSize;
-  return res;
-}
-
-
-HRESULT COutBuffer::FlushPart()
-{
-  // _streamPos < _bufferSize
-  UInt32 size = (_streamPos >= _pos) ? (_bufferSize - _streamPos) : (_pos - _streamPos);
-  HRESULT result = S_OK;
-  #ifdef _NO_EXCEPTIONS
-  result = ErrorCode;
-  #endif
-  if (_buffer2 != 0)
-  {
-    memmove(_buffer2, _buffer + _streamPos, size);
-    _buffer2 += size;
-  }
-
-  if (_stream != 0
-      #ifdef _NO_EXCEPTIONS
-      && (ErrorCode == S_OK)
-      #endif
-     )
-  {
-    UInt32 processedSize = 0;
-    result = _stream->Write(_buffer + _streamPos, size, &processedSize);
-    size = processedSize;
-  }
-  _streamPos += size;
-  if (_streamPos == _bufferSize)
-    _streamPos = 0;
-  if (_pos == _bufferSize)
-  {
-    _overDict = true;
-    _pos = 0;
-  }
-  _limitPos = (_streamPos > _pos) ? _streamPos : _bufferSize;
-  _processedSize += size;
-  return result;
-}
-
-HRESULT COutBuffer::Flush()
-{
-  #ifdef _NO_EXCEPTIONS
-  if (ErrorCode != S_OK)
-    return ErrorCode;
-  #endif
-
-  while(_streamPos != _pos)
-  {
-    HRESULT result = FlushPart();
-    if (result != S_OK)
-      return result;
-  }
-  return S_OK;
-}
-
-void COutBuffer::FlushWithCheck()
-{
-  HRESULT result = FlushPart();
-  #ifdef _NO_EXCEPTIONS
-  ErrorCode = result;
-  #else
-  if (result != S_OK)
-    throw COutBufferException(result);
-  #endif
-}
+// OutByte.cpp
+
+#include "StdAfx.h"
+
+#include "OutBuffer.h"
+
+#include "../../Common/Alloc.h"
+
+bool COutBuffer::Create(UInt32 bufferSize)
+{
+  const UInt32 kMinBlockSize = 1;
+  if (bufferSize < kMinBlockSize)
+    bufferSize = kMinBlockSize;
+  if (_buffer != 0 && _bufferSize == bufferSize)
+    return true;
+  Free();
+  _bufferSize = bufferSize;
+  _buffer = (Byte *)::MidAlloc(bufferSize);
+  return (_buffer != 0);
+}
+
+void COutBuffer::Free()
+{
+  ::MidFree(_buffer);
+  _buffer = 0;
+}
+
+void COutBuffer::SetStream(ISequentialOutStream *stream)
+{
+  _stream = stream;
+}
+
+void COutBuffer::Init()
+{
+  _streamPos = 0;
+  _limitPos = _bufferSize;
+  _pos = 0;
+  _processedSize = 0;
+  _overDict = false;
+  #ifdef _NO_EXCEPTIONS
+  ErrorCode = S_OK;
+  #endif
+}
+
+UInt64 COutBuffer::GetProcessedSize() const
+{ 
+  UInt64 res = _processedSize + _pos - _streamPos;
+  if (_streamPos > _pos) 
+    res += _bufferSize;
+  return res;
+}
+
+
+HRESULT COutBuffer::FlushPart()
+{
+  // _streamPos < _bufferSize
+  UInt32 size = (_streamPos >= _pos) ? (_bufferSize - _streamPos) : (_pos - _streamPos);
+  HRESULT result = S_OK;
+  #ifdef _NO_EXCEPTIONS
+  result = ErrorCode;
+  #endif
+  if (_buffer2 != 0)
+  {
+    memmove(_buffer2, _buffer + _streamPos, size);
+    _buffer2 += size;
+  }
+
+  if (_stream != 0
+      #ifdef _NO_EXCEPTIONS
+      && (ErrorCode == S_OK)
+      #endif
+     )
+  {
+    UInt32 processedSize = 0;
+    result = _stream->Write(_buffer + _streamPos, size, &processedSize);
+    size = processedSize;
+  }
+  _streamPos += size;
+  if (_streamPos == _bufferSize)
+    _streamPos = 0;
+  if (_pos == _bufferSize)
+  {
+    _overDict = true;
+    _pos = 0;
+  }
+  _limitPos = (_streamPos > _pos) ? _streamPos : _bufferSize;
+  _processedSize += size;
+  return result;
+}
+
+HRESULT COutBuffer::Flush()
+{
+  #ifdef _NO_EXCEPTIONS
+  if (ErrorCode != S_OK)
+    return ErrorCode;
+  #endif
+
+  while(_streamPos != _pos)
+  {
+    HRESULT result = FlushPart();
+    if (result != S_OK)
+      return result;
+  }
+  return S_OK;
+}
+
+void COutBuffer::FlushWithCheck()
+{
+  HRESULT result = FlushPart();
+  #ifdef _NO_EXCEPTIONS
+  ErrorCode = result;
+  #else
+  if (result != S_OK)
+    throw COutBufferException(result);
+  #endif
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/OutBuffer.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,64 +1,64 @@
-// OutBuffer.h
-
-#ifndef __OUTBUFFER_H
-#define __OUTBUFFER_H
-
-#include "../IStream.h"
-#include "../../Common/MyCom.h"
-
-#ifndef _NO_EXCEPTIONS
-struct COutBufferException
-{
-  HRESULT ErrorCode;
-  COutBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
-};
-#endif
-
-class COutBuffer
-{
-protected:
-  Byte *_buffer;
-  UInt32 _pos;
-  UInt32 _limitPos;
-  UInt32 _streamPos;
-  UInt32 _bufferSize;
-  CMyComPtr<ISequentialOutStream> _stream;
-  UInt64 _processedSize;
-  Byte  *_buffer2;
-  bool _overDict;
-
-  HRESULT FlushPart();
-  void FlushWithCheck();
-public:
-  #ifdef _NO_EXCEPTIONS
-  HRESULT ErrorCode;
-  #endif
-
-  COutBuffer(): _buffer(0), _pos(0), _stream(0), _buffer2(0) {}
-  ~COutBuffer() { Free(); }
-  
-  bool Create(UInt32 bufferSize);
-  void Free();
-
-  void SetMemStream(Byte *buffer) { _buffer2 = buffer; }
-  void SetStream(ISequentialOutStream *stream);
-  void Init();
-  HRESULT Flush();
-  void ReleaseStream() {  _stream.Release(); }
-
-  void WriteByte(Byte b)
-  {
-    _buffer[_pos++] = b;
-    if(_pos == _limitPos)
-      FlushWithCheck();
-  }
-  void WriteBytes(const void *data, size_t size)
-  {
-    for (size_t i = 0; i < size; i++)
-      WriteByte(((const Byte *)data)[i]);
-  }
-
-  UInt64 GetProcessedSize() const;
-};
-
-#endif
+// OutBuffer.h
+
+#ifndef __OUTBUFFER_H
+#define __OUTBUFFER_H
+
+#include "../IStream.h"
+#include "../../Common/MyCom.h"
+
+#ifndef _NO_EXCEPTIONS
+struct COutBufferException
+{
+  HRESULT ErrorCode;
+  COutBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
+};
+#endif
+
+class COutBuffer
+{
+protected:
+  Byte *_buffer;
+  UInt32 _pos;
+  UInt32 _limitPos;
+  UInt32 _streamPos;
+  UInt32 _bufferSize;
+  CMyComPtr<ISequentialOutStream> _stream;
+  UInt64 _processedSize;
+  Byte  *_buffer2;
+  bool _overDict;
+
+  HRESULT FlushPart();
+  void FlushWithCheck();
+public:
+  #ifdef _NO_EXCEPTIONS
+  HRESULT ErrorCode;
+  #endif
+
+  COutBuffer(): _buffer(0), _pos(0), _stream(0), _buffer2(0) {}
+  ~COutBuffer() { Free(); }
+  
+  bool Create(UInt32 bufferSize);
+  void Free();
+
+  void SetMemStream(Byte *buffer) { _buffer2 = buffer; }
+  void SetStream(ISequentialOutStream *stream);
+  void Init();
+  HRESULT Flush();
+  void ReleaseStream() {  _stream.Release(); }
+
+  void WriteByte(Byte b)
+  {
+    _buffer[_pos++] = b;
+    if(_pos == _limitPos)
+      FlushWithCheck();
+  }
+  void WriteBytes(const void *data, size_t size)
+  {
+    for (size_t i = 0; i < size; i++)
+      WriteByte(((const Byte *)data)[i]);
+  }
+
+  UInt64 GetProcessedSize() const;
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StdAfx.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StdAfx.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StdAfx.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,9 +1,9 @@
-// StdAfx.h
-
-#ifndef __STDAFX_H
-#define __STDAFX_H
-
-#include "../../Common/MyWindows.h"
-#include "../../Common/NewHandler.h"
-
-#endif 
+// StdAfx.h
+
+#ifndef __STDAFX_H
+#define __STDAFX_H
+
+#include "../../Common/MyWindows.h"
+#include "../../Common/NewHandler.h"
+
+#endif 

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,44 +1,44 @@
-// StreamUtils.cpp
-
-#include "StdAfx.h"
-
-#include "../../Common/MyCom.h"
-#include "StreamUtils.h"
-
-HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize)
-{
-  if (processedSize != 0)
-    *processedSize = 0;
-  while(size != 0)
-  {
-    UInt32 processedSizeLoc; 
-    HRESULT res = stream->Read(data, size, &processedSizeLoc);
-    if (processedSize != 0)
-      *processedSize += processedSizeLoc;
-    data = (Byte *)((Byte *)data + processedSizeLoc);
-    size -= processedSizeLoc;
-    RINOK(res);
-    if (processedSizeLoc == 0)
-      return S_OK;
-  }
-  return S_OK;
-}
-
-HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize)
-{
-  if (processedSize != 0)
-    *processedSize = 0;
-  while(size != 0)
-  {
-    UInt32 processedSizeLoc; 
-    HRESULT res = stream->Write(data, size, &processedSizeLoc);
-    if (processedSize != 0)
-      *processedSize += processedSizeLoc;
-    data = (const void *)((const Byte *)data + processedSizeLoc);
-    size -= processedSizeLoc;
-    RINOK(res);
-    if (processedSizeLoc == 0)
-      break;
-  }
-  return S_OK;
-}
+// StreamUtils.cpp
+
+#include "StdAfx.h"
+
+#include "../../Common/MyCom.h"
+#include "StreamUtils.h"
+
+HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize)
+{
+  if (processedSize != 0)
+    *processedSize = 0;
+  while(size != 0)
+  {
+    UInt32 processedSizeLoc; 
+    HRESULT res = stream->Read(data, size, &processedSizeLoc);
+    if (processedSize != 0)
+      *processedSize += processedSizeLoc;
+    data = (Byte *)((Byte *)data + processedSizeLoc);
+    size -= processedSizeLoc;
+    RINOK(res);
+    if (processedSizeLoc == 0)
+      return S_OK;
+  }
+  return S_OK;
+}
+
+HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize)
+{
+  if (processedSize != 0)
+    *processedSize = 0;
+  while(size != 0)
+  {
+    UInt32 processedSizeLoc; 
+    HRESULT res = stream->Write(data, size, &processedSizeLoc);
+    if (processedSize != 0)
+      *processedSize += processedSizeLoc;
+    data = (const void *)((const Byte *)data + processedSizeLoc);
+    size -= processedSizeLoc;
+    RINOK(res);
+    if (processedSizeLoc == 0)
+      break;
+  }
+  return S_OK;
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Common/StreamUtils.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,11 +1,11 @@
-// StreamUtils.h
-
-#ifndef __STREAMUTILS_H
-#define __STREAMUTILS_H
-
-#include "../IStream.h"
-
-HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize);
-HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize);
-
-#endif
+// StreamUtils.h
+
+#ifndef __STREAMUTILS_H
+#define __STREAMUTILS_H
+
+#include "../IStream.h"
+
+HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize);
+HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize);
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,54 +1,54 @@
-// BinTree.h
-
-#include "../LZInWindow.h"
-#include "../IMatchFinder.h"
- 
-namespace BT_NAMESPACE {
-
-typedef UInt32 CIndex;
-const UInt32 kMaxValForNormalize = (UInt32(1) << 31) - 1;
-
-class CMatchFinder: 
-  public IMatchFinder,
-  public CLZInWindow,
-  public CMyUnknownImp,
-  public IMatchFinderSetNumPasses
-{
-  UInt32 _cyclicBufferPos;
-  UInt32 _cyclicBufferSize; // it must be historySize + 1
-  UInt32 _matchMaxLen;
-  CIndex *_hash;
-  CIndex *_son;
-  UInt32 _hashMask;
-  UInt32 _cutValue;
-  UInt32 _hashSizeSum;
-
-  void Normalize();
-  void FreeThisClassMemory();
-  void FreeMemory();
-
-  MY_UNKNOWN_IMP
-
-  STDMETHOD(SetStream)(ISequentialInStream *inStream);
-  STDMETHOD_(void, ReleaseStream)();
-  STDMETHOD(Init)();
-  HRESULT MovePos();
-  STDMETHOD_(Byte, GetIndexByte)(Int32 index);
-  STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 back, UInt32 limit);
-  STDMETHOD_(UInt32, GetNumAvailableBytes)();
-  STDMETHOD_(const Byte *, GetPointerToCurrentPos)();
-  STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes);
-  STDMETHOD_(void, ChangeBufferPos)();
-
-  STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore, 
-      UInt32 matchMaxLen, UInt32 keepAddBufferAfter);
-  STDMETHOD(GetMatches)(UInt32 *distances);
-  STDMETHOD(Skip)(UInt32 num);
-
-public:
-  CMatchFinder();
-  virtual ~CMatchFinder();
-  virtual void SetNumPasses(UInt32 numPasses) { _cutValue = numPasses; }
-};
-
-}
+// BinTree.h
+
+#include "../LZInWindow.h"
+#include "../IMatchFinder.h"
+ 
+namespace BT_NAMESPACE {
+
+typedef UInt32 CIndex;
+const UInt32 kMaxValForNormalize = (UInt32(1) << 31) - 1;
+
+class CMatchFinder: 
+  public IMatchFinder,
+  public CLZInWindow,
+  public CMyUnknownImp,
+  public IMatchFinderSetNumPasses
+{
+  UInt32 _cyclicBufferPos;
+  UInt32 _cyclicBufferSize; // it must be historySize + 1
+  UInt32 _matchMaxLen;
+  CIndex *_hash;
+  CIndex *_son;
+  UInt32 _hashMask;
+  UInt32 _cutValue;
+  UInt32 _hashSizeSum;
+
+  void Normalize();
+  void FreeThisClassMemory();
+  void FreeMemory();
+
+  MY_UNKNOWN_IMP
+
+  STDMETHOD(SetStream)(ISequentialInStream *inStream);
+  STDMETHOD_(void, ReleaseStream)();
+  STDMETHOD(Init)();
+  HRESULT MovePos();
+  STDMETHOD_(Byte, GetIndexByte)(Int32 index);
+  STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 back, UInt32 limit);
+  STDMETHOD_(UInt32, GetNumAvailableBytes)();
+  STDMETHOD_(const Byte *, GetPointerToCurrentPos)();
+  STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes);
+  STDMETHOD_(void, ChangeBufferPos)();
+
+  STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore, 
+      UInt32 matchMaxLen, UInt32 keepAddBufferAfter);
+  STDMETHOD(GetMatches)(UInt32 *distances);
+  STDMETHOD(Skip)(UInt32 num);
+
+public:
+  CMatchFinder();
+  virtual ~CMatchFinder();
+  virtual void SetNumPasses(UInt32 numPasses) { _cutValue = numPasses; }
+};
+
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree2.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree2.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree2.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,12 +1,12 @@
-// BinTree2.h
-
-#ifndef __BINTREE2_H
-#define __BINTREE2_H
-
-#define BT_NAMESPACE NBT2
-
-#include "BinTreeMain.h"
-
-#undef BT_NAMESPACE
-
-#endif
+// BinTree2.h
+
+#ifndef __BINTREE2_H
+#define __BINTREE2_H
+
+#define BT_NAMESPACE NBT2
+
+#include "BinTreeMain.h"
+
+#undef BT_NAMESPACE
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree3.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree3.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree3.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,16 +1,16 @@
-// BinTree3.h
-
-#ifndef __BINTREE3_H
-#define __BINTREE3_H
-
-#define BT_NAMESPACE NBT3
-
-#define HASH_ARRAY_2
-
-#include "BinTreeMain.h"
-
-#undef HASH_ARRAY_2
-
-#undef BT_NAMESPACE
-
-#endif
+// BinTree3.h
+
+#ifndef __BINTREE3_H
+#define __BINTREE3_H
+
+#define BT_NAMESPACE NBT3
+
+#define HASH_ARRAY_2
+
+#include "BinTreeMain.h"
+
+#undef HASH_ARRAY_2
+
+#undef BT_NAMESPACE
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree4.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree4.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTree4.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,18 +1,18 @@
-// BinTree4.h
-
-#ifndef __BINTREE4_H
-#define __BINTREE4_H
-
-#define BT_NAMESPACE NBT4
-
-#define HASH_ARRAY_2
-#define HASH_ARRAY_3
-
-#include "BinTreeMain.h"
-
-#undef HASH_ARRAY_2
-#undef HASH_ARRAY_3
-
-#undef BT_NAMESPACE
-
-#endif
+// BinTree4.h
+
+#ifndef __BINTREE4_H
+#define __BINTREE4_H
+
+#define BT_NAMESPACE NBT4
+
+#define HASH_ARRAY_2
+#define HASH_ARRAY_3
+
+#include "BinTreeMain.h"
+
+#undef HASH_ARRAY_2
+#undef HASH_ARRAY_3
+
+#undef BT_NAMESPACE
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTreeMain.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTreeMain.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/BinTree/BinTreeMain.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,531 +1,531 @@
-// BinTreeMain.h
-
-#include "../../../../Common/Defs.h"
-#include "../../../../Common/CRC.h"
-#include "../../../../Common/Alloc.h"
-
-#include "BinTree.h"
-
-// #include <xmmintrin.h>
-// It's for prefetch
-// But prefetch doesn't give big gain in K8.
-
-namespace BT_NAMESPACE {
-
-#ifdef HASH_ARRAY_2
-  static const UInt32 kHash2Size = 1 << 10;
-  #define kNumHashDirectBytes 0
-  #ifdef HASH_ARRAY_3
-    static const UInt32 kNumHashBytes = 4;
-    static const UInt32 kHash3Size = 1 << 16;
-  #else
-    static const UInt32 kNumHashBytes = 3;
-  #endif
-  static const UInt32 kHashSize = 0;
-  static const UInt32 kMinMatchCheck = kNumHashBytes;
-  static const UInt32 kStartMaxLen = 1;
-#else
-  #ifdef HASH_ZIP 
-    #define kNumHashDirectBytes 0
-    static const UInt32 kNumHashBytes = 3;
-    static const UInt32 kHashSize = 1 << 16;
-    static const UInt32 kMinMatchCheck = kNumHashBytes;
-    static const UInt32 kStartMaxLen = 1;
-  #else
-    #define kNumHashDirectBytes 2
-    static const UInt32 kNumHashBytes = 2;
-    static const UInt32 kHashSize = 1 << (8 * kNumHashBytes);
-    static const UInt32 kMinMatchCheck = kNumHashBytes + 1;
-    static const UInt32 kStartMaxLen = 1;
-  #endif
-#endif
-
-#ifdef HASH_ARRAY_2
-#ifdef HASH_ARRAY_3
-static const UInt32 kHash3Offset = kHash2Size;
-#endif
-#endif
-
-static const UInt32 kFixHashSize = 0
-    #ifdef HASH_ARRAY_2
-    + kHash2Size
-    #ifdef HASH_ARRAY_3
-    + kHash3Size
-    #endif
-    #endif
-    ;
-
-CMatchFinder::CMatchFinder():
-  _hash(0)
-{
-}
-
-void CMatchFinder::FreeThisClassMemory()
-{
-  BigFree(_hash);
-  _hash = 0;
-}
-
-void CMatchFinder::FreeMemory()
-{
-  FreeThisClassMemory();
-  CLZInWindow::Free();
-}
-
-CMatchFinder::~CMatchFinder()
-{ 
-  FreeMemory();
-}
-
-STDMETHODIMP CMatchFinder::Create(UInt32 historySize, UInt32 keepAddBufferBefore, 
-    UInt32 matchMaxLen, UInt32 keepAddBufferAfter)
-{
-  if (historySize > kMaxValForNormalize - 256)
-  {
-    FreeMemory();
-    return E_INVALIDARG;
-  }
-  _cutValue = 
-  #ifdef _HASH_CHAIN
-    8 + (matchMaxLen >> 2);
-  #else
-    16 + (matchMaxLen >> 1);
-  #endif
-  UInt32 sizeReserv = (historySize + keepAddBufferBefore + 
-      matchMaxLen + keepAddBufferAfter) / 2 + 256;
-  if (CLZInWindow::Create(historySize + keepAddBufferBefore, 
-      matchMaxLen + keepAddBufferAfter, sizeReserv))
-  {
-    _matchMaxLen = matchMaxLen;
-    UInt32 newCyclicBufferSize = historySize + 1;
-    if (_hash != 0 && newCyclicBufferSize == _cyclicBufferSize)
-      return S_OK;
-    FreeThisClassMemory();
-    _cyclicBufferSize = newCyclicBufferSize; // don't change it
-
-    UInt32 hs = kHashSize;
-
-    #ifdef HASH_ARRAY_2
-    hs = historySize - 1;
-    hs |= (hs >> 1);
-    hs |= (hs >> 2);
-    hs |= (hs >> 4);
-    hs |= (hs >> 8);
-    hs >>= 1;
-    hs |= 0xFFFF;
-    if (hs > (1 << 24))
-    {
-      #ifdef HASH_ARRAY_3
-      hs >>= 1;
-      #else
-      hs = (1 << 24) - 1;
-      #endif
-    }
-    _hashMask = hs;
-    hs++;
-    #endif
-    _hashSizeSum = hs + kFixHashSize;
-    UInt32 numItems = _hashSizeSum + _cyclicBufferSize
-    #ifndef _HASH_CHAIN
-     * 2
-    #endif
-    ;
-    size_t sizeInBytes = (size_t)numItems * sizeof(CIndex);
-    if (sizeInBytes / sizeof(CIndex) != numItems)
-      return E_OUTOFMEMORY;
-    _hash = (CIndex *)BigAlloc(sizeInBytes);
-    _son = _hash + _hashSizeSum;
-    if (_hash != 0)
-      return S_OK;
-  }
-  FreeMemory();
-  return E_OUTOFMEMORY;
-}
-
-static const UInt32 kEmptyHashValue = 0;
-
-STDMETHODIMP CMatchFinder::SetStream(ISequentialInStream *stream)
-{
-  CLZInWindow::SetStream(stream);
-  return S_OK;
-}
-
-STDMETHODIMP CMatchFinder::Init()
-{
-  RINOK(CLZInWindow::Init());
-  for(UInt32 i = 0; i < _hashSizeSum; i++)
-    _hash[i] = kEmptyHashValue;
-  _cyclicBufferPos = 0;
-  ReduceOffsets(-1);
-  return S_OK;
-}
-
-STDMETHODIMP_(void) CMatchFinder::ReleaseStream()
-{ 
-  // ReleaseStream(); 
-}
-
-#ifdef HASH_ARRAY_2
-#ifdef HASH_ARRAY_3
-
-#define HASH_CALC { \
-  UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
-  hash2Value = temp & (kHash2Size - 1); \
-  hash3Value = (temp ^ (UInt32(cur[2]) << 8)) & (kHash3Size - 1); \
-  hashValue = (temp ^ (UInt32(cur[2]) << 8) ^ (CCRC::Table[cur[3]] << 5)) & _hashMask; }
-  
-#else // no HASH_ARRAY_3
-#define HASH_CALC { \
-  UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
-  hash2Value = temp & (kHash2Size - 1); \
-  hashValue = (temp ^ (UInt32(cur[2]) << 8)) & _hashMask; }
-#endif // HASH_ARRAY_3
-#else // no HASH_ARRAY_2
-#ifdef HASH_ZIP 
-inline UInt32 Hash(const Byte *pointer)
-{
-  return ((UInt32(pointer[0]) << 8) ^ CCRC::Table[pointer[1]] ^ pointer[2]) & (kHashSize - 1);
-}
-#else // no HASH_ZIP 
-inline UInt32 Hash(const Byte *pointer)
-{
-  return pointer[0] ^ (UInt32(pointer[1]) << 8);
-}
-#endif // HASH_ZIP
-#endif // HASH_ARRAY_2
-
-STDMETHODIMP CMatchFinder::GetMatches(UInt32 *distances)
-{
-  UInt32 lenLimit;
-  if (_pos + _matchMaxLen <= _streamPos)
-    lenLimit = _matchMaxLen;
-  else
-  {
-    lenLimit = _streamPos - _pos;
-    if(lenLimit < kMinMatchCheck)
-    {
-      distances[0] = 0;
-      return MovePos(); 
-    }
-  }
-
-  int offset = 1;
-
-  UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
-  const Byte *cur = _buffer + _pos;
-
-  UInt32 maxLen = kStartMaxLen; // to avoid items for len < hashSize;
-
-  #ifdef HASH_ARRAY_2
-  UInt32 hash2Value;
-  #ifdef HASH_ARRAY_3
-  UInt32 hash3Value;
-  #endif
-  UInt32 hashValue;
-  HASH_CALC;
-  #else
-  UInt32 hashValue = Hash(cur);
-  #endif
-
-  UInt32 curMatch = _hash[kFixHashSize + hashValue];
-  #ifdef HASH_ARRAY_2
-  UInt32 curMatch2 = _hash[hash2Value];
-  #ifdef HASH_ARRAY_3
-  UInt32 curMatch3 = _hash[kHash3Offset + hash3Value];
-  #endif
-  _hash[hash2Value] = _pos;
-  if(curMatch2 > matchMinPos)
-    if (_buffer[curMatch2] == cur[0])
-    {
-      distances[offset++] = maxLen = 2;
-      distances[offset++] = _pos - curMatch2 - 1;
-    }
-
-  #ifdef HASH_ARRAY_3
-  _hash[kHash3Offset + hash3Value] = _pos;
-  if(curMatch3 > matchMinPos)
-    if (_buffer[curMatch3] == cur[0])
-    {
-      if (curMatch3 == curMatch2)
-        offset -= 2;
-      distances[offset++] = maxLen = 3;
-      distances[offset++] = _pos - curMatch3 - 1;
-      curMatch2 = curMatch3;
-    }
-  #endif
-  if (offset != 1 && curMatch2 == curMatch)
-  {
-    offset -= 2;
-    maxLen = kStartMaxLen;
-  }
-  #endif
-
-  _hash[kFixHashSize + hashValue] = _pos;
-
-  CIndex *son = _son;
-
-  #ifdef _HASH_CHAIN
-  son[_cyclicBufferPos] = curMatch;
-  #else
-  CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
-  CIndex *ptr1 = son + (_cyclicBufferPos << 1);
-
-  UInt32 len0, len1;
-  len0 = len1 = kNumHashDirectBytes;
-  #endif
-
-  #if kNumHashDirectBytes != 0
-  if(curMatch > matchMinPos)
-  {
-    if (_buffer[curMatch + kNumHashDirectBytes] != cur[kNumHashDirectBytes])
-    {
-      distances[offset++] = maxLen = kNumHashDirectBytes;
-      distances[offset++] = _pos - curMatch - 1;
-    }
-  }
-  #endif
-  UInt32 count = _cutValue;
-  while(true)
-  {
-    if(curMatch <= matchMinPos || count-- == 0)
-    {
-      #ifndef _HASH_CHAIN
-      *ptr0 = *ptr1 = kEmptyHashValue;
-      #endif
-      break;
-    }
-    UInt32 delta = _pos - curMatch;
-    UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
-        (_cyclicBufferPos - delta):
-        (_cyclicBufferPos - delta + _cyclicBufferSize);
-    CIndex *pair = son + 
-    #ifdef _HASH_CHAIN
-      cyclicPos;
-    #else
-      (cyclicPos << 1);
-    #endif
-    
-    // _mm_prefetch((const char *)pair, _MM_HINT_T0);
-    
-    const Byte *pb = _buffer + curMatch;
-    UInt32 len = 
-    #ifdef _HASH_CHAIN
-    kNumHashDirectBytes;
-    if (pb[maxLen] == cur[maxLen])
-    #else
-    MyMin(len0, len1);
-    #endif
-    if (pb[len] == cur[len])
-    {
-      while(++len != lenLimit)
-        if (pb[len] != cur[len])
-          break;
-      if (maxLen < len)
-      {
-        distances[offset++] = maxLen = len;
-        distances[offset++] = delta - 1;
-        if (len == lenLimit)
-        {
-          #ifndef _HASH_CHAIN
-          *ptr1 = pair[0];
-          *ptr0 = pair[1];
-          #endif
-          break;
-        }
-      }
-    }
-    #ifdef _HASH_CHAIN
-    curMatch = *pair;
-    #else
-    if (pb[len] < cur[len])
-    {
-      *ptr1 = curMatch;
-      ptr1 = pair + 1;
-      curMatch = *ptr1;
-      len1 = len;
-    }
-    else
-    {
-      *ptr0 = curMatch;
-      ptr0 = pair;
-      curMatch = *ptr0;
-      len0 = len;
-    }
-    #endif
-  }
-  distances[0] = offset - 1;
-  if (++_cyclicBufferPos == _cyclicBufferSize)
-    _cyclicBufferPos = 0;
-  RINOK(CLZInWindow::MovePos());
-  if (_pos == kMaxValForNormalize)
-    Normalize();
-  return S_OK;
-}
-
-STDMETHODIMP CMatchFinder::Skip(UInt32 num)
-{
-  do
-  {
-  #ifdef _HASH_CHAIN
-  if (_streamPos - _pos < kNumHashBytes)
-  {
-    RINOK(MovePos()); 
-    continue;
-  }
-  #else
-  UInt32 lenLimit;
-  if (_pos + _matchMaxLen <= _streamPos)
-    lenLimit = _matchMaxLen;
-  else
-  {
-    lenLimit = _streamPos - _pos;
-    if(lenLimit < kMinMatchCheck)
-    {
-      RINOK(MovePos());
-      continue;
-    }
-  }
-  UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
-  #endif
-  const Byte *cur = _buffer + _pos;
-
-  #ifdef HASH_ARRAY_2
-  UInt32 hash2Value;
-  #ifdef HASH_ARRAY_3
-  UInt32 hash3Value;
-  UInt32 hashValue;
-  HASH_CALC;
-  _hash[kHash3Offset + hash3Value] = _pos;
-  #else
-  UInt32 hashValue;
-  HASH_CALC;
-  #endif
-  _hash[hash2Value] = _pos;
-  #else
-  UInt32 hashValue = Hash(cur);
-  #endif
-
-  UInt32 curMatch = _hash[kFixHashSize + hashValue];
-  _hash[kFixHashSize + hashValue] = _pos;
-
-  #ifdef _HASH_CHAIN
-  _son[_cyclicBufferPos] = curMatch;
-  #else
-  CIndex *son = _son;
-  CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
-  CIndex *ptr1 = son + (_cyclicBufferPos << 1);
-
-  UInt32 len0, len1;
-  len0 = len1 = kNumHashDirectBytes;
-  UInt32 count = _cutValue;
-  while(true)
-  {
-    if(curMatch <= matchMinPos || count-- == 0)
-    {
-      *ptr0 = *ptr1 = kEmptyHashValue;
-      break;
-    }
-    
-    UInt32 delta = _pos - curMatch;
-    UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
-      (_cyclicBufferPos - delta):
-      (_cyclicBufferPos - delta + _cyclicBufferSize);
-    CIndex *pair = son + (cyclicPos << 1);
-    
-    // _mm_prefetch((const char *)pair, _MM_HINT_T0);
-    
-    const Byte *pb = _buffer + curMatch;
-    UInt32 len = MyMin(len0, len1);
-    
-    if (pb[len] == cur[len])
-    {
-      while(++len != lenLimit)
-        if (pb[len] != cur[len])
-          break;
-      if (len == lenLimit)
-      {
-        *ptr1 = pair[0];
-        *ptr0 = pair[1];
-        break;
-      }
-    }
-    if (pb[len] < cur[len])
-    {
-      *ptr1 = curMatch;
-      ptr1 = pair + 1;
-      curMatch = *ptr1;
-      len1 = len;
-    }
-    else
-    {
-      *ptr0 = curMatch;
-      ptr0 = pair;
-      curMatch = *ptr0;
-      len0 = len;
-    }
-  }
-  #endif
-  if (++_cyclicBufferPos == _cyclicBufferSize)
-    _cyclicBufferPos = 0;
-  RINOK(CLZInWindow::MovePos());
-  if (_pos == kMaxValForNormalize)
-    Normalize();
-  }
-  while(--num != 0);
-  return S_OK;
-}
-
-void CMatchFinder::Normalize()
-{
-  UInt32 subValue = _pos - _cyclicBufferSize;
-  CIndex *items = _hash;
-  UInt32 numItems = (_hashSizeSum + _cyclicBufferSize 
-    #ifndef _HASH_CHAIN
-     * 2
-    #endif
-    );
-  for (UInt32 i = 0; i < numItems; i++)
-  {
-    UInt32 value = items[i];
-    if (value <= subValue)
-      value = kEmptyHashValue;
-    else
-      value -= subValue;
-    items[i] = value;
-  }
-  ReduceOffsets(subValue);
-}
-
-HRESULT CMatchFinder::MovePos()
-{
-  if (++_cyclicBufferPos == _cyclicBufferSize)
-    _cyclicBufferPos = 0;
-  RINOK(CLZInWindow::MovePos());
-  if (_pos == kMaxValForNormalize)
-    Normalize();
-  return S_OK;
-}
-
-STDMETHODIMP_(Byte) CMatchFinder::GetIndexByte(Int32 index)
-  { return CLZInWindow::GetIndexByte(index); }
-
-STDMETHODIMP_(UInt32) CMatchFinder::GetMatchLen(Int32 index, 
-    UInt32 back, UInt32 limit)
-  { return CLZInWindow::GetMatchLen(index, back, limit); }
-
-STDMETHODIMP_(UInt32) CMatchFinder::GetNumAvailableBytes()
-  { return CLZInWindow::GetNumAvailableBytes(); }
-
-STDMETHODIMP_(const Byte *) CMatchFinder::GetPointerToCurrentPos()
-  { return CLZInWindow::GetPointerToCurrentPos(); }
-
-STDMETHODIMP_(Int32) CMatchFinder::NeedChangeBufferPos(UInt32 numCheckBytes)
-  { return CLZInWindow::NeedMove(numCheckBytes) ? 1: 0; }
-
-STDMETHODIMP_(void) CMatchFinder::ChangeBufferPos()
-  { CLZInWindow::MoveBlock();}
-
-#undef HASH_CALC
-#undef kNumHashDirectBytes
- 
-}
+// BinTreeMain.h
+
+#include "../../../../Common/Defs.h"
+#include "../../../../Common/CRC.h"
+#include "../../../../Common/Alloc.h"
+
+#include "BinTree.h"
+
+// #include <xmmintrin.h>
+// It's for prefetch
+// But prefetch doesn't give big gain in K8.
+
+namespace BT_NAMESPACE {
+
+#ifdef HASH_ARRAY_2
+  static const UInt32 kHash2Size = 1 << 10;
+  #define kNumHashDirectBytes 0
+  #ifdef HASH_ARRAY_3
+    static const UInt32 kNumHashBytes = 4;
+    static const UInt32 kHash3Size = 1 << 16;
+  #else
+    static const UInt32 kNumHashBytes = 3;
+  #endif
+  static const UInt32 kHashSize = 0;
+  static const UInt32 kMinMatchCheck = kNumHashBytes;
+  static const UInt32 kStartMaxLen = 1;
+#else
+  #ifdef HASH_ZIP 
+    #define kNumHashDirectBytes 0
+    static const UInt32 kNumHashBytes = 3;
+    static const UInt32 kHashSize = 1 << 16;
+    static const UInt32 kMinMatchCheck = kNumHashBytes;
+    static const UInt32 kStartMaxLen = 1;
+  #else
+    #define kNumHashDirectBytes 2
+    static const UInt32 kNumHashBytes = 2;
+    static const UInt32 kHashSize = 1 << (8 * kNumHashBytes);
+    static const UInt32 kMinMatchCheck = kNumHashBytes + 1;
+    static const UInt32 kStartMaxLen = 1;
+  #endif
+#endif
+
+#ifdef HASH_ARRAY_2
+#ifdef HASH_ARRAY_3
+static const UInt32 kHash3Offset = kHash2Size;
+#endif
+#endif
+
+static const UInt32 kFixHashSize = 0
+    #ifdef HASH_ARRAY_2
+    + kHash2Size
+    #ifdef HASH_ARRAY_3
+    + kHash3Size
+    #endif
+    #endif
+    ;
+
+CMatchFinder::CMatchFinder():
+  _hash(0)
+{
+}
+
+void CMatchFinder::FreeThisClassMemory()
+{
+  BigFree(_hash);
+  _hash = 0;
+}
+
+void CMatchFinder::FreeMemory()
+{
+  FreeThisClassMemory();
+  CLZInWindow::Free();
+}
+
+CMatchFinder::~CMatchFinder()
+{ 
+  FreeMemory();
+}
+
+STDMETHODIMP CMatchFinder::Create(UInt32 historySize, UInt32 keepAddBufferBefore, 
+    UInt32 matchMaxLen, UInt32 keepAddBufferAfter)
+{
+  if (historySize > kMaxValForNormalize - 256)
+  {
+    FreeMemory();
+    return E_INVALIDARG;
+  }
+  _cutValue = 
+  #ifdef _HASH_CHAIN
+    8 + (matchMaxLen >> 2);
+  #else
+    16 + (matchMaxLen >> 1);
+  #endif
+  UInt32 sizeReserv = (historySize + keepAddBufferBefore + 
+      matchMaxLen + keepAddBufferAfter) / 2 + 256;
+  if (CLZInWindow::Create(historySize + keepAddBufferBefore, 
+      matchMaxLen + keepAddBufferAfter, sizeReserv))
+  {
+    _matchMaxLen = matchMaxLen;
+    UInt32 newCyclicBufferSize = historySize + 1;
+    if (_hash != 0 && newCyclicBufferSize == _cyclicBufferSize)
+      return S_OK;
+    FreeThisClassMemory();
+    _cyclicBufferSize = newCyclicBufferSize; // don't change it
+
+    UInt32 hs = kHashSize;
+
+    #ifdef HASH_ARRAY_2
+    hs = historySize - 1;
+    hs |= (hs >> 1);
+    hs |= (hs >> 2);
+    hs |= (hs >> 4);
+    hs |= (hs >> 8);
+    hs >>= 1;
+    hs |= 0xFFFF;
+    if (hs > (1 << 24))
+    {
+      #ifdef HASH_ARRAY_3
+      hs >>= 1;
+      #else
+      hs = (1 << 24) - 1;
+      #endif
+    }
+    _hashMask = hs;
+    hs++;
+    #endif
+    _hashSizeSum = hs + kFixHashSize;
+    UInt32 numItems = _hashSizeSum + _cyclicBufferSize
+    #ifndef _HASH_CHAIN
+     * 2
+    #endif
+    ;
+    size_t sizeInBytes = (size_t)numItems * sizeof(CIndex);
+    if (sizeInBytes / sizeof(CIndex) != numItems)
+      return E_OUTOFMEMORY;
+    _hash = (CIndex *)BigAlloc(sizeInBytes);
+    _son = _hash + _hashSizeSum;
+    if (_hash != 0)
+      return S_OK;
+  }
+  FreeMemory();
+  return E_OUTOFMEMORY;
+}
+
+static const UInt32 kEmptyHashValue = 0;
+
+STDMETHODIMP CMatchFinder::SetStream(ISequentialInStream *stream)
+{
+  CLZInWindow::SetStream(stream);
+  return S_OK;
+}
+
+STDMETHODIMP CMatchFinder::Init()
+{
+  RINOK(CLZInWindow::Init());
+  for(UInt32 i = 0; i < _hashSizeSum; i++)
+    _hash[i] = kEmptyHashValue;
+  _cyclicBufferPos = 0;
+  ReduceOffsets(-1);
+  return S_OK;
+}
+
+STDMETHODIMP_(void) CMatchFinder::ReleaseStream()
+{ 
+  // ReleaseStream(); 
+}
+
+#ifdef HASH_ARRAY_2
+#ifdef HASH_ARRAY_3
+
+#define HASH_CALC { \
+  UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
+  hash2Value = temp & (kHash2Size - 1); \
+  hash3Value = (temp ^ (UInt32(cur[2]) << 8)) & (kHash3Size - 1); \
+  hashValue = (temp ^ (UInt32(cur[2]) << 8) ^ (CCRC::Table[cur[3]] << 5)) & _hashMask; }
+  
+#else // no HASH_ARRAY_3
+#define HASH_CALC { \
+  UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
+  hash2Value = temp & (kHash2Size - 1); \
+  hashValue = (temp ^ (UInt32(cur[2]) << 8)) & _hashMask; }
+#endif // HASH_ARRAY_3
+#else // no HASH_ARRAY_2
+#ifdef HASH_ZIP 
+inline UInt32 Hash(const Byte *pointer)
+{
+  return ((UInt32(pointer[0]) << 8) ^ CCRC::Table[pointer[1]] ^ pointer[2]) & (kHashSize - 1);
+}
+#else // no HASH_ZIP 
+inline UInt32 Hash(const Byte *pointer)
+{
+  return pointer[0] ^ (UInt32(pointer[1]) << 8);
+}
+#endif // HASH_ZIP
+#endif // HASH_ARRAY_2
+
+STDMETHODIMP CMatchFinder::GetMatches(UInt32 *distances)
+{
+  UInt32 lenLimit;
+  if (_pos + _matchMaxLen <= _streamPos)
+    lenLimit = _matchMaxLen;
+  else
+  {
+    lenLimit = _streamPos - _pos;
+    if(lenLimit < kMinMatchCheck)
+    {
+      distances[0] = 0;
+      return MovePos(); 
+    }
+  }
+
+  int offset = 1;
+
+  UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
+  const Byte *cur = _buffer + _pos;
+
+  UInt32 maxLen = kStartMaxLen; // to avoid items for len < hashSize;
+
+  #ifdef HASH_ARRAY_2
+  UInt32 hash2Value;
+  #ifdef HASH_ARRAY_3
+  UInt32 hash3Value;
+  #endif
+  UInt32 hashValue;
+  HASH_CALC;
+  #else
+  UInt32 hashValue = Hash(cur);
+  #endif
+
+  UInt32 curMatch = _hash[kFixHashSize + hashValue];
+  #ifdef HASH_ARRAY_2
+  UInt32 curMatch2 = _hash[hash2Value];
+  #ifdef HASH_ARRAY_3
+  UInt32 curMatch3 = _hash[kHash3Offset + hash3Value];
+  #endif
+  _hash[hash2Value] = _pos;
+  if(curMatch2 > matchMinPos)
+    if (_buffer[curMatch2] == cur[0])
+    {
+      distances[offset++] = maxLen = 2;
+      distances[offset++] = _pos - curMatch2 - 1;
+    }
+
+  #ifdef HASH_ARRAY_3
+  _hash[kHash3Offset + hash3Value] = _pos;
+  if(curMatch3 > matchMinPos)
+    if (_buffer[curMatch3] == cur[0])
+    {
+      if (curMatch3 == curMatch2)
+        offset -= 2;
+      distances[offset++] = maxLen = 3;
+      distances[offset++] = _pos - curMatch3 - 1;
+      curMatch2 = curMatch3;
+    }
+  #endif
+  if (offset != 1 && curMatch2 == curMatch)
+  {
+    offset -= 2;
+    maxLen = kStartMaxLen;
+  }
+  #endif
+
+  _hash[kFixHashSize + hashValue] = _pos;
+
+  CIndex *son = _son;
+
+  #ifdef _HASH_CHAIN
+  son[_cyclicBufferPos] = curMatch;
+  #else
+  CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
+  CIndex *ptr1 = son + (_cyclicBufferPos << 1);
+
+  UInt32 len0, len1;
+  len0 = len1 = kNumHashDirectBytes;
+  #endif
+
+  #if kNumHashDirectBytes != 0
+  if(curMatch > matchMinPos)
+  {
+    if (_buffer[curMatch + kNumHashDirectBytes] != cur[kNumHashDirectBytes])
+    {
+      distances[offset++] = maxLen = kNumHashDirectBytes;
+      distances[offset++] = _pos - curMatch - 1;
+    }
+  }
+  #endif
+  UInt32 count = _cutValue;
+  while(true)
+  {
+    if(curMatch <= matchMinPos || count-- == 0)
+    {
+      #ifndef _HASH_CHAIN
+      *ptr0 = *ptr1 = kEmptyHashValue;
+      #endif
+      break;
+    }
+    UInt32 delta = _pos - curMatch;
+    UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
+        (_cyclicBufferPos - delta):
+        (_cyclicBufferPos - delta + _cyclicBufferSize);
+    CIndex *pair = son + 
+    #ifdef _HASH_CHAIN
+      cyclicPos;
+    #else
+      (cyclicPos << 1);
+    #endif
+    
+    // _mm_prefetch((const char *)pair, _MM_HINT_T0);
+    
+    const Byte *pb = _buffer + curMatch;
+    UInt32 len = 
+    #ifdef _HASH_CHAIN
+    kNumHashDirectBytes;
+    if (pb[maxLen] == cur[maxLen])
+    #else
+    MyMin(len0, len1);
+    #endif
+    if (pb[len] == cur[len])
+    {
+      while(++len != lenLimit)
+        if (pb[len] != cur[len])
+          break;
+      if (maxLen < len)
+      {
+        distances[offset++] = maxLen = len;
+        distances[offset++] = delta - 1;
+        if (len == lenLimit)
+        {
+          #ifndef _HASH_CHAIN
+          *ptr1 = pair[0];
+          *ptr0 = pair[1];
+          #endif
+          break;
+        }
+      }
+    }
+    #ifdef _HASH_CHAIN
+    curMatch = *pair;
+    #else
+    if (pb[len] < cur[len])
+    {
+      *ptr1 = curMatch;
+      ptr1 = pair + 1;
+      curMatch = *ptr1;
+      len1 = len;
+    }
+    else
+    {
+      *ptr0 = curMatch;
+      ptr0 = pair;
+      curMatch = *ptr0;
+      len0 = len;
+    }
+    #endif
+  }
+  distances[0] = offset - 1;
+  if (++_cyclicBufferPos == _cyclicBufferSize)
+    _cyclicBufferPos = 0;
+  RINOK(CLZInWindow::MovePos());
+  if (_pos == kMaxValForNormalize)
+    Normalize();
+  return S_OK;
+}
+
+STDMETHODIMP CMatchFinder::Skip(UInt32 num)
+{
+  do
+  {
+  #ifdef _HASH_CHAIN
+  if (_streamPos - _pos < kNumHashBytes)
+  {
+    RINOK(MovePos()); 
+    continue;
+  }
+  #else
+  UInt32 lenLimit;
+  if (_pos + _matchMaxLen <= _streamPos)
+    lenLimit = _matchMaxLen;
+  else
+  {
+    lenLimit = _streamPos - _pos;
+    if(lenLimit < kMinMatchCheck)
+    {
+      RINOK(MovePos());
+      continue;
+    }
+  }
+  UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
+  #endif
+  const Byte *cur = _buffer + _pos;
+
+  #ifdef HASH_ARRAY_2
+  UInt32 hash2Value;
+  #ifdef HASH_ARRAY_3
+  UInt32 hash3Value;
+  UInt32 hashValue;
+  HASH_CALC;
+  _hash[kHash3Offset + hash3Value] = _pos;
+  #else
+  UInt32 hashValue;
+  HASH_CALC;
+  #endif
+  _hash[hash2Value] = _pos;
+  #else
+  UInt32 hashValue = Hash(cur);
+  #endif
+
+  UInt32 curMatch = _hash[kFixHashSize + hashValue];
+  _hash[kFixHashSize + hashValue] = _pos;
+
+  #ifdef _HASH_CHAIN
+  _son[_cyclicBufferPos] = curMatch;
+  #else
+  CIndex *son = _son;
+  CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
+  CIndex *ptr1 = son + (_cyclicBufferPos << 1);
+
+  UInt32 len0, len1;
+  len0 = len1 = kNumHashDirectBytes;
+  UInt32 count = _cutValue;
+  while(true)
+  {
+    if(curMatch <= matchMinPos || count-- == 0)
+    {
+      *ptr0 = *ptr1 = kEmptyHashValue;
+      break;
+    }
+    
+    UInt32 delta = _pos - curMatch;
+    UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
+      (_cyclicBufferPos - delta):
+      (_cyclicBufferPos - delta + _cyclicBufferSize);
+    CIndex *pair = son + (cyclicPos << 1);
+    
+    // _mm_prefetch((const char *)pair, _MM_HINT_T0);
+    
+    const Byte *pb = _buffer + curMatch;
+    UInt32 len = MyMin(len0, len1);
+    
+    if (pb[len] == cur[len])
+    {
+      while(++len != lenLimit)
+        if (pb[len] != cur[len])
+          break;
+      if (len == lenLimit)
+      {
+        *ptr1 = pair[0];
+        *ptr0 = pair[1];
+        break;
+      }
+    }
+    if (pb[len] < cur[len])
+    {
+      *ptr1 = curMatch;
+      ptr1 = pair + 1;
+      curMatch = *ptr1;
+      len1 = len;
+    }
+    else
+    {
+      *ptr0 = curMatch;
+      ptr0 = pair;
+      curMatch = *ptr0;
+      len0 = len;
+    }
+  }
+  #endif
+  if (++_cyclicBufferPos == _cyclicBufferSize)
+    _cyclicBufferPos = 0;
+  RINOK(CLZInWindow::MovePos());
+  if (_pos == kMaxValForNormalize)
+    Normalize();
+  }
+  while(--num != 0);
+  return S_OK;
+}
+
+void CMatchFinder::Normalize()
+{
+  UInt32 subValue = _pos - _cyclicBufferSize;
+  CIndex *items = _hash;
+  UInt32 numItems = (_hashSizeSum + _cyclicBufferSize 
+    #ifndef _HASH_CHAIN
+     * 2
+    #endif
+    );
+  for (UInt32 i = 0; i < numItems; i++)
+  {
+    UInt32 value = items[i];
+    if (value <= subValue)
+      value = kEmptyHashValue;
+    else
+      value -= subValue;
+    items[i] = value;
+  }
+  ReduceOffsets(subValue);
+}
+
+HRESULT CMatchFinder::MovePos()
+{
+  if (++_cyclicBufferPos == _cyclicBufferSize)
+    _cyclicBufferPos = 0;
+  RINOK(CLZInWindow::MovePos());
+  if (_pos == kMaxValForNormalize)
+    Normalize();
+  return S_OK;
+}
+
+STDMETHODIMP_(Byte) CMatchFinder::GetIndexByte(Int32 index)
+  { return CLZInWindow::GetIndexByte(index); }
+
+STDMETHODIMP_(UInt32) CMatchFinder::GetMatchLen(Int32 index, 
+    UInt32 back, UInt32 limit)
+  { return CLZInWindow::GetMatchLen(index, back, limit); }
+
+STDMETHODIMP_(UInt32) CMatchFinder::GetNumAvailableBytes()
+  { return CLZInWindow::GetNumAvailableBytes(); }
+
+STDMETHODIMP_(const Byte *) CMatchFinder::GetPointerToCurrentPos()
+  { return CLZInWindow::GetPointerToCurrentPos(); }
+
+STDMETHODIMP_(Int32) CMatchFinder::NeedChangeBufferPos(UInt32 numCheckBytes)
+  { return CLZInWindow::NeedMove(numCheckBytes) ? 1: 0; }
+
+STDMETHODIMP_(void) CMatchFinder::ChangeBufferPos()
+  { CLZInWindow::MoveBlock();}
+
+#undef HASH_CALC
+#undef kNumHashDirectBytes
+ 
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HC4.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HC4.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HC4.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,19 +1,19 @@
-// HC4.h
-
-#ifndef __HC4_H
-#define __HC4_H
-
-#define BT_NAMESPACE NHC4
-
-#define HASH_ARRAY_2
-#define HASH_ARRAY_3
-
-#include "HCMain.h"
-
-#undef HASH_ARRAY_2
-#undef HASH_ARRAY_3
-
-#undef BT_NAMESPACE
-
-#endif
-
+// HC4.h
+
+#ifndef __HC4_H
+#define __HC4_H
+
+#define BT_NAMESPACE NHC4
+
+#define HASH_ARRAY_2
+#define HASH_ARRAY_3
+
+#include "HCMain.h"
+
+#undef HASH_ARRAY_2
+#undef HASH_ARRAY_3
+
+#undef BT_NAMESPACE
+
+#endif
+

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HCMain.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HCMain.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/HashChain/HCMain.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,6 +1,6 @@
-// HCMain.h
-
-#define _HASH_CHAIN
-#include "../BinTree/BinTreeMain.h"
-#undef _HASH_CHAIN
-
+// HCMain.h
+
+#define _HASH_CHAIN
+#include "../BinTree/BinTreeMain.h"
+#undef _HASH_CHAIN
+

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,33 +1,33 @@
-// MatchFinders/IMatchFinder.h
-
-#ifndef __IMATCHFINDER_H
-#define __IMATCHFINDER_H
-
-struct IInWindowStream: public IUnknown
-{
-  STDMETHOD(SetStream)(ISequentialInStream *inStream) PURE;
-  STDMETHOD_(void, ReleaseStream)() PURE;
-  STDMETHOD(Init)() PURE;
-  STDMETHOD_(Byte, GetIndexByte)(Int32 index) PURE;
-  STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 distance, UInt32 limit) PURE;
-  STDMETHOD_(UInt32, GetNumAvailableBytes)() PURE;
-  STDMETHOD_(const Byte *, GetPointerToCurrentPos)() PURE;
-  STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes) PURE;
-  STDMETHOD_(void, ChangeBufferPos)() PURE;
-};
- 
-struct IMatchFinder: public IInWindowStream
-{
-  STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore, 
-      UInt32 matchMaxLen, UInt32 keepAddBufferAfter) PURE;
-  STDMETHOD(GetMatches)(UInt32 *distances) PURE;
-  STDMETHOD(Skip)(UInt32 num) PURE;
-};
-
-struct IMatchFinderSetNumPasses
-{
-  //virtual ~IMatchFinderSetNumPasses(){}
-  virtual void SetNumPasses(UInt32 numPasses) PURE;
-};
-
-#endif
+// MatchFinders/IMatchFinder.h
+
+#ifndef __IMATCHFINDER_H
+#define __IMATCHFINDER_H
+
+struct IInWindowStream: public IUnknown
+{
+  STDMETHOD(SetStream)(ISequentialInStream *inStream) PURE;
+  STDMETHOD_(void, ReleaseStream)() PURE;
+  STDMETHOD(Init)() PURE;
+  STDMETHOD_(Byte, GetIndexByte)(Int32 index) PURE;
+  STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 distance, UInt32 limit) PURE;
+  STDMETHOD_(UInt32, GetNumAvailableBytes)() PURE;
+  STDMETHOD_(const Byte *, GetPointerToCurrentPos)() PURE;
+  STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes) PURE;
+  STDMETHOD_(void, ChangeBufferPos)() PURE;
+};
+ 
+struct IMatchFinder: public IInWindowStream
+{
+  STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore, 
+      UInt32 matchMaxLen, UInt32 keepAddBufferAfter) PURE;
+  STDMETHOD(GetMatches)(UInt32 *distances) PURE;
+  STDMETHOD(Skip)(UInt32 num) PURE;
+};
+
+struct IMatchFinderSetNumPasses
+{
+  //virtual ~IMatchFinderSetNumPasses(){}
+  virtual void SetNumPasses(UInt32 numPasses) PURE;
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,105 +1,105 @@
-// LZInWindow.cpp
-
-#include "StdAfx.h"
-
-#include "LZInWindow.h"
-#include "../../../Common/MyCom.h"
-#include "../../../Common/Alloc.h"
-
-void CLZInWindow::Free()
-{
-  ::BigFree(_bufferBase);
-  _bufferBase = 0;
-}
-
-bool CLZInWindow::Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv)
-{
-  _keepSizeBefore = keepSizeBefore;
-  _keepSizeAfter = keepSizeAfter;
-  UInt32 blockSize = keepSizeBefore + keepSizeAfter + keepSizeReserv;
-  if (_bufferBase == 0 || _blockSize != blockSize)
-  {
-    Free();
-    _blockSize = blockSize;
-    if (_blockSize != 0)
-      _bufferBase = (Byte *)::BigAlloc(_blockSize);
-  }
-  _pointerToLastSafePosition = _bufferBase + _blockSize - keepSizeAfter;
-  if (_blockSize == 0)
-    return true;
-  return (_bufferBase != 0);
-}
-
-void CLZInWindow::SetStream(ISequentialInStream *stream)
-{
-  _stream = stream;
-}
-
-HRESULT CLZInWindow::Init()
-{
-  _buffer = _bufferBase;
-  _pos = 0;
-  _streamPos = 0;
-  _streamEndWasReached = false;
-  return ReadBlock();
-}
-
-/*
-void CLZInWindow::ReleaseStream()
-{
-  _stream.Release();
-}
-*/
-
-///////////////////////////////////////////
-// ReadBlock
-
-// In State:
-//   (_buffer + _streamPos) <= (_bufferBase + _blockSize)
-// Out State:
-//   _posLimit <= _blockSize - _keepSizeAfter;
-//   if(_streamEndWasReached == false):
-//     _streamPos >= _pos + _keepSizeAfter
-//     _posLimit = _streamPos - _keepSizeAfter;
-//   else
-//          
-  
-HRESULT CLZInWindow::ReadBlock()
-{
-  if(_streamEndWasReached)
-    return S_OK;
-  while(true)
-  {
-    UInt32 size = (UInt32)(_bufferBase - _buffer) + _blockSize - _streamPos;
-    if(size == 0)
-      return S_OK;
-    UInt32 numReadBytes;
-    RINOK(_stream->Read(_buffer + _streamPos, size, &numReadBytes));
-    if(numReadBytes == 0)
-    {
-      _posLimit = _streamPos;
-      const Byte *pointerToPostion = _buffer + _posLimit;
-      if(pointerToPostion > _pointerToLastSafePosition)
-        _posLimit = (UInt32)(_pointerToLastSafePosition - _buffer);
-      _streamEndWasReached = true;
-      return S_OK;
-    }
-    _streamPos += numReadBytes;
-    if(_streamPos >= _pos + _keepSizeAfter)
-    {
-      _posLimit = _streamPos - _keepSizeAfter;
-      return S_OK;
-    }
-  }
-}
-
-void CLZInWindow::MoveBlock()
-{
-  UInt32 offset = (UInt32)(_buffer - _bufferBase) + _pos - _keepSizeBefore;
-  // we need one additional byte, since MovePos moves on 1 byte.
-  if (offset > 0)
-    offset--; 
-  UInt32 numBytes = (UInt32)(_buffer - _bufferBase) + _streamPos -  offset;
-  memmove(_bufferBase, _bufferBase + offset, numBytes);
-  _buffer -= offset;
-}
+// LZInWindow.cpp
+
+#include "StdAfx.h"
+
+#include "LZInWindow.h"
+#include "../../../Common/MyCom.h"
+#include "../../../Common/Alloc.h"
+
+void CLZInWindow::Free()
+{
+  ::BigFree(_bufferBase);
+  _bufferBase = 0;
+}
+
+bool CLZInWindow::Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv)
+{
+  _keepSizeBefore = keepSizeBefore;
+  _keepSizeAfter = keepSizeAfter;
+  UInt32 blockSize = keepSizeBefore + keepSizeAfter + keepSizeReserv;
+  if (_bufferBase == 0 || _blockSize != blockSize)
+  {
+    Free();
+    _blockSize = blockSize;
+    if (_blockSize != 0)
+      _bufferBase = (Byte *)::BigAlloc(_blockSize);
+  }
+  _pointerToLastSafePosition = _bufferBase + _blockSize - keepSizeAfter;
+  if (_blockSize == 0)
+    return true;
+  return (_bufferBase != 0);
+}
+
+void CLZInWindow::SetStream(ISequentialInStream *stream)
+{
+  _stream = stream;
+}
+
+HRESULT CLZInWindow::Init()
+{
+  _buffer = _bufferBase;
+  _pos = 0;
+  _streamPos = 0;
+  _streamEndWasReached = false;
+  return ReadBlock();
+}
+
+/*
+void CLZInWindow::ReleaseStream()
+{
+  _stream.Release();
+}
+*/
+
+///////////////////////////////////////////
+// ReadBlock
+
+// In State:
+//   (_buffer + _streamPos) <= (_bufferBase + _blockSize)
+// Out State:
+//   _posLimit <= _blockSize - _keepSizeAfter;
+//   if(_streamEndWasReached == false):
+//     _streamPos >= _pos + _keepSizeAfter
+//     _posLimit = _streamPos - _keepSizeAfter;
+//   else
+//          
+  
+HRESULT CLZInWindow::ReadBlock()
+{
+  if(_streamEndWasReached)
+    return S_OK;
+  while(true)
+  {
+    UInt32 size = (UInt32)(_bufferBase - _buffer) + _blockSize - _streamPos;
+    if(size == 0)
+      return S_OK;
+    UInt32 numReadBytes;
+    RINOK(_stream->Read(_buffer + _streamPos, size, &numReadBytes));
+    if(numReadBytes == 0)
+    {
+      _posLimit = _streamPos;
+      const Byte *pointerToPostion = _buffer + _posLimit;
+      if(pointerToPostion > _pointerToLastSafePosition)
+        _posLimit = (UInt32)(_pointerToLastSafePosition - _buffer);
+      _streamEndWasReached = true;
+      return S_OK;
+    }
+    _streamPos += numReadBytes;
+    if(_streamPos >= _pos + _keepSizeAfter)
+    {
+      _posLimit = _streamPos - _keepSizeAfter;
+      return S_OK;
+    }
+  }
+}
+
+void CLZInWindow::MoveBlock()
+{
+  UInt32 offset = (UInt32)(_buffer - _bufferBase) + _pos - _keepSizeBefore;
+  // we need one additional byte, since MovePos moves on 1 byte.
+  if (offset > 0)
+    offset--; 
+  UInt32 numBytes = (UInt32)(_buffer - _bufferBase) + _streamPos -  offset;
+  memmove(_bufferBase, _bufferBase + offset, numBytes);
+  _buffer -= offset;
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/LZInWindow.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,87 +1,87 @@
-// LZInWindow.h
-
-#ifndef __LZ_IN_WINDOW_H
-#define __LZ_IN_WINDOW_H
-
-#include "../../IStream.h"
-
-class CLZInWindow
-{
-  Byte *_bufferBase; // pointer to buffer with data
-  ISequentialInStream *_stream;
-  UInt32 _posLimit;  // offset (from _buffer) when new block reading must be done
-  bool _streamEndWasReached; // if (true) then _streamPos shows real end of stream
-  const Byte *_pointerToLastSafePosition;
-protected:
-  Byte  *_buffer;   // Pointer to virtual Buffer begin
-  UInt32 _blockSize;  // Size of Allocated memory block
-  UInt32 _pos;             // offset (from _buffer) of curent byte
-  UInt32 _keepSizeBefore;  // how many BYTEs must be kept in buffer before _pos
-  UInt32 _keepSizeAfter;   // how many BYTEs must be kept buffer after _pos
-  UInt32 _streamPos;   // offset (from _buffer) of first not read byte from Stream
-
-  void MoveBlock();
-  HRESULT ReadBlock();
-  void Free();
-public:
-  CLZInWindow(): _bufferBase(0) {}
-  virtual ~CLZInWindow() { Free(); }
-
-  // keepSizeBefore + keepSizeAfter + keepSizeReserv < 4G)
-  bool Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv = (1<<17));
-
-  void SetStream(ISequentialInStream *stream);
-  HRESULT Init();
-  // void ReleaseStream();
-
-  Byte *GetBuffer() const { return _buffer; }
-
-  const Byte *GetPointerToCurrentPos() const { return _buffer + _pos; }
-
-  HRESULT MovePos()
-  {
-    _pos++;
-    if (_pos > _posLimit)
-    {
-      const Byte *pointerToPostion = _buffer + _pos;
-      if(pointerToPostion > _pointerToLastSafePosition)
-        MoveBlock();
-      return ReadBlock();
-    }
-    else
-      return S_OK;
-  }
-  Byte GetIndexByte(Int32 index) const  {  return _buffer[(size_t)_pos + index]; }
-
-  // index + limit have not to exceed _keepSizeAfter;
-  // -2G <= index < 2G
-  UInt32 GetMatchLen(Int32 index, UInt32 distance, UInt32 limit) const
-  {  
-    if(_streamEndWasReached)
-      if ((_pos + index) + limit > _streamPos)
-        limit = _streamPos - (_pos + index);
-    distance++;
-    const Byte *pby = _buffer + (size_t)_pos + index;
-    UInt32 i;
-    for(i = 0; i < limit && pby[i] == pby[(size_t)i - distance]; i++);
-    return i;
-  }
-
-  UInt32 GetNumAvailableBytes() const { return _streamPos - _pos; }
-
-  void ReduceOffsets(Int32 subValue)
-  {
-    _buffer += subValue;
-    _posLimit -= subValue;
-    _pos -= subValue;
-    _streamPos -= subValue;
-  }
-
-  bool NeedMove(UInt32 numCheckBytes)
-  {
-    UInt32 reserv = _pointerToLastSafePosition - (_buffer + _pos);
-    return (reserv <= numCheckBytes);
-  }
-};
-
-#endif
+// LZInWindow.h
+
+#ifndef __LZ_IN_WINDOW_H
+#define __LZ_IN_WINDOW_H
+
+#include "../../IStream.h"
+
+class CLZInWindow
+{
+  Byte *_bufferBase; // pointer to buffer with data
+  ISequentialInStream *_stream;
+  UInt32 _posLimit;  // offset (from _buffer) when new block reading must be done
+  bool _streamEndWasReached; // if (true) then _streamPos shows real end of stream
+  const Byte *_pointerToLastSafePosition;
+protected:
+  Byte  *_buffer;   // Pointer to virtual Buffer begin
+  UInt32 _blockSize;  // Size of Allocated memory block
+  UInt32 _pos;             // offset (from _buffer) of curent byte
+  UInt32 _keepSizeBefore;  // how many BYTEs must be kept in buffer before _pos
+  UInt32 _keepSizeAfter;   // how many BYTEs must be kept buffer after _pos
+  UInt32 _streamPos;   // offset (from _buffer) of first not read byte from Stream
+
+  void MoveBlock();
+  HRESULT ReadBlock();
+  void Free();
+public:
+  CLZInWindow(): _bufferBase(0) {}
+  virtual ~CLZInWindow() { Free(); }
+
+  // keepSizeBefore + keepSizeAfter + keepSizeReserv < 4G)
+  bool Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv = (1<<17));
+
+  void SetStream(ISequentialInStream *stream);
+  HRESULT Init();
+  // void ReleaseStream();
+
+  Byte *GetBuffer() const { return _buffer; }
+
+  const Byte *GetPointerToCurrentPos() const { return _buffer + _pos; }
+
+  HRESULT MovePos()
+  {
+    _pos++;
+    if (_pos > _posLimit)
+    {
+      const Byte *pointerToPostion = _buffer + _pos;
+      if(pointerToPostion > _pointerToLastSafePosition)
+        MoveBlock();
+      return ReadBlock();
+    }
+    else
+      return S_OK;
+  }
+  Byte GetIndexByte(Int32 index) const  {  return _buffer[(size_t)_pos + index]; }
+
+  // index + limit have not to exceed _keepSizeAfter;
+  // -2G <= index < 2G
+  UInt32 GetMatchLen(Int32 index, UInt32 distance, UInt32 limit) const
+  {  
+    if(_streamEndWasReached)
+      if ((_pos + index) + limit > _streamPos)
+        limit = _streamPos - (_pos + index);
+    distance++;
+    const Byte *pby = _buffer + (size_t)_pos + index;
+    UInt32 i;
+    for(i = 0; i < limit && pby[i] == pby[(size_t)i - distance]; i++);
+    return i;
+  }
+
+  UInt32 GetNumAvailableBytes() const { return _streamPos - _pos; }
+
+  void ReduceOffsets(Int32 subValue)
+  {
+    _buffer += subValue;
+    _posLimit -= subValue;
+    _pos -= subValue;
+    _streamPos -= subValue;
+  }
+
+  bool NeedMove(UInt32 numCheckBytes)
+  {
+    UInt32 reserv = _pointerToLastSafePosition - (_buffer + _pos);
+    return (reserv <= numCheckBytes);
+  }
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/StdAfx.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/StdAfx.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/StdAfx.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,6 +1,6 @@
-// StdAfx.h
-
-#ifndef __STDAFX_H
-#define __STDAFX_H
-
-#endif 
+// StdAfx.h
+
+#ifndef __STDAFX_H
+#define __STDAFX_H
+
+#endif 

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMA.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMA.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMA.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,82 +1,82 @@
-// LZMA.h
-
-#ifndef __LZMA_H
-#define __LZMA_H
-
-namespace NCompress {
-namespace NLZMA {
-
-const UInt32 kNumRepDistances = 4;
-
-const int kNumStates = 12;
-
-const Byte kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};
-const Byte kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};
-const Byte kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};
-const Byte kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};
-
-class CState
-{
-public:
-  Byte Index;
-  void Init() { Index = 0; }
-  void UpdateChar() { Index = kLiteralNextStates[Index]; }
-  void UpdateMatch() { Index = kMatchNextStates[Index]; }
-  void UpdateRep() { Index = kRepNextStates[Index]; }
-  void UpdateShortRep() { Index = kShortRepNextStates[Index]; }
-  bool IsCharState() const { return Index < 7; }
-};
-
-const int kNumPosSlotBits = 6; 
-const int kDicLogSizeMin = 0; 
-const int kDicLogSizeMax = 32; 
-const int kDistTableSizeMax = kDicLogSizeMax * 2; 
-
-const UInt32 kNumLenToPosStates = 4;
-
-inline UInt32 GetLenToPosState(UInt32 len)
-{
-  len -= 2;
-  if (len < kNumLenToPosStates)
-    return len;
-  return kNumLenToPosStates - 1;
-}
-
-namespace NLength {
-
-const int kNumPosStatesBitsMax = 4;
-const UInt32 kNumPosStatesMax = (1 << kNumPosStatesBitsMax);
-
-const int kNumPosStatesBitsEncodingMax = 4;
-const UInt32 kNumPosStatesEncodingMax = (1 << kNumPosStatesBitsEncodingMax);
-
-const int kNumLowBits = 3;
-const int kNumMidBits = 3;
-const int kNumHighBits = 8;
-const UInt32 kNumLowSymbols = 1 << kNumLowBits;
-const UInt32 kNumMidSymbols = 1 << kNumMidBits;
-const UInt32 kNumSymbolsTotal = kNumLowSymbols + kNumMidSymbols + (1 << kNumHighBits);
-
-}
-
-const UInt32 kMatchMinLen = 2;
-const UInt32 kMatchMaxLen = kMatchMinLen + NLength::kNumSymbolsTotal - 1;
-
-const int kNumAlignBits = 4;
-const UInt32 kAlignTableSize = 1 << kNumAlignBits;
-const UInt32 kAlignMask = (kAlignTableSize - 1);
-
-const UInt32 kStartPosModelIndex = 4;
-const UInt32 kEndPosModelIndex = 14;
-const UInt32 kNumPosModels = kEndPosModelIndex - kStartPosModelIndex;
-
-const UInt32 kNumFullDistances = 1 << (kEndPosModelIndex / 2);
-
-const int kNumLitPosStatesBitsEncodingMax = 4;
-const int kNumLitContextBitsMax = 8;
-
-const int kNumMoveBits = 5;
-
-}}
-
-#endif
+// LZMA.h
+
+#ifndef __LZMA_H
+#define __LZMA_H
+
+namespace NCompress {
+namespace NLZMA {
+
+const UInt32 kNumRepDistances = 4;
+
+const int kNumStates = 12;
+
+const Byte kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};
+const Byte kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};
+const Byte kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};
+const Byte kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};
+
+class CState
+{
+public:
+  Byte Index;
+  void Init() { Index = 0; }
+  void UpdateChar() { Index = kLiteralNextStates[Index]; }
+  void UpdateMatch() { Index = kMatchNextStates[Index]; }
+  void UpdateRep() { Index = kRepNextStates[Index]; }
+  void UpdateShortRep() { Index = kShortRepNextStates[Index]; }
+  bool IsCharState() const { return Index < 7; }
+};
+
+const int kNumPosSlotBits = 6; 
+const int kDicLogSizeMin = 0; 
+const int kDicLogSizeMax = 32; 
+const int kDistTableSizeMax = kDicLogSizeMax * 2; 
+
+const UInt32 kNumLenToPosStates = 4;
+
+inline UInt32 GetLenToPosState(UInt32 len)
+{
+  len -= 2;
+  if (len < kNumLenToPosStates)
+    return len;
+  return kNumLenToPosStates - 1;
+}
+
+namespace NLength {
+
+const int kNumPosStatesBitsMax = 4;
+const UInt32 kNumPosStatesMax = (1 << kNumPosStatesBitsMax);
+
+const int kNumPosStatesBitsEncodingMax = 4;
+const UInt32 kNumPosStatesEncodingMax = (1 << kNumPosStatesBitsEncodingMax);
+
+const int kNumLowBits = 3;
+const int kNumMidBits = 3;
+const int kNumHighBits = 8;
+const UInt32 kNumLowSymbols = 1 << kNumLowBits;
+const UInt32 kNumMidSymbols = 1 << kNumMidBits;
+const UInt32 kNumSymbolsTotal = kNumLowSymbols + kNumMidSymbols + (1 << kNumHighBits);
+
+}
+
+const UInt32 kMatchMinLen = 2;
+const UInt32 kMatchMaxLen = kMatchMinLen + NLength::kNumSymbolsTotal - 1;
+
+const int kNumAlignBits = 4;
+const UInt32 kAlignTableSize = 1 << kNumAlignBits;
+const UInt32 kAlignMask = (kAlignTableSize - 1);
+
+const UInt32 kStartPosModelIndex = 4;
+const UInt32 kEndPosModelIndex = 14;
+const UInt32 kNumPosModels = kEndPosModelIndex - kStartPosModelIndex;
+
+const UInt32 kNumFullDistances = 1 << (kEndPosModelIndex / 2);
+
+const int kNumLitPosStatesBitsEncodingMax = 4;
+const int kNumLitContextBitsMax = 8;
+
+const int kNumMoveBits = 5;
+
+}}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,1564 +1,1564 @@
-// LZMA/Encoder.cpp
-
-#include "StdAfx.h"
-
-#include "../../../Common/Defs.h"
-#include "../../Common/StreamUtils.h"
-
-#include "LZMAEncoder.h"
-
-// for minimal compressing code size define these:
-// #define COMPRESS_MF_BT
-// #define COMPRESS_MF_BT4
-
-#if !defined(COMPRESS_MF_BT) && !defined(COMPRESS_MF_HC)
-#define COMPRESS_MF_BT
-#define COMPRESS_MF_HC
-#endif
-
-#ifdef COMPRESS_MF_BT
-#if !defined(COMPRESS_MF_BT2) && !defined(COMPRESS_MF_BT3) && !defined(COMPRESS_MF_BT4)
-#define COMPRESS_MF_BT2
-#define COMPRESS_MF_BT3
-#define COMPRESS_MF_BT4
-#endif
-#ifdef COMPRESS_MF_BT2
-#include "../LZ/BinTree/BinTree2.h"
-#endif
-#ifdef COMPRESS_MF_BT3
-#include "../LZ/BinTree/BinTree3.h"
-#endif
-#ifdef COMPRESS_MF_BT4
-#include "../LZ/BinTree/BinTree4.h"
-#endif
-#endif
-
-#ifdef COMPRESS_MF_HC
-#include "../LZ/HashChain/HC4.h"
-#endif
-
-#ifdef COMPRESS_MF_MT
-#include "../LZ/MT/MT.h"
-#endif
-
-namespace NCompress {
-namespace NLZMA {
-
-const int kDefaultDictionaryLogSize = 22;
-const UInt32 kNumFastBytesDefault = 0x20;
-
-enum 
-{
-  kBT2,
-  kBT3,
-  kBT4,
-  kHC4
-};
-
-static const wchar_t *kMatchFinderIDs[] = 
-{
-  L"BT2",
-  L"BT3",
-  L"BT4",
-  L"HC4"
-};
-
-Byte g_FastPos[1 << 11];
-
-class CFastPosInit
-{
-public:
-  CFastPosInit() { Init(); }
-  void Init()
-  {
-    const Byte kFastSlots = 22;
-    int c = 2;
-    g_FastPos[0] = 0;
-    g_FastPos[1] = 1;
-
-    for (Byte slotFast = 2; slotFast < kFastSlots; slotFast++)
-    {
-      UInt32 k = (1 << ((slotFast >> 1) - 1));
-      for (UInt32 j = 0; j < k; j++, c++)
-        g_FastPos[c] = slotFast;
-    }
-  }
-} g_FastPosInit;
-
-
-void CLiteralEncoder2::Encode(NRangeCoder::CEncoder *rangeEncoder, Byte symbol)
-{
-  UInt32 context = 1;
-  int i = 8;
-  do 
-  {
-    i--;
-    UInt32 bit = (symbol >> i) & 1;
-    _encoders[context].Encode(rangeEncoder, bit);
-    context = (context << 1) | bit;
-  }
-  while(i != 0);
-}
-
-void CLiteralEncoder2::EncodeMatched(NRangeCoder::CEncoder *rangeEncoder, 
-    Byte matchByte, Byte symbol)
-{
-  UInt32 context = 1;
-  int i = 8;
-  do 
-  {
-    i--;
-    UInt32 bit = (symbol >> i) & 1;
-    UInt32 matchBit = (matchByte >> i) & 1;
-    _encoders[0x100 + (matchBit << 8) + context].Encode(rangeEncoder, bit);
-    context = (context << 1) | bit;
-    if (matchBit != bit)
-    {
-      while(i != 0)
-      {
-        i--;
-        UInt32 bit = (symbol >> i) & 1;
-        _encoders[context].Encode(rangeEncoder, bit);
-        context = (context << 1) | bit;
-      }
-      break;
-    }
-  }
-  while(i != 0);
-}
-
-UInt32 CLiteralEncoder2::GetPrice(bool matchMode, Byte matchByte, Byte symbol) const
-{
-  UInt32 price = 0;
-  UInt32 context = 1;
-  int i = 8;
-  if (matchMode)
-  {
-    do 
-    {
-      i--;
-      UInt32 matchBit = (matchByte >> i) & 1;
-      UInt32 bit = (symbol >> i) & 1;
-      price += _encoders[0x100 + (matchBit << 8) + context].GetPrice(bit);
-      context = (context << 1) | bit;
-      if (matchBit != bit)
-        break;
-    }
-    while (i != 0);
-  }
-  while(i != 0)
-  {
-    i--;
-    UInt32 bit = (symbol >> i) & 1;
-    price += _encoders[context].GetPrice(bit);
-    context = (context << 1) | bit;
-  }
-  return price;
-};
-
-
-namespace NLength {
-
-void CEncoder::Init(UInt32 numPosStates)
-{
-  _choice.Init();
-  _choice2.Init();
-  for (UInt32 posState = 0; posState < numPosStates; posState++)
-  {
-    _lowCoder[posState].Init();
-    _midCoder[posState].Init();
-  }
-  _highCoder.Init();
-}
-
-void CEncoder::Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState)
-{
-  if(symbol < kNumLowSymbols)
-  {
-    _choice.Encode(rangeEncoder, 0);
-    _lowCoder[posState].Encode(rangeEncoder, symbol);
-  }
-  else
-  {
-    _choice.Encode(rangeEncoder, 1);
-    if(symbol < kNumLowSymbols + kNumMidSymbols)
-    {
-      _choice2.Encode(rangeEncoder, 0);
-      _midCoder[posState].Encode(rangeEncoder, symbol - kNumLowSymbols);
-    }
-    else
-    {
-      _choice2.Encode(rangeEncoder, 1);
-      _highCoder.Encode(rangeEncoder, symbol - kNumLowSymbols - kNumMidSymbols);
-    }
-  }
-}
-
-void CEncoder::SetPrices(UInt32 posState, UInt32 numSymbols, UInt32 *prices) const
-{
-  UInt32 a0 = _choice.GetPrice0();
-  UInt32 a1 = _choice.GetPrice1();
-  UInt32 b0 = a1 + _choice2.GetPrice0();
-  UInt32 b1 = a1 + _choice2.GetPrice1();
-  UInt32 i = 0;
-  for (i = 0; i < kNumLowSymbols; i++)
-  {
-    if (i >= numSymbols)
-      return;
-    prices[i] = a0 + _lowCoder[posState].GetPrice(i);
-  }
-  for (; i < kNumLowSymbols + kNumMidSymbols; i++)
-  {
-    if (i >= numSymbols)
-      return;
-    prices[i] = b0 + _midCoder[posState].GetPrice(i - kNumLowSymbols);
-  }
-  for (; i < numSymbols; i++)
-    prices[i] = b1 + _highCoder.GetPrice(i - kNumLowSymbols - kNumMidSymbols);
-}
-
-}
-CEncoder::CEncoder():
-  _numFastBytes(kNumFastBytesDefault),
-  _distTableSize(kDefaultDictionaryLogSize * 2),
-  _posStateBits(2),
-  _posStateMask(4 - 1),
-  _numLiteralPosStateBits(0),
-  _numLiteralContextBits(3),
-  _dictionarySize(1 << kDefaultDictionaryLogSize),
-  _dictionarySizePrev(UInt32(-1)),
-  _numFastBytesPrev(UInt32(-1)),
-  _matchFinderCycles(0),
-  _matchFinderIndex(kBT4),
-   #ifdef COMPRESS_MF_MT
-  _multiThread(false),
-   #endif
-  _writeEndMark(false),
-  setMfPasses(0)
-{
-  // _maxMode = false;
-  _fastMode = false;
-}
-
-HRESULT CEncoder::Create()
-{
-  if (!_rangeEncoder.Create(1 << 20))
-    return E_OUTOFMEMORY;
-  if (!_matchFinder)
-  {
-    switch(_matchFinderIndex)
-    {
-      #ifdef COMPRESS_MF_BT
-      #ifdef COMPRESS_MF_BT2
-      case kBT2:
-      {
-        NBT2::CMatchFinder *mfSpec = new NBT2::CMatchFinder;
-        setMfPasses = mfSpec;
-        _matchFinder = mfSpec;
-        break;
-      }
-      #endif
-      #ifdef COMPRESS_MF_BT3
-      case kBT3:
-      {
-        NBT3::CMatchFinder *mfSpec = new NBT3::CMatchFinder;
-        setMfPasses = mfSpec;
-        _matchFinder = mfSpec;
-        break;
-      }
-      #endif
-      #ifdef COMPRESS_MF_BT4
-      case kBT4:
-      {
-        NBT4::CMatchFinder *mfSpec = new NBT4::CMatchFinder;
-        setMfPasses = mfSpec;
-        _matchFinder = mfSpec;
-        break;
-      }
-      #endif
-      #endif
-      
-      #ifdef COMPRESS_MF_HC
-      case kHC4:
-      {
-        NHC4::CMatchFinder *mfSpec = new NHC4::CMatchFinder;
-        setMfPasses = mfSpec;
-        _matchFinder = mfSpec;
-        break;
-      }
-      #endif
-    }
-    if (_matchFinder == 0)
-      return E_OUTOFMEMORY;
-
-    #ifdef COMPRESS_MF_MT
-    if (_multiThread && !(_fastMode && (_matchFinderIndex == kHC4)))
-    {
-      CMatchFinderMT *mfSpec = new CMatchFinderMT;
-      if (mfSpec == 0)
-        return E_OUTOFMEMORY;
-      CMyComPtr<IMatchFinder> mf = mfSpec;
-      RINOK(mfSpec->SetMatchFinder(_matchFinder));
-      _matchFinder.Release();
-      _matchFinder = mf;
-    }
-    #endif
-  }
-  
-  if (!_literalEncoder.Create(_numLiteralPosStateBits, _numLiteralContextBits))
-    return E_OUTOFMEMORY;
-
-  if (_dictionarySize == _dictionarySizePrev && _numFastBytesPrev == _numFastBytes)
-    return S_OK;
-  RINOK(_matchFinder->Create(_dictionarySize, kNumOpts, _numFastBytes, kMatchMaxLen + 1)); // actually it's + _numFastBytes - _numFastBytes
-  if (_matchFinderCycles != 0 && setMfPasses != 0)
-    setMfPasses->SetNumPasses(_matchFinderCycles);
-  _dictionarySizePrev = _dictionarySize;
-  _numFastBytesPrev = _numFastBytes;
-  return S_OK;
-}
-
-static bool AreStringsEqual(const wchar_t *base, const wchar_t *testString)
-{
-  while (true)
-  {
-    wchar_t c = *testString;
-    if (c >= 'a' && c <= 'z')
-      c -= 0x20;
-    if (*base != c)
-      return false;
-    if (c == 0)
-      return true;
-    base++;
-    testString++;
-  }
-}
-
-static int FindMatchFinder(const wchar_t *s)
-{
-  for (int m = 0; m < (int)(sizeof(kMatchFinderIDs) / sizeof(kMatchFinderIDs[0])); m++)
-    if (AreStringsEqual(kMatchFinderIDs[m], s))
-      return m;
-  return -1;
-}
-
-STDMETHODIMP CEncoder::SetCoderProperties(const PROPID *propIDs, 
-    const PROPVARIANT *properties, UInt32 numProperties)
-{
-  for (UInt32 i = 0; i < numProperties; i++)
-  {
-    const PROPVARIANT &prop = properties[i];
-    switch(propIDs[i])
-    {
-      case NCoderPropID::kNumFastBytes:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 numFastBytes = prop.ulVal;
-        if(numFastBytes < 5 || numFastBytes > kMatchMaxLen)
-          return E_INVALIDARG;
-        _numFastBytes = numFastBytes;
-        break;
-      }
-      case NCoderPropID::kMatchFinderCycles:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        _matchFinderCycles = prop.ulVal;
-        break;
-      }
-      case NCoderPropID::kAlgorithm:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 maximize = prop.ulVal;
-        _fastMode = (maximize == 0); 
-        // _maxMode = (maximize >= 2);
-        break;
-      }
-      case NCoderPropID::kMatchFinder:
-      {
-        if (prop.vt != VT_BSTR)
-          return E_INVALIDARG;
-        int matchFinderIndexPrev = _matchFinderIndex;
-        int m = FindMatchFinder(prop.bstrVal);
-        if (m < 0)
-          return E_INVALIDARG;
-        _matchFinderIndex = m;
-        if (_matchFinder && matchFinderIndexPrev != _matchFinderIndex)
-        {
-          _dictionarySizePrev = (UInt32)-1;
-          ReleaseMatchFinder();
-        }
-        break;
-      }
-      #ifdef COMPRESS_MF_MT
-      case NCoderPropID::kMultiThread:
-      {
-        if (prop.vt != VT_BOOL)
-          return E_INVALIDARG;
-        bool newMultiThread = (prop.boolVal == VARIANT_TRUE);
-        if (newMultiThread != _multiThread)
-        {
-          _dictionarySizePrev = (UInt32)-1;
-          ReleaseMatchFinder();
-          _multiThread = newMultiThread;
-        }
-        break;
-      }
-      case NCoderPropID::kNumThreads:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        bool newMultiThread = (prop.ulVal > 1);
-        if (newMultiThread != _multiThread)
-        {
-          _dictionarySizePrev = (UInt32)-1;
-          ReleaseMatchFinder();
-          _multiThread = newMultiThread;
-        }
-        break;
-      }
-      #endif
-      case NCoderPropID::kDictionarySize:
-      {
-        const int kDicLogSizeMaxCompress = 30;
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 dictionarySize = prop.ulVal;
-        if (dictionarySize < UInt32(1 << kDicLogSizeMin) ||
-            dictionarySize > UInt32(1 << kDicLogSizeMaxCompress))
-          return E_INVALIDARG;
-        _dictionarySize = dictionarySize;
-        UInt32 dicLogSize;
-        for(dicLogSize = 0; dicLogSize < (UInt32)kDicLogSizeMaxCompress; dicLogSize++)
-          if (dictionarySize <= (UInt32(1) << dicLogSize))
-            break;
-        _distTableSize = dicLogSize * 2;
-        break;
-      }
-      case NCoderPropID::kPosStateBits:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 value = prop.ulVal;
-        if (value > (UInt32)NLength::kNumPosStatesBitsEncodingMax)
-          return E_INVALIDARG;
-        _posStateBits = value;
-        _posStateMask = (1 << _posStateBits) - 1;
-        break;
-      }
-      case NCoderPropID::kLitPosBits:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 value = prop.ulVal;
-        if (value > (UInt32)kNumLitPosStatesBitsEncodingMax)
-          return E_INVALIDARG;
-        _numLiteralPosStateBits = value;
-        break;
-      }
-      case NCoderPropID::kLitContextBits:
-      {
-        if (prop.vt != VT_UI4)
-          return E_INVALIDARG;
-        UInt32 value = prop.ulVal;
-        if (value > (UInt32)kNumLitContextBitsMax)
-          return E_INVALIDARG;
-        _numLiteralContextBits = value;
-        break;
-      }
-      case NCoderPropID::kEndMarker:
-      {
-        if (prop.vt != VT_BOOL)
-          return E_INVALIDARG;
-        SetWriteEndMarkerMode(prop.boolVal == VARIANT_TRUE);
-        break;
-      }
-      default:
-        return E_INVALIDARG;
-    }
-  }
-  return S_OK;
-}
-
-STDMETHODIMP CEncoder::WriteCoderProperties(ISequentialOutStream *outStream)
-{ 
-  const UInt32 kPropSize = 5;
-  Byte properties[kPropSize];
-  properties[0] = (_posStateBits * 5 + _numLiteralPosStateBits) * 9 + _numLiteralContextBits;
-  for (int i = 0; i < 4; i++)
-    properties[1 + i] = Byte(_dictionarySize >> (8 * i));
-  return WriteStream(outStream, properties, kPropSize, NULL);
-}
-
-STDMETHODIMP CEncoder::SetOutStream(ISequentialOutStream *outStream)
-{
-  _rangeEncoder.SetStream(outStream);
-  return S_OK;
-}
-
-STDMETHODIMP CEncoder::ReleaseOutStream()
-{
-  _rangeEncoder.ReleaseStream();
-  return S_OK;
-}
-
-HRESULT CEncoder::Init()
-{
-  CBaseState::Init();
-
-  // RINOK(_matchFinder->Init(inStream));
-  _rangeEncoder.Init();
-
-  for(int i = 0; i < kNumStates; i++)
-  {
-    for (UInt32 j = 0; j <= _posStateMask; j++)
-    {
-      _isMatch[i][j].Init();
-      _isRep0Long[i][j].Init();
-    }
-    _isRep[i].Init();
-    _isRepG0[i].Init();
-    _isRepG1[i].Init();
-    _isRepG2[i].Init();
-  }
-
-  _literalEncoder.Init();
-
-  {
-    for(UInt32 i = 0; i < kNumLenToPosStates; i++)
-      _posSlotEncoder[i].Init();
-  }
-  {
-    for(UInt32 i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)
-      _posEncoders[i].Init();
-  }
-
-  _lenEncoder.Init(1 << _posStateBits);
-  _repMatchLenEncoder.Init(1 << _posStateBits);
-
-  _posAlignEncoder.Init();
-
-  _longestMatchWasFound = false;
-  _optimumEndIndex = 0;
-  _optimumCurrentIndex = 0;
-  _additionalOffset = 0;
-
-  return S_OK;
-}
-
-HRESULT CEncoder::MovePos(UInt32 num)
-{
-  if (num == 0)
-    return S_OK;
-  _additionalOffset += num;
-  return _matchFinder->Skip(num);
-}
-
-UInt32 CEncoder::Backward(UInt32 &backRes, UInt32 cur)
-{
-  _optimumEndIndex = cur;
-  UInt32 posMem = _optimum[cur].PosPrev;
-  UInt32 backMem = _optimum[cur].BackPrev;
-  do
-  {
-    if (_optimum[cur].Prev1IsChar)
-    {
-      _optimum[posMem].MakeAsChar();
-      _optimum[posMem].PosPrev = posMem - 1;
-      if (_optimum[cur].Prev2)
-      {
-        _optimum[posMem - 1].Prev1IsChar = false;
-        _optimum[posMem - 1].PosPrev = _optimum[cur].PosPrev2;
-        _optimum[posMem - 1].BackPrev = _optimum[cur].BackPrev2;
-      }
-    }
-    UInt32 posPrev = posMem;
-    UInt32 backCur = backMem;
-
-    backMem = _optimum[posPrev].BackPrev;
-    posMem = _optimum[posPrev].PosPrev;
-
-    _optimum[posPrev].BackPrev = backCur;
-    _optimum[posPrev].PosPrev = cur;
-    cur = posPrev;
-  }
-  while(cur != 0);
-  backRes = _optimum[0].BackPrev;
-  _optimumCurrentIndex  = _optimum[0].PosPrev;
-  return _optimumCurrentIndex; 
-}
-
-/*
-Out:
-  (lenRes == 1) && (backRes == 0xFFFFFFFF) means Literal
-*/
-
-HRESULT CEncoder::GetOptimum(UInt32 position, UInt32 &backRes, UInt32 &lenRes)
-{
-  if(_optimumEndIndex != _optimumCurrentIndex)
-  {
-    const COptimal &optimum = _optimum[_optimumCurrentIndex];
-    lenRes = optimum.PosPrev - _optimumCurrentIndex;
-    backRes = optimum.BackPrev;
-    _optimumCurrentIndex = optimum.PosPrev;
-    return S_OK;
-  }
-  _optimumCurrentIndex = _optimumEndIndex = 0;
-  
-  UInt32 lenMain, numDistancePairs;
-  if (!_longestMatchWasFound)
-  {
-    RINOK(ReadMatchDistances(lenMain, numDistancePairs));
-  }
-  else
-  {
-    lenMain = _longestMatchLength;
-    numDistancePairs = _numDistancePairs;
-    _longestMatchWasFound = false;
-  }
-
-  const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
-  UInt32 numAvailableBytes = _matchFinder->GetNumAvailableBytes() + 1;
-  if (numAvailableBytes < 2)
-  {
-    backRes = (UInt32)(-1);
-    lenRes = 1;
-    return S_OK;
-  }
-  if (numAvailableBytes > kMatchMaxLen)
-    numAvailableBytes = kMatchMaxLen;
-
-  UInt32 reps[kNumRepDistances];
-  UInt32 repLens[kNumRepDistances];
-  UInt32 repMaxIndex = 0;
-  UInt32 i;
-  for(i = 0; i < kNumRepDistances; i++)
-  {
-    reps[i] = _repDistances[i];
-    UInt32 backOffset = reps[i] + 1;
-    if (data[0] != data[(size_t)0 - backOffset] || data[1] != data[(size_t)1 - backOffset])
-    {
-      repLens[i] = 0;
-      continue;
-    }
-    UInt32 lenTest;
-    for (lenTest = 2; lenTest < numAvailableBytes && 
-        data[lenTest] == data[(size_t)lenTest - backOffset]; lenTest++);
-    repLens[i] = lenTest;
-    if (lenTest > repLens[repMaxIndex])
-      repMaxIndex = i;
-  }
-  if(repLens[repMaxIndex] >= _numFastBytes)
-  {
-    backRes = repMaxIndex;
-    lenRes = repLens[repMaxIndex];
-    return MovePos(lenRes - 1);
-  }
-
-  UInt32 *matchDistances = _matchDistances + 1;
-  if(lenMain >= _numFastBytes)
-  {
-    backRes = matchDistances[numDistancePairs - 1] + kNumRepDistances; 
-    lenRes = lenMain;
-    return MovePos(lenMain - 1);
-  }
-  Byte currentByte = *data;
-  Byte matchByte = data[(size_t)0 - reps[0] - 1];
-
-  if(lenMain < 2 && currentByte != matchByte && repLens[repMaxIndex] < 2)
-  {
-    backRes = (UInt32)-1;
-    lenRes = 1;
-    return S_OK;
-  }
-
-  _optimum[0].State = _state;
-
-  UInt32 posState = (position & _posStateMask);
-
-  _optimum[1].Price = _isMatch[_state.Index][posState].GetPrice0() + 
-      _literalEncoder.GetSubCoder(position, _previousByte)->GetPrice(!_state.IsCharState(), matchByte, currentByte);
-  _optimum[1].MakeAsChar();
-
-  UInt32 matchPrice = _isMatch[_state.Index][posState].GetPrice1();
-  UInt32 repMatchPrice = matchPrice + _isRep[_state.Index].GetPrice1();
-
-  if(matchByte == currentByte)
-  {
-    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(_state, posState);
-    if(shortRepPrice < _optimum[1].Price)
-    {
-      _optimum[1].Price = shortRepPrice;
-      _optimum[1].MakeAsShortRep();
-    }
-  }
-  UInt32 lenEnd = ((lenMain >= repLens[repMaxIndex]) ? lenMain : repLens[repMaxIndex]);
-
-  if(lenEnd < 2)
-  {
-    backRes = _optimum[1].BackPrev;
-    lenRes = 1;
-    return S_OK;
-  }
-
-  _optimum[1].PosPrev = 0;
-  for (i = 0; i < kNumRepDistances; i++)
-    _optimum[0].Backs[i] = reps[i];
-
-  UInt32 len = lenEnd;
-  do
-    _optimum[len--].Price = kIfinityPrice;
-  while (len >= 2);
-
-  for(i = 0; i < kNumRepDistances; i++)
-  {
-    UInt32 repLen = repLens[i];
-    if (repLen < 2)
-      continue;
-    UInt32 price = repMatchPrice + GetPureRepPrice(i, _state, posState);
-    do
-    {
-      UInt32 curAndLenPrice = price + _repMatchLenEncoder.GetPrice(repLen - 2, posState);
-      COptimal &optimum = _optimum[repLen];
-      if (curAndLenPrice < optimum.Price) 
-      {
-        optimum.Price = curAndLenPrice;
-        optimum.PosPrev = 0;
-        optimum.BackPrev = i;
-        optimum.Prev1IsChar = false;
-      }
-    }
-    while(--repLen >= 2);
-  }
-
-  UInt32 normalMatchPrice = matchPrice + _isRep[_state.Index].GetPrice0();
-
-  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);
-  if (len <= lenMain)
-  {
-    UInt32 offs = 0;
-    while (len > matchDistances[offs])
-      offs += 2;
-    for(; ; len++)
-    {
-      UInt32 distance = matchDistances[offs + 1];
-      UInt32 curAndLenPrice = normalMatchPrice + GetPosLenPrice(distance, len, posState);
-      COptimal &optimum = _optimum[len];
-      if (curAndLenPrice < optimum.Price) 
-      {
-        optimum.Price = curAndLenPrice;
-        optimum.PosPrev = 0;
-        optimum.BackPrev = distance + kNumRepDistances;
-        optimum.Prev1IsChar = false;
-      }
-      if (len == matchDistances[offs])
-      {
-        offs += 2;
-        if (offs == numDistancePairs)
-          break;
-      }
-    }
-  }
-
-  UInt32 cur = 0;
-
-  while(true)
-  {
-    cur++;
-    if(cur == lenEnd)
-    {
-      lenRes = Backward(backRes, cur);
-      return S_OK;
-    }
-    UInt32 newLen, numDistancePairs;
-    RINOK(ReadMatchDistances(newLen, numDistancePairs));
-    if(newLen >= _numFastBytes)
-    {
-      _numDistancePairs = numDistancePairs;
-      _longestMatchLength = newLen;
-      _longestMatchWasFound = true;
-      lenRes = Backward(backRes, cur);
-      return S_OK;
-    }
-    position++;
-    COptimal &curOptimum = _optimum[cur];
-    UInt32 posPrev = curOptimum.PosPrev;
-    CState state;
-    if (curOptimum.Prev1IsChar)
-    {
-      posPrev--;
-      if (curOptimum.Prev2)
-      {
-        state = _optimum[curOptimum.PosPrev2].State;
-        if (curOptimum.BackPrev2 < kNumRepDistances)
-          state.UpdateRep();
-        else
-          state.UpdateMatch();
-      }
-      else
-        state = _optimum[posPrev].State;
-      state.UpdateChar();
-    }
-    else
-      state = _optimum[posPrev].State;
-    if (posPrev == cur - 1)
-    {
-      if (curOptimum.IsShortRep())
-        state.UpdateShortRep();
-      else
-        state.UpdateChar();
-    }
-    else
-    {
-      UInt32 pos;
-      if (curOptimum.Prev1IsChar && curOptimum.Prev2)
-      {
-        posPrev = curOptimum.PosPrev2;
-        pos = curOptimum.BackPrev2;
-        state.UpdateRep();
-      }
-      else
-      {
-        pos = curOptimum.BackPrev;
-        if (pos < kNumRepDistances)
-          state.UpdateRep();
-        else
-          state.UpdateMatch();
-      }
-      const COptimal &prevOptimum = _optimum[posPrev];
-      if (pos < kNumRepDistances)
-      {
-        reps[0] = prevOptimum.Backs[pos];
-    		UInt32 i;
-        for(i = 1; i <= pos; i++)
-          reps[i] = prevOptimum.Backs[i - 1];
-        for(; i < kNumRepDistances; i++)
-          reps[i] = prevOptimum.Backs[i];
-      }
-      else
-      {
-        reps[0] = (pos - kNumRepDistances);
-        for(UInt32 i = 1; i < kNumRepDistances; i++)
-          reps[i] = prevOptimum.Backs[i - 1];
-      }
-    }
-    curOptimum.State = state;
-    for(UInt32 i = 0; i < kNumRepDistances; i++)
-      curOptimum.Backs[i] = reps[i];
-    UInt32 curPrice = curOptimum.Price; 
-    const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
-    const Byte currentByte = *data;
-    const Byte matchByte = data[(size_t)0 - reps[0] - 1];
-
-    UInt32 posState = (position & _posStateMask);
-
-    UInt32 curAnd1Price = curPrice +
-        _isMatch[state.Index][posState].GetPrice0() +
-        _literalEncoder.GetSubCoder(position, data[(size_t)0 - 1])->GetPrice(!state.IsCharState(), matchByte, currentByte);
-
-    COptimal &nextOptimum = _optimum[cur + 1];
-
-    bool nextIsChar = false;
-    if (curAnd1Price < nextOptimum.Price) 
-    {
-      nextOptimum.Price = curAnd1Price;
-      nextOptimum.PosPrev = cur;
-      nextOptimum.MakeAsChar();
-      nextIsChar = true;
-    }
-
-    UInt32 matchPrice = curPrice + _isMatch[state.Index][posState].GetPrice1();
-    UInt32 repMatchPrice = matchPrice + _isRep[state.Index].GetPrice1();
-    
-    if(matchByte == currentByte &&
-        !(nextOptimum.PosPrev < cur && nextOptimum.BackPrev == 0))
-    {
-      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(state, posState);
-      if(shortRepPrice <= nextOptimum.Price)
-      {
-        nextOptimum.Price = shortRepPrice;
-        nextOptimum.PosPrev = cur;
-        nextOptimum.MakeAsShortRep();
-        nextIsChar = true;
-      }
-    }
-    /*
-    if(newLen == 2 && matchDistances[2] >= kDistLimit2) // test it maybe set 2000 ?
-      continue;
-    */
-
-    UInt32 numAvailableBytesFull = _matchFinder->GetNumAvailableBytes() + 1;
-    numAvailableBytesFull = MyMin(kNumOpts - 1 - cur, numAvailableBytesFull);
-    UInt32 numAvailableBytes = numAvailableBytesFull;
-
-    if (numAvailableBytes < 2)
-      continue;
-    if (numAvailableBytes > _numFastBytes)
-      numAvailableBytes = _numFastBytes;
-    if (!nextIsChar && matchByte != currentByte) // speed optimization
-    {
-      // try Literal + rep0
-      UInt32 backOffset = reps[0] + 1;
-      UInt32 limit = MyMin(numAvailableBytesFull, _numFastBytes + 1);
-      UInt32 temp;
-      for (temp = 1; temp < limit && 
-          data[temp] == data[(size_t)temp - backOffset]; temp++);
-      UInt32 lenTest2 = temp - 1;
-      if (lenTest2 >= 2)
-      {
-        CState state2 = state;
-        state2.UpdateChar();
-        UInt32 posStateNext = (position + 1) & _posStateMask;
-        UInt32 nextRepMatchPrice = curAnd1Price + 
-            _isMatch[state2.Index][posStateNext].GetPrice1() +
-            _isRep[state2.Index].GetPrice1();
-        // for (; lenTest2 >= 2; lenTest2--)
-        {
-          UInt32 offset = cur + 1 + lenTest2;
-          while(lenEnd < offset)
-            _optimum[++lenEnd].Price = kIfinityPrice;
-          UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(
-              0, lenTest2, state2, posStateNext);
-          COptimal &optimum = _optimum[offset];
-          if (curAndLenPrice < optimum.Price) 
-          {
-            optimum.Price = curAndLenPrice;
-            optimum.PosPrev = cur + 1;
-            optimum.BackPrev = 0;
-            optimum.Prev1IsChar = true;
-            optimum.Prev2 = false;
-          }
-        }
-      }
-    }
-    
-    UInt32 startLen = 2; // speed optimization 
-    for(UInt32 repIndex = 0; repIndex < kNumRepDistances; repIndex++)
-    {
-      // UInt32 repLen = _matchFinder->GetMatchLen(0 - 1, reps[repIndex], newLen); // test it;
-      UInt32 backOffset = reps[repIndex] + 1;
-      if (data[0] != data[(size_t)0 - backOffset] ||
-          data[1] != data[(size_t)1 - backOffset])
-        continue;
-      UInt32 lenTest;
-      for (lenTest = 2; lenTest < numAvailableBytes && 
-          data[lenTest] == data[(size_t)lenTest - backOffset]; lenTest++);
-      while(lenEnd < cur + lenTest)
-        _optimum[++lenEnd].Price = kIfinityPrice;
-      UInt32 lenTestTemp = lenTest;
-      UInt32 price = repMatchPrice + GetPureRepPrice(repIndex, state, posState);
-      do
-      {
-        UInt32 curAndLenPrice = price + _repMatchLenEncoder.GetPrice(lenTest - 2, posState);
-        COptimal &optimum = _optimum[cur + lenTest];
-        if (curAndLenPrice < optimum.Price) 
-        {
-          optimum.Price = curAndLenPrice;
-          optimum.PosPrev = cur;
-          optimum.BackPrev = repIndex;
-          optimum.Prev1IsChar = false;
-        }
-      }
-      while(--lenTest >= 2);
-      lenTest = lenTestTemp;
-      
-      if (repIndex == 0)
-        startLen = lenTest + 1;
-        
-      // if (_maxMode)
-        {
-          UInt32 lenTest2 = lenTest + 1;
-          UInt32 limit = MyMin(numAvailableBytesFull, lenTest2 + _numFastBytes);
-          for (; lenTest2 < limit && 
-              data[lenTest2] == data[(size_t)lenTest2 - backOffset]; lenTest2++);
-          lenTest2 -= lenTest + 1;
-          if (lenTest2 >= 2)
-          {
-            CState state2 = state;
-            state2.UpdateRep();
-            UInt32 posStateNext = (position + lenTest) & _posStateMask;
-            UInt32 curAndLenCharPrice = 
-                price + _repMatchLenEncoder.GetPrice(lenTest - 2, posState) + 
-                _isMatch[state2.Index][posStateNext].GetPrice0() +
-                _literalEncoder.GetSubCoder(position + lenTest, data[(size_t)lenTest - 1])->GetPrice(
-                true, data[(size_t)lenTest - backOffset], data[lenTest]);
-            state2.UpdateChar();
-            posStateNext = (position + lenTest + 1) & _posStateMask;
-            UInt32 nextRepMatchPrice = curAndLenCharPrice + 
-                _isMatch[state2.Index][posStateNext].GetPrice1() +
-                _isRep[state2.Index].GetPrice1();
-            
-            // for(; lenTest2 >= 2; lenTest2--)
-            {
-              UInt32 offset = cur + lenTest + 1 + lenTest2;
-              while(lenEnd < offset)
-                _optimum[++lenEnd].Price = kIfinityPrice;
-              UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(
-                  0, lenTest2, state2, posStateNext);
-              COptimal &optimum = _optimum[offset];
-              if (curAndLenPrice < optimum.Price) 
-              {
-                optimum.Price = curAndLenPrice;
-                optimum.PosPrev = cur + lenTest + 1;
-                optimum.BackPrev = 0;
-                optimum.Prev1IsChar = true;
-                optimum.Prev2 = true;
-                optimum.PosPrev2 = cur;
-                optimum.BackPrev2 = repIndex;
-              }
-            }
-          }
-        }
-      }
-    
-    //    for(UInt32 lenTest = 2; lenTest <= newLen; lenTest++)
-    if (newLen > numAvailableBytes)
-    {
-      newLen = numAvailableBytes;
-      for (numDistancePairs = 0; newLen > matchDistances[numDistancePairs]; numDistancePairs += 2);
-      matchDistances[numDistancePairs] = newLen;
-      numDistancePairs += 2;
-    }
-    if (newLen >= startLen)
-    {
-      UInt32 normalMatchPrice = matchPrice + _isRep[state.Index].GetPrice0();
-      while(lenEnd < cur + newLen)
-        _optimum[++lenEnd].Price = kIfinityPrice;
-
-      UInt32 offs = 0;
-      while(startLen > matchDistances[offs])
-        offs += 2;
-      UInt32 curBack = matchDistances[offs + 1];
-      UInt32 posSlot = GetPosSlot2(curBack);
-      for(UInt32 lenTest = /*2*/ startLen; ; lenTest++)
-      {
-        UInt32 curAndLenPrice = normalMatchPrice;
-        UInt32 lenToPosState = GetLenToPosState(lenTest);
-        if (curBack < kNumFullDistances)
-          curAndLenPrice += _distancesPrices[lenToPosState][curBack];
-        else
-          curAndLenPrice += _posSlotPrices[lenToPosState][posSlot] + _alignPrices[curBack & kAlignMask];
-  
-        curAndLenPrice += _lenEncoder.GetPrice(lenTest - kMatchMinLen, posState);
-        
-        COptimal &optimum = _optimum[cur + lenTest];
-        if (curAndLenPrice < optimum.Price) 
-        {
-          optimum.Price = curAndLenPrice;
-          optimum.PosPrev = cur;
-          optimum.BackPrev = curBack + kNumRepDistances;
-          optimum.Prev1IsChar = false;
-        }
-
-        if (/*_maxMode && */lenTest == matchDistances[offs])
-        {
-          // Try Match + Literal + Rep0
-          UInt32 backOffset = curBack + 1;
-          UInt32 lenTest2 = lenTest + 1;
-          UInt32 limit = MyMin(numAvailableBytesFull, lenTest2 + _numFastBytes);
-          for (; lenTest2 < limit && 
-              data[lenTest2] == data[(size_t)lenTest2 - backOffset]; lenTest2++);
-          lenTest2 -= lenTest + 1;
-          if (lenTest2 >= 2)
-          {
-            CState state2 = state;
-            state2.UpdateMatch();
-            UInt32 posStateNext = (position + lenTest) & _posStateMask;
-            UInt32 curAndLenCharPrice = curAndLenPrice + 
-                _isMatch[state2.Index][posStateNext].GetPrice0() +
-                _literalEncoder.GetSubCoder(position + lenTest, data[(size_t)lenTest - 1])->GetPrice( 
-                true, data[(size_t)lenTest - backOffset], data[lenTest]);
-            state2.UpdateChar();
-            posStateNext = (posStateNext + 1) & _posStateMask;
-            UInt32 nextRepMatchPrice = curAndLenCharPrice + 
-                _isMatch[state2.Index][posStateNext].GetPrice1() +
-                _isRep[state2.Index].GetPrice1();
-            
-            // for(; lenTest2 >= 2; lenTest2--)
-            {
-              UInt32 offset = cur + lenTest + 1 + lenTest2;
-              while(lenEnd < offset)
-                _optimum[++lenEnd].Price = kIfinityPrice;
-              UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(0, lenTest2, state2, posStateNext);
-              COptimal &optimum = _optimum[offset];
-              if (curAndLenPrice < optimum.Price) 
-              {
-                optimum.Price = curAndLenPrice;
-                optimum.PosPrev = cur + lenTest + 1;
-                optimum.BackPrev = 0;
-                optimum.Prev1IsChar = true;
-                optimum.Prev2 = true;
-                optimum.PosPrev2 = cur;
-                optimum.BackPrev2 = curBack + kNumRepDistances;
-              }
-            }
-          }
-          offs += 2;
-          if (offs == numDistancePairs)
-            break;
-          curBack = matchDistances[offs + 1];
-          if (curBack >= kNumFullDistances)
-            posSlot = GetPosSlot2(curBack);
-        }
-      }
-    }
-  }
-}
-
-static inline bool ChangePair(UInt32 smallDist, UInt32 bigDist)
-{
-  return ((bigDist >> 7) > smallDist);
-}
-
-
-HRESULT CEncoder::ReadMatchDistances(UInt32 &lenRes, UInt32 &numDistancePairs)
-{
-  lenRes = 0;
-  RINOK(_matchFinder->GetMatches(_matchDistances));
-  numDistancePairs = _matchDistances[0];
-  if (numDistancePairs > 0)
-  {
-    lenRes = _matchDistances[1 + numDistancePairs - 2];
-    if (lenRes == _numFastBytes)
-      lenRes += _matchFinder->GetMatchLen(lenRes - 1, _matchDistances[1 + numDistancePairs - 1], 
-          kMatchMaxLen - lenRes);
-  }
-  _additionalOffset++;
-  return S_OK;
-}
-
-HRESULT CEncoder::GetOptimumFast(UInt32 position, UInt32 &backRes, UInt32 &lenRes)
-{
-  UInt32 lenMain, numDistancePairs;
-  if (!_longestMatchWasFound)
-  {
-    RINOK(ReadMatchDistances(lenMain, numDistancePairs));
-  }
-  else
-  {
-    lenMain = _longestMatchLength;
-    numDistancePairs = _numDistancePairs;
-    _longestMatchWasFound = false;
-  }
-
-  const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
-  UInt32 numAvailableBytes = _matchFinder->GetNumAvailableBytes() + 1;
-  if (numAvailableBytes > kMatchMaxLen)
-    numAvailableBytes = kMatchMaxLen;
-  if (numAvailableBytes < 2)
-  {
-    backRes = (UInt32)(-1);
-    lenRes = 1;
-    return S_OK;
-  }
-
-  UInt32 repLens[kNumRepDistances];
-  UInt32 repMaxIndex = 0;
-
-  for(UInt32 i = 0; i < kNumRepDistances; i++)
-  {
-    UInt32 backOffset = _repDistances[i] + 1;
-    if (data[0] != data[(size_t)0 - backOffset] || data[1] != data[(size_t)1 - backOffset])
-    {
-      repLens[i] = 0;
-      continue;
-    }
-    UInt32 len;
-    for (len = 2; len < numAvailableBytes && data[len] == data[(size_t)len - backOffset]; len++);
-    if(len >= _numFastBytes)
-    {
-      backRes = i;
-      lenRes = len;
-      return MovePos(lenRes - 1);
-    }
-    repLens[i] = len;
-    if (len > repLens[repMaxIndex])
-      repMaxIndex = i;
-  }
-  UInt32 *matchDistances = _matchDistances + 1;
-  if(lenMain >= _numFastBytes)
-  {
-    backRes = matchDistances[numDistancePairs - 1] + kNumRepDistances; 
-    lenRes = lenMain;
-    return MovePos(lenMain - 1);
-  }
-
-  UInt32 backMain = 0;
-  if (lenMain >= 2)
-  {
-    backMain = matchDistances[numDistancePairs - 1];
-    while (numDistancePairs > 2 && lenMain == matchDistances[numDistancePairs - 4] + 1)
-    {
-      if (!ChangePair(matchDistances[numDistancePairs - 3], backMain))
-        break;
-      numDistancePairs -= 2;
-      lenMain = matchDistances[numDistancePairs - 2];
-      backMain = matchDistances[numDistancePairs - 1];
-    }
-    if (lenMain == 2 && backMain >= 0x80)
-      lenMain = 1;
-  }
-
-  if (repLens[repMaxIndex] >= 2)
-  {
-    if (repLens[repMaxIndex] + 1 >= lenMain || 
-        repLens[repMaxIndex] + 2 >= lenMain && (backMain > (1 << 9)) ||
-        repLens[repMaxIndex] + 3 >= lenMain && (backMain > (1 << 15)))
-    {
-      backRes = repMaxIndex;
-      lenRes = repLens[repMaxIndex];
-      return MovePos(lenRes - 1);
-    }
-  }
-  
-  if (lenMain >= 2 && numAvailableBytes > 2)
-  {
-    RINOK(ReadMatchDistances(_longestMatchLength, _numDistancePairs));
-    if (_longestMatchLength >= 2)
-    {
-      UInt32 newDistance = matchDistances[_numDistancePairs - 1];
-      if (_longestMatchLength >= lenMain && newDistance < backMain || 
-          _longestMatchLength == lenMain + 1 && !ChangePair(backMain, newDistance) ||
-          _longestMatchLength > lenMain + 1 ||
-          _longestMatchLength + 1 >= lenMain && lenMain >= 3 && ChangePair(newDistance, backMain))
-      {
-        _longestMatchWasFound = true;
-        backRes = UInt32(-1);
-        lenRes = 1;
-        return S_OK;
-      }
-    }
-    data++;
-    numAvailableBytes--;
-    for(UInt32 i = 0; i < kNumRepDistances; i++)
-    {
-      UInt32 backOffset = _repDistances[i] + 1;
-      if (data[1] != data[(size_t)1 - backOffset] || data[2] != data[(size_t)2 - backOffset])
-      {
-        repLens[i] = 0;
-        continue;
-      }
-      UInt32 len;
-      for (len = 2; len < numAvailableBytes && data[len] == data[(size_t)len - backOffset]; len++);
-      if (len + 1 >= lenMain)
-      {
-        _longestMatchWasFound = true;
-        backRes = UInt32(-1);
-        lenRes = 1;
-        return S_OK;
-      }
-    }
-    backRes = backMain + kNumRepDistances; 
-    lenRes = lenMain;
-    return MovePos(lenMain - 2);
-  }
-  backRes = UInt32(-1);
-  lenRes = 1;
-  return S_OK;
-}
-
-HRESULT CEncoder::Flush(UInt32 nowPos)
-{
-  ReleaseMFStream();
-  WriteEndMarker(nowPos & _posStateMask);
-  _rangeEncoder.FlushData();
-  return _rangeEncoder.FlushStream();
-}
-
-void CEncoder::WriteEndMarker(UInt32 posState)
-{
-  // This function for writing End Mark for stream version of LZMA. 
-  // In current version this feature is not used.
-  if (!_writeEndMark)
-    return;
-
-  _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 1);
-  _isRep[_state.Index].Encode(&_rangeEncoder, 0);
-  _state.UpdateMatch();
-  UInt32 len = kMatchMinLen; // kMatchMaxLen;
-  _lenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
-  UInt32 posSlot = (1 << kNumPosSlotBits)  - 1;
-  UInt32 lenToPosState = GetLenToPosState(len);
-  _posSlotEncoder[lenToPosState].Encode(&_rangeEncoder, posSlot);
-  UInt32 footerBits = 30;
-  UInt32 posReduced = (UInt32(1) << footerBits) - 1;
-  _rangeEncoder.EncodeDirectBits(posReduced >> kNumAlignBits, footerBits - kNumAlignBits);
-  _posAlignEncoder.ReverseEncode(&_rangeEncoder, posReduced & kAlignMask);
-}
-
-HRESULT CEncoder::CodeReal(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream, 
-      const UInt64 *inSize, const UInt64 *outSize,
-      ICompressProgressInfo *progress)
-{
-  _needReleaseMFStream = false;
-  CCoderReleaser coderReleaser(this);
-  RINOK(SetStreams(inStream, outStream, inSize, outSize));
-  while(true)
-  {
-    UInt64 processedInSize;
-    UInt64 processedOutSize;
-    Int32 finished;
-    RINOK(CodeOneBlock(&processedInSize, &processedOutSize, &finished));
-    if (finished != 0)
-      return S_OK;
-    if (progress != 0)
-    {
-      RINOK(progress->SetRatioInfo(&processedInSize, &processedOutSize));
-    }
-  }
-}
-
-HRESULT CEncoder::SetStreams(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream, 
-      const UInt64 *inSize, const UInt64 *outSize)
-{
-  _inStream = inStream;
-  _finished = false;
-  RINOK(Create());
-  RINOK(SetOutStream(outStream));
-  RINOK(Init());
-  
-  // CCoderReleaser releaser(this);
-
-  /*
-  if (_matchFinder->GetNumAvailableBytes() == 0)
-    return Flush();
-  */
-
-  if (!_fastMode)
-  {
-    FillDistancesPrices();
-    FillAlignPrices();
-  }
-
-  _lenEncoder.SetTableSize(_numFastBytes + 1 - kMatchMinLen);
-  _lenEncoder.UpdateTables(1 << _posStateBits);
-  _repMatchLenEncoder.SetTableSize(_numFastBytes + 1 - kMatchMinLen);
-  _repMatchLenEncoder.UpdateTables(1 << _posStateBits);
-
-  nowPos64 = 0;
-  return S_OK;
-}
-
-HRESULT CEncoder::CodeOneBlock(UInt64 *inSize, UInt64 *outSize, Int32 *finished)
-{
-  if (_inStream != 0)
-  {
-    RINOK(_matchFinder->SetStream(_inStream));
-    RINOK(_matchFinder->Init());
-    _needReleaseMFStream = true;
-    _inStream = 0;
-  }
-
-
-  *finished = 1;
-  if (_finished)
-    return S_OK;
-  _finished = true;
-
-  if (nowPos64 == 0)
-  {
-    if (_matchFinder->GetNumAvailableBytes() == 0)
-      return Flush(UInt32(nowPos64));
-    UInt32 len, numDistancePairs;
-    RINOK(ReadMatchDistances(len, numDistancePairs));
-    UInt32 posState = UInt32(nowPos64) & _posStateMask;
-    _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 0);
-    _state.UpdateChar();
-    Byte curByte = _matchFinder->GetIndexByte(0 - _additionalOffset);
-    _literalEncoder.GetSubCoder(UInt32(nowPos64), _previousByte)->Encode(&_rangeEncoder, curByte);
-    _previousByte = curByte;
-    _additionalOffset--;
-    nowPos64++;
-  }
-
-  UInt32 nowPos32 = (UInt32)nowPos64;
-  UInt32 progressPosValuePrev = nowPos32;
-
-  if (_matchFinder->GetNumAvailableBytes() == 0)
-    return Flush(nowPos32);
-
-  while(true)
-  {
-    #ifdef _NO_EXCEPTIONS
-    if (_rangeEncoder.Stream.ErrorCode != S_OK)
-      return _rangeEncoder.Stream.ErrorCode;
-    #endif
-    UInt32 pos, len;
-    HRESULT result;
-    if (_fastMode)
-      result = GetOptimumFast(nowPos32, pos, len);
-    else
-      result = GetOptimum(nowPos32, pos, len);
-    RINOK(result);
-
-    UInt32 posState = nowPos32 & _posStateMask;
-    if(len == 1 && pos == 0xFFFFFFFF)
-    {
-      _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 0);
-      Byte curByte = _matchFinder->GetIndexByte(0 - _additionalOffset);
-      CLiteralEncoder2 *subCoder = _literalEncoder.GetSubCoder(nowPos32, _previousByte);
-      if(_state.IsCharState())
-        subCoder->Encode(&_rangeEncoder, curByte);
-      else
-      {
-        Byte matchByte = _matchFinder->GetIndexByte(0 - _repDistances[0] - 1 - _additionalOffset);
-        subCoder->EncodeMatched(&_rangeEncoder, matchByte, curByte);
-      }
-      _state.UpdateChar();
-      _previousByte = curByte;
-    }
-    else
-    {
-      _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 1);
-      if(pos < kNumRepDistances)
-      {
-        _isRep[_state.Index].Encode(&_rangeEncoder, 1);
-        if(pos == 0)
-        {
-          _isRepG0[_state.Index].Encode(&_rangeEncoder, 0);
-          _isRep0Long[_state.Index][posState].Encode(&_rangeEncoder, ((len == 1) ? 0 : 1));
-        }
-        else
-        {
-          UInt32 distance = _repDistances[pos];
-          _isRepG0[_state.Index].Encode(&_rangeEncoder, 1);
-          if (pos == 1)
-            _isRepG1[_state.Index].Encode(&_rangeEncoder, 0);
-          else
-          {
-            _isRepG1[_state.Index].Encode(&_rangeEncoder, 1);
-            _isRepG2[_state.Index].Encode(&_rangeEncoder, pos - 2);
-            if (pos == 3)
-              _repDistances[3] = _repDistances[2];
-            _repDistances[2] = _repDistances[1];
-          }
-          _repDistances[1] = _repDistances[0];
-          _repDistances[0] = distance;
-        }
-        if (len == 1)
-          _state.UpdateShortRep();
-        else
-        {
-          _repMatchLenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
-          _state.UpdateRep();
-        }
-      }
-      else
-      {
-        _isRep[_state.Index].Encode(&_rangeEncoder, 0);
-        _state.UpdateMatch();
-        _lenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
-        pos -= kNumRepDistances;
-        UInt32 posSlot = GetPosSlot(pos);
-        _posSlotEncoder[GetLenToPosState(len)].Encode(&_rangeEncoder, posSlot);
-        
-        if (posSlot >= kStartPosModelIndex)
-        {
-          UInt32 footerBits = ((posSlot >> 1) - 1);
-          UInt32 base = ((2 | (posSlot & 1)) << footerBits);
-          UInt32 posReduced = pos - base;
-
-          if (posSlot < kEndPosModelIndex)
-            NRangeCoder::ReverseBitTreeEncode(_posEncoders + base - posSlot - 1, 
-                &_rangeEncoder, footerBits, posReduced);
-          else
-          {
-            _rangeEncoder.EncodeDirectBits(posReduced >> kNumAlignBits, footerBits - kNumAlignBits);
-            _posAlignEncoder.ReverseEncode(&_rangeEncoder, posReduced & kAlignMask);
-            _alignPriceCount++;
-          }
-        }
-        _repDistances[3] = _repDistances[2];
-        _repDistances[2] = _repDistances[1];
-        _repDistances[1] = _repDistances[0];
-        _repDistances[0] = pos;
-        _matchPriceCount++;
-      }
-      _previousByte = _matchFinder->GetIndexByte(len - 1 - _additionalOffset);
-    }
-    _additionalOffset -= len;
-    nowPos32 += len;
-    if (_additionalOffset == 0)
-    {
-      if (!_fastMode)
-      {
-        if (_matchPriceCount >= (1 << 7))
-          FillDistancesPrices();
-        if (_alignPriceCount >= kAlignTableSize)
-          FillAlignPrices();
-      }
-      if (_matchFinder->GetNumAvailableBytes() == 0)
-        return Flush(nowPos32);
-      if (nowPos32 - progressPosValuePrev >= (1 << 14))
-      {
-        nowPos64 += nowPos32 - progressPosValuePrev;
-        *inSize = nowPos64;
-        *outSize = _rangeEncoder.GetProcessedSize();
-        _finished = false;
-        *finished = 0;
-        return S_OK;
-      }
-    }
-  }
-}
-
-STDMETHODIMP CEncoder::Code(ISequentialInStream *inStream,
-    ISequentialOutStream *outStream, const UInt64 *inSize, const UInt64 *outSize,
-    ICompressProgressInfo *progress)
-{
-  #ifndef _NO_EXCEPTIONS
-  try 
-  { 
-  #endif
-    return CodeReal(inStream, outStream, inSize, outSize, progress); 
-  #ifndef _NO_EXCEPTIONS
-  }
-  catch(const COutBufferException &e) { return e.ErrorCode; }
-  catch(...) { return E_FAIL; }
-  #endif
-}
-  
-void CEncoder::FillDistancesPrices()
-{
-  UInt32 tempPrices[kNumFullDistances];
-  for (UInt32 i = kStartPosModelIndex; i < kNumFullDistances; i++)
-  { 
-    UInt32 posSlot = GetPosSlot(i);
-    UInt32 footerBits = ((posSlot >> 1) - 1);
-    UInt32 base = ((2 | (posSlot & 1)) << footerBits);
-    tempPrices[i] = NRangeCoder::ReverseBitTreeGetPrice(_posEncoders + 
-      base - posSlot - 1, footerBits, i - base);
-  }
-
-  for (UInt32 lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)
-  {
-	  UInt32 posSlot;
-    NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumPosSlotBits> &encoder = _posSlotEncoder[lenToPosState];
-    UInt32 *posSlotPrices = _posSlotPrices[lenToPosState];
-    for (posSlot = 0; posSlot < _distTableSize; posSlot++)
-      posSlotPrices[posSlot] = encoder.GetPrice(posSlot);
-    for (posSlot = kEndPosModelIndex; posSlot < _distTableSize; posSlot++)
-      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << NRangeCoder::kNumBitPriceShiftBits);
-
-    UInt32 *distancesPrices = _distancesPrices[lenToPosState];
-	  UInt32 i;
-    for (i = 0; i < kStartPosModelIndex; i++)
-      distancesPrices[i] = posSlotPrices[i];
-    for (; i < kNumFullDistances; i++)
-      distancesPrices[i] = posSlotPrices[GetPosSlot(i)] + tempPrices[i];
-  }
-  _matchPriceCount = 0;
-}
-
-void CEncoder::FillAlignPrices()
-{
-  for (UInt32 i = 0; i < kAlignTableSize; i++)
-    _alignPrices[i] = _posAlignEncoder.ReverseGetPrice(i);
-  _alignPriceCount = 0;
-}
-
-}}
+// LZMA/Encoder.cpp
+
+#include "StdAfx.h"
+
+#include "../../../Common/Defs.h"
+#include "../../Common/StreamUtils.h"
+
+#include "LZMAEncoder.h"
+
+// for minimal compressing code size define these:
+// #define COMPRESS_MF_BT
+// #define COMPRESS_MF_BT4
+
+#if !defined(COMPRESS_MF_BT) && !defined(COMPRESS_MF_HC)
+#define COMPRESS_MF_BT
+#define COMPRESS_MF_HC
+#endif
+
+#ifdef COMPRESS_MF_BT
+#if !defined(COMPRESS_MF_BT2) && !defined(COMPRESS_MF_BT3) && !defined(COMPRESS_MF_BT4)
+#define COMPRESS_MF_BT2
+#define COMPRESS_MF_BT3
+#define COMPRESS_MF_BT4
+#endif
+#ifdef COMPRESS_MF_BT2
+#include "../LZ/BinTree/BinTree2.h"
+#endif
+#ifdef COMPRESS_MF_BT3
+#include "../LZ/BinTree/BinTree3.h"
+#endif
+#ifdef COMPRESS_MF_BT4
+#include "../LZ/BinTree/BinTree4.h"
+#endif
+#endif
+
+#ifdef COMPRESS_MF_HC
+#include "../LZ/HashChain/HC4.h"
+#endif
+
+#ifdef COMPRESS_MF_MT
+#include "../LZ/MT/MT.h"
+#endif
+
+namespace NCompress {
+namespace NLZMA {
+
+const int kDefaultDictionaryLogSize = 22;
+const UInt32 kNumFastBytesDefault = 0x20;
+
+enum 
+{
+  kBT2,
+  kBT3,
+  kBT4,
+  kHC4
+};
+
+static const wchar_t *kMatchFinderIDs[] = 
+{
+  L"BT2",
+  L"BT3",
+  L"BT4",
+  L"HC4"
+};
+
+Byte g_FastPos[1 << 11];
+
+class CFastPosInit
+{
+public:
+  CFastPosInit() { Init(); }
+  void Init()
+  {
+    const Byte kFastSlots = 22;
+    int c = 2;
+    g_FastPos[0] = 0;
+    g_FastPos[1] = 1;
+
+    for (Byte slotFast = 2; slotFast < kFastSlots; slotFast++)
+    {
+      UInt32 k = (1 << ((slotFast >> 1) - 1));
+      for (UInt32 j = 0; j < k; j++, c++)
+        g_FastPos[c] = slotFast;
+    }
+  }
+} g_FastPosInit;
+
+
+void CLiteralEncoder2::Encode(NRangeCoder::CEncoder *rangeEncoder, Byte symbol)
+{
+  UInt32 context = 1;
+  int i = 8;
+  do 
+  {
+    i--;
+    UInt32 bit = (symbol >> i) & 1;
+    _encoders[context].Encode(rangeEncoder, bit);
+    context = (context << 1) | bit;
+  }
+  while(i != 0);
+}
+
+void CLiteralEncoder2::EncodeMatched(NRangeCoder::CEncoder *rangeEncoder, 
+    Byte matchByte, Byte symbol)
+{
+  UInt32 context = 1;
+  int i = 8;
+  do 
+  {
+    i--;
+    UInt32 bit = (symbol >> i) & 1;
+    UInt32 matchBit = (matchByte >> i) & 1;
+    _encoders[0x100 + (matchBit << 8) + context].Encode(rangeEncoder, bit);
+    context = (context << 1) | bit;
+    if (matchBit != bit)
+    {
+      while(i != 0)
+      {
+        i--;
+        UInt32 bit = (symbol >> i) & 1;
+        _encoders[context].Encode(rangeEncoder, bit);
+        context = (context << 1) | bit;
+      }
+      break;
+    }
+  }
+  while(i != 0);
+}
+
+UInt32 CLiteralEncoder2::GetPrice(bool matchMode, Byte matchByte, Byte symbol) const
+{
+  UInt32 price = 0;
+  UInt32 context = 1;
+  int i = 8;
+  if (matchMode)
+  {
+    do 
+    {
+      i--;
+      UInt32 matchBit = (matchByte >> i) & 1;
+      UInt32 bit = (symbol >> i) & 1;
+      price += _encoders[0x100 + (matchBit << 8) + context].GetPrice(bit);
+      context = (context << 1) | bit;
+      if (matchBit != bit)
+        break;
+    }
+    while (i != 0);
+  }
+  while(i != 0)
+  {
+    i--;
+    UInt32 bit = (symbol >> i) & 1;
+    price += _encoders[context].GetPrice(bit);
+    context = (context << 1) | bit;
+  }
+  return price;
+};
+
+
+namespace NLength {
+
+void CEncoder::Init(UInt32 numPosStates)
+{
+  _choice.Init();
+  _choice2.Init();
+  for (UInt32 posState = 0; posState < numPosStates; posState++)
+  {
+    _lowCoder[posState].Init();
+    _midCoder[posState].Init();
+  }
+  _highCoder.Init();
+}
+
+void CEncoder::Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState)
+{
+  if(symbol < kNumLowSymbols)
+  {
+    _choice.Encode(rangeEncoder, 0);
+    _lowCoder[posState].Encode(rangeEncoder, symbol);
+  }
+  else
+  {
+    _choice.Encode(rangeEncoder, 1);
+    if(symbol < kNumLowSymbols + kNumMidSymbols)
+    {
+      _choice2.Encode(rangeEncoder, 0);
+      _midCoder[posState].Encode(rangeEncoder, symbol - kNumLowSymbols);
+    }
+    else
+    {
+      _choice2.Encode(rangeEncoder, 1);
+      _highCoder.Encode(rangeEncoder, symbol - kNumLowSymbols - kNumMidSymbols);
+    }
+  }
+}
+
+void CEncoder::SetPrices(UInt32 posState, UInt32 numSymbols, UInt32 *prices) const
+{
+  UInt32 a0 = _choice.GetPrice0();
+  UInt32 a1 = _choice.GetPrice1();
+  UInt32 b0 = a1 + _choice2.GetPrice0();
+  UInt32 b1 = a1 + _choice2.GetPrice1();
+  UInt32 i = 0;
+  for (i = 0; i < kNumLowSymbols; i++)
+  {
+    if (i >= numSymbols)
+      return;
+    prices[i] = a0 + _lowCoder[posState].GetPrice(i);
+  }
+  for (; i < kNumLowSymbols + kNumMidSymbols; i++)
+  {
+    if (i >= numSymbols)
+      return;
+    prices[i] = b0 + _midCoder[posState].GetPrice(i - kNumLowSymbols);
+  }
+  for (; i < numSymbols; i++)
+    prices[i] = b1 + _highCoder.GetPrice(i - kNumLowSymbols - kNumMidSymbols);
+}
+
+}
+CEncoder::CEncoder():
+  _numFastBytes(kNumFastBytesDefault),
+  _distTableSize(kDefaultDictionaryLogSize * 2),
+  _posStateBits(2),
+  _posStateMask(4 - 1),
+  _numLiteralPosStateBits(0),
+  _numLiteralContextBits(3),
+  _dictionarySize(1 << kDefaultDictionaryLogSize),
+  _dictionarySizePrev(UInt32(-1)),
+  _numFastBytesPrev(UInt32(-1)),
+  _matchFinderCycles(0),
+  _matchFinderIndex(kBT4),
+   #ifdef COMPRESS_MF_MT
+  _multiThread(false),
+   #endif
+  _writeEndMark(false),
+  setMfPasses(0)
+{
+  // _maxMode = false;
+  _fastMode = false;
+}
+
+HRESULT CEncoder::Create()
+{
+  if (!_rangeEncoder.Create(1 << 20))
+    return E_OUTOFMEMORY;
+  if (!_matchFinder)
+  {
+    switch(_matchFinderIndex)
+    {
+      #ifdef COMPRESS_MF_BT
+      #ifdef COMPRESS_MF_BT2
+      case kBT2:
+      {
+        NBT2::CMatchFinder *mfSpec = new NBT2::CMatchFinder;
+        setMfPasses = mfSpec;
+        _matchFinder = mfSpec;
+        break;
+      }
+      #endif
+      #ifdef COMPRESS_MF_BT3
+      case kBT3:
+      {
+        NBT3::CMatchFinder *mfSpec = new NBT3::CMatchFinder;
+        setMfPasses = mfSpec;
+        _matchFinder = mfSpec;
+        break;
+      }
+      #endif
+      #ifdef COMPRESS_MF_BT4
+      case kBT4:
+      {
+        NBT4::CMatchFinder *mfSpec = new NBT4::CMatchFinder;
+        setMfPasses = mfSpec;
+        _matchFinder = mfSpec;
+        break;
+      }
+      #endif
+      #endif
+      
+      #ifdef COMPRESS_MF_HC
+      case kHC4:
+      {
+        NHC4::CMatchFinder *mfSpec = new NHC4::CMatchFinder;
+        setMfPasses = mfSpec;
+        _matchFinder = mfSpec;
+        break;
+      }
+      #endif
+    }
+    if (_matchFinder == 0)
+      return E_OUTOFMEMORY;
+
+    #ifdef COMPRESS_MF_MT
+    if (_multiThread && !(_fastMode && (_matchFinderIndex == kHC4)))
+    {
+      CMatchFinderMT *mfSpec = new CMatchFinderMT;
+      if (mfSpec == 0)
+        return E_OUTOFMEMORY;
+      CMyComPtr<IMatchFinder> mf = mfSpec;
+      RINOK(mfSpec->SetMatchFinder(_matchFinder));
+      _matchFinder.Release();
+      _matchFinder = mf;
+    }
+    #endif
+  }
+  
+  if (!_literalEncoder.Create(_numLiteralPosStateBits, _numLiteralContextBits))
+    return E_OUTOFMEMORY;
+
+  if (_dictionarySize == _dictionarySizePrev && _numFastBytesPrev == _numFastBytes)
+    return S_OK;
+  RINOK(_matchFinder->Create(_dictionarySize, kNumOpts, _numFastBytes, kMatchMaxLen + 1)); // actually it's + _numFastBytes - _numFastBytes
+  if (_matchFinderCycles != 0 && setMfPasses != 0)
+    setMfPasses->SetNumPasses(_matchFinderCycles);
+  _dictionarySizePrev = _dictionarySize;
+  _numFastBytesPrev = _numFastBytes;
+  return S_OK;
+}
+
+static bool AreStringsEqual(const wchar_t *base, const wchar_t *testString)
+{
+  while (true)
+  {
+    wchar_t c = *testString;
+    if (c >= 'a' && c <= 'z')
+      c -= 0x20;
+    if (*base != c)
+      return false;
+    if (c == 0)
+      return true;
+    base++;
+    testString++;
+  }
+}
+
+static int FindMatchFinder(const wchar_t *s)
+{
+  for (int m = 0; m < (int)(sizeof(kMatchFinderIDs) / sizeof(kMatchFinderIDs[0])); m++)
+    if (AreStringsEqual(kMatchFinderIDs[m], s))
+      return m;
+  return -1;
+}
+
+STDMETHODIMP CEncoder::SetCoderProperties(const PROPID *propIDs, 
+    const PROPVARIANT *properties, UInt32 numProperties)
+{
+  for (UInt32 i = 0; i < numProperties; i++)
+  {
+    const PROPVARIANT &prop = properties[i];
+    switch(propIDs[i])
+    {
+      case NCoderPropID::kNumFastBytes:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 numFastBytes = prop.ulVal;
+        if(numFastBytes < 5 || numFastBytes > kMatchMaxLen)
+          return E_INVALIDARG;
+        _numFastBytes = numFastBytes;
+        break;
+      }
+      case NCoderPropID::kMatchFinderCycles:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        _matchFinderCycles = prop.ulVal;
+        break;
+      }
+      case NCoderPropID::kAlgorithm:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 maximize = prop.ulVal;
+        _fastMode = (maximize == 0); 
+        // _maxMode = (maximize >= 2);
+        break;
+      }
+      case NCoderPropID::kMatchFinder:
+      {
+        if (prop.vt != VT_BSTR)
+          return E_INVALIDARG;
+        int matchFinderIndexPrev = _matchFinderIndex;
+        int m = FindMatchFinder(prop.bstrVal);
+        if (m < 0)
+          return E_INVALIDARG;
+        _matchFinderIndex = m;
+        if (_matchFinder && matchFinderIndexPrev != _matchFinderIndex)
+        {
+          _dictionarySizePrev = (UInt32)-1;
+          ReleaseMatchFinder();
+        }
+        break;
+      }
+      #ifdef COMPRESS_MF_MT
+      case NCoderPropID::kMultiThread:
+      {
+        if (prop.vt != VT_BOOL)
+          return E_INVALIDARG;
+        bool newMultiThread = (prop.boolVal == VARIANT_TRUE);
+        if (newMultiThread != _multiThread)
+        {
+          _dictionarySizePrev = (UInt32)-1;
+          ReleaseMatchFinder();
+          _multiThread = newMultiThread;
+        }
+        break;
+      }
+      case NCoderPropID::kNumThreads:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        bool newMultiThread = (prop.ulVal > 1);
+        if (newMultiThread != _multiThread)
+        {
+          _dictionarySizePrev = (UInt32)-1;
+          ReleaseMatchFinder();
+          _multiThread = newMultiThread;
+        }
+        break;
+      }
+      #endif
+      case NCoderPropID::kDictionarySize:
+      {
+        const int kDicLogSizeMaxCompress = 30;
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 dictionarySize = prop.ulVal;
+        if (dictionarySize < UInt32(1 << kDicLogSizeMin) ||
+            dictionarySize > UInt32(1 << kDicLogSizeMaxCompress))
+          return E_INVALIDARG;
+        _dictionarySize = dictionarySize;
+        UInt32 dicLogSize;
+        for(dicLogSize = 0; dicLogSize < (UInt32)kDicLogSizeMaxCompress; dicLogSize++)
+          if (dictionarySize <= (UInt32(1) << dicLogSize))
+            break;
+        _distTableSize = dicLogSize * 2;
+        break;
+      }
+      case NCoderPropID::kPosStateBits:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 value = prop.ulVal;
+        if (value > (UInt32)NLength::kNumPosStatesBitsEncodingMax)
+          return E_INVALIDARG;
+        _posStateBits = value;
+        _posStateMask = (1 << _posStateBits) - 1;
+        break;
+      }
+      case NCoderPropID::kLitPosBits:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 value = prop.ulVal;
+        if (value > (UInt32)kNumLitPosStatesBitsEncodingMax)
+          return E_INVALIDARG;
+        _numLiteralPosStateBits = value;
+        break;
+      }
+      case NCoderPropID::kLitContextBits:
+      {
+        if (prop.vt != VT_UI4)
+          return E_INVALIDARG;
+        UInt32 value = prop.ulVal;
+        if (value > (UInt32)kNumLitContextBitsMax)
+          return E_INVALIDARG;
+        _numLiteralContextBits = value;
+        break;
+      }
+      case NCoderPropID::kEndMarker:
+      {
+        if (prop.vt != VT_BOOL)
+          return E_INVALIDARG;
+        SetWriteEndMarkerMode(prop.boolVal == VARIANT_TRUE);
+        break;
+      }
+      default:
+        return E_INVALIDARG;
+    }
+  }
+  return S_OK;
+}
+
+STDMETHODIMP CEncoder::WriteCoderProperties(ISequentialOutStream *outStream)
+{ 
+  const UInt32 kPropSize = 5;
+  Byte properties[kPropSize];
+  properties[0] = (_posStateBits * 5 + _numLiteralPosStateBits) * 9 + _numLiteralContextBits;
+  for (int i = 0; i < 4; i++)
+    properties[1 + i] = Byte(_dictionarySize >> (8 * i));
+  return WriteStream(outStream, properties, kPropSize, NULL);
+}
+
+STDMETHODIMP CEncoder::SetOutStream(ISequentialOutStream *outStream)
+{
+  _rangeEncoder.SetStream(outStream);
+  return S_OK;
+}
+
+STDMETHODIMP CEncoder::ReleaseOutStream()
+{
+  _rangeEncoder.ReleaseStream();
+  return S_OK;
+}
+
+HRESULT CEncoder::Init()
+{
+  CBaseState::Init();
+
+  // RINOK(_matchFinder->Init(inStream));
+  _rangeEncoder.Init();
+
+  for(int i = 0; i < kNumStates; i++)
+  {
+    for (UInt32 j = 0; j <= _posStateMask; j++)
+    {
+      _isMatch[i][j].Init();
+      _isRep0Long[i][j].Init();
+    }
+    _isRep[i].Init();
+    _isRepG0[i].Init();
+    _isRepG1[i].Init();
+    _isRepG2[i].Init();
+  }
+
+  _literalEncoder.Init();
+
+  {
+    for(UInt32 i = 0; i < kNumLenToPosStates; i++)
+      _posSlotEncoder[i].Init();
+  }
+  {
+    for(UInt32 i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)
+      _posEncoders[i].Init();
+  }
+
+  _lenEncoder.Init(1 << _posStateBits);
+  _repMatchLenEncoder.Init(1 << _posStateBits);
+
+  _posAlignEncoder.Init();
+
+  _longestMatchWasFound = false;
+  _optimumEndIndex = 0;
+  _optimumCurrentIndex = 0;
+  _additionalOffset = 0;
+
+  return S_OK;
+}
+
+HRESULT CEncoder::MovePos(UInt32 num)
+{
+  if (num == 0)
+    return S_OK;
+  _additionalOffset += num;
+  return _matchFinder->Skip(num);
+}
+
+UInt32 CEncoder::Backward(UInt32 &backRes, UInt32 cur)
+{
+  _optimumEndIndex = cur;
+  UInt32 posMem = _optimum[cur].PosPrev;
+  UInt32 backMem = _optimum[cur].BackPrev;
+  do
+  {
+    if (_optimum[cur].Prev1IsChar)
+    {
+      _optimum[posMem].MakeAsChar();
+      _optimum[posMem].PosPrev = posMem - 1;
+      if (_optimum[cur].Prev2)
+      {
+        _optimum[posMem - 1].Prev1IsChar = false;
+        _optimum[posMem - 1].PosPrev = _optimum[cur].PosPrev2;
+        _optimum[posMem - 1].BackPrev = _optimum[cur].BackPrev2;
+      }
+    }
+    UInt32 posPrev = posMem;
+    UInt32 backCur = backMem;
+
+    backMem = _optimum[posPrev].BackPrev;
+    posMem = _optimum[posPrev].PosPrev;
+
+    _optimum[posPrev].BackPrev = backCur;
+    _optimum[posPrev].PosPrev = cur;
+    cur = posPrev;
+  }
+  while(cur != 0);
+  backRes = _optimum[0].BackPrev;
+  _optimumCurrentIndex  = _optimum[0].PosPrev;
+  return _optimumCurrentIndex; 
+}
+
+/*
+Out:
+  (lenRes == 1) && (backRes == 0xFFFFFFFF) means Literal
+*/
+
+HRESULT CEncoder::GetOptimum(UInt32 position, UInt32 &backRes, UInt32 &lenRes)
+{
+  if(_optimumEndIndex != _optimumCurrentIndex)
+  {
+    const COptimal &optimum = _optimum[_optimumCurrentIndex];
+    lenRes = optimum.PosPrev - _optimumCurrentIndex;
+    backRes = optimum.BackPrev;
+    _optimumCurrentIndex = optimum.PosPrev;
+    return S_OK;
+  }
+  _optimumCurrentIndex = _optimumEndIndex = 0;
+  
+  UInt32 lenMain, numDistancePairs;
+  if (!_longestMatchWasFound)
+  {
+    RINOK(ReadMatchDistances(lenMain, numDistancePairs));
+  }
+  else
+  {
+    lenMain = _longestMatchLength;
+    numDistancePairs = _numDistancePairs;
+    _longestMatchWasFound = false;
+  }
+
+  const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
+  UInt32 numAvailableBytes = _matchFinder->GetNumAvailableBytes() + 1;
+  if (numAvailableBytes < 2)
+  {
+    backRes = (UInt32)(-1);
+    lenRes = 1;
+    return S_OK;
+  }
+  if (numAvailableBytes > kMatchMaxLen)
+    numAvailableBytes = kMatchMaxLen;
+
+  UInt32 reps[kNumRepDistances];
+  UInt32 repLens[kNumRepDistances];
+  UInt32 repMaxIndex = 0;
+  UInt32 i;
+  for(i = 0; i < kNumRepDistances; i++)
+  {
+    reps[i] = _repDistances[i];
+    UInt32 backOffset = reps[i] + 1;
+    if (data[0] != data[(size_t)0 - backOffset] || data[1] != data[(size_t)1 - backOffset])
+    {
+      repLens[i] = 0;
+      continue;
+    }
+    UInt32 lenTest;
+    for (lenTest = 2; lenTest < numAvailableBytes && 
+        data[lenTest] == data[(size_t)lenTest - backOffset]; lenTest++);
+    repLens[i] = lenTest;
+    if (lenTest > repLens[repMaxIndex])
+      repMaxIndex = i;
+  }
+  if(repLens[repMaxIndex] >= _numFastBytes)
+  {
+    backRes = repMaxIndex;
+    lenRes = repLens[repMaxIndex];
+    return MovePos(lenRes - 1);
+  }
+
+  UInt32 *matchDistances = _matchDistances + 1;
+  if(lenMain >= _numFastBytes)
+  {
+    backRes = matchDistances[numDistancePairs - 1] + kNumRepDistances; 
+    lenRes = lenMain;
+    return MovePos(lenMain - 1);
+  }
+  Byte currentByte = *data;
+  Byte matchByte = data[(size_t)0 - reps[0] - 1];
+
+  if(lenMain < 2 && currentByte != matchByte && repLens[repMaxIndex] < 2)
+  {
+    backRes = (UInt32)-1;
+    lenRes = 1;
+    return S_OK;
+  }
+
+  _optimum[0].State = _state;
+
+  UInt32 posState = (position & _posStateMask);
+
+  _optimum[1].Price = _isMatch[_state.Index][posState].GetPrice0() + 
+      _literalEncoder.GetSubCoder(position, _previousByte)->GetPrice(!_state.IsCharState(), matchByte, currentByte);
+  _optimum[1].MakeAsChar();
+
+  UInt32 matchPrice = _isMatch[_state.Index][posState].GetPrice1();
+  UInt32 repMatchPrice = matchPrice + _isRep[_state.Index].GetPrice1();
+
+  if(matchByte == currentByte)
+  {
+    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(_state, posState);
+    if(shortRepPrice < _optimum[1].Price)
+    {
+      _optimum[1].Price = shortRepPrice;
+      _optimum[1].MakeAsShortRep();
+    }
+  }
+  UInt32 lenEnd = ((lenMain >= repLens[repMaxIndex]) ? lenMain : repLens[repMaxIndex]);
+
+  if(lenEnd < 2)
+  {
+    backRes = _optimum[1].BackPrev;
+    lenRes = 1;
+    return S_OK;
+  }
+
+  _optimum[1].PosPrev = 0;
+  for (i = 0; i < kNumRepDistances; i++)
+    _optimum[0].Backs[i] = reps[i];
+
+  UInt32 len = lenEnd;
+  do
+    _optimum[len--].Price = kIfinityPrice;
+  while (len >= 2);
+
+  for(i = 0; i < kNumRepDistances; i++)
+  {
+    UInt32 repLen = repLens[i];
+    if (repLen < 2)
+      continue;
+    UInt32 price = repMatchPrice + GetPureRepPrice(i, _state, posState);
+    do
+    {
+      UInt32 curAndLenPrice = price + _repMatchLenEncoder.GetPrice(repLen - 2, posState);
+      COptimal &optimum = _optimum[repLen];
+      if (curAndLenPrice < optimum.Price) 
+      {
+        optimum.Price = curAndLenPrice;
+        optimum.PosPrev = 0;
+        optimum.BackPrev = i;
+        optimum.Prev1IsChar = false;
+      }
+    }
+    while(--repLen >= 2);
+  }
+
+  UInt32 normalMatchPrice = matchPrice + _isRep[_state.Index].GetPrice0();
+
+  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);
+  if (len <= lenMain)
+  {
+    UInt32 offs = 0;
+    while (len > matchDistances[offs])
+      offs += 2;
+    for(; ; len++)
+    {
+      UInt32 distance = matchDistances[offs + 1];
+      UInt32 curAndLenPrice = normalMatchPrice + GetPosLenPrice(distance, len, posState);
+      COptimal &optimum = _optimum[len];
+      if (curAndLenPrice < optimum.Price) 
+      {
+        optimum.Price = curAndLenPrice;
+        optimum.PosPrev = 0;
+        optimum.BackPrev = distance + kNumRepDistances;
+        optimum.Prev1IsChar = false;
+      }
+      if (len == matchDistances[offs])
+      {
+        offs += 2;
+        if (offs == numDistancePairs)
+          break;
+      }
+    }
+  }
+
+  UInt32 cur = 0;
+
+  while(true)
+  {
+    cur++;
+    if(cur == lenEnd)
+    {
+      lenRes = Backward(backRes, cur);
+      return S_OK;
+    }
+    UInt32 newLen, numDistancePairs;
+    RINOK(ReadMatchDistances(newLen, numDistancePairs));
+    if(newLen >= _numFastBytes)
+    {
+      _numDistancePairs = numDistancePairs;
+      _longestMatchLength = newLen;
+      _longestMatchWasFound = true;
+      lenRes = Backward(backRes, cur);
+      return S_OK;
+    }
+    position++;
+    COptimal &curOptimum = _optimum[cur];
+    UInt32 posPrev = curOptimum.PosPrev;
+    CState state;
+    if (curOptimum.Prev1IsChar)
+    {
+      posPrev--;
+      if (curOptimum.Prev2)
+      {
+        state = _optimum[curOptimum.PosPrev2].State;
+        if (curOptimum.BackPrev2 < kNumRepDistances)
+          state.UpdateRep();
+        else
+          state.UpdateMatch();
+      }
+      else
+        state = _optimum[posPrev].State;
+      state.UpdateChar();
+    }
+    else
+      state = _optimum[posPrev].State;
+    if (posPrev == cur - 1)
+    {
+      if (curOptimum.IsShortRep())
+        state.UpdateShortRep();
+      else
+        state.UpdateChar();
+    }
+    else
+    {
+      UInt32 pos;
+      if (curOptimum.Prev1IsChar && curOptimum.Prev2)
+      {
+        posPrev = curOptimum.PosPrev2;
+        pos = curOptimum.BackPrev2;
+        state.UpdateRep();
+      }
+      else
+      {
+        pos = curOptimum.BackPrev;
+        if (pos < kNumRepDistances)
+          state.UpdateRep();
+        else
+          state.UpdateMatch();
+      }
+      const COptimal &prevOptimum = _optimum[posPrev];
+      if (pos < kNumRepDistances)
+      {
+        reps[0] = prevOptimum.Backs[pos];
+    		UInt32 i;
+        for(i = 1; i <= pos; i++)
+          reps[i] = prevOptimum.Backs[i - 1];
+        for(; i < kNumRepDistances; i++)
+          reps[i] = prevOptimum.Backs[i];
+      }
+      else
+      {
+        reps[0] = (pos - kNumRepDistances);
+        for(UInt32 i = 1; i < kNumRepDistances; i++)
+          reps[i] = prevOptimum.Backs[i - 1];
+      }
+    }
+    curOptimum.State = state;
+    for(UInt32 i = 0; i < kNumRepDistances; i++)
+      curOptimum.Backs[i] = reps[i];
+    UInt32 curPrice = curOptimum.Price; 
+    const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
+    const Byte currentByte = *data;
+    const Byte matchByte = data[(size_t)0 - reps[0] - 1];
+
+    UInt32 posState = (position & _posStateMask);
+
+    UInt32 curAnd1Price = curPrice +
+        _isMatch[state.Index][posState].GetPrice0() +
+        _literalEncoder.GetSubCoder(position, data[(size_t)0 - 1])->GetPrice(!state.IsCharState(), matchByte, currentByte);
+
+    COptimal &nextOptimum = _optimum[cur + 1];
+
+    bool nextIsChar = false;
+    if (curAnd1Price < nextOptimum.Price) 
+    {
+      nextOptimum.Price = curAnd1Price;
+      nextOptimum.PosPrev = cur;
+      nextOptimum.MakeAsChar();
+      nextIsChar = true;
+    }
+
+    UInt32 matchPrice = curPrice + _isMatch[state.Index][posState].GetPrice1();
+    UInt32 repMatchPrice = matchPrice + _isRep[state.Index].GetPrice1();
+    
+    if(matchByte == currentByte &&
+        !(nextOptimum.PosPrev < cur && nextOptimum.BackPrev == 0))
+    {
+      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(state, posState);
+      if(shortRepPrice <= nextOptimum.Price)
+      {
+        nextOptimum.Price = shortRepPrice;
+        nextOptimum.PosPrev = cur;
+        nextOptimum.MakeAsShortRep();
+        nextIsChar = true;
+      }
+    }
+    /*
+    if(newLen == 2 && matchDistances[2] >= kDistLimit2) // test it maybe set 2000 ?
+      continue;
+    */
+
+    UInt32 numAvailableBytesFull = _matchFinder->GetNumAvailableBytes() + 1;
+    numAvailableBytesFull = MyMin(kNumOpts - 1 - cur, numAvailableBytesFull);
+    UInt32 numAvailableBytes = numAvailableBytesFull;
+
+    if (numAvailableBytes < 2)
+      continue;
+    if (numAvailableBytes > _numFastBytes)
+      numAvailableBytes = _numFastBytes;
+    if (!nextIsChar && matchByte != currentByte) // speed optimization
+    {
+      // try Literal + rep0
+      UInt32 backOffset = reps[0] + 1;
+      UInt32 limit = MyMin(numAvailableBytesFull, _numFastBytes + 1);
+      UInt32 temp;
+      for (temp = 1; temp < limit && 
+          data[temp] == data[(size_t)temp - backOffset]; temp++);
+      UInt32 lenTest2 = temp - 1;
+      if (lenTest2 >= 2)
+      {
+        CState state2 = state;
+        state2.UpdateChar();
+        UInt32 posStateNext = (position + 1) & _posStateMask;
+        UInt32 nextRepMatchPrice = curAnd1Price + 
+            _isMatch[state2.Index][posStateNext].GetPrice1() +
+            _isRep[state2.Index].GetPrice1();
+        // for (; lenTest2 >= 2; lenTest2--)
+        {
+          UInt32 offset = cur + 1 + lenTest2;
+          while(lenEnd < offset)
+            _optimum[++lenEnd].Price = kIfinityPrice;
+          UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(
+              0, lenTest2, state2, posStateNext);
+          COptimal &optimum = _optimum[offset];
+          if (curAndLenPrice < optimum.Price) 
+          {
+            optimum.Price = curAndLenPrice;
+            optimum.PosPrev = cur + 1;
+            optimum.BackPrev = 0;
+            optimum.Prev1IsChar = true;
+            optimum.Prev2 = false;
+          }
+        }
+      }
+    }
+    
+    UInt32 startLen = 2; // speed optimization 
+    for(UInt32 repIndex = 0; repIndex < kNumRepDistances; repIndex++)
+    {
+      // UInt32 repLen = _matchFinder->GetMatchLen(0 - 1, reps[repIndex], newLen); // test it;
+      UInt32 backOffset = reps[repIndex] + 1;
+      if (data[0] != data[(size_t)0 - backOffset] ||
+          data[1] != data[(size_t)1 - backOffset])
+        continue;
+      UInt32 lenTest;
+      for (lenTest = 2; lenTest < numAvailableBytes && 
+          data[lenTest] == data[(size_t)lenTest - backOffset]; lenTest++);
+      while(lenEnd < cur + lenTest)
+        _optimum[++lenEnd].Price = kIfinityPrice;
+      UInt32 lenTestTemp = lenTest;
+      UInt32 price = repMatchPrice + GetPureRepPrice(repIndex, state, posState);
+      do
+      {
+        UInt32 curAndLenPrice = price + _repMatchLenEncoder.GetPrice(lenTest - 2, posState);
+        COptimal &optimum = _optimum[cur + lenTest];
+        if (curAndLenPrice < optimum.Price) 
+        {
+          optimum.Price = curAndLenPrice;
+          optimum.PosPrev = cur;
+          optimum.BackPrev = repIndex;
+          optimum.Prev1IsChar = false;
+        }
+      }
+      while(--lenTest >= 2);
+      lenTest = lenTestTemp;
+      
+      if (repIndex == 0)
+        startLen = lenTest + 1;
+        
+      // if (_maxMode)
+        {
+          UInt32 lenTest2 = lenTest + 1;
+          UInt32 limit = MyMin(numAvailableBytesFull, lenTest2 + _numFastBytes);
+          for (; lenTest2 < limit && 
+              data[lenTest2] == data[(size_t)lenTest2 - backOffset]; lenTest2++);
+          lenTest2 -= lenTest + 1;
+          if (lenTest2 >= 2)
+          {
+            CState state2 = state;
+            state2.UpdateRep();
+            UInt32 posStateNext = (position + lenTest) & _posStateMask;
+            UInt32 curAndLenCharPrice = 
+                price + _repMatchLenEncoder.GetPrice(lenTest - 2, posState) + 
+                _isMatch[state2.Index][posStateNext].GetPrice0() +
+                _literalEncoder.GetSubCoder(position + lenTest, data[(size_t)lenTest - 1])->GetPrice(
+                true, data[(size_t)lenTest - backOffset], data[lenTest]);
+            state2.UpdateChar();
+            posStateNext = (position + lenTest + 1) & _posStateMask;
+            UInt32 nextRepMatchPrice = curAndLenCharPrice + 
+                _isMatch[state2.Index][posStateNext].GetPrice1() +
+                _isRep[state2.Index].GetPrice1();
+            
+            // for(; lenTest2 >= 2; lenTest2--)
+            {
+              UInt32 offset = cur + lenTest + 1 + lenTest2;
+              while(lenEnd < offset)
+                _optimum[++lenEnd].Price = kIfinityPrice;
+              UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(
+                  0, lenTest2, state2, posStateNext);
+              COptimal &optimum = _optimum[offset];
+              if (curAndLenPrice < optimum.Price) 
+              {
+                optimum.Price = curAndLenPrice;
+                optimum.PosPrev = cur + lenTest + 1;
+                optimum.BackPrev = 0;
+                optimum.Prev1IsChar = true;
+                optimum.Prev2 = true;
+                optimum.PosPrev2 = cur;
+                optimum.BackPrev2 = repIndex;
+              }
+            }
+          }
+        }
+      }
+    
+    //    for(UInt32 lenTest = 2; lenTest <= newLen; lenTest++)
+    if (newLen > numAvailableBytes)
+    {
+      newLen = numAvailableBytes;
+      for (numDistancePairs = 0; newLen > matchDistances[numDistancePairs]; numDistancePairs += 2);
+      matchDistances[numDistancePairs] = newLen;
+      numDistancePairs += 2;
+    }
+    if (newLen >= startLen)
+    {
+      UInt32 normalMatchPrice = matchPrice + _isRep[state.Index].GetPrice0();
+      while(lenEnd < cur + newLen)
+        _optimum[++lenEnd].Price = kIfinityPrice;
+
+      UInt32 offs = 0;
+      while(startLen > matchDistances[offs])
+        offs += 2;
+      UInt32 curBack = matchDistances[offs + 1];
+      UInt32 posSlot = GetPosSlot2(curBack);
+      for(UInt32 lenTest = /*2*/ startLen; ; lenTest++)
+      {
+        UInt32 curAndLenPrice = normalMatchPrice;
+        UInt32 lenToPosState = GetLenToPosState(lenTest);
+        if (curBack < kNumFullDistances)
+          curAndLenPrice += _distancesPrices[lenToPosState][curBack];
+        else
+          curAndLenPrice += _posSlotPrices[lenToPosState][posSlot] + _alignPrices[curBack & kAlignMask];
+  
+        curAndLenPrice += _lenEncoder.GetPrice(lenTest - kMatchMinLen, posState);
+        
+        COptimal &optimum = _optimum[cur + lenTest];
+        if (curAndLenPrice < optimum.Price) 
+        {
+          optimum.Price = curAndLenPrice;
+          optimum.PosPrev = cur;
+          optimum.BackPrev = curBack + kNumRepDistances;
+          optimum.Prev1IsChar = false;
+        }
+
+        if (/*_maxMode && */lenTest == matchDistances[offs])
+        {
+          // Try Match + Literal + Rep0
+          UInt32 backOffset = curBack + 1;
+          UInt32 lenTest2 = lenTest + 1;
+          UInt32 limit = MyMin(numAvailableBytesFull, lenTest2 + _numFastBytes);
+          for (; lenTest2 < limit && 
+              data[lenTest2] == data[(size_t)lenTest2 - backOffset]; lenTest2++);
+          lenTest2 -= lenTest + 1;
+          if (lenTest2 >= 2)
+          {
+            CState state2 = state;
+            state2.UpdateMatch();
+            UInt32 posStateNext = (position + lenTest) & _posStateMask;
+            UInt32 curAndLenCharPrice = curAndLenPrice + 
+                _isMatch[state2.Index][posStateNext].GetPrice0() +
+                _literalEncoder.GetSubCoder(position + lenTest, data[(size_t)lenTest - 1])->GetPrice( 
+                true, data[(size_t)lenTest - backOffset], data[lenTest]);
+            state2.UpdateChar();
+            posStateNext = (posStateNext + 1) & _posStateMask;
+            UInt32 nextRepMatchPrice = curAndLenCharPrice + 
+                _isMatch[state2.Index][posStateNext].GetPrice1() +
+                _isRep[state2.Index].GetPrice1();
+            
+            // for(; lenTest2 >= 2; lenTest2--)
+            {
+              UInt32 offset = cur + lenTest + 1 + lenTest2;
+              while(lenEnd < offset)
+                _optimum[++lenEnd].Price = kIfinityPrice;
+              UInt32 curAndLenPrice = nextRepMatchPrice + GetRepPrice(0, lenTest2, state2, posStateNext);
+              COptimal &optimum = _optimum[offset];
+              if (curAndLenPrice < optimum.Price) 
+              {
+                optimum.Price = curAndLenPrice;
+                optimum.PosPrev = cur + lenTest + 1;
+                optimum.BackPrev = 0;
+                optimum.Prev1IsChar = true;
+                optimum.Prev2 = true;
+                optimum.PosPrev2 = cur;
+                optimum.BackPrev2 = curBack + kNumRepDistances;
+              }
+            }
+          }
+          offs += 2;
+          if (offs == numDistancePairs)
+            break;
+          curBack = matchDistances[offs + 1];
+          if (curBack >= kNumFullDistances)
+            posSlot = GetPosSlot2(curBack);
+        }
+      }
+    }
+  }
+}
+
+static inline bool ChangePair(UInt32 smallDist, UInt32 bigDist)
+{
+  return ((bigDist >> 7) > smallDist);
+}
+
+
+HRESULT CEncoder::ReadMatchDistances(UInt32 &lenRes, UInt32 &numDistancePairs)
+{
+  lenRes = 0;
+  RINOK(_matchFinder->GetMatches(_matchDistances));
+  numDistancePairs = _matchDistances[0];
+  if (numDistancePairs > 0)
+  {
+    lenRes = _matchDistances[1 + numDistancePairs - 2];
+    if (lenRes == _numFastBytes)
+      lenRes += _matchFinder->GetMatchLen(lenRes - 1, _matchDistances[1 + numDistancePairs - 1], 
+          kMatchMaxLen - lenRes);
+  }
+  _additionalOffset++;
+  return S_OK;
+}
+
+HRESULT CEncoder::GetOptimumFast(UInt32 position, UInt32 &backRes, UInt32 &lenRes)
+{
+  UInt32 lenMain, numDistancePairs;
+  if (!_longestMatchWasFound)
+  {
+    RINOK(ReadMatchDistances(lenMain, numDistancePairs));
+  }
+  else
+  {
+    lenMain = _longestMatchLength;
+    numDistancePairs = _numDistancePairs;
+    _longestMatchWasFound = false;
+  }
+
+  const Byte *data = _matchFinder->GetPointerToCurrentPos() - 1;
+  UInt32 numAvailableBytes = _matchFinder->GetNumAvailableBytes() + 1;
+  if (numAvailableBytes > kMatchMaxLen)
+    numAvailableBytes = kMatchMaxLen;
+  if (numAvailableBytes < 2)
+  {
+    backRes = (UInt32)(-1);
+    lenRes = 1;
+    return S_OK;
+  }
+
+  UInt32 repLens[kNumRepDistances];
+  UInt32 repMaxIndex = 0;
+
+  for(UInt32 i = 0; i < kNumRepDistances; i++)
+  {
+    UInt32 backOffset = _repDistances[i] + 1;
+    if (data[0] != data[(size_t)0 - backOffset] || data[1] != data[(size_t)1 - backOffset])
+    {
+      repLens[i] = 0;
+      continue;
+    }
+    UInt32 len;
+    for (len = 2; len < numAvailableBytes && data[len] == data[(size_t)len - backOffset]; len++);
+    if(len >= _numFastBytes)
+    {
+      backRes = i;
+      lenRes = len;
+      return MovePos(lenRes - 1);
+    }
+    repLens[i] = len;
+    if (len > repLens[repMaxIndex])
+      repMaxIndex = i;
+  }
+  UInt32 *matchDistances = _matchDistances + 1;
+  if(lenMain >= _numFastBytes)
+  {
+    backRes = matchDistances[numDistancePairs - 1] + kNumRepDistances; 
+    lenRes = lenMain;
+    return MovePos(lenMain - 1);
+  }
+
+  UInt32 backMain = 0;
+  if (lenMain >= 2)
+  {
+    backMain = matchDistances[numDistancePairs - 1];
+    while (numDistancePairs > 2 && lenMain == matchDistances[numDistancePairs - 4] + 1)
+    {
+      if (!ChangePair(matchDistances[numDistancePairs - 3], backMain))
+        break;
+      numDistancePairs -= 2;
+      lenMain = matchDistances[numDistancePairs - 2];
+      backMain = matchDistances[numDistancePairs - 1];
+    }
+    if (lenMain == 2 && backMain >= 0x80)
+      lenMain = 1;
+  }
+
+  if (repLens[repMaxIndex] >= 2)
+  {
+    if (repLens[repMaxIndex] + 1 >= lenMain || 
+        repLens[repMaxIndex] + 2 >= lenMain && (backMain > (1 << 9)) ||
+        repLens[repMaxIndex] + 3 >= lenMain && (backMain > (1 << 15)))
+    {
+      backRes = repMaxIndex;
+      lenRes = repLens[repMaxIndex];
+      return MovePos(lenRes - 1);
+    }
+  }
+  
+  if (lenMain >= 2 && numAvailableBytes > 2)
+  {
+    RINOK(ReadMatchDistances(_longestMatchLength, _numDistancePairs));
+    if (_longestMatchLength >= 2)
+    {
+      UInt32 newDistance = matchDistances[_numDistancePairs - 1];
+      if (_longestMatchLength >= lenMain && newDistance < backMain || 
+          _longestMatchLength == lenMain + 1 && !ChangePair(backMain, newDistance) ||
+          _longestMatchLength > lenMain + 1 ||
+          _longestMatchLength + 1 >= lenMain && lenMain >= 3 && ChangePair(newDistance, backMain))
+      {
+        _longestMatchWasFound = true;
+        backRes = UInt32(-1);
+        lenRes = 1;
+        return S_OK;
+      }
+    }
+    data++;
+    numAvailableBytes--;
+    for(UInt32 i = 0; i < kNumRepDistances; i++)
+    {
+      UInt32 backOffset = _repDistances[i] + 1;
+      if (data[1] != data[(size_t)1 - backOffset] || data[2] != data[(size_t)2 - backOffset])
+      {
+        repLens[i] = 0;
+        continue;
+      }
+      UInt32 len;
+      for (len = 2; len < numAvailableBytes && data[len] == data[(size_t)len - backOffset]; len++);
+      if (len + 1 >= lenMain)
+      {
+        _longestMatchWasFound = true;
+        backRes = UInt32(-1);
+        lenRes = 1;
+        return S_OK;
+      }
+    }
+    backRes = backMain + kNumRepDistances; 
+    lenRes = lenMain;
+    return MovePos(lenMain - 2);
+  }
+  backRes = UInt32(-1);
+  lenRes = 1;
+  return S_OK;
+}
+
+HRESULT CEncoder::Flush(UInt32 nowPos)
+{
+  ReleaseMFStream();
+  WriteEndMarker(nowPos & _posStateMask);
+  _rangeEncoder.FlushData();
+  return _rangeEncoder.FlushStream();
+}
+
+void CEncoder::WriteEndMarker(UInt32 posState)
+{
+  // This function for writing End Mark for stream version of LZMA. 
+  // In current version this feature is not used.
+  if (!_writeEndMark)
+    return;
+
+  _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 1);
+  _isRep[_state.Index].Encode(&_rangeEncoder, 0);
+  _state.UpdateMatch();
+  UInt32 len = kMatchMinLen; // kMatchMaxLen;
+  _lenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
+  UInt32 posSlot = (1 << kNumPosSlotBits)  - 1;
+  UInt32 lenToPosState = GetLenToPosState(len);
+  _posSlotEncoder[lenToPosState].Encode(&_rangeEncoder, posSlot);
+  UInt32 footerBits = 30;
+  UInt32 posReduced = (UInt32(1) << footerBits) - 1;
+  _rangeEncoder.EncodeDirectBits(posReduced >> kNumAlignBits, footerBits - kNumAlignBits);
+  _posAlignEncoder.ReverseEncode(&_rangeEncoder, posReduced & kAlignMask);
+}
+
+HRESULT CEncoder::CodeReal(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream, 
+      const UInt64 *inSize, const UInt64 *outSize,
+      ICompressProgressInfo *progress)
+{
+  _needReleaseMFStream = false;
+  CCoderReleaser coderReleaser(this);
+  RINOK(SetStreams(inStream, outStream, inSize, outSize));
+  while(true)
+  {
+    UInt64 processedInSize;
+    UInt64 processedOutSize;
+    Int32 finished;
+    RINOK(CodeOneBlock(&processedInSize, &processedOutSize, &finished));
+    if (finished != 0)
+      return S_OK;
+    if (progress != 0)
+    {
+      RINOK(progress->SetRatioInfo(&processedInSize, &processedOutSize));
+    }
+  }
+}
+
+HRESULT CEncoder::SetStreams(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream, 
+      const UInt64 *inSize, const UInt64 *outSize)
+{
+  _inStream = inStream;
+  _finished = false;
+  RINOK(Create());
+  RINOK(SetOutStream(outStream));
+  RINOK(Init());
+  
+  // CCoderReleaser releaser(this);
+
+  /*
+  if (_matchFinder->GetNumAvailableBytes() == 0)
+    return Flush();
+  */
+
+  if (!_fastMode)
+  {
+    FillDistancesPrices();
+    FillAlignPrices();
+  }
+
+  _lenEncoder.SetTableSize(_numFastBytes + 1 - kMatchMinLen);
+  _lenEncoder.UpdateTables(1 << _posStateBits);
+  _repMatchLenEncoder.SetTableSize(_numFastBytes + 1 - kMatchMinLen);
+  _repMatchLenEncoder.UpdateTables(1 << _posStateBits);
+
+  nowPos64 = 0;
+  return S_OK;
+}
+
+HRESULT CEncoder::CodeOneBlock(UInt64 *inSize, UInt64 *outSize, Int32 *finished)
+{
+  if (_inStream != 0)
+  {
+    RINOK(_matchFinder->SetStream(_inStream));
+    RINOK(_matchFinder->Init());
+    _needReleaseMFStream = true;
+    _inStream = 0;
+  }
+
+
+  *finished = 1;
+  if (_finished)
+    return S_OK;
+  _finished = true;
+
+  if (nowPos64 == 0)
+  {
+    if (_matchFinder->GetNumAvailableBytes() == 0)
+      return Flush(UInt32(nowPos64));
+    UInt32 len, numDistancePairs;
+    RINOK(ReadMatchDistances(len, numDistancePairs));
+    UInt32 posState = UInt32(nowPos64) & _posStateMask;
+    _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 0);
+    _state.UpdateChar();
+    Byte curByte = _matchFinder->GetIndexByte(0 - _additionalOffset);
+    _literalEncoder.GetSubCoder(UInt32(nowPos64), _previousByte)->Encode(&_rangeEncoder, curByte);
+    _previousByte = curByte;
+    _additionalOffset--;
+    nowPos64++;
+  }
+
+  UInt32 nowPos32 = (UInt32)nowPos64;
+  UInt32 progressPosValuePrev = nowPos32;
+
+  if (_matchFinder->GetNumAvailableBytes() == 0)
+    return Flush(nowPos32);
+
+  while(true)
+  {
+    #ifdef _NO_EXCEPTIONS
+    if (_rangeEncoder.Stream.ErrorCode != S_OK)
+      return _rangeEncoder.Stream.ErrorCode;
+    #endif
+    UInt32 pos, len;
+    HRESULT result;
+    if (_fastMode)
+      result = GetOptimumFast(nowPos32, pos, len);
+    else
+      result = GetOptimum(nowPos32, pos, len);
+    RINOK(result);
+
+    UInt32 posState = nowPos32 & _posStateMask;
+    if(len == 1 && pos == 0xFFFFFFFF)
+    {
+      _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 0);
+      Byte curByte = _matchFinder->GetIndexByte(0 - _additionalOffset);
+      CLiteralEncoder2 *subCoder = _literalEncoder.GetSubCoder(nowPos32, _previousByte);
+      if(_state.IsCharState())
+        subCoder->Encode(&_rangeEncoder, curByte);
+      else
+      {
+        Byte matchByte = _matchFinder->GetIndexByte(0 - _repDistances[0] - 1 - _additionalOffset);
+        subCoder->EncodeMatched(&_rangeEncoder, matchByte, curByte);
+      }
+      _state.UpdateChar();
+      _previousByte = curByte;
+    }
+    else
+    {
+      _isMatch[_state.Index][posState].Encode(&_rangeEncoder, 1);
+      if(pos < kNumRepDistances)
+      {
+        _isRep[_state.Index].Encode(&_rangeEncoder, 1);
+        if(pos == 0)
+        {
+          _isRepG0[_state.Index].Encode(&_rangeEncoder, 0);
+          _isRep0Long[_state.Index][posState].Encode(&_rangeEncoder, ((len == 1) ? 0 : 1));
+        }
+        else
+        {
+          UInt32 distance = _repDistances[pos];
+          _isRepG0[_state.Index].Encode(&_rangeEncoder, 1);
+          if (pos == 1)
+            _isRepG1[_state.Index].Encode(&_rangeEncoder, 0);
+          else
+          {
+            _isRepG1[_state.Index].Encode(&_rangeEncoder, 1);
+            _isRepG2[_state.Index].Encode(&_rangeEncoder, pos - 2);
+            if (pos == 3)
+              _repDistances[3] = _repDistances[2];
+            _repDistances[2] = _repDistances[1];
+          }
+          _repDistances[1] = _repDistances[0];
+          _repDistances[0] = distance;
+        }
+        if (len == 1)
+          _state.UpdateShortRep();
+        else
+        {
+          _repMatchLenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
+          _state.UpdateRep();
+        }
+      }
+      else
+      {
+        _isRep[_state.Index].Encode(&_rangeEncoder, 0);
+        _state.UpdateMatch();
+        _lenEncoder.Encode(&_rangeEncoder, len - kMatchMinLen, posState, !_fastMode);
+        pos -= kNumRepDistances;
+        UInt32 posSlot = GetPosSlot(pos);
+        _posSlotEncoder[GetLenToPosState(len)].Encode(&_rangeEncoder, posSlot);
+        
+        if (posSlot >= kStartPosModelIndex)
+        {
+          UInt32 footerBits = ((posSlot >> 1) - 1);
+          UInt32 base = ((2 | (posSlot & 1)) << footerBits);
+          UInt32 posReduced = pos - base;
+
+          if (posSlot < kEndPosModelIndex)
+            NRangeCoder::ReverseBitTreeEncode(_posEncoders + base - posSlot - 1, 
+                &_rangeEncoder, footerBits, posReduced);
+          else
+          {
+            _rangeEncoder.EncodeDirectBits(posReduced >> kNumAlignBits, footerBits - kNumAlignBits);
+            _posAlignEncoder.ReverseEncode(&_rangeEncoder, posReduced & kAlignMask);
+            _alignPriceCount++;
+          }
+        }
+        _repDistances[3] = _repDistances[2];
+        _repDistances[2] = _repDistances[1];
+        _repDistances[1] = _repDistances[0];
+        _repDistances[0] = pos;
+        _matchPriceCount++;
+      }
+      _previousByte = _matchFinder->GetIndexByte(len - 1 - _additionalOffset);
+    }
+    _additionalOffset -= len;
+    nowPos32 += len;
+    if (_additionalOffset == 0)
+    {
+      if (!_fastMode)
+      {
+        if (_matchPriceCount >= (1 << 7))
+          FillDistancesPrices();
+        if (_alignPriceCount >= kAlignTableSize)
+          FillAlignPrices();
+      }
+      if (_matchFinder->GetNumAvailableBytes() == 0)
+        return Flush(nowPos32);
+      if (nowPos32 - progressPosValuePrev >= (1 << 14))
+      {
+        nowPos64 += nowPos32 - progressPosValuePrev;
+        *inSize = nowPos64;
+        *outSize = _rangeEncoder.GetProcessedSize();
+        _finished = false;
+        *finished = 0;
+        return S_OK;
+      }
+    }
+  }
+}
+
+STDMETHODIMP CEncoder::Code(ISequentialInStream *inStream,
+    ISequentialOutStream *outStream, const UInt64 *inSize, const UInt64 *outSize,
+    ICompressProgressInfo *progress)
+{
+  #ifndef _NO_EXCEPTIONS
+  try 
+  { 
+  #endif
+    return CodeReal(inStream, outStream, inSize, outSize, progress); 
+  #ifndef _NO_EXCEPTIONS
+  }
+  catch(const COutBufferException &e) { return e.ErrorCode; }
+  catch(...) { return E_FAIL; }
+  #endif
+}
+  
+void CEncoder::FillDistancesPrices()
+{
+  UInt32 tempPrices[kNumFullDistances];
+  for (UInt32 i = kStartPosModelIndex; i < kNumFullDistances; i++)
+  { 
+    UInt32 posSlot = GetPosSlot(i);
+    UInt32 footerBits = ((posSlot >> 1) - 1);
+    UInt32 base = ((2 | (posSlot & 1)) << footerBits);
+    tempPrices[i] = NRangeCoder::ReverseBitTreeGetPrice(_posEncoders + 
+      base - posSlot - 1, footerBits, i - base);
+  }
+
+  for (UInt32 lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)
+  {
+	  UInt32 posSlot;
+    NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumPosSlotBits> &encoder = _posSlotEncoder[lenToPosState];
+    UInt32 *posSlotPrices = _posSlotPrices[lenToPosState];
+    for (posSlot = 0; posSlot < _distTableSize; posSlot++)
+      posSlotPrices[posSlot] = encoder.GetPrice(posSlot);
+    for (posSlot = kEndPosModelIndex; posSlot < _distTableSize; posSlot++)
+      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << NRangeCoder::kNumBitPriceShiftBits);
+
+    UInt32 *distancesPrices = _distancesPrices[lenToPosState];
+	  UInt32 i;
+    for (i = 0; i < kStartPosModelIndex; i++)
+      distancesPrices[i] = posSlotPrices[i];
+    for (; i < kNumFullDistances; i++)
+      distancesPrices[i] = posSlotPrices[GetPosSlot(i)] + tempPrices[i];
+  }
+  _matchPriceCount = 0;
+}
+
+void CEncoder::FillAlignPrices()
+{
+  for (UInt32 i = 0; i < kAlignTableSize; i++)
+    _alignPrices[i] = _posAlignEncoder.ReverseGetPrice(i);
+  _alignPriceCount = 0;
+}
+
+}}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/LZMAEncoder.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,411 +1,411 @@
-// LZMA/Encoder.h
-
-#ifndef __LZMA_ENCODER_H
-#define __LZMA_ENCODER_H
-
-#include "../../../Common/MyCom.h"
-#include "../../../Common/Alloc.h"
-#include "../../ICoder.h"
-#include "../LZ/IMatchFinder.h"
-#include "../RangeCoder/RangeCoderBitTree.h"
-
-#include "LZMA.h"
-
-namespace NCompress {
-namespace NLZMA {
-
-typedef NRangeCoder::CBitEncoder<kNumMoveBits> CMyBitEncoder;
-
-class CBaseState
-{
-protected:
-  CState _state;
-  Byte _previousByte;
-  UInt32 _repDistances[kNumRepDistances];
-  void Init()
-  {
-    _state.Init();
-    _previousByte = 0;
-    for(UInt32 i = 0 ; i < kNumRepDistances; i++)
-      _repDistances[i] = 0;
-  }
-};
-
-struct COptimal
-{
-  CState State;
-
-  bool Prev1IsChar;
-  bool Prev2;
-
-  UInt32 PosPrev2;
-  UInt32 BackPrev2;     
-
-  UInt32 Price;    
-  UInt32 PosPrev;         // posNext;
-  UInt32 BackPrev;     
-  UInt32 Backs[kNumRepDistances];
-  void MakeAsChar() { BackPrev = UInt32(-1); Prev1IsChar = false; }
-  void MakeAsShortRep() { BackPrev = 0; ; Prev1IsChar = false; }
-  bool IsShortRep() { return (BackPrev == 0); }
-};
-
-
-extern Byte g_FastPos[1 << 11];
-inline UInt32 GetPosSlot(UInt32 pos)
-{
-  if (pos < (1 << 11))
-    return g_FastPos[pos];
-  if (pos < (1 << 21))
-    return g_FastPos[pos >> 10] + 20;
-  return g_FastPos[pos >> 20] + 40;
-}
-
-inline UInt32 GetPosSlot2(UInt32 pos)
-{
-  if (pos < (1 << 17))
-    return g_FastPos[pos >> 6] + 12;
-  if (pos < (1 << 27))
-    return g_FastPos[pos >> 16] + 32;
-  return g_FastPos[pos >> 26] + 52;
-}
-
-const UInt32 kIfinityPrice = 0xFFFFFFF;
-
-const UInt32 kNumOpts = 1 << 12;
-
-
-class CLiteralEncoder2
-{
-  CMyBitEncoder _encoders[0x300];
-public:
-  void Init()
-  {
-    for (int i = 0; i < 0x300; i++)
-      _encoders[i].Init();
-  }
-  void Encode(NRangeCoder::CEncoder *rangeEncoder, Byte symbol);
-  void EncodeMatched(NRangeCoder::CEncoder *rangeEncoder, Byte matchByte, Byte symbol);
-  UInt32 GetPrice(bool matchMode, Byte matchByte, Byte symbol) const;
-};
-
-class CLiteralEncoder
-{
-  CLiteralEncoder2 *_coders;
-  int _numPrevBits;
-  int _numPosBits;
-  UInt32 _posMask;
-public:
-  CLiteralEncoder(): _coders(0) {}
-  ~CLiteralEncoder()  { Free(); }
-  void Free()
-  { 
-    MyFree(_coders);
-    _coders = 0;
-  }
-  bool Create(int numPosBits, int numPrevBits)
-  {
-    if (_coders == 0 || (numPosBits + numPrevBits) != (_numPrevBits + _numPosBits))
-    {
-      Free();
-      UInt32 numStates = 1 << (numPosBits + numPrevBits);
-      _coders = (CLiteralEncoder2 *)MyAlloc(numStates * sizeof(CLiteralEncoder2));
-    }
-    _numPosBits = numPosBits;
-    _posMask = (1 << numPosBits) - 1;
-    _numPrevBits = numPrevBits;
-    return (_coders != 0);
-  }
-  void Init()
-  {
-    UInt32 numStates = 1 << (_numPrevBits + _numPosBits);
-    for (UInt32 i = 0; i < numStates; i++)
-      _coders[i].Init();
-  }
-  CLiteralEncoder2 *GetSubCoder(UInt32 pos, Byte prevByte)
-    { return &_coders[((pos & _posMask) << _numPrevBits) + (prevByte >> (8 - _numPrevBits))]; }
-};
-
-namespace NLength {
-
-class CEncoder
-{
-  CMyBitEncoder _choice;
-  CMyBitEncoder _choice2;
-  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumLowBits> _lowCoder[kNumPosStatesEncodingMax];
-  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumMidBits> _midCoder[kNumPosStatesEncodingMax];
-  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumHighBits> _highCoder;
-public:
-  void Init(UInt32 numPosStates);
-  void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState);
-  void SetPrices(UInt32 posState, UInt32 numSymbols, UInt32 *prices) const;
-};
-
-const UInt32 kNumSpecSymbols = kNumLowSymbols + kNumMidSymbols;
-
-class CPriceTableEncoder: public CEncoder
-{
-  UInt32 _prices[kNumPosStatesEncodingMax][kNumSymbolsTotal];
-  UInt32 _tableSize;
-  UInt32 _counters[kNumPosStatesEncodingMax];
-public:
-  void SetTableSize(UInt32 tableSize) { _tableSize = tableSize;  }
-  UInt32 GetPrice(UInt32 symbol, UInt32 posState) const { return _prices[posState][symbol]; }
-  void UpdateTable(UInt32 posState)
-  {
-    SetPrices(posState, _tableSize, _prices[posState]);
-    _counters[posState] = _tableSize;
-  }
-  void UpdateTables(UInt32 numPosStates)
-  {
-    for (UInt32 posState = 0; posState < numPosStates; posState++)
-      UpdateTable(posState);
-  }
-  void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState, bool updatePrice)
-  {
-    CEncoder::Encode(rangeEncoder, symbol, posState);
-    if (updatePrice)
-      if (--_counters[posState] == 0)
-        UpdateTable(posState);
-  }
-};
-
-}
-
-class CEncoder : 
-  public ICompressCoder,
-  public ICompressSetOutStream,
-  public ICompressSetCoderProperties,
-  public ICompressWriteCoderProperties,
-  public CBaseState,
-  public CMyUnknownImp
-{
-  COptimal _optimum[kNumOpts];
-  CMyComPtr<IMatchFinder> _matchFinder; // test it
-  NRangeCoder::CEncoder _rangeEncoder;
-
-  CMyBitEncoder _isMatch[kNumStates][NLength::kNumPosStatesEncodingMax];
-  CMyBitEncoder _isRep[kNumStates];
-  CMyBitEncoder _isRepG0[kNumStates];
-  CMyBitEncoder _isRepG1[kNumStates];
-  CMyBitEncoder _isRepG2[kNumStates];
-  CMyBitEncoder _isRep0Long[kNumStates][NLength::kNumPosStatesEncodingMax];
-
-  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumPosSlotBits> _posSlotEncoder[kNumLenToPosStates];
-
-  CMyBitEncoder _posEncoders[kNumFullDistances - kEndPosModelIndex];
-  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumAlignBits> _posAlignEncoder;
-  
-  NLength::CPriceTableEncoder _lenEncoder;
-  NLength::CPriceTableEncoder _repMatchLenEncoder;
-
-  CLiteralEncoder _literalEncoder;
-
-  UInt32 _matchDistances[kMatchMaxLen * 2 + 2 + 1];
-
-  bool _fastMode;
-  // bool _maxMode;
-  UInt32 _numFastBytes;
-  UInt32 _longestMatchLength;    
-  UInt32 _numDistancePairs;
-
-  UInt32 _additionalOffset;
-
-  UInt32 _optimumEndIndex;
-  UInt32 _optimumCurrentIndex;
-
-  bool _longestMatchWasFound;
-
-  UInt32 _posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];
-  
-  UInt32 _distancesPrices[kNumLenToPosStates][kNumFullDistances];
-
-  UInt32 _alignPrices[kAlignTableSize];
-  UInt32 _alignPriceCount;
-
-  UInt32 _distTableSize;
-
-  UInt32 _posStateBits;
-  UInt32 _posStateMask;
-  UInt32 _numLiteralPosStateBits;
-  UInt32 _numLiteralContextBits;
-
-  UInt32 _dictionarySize;
-
-  UInt32 _dictionarySizePrev;
-  UInt32 _numFastBytesPrev;
-
-  UInt32 _matchPriceCount;
-  UInt64 nowPos64;
-  bool _finished;
-  ISequentialInStream *_inStream;
-
-  UInt32 _matchFinderCycles;
-  int _matchFinderIndex;
-  #ifdef COMPRESS_MF_MT
-  bool _multiThread;
-  #endif
-
-  bool _writeEndMark;
-
-  bool _needReleaseMFStream;
-
-  IMatchFinderSetNumPasses *setMfPasses;
-
-  void ReleaseMatchFinder()
-  {
-    setMfPasses = 0;
-    _matchFinder.Release();
-  }
-  
-  HRESULT ReadMatchDistances(UInt32 &len, UInt32 &numDistancePairs);
-
-  HRESULT MovePos(UInt32 num);
-  UInt32 GetRepLen1Price(CState state, UInt32 posState) const
-  {
-    return _isRepG0[state.Index].GetPrice0() +
-        _isRep0Long[state.Index][posState].GetPrice0();
-  }
-  
-  UInt32 GetPureRepPrice(UInt32 repIndex, CState state, UInt32 posState) const
-  {
-    UInt32 price;
-    if(repIndex == 0)
-    {
-      price = _isRepG0[state.Index].GetPrice0();
-      price += _isRep0Long[state.Index][posState].GetPrice1();
-    }
-    else
-    {
-      price = _isRepG0[state.Index].GetPrice1();
-      if (repIndex == 1)
-        price += _isRepG1[state.Index].GetPrice0();
-      else
-      {
-        price += _isRepG1[state.Index].GetPrice1();
-        price += _isRepG2[state.Index].GetPrice(repIndex - 2);
-      }
-    }
-    return price;
-  }
-  UInt32 GetRepPrice(UInt32 repIndex, UInt32 len, CState state, UInt32 posState) const
-  {
-    return _repMatchLenEncoder.GetPrice(len - kMatchMinLen, posState) +
-        GetPureRepPrice(repIndex, state, posState);
-  }
-  /*
-  UInt32 GetPosLen2Price(UInt32 pos, UInt32 posState) const
-  {
-    if (pos >= kNumFullDistances)
-      return kIfinityPrice;
-    return _distancesPrices[0][pos] + _lenEncoder.GetPrice(0, posState);
-  }
-  UInt32 GetPosLen3Price(UInt32 pos, UInt32 len, UInt32 posState) const
-  {
-    UInt32 price;
-    UInt32 lenToPosState = GetLenToPosState(len);
-    if (pos < kNumFullDistances)
-      price = _distancesPrices[lenToPosState][pos];
-    else
-      price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] + 
-          _alignPrices[pos & kAlignMask];
-    return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
-  }
-  */
-  UInt32 GetPosLenPrice(UInt32 pos, UInt32 len, UInt32 posState) const
-  {
-    UInt32 price;
-    UInt32 lenToPosState = GetLenToPosState(len);
-    if (pos < kNumFullDistances)
-      price = _distancesPrices[lenToPosState][pos];
-    else
-      price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] + 
-          _alignPrices[pos & kAlignMask];
-    return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
-  }
-
-  UInt32 Backward(UInt32 &backRes, UInt32 cur);
-  HRESULT GetOptimum(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
-  HRESULT GetOptimumFast(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
-
-  void FillDistancesPrices();
-  void FillAlignPrices();
-    
-  void ReleaseMFStream()
-  {
-    if (_matchFinder && _needReleaseMFStream)
-    {
-      _matchFinder->ReleaseStream();
-      _needReleaseMFStream = false;
-    }
-  }
-
-  void ReleaseStreams()
-  {
-    ReleaseMFStream();
-    ReleaseOutStream();
-  }
-
-  HRESULT Flush(UInt32 nowPos);
-  class CCoderReleaser
-  {
-    CEncoder *_coder;
-  public:
-    CCoderReleaser(CEncoder *coder): _coder(coder) {}
-    ~CCoderReleaser()
-    {
-      _coder->ReleaseStreams();
-    }
-  };
-  friend class CCoderReleaser;
-
-  void WriteEndMarker(UInt32 posState);
-
-public:
-  CEncoder();
-  void SetWriteEndMarkerMode(bool writeEndMarker)
-    { _writeEndMark= writeEndMarker; }
-
-  HRESULT Create();
-
-  MY_UNKNOWN_IMP3(
-      ICompressSetOutStream,
-      ICompressSetCoderProperties,
-      ICompressWriteCoderProperties
-      )
-    
-  HRESULT Init();
-  
-  // ICompressCoder interface
-  HRESULT SetStreams(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream,
-      const UInt64 *inSize, const UInt64 *outSize);
-  HRESULT CodeOneBlock(UInt64 *inSize, UInt64 *outSize, Int32 *finished);
-
-  HRESULT CodeReal(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream, 
-      const UInt64 *inSize, const UInt64 *outSize,
-      ICompressProgressInfo *progress);
-
-  // ICompressCoder interface
-  STDMETHOD(Code)(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream, 
-      const UInt64 *inSize, const UInt64 *outSize,
-      ICompressProgressInfo *progress);
-
-  // ICompressSetCoderProperties2
-  STDMETHOD(SetCoderProperties)(const PROPID *propIDs, 
-      const PROPVARIANT *properties, UInt32 numProperties);
-  
-  // ICompressWriteCoderProperties
-  STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStream);
-
-  STDMETHOD(SetOutStream)(ISequentialOutStream *outStream);
-  STDMETHOD(ReleaseOutStream)();
-
-  virtual ~CEncoder() {}
-};
-
-}}
-
-#endif
+// LZMA/Encoder.h
+
+#ifndef __LZMA_ENCODER_H
+#define __LZMA_ENCODER_H
+
+#include "../../../Common/MyCom.h"
+#include "../../../Common/Alloc.h"
+#include "../../ICoder.h"
+#include "../LZ/IMatchFinder.h"
+#include "../RangeCoder/RangeCoderBitTree.h"
+
+#include "LZMA.h"
+
+namespace NCompress {
+namespace NLZMA {
+
+typedef NRangeCoder::CBitEncoder<kNumMoveBits> CMyBitEncoder;
+
+class CBaseState
+{
+protected:
+  CState _state;
+  Byte _previousByte;
+  UInt32 _repDistances[kNumRepDistances];
+  void Init()
+  {
+    _state.Init();
+    _previousByte = 0;
+    for(UInt32 i = 0 ; i < kNumRepDistances; i++)
+      _repDistances[i] = 0;
+  }
+};
+
+struct COptimal
+{
+  CState State;
+
+  bool Prev1IsChar;
+  bool Prev2;
+
+  UInt32 PosPrev2;
+  UInt32 BackPrev2;     
+
+  UInt32 Price;    
+  UInt32 PosPrev;         // posNext;
+  UInt32 BackPrev;     
+  UInt32 Backs[kNumRepDistances];
+  void MakeAsChar() { BackPrev = UInt32(-1); Prev1IsChar = false; }
+  void MakeAsShortRep() { BackPrev = 0; ; Prev1IsChar = false; }
+  bool IsShortRep() { return (BackPrev == 0); }
+};
+
+
+extern Byte g_FastPos[1 << 11];
+inline UInt32 GetPosSlot(UInt32 pos)
+{
+  if (pos < (1 << 11))
+    return g_FastPos[pos];
+  if (pos < (1 << 21))
+    return g_FastPos[pos >> 10] + 20;
+  return g_FastPos[pos >> 20] + 40;
+}
+
+inline UInt32 GetPosSlot2(UInt32 pos)
+{
+  if (pos < (1 << 17))
+    return g_FastPos[pos >> 6] + 12;
+  if (pos < (1 << 27))
+    return g_FastPos[pos >> 16] + 32;
+  return g_FastPos[pos >> 26] + 52;
+}
+
+const UInt32 kIfinityPrice = 0xFFFFFFF;
+
+const UInt32 kNumOpts = 1 << 12;
+
+
+class CLiteralEncoder2
+{
+  CMyBitEncoder _encoders[0x300];
+public:
+  void Init()
+  {
+    for (int i = 0; i < 0x300; i++)
+      _encoders[i].Init();
+  }
+  void Encode(NRangeCoder::CEncoder *rangeEncoder, Byte symbol);
+  void EncodeMatched(NRangeCoder::CEncoder *rangeEncoder, Byte matchByte, Byte symbol);
+  UInt32 GetPrice(bool matchMode, Byte matchByte, Byte symbol) const;
+};
+
+class CLiteralEncoder
+{
+  CLiteralEncoder2 *_coders;
+  int _numPrevBits;
+  int _numPosBits;
+  UInt32 _posMask;
+public:
+  CLiteralEncoder(): _coders(0) {}
+  ~CLiteralEncoder()  { Free(); }
+  void Free()
+  { 
+    MyFree(_coders);
+    _coders = 0;
+  }
+  bool Create(int numPosBits, int numPrevBits)
+  {
+    if (_coders == 0 || (numPosBits + numPrevBits) != (_numPrevBits + _numPosBits))
+    {
+      Free();
+      UInt32 numStates = 1 << (numPosBits + numPrevBits);
+      _coders = (CLiteralEncoder2 *)MyAlloc(numStates * sizeof(CLiteralEncoder2));
+    }
+    _numPosBits = numPosBits;
+    _posMask = (1 << numPosBits) - 1;
+    _numPrevBits = numPrevBits;
+    return (_coders != 0);
+  }
+  void Init()
+  {
+    UInt32 numStates = 1 << (_numPrevBits + _numPosBits);
+    for (UInt32 i = 0; i < numStates; i++)
+      _coders[i].Init();
+  }
+  CLiteralEncoder2 *GetSubCoder(UInt32 pos, Byte prevByte)
+    { return &_coders[((pos & _posMask) << _numPrevBits) + (prevByte >> (8 - _numPrevBits))]; }
+};
+
+namespace NLength {
+
+class CEncoder
+{
+  CMyBitEncoder _choice;
+  CMyBitEncoder _choice2;
+  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumLowBits> _lowCoder[kNumPosStatesEncodingMax];
+  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumMidBits> _midCoder[kNumPosStatesEncodingMax];
+  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumHighBits> _highCoder;
+public:
+  void Init(UInt32 numPosStates);
+  void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState);
+  void SetPrices(UInt32 posState, UInt32 numSymbols, UInt32 *prices) const;
+};
+
+const UInt32 kNumSpecSymbols = kNumLowSymbols + kNumMidSymbols;
+
+class CPriceTableEncoder: public CEncoder
+{
+  UInt32 _prices[kNumPosStatesEncodingMax][kNumSymbolsTotal];
+  UInt32 _tableSize;
+  UInt32 _counters[kNumPosStatesEncodingMax];
+public:
+  void SetTableSize(UInt32 tableSize) { _tableSize = tableSize;  }
+  UInt32 GetPrice(UInt32 symbol, UInt32 posState) const { return _prices[posState][symbol]; }
+  void UpdateTable(UInt32 posState)
+  {
+    SetPrices(posState, _tableSize, _prices[posState]);
+    _counters[posState] = _tableSize;
+  }
+  void UpdateTables(UInt32 numPosStates)
+  {
+    for (UInt32 posState = 0; posState < numPosStates; posState++)
+      UpdateTable(posState);
+  }
+  void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState, bool updatePrice)
+  {
+    CEncoder::Encode(rangeEncoder, symbol, posState);
+    if (updatePrice)
+      if (--_counters[posState] == 0)
+        UpdateTable(posState);
+  }
+};
+
+}
+
+class CEncoder : 
+  public ICompressCoder,
+  public ICompressSetOutStream,
+  public ICompressSetCoderProperties,
+  public ICompressWriteCoderProperties,
+  public CBaseState,
+  public CMyUnknownImp
+{
+  COptimal _optimum[kNumOpts];
+  CMyComPtr<IMatchFinder> _matchFinder; // test it
+  NRangeCoder::CEncoder _rangeEncoder;
+
+  CMyBitEncoder _isMatch[kNumStates][NLength::kNumPosStatesEncodingMax];
+  CMyBitEncoder _isRep[kNumStates];
+  CMyBitEncoder _isRepG0[kNumStates];
+  CMyBitEncoder _isRepG1[kNumStates];
+  CMyBitEncoder _isRepG2[kNumStates];
+  CMyBitEncoder _isRep0Long[kNumStates][NLength::kNumPosStatesEncodingMax];
+
+  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumPosSlotBits> _posSlotEncoder[kNumLenToPosStates];
+
+  CMyBitEncoder _posEncoders[kNumFullDistances - kEndPosModelIndex];
+  NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumAlignBits> _posAlignEncoder;
+  
+  NLength::CPriceTableEncoder _lenEncoder;
+  NLength::CPriceTableEncoder _repMatchLenEncoder;
+
+  CLiteralEncoder _literalEncoder;
+
+  UInt32 _matchDistances[kMatchMaxLen * 2 + 2 + 1];
+
+  bool _fastMode;
+  // bool _maxMode;
+  UInt32 _numFastBytes;
+  UInt32 _longestMatchLength;    
+  UInt32 _numDistancePairs;
+
+  UInt32 _additionalOffset;
+
+  UInt32 _optimumEndIndex;
+  UInt32 _optimumCurrentIndex;
+
+  bool _longestMatchWasFound;
+
+  UInt32 _posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];
+  
+  UInt32 _distancesPrices[kNumLenToPosStates][kNumFullDistances];
+
+  UInt32 _alignPrices[kAlignTableSize];
+  UInt32 _alignPriceCount;
+
+  UInt32 _distTableSize;
+
+  UInt32 _posStateBits;
+  UInt32 _posStateMask;
+  UInt32 _numLiteralPosStateBits;
+  UInt32 _numLiteralContextBits;
+
+  UInt32 _dictionarySize;
+
+  UInt32 _dictionarySizePrev;
+  UInt32 _numFastBytesPrev;
+
+  UInt32 _matchPriceCount;
+  UInt64 nowPos64;
+  bool _finished;
+  ISequentialInStream *_inStream;
+
+  UInt32 _matchFinderCycles;
+  int _matchFinderIndex;
+  #ifdef COMPRESS_MF_MT
+  bool _multiThread;
+  #endif
+
+  bool _writeEndMark;
+
+  bool _needReleaseMFStream;
+
+  IMatchFinderSetNumPasses *setMfPasses;
+
+  void ReleaseMatchFinder()
+  {
+    setMfPasses = 0;
+    _matchFinder.Release();
+  }
+  
+  HRESULT ReadMatchDistances(UInt32 &len, UInt32 &numDistancePairs);
+
+  HRESULT MovePos(UInt32 num);
+  UInt32 GetRepLen1Price(CState state, UInt32 posState) const
+  {
+    return _isRepG0[state.Index].GetPrice0() +
+        _isRep0Long[state.Index][posState].GetPrice0();
+  }
+  
+  UInt32 GetPureRepPrice(UInt32 repIndex, CState state, UInt32 posState) const
+  {
+    UInt32 price;
+    if(repIndex == 0)
+    {
+      price = _isRepG0[state.Index].GetPrice0();
+      price += _isRep0Long[state.Index][posState].GetPrice1();
+    }
+    else
+    {
+      price = _isRepG0[state.Index].GetPrice1();
+      if (repIndex == 1)
+        price += _isRepG1[state.Index].GetPrice0();
+      else
+      {
+        price += _isRepG1[state.Index].GetPrice1();
+        price += _isRepG2[state.Index].GetPrice(repIndex - 2);
+      }
+    }
+    return price;
+  }
+  UInt32 GetRepPrice(UInt32 repIndex, UInt32 len, CState state, UInt32 posState) const
+  {
+    return _repMatchLenEncoder.GetPrice(len - kMatchMinLen, posState) +
+        GetPureRepPrice(repIndex, state, posState);
+  }
+  /*
+  UInt32 GetPosLen2Price(UInt32 pos, UInt32 posState) const
+  {
+    if (pos >= kNumFullDistances)
+      return kIfinityPrice;
+    return _distancesPrices[0][pos] + _lenEncoder.GetPrice(0, posState);
+  }
+  UInt32 GetPosLen3Price(UInt32 pos, UInt32 len, UInt32 posState) const
+  {
+    UInt32 price;
+    UInt32 lenToPosState = GetLenToPosState(len);
+    if (pos < kNumFullDistances)
+      price = _distancesPrices[lenToPosState][pos];
+    else
+      price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] + 
+          _alignPrices[pos & kAlignMask];
+    return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
+  }
+  */
+  UInt32 GetPosLenPrice(UInt32 pos, UInt32 len, UInt32 posState) const
+  {
+    UInt32 price;
+    UInt32 lenToPosState = GetLenToPosState(len);
+    if (pos < kNumFullDistances)
+      price = _distancesPrices[lenToPosState][pos];
+    else
+      price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] + 
+          _alignPrices[pos & kAlignMask];
+    return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
+  }
+
+  UInt32 Backward(UInt32 &backRes, UInt32 cur);
+  HRESULT GetOptimum(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
+  HRESULT GetOptimumFast(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
+
+  void FillDistancesPrices();
+  void FillAlignPrices();
+    
+  void ReleaseMFStream()
+  {
+    if (_matchFinder && _needReleaseMFStream)
+    {
+      _matchFinder->ReleaseStream();
+      _needReleaseMFStream = false;
+    }
+  }
+
+  void ReleaseStreams()
+  {
+    ReleaseMFStream();
+    ReleaseOutStream();
+  }
+
+  HRESULT Flush(UInt32 nowPos);
+  class CCoderReleaser
+  {
+    CEncoder *_coder;
+  public:
+    CCoderReleaser(CEncoder *coder): _coder(coder) {}
+    ~CCoderReleaser()
+    {
+      _coder->ReleaseStreams();
+    }
+  };
+  friend class CCoderReleaser;
+
+  void WriteEndMarker(UInt32 posState);
+
+public:
+  CEncoder();
+  void SetWriteEndMarkerMode(bool writeEndMarker)
+    { _writeEndMark= writeEndMarker; }
+
+  HRESULT Create();
+
+  MY_UNKNOWN_IMP3(
+      ICompressSetOutStream,
+      ICompressSetCoderProperties,
+      ICompressWriteCoderProperties
+      )
+    
+  HRESULT Init();
+  
+  // ICompressCoder interface
+  HRESULT SetStreams(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream,
+      const UInt64 *inSize, const UInt64 *outSize);
+  HRESULT CodeOneBlock(UInt64 *inSize, UInt64 *outSize, Int32 *finished);
+
+  HRESULT CodeReal(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream, 
+      const UInt64 *inSize, const UInt64 *outSize,
+      ICompressProgressInfo *progress);
+
+  // ICompressCoder interface
+  STDMETHOD(Code)(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream, 
+      const UInt64 *inSize, const UInt64 *outSize,
+      ICompressProgressInfo *progress);
+
+  // ICompressSetCoderProperties2
+  STDMETHOD(SetCoderProperties)(const PROPID *propIDs, 
+      const PROPVARIANT *properties, UInt32 numProperties);
+  
+  // ICompressWriteCoderProperties
+  STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStream);
+
+  STDMETHOD(SetOutStream)(ISequentialOutStream *outStream);
+  STDMETHOD(ReleaseOutStream)();
+
+  virtual ~CEncoder() {}
+};
+
+}}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/StdAfx.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/StdAfx.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZMA/StdAfx.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,8 +1,8 @@
-// StdAfx.h
-
-#ifndef __STDAFX_H
-#define __STDAFX_H
-
-#include "../../../Common/MyWindows.h"
-
-#endif
+// StdAfx.h
+
+#ifndef __STDAFX_H
+#define __STDAFX_H
+
+#include "../../../Common/MyWindows.h"
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoder.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoder.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoder.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,205 +1,205 @@
-// Compress/RangeCoder/RangeCoder.h
-
-#ifndef __COMPRESS_RANGECODER_H
-#define __COMPRESS_RANGECODER_H
-
-#include "../../Common/InBuffer.h"
-#include "../../Common/OutBuffer.h"
-
-namespace NCompress {
-namespace NRangeCoder {
-
-const int kNumTopBits = 24;
-const UInt32 kTopValue = (1 << kNumTopBits);
-
-class CEncoder
-{
-  UInt32 _cacheSize;
-  Byte _cache;
-public:
-  UInt64 Low;
-  UInt32 Range;
-  COutBuffer Stream;
-  bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
-
-  void SetStream(ISequentialOutStream *stream) { Stream.SetStream(stream); }
-  void Init()
-  {
-    Stream.Init();
-    Low = 0;
-    Range = 0xFFFFFFFF;
-    _cacheSize = 1;
-    _cache = 0;
-  }
-
-  void FlushData()
-  {
-    // Low += 1; 
-    for(int i = 0; i < 5; i++)
-      ShiftLow();
-  }
-
-  HRESULT FlushStream() { return Stream.Flush();  }
-
-  void ReleaseStream() { Stream.ReleaseStream(); }
-
-  void Encode(UInt32 start, UInt32 size, UInt32 total)
-  {
-    Low += start * (Range /= total);
-    Range *= size;
-    while (Range < kTopValue)
-    {
-      Range <<= 8;
-      ShiftLow();
-    }
-  }
-
-  void ShiftLow()
-  {
-    if ((UInt32)Low < (UInt32)0xFF000000 || (int)(Low >> 32) != 0) 
-    {
-      Byte temp = _cache;
-      do
-      {
-        Stream.WriteByte((Byte)(temp + (Byte)(Low >> 32)));
-        temp = 0xFF;
-      }
-      while(--_cacheSize != 0);
-      _cache = (Byte)((UInt32)Low >> 24);                      
-    } 
-    _cacheSize++;                               
-    Low = (UInt32)Low << 8;                           
-  }
-  
-  void EncodeDirectBits(UInt32 value, int numTotalBits)
-  {
-    for (int i = numTotalBits - 1; i >= 0; i--)
-    {
-      Range >>= 1;
-      if (((value >> i) & 1) == 1)
-        Low += Range;
-      if (Range < kTopValue)
-      {
-        Range <<= 8;
-        ShiftLow();
-      }
-    }
-  }
-
-  void EncodeBit(UInt32 size0, UInt32 numTotalBits, UInt32 symbol)
-  {
-    UInt32 newBound = (Range >> numTotalBits) * size0;
-    if (symbol == 0)
-      Range = newBound;
-    else
-    {
-      Low += newBound;
-      Range -= newBound;
-    }
-    while (Range < kTopValue)
-    {
-      Range <<= 8;
-      ShiftLow();
-    }
-  }
-
-  UInt64 GetProcessedSize() {  return Stream.GetProcessedSize() + _cacheSize + 4; }
-};
-
-class CDecoder
-{
-public:
-  CInBuffer Stream;
-  UInt32 Range;
-  UInt32 Code;
-  bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
-
-  void Normalize()
-  {
-    while (Range < kTopValue)
-    {
-      Code = (Code << 8) | Stream.ReadByte();
-      Range <<= 8;
-    }
-  }
-  
-  void SetStream(ISequentialInStream *stream) { Stream.SetStream(stream); }
-  void Init()
-  {
-    Stream.Init();
-    Code = 0;
-    Range = 0xFFFFFFFF;
-    for(int i = 0; i < 5; i++)
-      Code = (Code << 8) | Stream.ReadByte();
-  }
-
-  void ReleaseStream() { Stream.ReleaseStream(); }
-
-  UInt32 GetThreshold(UInt32 total)
-  {
-    return (Code) / ( Range /= total);
-  }
-
-  void Decode(UInt32 start, UInt32 size)
-  {
-    Code -= start * Range;
-    Range *= size;
-    Normalize();
-  }
-
-  UInt32 DecodeDirectBits(int numTotalBits)
-  {
-    UInt32 range = Range;
-    UInt32 code = Code;        
-    UInt32 result = 0;
-    for (int i = numTotalBits; i != 0; i--)
-    {
-      range >>= 1;
-      /*
-      result <<= 1;
-      if (code >= range)
-      {
-        code -= range;
-        result |= 1;
-      }
-      */
-      UInt32 t = (code - range) >> 31;
-      code -= range & (t - 1);
-      result = (result << 1) | (1 - t);
-
-      if (range < kTopValue)
-      {
-        code = (code << 8) | Stream.ReadByte();
-        range <<= 8; 
-      }
-    }
-    Range = range;
-    Code = code;
-    return result;
-  }
-
-  UInt32 DecodeBit(UInt32 size0, UInt32 numTotalBits)
-  {
-    UInt32 newBound = (Range >> numTotalBits) * size0;
-    UInt32 symbol;
-    if (Code < newBound)
-    {
-      symbol = 0;
-      Range = newBound;
-    }
-    else
-    {
-      symbol = 1;
-      Code -= newBound;
-      Range -= newBound;
-    }
-    Normalize();
-    return symbol;
-  }
-
-  UInt64 GetProcessedSize() {return Stream.GetProcessedSize(); }
-};
-
-}}
-
-#endif
+// Compress/RangeCoder/RangeCoder.h
+
+#ifndef __COMPRESS_RANGECODER_H
+#define __COMPRESS_RANGECODER_H
+
+#include "../../Common/InBuffer.h"
+#include "../../Common/OutBuffer.h"
+
+namespace NCompress {
+namespace NRangeCoder {
+
+const int kNumTopBits = 24;
+const UInt32 kTopValue = (1 << kNumTopBits);
+
+class CEncoder
+{
+  UInt32 _cacheSize;
+  Byte _cache;
+public:
+  UInt64 Low;
+  UInt32 Range;
+  COutBuffer Stream;
+  bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
+
+  void SetStream(ISequentialOutStream *stream) { Stream.SetStream(stream); }
+  void Init()
+  {
+    Stream.Init();
+    Low = 0;
+    Range = 0xFFFFFFFF;
+    _cacheSize = 1;
+    _cache = 0;
+  }
+
+  void FlushData()
+  {
+    // Low += 1; 
+    for(int i = 0; i < 5; i++)
+      ShiftLow();
+  }
+
+  HRESULT FlushStream() { return Stream.Flush();  }
+
+  void ReleaseStream() { Stream.ReleaseStream(); }
+
+  void Encode(UInt32 start, UInt32 size, UInt32 total)
+  {
+    Low += start * (Range /= total);
+    Range *= size;
+    while (Range < kTopValue)
+    {
+      Range <<= 8;
+      ShiftLow();
+    }
+  }
+
+  void ShiftLow()
+  {
+    if ((UInt32)Low < (UInt32)0xFF000000 || (int)(Low >> 32) != 0) 
+    {
+      Byte temp = _cache;
+      do
+      {
+        Stream.WriteByte((Byte)(temp + (Byte)(Low >> 32)));
+        temp = 0xFF;
+      }
+      while(--_cacheSize != 0);
+      _cache = (Byte)((UInt32)Low >> 24);                      
+    } 
+    _cacheSize++;                               
+    Low = (UInt32)Low << 8;                           
+  }
+  
+  void EncodeDirectBits(UInt32 value, int numTotalBits)
+  {
+    for (int i = numTotalBits - 1; i >= 0; i--)
+    {
+      Range >>= 1;
+      if (((value >> i) & 1) == 1)
+        Low += Range;
+      if (Range < kTopValue)
+      {
+        Range <<= 8;
+        ShiftLow();
+      }
+    }
+  }
+
+  void EncodeBit(UInt32 size0, UInt32 numTotalBits, UInt32 symbol)
+  {
+    UInt32 newBound = (Range >> numTotalBits) * size0;
+    if (symbol == 0)
+      Range = newBound;
+    else
+    {
+      Low += newBound;
+      Range -= newBound;
+    }
+    while (Range < kTopValue)
+    {
+      Range <<= 8;
+      ShiftLow();
+    }
+  }
+
+  UInt64 GetProcessedSize() {  return Stream.GetProcessedSize() + _cacheSize + 4; }
+};
+
+class CDecoder
+{
+public:
+  CInBuffer Stream;
+  UInt32 Range;
+  UInt32 Code;
+  bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
+
+  void Normalize()
+  {
+    while (Range < kTopValue)
+    {
+      Code = (Code << 8) | Stream.ReadByte();
+      Range <<= 8;
+    }
+  }
+  
+  void SetStream(ISequentialInStream *stream) { Stream.SetStream(stream); }
+  void Init()
+  {
+    Stream.Init();
+    Code = 0;
+    Range = 0xFFFFFFFF;
+    for(int i = 0; i < 5; i++)
+      Code = (Code << 8) | Stream.ReadByte();
+  }
+
+  void ReleaseStream() { Stream.ReleaseStream(); }
+
+  UInt32 GetThreshold(UInt32 total)
+  {
+    return (Code) / ( Range /= total);
+  }
+
+  void Decode(UInt32 start, UInt32 size)
+  {
+    Code -= start * Range;
+    Range *= size;
+    Normalize();
+  }
+
+  UInt32 DecodeDirectBits(int numTotalBits)
+  {
+    UInt32 range = Range;
+    UInt32 code = Code;        
+    UInt32 result = 0;
+    for (int i = numTotalBits; i != 0; i--)
+    {
+      range >>= 1;
+      /*
+      result <<= 1;
+      if (code >= range)
+      {
+        code -= range;
+        result |= 1;
+      }
+      */
+      UInt32 t = (code - range) >> 31;
+      code -= range & (t - 1);
+      result = (result << 1) | (1 - t);
+
+      if (range < kTopValue)
+      {
+        code = (code << 8) | Stream.ReadByte();
+        range <<= 8; 
+      }
+    }
+    Range = range;
+    Code = code;
+    return result;
+  }
+
+  UInt32 DecodeBit(UInt32 size0, UInt32 numTotalBits)
+  {
+    UInt32 newBound = (Range >> numTotalBits) * size0;
+    UInt32 symbol;
+    if (Code < newBound)
+    {
+      symbol = 0;
+      Range = newBound;
+    }
+    else
+    {
+      symbol = 1;
+      Code -= newBound;
+      Range -= newBound;
+    }
+    Normalize();
+    return symbol;
+  }
+
+  UInt64 GetProcessedSize() {return Stream.GetProcessedSize(); }
+};
+
+}}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,80 +1,80 @@
-// Compress/RangeCoder/RangeCoderBit.cpp
-
-#include "StdAfx.h"
-
-#include "RangeCoderBit.h"
-
-namespace NCompress {
-namespace NRangeCoder {
-
-UInt32 CPriceTables::ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
-static CPriceTables g_PriceTables;
-
-CPriceTables::CPriceTables() { Init(); }
-
-void CPriceTables::Init()
-{
-  const int kNumBits = (kNumBitModelTotalBits - kNumMoveReducingBits);
-  for(int i = kNumBits - 1; i >= 0; i--)
-  {
-    UInt32 start = 1 << (kNumBits - i - 1);
-    UInt32 end = 1 << (kNumBits - i);
-    for (UInt32 j = start; j < end; j++)
-      ProbPrices[j] = (i << kNumBitPriceShiftBits) + 
-          (((end - j) << kNumBitPriceShiftBits) >> (kNumBits - i - 1));
-  }
-
-  /*
-  // simplest: bad solution
-  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
-    ProbPrices[i] = kBitPrice;
-  */
-  
-  /*
-  const double kDummyMultMid = (1.0 / kBitPrice) / 2;
-  const double kDummyMultMid = 0;
-  // float solution
-  double ln2 = log(double(2));
-  double lnAll = log(double(kBitModelTotal >> kNumMoveReducingBits));
-  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
-    ProbPrices[i] = UInt32((fabs(lnAll - log(double(i))) / ln2 + kDummyMultMid) * kBitPrice);
-  */
-  
-  /*
-  // experimental, slow, solution:
-  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
-  {
-    const int kCyclesBits = 5;
-    const UInt32 kCycles = (1 << kCyclesBits);
-
-    UInt32 range = UInt32(-1);
-    UInt32 bitCount = 0;
-    for (UInt32 j = 0; j < kCycles; j++)
-    {
-      range >>= (kNumBitModelTotalBits - kNumMoveReducingBits);
-      range *= i;
-      while(range < (1 << 31))
-      {
-        range <<= 1;
-        bitCount++;
-      }
-    }
-    bitCount <<= kNumBitPriceShiftBits;
-    range -= (1 << 31);
-    for (int k = kNumBitPriceShiftBits - 1; k >= 0; k--)
-    {
-      range <<= 1;
-      if (range > (1 << 31))
-      {
-        bitCount += (1 << k);
-        range -= (1 << 31);
-      }
-    }
-    ProbPrices[i] = (bitCount 
-      // + (1 << (kCyclesBits - 1))
-      ) >> kCyclesBits;
-  }
-  */
-}
-
-}}
+// Compress/RangeCoder/RangeCoderBit.cpp
+
+#include "StdAfx.h"
+
+#include "RangeCoderBit.h"
+
+namespace NCompress {
+namespace NRangeCoder {
+
+UInt32 CPriceTables::ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
+static CPriceTables g_PriceTables;
+
+CPriceTables::CPriceTables() { Init(); }
+
+void CPriceTables::Init()
+{
+  const int kNumBits = (kNumBitModelTotalBits - kNumMoveReducingBits);
+  for(int i = kNumBits - 1; i >= 0; i--)
+  {
+    UInt32 start = 1 << (kNumBits - i - 1);
+    UInt32 end = 1 << (kNumBits - i);
+    for (UInt32 j = start; j < end; j++)
+      ProbPrices[j] = (i << kNumBitPriceShiftBits) + 
+          (((end - j) << kNumBitPriceShiftBits) >> (kNumBits - i - 1));
+  }
+
+  /*
+  // simplest: bad solution
+  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
+    ProbPrices[i] = kBitPrice;
+  */
+  
+  /*
+  const double kDummyMultMid = (1.0 / kBitPrice) / 2;
+  const double kDummyMultMid = 0;
+  // float solution
+  double ln2 = log(double(2));
+  double lnAll = log(double(kBitModelTotal >> kNumMoveReducingBits));
+  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
+    ProbPrices[i] = UInt32((fabs(lnAll - log(double(i))) / ln2 + kDummyMultMid) * kBitPrice);
+  */
+  
+  /*
+  // experimental, slow, solution:
+  for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
+  {
+    const int kCyclesBits = 5;
+    const UInt32 kCycles = (1 << kCyclesBits);
+
+    UInt32 range = UInt32(-1);
+    UInt32 bitCount = 0;
+    for (UInt32 j = 0; j < kCycles; j++)
+    {
+      range >>= (kNumBitModelTotalBits - kNumMoveReducingBits);
+      range *= i;
+      while(range < (1 << 31))
+      {
+        range <<= 1;
+        bitCount++;
+      }
+    }
+    bitCount <<= kNumBitPriceShiftBits;
+    range -= (1 << 31);
+    for (int k = kNumBitPriceShiftBits - 1; k >= 0; k--)
+    {
+      range <<= 1;
+      if (range > (1 << 31))
+      {
+        bitCount += (1 << k);
+        range -= (1 << 31);
+      }
+    }
+    ProbPrices[i] = (bitCount 
+      // + (1 << (kCyclesBits - 1))
+      ) >> kCyclesBits;
+  }
+  */
+}
+
+}}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBit.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,120 +1,120 @@
-// Compress/RangeCoder/RangeCoderBit.h
-
-#ifndef __COMPRESS_RANGECODER_BIT_H
-#define __COMPRESS_RANGECODER_BIT_H
-
-#include "RangeCoder.h"
-
-namespace NCompress {
-namespace NRangeCoder {
-
-const int kNumBitModelTotalBits  = 11;
-const UInt32 kBitModelTotal = (1 << kNumBitModelTotalBits);
-
-const int kNumMoveReducingBits = 2;
-
-const int kNumBitPriceShiftBits = 6;
-const UInt32 kBitPrice = 1 << kNumBitPriceShiftBits;
-
-class CPriceTables
-{
-public:
-  static UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
-  static void Init();
-  CPriceTables();
-};
-
-template <int numMoveBits>
-class CBitModel
-{
-public:
-  UInt32 Prob;
-  void UpdateModel(UInt32 symbol)
-  {
-    /*
-    Prob -= (Prob + ((symbol - 1) & ((1 << numMoveBits) - 1))) >> numMoveBits;
-    Prob += (1 - symbol) << (kNumBitModelTotalBits - numMoveBits);
-    */
-    if (symbol == 0)
-      Prob += (kBitModelTotal - Prob) >> numMoveBits;
-    else
-      Prob -= (Prob) >> numMoveBits;
-  }
-public:
-  void Init() { Prob = kBitModelTotal / 2; }
-};
-
-template <int numMoveBits>
-class CBitEncoder: public CBitModel<numMoveBits>
-{
-public:
-  void Encode(CEncoder *encoder, UInt32 symbol)
-  {
-    /*
-    encoder->EncodeBit(this->Prob, kNumBitModelTotalBits, symbol);
-    this->UpdateModel(symbol);
-    */
-    UInt32 newBound = (encoder->Range >> kNumBitModelTotalBits) * this->Prob;
-    if (symbol == 0)
-    {
-      encoder->Range = newBound;
-      this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
-    }
-    else
-    {
-      encoder->Low += newBound;
-      encoder->Range -= newBound;
-      this->Prob -= (this->Prob) >> numMoveBits;
-    }
-    if (encoder->Range < kTopValue)
-    {
-      encoder->Range <<= 8;
-      encoder->ShiftLow();
-    }
-  }
-  UInt32 GetPrice(UInt32 symbol) const
-  {
-    return CPriceTables::ProbPrices[
-      (((this->Prob - symbol) ^ ((-(int)symbol))) & (kBitModelTotal - 1)) >> kNumMoveReducingBits];
-  }
-  UInt32 GetPrice0() const { return CPriceTables::ProbPrices[this->Prob >> kNumMoveReducingBits]; }
-  UInt32 GetPrice1() const { return CPriceTables::ProbPrices[(kBitModelTotal - this->Prob) >> kNumMoveReducingBits]; }
-};
-
-
-template <int numMoveBits>
-class CBitDecoder: public CBitModel<numMoveBits>
-{
-public:
-  UInt32 Decode(CDecoder *decoder)
-  {
-    UInt32 newBound = (decoder->Range >> kNumBitModelTotalBits) * this->Prob;
-    if (decoder->Code < newBound)
-    {
-      decoder->Range = newBound;
-      this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
-      if (decoder->Range < kTopValue)
-      {
-        decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
-        decoder->Range <<= 8;
-      }
-      return 0;
-    }
-    else
-    {
-      decoder->Range -= newBound;
-      decoder->Code -= newBound;
-      this->Prob -= (this->Prob) >> numMoveBits;
-      if (decoder->Range < kTopValue)
-      {
-        decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
-        decoder->Range <<= 8;
-      }
-      return 1;
-    }
-  }
-};
-
-}}
-
-#endif
+// Compress/RangeCoder/RangeCoderBit.h
+
+#ifndef __COMPRESS_RANGECODER_BIT_H
+#define __COMPRESS_RANGECODER_BIT_H
+
+#include "RangeCoder.h"
+
+namespace NCompress {
+namespace NRangeCoder {
+
+const int kNumBitModelTotalBits  = 11;
+const UInt32 kBitModelTotal = (1 << kNumBitModelTotalBits);
+
+const int kNumMoveReducingBits = 2;
+
+const int kNumBitPriceShiftBits = 6;
+const UInt32 kBitPrice = 1 << kNumBitPriceShiftBits;
+
+class CPriceTables
+{
+public:
+  static UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
+  static void Init();
+  CPriceTables();
+};
+
+template <int numMoveBits>
+class CBitModel
+{
+public:
+  UInt32 Prob;
+  void UpdateModel(UInt32 symbol)
+  {
+    /*
+    Prob -= (Prob + ((symbol - 1) & ((1 << numMoveBits) - 1))) >> numMoveBits;
+    Prob += (1 - symbol) << (kNumBitModelTotalBits - numMoveBits);
+    */
+    if (symbol == 0)
+      Prob += (kBitModelTotal - Prob) >> numMoveBits;
+    else
+      Prob -= (Prob) >> numMoveBits;
+  }
+public:
+  void Init() { Prob = kBitModelTotal / 2; }
+};
+
+template <int numMoveBits>
+class CBitEncoder: public CBitModel<numMoveBits>
+{
+public:
+  void Encode(CEncoder *encoder, UInt32 symbol)
+  {
+    /*
+    encoder->EncodeBit(this->Prob, kNumBitModelTotalBits, symbol);
+    this->UpdateModel(symbol);
+    */
+    UInt32 newBound = (encoder->Range >> kNumBitModelTotalBits) * this->Prob;
+    if (symbol == 0)
+    {
+      encoder->Range = newBound;
+      this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
+    }
+    else
+    {
+      encoder->Low += newBound;
+      encoder->Range -= newBound;
+      this->Prob -= (this->Prob) >> numMoveBits;
+    }
+    if (encoder->Range < kTopValue)
+    {
+      encoder->Range <<= 8;
+      encoder->ShiftLow();
+    }
+  }
+  UInt32 GetPrice(UInt32 symbol) const
+  {
+    return CPriceTables::ProbPrices[
+      (((this->Prob - symbol) ^ ((-(int)symbol))) & (kBitModelTotal - 1)) >> kNumMoveReducingBits];
+  }
+  UInt32 GetPrice0() const { return CPriceTables::ProbPrices[this->Prob >> kNumMoveReducingBits]; }
+  UInt32 GetPrice1() const { return CPriceTables::ProbPrices[(kBitModelTotal - this->Prob) >> kNumMoveReducingBits]; }
+};
+
+
+template <int numMoveBits>
+class CBitDecoder: public CBitModel<numMoveBits>
+{
+public:
+  UInt32 Decode(CDecoder *decoder)
+  {
+    UInt32 newBound = (decoder->Range >> kNumBitModelTotalBits) * this->Prob;
+    if (decoder->Code < newBound)
+    {
+      decoder->Range = newBound;
+      this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
+      if (decoder->Range < kTopValue)
+      {
+        decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
+        decoder->Range <<= 8;
+      }
+      return 0;
+    }
+    else
+    {
+      decoder->Range -= newBound;
+      decoder->Code -= newBound;
+      this->Prob -= (this->Prob) >> numMoveBits;
+      if (decoder->Range < kTopValue)
+      {
+        decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
+        decoder->Range <<= 8;
+      }
+      return 1;
+    }
+  }
+};
+
+}}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBitTree.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBitTree.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderBitTree.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,161 +1,161 @@
-// Compress/RangeCoder/RangeCoderBitTree.h
-
-#ifndef __COMPRESS_RANGECODER_BIT_TREE_H
-#define __COMPRESS_RANGECODER_BIT_TREE_H
-
-#include "RangeCoderBit.h"
-#include "RangeCoderOpt.h"
-
-namespace NCompress {
-namespace NRangeCoder {
-
-template <int numMoveBits, int NumBitLevels>
-class CBitTreeEncoder
-{
-  CBitEncoder<numMoveBits> Models[1 << NumBitLevels];
-public:
-  void Init()
-  {
-    for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
-      Models[i].Init();
-  }
-  void Encode(CEncoder *rangeEncoder, UInt32 symbol)
-  {
-    UInt32 modelIndex = 1;
-    for (int bitIndex = NumBitLevels; bitIndex != 0 ;)
-    {
-      bitIndex--;
-      UInt32 bit = (symbol >> bitIndex) & 1;
-      Models[modelIndex].Encode(rangeEncoder, bit);
-      modelIndex = (modelIndex << 1) | bit;
-    }
-  };
-  void ReverseEncode(CEncoder *rangeEncoder, UInt32 symbol)
-  {
-    UInt32 modelIndex = 1;
-    for (int i = 0; i < NumBitLevels; i++)
-    {
-      UInt32 bit = symbol & 1;
-      Models[modelIndex].Encode(rangeEncoder, bit);
-      modelIndex = (modelIndex << 1) | bit;
-      symbol >>= 1;
-    }
-  }
-  UInt32 GetPrice(UInt32 symbol) const
-  {
-    symbol |= (1 << NumBitLevels);
-    UInt32 price = 0;
-    while (symbol != 1)
-    {
-      price += Models[symbol >> 1].GetPrice(symbol & 1);
-      symbol >>= 1;
-    }
-    return price;
-  }
-  UInt32 ReverseGetPrice(UInt32 symbol) const
-  {
-    UInt32 price = 0;
-    UInt32 modelIndex = 1;
-    for (int i = NumBitLevels; i != 0; i--)
-    {
-      UInt32 bit = symbol & 1;
-      symbol >>= 1;
-      price += Models[modelIndex].GetPrice(bit);
-      modelIndex = (modelIndex << 1) | bit;
-    }
-    return price;
-  }
-};
-
-template <int numMoveBits, int NumBitLevels>
-class CBitTreeDecoder
-{
-  CBitDecoder<numMoveBits> Models[1 << NumBitLevels];
-public:
-  void Init()
-  {
-    for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
-      Models[i].Init();
-  }
-  UInt32 Decode(CDecoder *rangeDecoder)
-  {
-    UInt32 modelIndex = 1;
-    RC_INIT_VAR
-    for(int bitIndex = NumBitLevels; bitIndex != 0; bitIndex--)
-    {
-      // modelIndex = (modelIndex << 1) + Models[modelIndex].Decode(rangeDecoder);
-      RC_GETBIT(numMoveBits, Models[modelIndex].Prob, modelIndex)
-    }
-    RC_FLUSH_VAR
-    return modelIndex - (1 << NumBitLevels);
-  };
-  UInt32 ReverseDecode(CDecoder *rangeDecoder)
-  {
-    UInt32 modelIndex = 1;
-    UInt32 symbol = 0;
-    RC_INIT_VAR
-    for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
-    {
-      // UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
-      // modelIndex <<= 1;
-      // modelIndex += bit;
-      // symbol |= (bit << bitIndex);
-      RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
-    }
-    RC_FLUSH_VAR
-    return symbol;
-  }
-};
-
-template <int numMoveBits>
-void ReverseBitTreeEncode(CBitEncoder<numMoveBits> *Models, 
-    CEncoder *rangeEncoder, int NumBitLevels, UInt32 symbol)
-{
-  UInt32 modelIndex = 1;
-  for (int i = 0; i < NumBitLevels; i++)
-  {
-    UInt32 bit = symbol & 1;
-    Models[modelIndex].Encode(rangeEncoder, bit);
-    modelIndex = (modelIndex << 1) | bit;
-    symbol >>= 1;
-  }
-}
-
-template <int numMoveBits>
-UInt32 ReverseBitTreeGetPrice(CBitEncoder<numMoveBits> *Models, 
-    UInt32 NumBitLevels, UInt32 symbol)
-{
-  UInt32 price = 0;
-  UInt32 modelIndex = 1;
-  for (int i = NumBitLevels; i != 0; i--)
-  {
-    UInt32 bit = symbol & 1;
-    symbol >>= 1;
-    price += Models[modelIndex].GetPrice(bit);
-    modelIndex = (modelIndex << 1) | bit;
-  }
-  return price;
-}
-
-template <int numMoveBits>
-UInt32 ReverseBitTreeDecode(CBitDecoder<numMoveBits> *Models, 
-    CDecoder *rangeDecoder, int NumBitLevels)
-{
-  UInt32 modelIndex = 1;
-  UInt32 symbol = 0;
-  RC_INIT_VAR
-  for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
-  {
-    // UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
-    // modelIndex <<= 1;
-    // modelIndex += bit;
-    // symbol |= (bit << bitIndex);
-    RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
-  }
-  RC_FLUSH_VAR
-  return symbol;
-}
-
-}}
-
-#endif
+// Compress/RangeCoder/RangeCoderBitTree.h
+
+#ifndef __COMPRESS_RANGECODER_BIT_TREE_H
+#define __COMPRESS_RANGECODER_BIT_TREE_H
+
+#include "RangeCoderBit.h"
+#include "RangeCoderOpt.h"
+
+namespace NCompress {
+namespace NRangeCoder {
+
+template <int numMoveBits, int NumBitLevels>
+class CBitTreeEncoder
+{
+  CBitEncoder<numMoveBits> Models[1 << NumBitLevels];
+public:
+  void Init()
+  {
+    for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
+      Models[i].Init();
+  }
+  void Encode(CEncoder *rangeEncoder, UInt32 symbol)
+  {
+    UInt32 modelIndex = 1;
+    for (int bitIndex = NumBitLevels; bitIndex != 0 ;)
+    {
+      bitIndex--;
+      UInt32 bit = (symbol >> bitIndex) & 1;
+      Models[modelIndex].Encode(rangeEncoder, bit);
+      modelIndex = (modelIndex << 1) | bit;
+    }
+  };
+  void ReverseEncode(CEncoder *rangeEncoder, UInt32 symbol)
+  {
+    UInt32 modelIndex = 1;
+    for (int i = 0; i < NumBitLevels; i++)
+    {
+      UInt32 bit = symbol & 1;
+      Models[modelIndex].Encode(rangeEncoder, bit);
+      modelIndex = (modelIndex << 1) | bit;
+      symbol >>= 1;
+    }
+  }
+  UInt32 GetPrice(UInt32 symbol) const
+  {
+    symbol |= (1 << NumBitLevels);
+    UInt32 price = 0;
+    while (symbol != 1)
+    {
+      price += Models[symbol >> 1].GetPrice(symbol & 1);
+      symbol >>= 1;
+    }
+    return price;
+  }
+  UInt32 ReverseGetPrice(UInt32 symbol) const
+  {
+    UInt32 price = 0;
+    UInt32 modelIndex = 1;
+    for (int i = NumBitLevels; i != 0; i--)
+    {
+      UInt32 bit = symbol & 1;
+      symbol >>= 1;
+      price += Models[modelIndex].GetPrice(bit);
+      modelIndex = (modelIndex << 1) | bit;
+    }
+    return price;
+  }
+};
+
+template <int numMoveBits, int NumBitLevels>
+class CBitTreeDecoder
+{
+  CBitDecoder<numMoveBits> Models[1 << NumBitLevels];
+public:
+  void Init()
+  {
+    for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
+      Models[i].Init();
+  }
+  UInt32 Decode(CDecoder *rangeDecoder)
+  {
+    UInt32 modelIndex = 1;
+    RC_INIT_VAR
+    for(int bitIndex = NumBitLevels; bitIndex != 0; bitIndex--)
+    {
+      // modelIndex = (modelIndex << 1) + Models[modelIndex].Decode(rangeDecoder);
+      RC_GETBIT(numMoveBits, Models[modelIndex].Prob, modelIndex)
+    }
+    RC_FLUSH_VAR
+    return modelIndex - (1 << NumBitLevels);
+  };
+  UInt32 ReverseDecode(CDecoder *rangeDecoder)
+  {
+    UInt32 modelIndex = 1;
+    UInt32 symbol = 0;
+    RC_INIT_VAR
+    for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
+    {
+      // UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
+      // modelIndex <<= 1;
+      // modelIndex += bit;
+      // symbol |= (bit << bitIndex);
+      RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
+    }
+    RC_FLUSH_VAR
+    return symbol;
+  }
+};
+
+template <int numMoveBits>
+void ReverseBitTreeEncode(CBitEncoder<numMoveBits> *Models, 
+    CEncoder *rangeEncoder, int NumBitLevels, UInt32 symbol)
+{
+  UInt32 modelIndex = 1;
+  for (int i = 0; i < NumBitLevels; i++)
+  {
+    UInt32 bit = symbol & 1;
+    Models[modelIndex].Encode(rangeEncoder, bit);
+    modelIndex = (modelIndex << 1) | bit;
+    symbol >>= 1;
+  }
+}
+
+template <int numMoveBits>
+UInt32 ReverseBitTreeGetPrice(CBitEncoder<numMoveBits> *Models, 
+    UInt32 NumBitLevels, UInt32 symbol)
+{
+  UInt32 price = 0;
+  UInt32 modelIndex = 1;
+  for (int i = NumBitLevels; i != 0; i--)
+  {
+    UInt32 bit = symbol & 1;
+    symbol >>= 1;
+    price += Models[modelIndex].GetPrice(bit);
+    modelIndex = (modelIndex << 1) | bit;
+  }
+  return price;
+}
+
+template <int numMoveBits>
+UInt32 ReverseBitTreeDecode(CBitDecoder<numMoveBits> *Models, 
+    CDecoder *rangeDecoder, int NumBitLevels)
+{
+  UInt32 modelIndex = 1;
+  UInt32 symbol = 0;
+  RC_INIT_VAR
+  for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
+  {
+    // UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
+    // modelIndex <<= 1;
+    // modelIndex += bit;
+    // symbol |= (bit << bitIndex);
+    RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
+  }
+  RC_FLUSH_VAR
+  return symbol;
+}
+
+}}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderOpt.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderOpt.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/RangeCoderOpt.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,31 +1,31 @@
-// Compress/RangeCoder/RangeCoderOpt.h
-
-#ifndef __COMPRESS_RANGECODER_OPT_H
-#define __COMPRESS_RANGECODER_OPT_H
-
-#define RC_INIT_VAR \
-  UInt32 range = rangeDecoder->Range; \
-  UInt32 code = rangeDecoder->Code;        
-
-#define RC_FLUSH_VAR \
-  rangeDecoder->Range = range; \
-  rangeDecoder->Code = code;
-
-#define RC_NORMALIZE \
-  if (range < NCompress::NRangeCoder::kTopValue) \
-    { code = (code << 8) | rangeDecoder->Stream.ReadByte(); range <<= 8; }
-
-#define RC_GETBIT2(numMoveBits, prob, mi, A0, A1) \
-  { UInt32 bound = (range >> NCompress::NRangeCoder::kNumBitModelTotalBits) * prob; \
-  if (code < bound) \
-  { A0; range = bound; \
-    prob += (NCompress::NRangeCoder::kBitModelTotal - prob) >> numMoveBits; \
-    mi <<= 1; } \
-  else \
-  { A1; range -= bound; code -= bound; prob -= (prob) >> numMoveBits; \
-    mi = (mi + mi) + 1; }} \
-  RC_NORMALIZE
-
-#define RC_GETBIT(numMoveBits, prob, mi) RC_GETBIT2(numMoveBits, prob, mi, ; , ;)
-
-#endif
+// Compress/RangeCoder/RangeCoderOpt.h
+
+#ifndef __COMPRESS_RANGECODER_OPT_H
+#define __COMPRESS_RANGECODER_OPT_H
+
+#define RC_INIT_VAR \
+  UInt32 range = rangeDecoder->Range; \
+  UInt32 code = rangeDecoder->Code;        
+
+#define RC_FLUSH_VAR \
+  rangeDecoder->Range = range; \
+  rangeDecoder->Code = code;
+
+#define RC_NORMALIZE \
+  if (range < NCompress::NRangeCoder::kTopValue) \
+    { code = (code << 8) | rangeDecoder->Stream.ReadByte(); range <<= 8; }
+
+#define RC_GETBIT2(numMoveBits, prob, mi, A0, A1) \
+  { UInt32 bound = (range >> NCompress::NRangeCoder::kNumBitModelTotalBits) * prob; \
+  if (code < bound) \
+  { A0; range = bound; \
+    prob += (NCompress::NRangeCoder::kBitModelTotal - prob) >> numMoveBits; \
+    mi <<= 1; } \
+  else \
+  { A1; range -= bound; code -= bound; prob -= (prob) >> numMoveBits; \
+    mi = (mi + mi) + 1; }} \
+  RC_NORMALIZE
+
+#define RC_GETBIT(numMoveBits, prob, mi) RC_GETBIT2(numMoveBits, prob, mi, ; , ;)
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/StdAfx.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/StdAfx.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/RangeCoder/StdAfx.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,6 +1,6 @@
-// StdAfx.h
-
-#ifndef __STDAFX_H
-#define __STDAFX_H
-
-#endif
+// StdAfx.h
+
+#ifndef __STDAFX_H
+#define __STDAFX_H
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/ICoder.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/ICoder.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/ICoder.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,163 +1,163 @@
-// ICoder.h
-
-#ifndef __ICODER_H
-#define __ICODER_H
-
-#include "IStream.h"
-
-// "23170F69-40C1-278A-0000-000400xx0000"
-#define CODER_INTERFACE(i, x) \
-DEFINE_GUID(IID_ ## i, \
-0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x04, 0x00, x, 0x00, 0x00); \
-struct i: public IUnknown
-
-CODER_INTERFACE(ICompressProgressInfo, 0x04)
-{
-  STDMETHOD(SetRatioInfo)(const UInt64 *inSize, const UInt64 *outSize) PURE;
-};
-
-CODER_INTERFACE(ICompressCoder, 0x05)
-{
-  STDMETHOD(Code)(ISequentialInStream *inStream,
-      ISequentialOutStream *outStream, 
-      const UInt64 *inSize, 
-      const UInt64 *outSize,
-      ICompressProgressInfo *progress) PURE;
-};
-
-CODER_INTERFACE(ICompressCoder2, 0x18)
-{
-  STDMETHOD(Code)(ISequentialInStream **inStreams,
-      const UInt64 **inSizes, 
-      UInt32 numInStreams,
-      ISequentialOutStream **outStreams, 
-      const UInt64 **outSizes,
-      UInt32 numOutStreams,
-      ICompressProgressInfo *progress) PURE;
-};
-
-namespace NCoderPropID
-{
-  enum EEnum
-  {
-    kDictionarySize = 0x400,
-    kUsedMemorySize,
-    kOrder,
-    kPosStateBits = 0x440,
-    kLitContextBits,
-    kLitPosBits,
-    kNumFastBytes = 0x450,
-    kMatchFinder,
-    kMatchFinderCycles,
-    kNumPasses = 0x460, 
-    kAlgorithm = 0x470,
-    kMultiThread = 0x480,
-    kNumThreads,
-    kEndMarker = 0x490
-  };
-}
-
-CODER_INTERFACE(ICompressSetCoderProperties, 0x20)
-{
-  STDMETHOD(SetCoderProperties)(const PROPID *propIDs, 
-      const PROPVARIANT *properties, UInt32 numProperties) PURE;
-};
-
-/*
-CODER_INTERFACE(ICompressSetCoderProperties, 0x21)
-{
-  STDMETHOD(SetDecoderProperties)(ISequentialInStream *inStream) PURE;
-};
-*/
-
-CODER_INTERFACE(ICompressSetDecoderProperties2, 0x22)
-{
-  STDMETHOD(SetDecoderProperties2)(const Byte *data, UInt32 size) PURE;
-};
-
-CODER_INTERFACE(ICompressWriteCoderProperties, 0x23)
-{
-  STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStreams) PURE;
-};
-
-CODER_INTERFACE(ICompressGetInStreamProcessedSize, 0x24)
-{
-  STDMETHOD(GetInStreamProcessedSize)(UInt64 *value) PURE;
-};
-
-CODER_INTERFACE(ICompressSetCoderMt, 0x25)
-{
-  STDMETHOD(SetNumberOfThreads)(UInt32 numThreads) PURE;
-};
-
-CODER_INTERFACE(ICompressGetSubStreamSize, 0x30)
-{
-  STDMETHOD(GetSubStreamSize)(UInt64 subStream, UInt64 *value) PURE;
-};
-
-CODER_INTERFACE(ICompressSetInStream, 0x31)
-{
-  STDMETHOD(SetInStream)(ISequentialInStream *inStream) PURE;
-  STDMETHOD(ReleaseInStream)() PURE;
-};
-
-CODER_INTERFACE(ICompressSetOutStream, 0x32)
-{
-  STDMETHOD(SetOutStream)(ISequentialOutStream *outStream) PURE;
-  STDMETHOD(ReleaseOutStream)() PURE;
-};
-
-CODER_INTERFACE(ICompressSetInStreamSize, 0x33)
-{
-  STDMETHOD(SetInStreamSize)(const UInt64 *inSize) PURE;
-};
-
-CODER_INTERFACE(ICompressSetOutStreamSize, 0x34)
-{
-  STDMETHOD(SetOutStreamSize)(const UInt64 *outSize) PURE;
-};
-
-CODER_INTERFACE(ICompressFilter, 0x40)
-{
-  STDMETHOD(Init)() PURE;
-  STDMETHOD_(UInt32, Filter)(Byte *data, UInt32 size) PURE;
-  // Filter return outSize (UInt32)
-  // if (outSize <= size): Filter have converted outSize bytes
-  // if (outSize > size): Filter have not converted anything.
-  //      and it needs at least outSize bytes to convert one block 
-  //      (it's for crypto block algorithms).
-};
-
-CODER_INTERFACE(ICryptoProperties, 0x80)
-{
-  STDMETHOD(SetKey)(const Byte *data, UInt32 size) PURE;
-  STDMETHOD(SetInitVector)(const Byte *data, UInt32 size) PURE;
-};
-
-CODER_INTERFACE(ICryptoSetPassword, 0x90)
-{
-  STDMETHOD(CryptoSetPassword)(const Byte *data, UInt32 size) PURE;
-};
-
-CODER_INTERFACE(ICryptoSetCRC, 0xA0)
-{
-  STDMETHOD(CryptoSetCRC)(UInt32 crc) PURE;
-};
-
-//////////////////////
-// It's for DLL file
-namespace NMethodPropID
-{
-  enum EEnum
-  {
-    kID,
-    kName,
-    kDecoder,
-    kEncoder,
-    kInStreams,
-    kOutStreams,
-    kDescription
-  };
-}
-
-#endif
+// ICoder.h
+
+#ifndef __ICODER_H
+#define __ICODER_H
+
+#include "IStream.h"
+
+// "23170F69-40C1-278A-0000-000400xx0000"
+#define CODER_INTERFACE(i, x) \
+DEFINE_GUID(IID_ ## i, \
+0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x04, 0x00, x, 0x00, 0x00); \
+struct i: public IUnknown
+
+CODER_INTERFACE(ICompressProgressInfo, 0x04)
+{
+  STDMETHOD(SetRatioInfo)(const UInt64 *inSize, const UInt64 *outSize) PURE;
+};
+
+CODER_INTERFACE(ICompressCoder, 0x05)
+{
+  STDMETHOD(Code)(ISequentialInStream *inStream,
+      ISequentialOutStream *outStream, 
+      const UInt64 *inSize, 
+      const UInt64 *outSize,
+      ICompressProgressInfo *progress) PURE;
+};
+
+CODER_INTERFACE(ICompressCoder2, 0x18)
+{
+  STDMETHOD(Code)(ISequentialInStream **inStreams,
+      const UInt64 **inSizes, 
+      UInt32 numInStreams,
+      ISequentialOutStream **outStreams, 
+      const UInt64 **outSizes,
+      UInt32 numOutStreams,
+      ICompressProgressInfo *progress) PURE;
+};
+
+namespace NCoderPropID
+{
+  enum EEnum
+  {
+    kDictionarySize = 0x400,
+    kUsedMemorySize,
+    kOrder,
+    kPosStateBits = 0x440,
+    kLitContextBits,
+    kLitPosBits,
+    kNumFastBytes = 0x450,
+    kMatchFinder,
+    kMatchFinderCycles,
+    kNumPasses = 0x460, 
+    kAlgorithm = 0x470,
+    kMultiThread = 0x480,
+    kNumThreads,
+    kEndMarker = 0x490
+  };
+}
+
+CODER_INTERFACE(ICompressSetCoderProperties, 0x20)
+{
+  STDMETHOD(SetCoderProperties)(const PROPID *propIDs, 
+      const PROPVARIANT *properties, UInt32 numProperties) PURE;
+};
+
+/*
+CODER_INTERFACE(ICompressSetCoderProperties, 0x21)
+{
+  STDMETHOD(SetDecoderProperties)(ISequentialInStream *inStream) PURE;
+};
+*/
+
+CODER_INTERFACE(ICompressSetDecoderProperties2, 0x22)
+{
+  STDMETHOD(SetDecoderProperties2)(const Byte *data, UInt32 size) PURE;
+};
+
+CODER_INTERFACE(ICompressWriteCoderProperties, 0x23)
+{
+  STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStreams) PURE;
+};
+
+CODER_INTERFACE(ICompressGetInStreamProcessedSize, 0x24)
+{
+  STDMETHOD(GetInStreamProcessedSize)(UInt64 *value) PURE;
+};
+
+CODER_INTERFACE(ICompressSetCoderMt, 0x25)
+{
+  STDMETHOD(SetNumberOfThreads)(UInt32 numThreads) PURE;
+};
+
+CODER_INTERFACE(ICompressGetSubStreamSize, 0x30)
+{
+  STDMETHOD(GetSubStreamSize)(UInt64 subStream, UInt64 *value) PURE;
+};
+
+CODER_INTERFACE(ICompressSetInStream, 0x31)
+{
+  STDMETHOD(SetInStream)(ISequentialInStream *inStream) PURE;
+  STDMETHOD(ReleaseInStream)() PURE;
+};
+
+CODER_INTERFACE(ICompressSetOutStream, 0x32)
+{
+  STDMETHOD(SetOutStream)(ISequentialOutStream *outStream) PURE;
+  STDMETHOD(ReleaseOutStream)() PURE;
+};
+
+CODER_INTERFACE(ICompressSetInStreamSize, 0x33)
+{
+  STDMETHOD(SetInStreamSize)(const UInt64 *inSize) PURE;
+};
+
+CODER_INTERFACE(ICompressSetOutStreamSize, 0x34)
+{
+  STDMETHOD(SetOutStreamSize)(const UInt64 *outSize) PURE;
+};
+
+CODER_INTERFACE(ICompressFilter, 0x40)
+{
+  STDMETHOD(Init)() PURE;
+  STDMETHOD_(UInt32, Filter)(Byte *data, UInt32 size) PURE;
+  // Filter return outSize (UInt32)
+  // if (outSize <= size): Filter have converted outSize bytes
+  // if (outSize > size): Filter have not converted anything.
+  //      and it needs at least outSize bytes to convert one block 
+  //      (it's for crypto block algorithms).
+};
+
+CODER_INTERFACE(ICryptoProperties, 0x80)
+{
+  STDMETHOD(SetKey)(const Byte *data, UInt32 size) PURE;
+  STDMETHOD(SetInitVector)(const Byte *data, UInt32 size) PURE;
+};
+
+CODER_INTERFACE(ICryptoSetPassword, 0x90)
+{
+  STDMETHOD(CryptoSetPassword)(const Byte *data, UInt32 size) PURE;
+};
+
+CODER_INTERFACE(ICryptoSetCRC, 0xA0)
+{
+  STDMETHOD(CryptoSetCRC)(UInt32 crc) PURE;
+};
+
+//////////////////////
+// It's for DLL file
+namespace NMethodPropID
+{
+  enum EEnum
+  {
+    kID,
+    kName,
+    kDecoder,
+    kEncoder,
+    kInStreams,
+    kOutStreams,
+    kDescription
+  };
+}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/IStream.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/IStream.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/IStream.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,62 +1,62 @@
-// IStream.h
-
-#ifndef __ISTREAM_H
-#define __ISTREAM_H
-
-#include "../Common/MyUnknown.h"
-#include "../Common/Types.h"
-
-// "23170F69-40C1-278A-0000-000300xx0000"
-
-#define STREAM_INTERFACE_SUB(i, b, x) \
-DEFINE_GUID(IID_ ## i, \
-0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x03, 0x00, x, 0x00, 0x00); \
-struct i: public b
-
-#define STREAM_INTERFACE(i, x) STREAM_INTERFACE_SUB(i, IUnknown, x)
-
-STREAM_INTERFACE(ISequentialInStream, 0x01)
-{
-  STDMETHOD(Read)(void *data, UInt32 size, UInt32 *processedSize) PURE;
-  /*
-  Out: if size != 0, return_value = S_OK and (*processedSize == 0),
-    then there are no more bytes in stream.
-  if (size > 0) && there are bytes in stream, 
-  this function must read at least 1 byte.
-  This function is allowed to read less than number of remaining bytes in stream.
-  You must call Read function in loop, if you need exact amount of data
-  */
-};
-
-STREAM_INTERFACE(ISequentialOutStream, 0x02)
-{
-  STDMETHOD(Write)(const void *data, UInt32 size, UInt32 *processedSize) PURE;
-  /*
-  if (size > 0) this function must write at least 1 byte.
-  This function is allowed to write less than "size".
-  You must call Write function in loop, if you need to write exact amount of data
-  */
-};
-
-STREAM_INTERFACE_SUB(IInStream, ISequentialInStream, 0x03)
-{
-  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
-};
-
-STREAM_INTERFACE_SUB(IOutStream, ISequentialOutStream, 0x04)
-{
-  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
-  STDMETHOD(SetSize)(Int64 newSize) PURE;
-};
-
-STREAM_INTERFACE(IStreamGetSize, 0x06)
-{
-  STDMETHOD(GetSize)(UInt64 *size) PURE;
-};
-
-STREAM_INTERFACE(IOutStreamFlush, 0x07)
-{
-  STDMETHOD(Flush)() PURE;
-};
-
-#endif
+// IStream.h
+
+#ifndef __ISTREAM_H
+#define __ISTREAM_H
+
+#include "../Common/MyUnknown.h"
+#include "../Common/Types.h"
+
+// "23170F69-40C1-278A-0000-000300xx0000"
+
+#define STREAM_INTERFACE_SUB(i, b, x) \
+DEFINE_GUID(IID_ ## i, \
+0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x03, 0x00, x, 0x00, 0x00); \
+struct i: public b
+
+#define STREAM_INTERFACE(i, x) STREAM_INTERFACE_SUB(i, IUnknown, x)
+
+STREAM_INTERFACE(ISequentialInStream, 0x01)
+{
+  STDMETHOD(Read)(void *data, UInt32 size, UInt32 *processedSize) PURE;
+  /*
+  Out: if size != 0, return_value = S_OK and (*processedSize == 0),
+    then there are no more bytes in stream.
+  if (size > 0) && there are bytes in stream, 
+  this function must read at least 1 byte.
+  This function is allowed to read less than number of remaining bytes in stream.
+  You must call Read function in loop, if you need exact amount of data
+  */
+};
+
+STREAM_INTERFACE(ISequentialOutStream, 0x02)
+{
+  STDMETHOD(Write)(const void *data, UInt32 size, UInt32 *processedSize) PURE;
+  /*
+  if (size > 0) this function must write at least 1 byte.
+  This function is allowed to write less than "size".
+  You must call Write function in loop, if you need to write exact amount of data
+  */
+};
+
+STREAM_INTERFACE_SUB(IInStream, ISequentialInStream, 0x03)
+{
+  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
+};
+
+STREAM_INTERFACE_SUB(IOutStream, ISequentialOutStream, 0x04)
+{
+  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
+  STDMETHOD(SetSize)(Int64 newSize) PURE;
+};
+
+STREAM_INTERFACE(IStreamGetSize, 0x06)
+{
+  STDMETHOD(GetSize)(UInt64 *size) PURE;
+};
+
+STREAM_INTERFACE(IOutStreamFlush, 0x07)
+{
+  STDMETHOD(Flush)() PURE;
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,118 +1,118 @@
-// Common/Alloc.cpp
-
-#include "StdAfx.h"
-
-#ifdef _WIN32
-#include "MyWindows.h"
-#else
-#include <stdlib.h>
-#endif
-
-#include "Alloc.h"
-
-/* #define _SZ_ALLOC_DEBUG */
-/* use _SZ_ALLOC_DEBUG to debug alloc/free operations */
-#ifdef _SZ_ALLOC_DEBUG
-#include <stdio.h>
-int g_allocCount = 0;
-int g_allocCountMid = 0;
-int g_allocCountBig = 0;
-#endif
-
-void *MyAlloc(size_t size) throw()
-{
-  if (size == 0)
-    return 0;
-  #ifdef _SZ_ALLOC_DEBUG
-  fprintf(stderr, "\nAlloc %10d bytes; count = %10d", size, g_allocCount++);
-  #endif
-  return ::malloc(size);
-}
-
-void MyFree(void *address) throw()
-{
-  #ifdef _SZ_ALLOC_DEBUG
-  if (address != 0)
-    fprintf(stderr, "\nFree; count = %10d", --g_allocCount);
-  #endif
-  
-  ::free(address);
-}
-
-#ifdef _WIN32
-
-void *MidAlloc(size_t size) throw()
-{
-  if (size == 0)
-    return 0;
-  #ifdef _SZ_ALLOC_DEBUG
-  fprintf(stderr, "\nAlloc_Mid %10d bytes;  count = %10d", size, g_allocCountMid++);
-  #endif
-  return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
-}
-
-void MidFree(void *address) throw()
-{
-  #ifdef _SZ_ALLOC_DEBUG
-  if (address != 0)
-    fprintf(stderr, "\nFree_Mid; count = %10d", --g_allocCountMid);
-  #endif
-  if (address == 0)
-    return;
-  ::VirtualFree(address, 0, MEM_RELEASE);
-}
-
-static SIZE_T g_LargePageSize = 
-    #ifdef _WIN64
-    (1 << 21);
-    #else
-    (1 << 22);
-    #endif
-
-typedef SIZE_T (WINAPI *GetLargePageMinimumP)();
-
-bool SetLargePageSize()
-{
-  GetLargePageMinimumP largePageMinimum = (GetLargePageMinimumP)
-        ::GetProcAddress(::GetModuleHandle(TEXT("kernel32.dll")), "GetLargePageMinimum");
-  if (largePageMinimum == 0)
-    return false;
-  SIZE_T size = largePageMinimum();
-  if (size == 0 || (size & (size - 1)) != 0)
-    return false;
-  g_LargePageSize = size;
-  return true;
-}
-
-
-void *BigAlloc(size_t size) throw()
-{
-  if (size == 0)
-    return 0;
-  #ifdef _SZ_ALLOC_DEBUG
-  fprintf(stderr, "\nAlloc_Big %10d bytes;  count = %10d", size, g_allocCountBig++);
-  #endif
-  
-  if (size >= (1 << 18))
-  {
-    void *res = ::VirtualAlloc(0, (size + g_LargePageSize - 1) & (~(g_LargePageSize - 1)), 
-        MEM_COMMIT | MEM_LARGE_PAGES, PAGE_READWRITE);
-    if (res != 0)
-      return res;
-  }
-  return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
-}
-
-void BigFree(void *address) throw()
-{
-  #ifdef _SZ_ALLOC_DEBUG
-  if (address != 0)
-    fprintf(stderr, "\nFree_Big; count = %10d", --g_allocCountBig);
-  #endif
-  
-  if (address == 0)
-    return;
-  ::VirtualFree(address, 0, MEM_RELEASE);
-}
-
-#endif
+// Common/Alloc.cpp
+
+#include "StdAfx.h"
+
+#ifdef _WIN32
+#include "MyWindows.h"
+#else
+#include <stdlib.h>
+#endif
+
+#include "Alloc.h"
+
+/* #define _SZ_ALLOC_DEBUG */
+/* use _SZ_ALLOC_DEBUG to debug alloc/free operations */
+#ifdef _SZ_ALLOC_DEBUG
+#include <stdio.h>
+int g_allocCount = 0;
+int g_allocCountMid = 0;
+int g_allocCountBig = 0;
+#endif
+
+void *MyAlloc(size_t size) throw()
+{
+  if (size == 0)
+    return 0;
+  #ifdef _SZ_ALLOC_DEBUG
+  fprintf(stderr, "\nAlloc %10d bytes; count = %10d", size, g_allocCount++);
+  #endif
+  return ::malloc(size);
+}
+
+void MyFree(void *address) throw()
+{
+  #ifdef _SZ_ALLOC_DEBUG
+  if (address != 0)
+    fprintf(stderr, "\nFree; count = %10d", --g_allocCount);
+  #endif
+  
+  ::free(address);
+}
+
+#ifdef _WIN32
+
+void *MidAlloc(size_t size) throw()
+{
+  if (size == 0)
+    return 0;
+  #ifdef _SZ_ALLOC_DEBUG
+  fprintf(stderr, "\nAlloc_Mid %10d bytes;  count = %10d", size, g_allocCountMid++);
+  #endif
+  return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
+}
+
+void MidFree(void *address) throw()
+{
+  #ifdef _SZ_ALLOC_DEBUG
+  if (address != 0)
+    fprintf(stderr, "\nFree_Mid; count = %10d", --g_allocCountMid);
+  #endif
+  if (address == 0)
+    return;
+  ::VirtualFree(address, 0, MEM_RELEASE);
+}
+
+static SIZE_T g_LargePageSize = 
+    #ifdef _WIN64
+    (1 << 21);
+    #else
+    (1 << 22);
+    #endif
+
+typedef SIZE_T (WINAPI *GetLargePageMinimumP)();
+
+bool SetLargePageSize()
+{
+  GetLargePageMinimumP largePageMinimum = (GetLargePageMinimumP)
+        ::GetProcAddress(::GetModuleHandle(TEXT("kernel32.dll")), "GetLargePageMinimum");
+  if (largePageMinimum == 0)
+    return false;
+  SIZE_T size = largePageMinimum();
+  if (size == 0 || (size & (size - 1)) != 0)
+    return false;
+  g_LargePageSize = size;
+  return true;
+}
+
+
+void *BigAlloc(size_t size) throw()
+{
+  if (size == 0)
+    return 0;
+  #ifdef _SZ_ALLOC_DEBUG
+  fprintf(stderr, "\nAlloc_Big %10d bytes;  count = %10d", size, g_allocCountBig++);
+  #endif
+  
+  if (size >= (1 << 18))
+  {
+    void *res = ::VirtualAlloc(0, (size + g_LargePageSize - 1) & (~(g_LargePageSize - 1)), 
+        MEM_COMMIT | MEM_LARGE_PAGES, PAGE_READWRITE);
+    if (res != 0)
+      return res;
+  }
+  return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
+}
+
+void BigFree(void *address) throw()
+{
+  #ifdef _SZ_ALLOC_DEBUG
+  if (address != 0)
+    fprintf(stderr, "\nFree_Big; count = %10d", --g_allocCountBig);
+  #endif
+  
+  if (address == 0)
+    return;
+  ::VirtualFree(address, 0, MEM_RELEASE);
+}
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Alloc.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,29 +1,29 @@
-// Common/Alloc.h
-
-#ifndef __COMMON_ALLOC_H
-#define __COMMON_ALLOC_H
-
-#include <stddef.h>
-
-void *MyAlloc(size_t size) throw();
-void MyFree(void *address) throw();
-
-#ifdef _WIN32
-
-bool SetLargePageSize();
-
-void *MidAlloc(size_t size) throw();
-void MidFree(void *address) throw();
-void *BigAlloc(size_t size) throw();
-void BigFree(void *address) throw();
-
-#else
-
-#define MidAlloc(size) MyAlloc(size)
-#define MidFree(address) MyFree(address)
-#define BigAlloc(size) MyAlloc(size)
-#define BigFree(address) MyFree(address)
-
-#endif
-
-#endif
+// Common/Alloc.h
+
+#ifndef __COMMON_ALLOC_H
+#define __COMMON_ALLOC_H
+
+#include <stddef.h>
+
+void *MyAlloc(size_t size) throw();
+void MyFree(void *address) throw();
+
+#ifdef _WIN32
+
+bool SetLargePageSize();
+
+void *MidAlloc(size_t size) throw();
+void MidFree(void *address) throw();
+void *BigAlloc(size_t size) throw();
+void BigFree(void *address) throw();
+
+#else
+
+#define MidAlloc(size) MyAlloc(size)
+#define MidFree(address) MyFree(address)
+#define BigAlloc(size) MyAlloc(size)
+#define BigFree(address) MyFree(address)
+
+#endif
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.cpp
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.cpp	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.cpp	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,61 +1,61 @@
-// Common/CRC.cpp
-
-#include "StdAfx.h"
-
-#include "CRC.h"
-
-static const UInt32 kCRCPoly = 0xEDB88320;
-
-UInt32 CCRC::Table[256];
-
-void CCRC::InitTable()
-{
-  for (UInt32 i = 0; i < 256; i++)
-  {
-    UInt32 r = i;
-    for (int j = 0; j < 8; j++)
-      if (r & 1) 
-        r = (r >> 1) ^ kCRCPoly;
-      else     
-        r >>= 1;
-    CCRC::Table[i] = r;
-  }
-}
-
-class CCRCTableInit
-{
-public:
-  CCRCTableInit() { CCRC::InitTable(); }
-} g_CRCTableInit;
-
-void CCRC::UpdateByte(Byte b)
-{
-  _value = Table[((Byte)(_value)) ^ b] ^ (_value >> 8);
-}
-
-void CCRC::UpdateUInt16(UInt16 v)
-{
-  UpdateByte(Byte(v));
-  UpdateByte(Byte(v >> 8));
-}
-
-void CCRC::UpdateUInt32(UInt32 v)
-{
-  for (int i = 0; i < 4; i++)
-    UpdateByte((Byte)(v >> (8 * i)));
-}
-
-void CCRC::UpdateUInt64(UInt64 v)
-{
-  for (int i = 0; i < 8; i++)
-    UpdateByte((Byte)(v >> (8 * i)));
-}
-
-void CCRC::Update(const void *data, size_t size)
-{
-  UInt32 v = _value;
-  const Byte *p = (const Byte *)data;
-  for (; size > 0 ; size--, p++)
-    v = Table[((Byte)(v)) ^ *p] ^ (v >> 8);
-  _value = v;
-}
+// Common/CRC.cpp
+
+#include "StdAfx.h"
+
+#include "CRC.h"
+
+static const UInt32 kCRCPoly = 0xEDB88320;
+
+UInt32 CCRC::Table[256];
+
+void CCRC::InitTable()
+{
+  for (UInt32 i = 0; i < 256; i++)
+  {
+    UInt32 r = i;
+    for (int j = 0; j < 8; j++)
+      if (r & 1) 
+        r = (r >> 1) ^ kCRCPoly;
+      else     
+        r >>= 1;
+    CCRC::Table[i] = r;
+  }
+}
+
+class CCRCTableInit
+{
+public:
+  CCRCTableInit() { CCRC::InitTable(); }
+} g_CRCTableInit;
+
+void CCRC::UpdateByte(Byte b)
+{
+  _value = Table[((Byte)(_value)) ^ b] ^ (_value >> 8);
+}
+
+void CCRC::UpdateUInt16(UInt16 v)
+{
+  UpdateByte(Byte(v));
+  UpdateByte(Byte(v >> 8));
+}
+
+void CCRC::UpdateUInt32(UInt32 v)
+{
+  for (int i = 0; i < 4; i++)
+    UpdateByte((Byte)(v >> (8 * i)));
+}
+
+void CCRC::UpdateUInt64(UInt64 v)
+{
+  for (int i = 0; i < 8; i++)
+    UpdateByte((Byte)(v >> (8 * i)));
+}
+
+void CCRC::Update(const void *data, size_t size)
+{
+  UInt32 v = _value;
+  const Byte *p = (const Byte *)data;
+  for (; size > 0 ; size--, p++)
+    v = Table[((Byte)(v)) ^ *p] ^ (v >> 8);
+  _value = v;
+}

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/CRC.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,36 +1,36 @@
-// Common/CRC.h
-
-#ifndef __COMMON_CRC_H
-#define __COMMON_CRC_H
-
-#include <stddef.h>
-#include "Types.h"
-
-class CCRC
-{
-  UInt32 _value;
-public:
-	static UInt32 Table[256];
-	static void InitTable();
-
-  CCRC():  _value(0xFFFFFFFF){};
-  void Init() { _value = 0xFFFFFFFF; }
-  void UpdateByte(Byte v);
-  void UpdateUInt16(UInt16 v);
-  void UpdateUInt32(UInt32 v);
-  void UpdateUInt64(UInt64 v);
-  void Update(const void *data, size_t size);
-  UInt32 GetDigest() const { return _value ^ 0xFFFFFFFF; } 
-  static UInt32 CalculateDigest(const void *data, size_t size)
-  {
-    CCRC crc;
-    crc.Update(data, size);
-    return crc.GetDigest();
-  }
-  static bool VerifyDigest(UInt32 digest, const void *data, size_t size)
-  {
-    return (CalculateDigest(data, size) == digest);
-  }
-};
-
-#endif
+// Common/CRC.h
+
+#ifndef __COMMON_CRC_H
+#define __COMMON_CRC_H
+
+#include <stddef.h>
+#include "Types.h"
+
+class CCRC
+{
+  UInt32 _value;
+public:
+	static UInt32 Table[256];
+	static void InitTable();
+
+  CCRC():  _value(0xFFFFFFFF){};
+  void Init() { _value = 0xFFFFFFFF; }
+  void UpdateByte(Byte v);
+  void UpdateUInt16(UInt16 v);
+  void UpdateUInt32(UInt32 v);
+  void UpdateUInt64(UInt64 v);
+  void Update(const void *data, size_t size);
+  UInt32 GetDigest() const { return _value ^ 0xFFFFFFFF; } 
+  static UInt32 CalculateDigest(const void *data, size_t size)
+  {
+    CCRC crc;
+    crc.Update(data, size);
+    return crc.GetDigest();
+  }
+  static bool VerifyDigest(UInt32 digest, const void *data, size_t size)
+  {
+    return (CalculateDigest(data, size) == digest);
+  }
+};
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Defs.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Defs.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Defs.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,20 +1,20 @@
-// Common/Defs.h
-
-#ifndef __COMMON_DEFS_H
-#define __COMMON_DEFS_H
-
-template <class T> inline T MyMin(T a, T b)
-  {  return a < b ? a : b; }
-template <class T> inline T MyMax(T a, T b)
-  {  return a > b ? a : b; }
-
-template <class T> inline int MyCompare(T a, T b)
-  {  return a < b ? -1 : (a == b ? 0 : 1); }
-
-inline int BoolToInt(bool value)
-  { return (value ? 1: 0); }
-
-inline bool IntToBool(int value)
-  { return (value != 0); }
-
-#endif
+// Common/Defs.h
+
+#ifndef __COMMON_DEFS_H
+#define __COMMON_DEFS_H
+
+template <class T> inline T MyMin(T a, T b)
+  {  return a < b ? a : b; }
+template <class T> inline T MyMax(T a, T b)
+  {  return a > b ? a : b; }
+
+template <class T> inline int MyCompare(T a, T b)
+  {  return a < b ? -1 : (a == b ? 0 : 1); }
+
+inline int BoolToInt(bool value)
+  { return (value ? 1: 0); }
+
+inline bool IntToBool(int value)
+  { return (value != 0); }
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyCom.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyCom.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyCom.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,203 +1,203 @@
-// MyCom.h
-
-#ifndef __MYCOM_H
-#define __MYCOM_H
-
-#include "MyWindows.h"
-
-#define RINOK(x) { HRESULT __result_ = (x); if(__result_ != S_OK) return __result_; }
-
-template <class T>
-class CMyComPtr
-{
-  T* _p;
-public:
-  // typedef T _PtrClass;
-  CMyComPtr() { _p = NULL;}
-  CMyComPtr(T* p) {if ((_p = p) != NULL) p->AddRef(); }
-  CMyComPtr(const CMyComPtr<T>& lp)
-  {
-    if ((_p = lp._p) != NULL)
-      _p->AddRef();
-  }
-  ~CMyComPtr() { if (_p) _p->Release(); }
-  void Release() { if (_p) { _p->Release(); _p = NULL; } }
-  operator T*() const {  return (T*)_p;  }
-  // T& operator*() const {  return *_p; }
-  T** operator&() { return &_p; }
-  T* operator->() const { return _p; }
-  T* operator=(T* p) 
-  { 
-    if (p != 0)
-      p->AddRef();
-    if (_p) 
-      _p->Release();
-    _p = p;
-    return p;
-  }
-  T* operator=(const CMyComPtr<T>& lp) { return (*this = lp._p); }
-  bool operator!() const { return (_p == NULL); }
-  // bool operator==(T* pT) const {  return _p == pT; }
-  // Compare two objects for equivalence
-  void Attach(T* p2)
-  {
-    Release();
-    _p = p2;
-  }
-  T* Detach()
-  {
-    T* pt = _p;
-    _p = NULL;
-    return pt;
-  }
-  #ifdef _WIN32
-  HRESULT CoCreateInstance(REFCLSID rclsid, REFIID iid, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
-  {
-    return ::CoCreateInstance(rclsid, pUnkOuter, dwClsContext, iid, (void**)&_p);
-  }
-  #endif
-  /*
-  HRESULT CoCreateInstance(LPCOLESTR szProgID, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
-  {
-    CLSID clsid;
-    HRESULT hr = CLSIDFromProgID(szProgID, &clsid);
-    ATLASSERT(_p == NULL);
-    if (SUCCEEDED(hr))
-      hr = ::CoCreateInstance(clsid, pUnkOuter, dwClsContext, __uuidof(T), (void**)&_p);
-    return hr;
-  }
-  */
-  template <class Q>
-  HRESULT QueryInterface(REFGUID iid, Q** pp) const
-  {
-    return _p->QueryInterface(iid, (void**)pp);
-  }
-};
-
-//////////////////////////////////////////////////////////
-
-class CMyComBSTR
-{
-public:
-  BSTR m_str;
-  CMyComBSTR() { m_str = NULL; }
-  CMyComBSTR(LPCOLESTR pSrc) {  m_str = ::SysAllocString(pSrc);  }
-  // CMyComBSTR(int nSize) { m_str = ::SysAllocStringLen(NULL, nSize); }
-  // CMyComBSTR(int nSize, LPCOLESTR sz) { m_str = ::SysAllocStringLen(sz, nSize);  }
-  CMyComBSTR(const CMyComBSTR& src) { m_str = src.MyCopy(); }
-  /*
-  CMyComBSTR(REFGUID src)
-  {
-    LPOLESTR szGuid;
-    StringFromCLSID(src, &szGuid);
-    m_str = ::SysAllocString(szGuid);
-    CoTaskMemFree(szGuid);
-  }
-  */
-  ~CMyComBSTR() { ::SysFreeString(m_str); }
-  CMyComBSTR& operator=(const CMyComBSTR& src)
-  {
-    if (m_str != src.m_str)
-    {
-      if (m_str)
-        ::SysFreeString(m_str);
-      m_str = src.MyCopy();
-    }
-    return *this;
-  }
-  CMyComBSTR& operator=(LPCOLESTR pSrc)
-  {
-    ::SysFreeString(m_str);
-    m_str = ::SysAllocString(pSrc);
-    return *this;
-  }
-  unsigned int Length() const { return ::SysStringLen(m_str); }
-  operator BSTR() const { return m_str; }
-  BSTR* operator&() { return &m_str; }
-  BSTR MyCopy() const 
-  { 
-    int byteLen = ::SysStringByteLen(m_str);
-    BSTR res = ::SysAllocStringByteLen(NULL, byteLen);
-    memmove(res, m_str, byteLen);
-    return res;
-  }
-  void Attach(BSTR src) {  m_str = src; }
-  BSTR Detach()
-  {
-    BSTR s = m_str;
-    m_str = NULL;
-    return s;
-  }
-  void Empty()
-  {
-    ::SysFreeString(m_str);
-    m_str = NULL;
-  }
-  bool operator!() const {  return (m_str == NULL); }
-};
-
-
-//////////////////////////////////////////////////////////
-
-class CMyUnknownImp
-{
-public:
-  ULONG __m_RefCount;
-  CMyUnknownImp(): __m_RefCount(0) {}
-};
-
-#define MY_QUERYINTERFACE_BEGIN STDMETHOD(QueryInterface) \
-    (REFGUID iid, void **outObject) { 
-
-#define MY_QUERYINTERFACE_ENTRY(i) if (iid == IID_ ## i) \
-    { *outObject = (void *)(i *)this; AddRef(); return S_OK; }
-
-#define MY_QUERYINTERFACE_END return E_NOINTERFACE; }
-
-#define MY_ADDREF_RELEASE \
-STDMETHOD_(ULONG, AddRef)() { return ++__m_RefCount; } \
-STDMETHOD_(ULONG, Release)() { if (--__m_RefCount != 0)  \
-  return __m_RefCount; delete this; return 0; }
-
-#define MY_UNKNOWN_IMP_SPEC(i) \
-  MY_QUERYINTERFACE_BEGIN \
-  i \
-  MY_QUERYINTERFACE_END \
-  MY_ADDREF_RELEASE
-
-
-#define MY_UNKNOWN_IMP STDMETHOD(QueryInterface)(REFGUID, void **) { \
-  MY_QUERYINTERFACE_END \
-  MY_ADDREF_RELEASE
-
-#define MY_UNKNOWN_IMP1(i) MY_UNKNOWN_IMP_SPEC( \
-  MY_QUERYINTERFACE_ENTRY(i) \
-  )
-
-#define MY_UNKNOWN_IMP2(i1, i2) MY_UNKNOWN_IMP_SPEC( \
-  MY_QUERYINTERFACE_ENTRY(i1) \
-  MY_QUERYINTERFACE_ENTRY(i2) \
-  )
-
-#define MY_UNKNOWN_IMP3(i1, i2, i3) MY_UNKNOWN_IMP_SPEC( \
-  MY_QUERYINTERFACE_ENTRY(i1) \
-  MY_QUERYINTERFACE_ENTRY(i2) \
-  MY_QUERYINTERFACE_ENTRY(i3) \
-  )
-
-#define MY_UNKNOWN_IMP4(i1, i2, i3, i4) MY_UNKNOWN_IMP_SPEC( \
-  MY_QUERYINTERFACE_ENTRY(i1) \
-  MY_QUERYINTERFACE_ENTRY(i2) \
-  MY_QUERYINTERFACE_ENTRY(i3) \
-  MY_QUERYINTERFACE_ENTRY(i4) \
-  )
-
-#define MY_UNKNOWN_IMP5(i1, i2, i3, i4, i5) MY_UNKNOWN_IMP_SPEC( \
-  MY_QUERYINTERFACE_ENTRY(i1) \
-  MY_QUERYINTERFACE_ENTRY(i2) \
-  MY_QUERYINTERFACE_ENTRY(i3) \
-  MY_QUERYINTERFACE_ENTRY(i4) \
-  MY_QUERYINTERFACE_ENTRY(i5) \
-  )
-
-#endif
+// MyCom.h
+
+#ifndef __MYCOM_H
+#define __MYCOM_H
+
+#include "MyWindows.h"
+
+#define RINOK(x) { HRESULT __result_ = (x); if(__result_ != S_OK) return __result_; }
+
+template <class T>
+class CMyComPtr
+{
+  T* _p;
+public:
+  // typedef T _PtrClass;
+  CMyComPtr() { _p = NULL;}
+  CMyComPtr(T* p) {if ((_p = p) != NULL) p->AddRef(); }
+  CMyComPtr(const CMyComPtr<T>& lp)
+  {
+    if ((_p = lp._p) != NULL)
+      _p->AddRef();
+  }
+  ~CMyComPtr() { if (_p) _p->Release(); }
+  void Release() { if (_p) { _p->Release(); _p = NULL; } }
+  operator T*() const {  return (T*)_p;  }
+  // T& operator*() const {  return *_p; }
+  T** operator&() { return &_p; }
+  T* operator->() const { return _p; }
+  T* operator=(T* p) 
+  { 
+    if (p != 0)
+      p->AddRef();
+    if (_p) 
+      _p->Release();
+    _p = p;
+    return p;
+  }
+  T* operator=(const CMyComPtr<T>& lp) { return (*this = lp._p); }
+  bool operator!() const { return (_p == NULL); }
+  // bool operator==(T* pT) const {  return _p == pT; }
+  // Compare two objects for equivalence
+  void Attach(T* p2)
+  {
+    Release();
+    _p = p2;
+  }
+  T* Detach()
+  {
+    T* pt = _p;
+    _p = NULL;
+    return pt;
+  }
+  #ifdef _WIN32
+  HRESULT CoCreateInstance(REFCLSID rclsid, REFIID iid, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
+  {
+    return ::CoCreateInstance(rclsid, pUnkOuter, dwClsContext, iid, (void**)&_p);
+  }
+  #endif
+  /*
+  HRESULT CoCreateInstance(LPCOLESTR szProgID, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
+  {
+    CLSID clsid;
+    HRESULT hr = CLSIDFromProgID(szProgID, &clsid);
+    ATLASSERT(_p == NULL);
+    if (SUCCEEDED(hr))
+      hr = ::CoCreateInstance(clsid, pUnkOuter, dwClsContext, __uuidof(T), (void**)&_p);
+    return hr;
+  }
+  */
+  template <class Q>
+  HRESULT QueryInterface(REFGUID iid, Q** pp) const
+  {
+    return _p->QueryInterface(iid, (void**)pp);
+  }
+};
+
+//////////////////////////////////////////////////////////
+
+class CMyComBSTR
+{
+public:
+  BSTR m_str;
+  CMyComBSTR() { m_str = NULL; }
+  CMyComBSTR(LPCOLESTR pSrc) {  m_str = ::SysAllocString(pSrc);  }
+  // CMyComBSTR(int nSize) { m_str = ::SysAllocStringLen(NULL, nSize); }
+  // CMyComBSTR(int nSize, LPCOLESTR sz) { m_str = ::SysAllocStringLen(sz, nSize);  }
+  CMyComBSTR(const CMyComBSTR& src) { m_str = src.MyCopy(); }
+  /*
+  CMyComBSTR(REFGUID src)
+  {
+    LPOLESTR szGuid;
+    StringFromCLSID(src, &szGuid);
+    m_str = ::SysAllocString(szGuid);
+    CoTaskMemFree(szGuid);
+  }
+  */
+  ~CMyComBSTR() { ::SysFreeString(m_str); }
+  CMyComBSTR& operator=(const CMyComBSTR& src)
+  {
+    if (m_str != src.m_str)
+    {
+      if (m_str)
+        ::SysFreeString(m_str);
+      m_str = src.MyCopy();
+    }
+    return *this;
+  }
+  CMyComBSTR& operator=(LPCOLESTR pSrc)
+  {
+    ::SysFreeString(m_str);
+    m_str = ::SysAllocString(pSrc);
+    return *this;
+  }
+  unsigned int Length() const { return ::SysStringLen(m_str); }
+  operator BSTR() const { return m_str; }
+  BSTR* operator&() { return &m_str; }
+  BSTR MyCopy() const 
+  { 
+    int byteLen = ::SysStringByteLen(m_str);
+    BSTR res = ::SysAllocStringByteLen(NULL, byteLen);
+    memmove(res, m_str, byteLen);
+    return res;
+  }
+  void Attach(BSTR src) {  m_str = src; }
+  BSTR Detach()
+  {
+    BSTR s = m_str;
+    m_str = NULL;
+    return s;
+  }
+  void Empty()
+  {
+    ::SysFreeString(m_str);
+    m_str = NULL;
+  }
+  bool operator!() const {  return (m_str == NULL); }
+};
+
+
+//////////////////////////////////////////////////////////
+
+class CMyUnknownImp
+{
+public:
+  ULONG __m_RefCount;
+  CMyUnknownImp(): __m_RefCount(0) {}
+};
+
+#define MY_QUERYINTERFACE_BEGIN STDMETHOD(QueryInterface) \
+    (REFGUID iid, void **outObject) { 
+
+#define MY_QUERYINTERFACE_ENTRY(i) if (iid == IID_ ## i) \
+    { *outObject = (void *)(i *)this; AddRef(); return S_OK; }
+
+#define MY_QUERYINTERFACE_END return E_NOINTERFACE; }
+
+#define MY_ADDREF_RELEASE \
+STDMETHOD_(ULONG, AddRef)() { return ++__m_RefCount; } \
+STDMETHOD_(ULONG, Release)() { if (--__m_RefCount != 0)  \
+  return __m_RefCount; delete this; return 0; }
+
+#define MY_UNKNOWN_IMP_SPEC(i) \
+  MY_QUERYINTERFACE_BEGIN \
+  i \
+  MY_QUERYINTERFACE_END \
+  MY_ADDREF_RELEASE
+
+
+#define MY_UNKNOWN_IMP STDMETHOD(QueryInterface)(REFGUID, void **) { \
+  MY_QUERYINTERFACE_END \
+  MY_ADDREF_RELEASE
+
+#define MY_UNKNOWN_IMP1(i) MY_UNKNOWN_IMP_SPEC( \
+  MY_QUERYINTERFACE_ENTRY(i) \
+  )
+
+#define MY_UNKNOWN_IMP2(i1, i2) MY_UNKNOWN_IMP_SPEC( \
+  MY_QUERYINTERFACE_ENTRY(i1) \
+  MY_QUERYINTERFACE_ENTRY(i2) \
+  )
+
+#define MY_UNKNOWN_IMP3(i1, i2, i3) MY_UNKNOWN_IMP_SPEC( \
+  MY_QUERYINTERFACE_ENTRY(i1) \
+  MY_QUERYINTERFACE_ENTRY(i2) \
+  MY_QUERYINTERFACE_ENTRY(i3) \
+  )
+
+#define MY_UNKNOWN_IMP4(i1, i2, i3, i4) MY_UNKNOWN_IMP_SPEC( \
+  MY_QUERYINTERFACE_ENTRY(i1) \
+  MY_QUERYINTERFACE_ENTRY(i2) \
+  MY_QUERYINTERFACE_ENTRY(i3) \
+  MY_QUERYINTERFACE_ENTRY(i4) \
+  )
+
+#define MY_UNKNOWN_IMP5(i1, i2, i3, i4, i5) MY_UNKNOWN_IMP_SPEC( \
+  MY_QUERYINTERFACE_ENTRY(i1) \
+  MY_QUERYINTERFACE_ENTRY(i2) \
+  MY_QUERYINTERFACE_ENTRY(i3) \
+  MY_QUERYINTERFACE_ENTRY(i4) \
+  MY_QUERYINTERFACE_ENTRY(i5) \
+  )
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyGuidDef.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyGuidDef.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyGuidDef.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,54 +1,54 @@
-// Common/MyGuidDef.h
-
-#ifndef GUID_DEFINED
-#define GUID_DEFINED
-
-#include "Types.h"
-
-typedef struct {
-  UInt32 Data1;
-  UInt16 Data2;
-  UInt16 Data3;
-  unsigned char Data4[8];
-} GUID;
-
-#ifdef __cplusplus
-#define REFGUID const GUID &
-#else
-#define REFGUID const GUID *
-#endif
-
-#define REFCLSID REFGUID
-#define REFIID REFGUID
-
-#ifdef __cplusplus
-inline bool operator==(REFGUID g1, REFGUID g2)
-{ 
-  for (int i = 0; i < (int)sizeof(g1); i++)
-    if (((const unsigned char *)&g1)[i] != ((const unsigned char *)&g2)[i])
-      return false;
-  return true;
-}
-inline bool operator!=(REFGUID g1, REFGUID g2) { return !(g1 == g2); }
-#endif
-
-#ifdef __cplusplus
-  #define MY_EXTERN_C extern "C"
-#else
-  #define MY_EXTERN_C extern
-#endif
-
-#endif // GUID_DEFINED
-
-
-#ifdef DEFINE_GUID
-#undef DEFINE_GUID
-#endif
-
-#ifdef INITGUID
-  #define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
-    MY_EXTERN_C const GUID name = { l, w1, w2, { b1, b2,  b3,  b4,  b5,  b6,  b7,  b8 } }
-#else
-  #define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
-    MY_EXTERN_C const GUID name
-#endif
+// Common/MyGuidDef.h
+
+#ifndef GUID_DEFINED
+#define GUID_DEFINED
+
+#include "Types.h"
+
+typedef struct {
+  UInt32 Data1;
+  UInt16 Data2;
+  UInt16 Data3;
+  unsigned char Data4[8];
+} GUID;
+
+#ifdef __cplusplus
+#define REFGUID const GUID &
+#else
+#define REFGUID const GUID *
+#endif
+
+#define REFCLSID REFGUID
+#define REFIID REFGUID
+
+#ifdef __cplusplus
+inline bool operator==(REFGUID g1, REFGUID g2)
+{ 
+  for (int i = 0; i < (int)sizeof(g1); i++)
+    if (((const unsigned char *)&g1)[i] != ((const unsigned char *)&g2)[i])
+      return false;
+  return true;
+}
+inline bool operator!=(REFGUID g1, REFGUID g2) { return !(g1 == g2); }
+#endif
+
+#ifdef __cplusplus
+  #define MY_EXTERN_C extern "C"
+#else
+  #define MY_EXTERN_C extern
+#endif
+
+#endif // GUID_DEFINED
+
+
+#ifdef DEFINE_GUID
+#undef DEFINE_GUID
+#endif
+
+#ifdef INITGUID
+  #define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
+    MY_EXTERN_C const GUID name = { l, w1, w2, { b1, b2,  b3,  b4,  b5,  b6,  b7,  b8 } }
+#else
+  #define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
+    MY_EXTERN_C const GUID name
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyInitGuid.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyInitGuid.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyInitGuid.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,13 +1,13 @@
-// Common/MyInitGuid.h
-
-#ifndef __COMMON_MYINITGUID_H
-#define __COMMON_MYINITGUID_H
-
-#ifdef _WIN32
-#include <initguid.h>
-#else
-#define INITGUID
-#include "MyGuidDef.h"
-#endif
-
-#endif
+// Common/MyInitGuid.h
+
+#ifndef __COMMON_MYINITGUID_H
+#define __COMMON_MYINITGUID_H
+
+#ifdef _WIN32
+#include <initguid.h>
+#else
+#define INITGUID
+#include "MyGuidDef.h"
+#endif
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyUnknown.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyUnknown.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyUnknown.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,24 +1,24 @@
-// MyUnknown.h
-
-#ifndef __MYUNKNOWN_H
-#define __MYUNKNOWN_H
-
-#ifdef _WIN32
-
-#ifdef _WIN32_WCE
-#if (_WIN32_WCE > 300)
-#include <basetyps.h>
-#else
-#define MIDL_INTERFACE(x) struct 
-#endif
-#else
-#include <basetyps.h>
-#endif
-
-#include <unknwn.h>
-
-#else 
-#include "MyWindows.h"
-#endif
-  
-#endif
+// MyUnknown.h
+
+#ifndef __MYUNKNOWN_H
+#define __MYUNKNOWN_H
+
+#ifdef _WIN32
+
+#ifdef _WIN32_WCE
+#if (_WIN32_WCE > 300)
+#include <basetyps.h>
+#else
+#define MIDL_INTERFACE(x) struct 
+#endif
+#else
+#include <basetyps.h>
+#endif
+
+#include <unknwn.h>
+
+#else 
+#include "MyWindows.h"
+#endif
+  
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,201 +1,201 @@
-// MyWindows.h
-
-#ifndef __MYWINDOWS_H
-#define __MYWINDOWS_H
-
-#ifdef _WIN32
-
-#include <windows.h>
-
-#define CHAR_PATH_SEPARATOR '\\'
-#define WCHAR_PATH_SEPARATOR L'\\'
-#define STRING_PATH_SEPARATOR "\\"
-#define WSTRING_PATH_SEPARATOR L"\\"
-
-#else
-
-#define CHAR_PATH_SEPARATOR '/'
-#define WCHAR_PATH_SEPARATOR L'/'
-#define STRING_PATH_SEPARATOR "/"
-#define WSTRING_PATH_SEPARATOR L"/"
-
-#include <stddef.h> // for wchar_t
-#include <string.h>
-
-#include "MyGuidDef.h"
-
-typedef char CHAR;
-typedef unsigned char UCHAR;
-
-#undef BYTE
-typedef unsigned char BYTE;
-
-typedef short SHORT;
-typedef unsigned short USHORT;
-
-#undef WORD
-typedef unsigned short WORD;
-typedef short VARIANT_BOOL;
-
-typedef int INT;
-typedef Int32 INT32;
-typedef unsigned int UINT;
-typedef UInt32 UINT32;
-typedef INT32 LONG;   // LONG, ULONG and DWORD must be 32-bit
-typedef UINT32 ULONG;
-
-#undef DWORD
-typedef UINT32 DWORD;
-
-typedef Int64 LONGLONG;
-typedef UInt64 ULONGLONG;
-
-typedef struct LARGE_INTEGER { LONGLONG QuadPart; }LARGE_INTEGER;
-typedef struct _ULARGE_INTEGER { ULONGLONG QuadPart;} ULARGE_INTEGER;
-
-typedef const CHAR *LPCSTR;
-typedef CHAR TCHAR;
-typedef const TCHAR *LPCTSTR;
-typedef wchar_t WCHAR;
-typedef WCHAR OLECHAR;
-typedef const WCHAR *LPCWSTR;
-typedef OLECHAR *BSTR;
-typedef const OLECHAR *LPCOLESTR;
-typedef OLECHAR *LPOLESTR;
-
-typedef struct _FILETIME
-{
-  DWORD dwLowDateTime;
-  DWORD dwHighDateTime;
-}FILETIME;
-
-#define HRESULT LONG
-#define FAILED(Status) ((HRESULT)(Status)<0)
-typedef ULONG PROPID;
-typedef LONG SCODE;
-
-#define S_OK    ((HRESULT)0x00000000L)
-#define S_FALSE ((HRESULT)0x00000001L)
-#define E_NOTIMPL ((HRESULT)0x80004001L)
-#define E_NOINTERFACE ((HRESULT)0x80004002L)
-#define E_ABORT ((HRESULT)0x80004004L)
-#define E_FAIL ((HRESULT)0x80004005L)
-#define STG_E_INVALIDFUNCTION ((HRESULT)0x80030001L)
-#define E_OUTOFMEMORY ((HRESULT)0x8007000EL)
-#define E_INVALIDARG ((HRESULT)0x80070057L)
-
-#ifdef _MSC_VER
-#define STDMETHODCALLTYPE __stdcall 
-#else
-#define STDMETHODCALLTYPE 
-#endif
-
-#define STDMETHOD_(t, f) virtual t STDMETHODCALLTYPE f
-#define STDMETHOD(f) STDMETHOD_(HRESULT, f)
-#define STDMETHODIMP_(type) type STDMETHODCALLTYPE
-#define STDMETHODIMP STDMETHODIMP_(HRESULT)
-
-#define PURE = 0
-
-#define MIDL_INTERFACE(x) struct 
-
-struct IUnknown
-{
-  //virtual ~IUnknown() {}
-  STDMETHOD(QueryInterface) (REFIID iid, void **outObject) PURE;
-  STDMETHOD_(ULONG, AddRef)() PURE;
-  STDMETHOD_(ULONG, Release)() PURE;
-};
-
-typedef IUnknown *LPUNKNOWN;
-
-#define VARIANT_TRUE ((VARIANT_BOOL)-1)
-#define VARIANT_FALSE ((VARIANT_BOOL)0)
-
-enum VARENUM
-{	
-  VT_EMPTY	= 0,
-	VT_NULL	= 1,
-	VT_I2	= 2,
-	VT_I4	= 3,
-	VT_R4	= 4,
-	VT_R8	= 5,
-	VT_CY	= 6,
-	VT_DATE	= 7,
-	VT_BSTR	= 8,
-	VT_DISPATCH	= 9,
-	VT_ERROR	= 10,
-	VT_BOOL	= 11,
-	VT_VARIANT	= 12,
-	VT_UNKNOWN	= 13,
-	VT_DECIMAL	= 14,
-	VT_I1	= 16,
-	VT_UI1	= 17,
-	VT_UI2	= 18,
-	VT_UI4	= 19,
-	VT_I8	= 20,
-	VT_UI8	= 21,
-	VT_INT	= 22,
-	VT_UINT	= 23,
-	VT_VOID	= 24,
-	VT_HRESULT	= 25,
-	VT_FILETIME	= 64
-};
-
-typedef unsigned short VARTYPE;
-typedef WORD PROPVAR_PAD1;
-typedef WORD PROPVAR_PAD2;
-typedef WORD PROPVAR_PAD3;
-
-typedef struct tagPROPVARIANT
-{
-  VARTYPE vt;
-  PROPVAR_PAD1 wReserved1;
-  PROPVAR_PAD2 wReserved2;
-  PROPVAR_PAD3 wReserved3;
-  union 
-  {
-    CHAR cVal;
-    UCHAR bVal;
-    SHORT iVal;
-    USHORT uiVal;
-    LONG lVal;
-    ULONG ulVal;
-    INT intVal;
-    UINT uintVal;
-    LARGE_INTEGER hVal;
-    ULARGE_INTEGER uhVal;
-    VARIANT_BOOL boolVal;
-    SCODE scode;
-    FILETIME filetime;
-    BSTR bstrVal;
-  };
-} PROPVARIANT;
-
-typedef PROPVARIANT tagVARIANT;
-typedef tagVARIANT VARIANT;
-typedef VARIANT VARIANTARG;
-
-MY_EXTERN_C BSTR SysAllocStringByteLen(LPCSTR psz, UINT len);
-MY_EXTERN_C BSTR SysAllocString(const OLECHAR *sz);
-MY_EXTERN_C void SysFreeString(BSTR bstr);
-MY_EXTERN_C UINT SysStringByteLen(BSTR bstr);
-MY_EXTERN_C UINT SysStringLen(BSTR bstr);
-
-MY_EXTERN_C DWORD GetLastError();
-MY_EXTERN_C HRESULT VariantClear(VARIANTARG *prop);
-MY_EXTERN_C HRESULT VariantCopy(VARIANTARG *dest, VARIANTARG *src);
-MY_EXTERN_C LONG CompareFileTime(const FILETIME* ft1, const FILETIME* ft2);
-
-#define CP_ACP    0
-#define CP_OEMCP  1
-
-typedef enum tagSTREAM_SEEK
-{	
-  STREAM_SEEK_SET	= 0,
-  STREAM_SEEK_CUR	= 1,
-  STREAM_SEEK_END	= 2
-} STREAM_SEEK;
-
-#endif
-#endif
+// MyWindows.h
+
+#ifndef __MYWINDOWS_H
+#define __MYWINDOWS_H
+
+#ifdef _WIN32
+
+#include <windows.h>
+
+#define CHAR_PATH_SEPARATOR '\\'
+#define WCHAR_PATH_SEPARATOR L'\\'
+#define STRING_PATH_SEPARATOR "\\"
+#define WSTRING_PATH_SEPARATOR L"\\"
+
+#else
+
+#define CHAR_PATH_SEPARATOR '/'
+#define WCHAR_PATH_SEPARATOR L'/'
+#define STRING_PATH_SEPARATOR "/"
+#define WSTRING_PATH_SEPARATOR L"/"
+
+#include <stddef.h> // for wchar_t
+#include <string.h>
+
+#include "MyGuidDef.h"
+
+typedef char CHAR;
+typedef unsigned char UCHAR;
+
+#undef BYTE
+typedef unsigned char BYTE;
+
+typedef short SHORT;
+typedef unsigned short USHORT;
+
+#undef WORD
+typedef unsigned short WORD;
+typedef short VARIANT_BOOL;
+
+typedef int INT;
+typedef Int32 INT32;
+typedef unsigned int UINT;
+typedef UInt32 UINT32;
+typedef INT32 LONG;   // LONG, ULONG and DWORD must be 32-bit
+typedef UINT32 ULONG;
+
+#undef DWORD
+typedef UINT32 DWORD;
+
+typedef Int64 LONGLONG;
+typedef UInt64 ULONGLONG;
+
+typedef struct LARGE_INTEGER { LONGLONG QuadPart; }LARGE_INTEGER;
+typedef struct _ULARGE_INTEGER { ULONGLONG QuadPart;} ULARGE_INTEGER;
+
+typedef const CHAR *LPCSTR;
+typedef CHAR TCHAR;
+typedef const TCHAR *LPCTSTR;
+typedef wchar_t WCHAR;
+typedef WCHAR OLECHAR;
+typedef const WCHAR *LPCWSTR;
+typedef OLECHAR *BSTR;
+typedef const OLECHAR *LPCOLESTR;
+typedef OLECHAR *LPOLESTR;
+
+typedef struct _FILETIME
+{
+  DWORD dwLowDateTime;
+  DWORD dwHighDateTime;
+}FILETIME;
+
+#define HRESULT LONG
+#define FAILED(Status) ((HRESULT)(Status)<0)
+typedef ULONG PROPID;
+typedef LONG SCODE;
+
+#define S_OK    ((HRESULT)0x00000000L)
+#define S_FALSE ((HRESULT)0x00000001L)
+#define E_NOTIMPL ((HRESULT)0x80004001L)
+#define E_NOINTERFACE ((HRESULT)0x80004002L)
+#define E_ABORT ((HRESULT)0x80004004L)
+#define E_FAIL ((HRESULT)0x80004005L)
+#define STG_E_INVALIDFUNCTION ((HRESULT)0x80030001L)
+#define E_OUTOFMEMORY ((HRESULT)0x8007000EL)
+#define E_INVALIDARG ((HRESULT)0x80070057L)
+
+#ifdef _MSC_VER
+#define STDMETHODCALLTYPE __stdcall 
+#else
+#define STDMETHODCALLTYPE 
+#endif
+
+#define STDMETHOD_(t, f) virtual t STDMETHODCALLTYPE f
+#define STDMETHOD(f) STDMETHOD_(HRESULT, f)
+#define STDMETHODIMP_(type) type STDMETHODCALLTYPE
+#define STDMETHODIMP STDMETHODIMP_(HRESULT)
+
+#define PURE = 0
+
+#define MIDL_INTERFACE(x) struct 
+
+struct IUnknown
+{
+  //virtual ~IUnknown() {}
+  STDMETHOD(QueryInterface) (REFIID iid, void **outObject) PURE;
+  STDMETHOD_(ULONG, AddRef)() PURE;
+  STDMETHOD_(ULONG, Release)() PURE;
+};
+
+typedef IUnknown *LPUNKNOWN;
+
+#define VARIANT_TRUE ((VARIANT_BOOL)-1)
+#define VARIANT_FALSE ((VARIANT_BOOL)0)
+
+enum VARENUM
+{	
+  VT_EMPTY	= 0,
+	VT_NULL	= 1,
+	VT_I2	= 2,
+	VT_I4	= 3,
+	VT_R4	= 4,
+	VT_R8	= 5,
+	VT_CY	= 6,
+	VT_DATE	= 7,
+	VT_BSTR	= 8,
+	VT_DISPATCH	= 9,
+	VT_ERROR	= 10,
+	VT_BOOL	= 11,
+	VT_VARIANT	= 12,
+	VT_UNKNOWN	= 13,
+	VT_DECIMAL	= 14,
+	VT_I1	= 16,
+	VT_UI1	= 17,
+	VT_UI2	= 18,
+	VT_UI4	= 19,
+	VT_I8	= 20,
+	VT_UI8	= 21,
+	VT_INT	= 22,
+	VT_UINT	= 23,
+	VT_VOID	= 24,
+	VT_HRESULT	= 25,
+	VT_FILETIME	= 64
+};
+
+typedef unsigned short VARTYPE;
+typedef WORD PROPVAR_PAD1;
+typedef WORD PROPVAR_PAD2;
+typedef WORD PROPVAR_PAD3;
+
+typedef struct tagPROPVARIANT
+{
+  VARTYPE vt;
+  PROPVAR_PAD1 wReserved1;
+  PROPVAR_PAD2 wReserved2;
+  PROPVAR_PAD3 wReserved3;
+  union 
+  {
+    CHAR cVal;
+    UCHAR bVal;
+    SHORT iVal;
+    USHORT uiVal;
+    LONG lVal;
+    ULONG ulVal;
+    INT intVal;
+    UINT uintVal;
+    LARGE_INTEGER hVal;
+    ULARGE_INTEGER uhVal;
+    VARIANT_BOOL boolVal;
+    SCODE scode;
+    FILETIME filetime;
+    BSTR bstrVal;
+  };
+} PROPVARIANT;
+
+typedef PROPVARIANT tagVARIANT;
+typedef tagVARIANT VARIANT;
+typedef VARIANT VARIANTARG;
+
+MY_EXTERN_C BSTR SysAllocStringByteLen(LPCSTR psz, UINT len);
+MY_EXTERN_C BSTR SysAllocString(const OLECHAR *sz);
+MY_EXTERN_C void SysFreeString(BSTR bstr);
+MY_EXTERN_C UINT SysStringByteLen(BSTR bstr);
+MY_EXTERN_C UINT SysStringLen(BSTR bstr);
+
+MY_EXTERN_C DWORD GetLastError();
+MY_EXTERN_C HRESULT VariantClear(VARIANTARG *prop);
+MY_EXTERN_C HRESULT VariantCopy(VARIANTARG *dest, VARIANTARG *src);
+MY_EXTERN_C LONG CompareFileTime(const FILETIME* ft1, const FILETIME* ft2);
+
+#define CP_ACP    0
+#define CP_OEMCP  1
+
+typedef enum tagSTREAM_SEEK
+{	
+  STREAM_SEEK_SET	= 0,
+  STREAM_SEEK_CUR	= 1,
+  STREAM_SEEK_END	= 2
+} STREAM_SEEK;
+
+#endif
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/NewHandler.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/NewHandler.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/NewHandler.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,16 +1,16 @@
-// Common/NewHandler.h
-
-#ifndef __COMMON_NEWHANDLER_H
-#define __COMMON_NEWHANDLER_H
-
-class CNewException {};
-
-#ifdef _WIN32
-void 
-#ifdef _MSC_VER
-__cdecl 
-#endif
-operator delete(void *p) throw();
-#endif 
-
-#endif 
+// Common/NewHandler.h
+
+#ifndef __COMMON_NEWHANDLER_H
+#define __COMMON_NEWHANDLER_H
+
+class CNewException {};
+
+#ifdef _WIN32
+void 
+#ifdef _MSC_VER
+__cdecl 
+#endif
+operator delete(void *p) throw();
+#endif 
+
+#endif 

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/StdAfx.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/StdAfx.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/StdAfx.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,9 +1,9 @@
-// StdAfx.h
-
-#ifndef __STDAFX_H
-#define __STDAFX_H
-
-// #include "MyWindows.h"
-#include "NewHandler.h"
-
-#endif 
+// StdAfx.h
+
+#ifndef __STDAFX_H
+#define __STDAFX_H
+
+// #include "MyWindows.h"
+#include "NewHandler.h"
+
+#endif 

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Types.h
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Types.h	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/Types.h	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,19 +1,19 @@
-// Common/Types.h
-
-#ifndef __COMMON_TYPES_H
-#define __COMMON_TYPES_H
-
-typedef unsigned char Byte;
-typedef short Int16;
-typedef unsigned short UInt16;
-typedef int Int32;
-typedef unsigned int UInt32;
-#ifdef _MSC_VER
-typedef __int64 Int64;
-typedef unsigned __int64 UInt64;
-#else
-typedef long long int Int64;
-typedef unsigned long long int UInt64;
-#endif
-
-#endif
+// Common/Types.h
+
+#ifndef __COMMON_TYPES_H
+#define __COMMON_TYPES_H
+
+typedef unsigned char Byte;
+typedef short Int16;
+typedef unsigned short UInt16;
+typedef int Int32;
+typedef unsigned int UInt32;
+#ifdef _MSC_VER
+typedef __int64 Int64;
+typedef unsigned __int64 UInt64;
+#else
+typedef long long int Int64;
+typedef unsigned long long int UInt64;
+#endif
+
+#endif

Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/LGPL.txt
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/LGPL.txt	2009-05-02 00:59:03 UTC (rev 4249)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/LGPL.txt	2009-05-02 12:42:30 UTC (rev 4250)
@@ -1,504 +1,504 @@
-      GNU LESSER GENERAL PUBLIC LICENSE
-           Version 2.1, February 1999
-
- Copyright (C) 1991, 1999 Free Software Foundation, Inc.
-     59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the Lesser GPL.  It also counts
- as the successor of the GNU Library Public License, version 2, hence
- the version number 2.1.]
-
-          Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
-  This license, the Lesser General Public License, applies to some
-specially designated software packages--typically libraries--of the
-Free Software Foundation and other authors who decide to use it.  You
-can use it too, but we suggest you first think carefully about whether
-this license or the ordinary General Public License is the better
-strategy to use in any particular case, based on the explanations below.
-
-  When we speak of free software, we are referring to freedom of use,
-not price.  Our General Public Licenses are designed to make sure that
-you have the freedom to distribute copies of free software (and charge
-for this service if you wish); that you receive source code or can get
-it if you want it; that you can change the software and use pieces of
-it in new free programs; and that you are informed that you can do
-these things.
-
-  To protect your rights, we need to make restrictions that forbid
-distributors to deny you these rights or to ask you to surrender these
-rights.  These restrictions translate to certain responsibilities for
-you if you distribute copies of the library or if you modify it.
-
-  For example, if you distribute copies of the library, whether gratis
-or for a fee, you must give the recipients all the rights that we gave
-you.  You must make sure that they, too, receive or can get the source
-code.  If you link other code with the library, you must provide
-complete object files to the recipients, so that they can relink them
-with the library after making changes to the library and recompiling
-it.  And you must show them these terms so they know their rights.
-
-  We protect your rights with a two-step method: (1) we copyright the
-library, and (2) we offer you this license, which gives you legal
-permission to copy, distribute and/or modify the library.
-
-  To protect each distributor, we want to make it very clear that
-there is no warranty for the free library.  Also, if the library is
-modified by someone else and passed on, the recipients should know
-that what they have is not the original version, so that the original
-author's reputation will not be affected by problems that might be
-introduced by others.
-

-  Finally, software patents pose a constant threat to the existence of
-any free program.  We wish to make sure that a company cannot
-effectively restrict the users of a free program by obtaining a
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-  Most GNU software, including some libraries, is covered by the
-ordinary GNU General Public License.  This license, the GNU Lesser
-General Public License, applies to certain designated libraries, and
-is quite different from the ordinary General Public License.  We use
-this license for certain libraries in order to permit linking those
-libraries into non-free programs.
-
-  When a program is linked with a library, whether statically or using
-a shared library, the combination of the two is legally speaking a
-combined work, a derivative of the original library.  The ordinary
-General Public License therefore permits such linking only if the
-entire combination fits its criteria of freedom.  The Lesser General
-Public License permits more lax criteria for linking other code with
-the library.
-
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-does Less to protect the user's freedom than the ordinary General
-Public License.  It also provides other free software developers Less
-of an advantage over competing non-free programs.  These disadvantages
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-special circumstances.
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-  For example, on rare occasions, there may be a special need to
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-programs enables a greater number of people to use a large body of
-free software.  For example, permission to use the GNU C Library in
-non-free programs enables many more people to use the whole GNU
-operating system, as well as its variant, the GNU/Linux operating
-system.
-
-  Although the Lesser General Public License is Less protective of the
-users' freedom, it does ensure that the user of a program that is
-linked with the Library has the freedom and the wherewithal to run
-that program using a modified version of the Library.
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-      GNU LESSER GENERAL PUBLIC LICENSE
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+
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+conditions either of that version or of any later version published by
+the Free Software Foundation.  If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+

+  14. If you wish to incorporate parts of the Library into other free
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+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+         END OF TERMS AND CONDITIONS
+

+           How to Apply These Terms to Your New Libraries
+
+  If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change.  You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+  To apply these terms, attach the following notices to the library.  It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the library's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
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+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
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+    License along with this library; if not, write to the Free Software
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+
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+
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+  Ty Coon, President of Vice
+
+That's all there is to it!
+
+




From peter at stuge.se  Sat May  2 15:26:50 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 2 May 2009 15:26:50 +0200
Subject: [coreboot] [v2] r4250 - in trunk/coreboot-v2: ...
Message-ID: <20090502132650.4868.qmail@stuge.se>

svn at coreboot.org wrote:
> Log:
> Run dos2unix on all files:

Thanks! Please watch out for line endings when committing. Thanks!


//Peter



From joe at settoplinux.org  Sat May  2 16:50:53 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 02 May 2009 10:50:53 -0400
Subject: [coreboot]
 =?utf-8?q?=5Bv2=5D_r4248_-_in_trunk/coreboot-v2/src/ma?=
 =?utf-8?q?inboard=3A=09rca/rm4100_thomson/ip1000?=
In-Reply-To: <49FC3291.3010104@gmx.net>
References: <20090502005143.22961gmx1@mx004.gmx.net> <49FC3291.3010104@gmx.net>
Message-ID: <d6b6ce1f95cdf82cf993c7c963555f56@imap.1and1.com>




On Sat, 02 May 2009 13:46:25 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Hi Joe,
> 
> there is a small problem with your commit. Both files has their line
> endings (newlines) changed from LF (Unix style) to CR+LF (DOS style).
> 
> On 02.05.2009 02:50, svn at coreboot.org wrote:
>> Author: linux_junkie
>> Date: 2009-05-02 02:50:58 +0200 (Sat, 02 May 2009)
>> New Revision: 4248
>>
>> Modified:
>>    trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c
>>    trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
>> Log:
>> Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only
> set ones that are actually connected to something.
>> Signed-off-by: Joseph Smith <joe at settoplinux.org>
>> Acked-by: Joseph Smith <joe at settoplinux.org>
>>
> 
> Almost all files in our tree have LF line terminators. Exceptions are:
> 
> CR+LF:
> src/southbridge/intel/i82801ca/i82801ca_pci.c
> src/northbridge/intel/i82830/vga.c
> src/cpu/intel/model_f4x/microcode_MBDF410D.h
> src/mainboard/thomson/ip1000/gpio.c
> src/mainboard/dell/s1850/irq_tables.c
> src/mainboard/rca/rm4100/gpio.c
> 
> Mix of CR+LF and LF:
> src/mainboard/msi/ms9185/Options.lb
> src/mainboard/msi/ms9282/Options.lb
> src/mainboard/asus/m2v-mx_se/Options.lb
> 
I'll have to admit, sometimes when it is slow at work I do use
wordpad/notepad to edit/create files. Unfortunately when I am at work I am
stuck in windows world...

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Sat May  2 16:52:28 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 02 May 2009 10:52:28 -0400
Subject: [coreboot] [v2] r4250 - in trunk/coreboot-v2: ...
In-Reply-To: <20090502132650.4868.qmail@stuge.se>
References: <20090502132650.4868.qmail@stuge.se>
Message-ID: <cc1b81c1e922362c833ad33370b8cf00@imap.1and1.com>




On Sat, 2 May 2009 15:26:50 +0200, Peter Stuge <peter at stuge.se> wrote:
> svn at coreboot.org wrote:
>> Log:
>> Run dos2unix on all files:
> 
> Thanks! Please watch out for line endings when committing. Thanks!
> 
> 
Thanks Peter, I will store that command in my memory bank :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Sat May  2 17:15:32 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 02 May 2009 11:15:32 -0400
Subject: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or
	use default
Message-ID: <0bfb3fe4b46ee3ce13e77d84c24afddd@imap.1and1.com>

This patch lets you assign PIRQs in mainboard Config.lb or use the default
ones listed in i82801xx_lpc.c.
Once and if everyone converts to the better way of assign PIRQs in
mainboard Config.lb the option of using the defaults can be removed. The
patch enables a margin of time to do so.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From joe at settoplinux.org  Sat May  2 17:20:34 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 02 May 2009 11:20:34 -0400
Subject: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb
 or use default
In-Reply-To: <0bfb3fe4b46ee3ce13e77d84c24afddd@imap.1and1.com>
References: <0bfb3fe4b46ee3ce13e77d84c24afddd@imap.1and1.com>
Message-ID: <00ed2f9e1f100d7a5515a91c4fe2c8a3@imap.1and1.com>



On Sat, 02 May 2009 11:15:32 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> This patch lets you assign PIRQs in mainboard Config.lb or use the
default
> ones listed in i82801xx_lpc.c.
> Once and if everyone converts to the better way of assign PIRQs in
> mainboard Config.lb the option of using the defaults can be removed. The
> patch enables a margin of time to do so.
> 
oh, thanks Stefan for the idea, tested, and
Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From rminnich at gmail.com  Sat May  2 22:39:53 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 May 2009 13:39:53 -0700
Subject: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb
	or use default
In-Reply-To: <00ed2f9e1f100d7a5515a91c4fe2c8a3@imap.1and1.com>
References: <0bfb3fe4b46ee3ce13e77d84c24afddd@imap.1and1.com>
	<00ed2f9e1f100d7a5515a91c4fe2c8a3@imap.1and1.com>
Message-ID: <13426df10905021339y7f03dd59t25fba91ae3bb4fa6@mail.gmail.com>

Very nice.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From rminnich at gmail.com  Sat May  2 22:42:34 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 May 2009 13:42:34 -0700
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <20090501211503.GA18155@localdomain>
References: <20090501211503.GA18155@localdomain>
Message-ID: <13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>

It does look like an SMP machine in which both CPUs are trying to run
as the BSP.

Possible?

ron



From svn at coreboot.org  Sat May  2 23:30:58 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  2 May 2009 23:30:58 +0200
Subject: [coreboot] [v2] r4251 -
	trunk/coreboot-v2/src/southbridge/intel/i82801xx
Message-ID: <mailman.3151.1355071534.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-02 23:30:57 +0200 (Sat, 02 May 2009)
New Revision: 4251

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
Log:
Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe at settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h	2009-05-02 12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h	2009-05-02 21:30:57 UTC (rev 4251)
@@ -31,6 +31,18 @@
 #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
 
 struct southbridge_intel_i82801xx_config {
+	/**
+	 * Interrupt Routing configuration
+	 * If bit7 is 1, the interrupt is disabled.
+	 */
+	uint8_t pirqa_routing;
+	uint8_t pirqb_routing;
+	uint8_t pirqc_routing;
+	uint8_t pirqd_routing;
+	uint8_t pirqe_routing;
+	uint8_t pirqf_routing;
+	uint8_t pirqg_routing;
+	uint8_t pirqh_routing;
 };
 
 extern struct chip_operations southbridge_intel_i82801xx_ops;

Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-05-02 12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c	2009-05-02 21:30:57 UTC (rev 4251)
@@ -36,6 +36,8 @@
 
 #define NMI_OFF 0
 
+typedef struct southbridge_intel_i82801xx_config config_t;
+
 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
  * 0x01 - 0001 = Reserved
@@ -66,7 +68,11 @@
 #define PIRQG 0x0A
 #define PIRQH 0x0B
 
-/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+/* 
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's. 
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your mainboards Config.lb.
+*/
 
 void i82801xx_enable_apic(struct device *dev)
 {
@@ -114,18 +120,59 @@
 
 static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
 {
-	/* Route PIRQA - PIRQD. */
-	pci_write_config8(dev, PIRQA_ROUT, PIRQA);
-	pci_write_config8(dev, PIRQB_ROUT, PIRQB);
-	pci_write_config8(dev, PIRQC_ROUT, PIRQC);
-	pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
 
+	if (config->pirqa_routing) {
+		pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+	} else {
+		pci_write_config8(dev, PIRQA_ROUT, PIRQA);
+	}
+
+	if (config->pirqb_routing) {
+		pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+	} else {
+		pci_write_config8(dev, PIRQB_ROUT, PIRQB);
+	}
+
+	if (config->pirqc_routing) {
+		pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+	} else {
+		pci_write_config8(dev, PIRQC_ROUT, PIRQC);
+	}
+
+	if (config->pirqd_routing) {
+		pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+	} else {
+		pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+	}
+
 	/* Route PIRQE - PIRQH (for ICH2-ICH9). */
 	if (ich_model >= 0x2440) {
-		pci_write_config8(dev, PIRQE_ROUT, PIRQE);
-		pci_write_config8(dev, PIRQF_ROUT, PIRQF);
-		pci_write_config8(dev, PIRQG_ROUT, PIRQG);
-		pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+
+		if (config->pirqe_routing) {
+			pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+		} else {
+			pci_write_config8(dev, PIRQE_ROUT, PIRQE);
+		}
+
+		if (config->pirqf_routing) {
+			pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+		} else {
+			pci_write_config8(dev, PIRQF_ROUT, PIRQF);
+		}
+
+		if (config->pirqg_routing) {
+			pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+		} else {
+			pci_write_config8(dev, PIRQG_ROUT, PIRQG);
+		}
+
+		if (config->pirqh_routing) {
+			pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+		} else {
+			pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+		}
 	}
 }
 




From joe at settoplinux.org  Sat May  2 23:31:44 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 02 May 2009 17:31:44 -0400
Subject: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb
 or use default
In-Reply-To: <13426df10905021339y7f03dd59t25fba91ae3bb4fa6@mail.gmail.com>
References: <0bfb3fe4b46ee3ce13e77d84c24afddd@imap.1and1.com>
	<00ed2f9e1f100d7a5515a91c4fe2c8a3@imap.1and1.com>
	<13426df10905021339y7f03dd59t25fba91ae3bb4fa6@mail.gmail.com>
Message-ID: <df67e67aada5e96c2322d5da9516ccb2@imap.1and1.com>




On Sat, 2 May 2009 13:39:53 -0700, ron minnich <rminnich at gmail.com> wrote:
> Very nice.
> 
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Thanks r4251

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From r.marek at assembler.cz  Sat May  2 23:54:18 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 02 May 2009 23:54:18 +0200
Subject: [coreboot] [PATCH] fix the XIP size and fallback computations for
	M2V-MX SE
Message-ID: <49FCC10A.7060504@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

It seems I'm quite tired to formulate the description of the patch accurately I
hope it is understandable somehow.

Following patch fixes the XIP computation issue. I removed the normal image
because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)

This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.

Third reason is that now it makes 384KB for additional ROMs and payload - plenty
of space for CBFS fun ;)

Now it uses generic _ROMBASE etc computation which is nice too.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf


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Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkn8wQgACgkQ3J9wPJqZRNUftgCfXjuQUkJwksgI4VU81mdJ78Kh
PyMAoMMWXjUKmq5YVQhsWZ6iFMEdgTSu
=mtSc
-----END PGP SIGNATURE-----
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From ward at gnu.org  Sat May  2 23:58:15 2009
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 2 May 2009 17:58:15 -0400
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>
References: <20090501211503.GA18155@localdomain>
	<13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>
Message-ID: <20090502215815.GA1931@localdomain>

On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
> It does look like an SMP machine in which both CPUs are trying to run
> as the BSP.
> 
> Possible?

It's definitely an SMP machine, two dual-core CPUs.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From c-d.hailfinger.devel.2006 at gmx.net  Sun May  3 00:25:29 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 03 May 2009 00:25:29 +0200
Subject: [coreboot] LinuxTag 2009 in Berlin, June 24-27
In-Reply-To: <43e8564ca75ab4d5acf81e17628df371@imap.1and1.com>
References: <20090429221636.23865.qmail@stuge.se> <49F8D6CD.9070008@gmx.net>
	<20090429233345.9898.qmail@stuge.se> <49FAD41A.8080801@gmx.net>
	<43e8564ca75ab4d5acf81e17628df371@imap.1and1.com>
Message-ID: <49FCC859.4040008@gmx.net>

On 01.05.2009 13:26, Joseph Smith wrote:
>> (Or my top hat flash for these boards if that works out.)
>>
>>     
> What is this?
>   

http://www.coreboot.org/Top_Hat_Flash

I hope to build something similar for M2A-VM boards. The pinout and my
multimeter measurements certainly look favourable.

Ah yes. A generic top hat flash PCB with two or three jumpers would
probably handle almost every soldered LPC/FWH chip out there.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sun May  3 01:38:12 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 2 May 2009 16:38:12 -0700
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <20090502215815.GA1931@localdomain>
References: <20090501211503.GA18155@localdomain>
	<13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>
	<20090502215815.GA1931@localdomain>
Message-ID: <13426df10905021638oe5e6bf4vec06e7d994b24119@mail.gmail.com>

On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege <ward at gnu.org> wrote:
> On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
>> It does look like an SMP machine in which both CPUs are trying to run
>> as the BSP.
>>
>> Possible?
>
> It's definitely an SMP machine, two dual-core CPUs.

So can you see what changed in the k8 north/cpu support since the last
time it worked?

ron



From ward at gnu.org  Sun May  3 02:40:46 2009
From: ward at gnu.org (Ward Vandewege)
Date: Sat, 2 May 2009 20:40:46 -0400
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <13426df10905021638oe5e6bf4vec06e7d994b24119@mail.gmail.com>
References: <20090501211503.GA18155@localdomain>
	<13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>
	<20090502215815.GA1931@localdomain>
	<13426df10905021638oe5e6bf4vec06e7d994b24119@mail.gmail.com>
Message-ID: <20090503004046.GA10185@localdomain>

On Sat, May 02, 2009 at 04:38:12PM -0700, ron minnich wrote:
> On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege <ward at gnu.org> wrote:
> > On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
> >> It does look like an SMP machine in which both CPUs are trying to run
> >> as the BSP.
> >>
> >> Possible?
> >
> > It's definitely an SMP machine, two dual-core CPUs.
> 
> So can you see what changed in the k8 north/cpu support since the last
> time it worked?

Sure. The last time it worked is r4232, I had to bisect to find the commit
causing the problem. r4233/4234 are one changeset.

src/northbridge/amd is unchanged by this changeset.

The diff for src/cpu/amd is attached.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator
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From patrick at georgi-clan.de  Sun May  3 09:42:52 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 03 May 2009 09:42:52 +0200
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <20090503004046.GA10185@localdomain>
References: <20090501211503.GA18155@localdomain>	<13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>	<20090502215815.GA1931@localdomain>	<13426df10905021638oe5e6bf4vec06e7d994b24119@mail.gmail.com>
	<20090503004046.GA10185@localdomain>
Message-ID: <49FD4AFC.2080702@georgi-clan.de>

Am 03.05.2009 02:40, schrieb Ward Vandewege:
> On Sat, May 02, 2009 at 04:38:12PM -0700, ron minnich wrote:
>> On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege<ward at gnu.org>  wrote:
>>> On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
>>>> It does look like an SMP machine in which both CPUs are trying to run
>>>> as the BSP.
>>>>
>>>> Possible?
>>> It's definitely an SMP machine, two dual-core CPUs.
>> So can you see what changed in the k8 north/cpu support since the last
>> time it worked?
>
> Sure. The last time it worked is r4232, I had to bisect to find the commit
> causing the problem. r4233/4234 are one changeset.
>
> src/northbridge/amd is unchanged by this changeset.
>
> The diff for src/cpu/amd is attached.
The various copies of "copy_and_run" were merged into
src/arch/i386/lib/copy_and_run.c.
I tweaked the coreboot_apc generation a bit, by adding the serial driver 
and console output code. It worked on a fam10 board here, so I didn't 
think it to cause much trouble - seems like it does.

The interleaved messages are

(by the BSP)
malloc Enter, size 1100, free_mem_ptr 00148000
malloc 00148000
CPU APIC: 01

(by the AP)
image length = 00002a6c
Jumping to image.

That's definitely a different image used for the AP than the one for the 
BSP (see image length some lines earlier)


Patrick



From svn at coreboot.org  Sun May  3 16:25:55 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 May 2009 16:25:55 +0200
Subject: [coreboot] [BuildROM] r264 - buildrom-devel/packages/filo
Message-ID: <mailman.3152.1355071535.16123.coreboot@coreboot.org>

Author: ward
Date: 2009-05-03 16:25:54 +0200 (Sun, 03 May 2009)
New Revision: 264

Modified:
   buildrom-devel/packages/filo/filo.mk
Log:

Bump up filo to the latest rev. Boot tested on alix.2c3. This is a trivial patch.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/packages/filo/filo.mk
===================================================================
--- buildrom-devel/packages/filo/filo.mk	2009-04-08 15:26:59 UTC (rev 263)
+++ buildrom-devel/packages/filo/filo.mk	2009-05-03 14:25:54 UTC (rev 264)
@@ -1,5 +1,5 @@
 FILO_URL=svn://coreboot.org/filo/trunk/filo
-FILO_TAG=85
+FILO_TAG=94
 
 FILO_DIR=$(BUILD_DIR)/filo
 FILO_SRC_DIR=$(FILO_DIR)/svn




From svn at coreboot.org  Sun May  3 16:27:09 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  3 May 2009 16:27:09 +0200
Subject: [coreboot] [BuildROM] r265 - buildrom-devel/config/platforms
Message-ID: <mailman.3153.1355071535.16123.coreboot@coreboot.org>

Author: ward
Date: 2009-05-03 16:27:08 +0200 (Sun, 03 May 2009)
New Revision: 265

Modified:
   buildrom-devel/config/platforms/alix2c3.conf
Log:

Bump up v3 rev to head. Boot tested. This is a trivial patch.

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Ward Vandewege <ward at gnu.org>



Modified: buildrom-devel/config/platforms/alix2c3.conf
===================================================================
--- buildrom-devel/config/platforms/alix2c3.conf	2009-05-03 14:25:54 UTC (rev 264)
+++ buildrom-devel/config/platforms/alix2c3.conf	2009-05-03 14:27:08 UTC (rev 265)
@@ -18,7 +18,7 @@
 
 COREBOOT_VENDOR=pcengines
 COREBOOT_BOARD=alix2c3
-CBV3_TAG=682
+CBV3_TAG=1165
 
 # FILO configuration
 




From kbaski at yahoo.com  Sun May  3 19:16:33 2009
From: kbaski at yahoo.com (Baski)
Date: Sun, 3 May 2009 10:16:33 -0700 (PDT)
Subject: [coreboot] linux OS installation through FILO/coreboot
Message-ID: <701172.91627.qm@web51607.mail.re2.yahoo.com>

Hi,
Has anyone tried Linux OS installation on coreboot with FILO?? If yes, any hints or how-to?
TIA
- Baski



      
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From joe at settoplinux.org  Sun May  3 19:23:47 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 03 May 2009 13:23:47 -0400
Subject: [coreboot] linux OS installation through FILO/coreboot
In-Reply-To: <701172.91627.qm@web51607.mail.re2.yahoo.com>
References: <701172.91627.qm@web51607.mail.re2.yahoo.com>
Message-ID: <0a8670526e02e19ec998ff5b5f9c051d@imap.1and1.com>




On Sun, 3 May 2009 10:16:33 -0700 (PDT), Baski <kbaski at yahoo.com> wrote:
> Hi,
> Has anyone tried Linux OS installation on coreboot with FILO?? If yes,
> any hints or how-to?
> TIA
> - Baski
> 
Sure, see:
http://www.coreboot.org/FILO

the CD-ROM Booting section.

You can also check out:
http://www.settoplinux.org/index.php?title=RCA_RM4100:Howto_coreboot_and_Linux

the Putting Linux on your RM4100 section.

Hope that helps.
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From service at houghtalingsgarage.com  Sun May  3 21:08:00 2009
From: service at houghtalingsgarage.com (Roger Treat)
Date: Sun, 03 May 2009 14:08:00 -0500
Subject: [coreboot] coreboot-sdk
Message-ID: <49FDEB90.2090501@houghtalingsgarage.com>

Is there anywhere to get the sdk software other than cwlinux?



From svn at coreboot.org  Mon May  4 01:33:05 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 01:33:05 +0200
Subject: [coreboot] [flashrom] r453 - trunk
Message-ID: <mailman.3154.1355071535.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-04 01:33:05 +0200 (Mon, 04 May 2009)
New Revision: 453

Modified:
   trunk/README
Log:
Complement the README file with build instructions for the platforms it
currently compiles on.

Signed-off-by: Idwer Vollering <vidwer at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/README
===================================================================
--- trunk/README	2009-05-01 16:34:32 UTC (rev 452)
+++ trunk/README	2009-05-03 23:33:05 UTC (rev 453)
@@ -15,12 +15,21 @@
 Build Requirements
 ------------------
 
-To build the flashrom utility you need to install the following packages:
+To build the flashrom utility you need to install the following packages or
+ports:
 
+Linux et al:
 * pciutils
 * pciutils-devel / pciutils-dev / libpci-dev
 * zlib-devel / zlib1g-dev
 
+On FreeBSD, you need the following ports:
+* devel/gmake
+* devel/libpci
+
+To compile on FreeBSD, use the command below:
+gmake
+
 To compile on Solaris, use the commands below:
 gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2
 




From svn at coreboot.org  Mon May  4 14:18:10 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 14:18:10 +0200
Subject: [coreboot] [flashrom] r454 - trunk
Message-ID: <mailman.3155.1355071535.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-04 14:18:10 +0200 (Mon, 04 May 2009)
New Revision: 454

Modified:
   trunk/Makefile
   trunk/flashrom.c
Log:
flashrom 0.9.0

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/Makefile
===================================================================
--- trunk/Makefile	2009-05-03 23:33:05 UTC (rev 453)
+++ trunk/Makefile	2009-05-04 12:18:10 UTC (rev 454)
@@ -38,10 +38,8 @@
 
 all: pciutils dep $(PROGRAM)
 
-# Set the flashrom version string from the highest revision number
-# of the checked out flashrom files.
-SVNDEF := -D'FLASHROM_VERSION="$(shell svnversion -cn . \
-          | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
+# Set the flashrom version string
+SVNDEF := -D'FLASHROM_VERSION="0.9.0"'
 
 $(PROGRAM): $(OBJS)
 	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)

Modified: trunk/flashrom.c
===================================================================
--- trunk/flashrom.c	2009-05-03 23:33:05 UTC (rev 453)
+++ trunk/flashrom.c	2009-05-04 12:18:10 UTC (rev 454)
@@ -326,7 +326,7 @@
 
 void print_version(void)
 {
-	printf("flashrom r%s\n", FLASHROM_VERSION);
+	printf("flashrom v%s\n", FLASHROM_VERSION);
 }
 
 int main(int argc, char *argv[])




From svn at coreboot.org  Mon May  4 14:22:27 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 14:22:27 +0200
Subject: [coreboot] [flashrom] r455 - /
Message-ID: <mailman.3156.1355071535.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-04 14:22:27 +0200 (Mon, 04 May 2009)
New Revision: 455

Added:
   tags/
Log:
Create a tags directory for flashrom.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>





From svn at coreboot.org  Mon May  4 14:23:25 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 14:23:25 +0200
Subject: [coreboot] [flashrom] r456 - tags
Message-ID: <mailman.3157.1355071535.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-04 14:23:25 +0200 (Mon, 04 May 2009)
New Revision: 456

Added:
   tags/flashrom-0.9.0/
Log:
flashrom 0.9.0 tag

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>





From svn at coreboot.org  Mon May  4 14:29:59 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 14:29:59 +0200
Subject: [coreboot] [flashrom] r457 - trunk
Message-ID: <mailman.3158.1355071535.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-04 14:29:59 +0200 (Mon, 04 May 2009)
New Revision: 457

Modified:
   trunk/Makefile
Log:
Onwards with development. Re-add the svn revision to the version string.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/Makefile
===================================================================
--- trunk/Makefile	2009-05-04 12:23:25 UTC (rev 456)
+++ trunk/Makefile	2009-05-04 12:29:59 UTC (rev 457)
@@ -38,8 +38,10 @@
 
 all: pciutils dep $(PROGRAM)
 
-# Set the flashrom version string
-SVNDEF := -D'FLASHROM_VERSION="0.9.0"'
+# Set the flashrom version string from the highest revision number
+# of the checked out flashrom files.
+SVNDEF := -D'FLASHROM_VERSION="0.9.0-r$(shell svnversion -cn . \
+          | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
 
 $(PROGRAM): $(OBJS)
 	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)




From c-d.hailfinger.devel.2006 at gmx.net  Mon May  4 16:41:40 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 04 May 2009 16:41:40 +0200
Subject: [coreboot] [ANNOUNCE] flashrom 0.9.0 has been released!
Message-ID: <49FEFEA4.9090604@gmx.net>

The flashrom developers are happy to announce the release of flashrom 0.9.0.

flashrom is a utility for reading, writing, erasing and verifying flash
ROM chips.

flashrom is often used to flash BIOS/coreboot/firmware images because it
allows you to update your BIOS/coreboot/firmware without opening the
computer and without any special boot procedures.

After nine years of development and constant improvement, we have added
support for every BIOS flash ROM technology present on x86 mainboards
and every flash ROM chip we ever saw in the wild.

Highlights of flashrom include:
- Parallel, LPC, FWH and SPI flash interfaces.
- 157 flash chip families and half a dozen variants of each family.
- Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32,
TSOP40 and more have all been verified to work.
- 75 different chipsets, some with multiple flash controllers.
- Special mainboard enabling code for dozens of nonstandard mainboards.
- No physical access needed. root access is sufficient.
- No bootable floppy disk, bootable CD-ROM or other media needed.
- No keyboard or monitor needed. Simply reflash remotely via SSH.
- No instant reboot needed. Reflash your ROM in a running system, verify
it, be happy. The new firmware will be present next time you boot.
- Crossflashing and hotflashing is possible as long as the flash chips
are electrically and logically compatible (same protocol). Great for
recovery.
- Scriptability. Reflash a whole pool of identical machines at the same
time from the command line. It is recommended to check flashrom output
and error codes.
- Speed. flashrom is much faster than vendor flash tools.
- Supports Linux, FreeBSD, DragonFly BSD, Solaris, Mac OS X. Please
refer to the README for build instructions.

Thanks go to everyone who contributed to flashrom over the years and
especially to Li-Ta Lo for starting this project.

Please note that rewriting your flash chip can be dangerous and flashrom
developers make no guarantees whatsoever. That said, many users have
successfully replaced proprietary tools such as awdflash, amiflash and
afudos with flashrom.

flashrom has its own home page at http://coreboot.org/flashrom

flashrom 0.9.0 can be downloaded in various ways:

Anonymous checkout from the subversion repository at
svn://coreboot.org/flashrom/tags/flashrom-0.9.0

Tarball download at
http://qa.coreboot.org/releases/flashrom-0.9.0.tar.gz
http://qa.coreboot.org/releases/flashrom-0.9.0.tar.bz2
with GPG signatures at
http://qa.coreboot.org/releases/flashrom-0.9.0.tar.{gz,bz2}.asc




From svn at coreboot.org  Mon May  4 19:29:15 2009
From: svn at coreboot.org (coreboot)
Date: Mon, 04 May 2009 17:29:15 -0000
Subject: [coreboot]  #130: flashrom segfault (with backtrace)
Message-ID: <053.8685f970fa6e8c55c68283c093db37cb@coreboot.org>

#130: flashrom segfault (with backtrace)
---------------------------------+------------------------------------------
   Reporter:  fragabr@?          |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  flashrom           |        Version:  v2      
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 I want to test flashrom with a supported motherboard (Asus M2N-E with
 Linux 2.6.30-rc4) and it segfaults when I run it. I'm using the latest
 libpci (3.1.2):


 {{{
 Calibrating delay loop... OK.
 No coreboot table found.
 Segmentation fault
 }}}


 Backtrace:

 {{{
 #0  0x00007f1395141d49 in pci_fill_info_v31 () from
 /usr/local/lib/libpci.so.3
 #1  0x00007f1395143c59 in pci_filter_match () from
 /usr/local/lib/libpci.so.3
 #2  0x000000000040732f in ?? ()
 #3  0x00000000004016f8 in ?? ()
 #4  0x0000000000406d46 in ?? ()
 #5  0x00007f1394df24f6 in __libc_start_main () from /lib64/libc.so.6
 #6  0x0000000000401619 in ?? ()
 #7  0x00007fff9d579e98 in ?? ()
 #8  0x000000000000001c in ?? ()
 #9  0x0000000000000001 in ?? ()
 #10 0x00007fff9d57ab55 in ?? ()
 #11 0x0000000000000000 in ?? ()

 }}}

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/130>
coreboot <http://www.coreboot.org/>


From libv at skynet.be  Mon May  4 19:37:51 2009
From: libv at skynet.be (Luc Verhaegen)
Date: Mon, 4 May 2009 19:37:51 +0200
Subject: [coreboot] [PATCH] Free VGA BIOS for K8M890
In-Reply-To: <49FB6CB9.2000008@assembler.cz>
References: <49F317A5.4080401@assembler.cz>
	<13426df10904250925v44370982xc92c9fe408319c2c@mail.gmail.com>
	<20090426031036.GB21580@skynet.be> <49FB6CB9.2000008@assembler.cz>
Message-ID: <20090504173751.GA13304@skynet.be>

On Fri, May 01, 2009 at 11:42:17PM +0200, Rudolf Marek wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Hi again,
> 
> I'm attaching a rewritten version from VGA ROM, which mimics the BIOS init.
> 
> Sadly enough it is still not hitting the all required regs to make powernow
> working as it is with orig bios.
> 
> The rest register spill is the captured IO as it was. The top of the file is
> what bios is doing during the init. Just before it calls ax=0003 and exits the rom.
> 
> There is also one interresting place:
> 
> <------>write_cr((read_cr(0x36) & ~0x30) | (0x3 << 4), 0x36);

VGA H/VSync off.

> <------>write_cr((read_cr(0x30) & ~0x4), 0x30);

Disable Power Now Signals in CRTC1, as can be read from public via docs.

> <------>/* just read, hope compiler won't optimize that out */
> <------>tmp = inb(0x3da);
> <------>tmp = inb(0x3ba);

STAT1 (both colour and mono)
 
> <------>outb(0x0, 0x3c0);

STAT0

> 
> /* original bios has it but if I compile it in I get blank screen */
> //<---->tmp = inb(0x3da);
> <------>tmp = inb(0x3ba);

Halfway through the dump the vga device is set from mono to colour.

> The bios is doing it exactly like this. But if I enable the inb(0x3da) I get no
> picture but monitors seems to have some signal. It works fine without those
> inbs. Any idea what is doing the code?

Hrm. This is the AR register accesses. They require a read from STAT1 
for the internal counter to be reset and thus for correct read/write 
operations.

Luc Verhaegen.



From r.marek at assembler.cz  Mon May  4 19:39:38 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 04 May 2009 19:39:38 +0200
Subject: [coreboot] [PATCH] Free VGA BIOS for K8M890
In-Reply-To: <20090504173751.GA13304@skynet.be>
References: <49F317A5.4080401@assembler.cz>
	<13426df10904250925v44370982xc92c9fe408319c2c@mail.gmail.com>
	<20090426031036.GB21580@skynet.be> <49FB6CB9.2000008@assembler.cz>
	<20090504173751.GA13304@skynet.be>
Message-ID: <49FF285A.1040607@assembler.cz>


> Hrm. This is the AR register accesses. They require a read from STAT1 
> for the internal counter to be reset and thus for correct read/write 
> operations.
>   

I inserted a delay there, now it works. The bios has there just some 
CALL and I have it in one instruction stream. Maybe it is too fast.

Rudolf




From svn at coreboot.org  Mon May  4 20:07:10 2009
From: svn at coreboot.org (coreboot)
Date: Mon, 04 May 2009 18:07:10 -0000
Subject: [coreboot] #130: flashrom segfault (with backtrace)
In-Reply-To: <053.8685f970fa6e8c55c68283c093db37cb@coreboot.org>
References: <053.8685f970fa6e8c55c68283c093db37cb@coreboot.org>
Message-ID: <062.208418c0877c7cb9129f92a0742848aa@coreboot.org>

#130: flashrom segfault (with backtrace)
---------------------------------+------------------------------------------
   Reporter:  fragabr@?          |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  flashrom           |        Version:  v2      
   Keywords:                     |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by FENG Yu Ning <fengyuning1984@?>):

 Maybe you would like to run flashrom again with the verbose output
 option(-V) and attach the output. That should provide more information to
 diagnose the problem.

 You can also build an unstripped flashrom and backtrace again. Commenting
 out the strip command in makefile should do the job.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/130#comment:1>
coreboot <http://www.coreboot.org/>


From mylesgw at gmail.com  Mon May  4 20:51:43 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 12:51:43 -0600
Subject: [coreboot] [PATCH] Build warnings
Message-ID: <2831fecf0905041151n3ff9320bp65795a1988dc8057@mail.gmail.com>

This patch removes these warnings:
Makefile:435: warning: overriding commands for target `src/lib/memset.o'

And replaces these debug messages:
partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8>
part pci_domain
with:
partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain

The warnings come about because some object files are used INITOBJECTS
and OBJECTS.  They get written to the makefile twice.  I factored out
a function that writes the rules, then only write out the rules that
haven't been written.

The debugging messages is personal taste, so if someone really objects
I'll leave that part out.

Abuild tested.  The makefiles are identical except for the missing duplicates.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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Index: svn/util/newconfig/config.g
===================================================================
--- svn.orig/util/newconfig/config.g
+++ svn/util/newconfig/config.g
@@ -323,6 +323,22 @@ class romimage:
 			return
 		fatal("No such rule \"%s\" for addmakedepend" % id)
 
+	def addmakeobject(self, file, obj):
+		source = topify(obj[1])
+		type = obj[2]
+		if (type  == 'S'):
+			# for .S, .o depends on .s
+			file.write("%s: %s.s\n" % (obj[0], obj[3]))
+        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
+			# and .s depends on .S
+			file.write("%s.s: %s\n" % (obj[3], source))
+			# Note: next 2 lines are ONE output line!
+        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
+			file.write(">$@.new && mv $@.new $@\n")
+		else:
+			file.write("%s: %s\n" % (obj[0], source))
+			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+
 	# this is called with an an object name. 
 	# the easiest thing to do is add this object to the current 
 	# component.
@@ -608,8 +624,12 @@ class option_value:
 class partobj:
 	"""A configuration part"""
 	def __init__ (self, image, dir, parent, part, type_name, instance_name, chip_or_device):
-		debug.info(debug.object, "partobj dir %s parent %s part %s" \
-				% (dir, parent, part))
+		if (parent):
+			debug.info(debug.object, "partobj dir %s parent %s part %s" \
+				% (dir, parent.instance_name, part))
+		else:
+			debug.info(debug.object, "partobj dir %s part %s" \
+				% (dir, part))
 
 		# romimage that is configuring this part
 		self.image = image
@@ -2166,38 +2186,15 @@ def writeimagemakefile(image):
 
 	file.write("\n# initobjectrules:\n")
 	for irule, init in image.getinitobjectrules().items():
-		source = topify(init[1])
-		type = init[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (init[0], init[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (init[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
-		else:
-			file.write("%s: %s\n" % (init[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+		image.addmakeobject(file, init);
 
-	file.write("\n# objectrules:\n")
+	file.write("\n# objectrules (don't duplicate initobjects):\n")
 	for objrule, obj in image.getobjectrules().items():
-		source = topify(obj[1])
-		type = obj[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (obj[0], obj[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (obj[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
+
+		if (getdict(image.getinitobjectrules(), obj[3])):
+			debug.info(debug.object, "skipping %s" % (obj[3]))
 		else:
-			file.write("%s: %s\n" % (obj[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
-		#file.write("%s\n" % objrule[2])
+			image.addmakeobject(file, obj);
 
 	for driverrule, driver in image.getdriverrules().items():
 		source = topify(driver[1])
@@ -2207,20 +2204,7 @@ def writeimagemakefile(image):
 
 	file.write("\n# smmobjectrules:\n")
 	for irule, smm in image.getsmmobjectrules().items():
-		source = topify(smm[1])
-		type = smm[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (smm[0], smm[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (smm[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
-		else:
-			file.write("%s: %s\n" % (smm[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+		image.addmakeobject(file, smm);
 
 	# special rule for chip_target.c
 	file.write("static.o: static.c\n")

From r.marek at assembler.cz  Mon May  4 20:49:14 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 04 May 2009 20:49:14 +0200
Subject: [coreboot] slides/presentation
Message-ID: <49FF38AA.7080008@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello all,

I decided to speak a bit about coreboot in a student (university) UNIX/Linux
club. Are there any slides so I can "pirate" them and maybe improve them a bit?

Thanks,
Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkn/OKUACgkQ3J9wPJqZRNUnXwCgqAJxGLqtsIehElyb5vSYIRxG
p9MAoLbe/2Kx9iGuT0iddyNsPf2OkDF2
=GD2B
-----END PGP SIGNATURE-----



From svn at coreboot.org  Mon May  4 21:26:43 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 21:26:43 +0200
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
Message-ID: <mailman.3159.1355071535.16123.coreboot@coreboot.org>

Author: ruik
Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009)
New Revision: 4252

Modified:
   trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
Log:
The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change.
I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;).

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Rudolf Marek <r.marek at assembler.cz>



Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c	2009-05-02 21:30:57 UTC (rev 4251)
+++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c	2009-05-04 19:26:43 UTC (rev 4252)
@@ -6,8 +6,13 @@
 	// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
 	// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
 	// so noline clear_init_ram
+
+#if HAVE_ACPI_RESUME == 1
+	/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
+	clear_memory( _RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  _RAMBASE - DCACHE_RAM_SIZE);
+#else
         clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
-
+#endif
 }
 
 /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/




From svn at coreboot.org  Mon May  4 21:31:44 2009
From: svn at coreboot.org (coreboot)
Date: Mon, 04 May 2009 19:31:44 -0000
Subject: [coreboot]  #131: New flashrom motherboard support
Message-ID: <045.fafa58fccf6f1868f71243ff245dc850@coreboot.org>

#131: New flashrom motherboard support
---------------------------------+------------------------------------------
   Reporter:  anonymous          |          Owner:  somebody        
       Type:  enhancement        |         Status:  new             
   Priority:  trivial            |      Milestone:  Going mainstream
  Component:  flashrom           |        Version:  v2              
   Keywords:  flashrom asus      |   Dependencies:                  
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Did not know where I should put this but the bugtracker seemed like the
 right place.

 I tried flashrom and it could not detect my chip on my ASUS P5ND2-SLI
 Deluxe motherboard. The board has a SST49LF004B flash chip and after
 enforcing the right chip flashrom seems to work fine.

 {{{
 # ./flashrom -V -f -r -c SST49LF004A/B test
 Calibrating delay loop... 796M loops per second, 100 myus = 201 us. OK.
 No coreboot table found.
 WARNING: No chipset found. Flash detection will most likely fail.
 Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x21, id2 0x5e,
 id1 parity violation
 No EEPROM/flash device found.
 Force read (-f -r -c) requested, forcing chip probe success:
 Probing for SST SST49LF004A/B, 512 KB: Found chip "SST SST49LF004A/B" (512
 KB) at physical address 0xfff80000.
 Force reading flash... done.
 }}}

 This should probably apply to the P5ND-SLI board, too.

 What do you need from me for adding autodetection of this board/chip?

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131>
coreboot <http://www.coreboot.org/>


From mylesgw at gmail.com  Mon May  4 21:52:05 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 13:52:05 -0600
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
In-Reply-To: <49ff417f.081abc0a.6e0c.ffffaf4eSMTPIN_ADDED@mx.google.com>
References: <49ff417f.081abc0a.6e0c.ffffaf4eSMTPIN_ADDED@mx.google.com>
Message-ID: <2831fecf0905041252r3ead1bb7x8916b312539eab6b@mail.gmail.com>

On Mon, May 4, 2009 at 1:26 PM,  <svn at coreboot.org> wrote:
> Author: ruik
> Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009)
> New Revision: 4252
>
> Modified:
> ? trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
> Log:
> The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change.
> I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;).

Did you try Ron's suggestion of reading and writing the memory instead
of clearing it?  I'd prefer a solution without an #if.

If that's not feasible I think the comment is too weak.  Note: This
breaks ECC boards.

Thanks,
Myles

> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
> Acked-by: Rudolf Marek <r.marek at assembler.cz>
>
>
>
> Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
> ===================================================================
> --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c ?2009-05-02 21:30:57 UTC (rev 4251)
> +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c ?2009-05-04 19:26:43 UTC (rev 4252)
> @@ -6,8 +6,13 @@
> ? ? ? ?// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
> ? ? ? ?// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
> ? ? ? ?// so noline clear_init_ram
> +
> +#if HAVE_ACPI_RESUME == 1
> + ? ? ? /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
> + ? ? ? clear_memory( _RAMBASE, ?(CONFIG_LB_MEM_TOPK << 10) - ?_RAMBASE - DCACHE_RAM_SIZE);
> +#else
> ? ? ? ? clear_memory(0, ?((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
> -
> +#endif
> ?}
>
> ?/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From rminnich at gmail.com  Mon May  4 22:06:32 2009
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 May 2009 13:06:32 -0700
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
In-Reply-To: <49ff4182.081abc0a.7086.ffffa584SMTPIN_ADDED@mx.google.com>
References: <49ff4182.081abc0a.7086.ffffa584SMTPIN_ADDED@mx.google.com>
Message-ID: <13426df10905041306i289232d9q8742052e2b9ef2a8@mail.gmail.com>

> +
> +#if HAVE_ACPI_RESUME == 1
> + ? ? ? /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
> + ? ? ? clear_memory( _RAMBASE, ?(CONFIG_LB_MEM_TOPK << 10) - ?_RAMBASE - DCACHE_RAM_SIZE);
> +#else
> ? ? ? ? clear_memory(0, ?((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
> -
> +#endif
> ?}
>

here is a suggestion.

replace all this with:
       /* clear the coreboot memory */
       clear_memory( _RAMBASE,  (CONFIG_LB_MEM_TOPK << 10) -  _RAMBASE
- DCACHE_RAM_SIZE);
       /* We need to sync up ECC tags if this is a power-on or reset */
       /* we should have a clean way to test this but, for now, we'll
just always do it.
        * Note: fixing this in the right way will speed up resume
substantially.
        */
       /* init all non-coreboot memory ECC tags */
       memcpy(non-lb-memory-pointer, non-lb-memory-pointer, non-lb-memory-size);

I will leave it to you to fill in the blanks. Please, no #ifdef around
this very important piece of code. Let's not put in changes that we
*know* will break boards :-)

ron



From rminnich at gmail.com  Mon May  4 22:08:04 2009
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 May 2009 13:08:04 -0700
Subject: [coreboot] [PATCH] Build warnings
In-Reply-To: <2831fecf0905041151n3ff9320bp65795a1988dc8057@mail.gmail.com>
References: <2831fecf0905041151n3ff9320bp65795a1988dc8057@mail.gmail.com>
Message-ID: <13426df10905041308j4d6ca083pab87feee733d2add@mail.gmail.com>

Wonderful.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Mon May  4 22:27:09 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 22:27:09 +0200
Subject: [coreboot] [v2] r4253 - trunk/coreboot-v2/util/newconfig
Message-ID: <mailman.3160.1355071535.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-05-04 22:27:09 +0200 (Mon, 04 May 2009)
New Revision: 4253

Modified:
   trunk/coreboot-v2/util/newconfig/config.g
Log:
This patch removes these warnings:
Makefile:435: warning: overriding commands for target `src/lib/memset.o'

And replaces these debug messages:
partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8>
part pci_domain
with:
partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-05-04 19:26:43 UTC (rev 4252)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-05-04 20:27:09 UTC (rev 4253)
@@ -323,6 +323,22 @@
 			return
 		fatal("No such rule \"%s\" for addmakedepend" % id)
 
+	def addmakeobject(self, file, obj):
+		source = topify(obj[1])
+		type = obj[2]
+		if (type  == 'S'):
+			# for .S, .o depends on .s
+			file.write("%s: %s.s\n" % (obj[0], obj[3]))
+        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
+			# and .s depends on .S
+			file.write("%s.s: %s\n" % (obj[3], source))
+			# Note: next 2 lines are ONE output line!
+        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
+			file.write(">$@.new && mv $@.new $@\n")
+		else:
+			file.write("%s: %s\n" % (obj[0], source))
+			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+
 	# this is called with an an object name. 
 	# the easiest thing to do is add this object to the current 
 	# component.
@@ -608,8 +624,12 @@
 class partobj:
 	"""A configuration part"""
 	def __init__ (self, image, dir, parent, part, type_name, instance_name, chip_or_device):
-		debug.info(debug.object, "partobj dir %s parent %s part %s" \
-				% (dir, parent, part))
+		if (parent):
+			debug.info(debug.object, "partobj dir %s parent %s part %s" \
+				% (dir, parent.instance_name, part))
+		else:
+			debug.info(debug.object, "partobj dir %s part %s" \
+				% (dir, part))
 
 		# romimage that is configuring this part
 		self.image = image
@@ -2166,38 +2186,15 @@
 
 	file.write("\n# initobjectrules:\n")
 	for irule, init in image.getinitobjectrules().items():
-		source = topify(init[1])
-		type = init[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (init[0], init[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (init[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
-		else:
-			file.write("%s: %s\n" % (init[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+		image.addmakeobject(file, init);
 
-	file.write("\n# objectrules:\n")
+	file.write("\n# objectrules (don't duplicate initobjects):\n")
 	for objrule, obj in image.getobjectrules().items():
-		source = topify(obj[1])
-		type = obj[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (obj[0], obj[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (obj[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
+
+		if (getdict(image.getinitobjectrules(), obj[3])):
+			debug.info(debug.object, "skipping %s" % (obj[3]))
 		else:
-			file.write("%s: %s\n" % (obj[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
-		#file.write("%s\n" % objrule[2])
+			image.addmakeobject(file, obj);
 
 	for driverrule, driver in image.getdriverrules().items():
 		source = topify(driver[1])
@@ -2207,20 +2204,7 @@
 
 	file.write("\n# smmobjectrules:\n")
 	for irule, smm in image.getsmmobjectrules().items():
-		source = topify(smm[1])
-		type = smm[2]
-		if (type  == 'S'):
-			# for .S, .o depends on .s
-			file.write("%s: %s.s\n" % (smm[0], smm[3]))
-        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
-			# and .s depends on .S
-			file.write("%s.s: %s\n" % (smm[3], source))
-			# Note: next 2 lines are ONE output line!
-        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
-			file.write(">$@.new && mv $@.new $@\n")
-		else:
-			file.write("%s: %s\n" % (smm[0], source))
-			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+		image.addmakeobject(file, smm);
 
 	# special rule for chip_target.c
 	file.write("static.o: static.c\n")




From mylesgw at gmail.com  Mon May  4 22:27:40 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 14:27:40 -0600
Subject: [coreboot] [PATCH] Build warnings
In-Reply-To: <13426df10905041308j4d6ca083pab87feee733d2add@mail.gmail.com>
References: <2831fecf0905041151n3ff9320bp65795a1988dc8057@mail.gmail.com>
	<13426df10905041308j4d6ca083pab87feee733d2add@mail.gmail.com>
Message-ID: <2831fecf0905041327y89abbb0n7a16548857854276@mail.gmail.com>

On Mon, May 4, 2009 at 2:08 PM, ron minnich <rminnich at gmail.com> wrote:
> Wonderful.

Thanks.

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Rev 4253.

Myles



From mylesgw at gmail.com  Mon May  4 22:45:36 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 14:45:36 -0600
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <49FD4AFC.2080702@georgi-clan.de>
References: <20090501211503.GA18155@localdomain>
	<13426df10905021342k32a0382eo2e30b49ef48b0f27@mail.gmail.com>
	<20090502215815.GA1931@localdomain>
	<13426df10905021638oe5e6bf4vec06e7d994b24119@mail.gmail.com>
	<20090503004046.GA10185@localdomain> <49FD4AFC.2080702@georgi-clan.de>
Message-ID: <2831fecf0905041345nadb1f26s41050d56758865cb@mail.gmail.com>

On Sun, May 3, 2009 at 1:42 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 03.05.2009 02:40, schrieb Ward Vandewege:
>>
>> On Sat, May 02, 2009 at 04:38:12PM -0700, ron minnich wrote:
>>>
>>> On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege<ward at gnu.org> ?wrote:
>>>>
>>>> On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
>>>>>
>>>>> It does look like an SMP machine in which both CPUs are trying to run
>>>>> as the BSP.
>>>>>
>>>>> Possible?
>>>>
>>>> It's definitely an SMP machine, two dual-core CPUs.
>>>
>>> So can you see what changed in the k8 north/cpu support since the last
>>> time it worked?
>>
>> Sure. The last time it worked is r4232, I had to bisect to find the commit
>> causing the problem. r4233/4234 are one changeset.
>>
>> src/northbridge/amd is unchanged by this changeset.
>>
>> The diff for src/cpu/amd is attached.
>
> The various copies of "copy_and_run" were merged into
> src/arch/i386/lib/copy_and_run.c.
> I tweaked the coreboot_apc generation a bit, by adding the serial driver and
> console output code. It worked on a fam10 board here, so I didn't think it
> to cause much trouble - seems like it does.
>
> The interleaved messages are
>
> (by the BSP)
> malloc Enter, size 1100, free_mem_ptr 00148000
> malloc 00148000
> CPU APIC: 01
>
> (by the AP)
> image length = 00002a6c
> Jumping to image.
>
> That's definitely a different image used for the AP than the one for the BSP
> (see image length some lines earlier)

It didn't break my s2895 (dual dual-core K8)

I wonder what the difference is.

Thanks,
Myles



From russ at ashlandhome.net  Mon May  4 22:47:47 2009
From: russ at ashlandhome.net (Russell Whitaker)
Date: Mon, 4 May 2009 13:47:47 -0700 (PDT)
Subject: [coreboot] [ANNOUNCE] flashrom 0.9.0 has been released!
In-Reply-To: <49FEFEA4.9090604@gmx.net>
References: <49FEFEA4.9090604@gmx.net>
Message-ID: <alpine.LNX.2.00.0905041342010.2651@bigred.russwhit.org>



On Mon, 4 May 2009, Carl-Daniel Hailfinger wrote:

> The flashrom developers are happy to announce the release of flashrom 0.9.0.
>
Downloaded http://qa.coreboot.org/releases/flashrom-0.9.0.tar.bz2
compiles with gcc-4.4.0
installs, runs.

Good Job!

   Russ



From r.marek at assembler.cz  Mon May  4 22:41:27 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 04 May 2009 22:41:27 +0200
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
In-Reply-To: <13426df10905041306i289232d9q8742052e2b9ef2a8@mail.gmail.com>
References: <49ff4182.081abc0a.7086.ffffa584SMTPIN_ADDED@mx.google.com>
	<13426df10905041306i289232d9q8742052e2b9ef2a8@mail.gmail.com>
Message-ID: <49FF52F7.2030707@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

> I will leave it to you to fill in the blanks. Please, no #ifdef around
> this very important piece of code. Let's not put in changes that we
> *know* will break boards :-)

Hmm I dont have an ECC board. So maybe Myles could test. Second reason is that I
prefer to have here the ifdef because the RESUME stuff is quite unmature but
works at least somehow. I'm willing to test the changes when we know it works on
ECC boards,

Thanks for help,
Rudolf


-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkn/UvcACgkQ3J9wPJqZRNXgqgCgi1xDFm9vt5Ll2X9sgvLEJShJ
N5MAoNL9XXQ1DCvzdzreFiSIpDbKVseb
=hS4E
-----END PGP SIGNATURE-----



From mylesgw at gmail.com  Mon May  4 22:59:01 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 14:59:01 -0600
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
In-Reply-To: <49FF52F7.2030707@assembler.cz>
References: <49ff4182.081abc0a.7086.ffffa584SMTPIN_ADDED@mx.google.com>
	<13426df10905041306i289232d9q8742052e2b9ef2a8@mail.gmail.com>
	<49FF52F7.2030707@assembler.cz>
Message-ID: <2831fecf0905041359w65ab1e4p1324098f3160d2b4@mail.gmail.com>

On Mon, May 4, 2009 at 2:41 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>> I will leave it to you to fill in the blanks. Please, no #ifdef around
>> this very important piece of code. Let's not put in changes that we
>> *know* will break boards :-)
>
> Hmm I dont have an ECC board. So maybe Myles could test.
It didn't break my board.  Samuel and Ward had boards that broke.

Thanks,
Myles



From rminnich at gmail.com  Mon May  4 23:03:36 2009
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 May 2009 14:03:36 -0700
Subject: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
In-Reply-To: <49FF52F7.2030707@assembler.cz>
References: <49ff4182.081abc0a.7086.ffffa584SMTPIN_ADDED@mx.google.com>
	<13426df10905041306i289232d9q8742052e2b9ef2a8@mail.gmail.com>
	<49FF52F7.2030707@assembler.cz>
Message-ID: <13426df10905041403p433270cbx9195626eb8541e91@mail.gmail.com>

On Mon, May 4, 2009 at 1:41 PM, Rudolf Marek <r.marek at assembler.cz> wrote:

> Hmm I dont have an ECC board. So maybe Myles could test. Second reason is that I
> prefer to have here the ifdef because the RESUME stuff is quite unmature but
> works at least somehow. I'm willing to test the changes when we know it works on
> ECC boards,

I am pretty sure that code i just posted will work for any board.
Although I am being optimistic calling it "code", I realize :-)

But, can you try it? It really ought to Do No Harm, and will allow us
all to proceed without worrying about this again. We all want your
RESUME stuff, so we might as well just try to get this done in a way
that works for the long term.

ron



From svn at coreboot.org  Mon May  4 23:03:59 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  4 May 2009 23:03:59 +0200
Subject: [coreboot] [flashrom] r458 - trunk
Message-ID: <mailman.3161.1355071535.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-04 23:03:59 +0200 (Mon, 04 May 2009)
New Revision: 458

Modified:
   trunk/flashchips.c
Log:
SST25VF080B TEST_OK_READ

Per report from from Henning Fleddermann. Thanks!

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/flashchips.c
===================================================================
--- trunk/flashchips.c	2009-05-04 12:29:59 UTC (rev 457)
+++ trunk/flashchips.c	2009-05-04 21:03:59 UTC (rev 458)
@@ -1204,7 +1204,7 @@
 		.model_id	= SST_25VF080B,
 		.total_size	= 1024,
 		.page_size	= 256,
-		.tested		= TEST_OK_PROBE,
+		.tested		= TEST_OK_PR,
 		.probe		= probe_spi_rdid,
 		.erase		= spi_chip_erase_60_c7,
 		.write		= spi_chip_write,




From svn at coreboot.org  Tue May  5 00:33:50 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 May 2009 00:33:50 +0200
Subject: [coreboot] [flashrom] r459 - trunk
Message-ID: <mailman.3162.1355071535.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-05 00:33:50 +0200 (Tue, 05 May 2009)
New Revision: 459

Modified:
   trunk/chipset_enable.c
Log:
Force enabling SPI mode for SB600 is a bad idea and leads to hangs.

Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we
boot via SPI ROM.
The code to force enable SPI is commented out in case someone wants to
reenable it for a particular board with LPC and SPI flash.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-04 21:03:59 UTC (rev 458)
+++ trunk/chipset_enable.c	2009-05-04 22:33:50 UTC (rev 459)
@@ -680,8 +680,16 @@
 	flashbus = BUS_TYPE_SB600_SPI;
 
 	/* Enable SPI ROM in SB600 PM register. */
+	/* If we enable SPI ROM here, we have to disable it after we leave.
+	 * But how can we know which ROM we are going to handle? So we have
+	 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
+	 * only SPI ROM if we boot via SPI ROM. If you want to do it crossly,
+	 * you have to use the code below.
+	 */
+	/*
 	OUTB(0x8f, 0xcd6);
 	OUTB(0x0e, 0xcd7);
+	*/
 
 	return 0;
 }




From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 00:40:14 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 00:40:14 +0200
Subject: [coreboot] [patch] flashrom: resending my patch about SPI/LPC
 conflicts
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17025AD41E@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17025AD41E@sbjgexmb1.amd.com>
Message-ID: <49FF6ECE.3040706@gmx.net>

On 02.02.2009 05:12, Bao, Zheng wrote:
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
> This patch is about flashrom running on dbm690t. It was sent several
> months ago and hasn't got any response yet. Now it deals with 3
> problems.
> 1. Fix the bug that the flashrom would hang if there is not SPI chip. A
> timeout detection was added.
> 2. We only access LPC ROM if we boot via LPC ROM. And only SPI ROM if we
> boot via SPI ROM. Doing crossly is not allowed. Anybody has better idea?
> 3. When we read/write SPI, we use memory read/write instead of sending
> SPI command.
>   

I acked and committed part 2 in r459.
Sorry for the delay.

The other parts need to be committed separately because they fix
separate issues.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Tue May  5 05:04:01 2009
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 May 2009 20:04:01 -0700
Subject: [coreboot] cbfs XIP patch
Message-ID: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>

Attached. This patch lets us create XIP stages for cbfs.

ron
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From mylesgw at gmail.com  Tue May  5 05:55:11 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 4 May 2009 21:55:11 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
Message-ID: <62A75D47A41940C0BE145BCFD1C070C6@chimp>


> Attached. This patch lets us create XIP stages for cbfs.

I'd like to see the picture of what you're imagining here.  I thought CBFS
was designed to grow in only one direction.  Are you going to have to add
components in a certain order to make this work?  I don't see where you're
padding or inserting blank areas.

Thanks,
Myles




From marcj303 at gmail.com  Tue May  5 06:03:52 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 4 May 2009 22:03:52 -0600
Subject: [coreboot] [v2][patch] use updated microcode patches from AMD
In-Reply-To: <534e5dc20904080955l646ca040wc6a2bdfcf1463f58@mail.gmail.com>
References: <534e5dc20904011520g278c104cld8e55a57d7cd873b@mail.gmail.com>
	<534e5dc20904080955l646ca040wc6a2bdfcf1463f58@mail.gmail.com>
Message-ID: <534e5dc20905042103q2eb1a103y4a54717e802930e4@mail.gmail.com>

I no longer have a setup for Fam10 so someone will need to test this
patch. This doesn't include new errata for C2 (which really needs to
be addressed).

Update equivalent processor revision ID to load latest microcode
patches and register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.

Signed-off-by: Marc Jones <marcj303 at gmail.com>

-- 
http://marcjonesconsulting.com
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From marcj303 at gmail.com  Tue May  5 06:08:53 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 4 May 2009 22:08:53 -0600
Subject: [coreboot] slides/presentation
In-Reply-To: <49FF38AA.7080008@assembler.cz>
References: <49FF38AA.7080008@assembler.cz>
Message-ID: <534e5dc20905042108t41f704a6yc0e16889dffcbf88@mail.gmail.com>

On Mon, May 4, 2009 at 12:49 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Hello all,
>
> I decided to speak a bit about coreboot in a student (university) UNIX/Linux
> club. Are there any slides so I can "pirate" them and maybe improve them a bit?
>
> Thanks,
> Rudolf

These are slides I wrote for a talk I gave at the FSF members meeting.
They might be helpful.
http://marcjonesconsulting.com/FSF%20talk.pdf

-- 
http://marcjonesconsulting.com



From vincent.lim at amd.com  Tue May  5 06:12:38 2009
From: vincent.lim at amd.com (Lim, Vincent)
Date: Mon, 4 May 2009 23:12:38 -0500
Subject: [coreboot] [v2][patch] use updated microcode patches from AMD
In-Reply-To: <534e5dc20905042103q2eb1a103y4a54717e802930e4@mail.gmail.com>
References: <534e5dc20904011520g278c104cld8e55a57d7cd873b@mail.gmail.com>
	<534e5dc20904080955l646ca040wc6a2bdfcf1463f58@mail.gmail.com>
	<534e5dc20905042103q2eb1a103y4a54717e802930e4@mail.gmail.com>
Message-ID: <8ACC5F4627569841AF9B0331E5EDBF960160FB3D@sausexmb5.amd.com>

I will test this configuration via SimNow, further improve if issues
arise.

Acked-by: Vincent Lim (vincent.lim at amd.com)


Best Regards,

Vincent Lim
SimNow Team
Performance CoE
Central Engineering
T 512.602.1618
F 512.602.7745



-----Original Message-----
From: Marc Jones [mailto:marcj303 at gmail.com] 
Sent: Monday, May 04, 2009 11:04 PM
To: Coreboot
Cc: Lim, Vincent
Subject: Re: [v2][patch] use updated microcode patches from AMD

I no longer have a setup for Fam10 so someone will need to test this
patch. This doesn't include new errata for C2 (which really needs to be
addressed).

Update equivalent processor revision ID to load latest microcode patches
and register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.

Signed-off-by: Marc Jones <marcj303 at gmail.com>

--
http://marcjonesconsulting.com




From rminnich at gmail.com  Tue May  5 06:55:31 2009
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 May 2009 21:55:31 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <62A75D47A41940C0BE145BCFD1C070C6@chimp>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
Message-ID: <13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>

On Mon, May 4, 2009 at 8:55 PM, Myles Watson <mylesgw at gmail.com> wrote:
>
>> Attached. This patch lets us create XIP stages for cbfs.
>
> I'd like to see the picture of what you're imagining here. ?I thought CBFS
> was designed to grow in only one direction. ?Are you going to have to add
> components in a certain order to make this work? ?I don't see where you're
> padding or inserting blank areas.

no, cbfs files can be sparse. There is nothing in the design that
requires that all entries be contiguous. In fact, given that remove
exists,
cbfs has to allow holes.

The padding is implicit in the way the fs code works. The code
allocates a ROM image that is the size of the actual ROM, and
initializes that ROM image with empty values. To add a file, it simply
installs a cbfs file header at a location that is aligned with
rom->header->align. The header has a type and a length.

All that this XIP code patch does is allow cbfs to install a cbfs file
in the archive at an offset such that XIP will work for that file.
That's it. It's a very simple addition.

There is actually no change to the find code in src/lib, in fact; that
code also walks all of rom, in strides of 'align'. If we ever worry
that 16 bytes is too small an increment we can change it
at the command line, when we create a cbfs archive.

And, no, you don't have to add components in any particular order. The
only requirement, in fact, is that XIP components have room to fit.
That's about it.

ron



From patrick at georgi-clan.de  Tue May  5 09:42:41 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 09:42:41 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
Message-ID: <49FFEDF1.4090605@georgi-clan.de>

Am 05.05.2009 06:55, schrieb ron minnich:
> There is actually no change to the find code in src/lib, in fact; that
> code also walks all of rom, in strides of 'align'. If we ever worry
> that 16 bytes is too small an increment we can change it
> at the command line, when we create a cbfs archive.
In that case, I'll have to revert a change made to lib/cbfs.c to walk 
the chain of files (instead of a brute force walk through the whole 
image). SeaBIOS will have to do likewise.

And that means, that we either need some cache about file locations in 
the readers, or certain operations will be very expensive (eg. SeaBIOS 
looking for all kind of pci*roms)


Patrick



From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 09:48:22 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 09:48:22 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <49FFEDF1.4090605@georgi-clan.de>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de>
Message-ID: <49FFEF46.6010504@gmx.net>

On 05.05.2009 09:42, Patrick Georgi wrote:
> Am 05.05.2009 06:55, schrieb ron minnich:
>> There is actually no change to the find code in src/lib, in fact; that
>> code also walks all of rom, in strides of 'align'. If we ever worry
>> that 16 bytes is too small an increment we can change it
>> at the command line, when we create a cbfs archive.
> In that case, I'll have to revert a change made to lib/cbfs.c to walk
> the chain of files (instead of a brute force walk through the whole
> image). SeaBIOS will have to do likewise.
>
> And that means, that we either need some cache about file locations in
> the readers, or certain operations will be very expensive (eg. SeaBIOS
> looking for all kind of pci*roms)

Doesn't zerofill solve that problem?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 09:58:31 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 09:58:31 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
Message-ID: <49FFF1A7.7040708@gmx.net>

On 05.05.2009 06:55, ron minnich wrote:
> There is actually no change to the find code in src/lib, in fact; that
> code also walks all of rom, in strides of 'align'.

Didn't we decide in v3 that walking all of ROM was a bad idea after that
method (instead of skipping ahead based on headers) triggered too many
false positives? Remember funny constructs like

/* I hope the compiler does not optimize this */
char *magic = "L" + "ARCHIVE"

What did I miss?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Tue May  5 09:59:55 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 09:59:55 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <49FFEF46.6010504@gmx.net>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
Message-ID: <49FFF1FB.6090900@georgi-clan.de>

Am 05.05.2009 09:48, schrieb Carl-Daniel Hailfinger:
> On 05.05.2009 09:42, Patrick Georgi wrote:
>> Am 05.05.2009 06:55, schrieb ron minnich:
>>> There is actually no change to the find code in src/lib, in fact; that
>>> code also walks all of rom, in strides of 'align'. If we ever worry
>>> that 16 bytes is too small an increment we can change it
>>> at the command line, when we create a cbfs archive.
>> In that case, I'll have to revert a change made to lib/cbfs.c to walk
>> the chain of files (instead of a brute force walk through the whole
>> image). SeaBIOS will have to do likewise.
>>
>> And that means, that we either need some cache about file locations in
>> the readers, or certain operations will be very expensive (eg. SeaBIOS
>> looking for all kind of pci*roms)
>
> Doesn't zerofill solve that problem?
No, esp. with XIP images, we have no idea where images start and end. We 
have to look through the entire image for that.

I have some code for a "next" field that builds a chain without relying 
on "offset" and "len" (as the current chain walker do). That helps with 
a scenario like having two option roms right after another at the 
beginning of the ROM.
The current walker would be confused by that. (it always looks for the 
next file header after the current file's data)

The "next" field has the disadvantage that we can't simply hot-update 
anymore, as we'd have to change data (instead of merely adding it).

And solutions like "use the 'unwritten bytes' marker (eg. 0xffffffff) as 
end-of-chain identifier", so it can be overwritten feel quite unclean, too.


Patrick



From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 10:04:14 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 10:04:14 +0200
Subject: [coreboot] [PATCH] flashrom: Rewrite SB600 chipset enable function
Message-ID: <49FFF2FE.6080302@gmx.net>

Rewrite the SB600 chipset enable function:
- Check for read/write protected regions first.
- Region protection is write-once according to the data sheets. Check if
the write succeeded.
- Verbose region protection dumping.
- Improve readability of BAR mapping code.
- Align BAR mapping to a page boundary (4k) instead of a 16k boundary.

This patch prepares the code for a SPI detection heuristic.

Tests are appreciated.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-sb600/chipset_enable.c
===================================================================
--- flashrom-sb600/chipset_enable.c	(Revision 459)
+++ flashrom-sb600/chipset_enable.c	(Arbeitskopie)
@@ -658,33 +658,47 @@
 
 static int enable_flash_sb600(struct pci_dev *dev, const char *name)
 {
-	uint32_t tmp, low_bits, num;
+	uint32_t tmp, prot;
 	uint8_t reg;
 
-	low_bits = tmp = pci_read_long(dev, 0xa0);
-	low_bits &= ~0xffffc000; /* for mmap aligning requirements */
-	low_bits &= 0xfffffff0;	/* remove low 4 bits */
-	tmp &= 0xffffc000;
-	printf_debug("SPI base address is at 0x%x\n", tmp + low_bits);
-
-	sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000);
-	sb600_spibar += low_bits;
-
 	/* Clear ROM protect 0-3. */
 	for (reg = 0x50; reg < 0x60; reg += 4) {
-		num = pci_read_long(dev, reg);
-		num &= 0xfffffffc;
-		pci_write_byte(dev, reg, num);
+		prot = pci_read_long(dev, reg);
+		if (prot & 0x3)
+			printf("SB600 %s %s protected from %u to %u\n",
+				(prot & 0x1) ? "write" : "",
+				(prot & 0x2) ? "read" : "",
+				(prot & 0xfffffc00),
+				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
+		prot &= 0xfffffffc;
+		pci_write_byte(dev, reg, prot);
+		prot = pci_read_long(dev, reg);
+		if (prot & 0x3)
+			printf("SB600 still %s %s protected from %u to %u\n",
+				(prot & 0x1) ? "write" : "",
+				(prot & 0x2) ? "read" : "",
+				(prot & 0xfffffc00),
+				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
 	}
 
+	/* Read SPI_BaseAddr */
+	tmp = pci_read_long(dev, 0xa0);
+	tmp &= 0xfffffff0;	/* remove low 4 bits (reserved) */
+	printf_debug("SPI base address is at 0x%x\n", tmp);
+
+	/* Physical memory can only be mapped at page (4k) boundaries */
+	sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
+	/* The low bits of the SPI base address are used as offset into the mapped page */
+	sb600_spibar += tmp & 0xfff;
+
 	flashbus = BUS_TYPE_SB600_SPI;
 
-	/* Enable SPI ROM in SB600 PM register. */
-	/* If we enable SPI ROM here, we have to disable it after we leave.
+	/* Force enable SPI ROM in SB600 PM register.
+	 * If we enable SPI ROM here, we have to disable it after we leave.
 	 * But how can we know which ROM we are going to handle? So we have
 	 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
-	 * only SPI ROM if we boot via SPI ROM. If you want to do it crossly,
-	 * you have to use the code below.
+	 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
+	 * boards with LPC straps, you have to use the code below.
 	 */
 	/*
 	OUTB(0x8f, 0xcd6);


-- 
http://www.hailfinger.org/

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From joe at settoplinux.org  Tue May  5 12:13:41 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 05 May 2009 06:13:41 -0400
Subject: [coreboot] unexpected exception errors loading vga rom
In-Reply-To: <8ade8a17616cccd9908a26d6af14871e@imap.1and1.com>
References: <833def118eec581027d3ad14707ae547@imap.1and1.com>	<c7f6ec3b5899a4a3870ed3a47c9d02d4@imap.1and1.com>	<13426df10904221350u666ffeefl49cd45e819c6b55a@mail.gmail.com>	<a87182603ff274641abf1321407bc3f7@imap.1and1.com>	<2bbfb008bb973f2dbbce6f9c4f8c940e@imap.1and1.com>	<93f8dd29215f15ba4cb54848521b73f7@imap.1and1.com>	<13426df10904240815s649f2d8dj46e03f69e965babf@mail.gmail.com>	<810c1a3ab18b8a09e3497c3cd1f18e3e@imap.1and1.com>	<13426df10904241059u2f1df8deq12a9b744d035e05b@mail.gmail.com>	<8428a5f1747d8d48229ef2fafe45ea78@imap.1and1.com>	<13426df10904241208g2a0a955ay1ef439b233be828c@mail.gmail.com>	<0c666fa19b0a7ec3ff21d5d68215e722@imap.1and1.com>	<49F8B6E8.2010206@assembler.cz>
	<7ec5632b3062bbf456417105c705155e@imap.1and1.com>
	<49F8CCC2.4080509@assembler.cz>
	<8ade8a17616cccd9908a26d6af14871e@imap.1and1.com>
Message-ID: <5a129782045cc607bb13d21e7ae4eed4@imap.1and1.com>




On Wed, 29 Apr 2009 18:04:02 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> 
> 
> On Wed, 29 Apr 2009 23:55:14 +0200, Rudolf Marek <r.marek at assembler.cz>
> wrote:
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>> but you have been speaking that it gets IRQ0 right?
>>
>>
>> Do you mean it is that one from the PCI space bios IRQ?
>>
> Every PCI device gets an IRQ 0. 

Note to self: If every PCI device gets an IRQ 0 it means your irq table is
not readable by the OS because the check sum is invalid.


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mylesgw at gmail.com  Tue May  5 14:29:56 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 06:29:56 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
Message-ID: <1A08A3CEC154439FBB1F59D021D6B942@chimp>



> -----Original Message-----
> From: ron minnich [mailto:rminnich at gmail.com]
> On Mon, May 4, 2009 at 8:55 PM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >> Attached. This patch lets us create XIP stages for cbfs.
> >
> > I'd like to see the picture of what you're imagining here. ?I thought
> CBFS
> > was designed to grow in only one direction. ?Are you going to have to
> add
> > components in a certain order to make this work? ?I don't see where
> you're
> > padding or inserting blank areas.
> 
> no, cbfs files can be sparse. There is nothing in the design that
> requires that all entries be contiguous. In fact, given that remove
> exists,
> cbfs has to allow holes.

Someone needs to fix remove then.  Right now it moves all entries after it
and zeroes the new space.  I guess most of my confusion came from the
implementation/design gap.

Thanks,
Myles




From patrick at georgi-clan.de  Tue May  5 15:05:58 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 15:05:58 +0200
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <20090501211503.GA18155@localdomain>
References: <20090501211503.GA18155@localdomain>
Message-ID: <4A0039B6.6060406@georgi-clan.de>

Am 01.05.2009 23:15, schrieb Ward Vandewege:
> It seems r4233/4234 broke the tree for h8dme (k8). Here's how my boot hangs,
> note the corruption in the serial log:
The "corruption" is fine - it's just both cores chatting at the same time.

I made a small mistake in the refactoring of copy_and_run that affected 
only the coreboot_apc codepath (which I can't test).
While the copy_and_run_core function takes a "dst" argument, and 
compresses to that location, it jumped to a hardcoded entry point of 
_iseg - which works for all scenarios but coreboot_apc.

With the change, the dst value is used for all cases.

Please try attached patch which should fix it. It's tested to run in the 
non-APC codepath and is

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From ward at gnu.org  Tue May  5 16:02:35 2009
From: ward at gnu.org (Ward Vandewege)
Date: Tue, 5 May 2009 10:02:35 -0400
Subject: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
In-Reply-To: <4A0039B6.6060406@georgi-clan.de>
References: <20090501211503.GA18155@localdomain>
	<4A0039B6.6060406@georgi-clan.de>
Message-ID: <20090505140235.GA774@localdomain>

Hi Patrick,

On Tue, May 05, 2009 at 03:05:58PM +0200, Patrick Georgi wrote:
> Am 01.05.2009 23:15, schrieb Ward Vandewege:
>> It seems r4233/4234 broke the tree for h8dme (k8). Here's how my boot hangs,
>> note the corruption in the serial log:
> The "corruption" is fine - it's just both cores chatting at the same time.
>
> I made a small mistake in the refactoring of copy_and_run that affected  
> only the coreboot_apc codepath (which I can't test).
> While the copy_and_run_core function takes a "dst" argument, and  
> compresses to that location, it jumped to a hardcoded entry point of  
> _iseg - which works for all scenarios but coreboot_apc.
>
> With the change, the dst value is used for all cases.
>
> Please try attached patch which should fix it. It's tested to run in the  
> non-APC codepath and is

Thanks, tested on h8dme and this fixes the problem.

> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Ward Vandewege <ward at gnu.org>

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Tue May  5 16:06:20 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 May 2009 16:06:20 +0200
Subject: [coreboot] [v2] r4254 - trunk/coreboot-v2/src/arch/i386/lib
Message-ID: <mailman.3163.1355071536.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-05-05 16:06:20 +0200 (Tue, 05 May 2009)
New Revision: 4254

Modified:
   trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c
Log:
Fix a bug introduced in the copy_and_run refactoring.
The new code always decompressed to dst (as it should)
and then jumped to _iseg, when it should jump to dst.

With dst != _iseg this breaks (coreboot_apc)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>


Modified: trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c	2009-05-04 20:27:09 UTC (rev 4253)
+++ trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c	2009-05-05 14:06:20 UTC (rev 4254)
@@ -44,11 +44,10 @@
 	print_debug("Jumping to image.\r\n");
 
 	__asm__ volatile (
-		"movl %0, %%ebp\n\t"
+		"movl %%eax, %%ebp\n\t"
 		"cli\n\t"
-		"leal    _iseg, %%edi\n\t"
 		"jmp     *%%edi\n\t"
-		:: "a"(ebp)
+		:: "a"(ebp), "D"(dst)
 	);
 
 }




From rminnich at gmail.com  Tue May  5 17:06:41 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:06:41 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <1A08A3CEC154439FBB1F59D021D6B942@chimp>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
Message-ID: <13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>

On Tue, May 5, 2009 at 5:29 AM, Myles Watson <mylesgw at gmail.com> wrote:

> Someone needs to fix remove then. ?Right now it moves all entries after it
> and zeroes the new space. ?I guess most of my confusion came from the
> implementation/design gap.

I think it was my confusion, not yours :-)

But I think we have to have clean support for XIP in ROM, which means
we have to have a way for cbfs to place a block of code in a
designated place.
I like the idea of having the ROM stages visible in cbfs.

If we are certain we don't need XIP then we don't need this patch. But
if we have XIP we can
remove some fairly confusing __asm__ code in failover, as well as the
attendant load scripts.  Also, since the
stage header has the entry point as well, we get rid of the need to
have a reset vector at the end of the normal
and failover ROM images -- a much cleaner way to go.

Some suggestions:
- adopt a coarser granularity. Were we to adopt, e.g., 512B as a block
size, then at most the walking code would have to check  4096 items
on even a 2 Mbyte ROM (as opposed to the current 128K items)
- zero fill
- NEXT pointer

All of these will work.

ron



From rminnich at gmail.com  Tue May  5 17:09:19 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:09:19 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <49FFF1A7.7040708@gmx.net>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFF1A7.7040708@gmx.net>
Message-ID: <13426df10905050809l73c5f1e7l5bcba5a8baec5a30@mail.gmail.com>

On Tue, May 5, 2009 at 12:58 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 05.05.2009 06:55, ron minnich wrote:
>> There is actually no change to the find code in src/lib, in fact; that
>> code also walks all of rom, in strides of 'align'.
>
> Didn't we decide in v3 that walking all of ROM was a bad idea after that
> method (instead of skipping ahead based on headers) triggered too many
> false positives? Remember funny constructs like
>
> /* I hope the compiler does not optimize this */
> char *magic = "L" + "ARCHIVE"
>
> What did I miss?

You didn't miss anything. It's a bug in the current cbfs walking code
that I noticed last night.

Fix is simple: use Patrick's 'next' pointer or, when the code sees a
valid file, it should skip to the end of that file and keep looking --
at which point it is likely to find another file or a non-magic value.

After this discussion I am thinking his next pointer is a good idea.
ron



From rminnich at gmail.com  Tue May  5 17:12:37 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:12:37 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <49FFF1FB.6090900@georgi-clan.de>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
Message-ID: <13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>

On Tue, May 5, 2009 at 12:59 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:

> I have some code for a "next" field that builds a chain without relying on
> "offset" and "len" (as the current chain walker do). That helps with a
> scenario like having two option roms right after another at the beginning of
> the ROM.
> The current walker would be confused by that. (it always looks for the next
> file header after the current file's data)

I am missing the point. Are they two cbfs files or ... if they are two
cbfs files, then there is no problem.
The case that the option ROMs are not part of cbfs? Or there are two option
ROMs in one CBFS file?

it's too early in the morning for me :-)

ron



From mylesgw at gmail.com  Tue May  5 17:13:32 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:13:32 -0600
Subject: [coreboot] CBFS transition plan
Message-ID: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>

I like CBFS and hope all boards can use it soon.  I'm afraid that if
we're not careful we'll bring the instability of v3 to v2 as we try to
bring back what we've learned.

I'd like to see an orderly transition to CBFS, from simplest to most
complex.  I think fixed areas, romstraps, etc. should be last.

Simple things that don't work yet in CBFS:
1. Normal/Fallback/Failover -
    a. There are comments in the code that failover should disappear.
Either failover should disappear or the comments should.
    b. Normal should be stored in CBFS, not concatenated into the bootblock.
2. Delete - Delete works on the assumption that you want contiguous files
    a. I'm not convinced that fixed CBFS areas will be simpler than
ldscripts.  I consider them both ugly.
3. PCI ROM optimization.  There should be some optimization for ROMs.
    a. Possibilities:
        1. Traverse ROM once and set a flag in devices which have ROMs
        2. Traverse ROM and keep a list of ROMs
        3. ....
4. Geode ROM handling in CBFS.
    a. It would be nice to change the code so that it doesn't have to
be in a fixed location (maybe via a copy to RAM?)

I guess the short version is that I'd like to keep all the ugly
details in the bootblock and peel them out one at a time.  I think
we'll break fewer boards that way.  I feel like we've been lucky to
catch some of the little glitches lately, and we've had help from
people being willing to bisect.

Thanks,
Myles



From mylesgw at gmail.com  Tue May  5 17:20:36 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:20:36 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
Message-ID: <2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>

On Tue, May 5, 2009 at 9:06 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 5:29 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>> Someone needs to fix remove then. ?Right now it moves all entries after it
>> and zeroes the new space. ?I guess most of my confusion came from the
>> implementation/design gap.
>
> I think it was my confusion, not yours :-)
>
> But I think we have to have clean support for XIP in ROM, which means
> we have to have a way for cbfs to place a block of code in a
> designated place.
So can we force the compiler to make everything inside a block
relative so that it can be position-independent?

> I like the idea of having the ROM stages visible in cbfs.
So do I.

> If we are certain we don't need XIP then we don't need this patch. But
> if we have XIP we can
> remove some fairly confusing __asm__ code in failover, as well as the
> attendant load scripts.
Does a normal image need to be XIP?

> Also, since the
> stage header has the entry point as well, we get rid of the need to
> have a reset vector at the end of the normal
> and failover ROM images -- a much cleaner way to go.
Yes.

> Some suggestions:
> - adopt a coarser granularity. Were we to adopt, e.g., 512B as a block
> size, then at most the walking code would have to check ?4096 items
> on even a 2 Mbyte ROM (as opposed to the current 128K items)
> - zero fill
> - NEXT pointer
>
> All of these will work.
I think this is the easy part.  The harder problems have to do with
what we want to allow to be constrained to a specific location.  The
fewer of those the better to me.

Thanks,
Myles



From rminnich at gmail.com  Tue May  5 17:20:50 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:20:50 -0700
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
Message-ID: <13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>

On Tue, May 5, 2009 at 8:13 AM, Myles Watson <mylesgw at gmail.com> wrote:

> ? ?b. Normal should be stored in CBFS, not concatenated into the bootblock.

I would argue that fallback should also be in CBFS. Which is fine, but ...

> 2. Delete - Delete works on the assumption that you want contiguous files
> ? ?a. I'm not convinced that fixed CBFS areas will be simpler than
> ldscripts. ?I consider them both ugly.

How are we going to support code that runs at a fixed address? I can
only come up with
these two options. I think the PIE stuff from v3 is not an option:
we've been warned about
it for a while now, and I now believe the warnings.


> 4. Geode ROM handling in CBFS.
> ? ?a. It would be nice to change the code so that it doesn't have to
> be in a fixed location (maybe via a copy to RAM?)
>
> I guess the short version is that I'd like to keep all the ugly
> details in the bootblock and peel them out one at a time. ?I think
> we'll break fewer boards that way. ?I feel like we've been lucky to
> catch some of the little glitches lately, and we've had help from
> people being willing to bisect.

good points. But, we're at step 1b and we need to make a decision. Our
current decision, by default, is 'use ldscripts to create fallback and
normal images, not cbfs'.
If you look at how the normal symbol is created in the fallback image,
I don't see that fixed-location cbfs files are any uglier ...

ron



From mylesgw at gmail.com  Tue May  5 17:24:26 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:24:26 -0600
Subject: [coreboot] CBFS transition plan
In-Reply-To: <13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
Message-ID: <2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>

On Tue, May 5, 2009 at 9:20 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 8:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
>> ? ?b. Normal should be stored in CBFS, not concatenated into the bootblock.
>
> I would argue that fallback should also be in CBFS. Which is fine, but ...
I agree.  I just think that it can be a future step.

>> 2. Delete - Delete works on the assumption that you want contiguous files
>> ? ?a. I'm not convinced that fixed CBFS areas will be simpler than
>> ldscripts. ?I consider them both ugly.
>
> How are we going to support code that runs at a fixed address? I can
> only come up with
> these two options. I think the PIE stuff from v3 is not an option:
> we've been warned about
> it for a while now, and I now believe the warnings.
I wish I knew the best answer here.

>> 4. Geode ROM handling in CBFS.
>> ? ?a. It would be nice to change the code so that it doesn't have to
>> be in a fixed location (maybe via a copy to RAM?)
>>
>> I guess the short version is that I'd like to keep all the ugly
>> details in the bootblock and peel them out one at a time. ?I think
>> we'll break fewer boards that way. ?I feel like we've been lucky to
>> catch some of the little glitches lately, and we've had help from
>> people being willing to bisect.
>
> good points. But, we're at step 1b and we need to make a decision. Our
> current decision, by default, is 'use ldscripts to create fallback and
> normal images, not cbfs'.
I think we can put off the decision if we insert CBFS code to find the
normal image and jump to it.

> If you look at how the normal symbol is created in the fallback image,
> I don't see that fixed-location cbfs files are any uglier ...
It's ugly.  I hope that adding normal images in CBFS without changing
fallback will help us see the pathway forward.

Myles



From patrick at georgi-clan.de  Tue May  5 17:26:39 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 17:26:39 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>	
	<49FFF1FB.6090900@georgi-clan.de>
	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
Message-ID: <4A005AAF.1090205@georgi-clan.de>

Am 05.05.2009 17:12, schrieb ron minnich:
> On Tue, May 5, 2009 at 12:59 AM, Patrick Georgi<patrick at georgi-clan.de>  wrote:
>
>> I have some code for a "next" field that builds a chain without relying on
>> "offset" and "len" (as the current chain walker do). That helps with a
>> scenario like having two option roms right after another at the beginning of
>> the ROM.
>> The current walker would be confused by that. (it always looks for the next
>> file header after the current file's data)
>
> I am missing the point. Are they two cbfs files or ... if they are two
> cbfs files, then there is no problem.
> The case that the option ROMs are not part of cbfs? Or there are two option
> ROMs in one CBFS file?
Consider the following case: The system has _two_ images it requires at 
fixed addresses right after another. We don't process these images (eg. 
EC firmware) ourselves, but have to take care that they're at the right 
spot (similar to your XIP stuff).
We want to keep the images as two entries in cbfs (as they have 
different release cycles)

The layout would look like this:

file1-data | file2-data

The current algorithm in coreboot and seabios says to walk the chain by 
taking the current cbfs_file address, adding the offset (so you're at 
the beginning of the file in question), and adding the file length (so 
you're at the first byte after the file in question). There, the current 
algorithm expects a new cbfs_file header.

But there's already file2's data in the way. Oops.

With the next field, we decouple the file location and the cbfs_file 
location completely. offset/len point to the file data, next points to 
the next header.


Patrick



From rminnich at gmail.com  Tue May  5 17:28:01 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:28:01 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
Message-ID: <13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>

On Tue, May 5, 2009 at 8:20 AM, Myles Watson <mylesgw at gmail.com> wrote:
> On Tue, May 5, 2009 at 9:06 AM, ron minnich <rminnich at gmail.com> wrote:
>> But I think we have to have clean support for XIP in ROM, which means
>> we have to have a way for cbfs to place a block of code in a
>> designated place.
> So can we force the compiler to make everything inside a block
> relative so that it can be position-independent?

I've tried in v3, but have been warned that the way we get PIE in v3 is really
not legitimate, and not guaranteed to keep working. Some form of PIE
that gnubin experts would accept
would be very good to have.

I don't think we'll ever escape the need for some way to force files
into specific locations. The ROMSTRAP
code from nvidia is not the first example, nor will it be the last.


>> If we are certain we don't need XIP then we don't need this patch. But
>> if we have XIP we can
>> remove some fairly confusing __asm__ code in failover, as well as the
>> attendant load scripts.
> Does a normal image need to be XIP?

It is now and always has been. I don't know how to make it otherwise.

> I think this is the easy part. ?The harder problems have to do with
> what we want to allow to be constrained to a specific location. ?The
> fewer of those the better to me.

I agree. The chipset vendors will always create challenges in this
area, however. And we must still solve our own ROM code issues as
well.

One option is to do the FILO trick and make %cs point to the start of
the ROM code that you are running. This is easy: have a GDT entry for
fallback code and a GDT entry for normal code. Then it suffices to do
load the %cs with the right segment index for fallback or normal.
This approach would remove the need for XIP for our ROM segments.

ron



From rminnich at gmail.com  Tue May  5 17:33:14 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:33:14 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <4A005AAF.1090205@georgi-clan.de>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
	<4A005AAF.1090205@georgi-clan.de>
Message-ID: <13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>

On Tue, May 5, 2009 at 8:26 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:

> Consider the following case: The system has _two_ images it requires at
> fixed addresses right after another. We don't process these images (eg. EC
> firmware) ourselves, but have to take care that they're at the right spot
> (similar to your XIP stuff).
> We want to keep the images as two entries in cbfs (as they have different
> release cycles)
>
> The layout would look like this:
>
> file1-data | file2-data
>
> The current algorithm in coreboot and seabios says to walk the chain by
> taking the current cbfs_file address, adding the offset (so you're at the
> beginning of the file in question), and adding the file length (so you're at
> the first byte after the file in question). There, the current algorithm
> expects a new cbfs_file header.
>
> But there's already file2's data in the way. Oops.
>
> With the next field, we decouple the file location and the cbfs_file
> location completely. offset/len point to the file data, next points to the
> next header.

Thanks, I see it now.

So this scenario requires that we have two cbfs file headers, and data
somewhere else, not necessarily contiguous with the
header. Does the cbfstool currently create this kind of image?

ron



From mylesgw at gmail.com  Tue May  5 17:34:49 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:34:49 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
	<13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
Message-ID: <2831fecf0905050834i2cb20025pb55088bc256bb739@mail.gmail.com>

On Tue, May 5, 2009 at 9:28 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 8:20 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> On Tue, May 5, 2009 at 9:06 AM, ron minnich <rminnich at gmail.com> wrote:
>>> But I think we have to have clean support for XIP in ROM, which means
>>> we have to have a way for cbfs to place a block of code in a
>>> designated place.
>> So can we force the compiler to make everything inside a block
>> relative so that it can be position-independent?
>
> I've tried in v3, but have been warned that the way we get PIE in v3 is really
> not legitimate, and not guaranteed to keep working. Some form of PIE
> that gnubin experts would accept
> would be very good to have.
Agreed.  I think it should be used very sparingly even if we have it.

> I don't think we'll ever escape the need for some way to force files
> into specific locations. The ROMSTRAP
> code from nvidia is not the first example, nor will it be the last.
>
>
>>> If we are certain we don't need XIP then we don't need this patch. But
>>> if we have XIP we can
>>> remove some fairly confusing __asm__ code in failover, as well as the
>>> attendant load scripts.
>> Does a normal image need to be XIP?
>
> It is now and always has been. I don't know how to make it otherwise.
OK.

>> I think this is the easy part. ?The harder problems have to do with
>> what we want to allow to be constrained to a specific location. ?The
>> fewer of those the better to me.
>
> I agree. The chipset vendors will always create challenges in this
> area, however. And we must still solve our own ROM code issues as
> well.
>
> One option is to do the FILO trick and make %cs point to the start of
> the ROM code that you are running. This is easy: have a GDT entry for
> fallback code and a GDT entry for normal code. Then it suffices to do
> load the %cs with the right segment index for fallback or normal.
> This approach would remove the need for XIP for our ROM segments.
How hard would that be?  I'd be happy to test on SimNOW and a Tyan board.

Thanks,
Myles



From mylesgw at gmail.com  Tue May  5 17:36:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:36:54 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
	<4A005AAF.1090205@georgi-clan.de>
	<13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
Message-ID: <2831fecf0905050836kc2cecd7se90004fcbfad528f@mail.gmail.com>

On Tue, May 5, 2009 at 9:33 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 8:26 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>
>> Consider the following case: The system has _two_ images it requires at
>> fixed addresses right after another. We don't process these images (eg. EC
>> firmware) ourselves, but have to take care that they're at the right spot
>> (similar to your XIP stuff).
>> We want to keep the images as two entries in cbfs (as they have different
>> release cycles)
>>
>> The layout would look like this:
>>
>> file1-data | file2-data
>>
>> The current algorithm in coreboot and seabios says to walk the chain by
>> taking the current cbfs_file address, adding the offset (so you're at the
>> beginning of the file in question), and adding the file length (so you're at
>> the first byte after the file in question). There, the current algorithm
>> expects a new cbfs_file header.
>>
>> But there's already file2's data in the way. Oops.
>>
>> With the next field, we decouple the file location and the cbfs_file
>> location completely. offset/len point to the file data, next points to the
>> next header.
>
> Thanks, I see it now.
>
> So this scenario requires that we have two cbfs file headers, and data
> somewhere else, not necessarily contiguous with the
> header. Does the cbfstool currently create this kind of image?
I don't think so.

I think CBFS requires the header to be contiguous with the data.  We
could change it, but that seems like a fundamental redesign.

It would be easier to walk if all the headers were contiguous.

Myles



From rminnich at gmail.com  Tue May  5 17:40:26 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:40:26 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <2831fecf0905050834i2cb20025pb55088bc256bb739@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
	<13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
	<2831fecf0905050834i2cb20025pb55088bc256bb739@mail.gmail.com>
Message-ID: <13426df10905050840x61793121hfa288db97a345778@mail.gmail.com>

On Tue, May 5, 2009 at 8:34 AM, Myles Watson <mylesgw at gmail.com> wrote:

> How hard would that be? ?I'd be happy to test on SimNOW and a Tyan board.

We would need to link normal such that its addressing is based on some
fixed address (let's just pick one: 80000000).
Then, at runtime, we copy the GDT to CAR data area, and parse the
'stage' header for normal and produce a GDT with an extra
code segment entry for normal that maps that physical normal code (the
code location in ROM) to its virtual address (stage->loadaddress).

That should work. It's a bit more complexity than simple XIP, but it's
very flexitble for future work.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 17:42:12 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 17:42:12 +0200
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
Message-ID: <4A005E54.1020109@gmx.net>

On 05.05.2009 17:24, Myles Watson wrote:
> On Tue, May 5, 2009 at 9:20 AM, ron minnich <rminnich at gmail.com> wrote:
>   
>> On Tue, May 5, 2009 at 8:13 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>>     
>>> 2. Delete - Delete works on the assumption that you want contiguous files
>>>    a. I'm not convinced that fixed CBFS areas will be simpler than
>>> ldscripts.  I consider them both ugly.
>>>       
>> How are we going to support code that runs at a fixed address? I can
>> only come up with
>> these two options. I think the PIE stuff from v3 is not an option:
>> we've been warned about
>> it for a while now, and I now believe the warnings.
>>     
> I wish I knew the best answer here.
>   

Although some people have talked about the evilness of PIE, I believe it
still is the best way forward. And if GCC ever deprecates our usage of
that mode, LLVM people seem to be happy to accommodate fringe use cases
if it gets them improved regression tests or some press attention or a
thank you note.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Tue May  5 17:43:37 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:43:37 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <2831fecf0905050836kc2cecd7se90004fcbfad528f@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
	<4A005AAF.1090205@georgi-clan.de>
	<13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
	<2831fecf0905050836kc2cecd7se90004fcbfad528f@mail.gmail.com>
Message-ID: <13426df10905050843h1687a47flc228da6fa6e8d2fb@mail.gmail.com>

On Tue, May 5, 2009 at 8:36 AM, Myles Watson <mylesgw at gmail.com> wrote:
> On Tue, May 5, 2009 at 9:33 AM, ron minnich <rminnich at gmail.com> wrote:

>> So this scenario requires that we have two cbfs file headers, and data
>> somewhere else, not necessarily contiguous with the
>> header. Does the cbfstool currently create this kind of image?
> I don't think so.

I don't think it does either.

>
> I think CBFS requires the header to be contiguous with the data. ?We
> could change it, but that seems like a fundamental redesign.

Agreed.

>
> It would be easier to walk if all the headers were contiguous.

Agreed. But then you have to leave room somewhere for all possible
headers, which means you have to reserve part of flash for headers
only, which is something I would rather not do.

Many of the proposed changes will result in balooning cbfs code, which
I think we should avoid. I'm not even sure that arbitrary file name
lengths (which we have now) are a good idea :-)

ron



From rminnich at gmail.com  Tue May  5 17:44:41 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 08:44:41 -0700
Subject: [coreboot] CBFS transition plan
In-Reply-To: <4A005E54.1020109@gmx.net>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
	<4A005E54.1020109@gmx.net>
Message-ID: <13426df10905050844l4e85b73p200cb9c18e0eff09@mail.gmail.com>

On Tue, May 5, 2009 at 8:42 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Although some people have talked about the evilness of PIE, I believe it
> still is the best way forward. And if GCC ever deprecates our usage of
> that mode, LLVM people seem to be happy to accommodate fringe use cases
> if it gets them improved regression tests or some press attention or a
> thank you note.

I want to hear about a PIE mode that Segher will find acceptable :-)

ron



From patrick at georgi-clan.de  Tue May  5 17:45:13 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 17:45:13 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<49FFEDF1.4090605@georgi-clan.de>
	<49FFEF46.6010504@gmx.net>	<49FFF1FB.6090900@georgi-clan.de>	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>	<4A005AAF.1090205@georgi-clan.de>
	<13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
Message-ID: <4A005F09.7090907@georgi-clan.de>

Am 05.05.2009 17:33, schrieb ron minnich:
> So this scenario requires that we have two cbfs file headers, and data
> somewhere else, not necessarily contiguous with the
> header. Does the cbfstool currently create this kind of image?
Right now, it isn't able to. Without your patch, it isn't even able to 
put some data at a fixed address, so that patch is the first step in 
that direction.


Patrick



From mylesgw at gmail.com  Tue May  5 17:47:04 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 09:47:04 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050843h1687a47flc228da6fa6e8d2fb@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
	<13426df10905050812q23cd13a8kdc649e5f7dde43c2@mail.gmail.com>
	<4A005AAF.1090205@georgi-clan.de>
	<13426df10905050833s3108acf6u1d8009c1ea87ba70@mail.gmail.com>
	<2831fecf0905050836kc2cecd7se90004fcbfad528f@mail.gmail.com>
	<13426df10905050843h1687a47flc228da6fa6e8d2fb@mail.gmail.com>
Message-ID: <2831fecf0905050847ua3b7920u3f7d600fa2a7fc76@mail.gmail.com>

On Tue, May 5, 2009 at 9:43 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 8:36 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> On Tue, May 5, 2009 at 9:33 AM, ron minnich <rminnich at gmail.com> wrote:
>
>>> So this scenario requires that we have two cbfs file headers, and data
>>> somewhere else, not necessarily contiguous with the
>>> header. Does the cbfstool currently create this kind of image?
>> I don't think so.
>
> I don't think it does either.
>
>>
>> I think CBFS requires the header to be contiguous with the data. ?We
>> could change it, but that seems like a fundamental redesign.
>
> Agreed.
>
>>
>> It would be easier to walk if all the headers were contiguous.
>
> Agreed. But then you have to leave room somewhere for all possible
> headers, which means you have to reserve part of flash for headers
> only, which is something I would rather not do.
Yes.

> Many of the proposed changes will result in balooning cbfs code, which
> I think we should avoid. I'm not even sure that arbitrary file name
> lengths (which we have now) are a good idea :-)

I agree.  I think 16 bytes could be plenty...32 if someone complains
that there aren't enough file names in 16 characters.

Myles



From r.marek at assembler.cz  Tue May  5 17:22:26 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 May 2009 17:22:26 +0200
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
Message-ID: <4A0059B2.9030503@assembler.cz>

Hi Myles,

I tried CBFS on M2V-MX SE. So far it worked (Seabios + gpxe + vga rom) Well done 
  all ;)

It seems that the ROM SIP area for chipset is OK. Is there a way how to verify 
that it will be always so? (Its in last 128B of flash)

I only ran to one issue, did not investigated yet. I had this rom as above and I 
removed the VGA rom and system stopped finding the seabios.

Dont know maybe there is smth wrong with remove,

Rudolf



From mylesgw at gmail.com  Tue May  5 18:15:26 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 10:15:26 -0600
Subject: [coreboot] CBFS transition plan
In-Reply-To: <4A0059B2.9030503@assembler.cz>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<4A0059B2.9030503@assembler.cz>
Message-ID: <2831fecf0905050915u35fb2153x14f4db134e442fcf@mail.gmail.com>

On Tue, May 5, 2009 at 9:22 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hi Myles,
>
> I tried CBFS on M2V-MX SE. So far it worked (Seabios + gpxe + vga rom) Well
> done ?all ;)
>
> It seems that the ROM SIP area for chipset is OK. Is there a way how to
> verify that it will be always so? (Its in last 128B of flash)
As long as the compilation process stays as it is right now.  Right
now we take a working (fallback or failover) image and use it as the
"bootblock".  When that changes there will be no guarantees.  Right
now you should use fallback+failover or fallback-only images.  Normal
is guaranteed to fail.

> I only ran to one issue, did not investigated yet. I had this rom as above
> and I removed the VGA rom and system stopped finding the seabios.
>
> Dont know maybe there is smth wrong with remove,
Most likely.  I thought I fixed remove, but I probably missed a corner case.

Thanks,
Myles



From svn at coreboot.org  Tue May  5 18:15:46 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 May 2009 18:15:46 +0200
Subject: [coreboot] [flashrom] r460 - trunk
Message-ID: <mailman.3164.1355071536.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-05-05 18:15:46 +0200 (Tue, 05 May 2009)
New Revision: 460

Modified:
   trunk/README
   trunk/flashrom.8
Log:
Some cosmetics in README and manpage. Also, move more stuff to the manpage
where it belongs (this also eliminates some duplicated contents).

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/README
===================================================================
--- trunk/README	2009-05-04 22:33:50 UTC (rev 459)
+++ trunk/README	2009-05-05 16:15:46 UTC (rev 460)
@@ -3,7 +3,7 @@
 -------------------------------------------------------------------------------
 
 flashrom is a utility for reading, writing, verifying and erasing flash ROM
-chips.  It's often used to flash BIOS/coreboot/firmware images.
+chips. It's often used to flash BIOS/coreboot/firmware images.
 
 It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
 TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
@@ -15,33 +15,43 @@
 Build Requirements
 ------------------
 
-To build the flashrom utility you need to install the following packages or
-ports:
+To build flashrom you need to install the following packages or ports:
 
 Linux et al:
-* pciutils
-* pciutils-devel / pciutils-dev / libpci-dev
-* zlib-devel / zlib1g-dev
 
+ * pciutils
+ * pciutils-devel / pciutils-dev / libpci-dev
+ * zlib-devel / zlib1g-dev
+
 On FreeBSD, you need the following ports:
-* devel/gmake
-* devel/libpci
 
-To compile on FreeBSD, use the command below:
-gmake
+ * devel/gmake
+ * devel/libpci
 
-To compile on Solaris, use the commands below:
-gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2
+To compile on Linux, use:
 
-To compile on DragonFly BSD, use the commands below:
-ln -s /usr/pkg/include/pciutils pci
-gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
+ make
 
+To compile on FreeBSD, use:
+
+ gmake
+
+To compile on Solaris, use:
+
+ gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" \
+       CFLAGS=-O2
+
+To compile on DragonFly BSD, use:
+
+ ln -s /usr/pkg/include/pciutils pci
+ gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
+
 To compile and run on Darwin/Mac OS X:
-Install DirectIO from coresystems GmbH.
-DirectIO is available at http://www.coresystems.de/en/directio
 
+ Install DirectIO from coresystems GmbH.
+ DirectIO is available at http://www.coresystems.de/en/directio.
 
+
 Usage / Options
 ---------------
 
@@ -51,54 +61,21 @@
 Exit status
 -----------
 
-flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem
-(/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails.
+Please see the flashrom(8) manpage.
 
 
 coreboot Table and Mainboard Identification
 --------------------------------------------
 
-flashrom reads the coreboot table to determine the current mainboard. If no
-coreboot table could be read or if you want to override these values, you can
-specify -m, e.g.:
+Please see the flashrom(8) manpage.
 
- $ flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom
 
-See the 'Supported mainboards' section in the output of 'flashrom -L' for
-a list of boards which require the specification of the board name, if no
-coreboot table is found.
-
-
 ROM Layout Support
 ------------------
 
-flashrom supports ROM layouts. This allows you to flash certain parts of
-the flash chip only. A ROM layout file looks like follows:
+Please see the flashrom(8) manpage.
 
-  00000000:00008fff gfxrom
-  00009000:0003ffff normal
-  00040000:0007ffff fallback
 
-  i.e.:
-  startaddr:endaddr name
-
-  All addresses are offsets within the file, not absolute addresses!
-  
-If you only want to update the normal image in a ROM you can say:
-
-  flashrom -w --layout rom.layout --image normal agami_aruma.rom
-     
-To update normal and fallback but leave the VGA BIOS alone, say:
-
-  flashrom -w -l rom.layout -i normal -i fallback agami_aruma.rom
- 
-Currently overlapping sections are not supported.
-
-ROM layouts should replace the -s and -e option since they are more 
-flexible and they should lead to a ROM update file format with the 
-ROM layout and the ROM image in one file (cpio, zip or something?).
-
-
 Supported Flash Chips / Chipsets / Mainboards
 ---------------------------------------------
 

Modified: trunk/flashrom.8
===================================================================
--- trunk/flashrom.8	2009-05-04 22:33:50 UTC (rev 459)
+++ trunk/flashrom.8	2009-05-05 16:15:46 UTC (rev 460)
@@ -49,15 +49,49 @@
 .TP
 .B "\-s, \-\-estart" <addr>
 Exclude start position (obsolete).
+.sp
+flashrom supports ROM layouts. This allows you to flash certain parts of
+the flash chip only. A ROM layout file looks like follows:
+.sp
+  00000000:00008fff gfxrom
+  00009000:0003ffff normal
+  00040000:0007ffff fallback
+.sp
+  i.e.:
+  startaddr:endaddr name
+.sp
+All addresses are offsets within the file, not absolute addresses!
+If you only want to update the normal image in a ROM you can say:
+.sp
+.B "  flashrom -w --layout rom.layout --image normal agami_aruma.rom"
+.sp
+To update normal and fallback but leave the VGA BIOS alone, say:
+.sp
+.B "  flashrom -w -l rom.layout -i normal \"
+.br
+.B "           -i fallback agami_aruma.rom"
+.sp
+Currently overlapping sections are not supported.
+.sp
+ROM layouts should replace the -s and -e option since they are more
+flexible and they should lead to a ROM update file format with the
+ROM layout and the ROM image in one file (cpio, zip or something?).
 .TP
 .B "\-e, \-\-eend" <addr> 
 Exclude end postion (obsolete).
 .TP
 .B "\-m, \-\-mainboard" <[vendor:]part>
-Override mainboard settings. This option is needed for some mainboards,
-see the
-.B "flashrom \-\-list\-supported"
-output for a list. The vendor is not required when the board name is unique.
+Override mainboard settings.
+.sp
+flashrom reads the coreboot table to determine the current mainboard. If no
+coreboot table could be read or if you want to override these values, you can
+specify -m, e.g.:
+.sp
+.B "  flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom"
+.sp
+See the 'Supported mainboards' section in the output of 'flashrom -L' for
+a list of boards which require the specification of the board name, if no
+coreboot table is found.
 .TP
 .B "\-f, \-\-force"
 Force write without checking whether the ROM image file is really meant




From peter at stuge.se  Tue May  5 18:17:00 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 May 2009 18:17:00 +0200
Subject: [coreboot] [PATCH] flashrom: Rewrite SB600 chipset
	enable	function
In-Reply-To: <49FFF2FE.6080302@gmx.net>
References: <49FFF2FE.6080302@gmx.net>
Message-ID: <20090505161700.19422.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> +		prot = pci_read_long(dev, reg);
> +		if (prot & 0x3)
> +			printf("SB600 %s %s protected from %u to %u\n",
> +				(prot & 0x1) ? "write" : "",
> +				(prot & 0x2) ? "read" : "",
> +				(prot & 0xfffffc00),
> +				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
> +		prot &= 0xfffffffc;
> +		pci_write_byte(dev, reg, prot);

I'd like to avoid writing at all if the region is unprotected. Please
just if (0 == (prot & 0x3)) continue; at the top. Maybe add a message
saying that the region is unprotected.

And I think these should be printf_debug() or such.


> +			printf("SB600 still %s %s protected from %u to %u\n",
> +				(prot & 0x1) ? "write" : "",
> +				(prot & 0x2) ? "read" : "",

Output looks a little nicer if the space is moved down to the
trigraphs.

..still%s%s protected ..
" write" : "",
" read" : ""


Fix this and it's

Acked-by: Peter Stuge <peter at stuge.se>



From patrick at georgi-clan.de  Tue May  5 18:17:53 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 18:17:53 +0200
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
Message-ID: <4A0066B1.8060106@georgi-clan.de>

Am 05.05.2009 17:24, schrieb Myles Watson:
> I think we can put off the decision if we insert CBFS code to find the
> normal image and jump to it.
My next step is to make copy_and_run cbfs aware. That would push the 
coreboot_ram part of both stages into cbfs already, significantly 
decreasing the bootblock size.

It's a low hanging fruit given that copy_and_run is a single code path 
now, and that at this time of the boot process, RAM is available.

After that, I wanted to take a look at the location calculation stuff 
that determines where normal is linked to. That would fix normal and I 
think it can be automated in a way that works for both cbfs and 
"old-style". That would mean less numbers to tweak, too.

Unless you really want to put the remaining fallback/normal code into 
cbfs, in which case that work would be useless. I really like the idea 
of using %cs, if it's known to be stable.


Patrick



From mylesgw at gmail.com  Tue May  5 18:21:38 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 10:21:38 -0600
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050915u35fb2153x14f4db134e442fcf@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<4A0059B2.9030503@assembler.cz>
	<2831fecf0905050915u35fb2153x14f4db134e442fcf@mail.gmail.com>
Message-ID: <2831fecf0905050921i45ed54cv967ef376e1354e31@mail.gmail.com>

On Tue, May 5, 2009 at 10:15 AM, Myles Watson <mylesgw at gmail.com> wrote:
> On Tue, May 5, 2009 at 9:22 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>> Hi Myles,
>>
>> I tried CBFS on M2V-MX SE. So far it worked (Seabios + gpxe + vga rom) Well
>> done ?all ;)
>>
>> It seems that the ROM SIP area for chipset is OK. Is there a way how to
>> verify that it will be always so? (Its in last 128B of flash)
> As long as the compilation process stays as it is right now. ?Right
> now we take a working (fallback or failover) image and use it as the
> "bootblock". ?When that changes there will be no guarantees. ?Right
> now you should use fallback+failover or fallback-only images. ?Normal
> is guaranteed to fail.
>
>> I only ran to one issue, did not investigated yet. I had this rom as above
>> and I removed the VGA rom and system stopped finding the seabios.
>>
>> Dont know maybe there is smth wrong with remove,
> Most likely. ?I thought I fixed remove, but I probably missed a corner case.
If you send me the working ROM I'll look at it before and after VGA removal.

Have you tried a fresh build without the VGA ROM?

Thanks,
Myles



From r.marek at assembler.cz  Tue May  5 17:31:27 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 May 2009 17:31:27 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<1A08A3CEC154439FBB1F59D021D6B942@chimp>	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
	<13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
Message-ID: <4A005BCF.4000502@assembler.cz>

> I don't think we'll ever escape the need for some way to force files
> into specific locations. The ROMSTRAP
> code from nvidia is not the first example, nor will it be the last.

Here are two more. VIA has smth  like this too. (pointer at ffffffd0)
And notebooks usually has the uCode for EC somewhere fixed.

Rudolf



From rminnich at gmail.com  Tue May  5 18:24:08 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 09:24:08 -0700
Subject: [coreboot] CBFS transition plan
In-Reply-To: <4A0066B1.8060106@georgi-clan.de>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
	<4A0066B1.8060106@georgi-clan.de>
Message-ID: <13426df10905050924m2936d9ear1095f82575b73249@mail.gmail.com>

On Tue, May 5, 2009 at 9:17 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:

> My next step is to make copy_and_run cbfs aware. That would push the
> coreboot_ram part of both stages into cbfs already, significantly decreasing
> the bootblock size.

this is the next sensible step to make. I think I jumped a bit ahead
with the XIP patch.

ron



From rminnich at gmail.com  Tue May  5 18:26:12 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 09:26:12 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <4A005BCF.4000502@assembler.cz>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
	<13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
	<4A005BCF.4000502@assembler.cz>
Message-ID: <13426df10905050926m2c5cba18q2928f74b081d227a@mail.gmail.com>

On Tue, May 5, 2009 at 8:31 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>> I don't think we'll ever escape the need for some way to force files
>> into specific locations. The ROMSTRAP
>> code from nvidia is not the first example, nor will it be the last.
>
> Here are two more. VIA has smth ?like this too. (pointer at ffffffd0)
> And notebooks usually has the uCode for EC somewhere fixed.

I would argue that we need, at least, the part of my patch that
includes rom_find_area if we wish to put these types of things in
cbfs.

ron



From mylesgw at gmail.com  Tue May  5 18:28:55 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 10:28:55 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050926m2c5cba18q2928f74b081d227a@mail.gmail.com>
References: <13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<2831fecf0905050820u48c57f16u27daea1f4bed098b@mail.gmail.com>
	<13426df10905050828j66c9207ctb56781996b0caa94@mail.gmail.com>
	<4A005BCF.4000502@assembler.cz>
	<13426df10905050926m2c5cba18q2928f74b081d227a@mail.gmail.com>
Message-ID: <2831fecf0905050928k3e70dd94he93fb59481b6a0d5@mail.gmail.com>

On Tue, May 5, 2009 at 10:26 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 8:31 AM, Rudolf Marek <r.marek at assembler.cz> wrote:
>>> I don't think we'll ever escape the need for some way to force files
>>> into specific locations. The ROMSTRAP
>>> code from nvidia is not the first example, nor will it be the last.
>>
>> Here are two more. VIA has smth ?like this too. (pointer at ffffffd0)
>> And notebooks usually has the uCode for EC somewhere fixed.
>
> I would argue that we need, at least, the part of my patch that
> includes rom_find_area if we wish to put these types of things in
> cbfs.
I agree.  I'd like to go through a round of:

1. It's impossible to do fixed locations.
2. How do we convert everything that's fixed now?
3. What's impossible to do without fixed locations?

Otherwise I'm afraid we'll end up with fixed regions that don't need
to be fixed.

Thanks,
Myles



From svn at coreboot.org  Tue May  5 18:34:54 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 May 2009 18:34:54 +0200
Subject: [coreboot] [flashrom] r461 - trunk
Message-ID: <mailman.3165.1355071536.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-05 18:34:53 +0200 (Tue, 05 May 2009)
New Revision: 461

Modified:
   trunk/flashchips.c
Log:
SST25VF080B TEST_OK_ ERASE WRITE

As reported by A. Spamlover. Thanks!

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/flashchips.c
===================================================================
--- trunk/flashchips.c	2009-05-05 16:15:46 UTC (rev 460)
+++ trunk/flashchips.c	2009-05-05 16:34:53 UTC (rev 461)
@@ -1204,7 +1204,7 @@
 		.model_id	= SST_25VF080B,
 		.total_size	= 1024,
 		.page_size	= 256,
-		.tested		= TEST_OK_PR,
+		.tested		= TEST_OK_PREW,
 		.probe		= probe_spi_rdid,
 		.erase		= spi_chip_erase_60_c7,
 		.write		= spi_chip_write,




From mylesgw at gmail.com  Tue May  5 18:50:58 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 10:50:58 -0600
Subject: [coreboot] CBFS transition plan
In-Reply-To: <13426df10905050924m2936d9ear1095f82575b73249@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
	<4A0066B1.8060106@georgi-clan.de>
	<13426df10905050924m2936d9ear1095f82575b73249@mail.gmail.com>
Message-ID: <2831fecf0905050950n5935cb8bq4ef036069cbc79cb@mail.gmail.com>

On Tue, May 5, 2009 at 10:24 AM, ron minnich <rminnich at gmail.com> wrote:
> On Tue, May 5, 2009 at 9:17 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>
>> My next step is to make copy_and_run cbfs aware. That would push the
>> coreboot_ram part of both stages into cbfs already, significantly decreasing
>> the bootblock size.
Thanks Patrick.  This sounds great.

> this is the next sensible step to make. I think I jumped a bit ahead
> with the XIP patch.
It sparked a good discussion and hopefully clarified where we're going.

Thanks,
Myles



From peter at stuge.se  Tue May  5 18:56:12 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 May 2009 18:56:12 +0200
Subject: [coreboot] [flashrom] r460 - trunk
Message-ID: <20090505165612.31758.qmail@stuge.se>

svn at coreboot.org wrote:
> Some cosmetics in README and manpage.

Thanks!


//Peter



From peter at stuge.se  Tue May  5 19:07:33 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 May 2009 19:07:33 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de>
References: <62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<49FFF1FB.6090900@georgi-clan.de>
Message-ID: <20090505170733.1970.qmail@stuge.se>

Patrick Georgi wrote:
> The "next" field has the disadvantage that we can't simply hot-update 
> anymore, as we'd have to change data (instead of merely adding it).

ron minnich wrote:
> - NEXT pointer
> 
> All of these will work.

'next' foils the desirable property that single files in cbfs can be
updated in the flash chip without touching any other regions.


//Peter



From rminnich at gmail.com  Tue May  5 19:36:07 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 10:36:07 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <20090505170733.1970.qmail@stuge.se>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de> <20090505170733.1970.qmail@stuge.se>
Message-ID: <13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>

On Tue, May 5, 2009 at 10:07 AM, Peter Stuge <peter at stuge.se> wrote:
> Patrick Georgi wrote:
>> The "next" field has the disadvantage that we can't simply hot-update
>> anymore, as we'd have to change data (instead of merely adding it).
>
> ron minnich wrote:
>> - NEXT pointer
>>
>> All of these will work.
>
> 'next' foils the desirable property that single files in cbfs can be
> updated in the flash chip without touching any other regions.

Isn't this somewhat mythical anyway? how many flash chips support
'erase byte' at this point (I honestly don't know!). I.e., isn't an
update of any one byte in a block going to wipe out a whole block? How
many cbfs files fit on neat 64k or 16k or whatever boundaries?

I don't know these answers, but you do :-)

ron



From peter at stuge.se  Tue May  5 19:50:03 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 May 2009 19:50:03 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>
	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
Message-ID: <20090505175004.14302.qmail@stuge.se>

ron minnich wrote:
> > 'next' foils the desirable property that single files in cbfs can
> > be updated in the flash chip without touching any other regions.
> 
> Isn't this somewhat mythical anyway?

No sir.


> how many flash chips support 'erase byte' at this point (I honestly
> don't know!). I.e., isn't an update of any one byte in a block
> going to wipe out a whole block? How many cbfs files fit on neat
> 64k or 16k or whatever boundaries?

None have single byte erase blocks, but most of the SPI flash chips
can actually do 256 byte erase blocks.

I think it is important to keep the alignment in mind, so that files
can be fit onto boundaries. I also think we should try to do it in
the normal case.

I keep imagining how I will be able to safely update the coreboot
normal image but keep fallback, stages and payloads untouched.

Another factor is that this is something our competition already
allows, so we want to do it as well.


//Peter



From mylesgw at gmail.com  Tue May  5 19:54:04 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 11:54:04 -0600
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <20090505175004.14302.qmail@stuge.se>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de> <20090505170733.1970.qmail@stuge.se>
	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
	<20090505175004.14302.qmail@stuge.se>
Message-ID: <2831fecf0905051054n3f584f9bi888ec38ff8464177@mail.gmail.com>

On Tue, May 5, 2009 at 11:50 AM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> > 'next' foils the desirable property that single files in cbfs can
>> > be updated in the flash chip without touching any other regions.
>>
>> Isn't this somewhat mythical anyway?
>
> No sir.
>
>
>> how many flash chips support 'erase byte' at this point (I honestly
>> don't know!). I.e., isn't an update of any one byte in a block
>> going to wipe out a whole block? How many cbfs files fit on neat
>> 64k or 16k or whatever boundaries?
>
> None have single byte erase blocks, but most of the SPI flash chips
> can actually do 256 byte erase blocks.

Since erase block granularity is chip dependent, shouldn't flashrom be
in charge of touching the minimal number of blocks?  I don't see how
CBFS can know which chip it will be used in.

> I think it is important to keep the alignment in mind, so that files
> can be fit onto boundaries. I also think we should try to do it in
> the normal case.
What's the most common boundary?  1K, 2K, 4K?  Should we pick one that
is reasonable?

> I keep imagining how I will be able to safely update the coreboot
> normal image but keep fallback, stages and payloads untouched.
That would be nice.

Thanks,
Myles



From rminnich at gmail.com  Tue May  5 19:59:40 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 10:59:40 -0700
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <20090505175004.14302.qmail@stuge.se>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>
	<62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de> <20090505170733.1970.qmail@stuge.se>
	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
	<20090505175004.14302.qmail@stuge.se>
Message-ID: <13426df10905051059l23191c84gf890a37a4c495daf@mail.gmail.com>

On Tue, May 5, 2009 at 10:50 AM, Peter Stuge <peter at stuge.se> wrote:

>
> No sir.

This is great!

> None have single byte erase blocks, but most of the SPI flash chips
> can actually do 256 byte erase blocks.

Should we move to 256 byte default alignment?


> I keep imagining how I will be able to safely update the coreboot
> normal image but keep fallback, stages and payloads untouched.

me too.

ron



From peter at stuge.se  Tue May  5 20:08:56 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 5 May 2009 20:08:56 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <2831fecf0905051054n3f584f9bi888ec38ff8464177@mail.gmail.com>
References: <62A75D47A41940C0BE145BCFD1C070C6@chimp>
	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>
	<49FFEDF1.4090605@georgi-clan.de> <49FFEF46.6010504@gmx.net>
	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>
	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>
	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
	<20090505175004.14302.qmail@stuge.se>
	<2831fecf0905051054n3f584f9bi888ec38ff8464177@mail.gmail.com>
Message-ID: <20090505180856.19981.qmail@stuge.se>

Myles Watson wrote:
> > None have single byte erase blocks, but most of the SPI flash chips
> > can actually do 256 byte erase blocks.
> 
> Since erase block granularity is chip dependent, shouldn't flashrom
> be in charge of touching the minimal number of blocks?  I don't see
> how CBFS can know which chip it will be used in.

Correct, it can't on it's own, and I think flash writing and cbfs
expertise will go together eventually. I expect cbfstool and flashrom
to converge a bit. Not all the way into one tool, but they will be
close.


> What's the most common boundary?  1K, 2K, 4K?  Should we pick one
> that is reasonable?

Fun fun. A few chips even have odd-byte boundaries like 4300 bytes or
whatever. And some are very much not symmetrical.

I think it's impossible to pick a good universal default. The target
flash chip layout is required information. I expect the final
decision to be defered until actual flash write time. It could
certainly be the case that not everything in the flash chip can be
aligned into it's own block at that point.


//Peter



From patrick at georgi-clan.de  Tue May  5 20:11:30 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 05 May 2009 20:11:30 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <20090505170733.1970.qmail@stuge.se>
References: <62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<1A08A3CEC154439FBB1F59D021D6B942@chimp>	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>	<13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<49FFEDF1.4090605@georgi-clan.de>
	<49FFEF46.6010504@gmx.net>	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>
Message-ID: <4A008152.4030802@georgi-clan.de>

Am 05.05.2009 19:07, schrieb Peter Stuge:
> 'next' foils the desirable property that single files in cbfs can be
> updated in the flash chip without touching any other regions.
Two options:
1. have next point to 0xffffffff and replace the whole block it's in
2. have next point to a validated clean area (esp. no magic) and force 
the next cbfs_file header there.

2. is better, but there might be the rare corner case that the intended 
area is fixed memory for a new entry.

I guess we can live with that, right?


Patrick



From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 21:32:16 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 21:32:16 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>	<13426df10905042004s54514272m723c95f134c23e7f@mail.gmail.com>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<49FFEDF1.4090605@georgi-clan.de>
	<49FFEF46.6010504@gmx.net>	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>
	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>
Message-ID: <4A009440.5070609@gmx.net>

On 05.05.2009 19:36, ron minnich wrote:
> Isn't this somewhat mythical anyway? how many flash chips support
> 'erase byte' at this point (I honestly don't know!). I.e., isn't an
> update of any one byte in a block going to wipe out a whole block? How
> many cbfs files fit on neat 64k or 16k or whatever boundaries?
>   

Intel specifies that each flash chip location (byte) must be writable at
least twice after each erase, so you can update a previously written
byte once (well, set some more bits to 0) without erasing.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 21:35:00 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 21:35:00 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <2831fecf0905051054n3f584f9bi888ec38ff8464177@mail.gmail.com>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<49FFEDF1.4090605@georgi-clan.de>
	<49FFEF46.6010504@gmx.net>	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>	<20090505175004.14302.qmail@stuge.se>
	<2831fecf0905051054n3f584f9bi888ec38ff8464177@mail.gmail.com>
Message-ID: <4A0094E4.2000803@gmx.net>

On 05.05.2009 19:54, Myles Watson wrote:
> On Tue, May 5, 2009 at 11:50 AM, Peter Stuge <peter at stuge.se> wrote:
>   
>> ron minnich wrote:
>>     
>>> how many flash chips support 'erase byte' at this point (I honestly
>>> don't know!). I.e., isn't an update of any one byte in a block
>>> going to wipe out a whole block? How many cbfs files fit on neat
>>> 64k or 16k or whatever boundaries?
>>>       
>> None have single byte erase blocks, but most of the SPI flash chips
>> can actually do 256 byte erase blocks.
>>     
>
> Since erase block granularity is chip dependent, shouldn't flashrom be
> in charge of touching the minimal number of blocks?  I don't see how
> CBFS can know which chip it will be used in.
>   

Yes. I need to resend the flashrom patches solving this.


>> I think it is important to keep the alignment in mind, so that files
>> can be fit onto boundaries. I also think we should try to do it in
>> the normal case.
>>     
> What's the most common boundary?  1K, 2K, 4K?  Should we pick one that
> is reasonable?
>   

There is no common boundary. It all depends on how much you're willing
to pay per chip. I've seen anything from 256 Bytes to 64 kBytes as erase
granularity for SPI chips currently in production. Of course, some chips
have non-uniform erase sizes. That makes it even harder to handle.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Tue May  5 21:37:58 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 May 2009 21:37:58 +0200
Subject: [coreboot] cbfs XIP patch
In-Reply-To: <13426df10905051059l23191c84gf890a37a4c495daf@mail.gmail.com>
References: <1A08A3CEC154439FBB1F59D021D6B942@chimp>	<62A75D47A41940C0BE145BCFD1C070C6@chimp>	<13426df10905042155u6ddfd1bcq63625a1806f1c324@mail.gmail.com>	<49FFEDF1.4090605@georgi-clan.de>
	<49FFEF46.6010504@gmx.net>	<13426df10905050806n507f6372gc4c5a799a86496d0@mail.gmail.com>	<49FFF1FB.6090900@georgi-clan.de>
	<20090505170733.1970.qmail@stuge.se>	<13426df10905051036p52ae03afo85ac0af9d6897e7a@mail.gmail.com>	<20090505175004.14302.qmail@stuge.se>
	<13426df10905051059l23191c84gf890a37a4c495daf@mail.gmail.com>
Message-ID: <4A009596.8010704@gmx.net>

On 05.05.2009 19:59, ron minnich wrote:
> On Tue, May 5, 2009 at 10:50 AM, Peter Stuge <peter at stuge.se> wrote:
>
>   
>> No sir.
>>     
>
> This is great!
>
>   
>> None have single byte erase blocks, but most of the SPI flash chips
>> can actually do 256 byte erase blocks.
>>     
>
> Should we move to 256 byte default alignment?
>   

256 byte LAR member _content_ alignment or _header_ alignment? Sometimes
it may be useful to have the content aligned.


>> I keep imagining how I will be able to safely update the coreboot
>> normal image but keep fallback, stages and payloads untouched.
>>     
>
> me too.
>   

With LAR and a patched flashrom this is possible right now.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From beber at meleeweb.net  Tue May  5 22:22:05 2009
From: beber at meleeweb.net (Beber)
Date: Tue, 5 May 2009 22:22:05 +0200
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
Message-ID: <20090505222205.73554045@jojo.scabb>

Hi,

Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
fail no there is not reason to lseek in. Actually this is a trivial fix
for not well handled return from open.

Signed-off-by: Bertrand Jacquin <beber at meleeweb.net>

Patch is attached

-- 
Beber
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From rminnich at gmail.com  Tue May  5 22:26:55 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 13:26:55 -0700
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <20090505222205.73554045@jojo.scabb>
References: <20090505222205.73554045@jojo.scabb>
Message-ID: <13426df10905051326m11bc360aucf11193ec2b175ed@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Tue May  5 23:08:36 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  5 May 2009 23:08:36 +0200
Subject: [coreboot] [flashrom] r462 - trunk
Message-ID: <mailman.3166.1355071536.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-05-05 23:08:36 +0200 (Tue, 05 May 2009)
New Revision: 462

Modified:
   trunk/chipset_enable.c
Log:
Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
fails so there is no reason to lseek in. Actually this is a trivial fix
for a bad return value from open.

Signed-off-by: Bertrand Jacquin <beber at meleeweb.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-05 16:34:53 UTC (rev 461)
+++ trunk/chipset_enable.c	2009-05-05 21:08:36 UTC (rev 462)
@@ -511,7 +511,7 @@
 	unsigned char buf[8];
 
 	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
-	if (!fd_msr) {
+	if (fd_msr == -1) {
 		perror("open msr");
 		return -1;
 	}




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 00:11:46 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 00:11:46 +0200
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <20090505222205.73554045@jojo.scabb>
References: <20090505222205.73554045@jojo.scabb>
Message-ID: <4A00B9A2.5050803@gmx.net>

Hi Bertrand,

On 05.05.2009 22:22, Beber wrote:
> Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
> fail no there is not reason to lseek in. Actually this is a trivial fix
> for not well handled return from open.
>   

Although the fix seems trivial, it breaks the code a few lines down.
With the old code, you got a meaningful error message about having to
run "modprobe msr". This error message does not trigger anymore with the
new code.
Please fix. Thanks.


Regards,
Carl-Daniel

> Signed-off-by: Bertrand Jacquin <beber at meleeweb.net>
>
> Index: chipset_enable.c
> ===================================================================
> --- chipset_enable.c	(revision 461)
> +++ chipset_enable.c	(working copy)
> @@ -511,7 +511,7 @@
>  	unsigned char buf[8];
>  
>  	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
> -	if (!fd_msr) {
> +	if (fd_msr == -1) {
>  		perror("open msr");
>  		return -1;
>  	}
>
>   


-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Wed May  6 00:19:20 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 16:19:20 -0600
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <4A00B9A2.5050803@gmx.net>
References: <20090505222205.73554045@jojo.scabb> <4A00B9A2.5050803@gmx.net>
Message-ID: <C6ABA73D8B664E8DA4E4A6119DD4B855@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Carl-Daniel Hailfinger
> Sent: Tuesday, May 05, 2009 4:12 PM
> To: Beber
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
> 
> Hi Bertrand,
> 
> On 05.05.2009 22:22, Beber wrote:
> > Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
> > fail no there is not reason to lseek in. Actually this is a trivial fix
> > for not well handled return from open.
> >
> 
> Although the fix seems trivial, it breaks the code a few lines down.
> With the old code, you got a meaningful error message about having to
> run "modprobe msr". This error message does not trigger anymore with the
> new code.
> Please fix. Thanks.

Is this what you're asking for?

Index: util/flashrom/chipset_enable.c
===================================================================
--- util/flashrom/chipset_enable.c	(revision 462)
+++ util/flashrom/chipset_enable.c	(working copy)
@@ -512,7 +512,8 @@
 
 	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
 	if (fd_msr == -1) {
-		perror("open msr");
+		perror("open /dev/cpu/0/msr");
+		printf("Cannot open MSR. Did you run 'modprobe msr'?\n");
 		return -1;
 	}

Thanks,
Myles




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 00:30:56 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 00:30:56 +0200
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <C6ABA73D8B664E8DA4E4A6119DD4B855@chimp>
References: <20090505222205.73554045@jojo.scabb> <4A00B9A2.5050803@gmx.net>
	<C6ABA73D8B664E8DA4E4A6119DD4B855@chimp>
Message-ID: <4A00BE20.6010800@gmx.net>

On 06.05.2009 00:19, Myles Watson wrote:
>   
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Carl-Daniel Hailfinger
>> Sent: Tuesday, May 05, 2009 4:12 PM
>> To: Beber
>> Cc: coreboot at coreboot.org
>> Subject: Re: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
>>
>> Hi Bertrand,
>>
>> On 05.05.2009 22:22, Beber wrote:
>>     
>>> Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
>>> fail no there is not reason to lseek in. Actually this is a trivial fix
>>> for not well handled return from open.
>>>
>>>       
>> Although the fix seems trivial, it breaks the code a few lines down.
>> With the old code, you got a meaningful error message about having to
>> run "modprobe msr". This error message does not trigger anymore with the
>> new code.
>> Please fix. Thanks.
>>     
>
> Is this what you're asking for?
>   

Partially. I think it would make sense to unify this with the first
lseek() error check, but I don't have strong preferences either way.

> Index: util/flashrom/chipset_enable.c
> ===================================================================
> --- util/flashrom/chipset_enable.c	(revision 462)
> +++ util/flashrom/chipset_enable.c	(working copy)
> @@ -512,7 +512,8 @@
>  
>  	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
>  	if (fd_msr == -1) {
> -		perror("open msr");
> +		perror("open /dev/cpu/0/msr");
> +		printf("Cannot open MSR. Did you run 'modprobe msr'?\n");
>  		return -1;
>  	}
>
>   

If you think this is the preferred fix, I'll ack it once you signoff.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Wed May  6 00:33:52 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 16:33:52 -0600
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <4A00BE20.6010800@gmx.net>
References: <20090505222205.73554045@jojo.scabb> <4A00B9A2.5050803@gmx.net>
	<C6ABA73D8B664E8DA4E4A6119DD4B855@chimp> <4A00BE20.6010800@gmx.net>
Message-ID: <2831fecf0905051533r709434e0m5a08a1653fb02e37@mail.gmail.com>

On Tue, May 5, 2009 at 4:30 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 06.05.2009 00:19, Myles Watson wrote:
>>
>>> -----Original Message-----
>>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>>> On Behalf Of Carl-Daniel Hailfinger
>>> Sent: Tuesday, May 05, 2009 4:12 PM
>>> To: Beber
>>> Cc: coreboot at coreboot.org
>>> Subject: Re: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
>>>
>>> Hi Bertrand,
>>>
>>> On 05.05.2009 22:22, Beber wrote:
>>>
>>>> Here is a fix for chipset_enable.c when there is not /dev/cpu. Open
>>>> fail no there is not reason to lseek in. Actually this is a trivial fix
>>>> for not well handled return from open.
>>>>
>>>>
>>> Although the fix seems trivial, it breaks the code a few lines down.
>>> With the old code, you got a meaningful error message about having to
>>> run "modprobe msr". This error message does not trigger anymore with the
>>> new code.
>>> Please fix. Thanks.
>>>
>>
>> Is this what you're asking for?
>>
>
> Partially. I think it would make sense to unify this with the first
> lseek() error check, but I don't have strong preferences either way.

If you have something specific in mind, it should only be a couple of lines.

I'll ack it.

Thanks,
Myles



From svn at coreboot.org  Wed May  6 00:50:08 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 00:50:08 +0200
Subject: [coreboot] [flashrom] r463 - trunk
Message-ID: <mailman.3167.1355071536.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-06 00:50:07 +0200 (Wed, 06 May 2009)
New Revision: 463

Modified:
   trunk/chipset_enable.c
Log:
Rewrite the SB600 chipset enable function:
- Check for read/write protected regions first.
- Region protection is write-once according to the data sheets. Check if
the write succeeded. Don't write if the region is not protected.
- Verbose region protection dumping.
- Improve readability of BAR mapping code.
- Align BAR mapping to a page boundary (4k) instead of a 16k boundary.

This patch prepares the code for a SPI detection heuristic.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-05 21:08:36 UTC (rev 462)
+++ trunk/chipset_enable.c	2009-05-05 22:50:07 UTC (rev 463)
@@ -658,33 +658,49 @@
 
 static int enable_flash_sb600(struct pci_dev *dev, const char *name)
 {
-	uint32_t tmp, low_bits, num;
+	uint32_t tmp, prot;
 	uint8_t reg;
 
-	low_bits = tmp = pci_read_long(dev, 0xa0);
-	low_bits &= ~0xffffc000; /* for mmap aligning requirements */
-	low_bits &= 0xfffffff0;	/* remove low 4 bits */
-	tmp &= 0xffffc000;
-	printf_debug("SPI base address is at 0x%x\n", tmp + low_bits);
-
-	sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000);
-	sb600_spibar += low_bits;
-
 	/* Clear ROM protect 0-3. */
 	for (reg = 0x50; reg < 0x60; reg += 4) {
-		num = pci_read_long(dev, reg);
-		num &= 0xfffffffc;
-		pci_write_byte(dev, reg, num);
+		prot = pci_read_long(dev, reg);
+		/* No protection flags for this region?*/
+		if ((prot & 0x3) == 0)
+			continue;
+		printf_debug("SB600 %s%sprotected from %u to %u\n",
+			(prot & 0x1) ? "write " : "",
+			(prot & 0x2) ? "read " : "",
+			(prot & 0xfffffc00),
+			(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
+		prot &= 0xfffffffc;
+		pci_write_byte(dev, reg, prot);
+		prot = pci_read_long(dev, reg);
+		if (prot & 0x3)
+			printf("SB600 still %s%sprotected from %u to %u\n",
+				(prot & 0x1) ? "write " : "",
+				(prot & 0x2) ? "read " : "",
+				(prot & 0xfffffc00),
+				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
 	}
 
+	/* Read SPI_BaseAddr */
+	tmp = pci_read_long(dev, 0xa0);
+	tmp &= 0xfffffff0;	/* remove low 4 bits (reserved) */
+	printf_debug("SPI base address is at 0x%x\n", tmp);
+
+	/* Physical memory can only be mapped at page (4k) boundaries */
+	sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
+	/* The low bits of the SPI base address are used as offset into the mapped page */
+	sb600_spibar += tmp & 0xfff;
+
 	flashbus = BUS_TYPE_SB600_SPI;
 
-	/* Enable SPI ROM in SB600 PM register. */
-	/* If we enable SPI ROM here, we have to disable it after we leave.
+	/* Force enable SPI ROM in SB600 PM register.
+	 * If we enable SPI ROM here, we have to disable it after we leave.
 	 * But how can we know which ROM we are going to handle? So we have
 	 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
-	 * only SPI ROM if we boot via SPI ROM. If you want to do it crossly,
-	 * you have to use the code below.
+	 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
+	 * boards with LPC straps, you have to use the code below.
 	 */
 	/*
 	OUTB(0x8f, 0xcd6);




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 00:50:23 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 00:50:23 +0200
Subject: [coreboot] [PATCH] flashrom: Rewrite SB600
	chipset	enable	function
In-Reply-To: <20090505161700.19422.qmail@stuge.se>
References: <49FFF2FE.6080302@gmx.net> <20090505161700.19422.qmail@stuge.se>
Message-ID: <4A00C2AF.3070803@gmx.net>

On 05.05.2009 18:17, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> +		prot = pci_read_long(dev, reg);
>> +		if (prot & 0x3)
>> +			printf("SB600 %s %s protected from %u to %u\n",
>> +				(prot & 0x1) ? "write" : "",
>> +				(prot & 0x2) ? "read" : "",
>> +				(prot & 0xfffffc00),
>> +				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
>> +		prot &= 0xfffffffc;
>> +		pci_write_byte(dev, reg, prot);
>>     
>
> I'd like to avoid writing at all if the region is unprotected. Please
> just if (0 == (prot & 0x3)) continue; at the top.

Done.

> Maybe add a message
> saying that the region is unprotected.
>   

An empty region with zero address and no protection flags probably does
not need printing IMHO.


> And I think these should be printf_debug() or such.
>   

I made the first printf printf_debug and the second one (failure)
unconditional printf. Not telling the user about a failed unprotect is bad.


>> +			printf("SB600 still %s %s protected from %u to %u\n",
>> +				(prot & 0x1) ? "write" : "",
>> +				(prot & 0x2) ? "read" : "",
>>     
>
> Output looks a little nicer if the space is moved down to the
> trigraphs.
>
> ..still%s%s protected ..
> " write" : "",
> " read" : ""
>
>
> Fix this and it's
>   

Done.

> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks, committed in r463.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 01:44:14 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 01:44:14 +0200
Subject: [coreboot] [PATCH] flashrom: Clean up SB400 chipset enable
Message-ID: <4A00CF4E.1020406@gmx.net>

Clean up the SB400 chipset enable code. Use pci_dev_find() instead of
setting up a filter and iterating over PCI devices.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-sb400/chipset_enable.c
===================================================================
--- flashrom-sb400/chipset_enable.c	(Revision 463)
+++ flashrom-sb400/chipset_enable.c	(Arbeitskopie)
@@ -741,19 +741,11 @@
 static int enable_flash_sb400(struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
-	struct pci_filter f;
 	struct pci_dev *smbusdev;
 
 	/* Look for the SMBus device. */
-	pci_filter_init((struct pci_access *)0, &f);
-	f.vendor = 0x1002;
-	f.device = 0x4372;
+	smbusdev = pci_dev_find(0x1002, 0x4372);
 
-	for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
-		if (pci_filter_match(&f, smbusdev))
-			break;
-	}
-
 	if (!smbusdev) {
 		fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
 		exit(1);


-- 
http://www.hailfinger.org/

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From stepan at coresystems.de  Wed May  6 01:57:40 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 May 2009 01:57:40 +0200
Subject: [coreboot] [PATCH] flashrom: Clean up SB400 chipset enable
In-Reply-To: <4A00CF4E.1020406@gmx.net>
References: <4A00CF4E.1020406@gmx.net>
Message-ID: <4A00D274.8080508@coresystems.de>

On 06.05.2009 1:44 Uhr, Carl-Daniel Hailfinger wrote:
> Clean up the SB400 chipset enable code. Use pci_dev_find() instead of
> setting up a filter and iterating over PCI devices.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   
nice!

Acked-by: Stefan Reinauer <stepan at coresystems.de>


Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From kevin at koconnor.net  Wed May  6 02:14:18 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 5 May 2009 20:14:18 -0400
Subject: [coreboot] CBFS transition plan
In-Reply-To: <4A0066B1.8060106@georgi-clan.de>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>
	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>
	<4A0066B1.8060106@georgi-clan.de>
Message-ID: <20090506001418.GA32634@morn.localdomain>

On Tue, May 05, 2009 at 06:17:53PM +0200, Patrick Georgi wrote:
> Am 05.05.2009 17:24, schrieb Myles Watson:
>> I think we can put off the decision if we insert CBFS code to find the
>> normal image and jump to it.
> My next step is to make copy_and_run cbfs aware. That would push the  
> coreboot_ram part of both stages into cbfs already, significantly  
> decreasing the bootblock size.
>
> It's a low hanging fruit given that copy_and_run is a single code path  
> now, and that at this time of the boot process, RAM is available.

Thanks - that would be great to see.

What are your plans with lzma decoding?  (Will the bootblock have an
lzma decoder for deploying coreboot_ram and will coreboot_ram have an
lzma decoder for the payload?)

> Unless you really want to put the remaining fallback/normal code into  
> cbfs, in which case that work would be useless. I really like the idea  
> of using %cs, if it's known to be stable.

SeaBIOS must deal with %cs modifications, so I'm familiar with using
it.  However, it's not clear to me what coreboot needs it for.  Can
someone point me to a discussion on the problems with PIE?

-Kevin



From svn at coreboot.org  Wed May  6 02:35:32 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 02:35:32 +0200
Subject: [coreboot] [flashrom] r464 - trunk
Message-ID: <mailman.3168.1355071537.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-06 02:35:31 +0200 (Wed, 06 May 2009)
New Revision: 464

Modified:
   trunk/chipset_enable.c
Log:
Clean up the SB400 chipset enable code. Use pci_dev_find() instead of
setting up a filter and iterating over PCI devices.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-05 22:50:07 UTC (rev 463)
+++ trunk/chipset_enable.c	2009-05-06 00:35:31 UTC (rev 464)
@@ -741,19 +741,11 @@
 static int enable_flash_sb400(struct pci_dev *dev, const char *name)
 {
 	uint8_t tmp;
-	struct pci_filter f;
 	struct pci_dev *smbusdev;
 
 	/* Look for the SMBus device. */
-	pci_filter_init((struct pci_access *)0, &f);
-	f.vendor = 0x1002;
-	f.device = 0x4372;
+	smbusdev = pci_dev_find(0x1002, 0x4372);
 
-	for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
-		if (pci_filter_match(&f, smbusdev))
-			break;
-	}
-
 	if (!smbusdev) {
 		fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
 		exit(1);




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 02:39:22 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 02:39:22 +0200
Subject: [coreboot] [PATCH] flashrom: Clean up SB400 chipset enable
In-Reply-To: <4A00D274.8080508@coresystems.de>
References: <4A00CF4E.1020406@gmx.net> <4A00D274.8080508@coresystems.de>
Message-ID: <4A00DC3A.2090004@gmx.net>

On 06.05.2009 01:57, Stefan Reinauer wrote:
> On 06.05.2009 1:44 Uhr, Carl-Daniel Hailfinger wrote:
>   
>> Clean up the SB400 chipset enable code. Use pci_dev_find() instead of
>> setting up a filter and iterating over PCI devices.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>   
>>     
> nice!
>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
>   

Thanks, committed in r464.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From kevin at koconnor.net  Wed May  6 02:44:59 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 5 May 2009 20:44:59 -0400
Subject: [coreboot] CBFS transition plan
In-Reply-To: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
Message-ID: <20090506004459.GB32634@morn.localdomain>

On Tue, May 05, 2009 at 09:13:32AM -0600, Myles Watson wrote:
> 3. PCI ROM optimization.  There should be some optimization for ROMs.
>     a. Possibilities:
>         1. Traverse ROM once and set a flag in devices which have ROMs
>         2. Traverse ROM and keep a list of ROMs
>         3. ....

Are you referring to the email I sent on the time SeaBIOS spent
traversing CBFS to find option roms?

I did modify SeaBIOS so that option roms scans are much faster.  (The
cost is now negligible.)  I accomplished this by ending the file scan
if a signature of zeros is found.

I don't think caching the list of files in the flash will work well -
even one brute force scan will take too much time on large flash
chips.  Instead, I think CBFS needs to have an orderly layout of files
which doesn't require users to do a brute force scan.

I think there's a simple way to accomplish this - have cbfstool create
"null" files that contain all the empty space.  Then the users of cbfs
(eg, coreboot, seabios) wouldn't need any special code - they would
skip them just like they skip over any other file.

-Kevin



From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 02:50:53 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 02:50:53 +0200
Subject: [coreboot] [PATCH] flashrom: SB600 SPI detection heuristic
Message-ID: <4A00DEED.1030608@gmx.net>

Create a SB600 SPI detection heuristic.

I know that the data sheets say we can't read the ROM straps, but
creative interpretation of the data sheets yielded a heuristic which
should work pretty well.

NOTE: If you test this, make sure you power down and _unplug_ the
machine for a few minutes before you boot and run flashrom with this patch.
If the machine is not unplugged for some time, the test will yield
incorrect results.
If you run a slightly older flashrom version than svn HEAD, the test
will yield incorrect results.
If you run any flashrom version (except svn HEAD plus this patch) after
poweron, the test will yield incorrect results.

Explanation:
Older flashrom versions unconditionally stomp on registers which are
used for this heuristic. These registers are in the S5 power domain, so
even powering down does not clear them, you really have to unplug the
machine.

Please run
flashrom --verbose
once and post the output to this list.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-sb600/chipset_enable.c
===================================================================
--- flashrom-sb600/chipset_enable.c	(Revision 464)
+++ flashrom-sb600/chipset_enable.c	(Arbeitskopie)
@@ -660,6 +660,8 @@
 {
 	uint32_t tmp, prot;
 	uint8_t reg;
+	struct pci_dev *smbus_dev;
+	int has_spi = 1;
 
 	/* Clear ROM protect 0-3. */
 	for (reg = 0x50; reg < 0x60; reg += 4) {
@@ -688,13 +690,48 @@
 	tmp &= 0xfffffff0;	/* remove low 4 bits (reserved) */
 	printf_debug("SPI base address is at 0x%x\n", tmp);
 
+	/* If the BAR has address 0, it is unlikely SPI is used. */
+	if (!tmp)
+		has_spi = 0;
+
 	/* Physical memory can only be mapped at page (4k) boundaries */
 	sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
 	/* The low bits of the SPI base address are used as offset into the mapped page */
 	sb600_spibar += tmp & 0xfff;
 
-	flashbus = BUS_TYPE_SB600_SPI;
+	/* Look for the SMBus device. */
+	smbus_dev = pci_dev_find(0x1002, 0x4385);
 
+	if (!smbus_dev) {
+		fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
+		has_spi = 0;
+	} else {
+		/* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
+		/* GPIO11/SPI_DO and GPIO12/SPI_DI status */
+		reg = pci_read_byte(smbus_dev, 0xAB);
+		reg &= 0xC0;
+		printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
+		printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
+		if (reg != 0x00)
+			has_spi = 0;
+		/* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
+		reg = pci_read_byte(smbus_dev, 0x83);
+		reg &= 0xC0;
+		printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
+		printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
+		if (reg != 0x00)
+			has_spi = 0;
+		/* GPIO47/SPI_CLK status */
+		reg = pci_read_byte(smbus_dev, 0xA7);
+		reg &= 0x40;
+		printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
+		if (reg != 0x00)
+			has_spi = 0;
+	}
+
+	if (has_spi)
+		flashbus = BUS_TYPE_SB600_SPI;
+
 	/* Force enable SPI ROM in SB600 PM register.
 	 * If we enable SPI ROM here, we have to disable it after we leave.
 	 * But how can we know which ROM we are going to handle? So we have


-- 
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From stepan at coresystems.de  Wed May  6 03:22:45 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 06 May 2009 03:22:45 +0200
Subject: [coreboot] [PATCH] flashrom: SB600 SPI detection heuristic
In-Reply-To: <4A00DEED.1030608@gmx.net>
References: <4A00DEED.1030608@gmx.net>
Message-ID: <4A00E665.7070408@coresystems.de>

On 06.05.2009 2:50 Uhr, Carl-Daniel Hailfinger wrote:
> Create a SB600 SPI detection heuristic.
>
> I know that the data sheets say we can't read the ROM straps, but
> creative interpretation of the data sheets yielded a heuristic which
> should work pretty well.
>
> NOTE: If you test this, make sure you power down and _unplug_ the
> machine for a few minutes before you boot and run flashrom with this patch.
> If the machine is not unplugged for some time, the test will yield
> incorrect results.
> If you run a slightly older flashrom version than svn HEAD, the test
> will yield incorrect results.
> If you run any flashrom version (except svn HEAD plus this patch) after
> poweron, the test will yield incorrect results.
>
> Explanation:
> Older flashrom versions unconditionally stomp on registers which are
> used for this heuristic. These registers are in the S5 power domain, so
> even powering down does not clear them, you really have to unplug the
> machine.
>   
(and remove the battery if it is a laptop)

> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From mylesgw at gmail.com  Wed May  6 03:47:53 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 5 May 2009 19:47:53 -0600
Subject: [coreboot] CBFS transition plan
In-Reply-To: <20090506004459.GB32634@morn.localdomain>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<20090506004459.GB32634@morn.localdomain>
Message-ID: <5ACA763229764918A17DD6B85C4F4484@chimp>



> -----Original Message-----
> From: Kevin O'Connor [mailto:kevin at koconnor.net]
> Sent: Tuesday, May 05, 2009 6:45 PM
> To: Myles Watson
> Cc: coreboot
> Subject: Re: [coreboot] CBFS transition plan
> 
> On Tue, May 05, 2009 at 09:13:32AM -0600, Myles Watson wrote:
> > 3. PCI ROM optimization.  There should be some optimization for ROMs.
> >     a. Possibilities:
> >         1. Traverse ROM once and set a flag in devices which have ROMs
> >         2. Traverse ROM and keep a list of ROMs
> >         3. ....
> 
> Are you referring to the email I sent on the time SeaBIOS spent
> traversing CBFS to find option roms?

I'm referring to the cost if CBFS can be sparse.  I'm also referring to the
number of scans required for some hardware.  My Opteron boxes have many
onboard devices, so there are 20+ CBFS scans.

> I did modify SeaBIOS so that option roms scans are much faster.  (The
> cost is now negligible.)  I accomplished this by ending the file scan
> if a signature of zeros is found.

That only works if CBFS files are contiguous.

> I don't think caching the list of files in the flash will work well -
> even one brute force scan will take too much time on large flash
> chips.  Instead, I think CBFS needs to have an orderly layout of files
> which doesn't require users to do a brute force scan.
> 
> I think there's a simple way to accomplish this - have cbfstool create
> "null" files that contain all the empty space.  Then the users of cbfs
> (eg, coreboot, seabios) wouldn't need any special code - they would
> skip them just like they skip over any other file.

I could see that working.  It was zero-fill in v3 lar.

Thanks,
Myles




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 04:07:27 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 04:07:27 +0200
Subject: [coreboot] [PATCH] flashrom: Fix SST25 status register routines
Message-ID: <4A00F0DF.9040201@gmx.net>

Improve SST25 status register routines:
- Using a 4-bit index into an array with 8 elements leads to
out-of-bounds accesses. That bug was introduced by a self-acked patch
from someone. Use proper bit masking to fix this.
- Factor out common SST25 status register printing.
- Use the common SST25 status register printing for SST25VF080B.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-SST25VF080B/spi.c
===================================================================
--- flashrom-SST25VF080B/spi.c	(Revision 464)
+++ flashrom-SST25VF080B/spi.c	(Arbeitskopie)
@@ -275,6 +275,15 @@
 	spi_prettyprint_status_register_common(status);
 }
 
+void spi_prettyprint_status_register_sst25(uint8_t status)
+{
+	printf_debug("Chip status register: Block Protect Write Disable "
+		     "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+	printf_debug("Chip status register: Auto Address Increment Programming "
+		     "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
+	spi_prettyprint_status_register_common(status);
+}
+
 /* Prettyprint the status register. Works for
  * SST 25VF016
  */
@@ -289,11 +298,7 @@
 		"100000H-1FFFFFH",
 		"all", "all"
 	};
-	printf_debug("Chip status register: Block Protect Write Disable "
-		     "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
-	printf_debug("Chip status register: Auto Address Increment Programming "
-		     "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
-	spi_prettyprint_status_register_common(status);
+	spi_prettyprint_status_register_sst25(status);
 	printf_debug("Resulting block protection : %s\n",
 		     bpt[(status & 0x1c) >> 2]);
 }
@@ -307,13 +312,9 @@
 		"0x40000-0x7ffff",
 		"all blocks", "all blocks", "all blocks", "all blocks"
 	};
-	printf_debug("Chip status register: Block Protect Write Disable "
-		"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
-	printf_debug("Chip status register: Auto Address Increment Programming "
-		"(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
-	spi_prettyprint_status_register_common(status);
+	spi_prettyprint_status_register_sst25(status);
 	printf_debug("Resulting block protection : %s\n",
-		bpt[(status & 0x3c) >> 2]);
+		bpt[(status & 0x1c) >> 2]);
 }
 
 void spi_prettyprint_status_register(struct flashchip *flash)
@@ -341,6 +342,9 @@
 		case 0x258d:
 			spi_prettyprint_status_register_sst25vf040b(status);
 			break;
+		case 0x258e:
+			spi_prettyprint_status_register_sst25(status);
+			break;
 		}
 		break;
 	}


-- 
http://www.hailfinger.org/

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From rminnich at gmail.com  Wed May  6 07:15:41 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 5 May 2009 22:15:41 -0700
Subject: [coreboot] CBFS transition plan
In-Reply-To: <20090506004459.GB32634@morn.localdomain>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>
	<20090506004459.GB32634@morn.localdomain>
Message-ID: <13426df10905052215n6ca0cb7aq8b5f2c6b9e54496b@mail.gmail.com>

On Tue, May 5, 2009 at 5:44 PM, Kevin O'Connor <kevin at koconnor.net> wrote:

> I think there's a simple way to accomplish this - have cbfstool create
> "null" files that contain all the empty space. ?Then the users of cbfs
> (eg, coreboot, seabios) wouldn't need any special code - they would
> skip them just like they skip over any other file.

yes, this is easy. A simple post-pass like I did with LAR, take all
empty segments and turn them into "null" files.

LZMA decoding -- cbfs will let us have several types of decoders
available, one being lzma. cbfs is not done, it's work in progress but
I do see real progress. Things are going to be pretty good in the next
few weeks.

ron



From patrick at georgi-clan.de  Wed May  6 10:17:19 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 06 May 2009 10:17:19 +0200
Subject: [coreboot] CBFS transition plan
In-Reply-To: <20090506001418.GA32634@morn.localdomain>
References: <2831fecf0905050813l1722c1dds249109ec09d66df9@mail.gmail.com>	<13426df10905050820q55c44c3byeb69aa098ee36f9c@mail.gmail.com>	<2831fecf0905050824w3e5d813aie964e830420a444@mail.gmail.com>	<4A0066B1.8060106@georgi-clan.de>
	<20090506001418.GA32634@morn.localdomain>
Message-ID: <4A01478F.2090902@georgi-clan.de>

Am 06.05.2009 02:14, schrieb Kevin O'Connor:
> What are your plans with lzma decoding?  (Will the bootblock have an
> lzma decoder for deploying coreboot_ram and will coreboot_ram have an
> lzma decoder for the payload?)
Yes.
Tests with coreboot_ram showed that lzma compressing it gains more (vs. 
nrv2b compressing) than the overhead of shipping the lzma decoder, so 
this is a net win.

>> Unless you really want to put the remaining fallback/normal code into
>> cbfs, in which case that work would be useless. I really like the idea
>> of using %cs, if it's known to be stable.
>
> SeaBIOS must deal with %cs modifications, so I'm familiar with using
> it.  However, it's not clear to me what coreboot needs it for.  Can
> someone point me to a discussion on the problems with PIE?
Short version: We can't rely on the compiler to do the right thing. We 
already run into problems every now and then because coreboot uses gcc 
(and binutils) in ways not intended by its developers - unix userland 
and linux kernel (and probably hurd) is what they seem to support.


Patrick



From stanne at gmail.com  Wed May  6 11:33:52 2009
From: stanne at gmail.com (Stan Yong)
Date: Wed, 6 May 2009 17:33:52 +0800
Subject: [coreboot] [flashrom] Transaction Error with opcode 0x03 failed...
Message-ID: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>

Hi all,

I'm having problems with the flashrom on my system. I'm trying to read out
the rom content from my machine which is a hp machine with ich9 controller
and Amtel AT26DF321 flash chip. However, the reading only halfway through
and error occur. Anyone encountered this? Can provide some advice on this?

Thanks.

Attached is the error output:

...sanity check
...outside the Asylum at 0/00/0
...OK
Decided to use Intel-conf1
Scanning bus 00 for devices...
Scanning bus 01 for devices...
Scanning bus 20 for devices...
Scanning bus 30 for devices...
Scanning bus 07 for devices...
Calibrating delay loop... 648M loops per second. ok
No coreboot table found.
Found chipset "Intel ICH9DO", enabling flash write...
BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
tried to set 0xdc to 0x3 (0x2) on Intel ICH9DO failed (WARNING ONLY)
Root Complex Register Block address = 0xfed1c000
GCS = 0xb60464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1
(SPI)
Top Swap : not enabled
SPIBAR = 0xfed1c000 + 0x3800
0x04: 0xe008 (HSFS)
FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0
0x50: 0x00001a1b (FRAP)
BMWAG 0, BMRAG 0, BRWA 26, BRRA 27
0x54: 0x00000000 (FREG0)
0x58: 0x03ff0240 (FREG1)
0x5C: 0x023f000b (FREG2)
0x60: 0x00020001 (FREG3)
0x64: 0x000a0003 (FREG4)
0x74: 0x83ff03f0 (PR0)
0x78: 0x00000000 (PR1)
0x7C: 0x00000000 (PR2)
0x80: 0x00000000 (PR3)
0x84: 0x00000000 (PR4)
0x90: 0x007f400c (SSFS, SSFC)
0x94: 0x0606     (PREOP)
0x96: 0xb6f0     (OPTYPE)
0x98: 0x0220059f (OPMENU)
0x9C: 0x03020103 (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xB0: 0x00000000 (FDOC)
WARNING: SPI Configuration Lockdown activated.
Generating OPCODES... generate_opcodes: Opcode = 9f
generate_opcodes: Opcode = 5
generate_opcodes: Opcode = 20
generate_opcodes: Opcode = 2
generate_opcodes: Opcode = 3
generate_opcodes: Opcode = 1
generate_opcodes: Opcode = 2
generate_opcodes: Opcode = 3
done
SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
Probing for Atmel AT26DF321, 4096 KB: base = ffc00000, sys_pasgesize = 4096,
pagesize = 4194304
BBAR: 0x0
RDID returned 1f 47 00.
probe_spi_rdid_generic: id1 0x1f, id2 0x4700
BBAR: 0x0
Chip status register is 10
Found chip "Atmel AT26DF321" (4096 KB) at physical address 0xffc00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom at coreboot.org if any of the above
operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Reading flash... ich_spi_read_page: offset=0, number=256, buf=01630020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=256, number=256, buf=01630120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=512, number=256, buf=01630220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=768, number=256, buf=01630320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=1024, number=256, buf=01630420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=1280, number=256, buf=01630520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=1536, number=256, buf=01630620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=1792, number=256, buf=01630720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=2048, number=256, buf=01630820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=2304, number=256, buf=01630920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=2560, number=256, buf=01630A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=2816, number=256, buf=01630B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=3072, number=256, buf=01630C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=3328, number=256, buf=01630D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=3584, number=256, buf=01630E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=3840, number=256, buf=01630F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=4096, number=256, buf=01631020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=4352, number=256, buf=01631120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=4608, number=256, buf=01631220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=4864, number=256, buf=01631320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=5120, number=256, buf=01631420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=5376, number=256, buf=01631520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=5632, number=256, buf=01631620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=5888, number=256, buf=01631720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=6144, number=256, buf=01631820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=6400, number=256, buf=01631920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=6656, number=256, buf=01631A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=6912, number=256, buf=01631B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=7168, number=256, buf=01631C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=7424, number=256, buf=01631D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=7680, number=256, buf=01631E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=7936, number=256, buf=01631F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=8192, number=256, buf=01632020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=8448, number=256, buf=01632120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=8704, number=256, buf=01632220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=8960, number=256, buf=01632320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=9216, number=256, buf=01632420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=9472, number=256, buf=01632520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=9728, number=256, buf=01632620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=9984, number=256, buf=01632720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=10240, number=256, buf=01632820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=10496, number=256, buf=01632920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=10752, number=256, buf=01632A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=11008, number=256, buf=01632B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=11264, number=256, buf=01632C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=11520, number=256, buf=01632D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=11776, number=256, buf=01632E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=12032, number=256, buf=01632F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=12288, number=256, buf=01633020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=12544, number=256, buf=01633120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=12800, number=256, buf=01633220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=13056, number=256, buf=01633320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=13312, number=256, buf=01633420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=13568, number=256, buf=01633520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=13824, number=256, buf=01633620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=14080, number=256, buf=01633720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=14336, number=256, buf=01633820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=14592, number=256, buf=01633920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=14848, number=256, buf=01633A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=15104, number=256, buf=01633B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=15360, number=256, buf=01633C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=15616, number=256, buf=01633D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=15872, number=256, buf=01633E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=16128, number=256, buf=01633F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=16384, number=256, buf=01634020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=16640, number=256, buf=01634120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=16896, number=256, buf=01634220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=17152, number=256, buf=01634320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=17408, number=256, buf=01634420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=17664, number=256, buf=01634520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=17920, number=256, buf=01634620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=18176, number=256, buf=01634720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=18432, number=256, buf=01634820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=18688, number=256, buf=01634920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=18944, number=256, buf=01634A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=19200, number=256, buf=01634B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=19456, number=256, buf=01634C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=19712, number=256, buf=01634D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=19968, number=256, buf=01634E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=20224, number=256, buf=01634F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=20480, number=256, buf=01635020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=20736, number=256, buf=01635120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=20992, number=256, buf=01635220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=21248, number=256, buf=01635320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=21504, number=256, buf=01635420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=21760, number=256, buf=01635520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=22016, number=256, buf=01635620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=22272, number=256, buf=01635720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=22528, number=256, buf=01635820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=22784, number=256, buf=01635920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=23040, number=256, buf=01635A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=23296, number=256, buf=01635B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=23552, number=256, buf=01635C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=23808, number=256, buf=01635D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=24064, number=256, buf=01635E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=24320, number=256, buf=01635F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=24576, number=256, buf=01636020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=24832, number=256, buf=01636120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=25088, number=256, buf=01636220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=25344, number=256, buf=01636320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=25600, number=256, buf=01636420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=25856, number=256, buf=01636520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=26112, number=256, buf=01636620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=26368, number=256, buf=01636720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=26624, number=256, buf=01636820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=26880, number=256, buf=01636920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=27136, number=256, buf=01636A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=27392, number=256, buf=01636B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=27648, number=256, buf=01636C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=27904, number=256, buf=01636D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=28160, number=256, buf=01636E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=28416, number=256, buf=01636F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=28672, number=256, buf=01637020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=28928, number=256, buf=01637120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=29184, number=256, buf=01637220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=29440, number=256, buf=01637320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=29696, number=256, buf=01637420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=29952, number=256, buf=01637520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=30208, number=256, buf=01637620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=30464, number=256, buf=01637720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=30720, number=256, buf=01637820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=30976, number=256, buf=01637920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=31232, number=256, buf=01637A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=31488, number=256, buf=01637B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=31744, number=256, buf=01637C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=32000, number=256, buf=01637D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=32256, number=256, buf=01637E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=32512, number=256, buf=01637F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=32768, number=256, buf=01638020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=33024, number=256, buf=01638120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=33280, number=256, buf=01638220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=33536, number=256, buf=01638320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=33792, number=256, buf=01638420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=34048, number=256, buf=01638520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=34304, number=256, buf=01638620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=34560, number=256, buf=01638720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=34816, number=256, buf=01638820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=35072, number=256, buf=01638920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=35328, number=256, buf=01638A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=35584, number=256, buf=01638B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=35840, number=256, buf=01638C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=36096, number=256, buf=01638D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=36352, number=256, buf=01638E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=36608, number=256, buf=01638F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=36864, number=256, buf=01639020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=37120, number=256, buf=01639120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=37376, number=256, buf=01639220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=37632, number=256, buf=01639320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=37888, number=256, buf=01639420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=38144, number=256, buf=01639520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=38400, number=256, buf=01639620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=38656, number=256, buf=01639720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=38912, number=256, buf=01639820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=39168, number=256, buf=01639920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=39424, number=256, buf=01639A20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=39680, number=256, buf=01639B20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=39936, number=256, buf=01639C20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=40192, number=256, buf=01639D20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=40448, number=256, buf=01639E20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=40704, number=256, buf=01639F20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=40960, number=256, buf=0163A020
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=41216, number=256, buf=0163A120
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=41472, number=256, buf=0163A220
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=41728, number=256, buf=0163A320
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=41984, number=256, buf=0163A420
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=42240, number=256, buf=0163A520
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=42496, number=256, buf=0163A620
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=42752, number=256, buf=0163A720
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=43008, number=256, buf=0163A820
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=43264, number=256, buf=0163A920
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=43520, number=256, buf=0163AA20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=43776, number=256, buf=0163AB20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=44032, number=256, buf=0163AC20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=44288, number=256, buf=0163AD20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=44544, number=256, buf=0163AE20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=44800, number=256, buf=0163AF20
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
BBAR: 0x0
ich_spi_read_page: offset=45056, number=256, buf=0163B020
BBAR: 0x0
Transaction error!
run OPCODE 0x03 failed
Error readingdone.
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From svn at coreboot.org  Wed May  6 15:38:56 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 15:38:56 +0200
Subject: [coreboot] [flashrom] r465 - trunk
Message-ID: <mailman.3169.1355071537.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-06 15:38:55 +0200 (Wed, 06 May 2009)
New Revision: 465

Modified:
   trunk/chipset_enable.c
Log:
Touch up some error messages in enable_flash_cs5536().

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-06 00:35:31 UTC (rev 464)
+++ trunk/chipset_enable.c	2009-05-06 13:38:55 UTC (rev 465)
@@ -512,13 +512,13 @@
 
 	fd_msr = open("/dev/cpu/0/msr", O_RDWR);
 	if (fd_msr == -1) {
-		perror("open msr");
+		perror("open(/dev/cpu/0/msr)");
+		printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
 		return -1;
 	}
 
 	if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
 		perror("lseek64");
-		printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
 		close(fd_msr);
 		return -1;
 	}




From peter at stuge.se  Wed May  6 15:39:18 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 15:39:18 +0200
Subject: [coreboot] [PATCH] chipset_enable: Fix open /dev/cpu
In-Reply-To: <4A00B9A2.5050803@gmx.net>
References: <20090505222205.73554045@jojo.scabb> <4A00B9A2.5050803@gmx.net>
Message-ID: <20090506133918.5991.qmail@stuge.se>

Bertrand, thanks for your patch! It is obviously needed.


Carl-Daniel Hailfinger wrote:
> Although the fix seems trivial, it breaks the code a few lines
> down.
> Please fix. Thanks.

Carl-Daniel, this is a really silly argument. Stop wasting people's
lives with such trivial things, adress it if you want to, commit,
send a thank you to the original poster, and move on!

r465


//Peter



From svn at coreboot.org  Wed May  6 15:43:26 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 15:43:26 +0200
Subject: [coreboot] [flashrom] r466 - trunk
Message-ID: <mailman.3170.1355071537.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-06 15:43:26 +0200 (Wed, 06 May 2009)
New Revision: 466

Modified:
   trunk/chipset_enable.c
Log:
Cleanup redundant condition and clarify message a little.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-06 13:38:55 UTC (rev 465)
+++ trunk/chipset_enable.c	2009-05-06 13:43:26 UTC (rev 466)
@@ -675,12 +675,11 @@
 		prot &= 0xfffffffc;
 		pci_write_byte(dev, reg, prot);
 		prot = pci_read_long(dev, reg);
-		if (prot & 0x3)
-			printf("SB600 still %s%sprotected from %u to %u\n",
-				(prot & 0x1) ? "write " : "",
-				(prot & 0x2) ? "read " : "",
-				(prot & 0xfffffc00),
-				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
+		printf("SB600 %s%sunprotect failed from %u to %u\n",
+			(prot & 0x1) ? "write " : "",
+			(prot & 0x2) ? "read " : "",
+			(prot & 0xfffffc00),
+			(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
 	}
 
 	/* Read SPI_BaseAddr */




From svn at coreboot.org  Wed May  6 15:51:45 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 15:51:45 +0200
Subject: [coreboot] [flashrom] r467 - trunk
Message-ID: <mailman.3171.1355071537.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-06 15:51:44 +0200 (Wed, 06 May 2009)
New Revision: 467

Modified:
   trunk/chipset_enable.c
Log:
Revert r466 because it introduced a bug:
If unprotect succeeded, it will print "SB600 unprotect failed".

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-06 13:43:26 UTC (rev 466)
+++ trunk/chipset_enable.c	2009-05-06 13:51:44 UTC (rev 467)
@@ -675,11 +675,12 @@
 		prot &= 0xfffffffc;
 		pci_write_byte(dev, reg, prot);
 		prot = pci_read_long(dev, reg);
-		printf("SB600 %s%sunprotect failed from %u to %u\n",
-			(prot & 0x1) ? "write " : "",
-			(prot & 0x2) ? "read " : "",
-			(prot & 0xfffffc00),
-			(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
+		if (prot & 0x3)
+			printf("SB600 still %s%sprotected from %u to %u\n",
+				(prot & 0x1) ? "write " : "",
+				(prot & 0x2) ? "read " : "",
+				(prot & 0xfffffc00),
+				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
 	}
 
 	/* Read SPI_BaseAddr */




From peter at stuge.se  Wed May  6 15:52:11 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 15:52:11 +0200
Subject: [coreboot] [PATCH] flashrom: Fix SST25 status register routines
In-Reply-To: <4A00F0DF.9040201@gmx.net>
References: <4A00F0DF.9040201@gmx.net>
Message-ID: <20090506135211.9668.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> Improve SST25 status register routines:
> - Using a 4-bit index into an array with 8 elements leads to
> out-of-bounds accesses. That bug was introduced by a self-acked patch
> from someone. Use proper bit masking to fix this.

I think it's pointless to write "it was introduced by self-ack" at
all if you do not also write who it was. Either go all the way and
actually blame someone because you think it's a big deal or don't
bother because it's just about _one bit_. It takes more effort to
read the english text than to go with the patch.

My point; Some bugs warrant discussion, others maybe not as much.


> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Wed May  6 15:59:44 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 15:59:44 +0200
Subject: [coreboot] [flashrom] r468 - trunk
Message-ID: <mailman.3172.1355071537.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-06 15:59:44 +0200 (Wed, 06 May 2009)
New Revision: 468

Modified:
   trunk/spi.c
Log:
Improve SST25 status register routines:
- Using a 4-bit index into an array with 8 elements leads to
out-of-bounds accesses. Use proper bit masking to fix this.
- Factor out common SST25 status register printing.
- Use the common SST25 status register printing for SST25VF080B.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/spi.c
===================================================================
--- trunk/spi.c	2009-05-06 13:51:44 UTC (rev 467)
+++ trunk/spi.c	2009-05-06 13:59:44 UTC (rev 468)
@@ -275,6 +275,15 @@
 	spi_prettyprint_status_register_common(status);
 }
 
+void spi_prettyprint_status_register_sst25(uint8_t status)
+{
+	printf_debug("Chip status register: Block Protect Write Disable "
+		     "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+	printf_debug("Chip status register: Auto Address Increment Programming "
+		     "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
+	spi_prettyprint_status_register_common(status);
+}
+
 /* Prettyprint the status register. Works for
  * SST 25VF016
  */
@@ -289,11 +298,7 @@
 		"100000H-1FFFFFH",
 		"all", "all"
 	};
-	printf_debug("Chip status register: Block Protect Write Disable "
-		     "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
-	printf_debug("Chip status register: Auto Address Increment Programming "
-		     "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
-	spi_prettyprint_status_register_common(status);
+	spi_prettyprint_status_register_sst25(status);
 	printf_debug("Resulting block protection : %s\n",
 		     bpt[(status & 0x1c) >> 2]);
 }
@@ -307,13 +312,9 @@
 		"0x40000-0x7ffff",
 		"all blocks", "all blocks", "all blocks", "all blocks"
 	};
-	printf_debug("Chip status register: Block Protect Write Disable "
-		"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
-	printf_debug("Chip status register: Auto Address Increment Programming "
-		"(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
-	spi_prettyprint_status_register_common(status);
+	spi_prettyprint_status_register_sst25(status);
 	printf_debug("Resulting block protection : %s\n",
-		bpt[(status & 0x3c) >> 2]);
+		bpt[(status & 0x1c) >> 2]);
 }
 
 void spi_prettyprint_status_register(struct flashchip *flash)
@@ -341,6 +342,9 @@
 		case 0x258d:
 			spi_prettyprint_status_register_sst25vf040b(status);
 			break;
+		case 0x258e:
+			spi_prettyprint_status_register_sst25(status);
+			break;
 		}
 		break;
 	}




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 16:02:14 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 16:02:14 +0200
Subject: [coreboot] [PATCH] flashrom: Fix SST25 status register routines
In-Reply-To: <20090506135211.9668.qmail@stuge.se>
References: <4A00F0DF.9040201@gmx.net> <20090506135211.9668.qmail@stuge.se>
Message-ID: <4A019866.3000906@gmx.net>

On 06.05.2009 15:52, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> Improve SST25 status register routines:
>> - Using a 4-bit index into an array with 8 elements leads to
>> out-of-bounds accesses. That bug was introduced by a self-acked patch
>> from someone. Use proper bit masking to fix this.
>>     
>
> I think it's pointless to write "it was introduced by self-ack" at
> all if you do not also write who it was. Either go all the way and
> actually blame someone because you think it's a big deal or don't
> bother because it's just about _one bit_.

It's one bit which can cause segfaults. I know who did it (svn blame
helps), but I will NOT mention names in public. That would be bad style.


> It takes more effort to
> read the english text than to go with the patch.
>
> My point; Some bugs warrant discussion, others maybe not as much.
>   

Anyway, I removed the part about the self-ack from the changelog.


>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>>     
>
> Acked-by: Peter Stuge <peter at stuge.se>
>   

Thanks, r468.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 16:04:02 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 16:04:02 +0200
Subject: [coreboot] [flashrom] r467 - trunk
In-Reply-To: <20090506135223.10810gmx1@mx057.gmx.net>
References: <20090506135223.10810gmx1@mx057.gmx.net>
Message-ID: <4A0198D2.1040200@gmx.net>

Just in case someone wants a more detailed explanation:
prot is read again after the first if (prot & 0x3) and may have changed,
so the second if (prot & 0x3) is not redundant.

Regards,
Carl-Daniel

On 06.05.2009 15:51, svn at coreboot.org wrote:
> Author: hailfinger
> Date: 2009-05-06 15:51:44 +0200 (Wed, 06 May 2009)
> New Revision: 467
>
> Modified:
>    trunk/chipset_enable.c
> Log:
> Revert r466 because it introduced a bug:
> If unprotect succeeded, it will print "SB600 unprotect failed".
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
>
> Modified: trunk/chipset_enable.c
> ===================================================================
> --- trunk/chipset_enable.c	2009-05-06 13:43:26 UTC (rev 466)
> +++ trunk/chipset_enable.c	2009-05-06 13:51:44 UTC (rev 467)
> @@ -675,11 +675,12 @@
>  		prot &= 0xfffffffc;
>  		pci_write_byte(dev, reg, prot);
>  		prot = pci_read_long(dev, reg);
> -		printf("SB600 %s%sunprotect failed from %u to %u\n",
> -			(prot & 0x1) ? "write " : "",
> -			(prot & 0x2) ? "read " : "",
> -			(prot & 0xfffffc00),
> -			(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
> +		if (prot & 0x3)
> +			printf("SB600 still %s%sprotected from %u to %u\n",
> +				(prot & 0x1) ? "write " : "",
> +				(prot & 0x2) ? "read " : "",
> +				(prot & 0xfffffc00),
> +				(prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
>  	}
>  
>  	/* Read SPI_BaseAddr */
>
>
>   


-- 
http://www.hailfinger.org/




From ldorileo at gmail.com  Wed May  6 16:05:34 2009
From: ldorileo at gmail.com (Leandro Dorileo)
Date: Wed, 6 May 2009 10:05:34 -0400
Subject: [coreboot] GSoC: Seabios USB Option ROM, small initial planning
Message-ID: <d68f80d90905060705v109a09bag1e9363084f5032b@mail.gmail.com>

Hi Guys

I was talking to Jason and we found we need to draw a bit better the
API and responsibilities between us. I figure out I`m going to support
hardware detection and initialization, and a framework to read and
write blocks from MSC devices.

Looking the current libpayload`s source code I found UHCI is pretty
complete and meets the requirements I mentioned above. So, the focus
should be put on EHCI and OHCI. Of course bug fixing what becomes
needed as well.

Again looking in the source code, I found abstractions that will ease
the process of coupling the other host controller interface drivers, I
don`t have many questions regarding the internal design and API of
libpayload(by now at least) but how Jason is going to integrate and
use libpayload usb stack.

To test and improve my understanding I put together[1] some code from
FILO, libpayload and a stub option ROM, just to see how it`s supposed
to be integrate(PS: this option ROM is a work in progress and will be
used just for testing the usb implementations I`m going to do, and
it`s not functional yet).

For now, I have two major questions, #1: I`ve seen other projects like
FILO including libpayload with svn:external, once seabios is
maintained with git, how it should be done with seabios? how would we
manage the source code integration and maintainability between seabios
and libpayload?. #2: libpayload uses kbuild/kconfig but seabios
doesn`t, what would be the best approach to integrate their build
system? (PS: Sorry, it wasn`t two questions, but many questions and
two areas. ;-) )

A third questions would be, how people test the libpayload stuffs? do
they write small payloads for that? is that feasible writing an option
ROM for testing the libpayload`s usb stack?

A last question. Should I CC the mentors and people I judge
interested? or, is coreboot at coreboot.org good enough? ;-)

[1] - http://vps.dorilex.net/cgi-bin/gitweb.cgi

Thanks in advance....

-- 
(?=   Leandro Dorileo
//\    ldorileo at gmail.com   -   http://www.dorilex.net
V_/  Software is a matter of freedom.



From peter at stuge.se  Wed May  6 16:33:23 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 16:33:23 +0200
Subject: [coreboot] [PATCH] flashrom: Fix SST25 status register routines
In-Reply-To: <4A019866.3000906@gmx.net>
References: <4A00F0DF.9040201@gmx.net> <20090506135211.9668.qmail@stuge.se>
	<4A019866.3000906@gmx.net>
Message-ID: <20090506143323.23526.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> > I think it's pointless to write "it was introduced by self-ack" at
> > all if you do not also write who it was. Either go all the way and
> > actually blame someone because you think it's a big deal or don't
> > bother because it's just about _one bit_.
> 
> It's one bit which can cause segfaults. I know who did it (svn
> blame helps), but I will NOT mention names in public. That would be
> bad style.

I don't think it's bad style at all! There is zero drama. This is
just a piece of software we're working on together. I make bugs too.

Either the bug is important enough to tease someone a little, or it's
not. The information is easily available from svn blame as you
mentioned so it's not like you would be letting out a secret.


> > My point; Some bugs warrant discussion, others maybe not as much.
> 
> Anyway, I removed the part about the self-ack from the changelog.

Ok, but I think it would be fine for you to mention who caused it as
well, if you felt the need to.

And you could include the original rev. Or not.

Whatever is easiest and feels good. :)


> Thanks, r468.

Goodie!


//Peter



From peter at stuge.se  Wed May  6 16:36:24 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 16:36:24 +0200
Subject: [coreboot] [flashrom] r467 - trunk
Message-ID: <20090506143624.24635.qmail@stuge.se>

svn at coreboot.org wrote:
> +		if (prot & 0x3)

Yes of course! Silly me. Thanks for fixing!


> +			printf("SB600 still %s%sprotected from %u to %u\n",

How about the wording though? Without -V, using "still" is not so
great. I realize the old prot value needs to be saved to actually say
anything about what failed. Makes sense?


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Wed May  6 16:56:33 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 06 May 2009 16:56:33 +0200
Subject: [coreboot] [flashrom] r467 - trunk
In-Reply-To: <20090506143624.24635.qmail@stuge.se>
References: <20090506143624.24635.qmail@stuge.se>
Message-ID: <4A01A521.9030209@gmx.net>

On 06.05.2009 16:36, Peter Stuge wrote:
> svn at coreboot.org wrote:
>   
>> +		if (prot & 0x3)
>>     
>
> Yes of course! Silly me. Thanks for fixing!
>   

No problem. To err is human.


>> +			printf("SB600 still %s%sprotected from %u to %u\n",
>>     
>
> How about the wording though? Without -V, using "still" is not so
> great. I realize the old prot value needs to be saved to actually say
> anything about what failed. Makes sense?
>   

Hm. Since every bit which is still set is a "failed" bit, the original
value doesn't need to be saved.

Your message in r466 makes sense. Simply changing the current message
text and leaving everything else as-is should work.

printf("SB600 %s%sunprotect failed from %u to %u\n"


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Wed May  6 17:05:39 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 17:05:39 +0200
Subject: [coreboot] [flashrom] r469 - trunk
Message-ID: <mailman.3173.1355071537.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-05-06 17:05:39 +0200 (Wed, 06 May 2009)
New Revision: 469

Modified:
   trunk/chipset_enable.c
Log:
Clarify error message in enable_flash_sb600() a little.

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/chipset_enable.c
===================================================================
--- trunk/chipset_enable.c	2009-05-06 13:59:44 UTC (rev 468)
+++ trunk/chipset_enable.c	2009-05-06 15:05:39 UTC (rev 469)
@@ -676,7 +676,7 @@
 		pci_write_byte(dev, reg, prot);
 		prot = pci_read_long(dev, reg);
 		if (prot & 0x3)
-			printf("SB600 still %s%sprotected from %u to %u\n",
+			printf("SB600 %s%sunprotect failed from %u to %u\n",
 				(prot & 0x1) ? "write " : "",
 				(prot & 0x2) ? "read " : "",
 				(prot & 0xfffffc00),




From peter at stuge.se  Wed May  6 17:05:57 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 17:05:57 +0200
Subject: [coreboot] [flashrom] r467 - trunk
In-Reply-To: <4A01A521.9030209@gmx.net>
References: <20090506143624.24635.qmail@stuge.se> <4A01A521.9030209@gmx.net>
Message-ID: <20090506150557.483.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> printf("SB600 %s%sunprotect failed from %u to %u\n"

Let's try r469.


//Peter



From joelr at tyan.com  Wed May  6 17:34:13 2009
From: joelr at tyan.com (joelr at tyan.com)
Date: Wed, 6 May 2009 08:34:13 -0700
Subject: [coreboot] [flashrom] RE:  Tyan Product Listings
References: <62331AE06C95A144869EEB7EB2F8BE675CC3BA@MUSAEXVS01.mitacad.com>
	<200808271415.m7REFAf0015817@hyspamsql01.mic.com.tw>
	<62331AE06C95A144869EEB7EB2F8BE675CC4A5@MUSAEXVS01.mitacad.com>
	<48C1C23A.9010709@gmx.net> 
Message-ID: <9576AE3268355A4D8C0F16C700ADEA861C4E6C@MUSAEXVS02.mitacad.com>

Charles,

We have successfully tested both the 32-bit and 64-bit FlashROM utility on the S5397 motherboard and found it 100% compatible.  Can we have the S5397 motherboard added to the compatibility listings?

Thanks,

Joel Robertson
Tech Support Manager
Customer Service Manager
Vendor Relations Manager
TYAN Computer Corporation 
joelr at tyan.com
(510)?651-8868 ext. 5196





From fengyuning1984 at gmail.com  Wed May  6 17:41:17 2009
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Wed, 6 May 2009 23:41:17 +0800
Subject: [coreboot] [flashrom] Transaction Error with opcode 0x03
	failed...
In-Reply-To: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
References: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
Message-ID: <a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>

Stan Yong wrote:
> I'm having problems with the flashrom on my system. ...
> Can provide some advice on this?

I can only tell the reason. Your current BIOS prevents flashrom from
reading certain part of the flash chip. I don't know if there is any
way to bypass that setting.

If you are interested in further explanation on the flashrom output,
please read on.

> ich_spi_read_page: offset=45056, number=256, buf=0163B020
> BBAR: 0x0
> Transaction error!
> run OPCODE 0x03 failed
> Error readingdone.

Error occurs here, when flashrom tries to read data at offset 45056
from the flash chip. 45056(dec) = b000(hex).

Look at FREG2.
> 0x5C: 0x023f000b (FREG2)
The value 0x0(23f)0(00b) means, the area in the flash chip from
0x00(00b)000 to 0x00(23f)fff belongs to (F)lash (REG)ion (2), which
stores data for the "Management Engine". That is, flashrom runs into
error when it is trying to read FREG2.

Now look at FRAP.
> 0x50: 0x00001a1b (FRAP)
The least significant byte '1b' indicates which regions software can
read. Expand it to binary, 00011011. That means the software can read
FREG0, FREG1, FREG3 and FREG4 but not FREG2. That is why flashrom runs
into error at offset 45056.

yu ning



From peter at stuge.se  Wed May  6 17:45:44 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 17:45:44 +0200
Subject: [coreboot] [flashrom] RE:  Tyan Product Listings
In-Reply-To: <9576AE3268355A4D8C0F16C700ADEA861C4E6C@MUSAEXVS02.mitacad.com>
References: <62331AE06C95A144869EEB7EB2F8BE675CC3BA@MUSAEXVS01.mitacad.com>
	<200808271415.m7REFAf0015817@hyspamsql01.mic.com.tw>
	<62331AE06C95A144869EEB7EB2F8BE675CC4A5@MUSAEXVS01.mitacad.com>
	<48C1C23A.9010709@gmx.net>
	<9576AE3268355A4D8C0F16C700ADEA861C4E6C@MUSAEXVS02.mitacad.com>
Message-ID: <20090506154544.10791.qmail@stuge.se>

Hi Joel,

joelr at tyan.com wrote:
> We have successfully tested both the 32-bit and 64-bit FlashROM
> utility on the S5397 motherboard and found it 100% compatible.

Great!


> Can we have the S5397 motherboard added to the compatibility
> listings?

The list which is included in the utility itself (flashrom -L) only
includes those mainboards which need a special board enable code
sequence, but I've added S5397 to http://coreboot.org/Flashrom now.

Thanks for the report!


//Peter



From peter at stuge.se  Wed May  6 17:47:46 2009
From: peter at stuge.se (Peter Stuge)
Date: Wed, 6 May 2009 17:47:46 +0200
Subject: [coreboot] [flashrom] Transaction Error with opcode
	0x03	failed...
In-Reply-To: <a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
References: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
	<a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
Message-ID: <20090506154746.11384.qmail@stuge.se>

FENG Yu Ning wrote:
> Look at FREG2.
> Now look at FRAP.

Thanks a lot for those great explanations!

It might be nice to check this in the code as well.


//Peter



From svn at coreboot.org  Wed May  6 18:34:53 2009
From: svn at coreboot.org (coreboot)
Date: Wed, 06 May 2009 16:34:53 -0000
Subject: [coreboot] #131: New flashrom motherboard support
In-Reply-To: <045.fafa58fccf6f1868f71243ff245dc850@coreboot.org>
References: <045.fafa58fccf6f1868f71243ff245dc850@coreboot.org>
Message-ID: <054.618c124ff26759448d5dbd13e5914bb3@coreboot.org>

#131: New flashrom motherboard support
---------------------------------+------------------------------------------
   Reporter:  anonymous          |          Owner:  somebody        
       Type:  enhancement        |         Status:  new             
   Priority:  trivial            |      Milestone:  Going mainstream
  Component:  flashrom           |        Version:  v2              
   Keywords:  flashrom asus      |   Dependencies:                  
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by FrafPaguera):

 http://www.ambrosiasw.com/forums/index.php?showuser=43709 cialis order
 online,   71230,

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131#comment:1>
coreboot <http://www.coreboot.org/>


From avg at icyb.net.ua  Wed May  6 18:51:02 2009
From: avg at icyb.net.ua (Andriy Gapon)
Date: Wed, 06 May 2009 19:51:02 +0300
Subject: [coreboot] [flashrom] Transaction Error with opcode 0x03
	failed...
In-Reply-To: <a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
References: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
	<a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
Message-ID: <4A01BFF6.4000203@icyb.net.ua>

on 06/05/2009 18:41 FENG Yu Ning said the following:
> Look at FREG2.
>> 0x5C: 0x023f000b (FREG2)
> The value 0x0(23f)0(00b) means, the area in the flash chip from
> 0x00(00b)000 to 0x00(23f)fff belongs to (F)lash (REG)ion (2), which
> stores data for the "Management Engine". That is, flashrom runs into
> error when it is trying to read FREG2.
> 
> Now look at FRAP.
>> 0x50: 0x00001a1b (FRAP)
> The least significant byte '1b' indicates which regions software can
> read. Expand it to binary, 00011011. That means the software can read
> FREG0, FREG1, FREG3 and FREG4 but not FREG2. That is why flashrom runs
> into error at offset 45056.

Yu Ning, thank you for the very enlightening explanation!
I wonder what the following means (on my machine):
0x54: 0x00000000 (FREG0)

Flash region of size 0?
BTW:
0x50: 0x00000a0b (FRAP)

-- 
Andriy Gapon



From nadalizadeh at gmail.com  Wed May  6 18:52:21 2009
From: nadalizadeh at gmail.com (Ali Nadalizadeh)
Date: Wed, 6 May 2009 21:22:21 +0430
Subject: [coreboot] Failed flash, flashrom emergency help needed on ICH7
Message-ID: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>

I tried the latest svn version (6 May 09) of flashrom and unlike older
versions
didn't get a warning on my chipset. flashrom reads my chip successfully and
outputs a fine Phoenix bios. After writing a new image into the chip
I found that writer is not fully functional and reading the chip again
results in an image that is neither original one nor the new image.
then I tried erase functionality and it resulted in some 0xFF and some
unchanged bytes
in the chip. Currently writing either images doesn't change the chip
and it remains in mostly 0xFF bytes.

Here are the flashrom detection info :

ali at Velocity:~/tmp/f$ sudo ./flashrom/flashrom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH7M", enabling flash write... OK.
Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000.
No operations were specified.

verbose output at http://coreboot.pastebin.com/m604f01b6

history of my commands : http://coreboot.pastebin.com/m5c3c2372

Original Rom : http://filebin.ca/mhtqhm/mybios.rom

lspci -vv output attached.

I try to keep my Lenovo 3000 up and running and waiting for helps. :)

I'm also online on #coreboot as nadalizadeh

Thanks
Ali Nadalizadeh
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00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub (rev 03)
	Subsystem: Lenovo Device 2082
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel driver in use: agpgart-intel
	Kernel modules: intel-agp

00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)
	Subsystem: Lenovo Device 2083
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at d8100000 (32-bit, non-prefetchable) [size=512K]
	Region 1: I/O ports at 1800 [size=8]
	Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M]
	Region 3: Memory at d8200000 (32-bit, non-prefetchable) [size=256K]
	Capabilities: <access denied>
	Kernel modules: intelfb

00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller (rev 03)
	Subsystem: Lenovo Device 2083
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Region 0: Memory at d8180000 (32-bit, non-prefetchable) [size=512K]
	Capabilities: <access denied>

00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 02)
	Subsystem: Lenovo Device 2085
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 22
	Region 0: Memory at d8240000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: <access denied>
	Kernel driver in use: HDA Intel
	Kernel modules: snd-hda-intel

00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=02, subordinate=03, sec-latency=0
	I/O behind bridge: 00002000-00002fff
	Memory behind bridge: d4000000-d5ffffff
	Prefetchable memory behind bridge: 00000000d0000000-00000000d1ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport-driver
	Kernel modules: shpchp

00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=04, subordinate=05, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: d6000000-d7ffffff
	Prefetchable memory behind bridge: 00000000d2000000-00000000d3ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport-driver
	Kernel modules: shpchp

00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 02)
	Subsystem: Lenovo Device 208a
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 4: I/O ports at 1820 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 02)
	Subsystem: Lenovo Device 208b
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 1840 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 02)
	Subsystem: Lenovo Device 208c
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at 1860 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 02)
	Subsystem: Lenovo Device 208d
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin D routed to IRQ 16
	Region 4: I/O ports at 1880 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 02) (prog-if 20)
	Subsystem: Lenovo Device 208e
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 0: Memory at d8444000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2) (prog-if 01)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=32
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: d8000000-d80fffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>

00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge (rev 02)
	Subsystem: Lenovo Device 2090
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: <access denied>
	Kernel modules: iTCO_wdt, intel-rng

00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 02) (prog-if 8a [Master SecP PriP])
	Subsystem: Lenovo Device 209b
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 0: I/O ports at 01f0 [size=8]
	Region 1: I/O ports at 03f4 [size=1]
	Region 2: I/O ports at 0170 [size=8]
	Region 3: I/O ports at 0374 [size=1]
	Region 4: I/O ports at 1810 [size=16]
	Kernel driver in use: ata_piix

00:1f.2 SATA controller: Intel Corporation 82801GBM/GHM (ICH7 Family) SATA AHCI Controller (rev 02) (prog-if 01)
	Subsystem: Lenovo Device 2091
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 26
	Region 0: I/O ports at 18d0 [size=8]
	Region 1: I/O ports at 18c4 [size=4]
	Region 2: I/O ports at 18c8 [size=8]
	Region 3: I/O ports at 18c0 [size=4]
	Region 4: I/O ports at 18b0 [size=16]
	Region 5: Memory at d8444400 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ahci

00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02)
	Subsystem: Lenovo Device 2092
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 10
	Region 4: I/O ports at 18e0 [size=32]
	Kernel modules: i2c-i801

04:00.0 Network controller: Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection (rev 02)
	Subsystem: Intel Corporation Device 1011
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 27
	Region 0: Memory at d6000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <access denied>
	Kernel driver in use: iwl3945
	Kernel modules: iwl3945

0a:01.0 FireWire (IEEE 1394): Ricoh Co Ltd R5C832 IEEE 1394 Controller (prog-if 10)
	Subsystem: Lenovo Device 2094
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32 (500ns min, 1000ns max)
	Interrupt: pin A routed to IRQ 22
	Region 0: Memory at d8000000 (32-bit, non-prefetchable) [size=2K]
	Capabilities: <access denied>
	Kernel driver in use: ohci1394
	Kernel modules: firewire-ohci, ohci1394

0a:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 19)
	Subsystem: Lenovo Device 2095
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32
	Interrupt: pin B routed to IRQ 22
	Region 0: Memory at d8000800 (32-bit, non-prefetchable) [size=256]
	Capabilities: <access denied>
	Kernel driver in use: sdhci-pci
	Kernel modules: sdhci-pci

0a:01.2 System peripheral: Ricoh Co Ltd R5C843 MMC Host Controller (rev 0a)
	Subsystem: Lenovo Device 2097
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 255
	Region 0: [virtual] Memory at d8000c00 (32-bit, non-prefetchable) [disabled] [size=256]
	Capabilities: <access denied>
	Kernel driver in use: ricoh-mmc
	Kernel modules: ricoh_mmc

0a:01.3 System peripheral: Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter (rev 05)
	Subsystem: Lenovo Device 2098
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 255
	Region 0: Memory at d8001000 (32-bit, non-prefetchable) [size=256]
	Capabilities: <access denied>

0a:01.4 System peripheral: Ricoh Co Ltd xD-Picture Card Controller (rev ff) (prog-if ff)
	!!! Unknown header type 7f

0a:07.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Lenovo Device 2093
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 20
	Region 0: I/O ports at 4000 [size=256]
	Region 1: Memory at d8001800 (32-bit, non-prefetchable) [size=256]
	Capabilities: <access denied>
	Kernel driver in use: 8139too
	Kernel modules: 8139too, 8139cp


From r.marek at assembler.cz  Wed May  6 21:51:02 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 06 May 2009 21:51:02 +0200
Subject: [coreboot] Failed flash, flashrom emergency help needed on ICH7
In-Reply-To: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>
Message-ID: <4A01EA26.3000701@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hmm I checked the orig bios image for any special handling and there is none.
Even it seems that EC has its own flash somewhere else. (this is good)

Perhaps there are some locks in chip itself? Any expert here on that?
Can we read the status reg from the chip? The WP# of the chip seems just to
enable/disable modifications to the to the BP bits.

I suspect the part flashing does not work well. There seems to  be no obstacles
elsewhere.

Can you post here lspci -xxx

Rudolf

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From svn at coreboot.org  Wed May  6 23:54:22 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  6 May 2009 23:54:22 +0200
Subject: [coreboot] [flashrom] r470 - trunk
Message-ID: <mailman.3174.1355071537.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-06 23:54:22 +0200 (Wed, 06 May 2009)
New Revision: 470

Modified:
   trunk/flash.h
Log:
ASD chips may exist, but all available docs suggest they are just
rebranded Winbond chips with Winbond IDs.
The ASD vendor/chip IDs in flash.h are very likely just misinterpreted
LHA headers.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/flash.h
===================================================================
--- trunk/flash.h	2009-05-06 15:05:39 UTC (rev 469)
+++ trunk/flash.h	2009-05-06 21:54:22 UTC (rev 470)
@@ -186,6 +186,7 @@
 #define AMIC_A29040B		0x86
 #define AMIC_A49LF040A		0x9d
 
+/* This chip vendor/device ID is probably a misinterpreted LHA header. */
 #define ASD_ID			0x25	/* ASD, not listed in JEP106W */
 #define ASD_AE49F2008		0x52
 




From svn at coreboot.org  Wed May  6 23:59:11 2009
From: svn at coreboot.org (coreboot)
Date: Wed, 06 May 2009 21:59:11 -0000
Subject: [coreboot]  #132: Add version number to flashrom output
Message-ID: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>

#132: Add version number to flashrom output
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  somebody
       Type:  defect             |         Status:  new     
   Priority:  major              |      Milestone:          
  Component:  flashrom           |        Version:          
   Keywords:  ui debug info      |   Dependencies:          
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
 Asking users if they are really running the last version gets old really
 fast.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/132>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Thu May  7 00:07:57 2009
From: svn at coreboot.org (coreboot)
Date: Wed, 06 May 2009 22:07:57 -0000
Subject: [coreboot] #132: Add version number to flashrom output
In-Reply-To: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
References: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
Message-ID: <050.c418e6a0aef78b08a894fe9ca1880650@coreboot.org>

#132: Add version number to flashrom output
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  hailfinger
       Type:  defect             |         Status:  assigned  
   Priority:  major              |      Milestone:            
  Component:  flashrom           |        Version:            
   Keywords:  ui debug info      |   Dependencies:            
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------
Changes (by hailfinger):

  * owner:  somebody => hailfinger
  * status:  new => assigned


Comment:

 Do you want --version output for every startup even in non-verbose mode? I
 can create a patch for that.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/132#comment:1>
coreboot <http://www.coreboot.org/>


From c-d.hailfinger.devel.2006 at gmx.net  Thu May  7 00:16:26 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 07 May 2009 00:16:26 +0200
Subject: [coreboot] [PATCH] flashrom: Detect non-ID responses
Message-ID: <4A020C3A.4010308@gmx.net>

When flashrom JEDEC code sends the ID command to the chip, it expects to
see IDs in the default flash location. However, sometimes the chip does
not react to the ID command, either because it doesn't understand the
command or because the command never reached it.
One way to detect this is to compare ID output with flash chip contents
for the same location. If they are identical, there is a high chance
you're not actually seeing ID output. Warn the user in that case.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-real-jedec-id/jedec.c
===================================================================
--- flashrom-real-jedec-id/jedec.c	(Revision 470)
+++ flashrom-real-jedec-id/jedec.c	(Arbeitskopie)
@@ -92,6 +92,7 @@
 	volatile uint8_t *bios = flash->virtual_memory;
 	uint8_t id1, id2;
 	uint32_t largeid1, largeid2;
+	uint32_t flashcontent1, flashcontent2;
 
 	/* Issue JEDEC Product ID Entry command */
 	chip_writeb(0xAA, bios + 0x5555);
@@ -133,6 +134,26 @@
 	printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2);
 	if (!oddparity(id1))
 		printf_debug(", id1 parity violation");
+
+	/* Read the product ID location again. We should now see normal flash contents. */
+	flashcontent1 = chip_readb(bios);
+	flashcontent2 = chip_readb(bios + 0x01);
+
+	/* Check if it is a continuation ID, this should be a while loop. */
+	if (flashcontent1 == 0x7F) {
+		flashcontent1 <<= 8;
+		flashcontent1 |= chip_readb(bios + 0x100);
+	}
+	if (flashcontent2 == 0x7F) {
+		flashcontent2 <<= 8;
+		flashcontent2 |= chip_readb(bios + 0x101);
+	}
+
+	if (largeid1 == flashcontent1)
+		printf_debug(", id1 is normal flash content");
+	if (largeid2 == flashcontent2)
+		printf_debug(", id2 is normal flash content");
+
 	printf_debug("\n");
 	if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id)
 		return 1;


-- 
http://www.hailfinger.org/

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From c-d.hailfinger.devel.2006 at gmx.net  Thu May  7 00:29:15 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 07 May 2009 00:29:15 +0200
Subject: [coreboot] [PATCH] flashrom: Detect non-ID responses
In-Reply-To: <4A020C3A.4010308@gmx.net>
References: <4A020C3A.4010308@gmx.net>
Message-ID: <4A020F3B.2090604@gmx.net>

On 07.05.2009 00:16, Carl-Daniel Hailfinger wrote:
> When flashrom JEDEC code sends the ID command to the chip, it expects to
> see IDs in the default flash location. However, sometimes the chip does
> not react to the ID command, either because it doesn't understand the
> command or because the command never reached it.
> One way to detect this is to compare ID output with flash chip contents
> for the same location. If they are identical, there is a high chance
> you're not actually seeing ID output. Warn the user in that case.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Idwer Vollering tested the patch and it triggers each time the ID isn't
a real ID. Thanks!

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From svn at coreboot.org  Thu May  7 02:03:18 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  7 May 2009 02:03:18 +0200
Subject: [coreboot] [v2] r4255 - trunk/util/superiotool
Message-ID: <mailman.3175.1355071537.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-05-07 02:03:18 +0200 (Thu, 07 May 2009)
New Revision: 4255

Modified:
   trunk/util/superiotool/smsc.c
Log:
Support for detecting the SMSC FDC37N869 (trivial).

No datasheet available, chip identified by probing and looking at the PCB.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/smsc.c
===================================================================
--- trunk/util/superiotool/smsc.c	2009-05-05 14:06:20 UTC (rev 4254)
+++ trunk/util/superiotool/smsc.c	2009-05-07 00:03:18 UTC (rev 4255)
@@ -531,10 +531,8 @@
 		{EOT}}},
 	{0x79, "SCH5504", {	/* From sensors-detect (no datasheet) */
 		{EOT}}},
-#if 0
-	{0x7a, "Unknown", {	/* Found in Toshiba Satellite A80-117. */
+	{0x7a, "FDC37N869", {	/* Found in Toshiba Satellite A80-117. */
 		{EOT}}},
-#endif
 	{0x7c, "SCH3112", {
 		{EOT}}},
 	{0x7d, "SCH3114", {




From c-d.hailfinger.devel.2006 at gmx.net  Thu May  7 02:05:20 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 07 May 2009 02:05:20 +0200
Subject: [coreboot] [PATCH] flashrom: Group probe function together with
 associated IDs
In-Reply-To: <49EE56C8.20403@gmx.net>
References: <49EE56C8.20403@gmx.net>
Message-ID: <4A0225C0.8000209@gmx.net>

On 22.04.2009 01:29, Carl-Daniel Hailfinger wrote:
> Flashrom does not support any notion of multiple probe functions for the
> same chip nor does it support multiple IDs for the same chip. For
> external flasher support with a clean design, this has to be changed.
>
> Group each probe function together with the associated IDs in the flash
> chip description. They belong together.
>
> The trick in this patch is to use an anonymous struct which allows the
> chip-specific code to stay unchanged for now, while still keeping full
> functionality.
> Besides easing review, it also keeps the tree working and bisectable.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Now that flashrom 0.9.0 is out, can we please merge this?

Regards,
Carl-Daniel

> Index: flashrom-probe_grouping/flash.h
> ===================================================================
> --- flashrom-probe_grouping/flash.h	(Revision 4161)
> +++ flashrom-probe_grouping/flash.h	(Arbeitskopie)
> @@ -98,8 +98,11 @@
>  	 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
>  	 * Identification code.
>  	 */
> +	struct {
>  	uint32_t manufacture_id;
>  	uint32_t model_id;
> +	int (*probe) (struct flashchip *flash);
> +	};
>  
>  	int total_size;
>  	int page_size;
> @@ -110,7 +113,6 @@
>  	 */
>  	uint32_t tested;
>  
> -	int (*probe) (struct flashchip *flash);
>  	int (*erase) (struct flashchip *flash);
>  	int (*write) (struct flashchip *flash, uint8_t *buf);
>  	int (*read) (struct flashchip *flash, uint8_t *buf);
> Index: flashrom-probe_grouping/flashchips.c
> ===================================================================
> --- flashrom-probe_grouping/flashchips.c	(Revision 4161)
> +++ flashrom-probe_grouping/flashchips.c	(Arbeitskopie)
> @@ -31,21 +31,33 @@
>   */
>  struct flashchip flashchips[] = {
>  
> -	/* Vendor, Chip, Vendor ID, Chip ID,
> -	 * Total size (kB), Page size (B),
> -	 * Test status,
> -	 * Probe function, Erase function, Write function, Read function
> +	/*
> +	 * .vendor		= Vendor name
> +	 * .name		= Chip name
> +	 * {			Probe/ID tuple
> +	 * 	.manufacture_id	= Manufacturer chip ID
> +	 * 	.model_id	= Model chip ID
> +	 * 	.probe		= Probe function
> +	 * },
> +	 * .total_size		= Total size in (binary) kbytes
> +	 * .page_size		= Page or eraseblock(?) size in bytes
> +	 * .tested		= Test status
> +	 * .erase		= Chip erase function
> +	 * .write		= Chip write function
> +	 * .read		= Chip read function
>  	 */
>  
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29F002(N)BB",
> +		{
>  		.manufacture_id	= AMD_ID,
>  		.model_id	= AM_29F002BB,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_en29f002a,
>  	},
> @@ -53,12 +65,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29F002(N)BT",
> +		{
>  		.manufacture_id	= AMD_ID,
>  		.model_id	= AM_29F002BT,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_en29f002a,
>  	},
> @@ -66,12 +80,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29F016D",
> +		{
>  		.manufacture_id	= AMD_ID,
>  		.model_id	= AM_29F016D,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -79,12 +95,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29F040B",
> +		{
>  		.manufacture_id	= AMD_ID,
>  		.model_id	= AM_29F040B,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -92,12 +110,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29F080B",
> +		{
>  		.manufacture_id	= 0x01,
>  		.model_id	= 0xd5,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -105,12 +125,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29LV040B",
> +		{
>  		.manufacture_id	= AMD_ID,
>  		.model_id	= AM_29LV040B,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -118,12 +140,14 @@
>  	{
>  		.vendor		= "AMD",
>  		.name		= "Am29LV081B",
> +		{
>  		.manufacture_id	= 0x01,
>  		.model_id	= 0x38,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -131,12 +155,14 @@
>  	{
>  		.vendor		= "ASD",
>  		.name		= "AE49F2008",
> +		{
>  		.manufacture_id	= ASD_ID,
>  		.model_id	= ASD_AE49F2008,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -144,12 +170,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF021",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF021,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -158,12 +186,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF041A",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF041A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -172,12 +202,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF081",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF081,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -186,12 +218,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF161",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF161,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -200,12 +234,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF321",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF321,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -214,12 +250,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF321A",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF321A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -228,12 +266,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25DF641",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25DF641,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 8192,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -242,12 +282,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25F512B",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25F512B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 64,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -256,12 +298,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25FS010",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25FS010,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -270,12 +314,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT25FS040",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_25FS040,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -284,12 +330,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT26DF041",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26DF041,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL /* Incompatible Page write */,
>  		.read		= spi_chip_read,
> @@ -298,12 +346,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT26DF081A",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26DF081A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -312,12 +362,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT26DF161",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26DF161,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -326,12 +378,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT26DF161A",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26DF161A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -341,12 +395,14 @@
>  	/*{
>  		.vendor		= "Atmel",
>  		.name		= "AT26DF321",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26DF321,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -355,12 +411,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT26F004",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_26F004,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= NULL /* Incompatible Page write */,
>  		.read		= spi_chip_read,
> @@ -369,12 +427,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT29C020",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_29C020,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -382,12 +442,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT29C040A",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_29C040A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -395,12 +457,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45CS1282",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45CS1282,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 16896 /* No power of two sizes */,
>  		.page_size	= 1056 /* No power of two sizes */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL /* Incompatible Page write */,
>  		.read		= NULL /* Incompatible read */,
> @@ -409,12 +473,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB011D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB011D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128 /* Size can only be determined from status register */,
>  		.page_size	= 256 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -423,12 +489,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB021D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB021D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256 /* Size can only be determined from status register */,
>  		.page_size	= 256 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -437,12 +505,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB041D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB041D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512 /* Size can only be determined from status register */,
>  		.page_size	= 256 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -451,12 +521,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB081D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB081D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024 /* Size can only be determined from status register */,
>  		.page_size	= 256 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -465,12 +537,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB161D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB161D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048 /* Size can only be determined from status register */,
>  		.page_size	= 512 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -479,12 +553,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB321C",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB321C,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4224 /* No power of two sizes */,
>  		.page_size	= 528 /* No power of two sizes */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL /* Incompatible read */,
> @@ -493,12 +569,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB321D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB321D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096 /* Size can only be determined from status register */,
>  		.page_size	= 512 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -507,12 +585,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT45DB642D",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_45DB642D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 8192 /* Size can only be determined from status register */,
>  		.page_size	= 1024 /* Size can only be determined from status register */,
>  		.tested		= TEST_BAD_READ,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  		.read		= NULL,
> @@ -521,12 +601,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT49F002(N)",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_49F002N,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -534,12 +616,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "AT49F002(N)T",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= AT_49F002NT,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -547,12 +631,14 @@
>  	{
>  		.vendor		= "AMIC",
>  		.name		= "A25L40P",
> +		{
>  		.manufacture_id	= AMIC_ID,
>  		.model_id	= AMIC_A25L40P,
> +		.probe		= probe_spi_rdid4,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid4,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -561,12 +647,14 @@
>  	{
>  		.vendor		= "AMIC",
>  		.name		= "A29002B",
> +		{
>  		.manufacture_id	= AMIC_ID_NOPREFIX,
>  		.model_id	= AMIC_A29002B,
> +		.probe		= probe_29f002,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f002,
>  		.erase		= erase_29f002,
>  		.write		= write_29f002,
>  	},
> @@ -574,12 +662,14 @@
>  	{
>  		.vendor		= "AMIC",
>  		.name		= "A29002T",
> +		{
>  		.manufacture_id	= AMIC_ID_NOPREFIX,
>  		.model_id	= AMIC_A29002T,
> +		.probe		= probe_29f002,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_29f002,
>  		.erase		= erase_29f002,
>  		.write		= write_29f002,
>  	},
> @@ -587,12 +677,14 @@
>  	{
>  		.vendor		= "AMIC",
>  		.name		= "A29040B",
> +		{
>  		.manufacture_id	= AMIC_ID_NOPREFIX,
>  		.model_id	= AMIC_A29040B,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PR,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -600,12 +692,14 @@
>  	{
>  		.vendor		= "AMIC",
>  		.name		= "A49LF040A",
> +		{
>  		.manufacture_id	= AMIC_ID_NOPREFIX,
>  		.model_id	= AMIC_A49LF040A,
> +		.probe		= probe_49fl00x,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_49fl00x,
>  		.erase		= erase_49fl00x,
>  		.write		= write_49fl00x,
>  	},
> @@ -613,12 +707,14 @@
>  	{
>  		.vendor		= "EMST",
>  		.name		= "F49B002UA",
> +		{
>  		.manufacture_id	= EMST_ID,
>  		.model_id	= EMST_F49B002UA,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 4096,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -626,12 +722,14 @@
>  	{
>  		.vendor		= "EON",
>  		.name		= "EN29F002(A)(N)B",
> +		{
>  		.manufacture_id	= EON_ID,
>  		.model_id	= EN_29F002B,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_en29f002a,
>  	},
> @@ -639,12 +737,14 @@
>  	{
>  		.vendor		= "EON",
>  		.name		= "EN29F002(A)(N)T",
> +		{
>  		.manufacture_id	= EON_ID,
>  		.model_id	= EN_29F002T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_en29f002a,
>  	},
> @@ -652,12 +752,14 @@
>  	{
>  		.vendor		= "Fujitsu",
>  		.name		= "MBM29F004BC",
> +		{
>  		.manufacture_id	= FUJITSU_ID,
>  		.model_id	= MBM29F004BC,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -665,12 +767,14 @@
>  	{
>  		.vendor		= "Fujitsu",
>  		.name		= "MBM29F004TC",
> +		{
>  		.manufacture_id	= FUJITSU_ID,
>  		.model_id	= MBM29F004TC,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -678,12 +782,14 @@
>  	{
>  		.vendor		= "Fujitsu",
>  		.name		= "MBM29F400BC",
> +		{
>  		.manufacture_id	= FUJITSU_ID,
>  		.model_id	= MBM29F400BC,
> +		.probe		= probe_m29f400bt,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_m29f400bt,
>  		.erase		= erase_m29f400bt,
>  		.write		= write_coreboot_m29f400bt,
>  	},
> @@ -691,12 +797,14 @@
>  	{
>  		.vendor		= "Fujitsu",
>  		.name		= "MBM29F400TC",
> +		{
>  		.manufacture_id	= FUJITSU_ID,
>  		.model_id	= MBM29F400TC,
> +		.probe		= probe_m29f400bt,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_m29f400bt,
>  		.erase		= erase_m29f400bt,
>  		.write		= write_coreboot_m29f400bt,
>  	},
> @@ -704,12 +812,14 @@
>  	{
>  		.vendor		= "Intel",
>  		.name		= "82802AB",
> +		{
>  		.manufacture_id	= INTEL_ID,
>  		.model_id	= 173,
> +		.probe		= probe_82802ab,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_82802ab,
>  		.erase		= erase_82802ab,
>  		.write		= write_82802ab,
>  	},
> @@ -717,12 +827,14 @@
>  	{
>  		.vendor		= "Intel",
>  		.name		= "82802AC",
> +		{
>  		.manufacture_id	= INTEL_ID,
>  		.model_id	= 172,
> +		.probe		= probe_82802ab,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_82802ab,
>  		.erase		= erase_82802ab,
>  		.write		= write_82802ab,
>  	},
> @@ -730,12 +842,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L512",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L512,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 64,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -744,12 +858,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L1005",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L1005,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -758,12 +874,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L2005",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L2005,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -772,12 +890,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L4005",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L4005,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -786,12 +906,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L8005",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L8005,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -800,12 +922,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L1605",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L1605,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -814,12 +938,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L1635D",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L1635D,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -828,12 +954,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L3205",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L3205,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -842,12 +970,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L6405",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L6405,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 8192,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -856,12 +986,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX25L12805",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_25L12805,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 16384,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -870,12 +1002,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX29F002B",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_29F002B,
> +		.probe		= probe_29f002,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f002,
>  		.erase		= erase_29f002,
>  		.write		= write_29f002,
>  	},
> @@ -883,12 +1017,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX29F002T",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_29F002T,
> +		.probe		= probe_29f002,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_29f002,
>  		.erase		= erase_29f002,
>  		.write		= write_29f002,
>  	},
> @@ -896,12 +1032,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "MX29LV040C",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= MX_29LV040C,
> +		.probe		= probe_29f002,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PR,
> -		.probe		= probe_29f002,
>  		.erase		= erase_29f002,
>  		.write		= write_29f002,
>  	},
> @@ -909,12 +1047,14 @@
>  	{
>  		.vendor		= "Numonyx",
>  		.name		= "M25PE10",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= 0x8011,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_d8,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -923,12 +1063,14 @@
>  	{
>  		.vendor		= "Numonyx",
>  		.name		= "M25PE20",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= 0x8012,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_d8,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -937,12 +1079,14 @@
>  	{
>  		.vendor		= "Numonyx",
>  		.name		= "M25PE40",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= 0x8013,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_d8,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -951,12 +1095,14 @@
>  	{
>  		.vendor		= "Numonyx",
>  		.name		= "M25PE80",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= 0x8014,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_d8,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -965,12 +1111,14 @@
>  	{
>  		.vendor		= "Numonyx",
>  		.name		= "M25PE16",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= 0x8015,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_d8,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -979,12 +1127,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV010",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV010,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -993,12 +1143,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV016B",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV016B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1007,12 +1159,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV020",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV020,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1021,12 +1175,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV040",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV040,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1035,12 +1191,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV080B",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV080B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1049,12 +1207,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm25LV512",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= PMC_25LV512,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 64,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1063,12 +1223,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm49FL002",
> +		{
>  		.manufacture_id	= PMC_ID_NOPREFIX,
>  		.model_id	= PMC_49FL002,
> +		.probe		= probe_49fl00x,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 16 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_49fl00x,
>  		.erase		= erase_49fl00x,
>  		.write		= write_49fl00x,
>  	},
> @@ -1076,12 +1238,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "Pm49FL004",
> +		{
>  		.manufacture_id	= PMC_ID_NOPREFIX,
>  		.model_id	= PMC_49FL004,
> +		.probe		= probe_49fl00x,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_49fl00x,
>  		.erase		= erase_49fl00x,
>  		.write		= write_49fl00x,
>  	},
> @@ -1089,12 +1253,14 @@
>  	{
>  		.vendor		= "Sharp",
>  		.name		= "LHF00L04",
> +		{
>  		.manufacture_id	= SHARP_ID,
>  		.model_id	= SHARP_LHF00L04,
> +		.probe		= probe_lhf00l04,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_lhf00l04,
>  		.erase		= erase_lhf00l04,
>  		.write		= write_lhf00l04,
>  	},
> @@ -1102,12 +1268,14 @@
>  	{
>  		.vendor		= "Spansion",
>  		.name		= "S25FL016A",
> +		{
>  		.manufacture_id	= SPANSION_ID,
>  		.model_id	= SPANSION_S25FL016A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1116,12 +1284,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF016B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_25VF016B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1130,12 +1300,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF032B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_25VF032B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1144,12 +1316,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF040B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_25VF040B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1158,12 +1332,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF040.REMS",
> +		{
>  		.manufacture_id	= 0xbf,
>  		.model_id	= 0x44,
> +		.probe		= probe_spi_rems,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PR,
> -		.probe		= probe_spi_rems,
>  		.erase		= spi_chip_erase_60,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1172,12 +1348,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF040B.REMS",
> +		{
>  		.manufacture_id	= 0xbf,
>  		.model_id	= 0x8d,
> +		.probe		= probe_spi_rems,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PR,
> -		.probe		= probe_spi_rems,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_aai_write,
>  		.read		= spi_chip_read,
> @@ -1186,12 +1364,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST25VF080B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_25VF080B,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PROBE,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_60_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1200,12 +1380,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST28SF040A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_28SF040,
> +		.probe		= probe_28sf040,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_28sf040,
>  		.erase		= erase_28sf040,
>  		.write		= write_28sf040,
>  	},
> @@ -1213,12 +1395,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST29EE010",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_29EE010,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1226,12 +1410,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST29LE010",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_29LE010,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1239,12 +1425,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST29EE020A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_29EE020A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1252,12 +1440,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST29LE020",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_29LE020,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1265,12 +1455,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39SF010A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39SF010,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1278,12 +1470,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39SF020A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39SF020,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1291,12 +1485,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39SF040",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39SF040,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1304,12 +1500,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39VF512",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39VF512,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 64,
>  		.page_size	= 4096,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1317,12 +1515,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39VF010",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39VF010,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 4096,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1330,12 +1530,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39VF020",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39VF020,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1343,12 +1545,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39VF040",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_39VF040,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PROBE,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1356,12 +1560,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST39VF080",
> +		{
>  		.manufacture_id	= 0xbf,
>  		.model_id	= 0xd8,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 4096,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -1369,12 +1575,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF002A/B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF002A,
> +		.probe		= probe_sst_fwhub,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 16 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_sst_fwhub,
>  		.erase		= erase_sst_fwhub,
>  		.write		= write_sst_fwhub,
>  	},
> @@ -1382,12 +1590,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF003A/B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF003A,
> +		.probe		= probe_sst_fwhub,
> +		},
>  		.total_size	= 384,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_sst_fwhub,
>  		.erase		= erase_sst_fwhub,
>  		.write		= write_sst_fwhub,
>  	},
> @@ -1395,12 +1605,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF004A/B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF004A,
> +		.probe		= probe_sst_fwhub,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_sst_fwhub,
>  		.erase		= erase_sst_fwhub,
>  		.write		= write_sst_fwhub,
>  	},
> @@ -1408,12 +1620,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF004C",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF004C,
> +		.probe		= probe_49lfxxxc,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 4 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_49lfxxxc,
>  		.erase		= erase_49lfxxxc,
>  		.write		= write_49lfxxxc,
>  	},
> @@ -1421,12 +1635,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF008A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF008A,
> +		.probe		= probe_sst_fwhub,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_sst_fwhub,
>  		.erase		= erase_sst_fwhub,
>  		.write		= write_sst_fwhub,
>  	},
> @@ -1434,12 +1650,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF008C",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF008C,
> +		.probe		= probe_49lfxxxc,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 4 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_49lfxxxc,
>  		.erase		= erase_49lfxxxc,
>  		.write		= write_49lfxxxc,
>  	},
> @@ -1447,12 +1665,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF016C",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF016C,
> +		.probe		= probe_49lfxxxc,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 4 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_49lfxxxc,
>  		.erase		= erase_49lfxxxc,
>  		.write		= write_49lfxxxc,
>  	},
> @@ -1460,12 +1680,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF020",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF020,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 16 * 1024,
>  		.tested		= TEST_OK_PR,
> -		.probe		= probe_jedec,
>  		.erase		= erase_49lf040,
>  		.write		= write_49lf040,
>  	},
> @@ -1473,12 +1695,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF020A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF020A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 16 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_49lf040,
>  		.write		= write_49lf040,
>  	},
> @@ -1486,12 +1710,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF040",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF040,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_49lf040,
>  		.write		= write_49lf040,
>  	},
> @@ -1499,12 +1725,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF040B",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF040B,
> +		.probe		= probe_sst_fwhub,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_sst_fwhub,
>  		.erase		= erase_sst_fwhub,
>  		.write		= write_sst_fwhub,
>  	},
> @@ -1512,12 +1740,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF080A",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF080A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 4096,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_49lf040,
>  		.write		= write_49lf040,
>  	},
> @@ -1525,12 +1755,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "SST49LF160C",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= SST_49LF160C,
> +		.probe		= probe_49lfxxxc,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 4 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_49lfxxxc,
>  		.erase		= erase_49lfxxxc,
>  		.write		= write_49lfxxxc,
>  	},
> @@ -1538,12 +1770,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P05-A",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P05A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 64,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1552,12 +1786,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P10-A",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P10A,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1566,12 +1802,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P20",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P20,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1580,12 +1818,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P40",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P40,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1594,12 +1834,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P40-old",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P40_RES,
> +		.probe		= probe_spi_res,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_res,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1608,12 +1850,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P80",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P80,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1622,12 +1866,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P16",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P16,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1636,12 +1882,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P32",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P32,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 4096,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1650,12 +1898,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P64",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P64,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 8192,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1664,12 +1914,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M25P128",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M25P128,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 16384,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1678,12 +1930,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29F002B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29F002B,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_m29f002,
>  		.write		= write_m29f002b,
>  	},
> @@ -1691,12 +1945,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29F002T/NT",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29F002T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_m29f002,
>  		.write		= write_m29f002t,
>  	},
> @@ -1704,12 +1960,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29F040B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29F040B,
> +		.probe		= probe_29f040b,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_29f040b,
>  		.erase		= erase_29f040b,
>  		.write		= write_29f040b,
>  	},
> @@ -1717,12 +1975,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29F400BT",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29F400BT,
> +		.probe		= probe_m29f400bt,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_m29f400bt,
>  		.erase		= erase_m29f400bt,
>  		.write		= write_coreboot_m29f400bt,
>  	},
> @@ -1730,12 +1990,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29W010B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29W010B,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 16 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1743,12 +2005,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M29W040B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M29W040B,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1756,12 +2020,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FLW040A",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FLW040A,
> +		.probe		= probe_stm50flw0x0x,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_stm50flw0x0x,
>  		.erase		= erase_stm50flw0x0x,
>  		.write		= write_stm50flw0x0x,
>  	},
> @@ -1769,12 +2035,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FLW040B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FLW040B,
> +		.probe		= probe_stm50flw0x0x,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_stm50flw0x0x,
>  		.erase		= erase_stm50flw0x0x,
>  		.write		= write_stm50flw0x0x,
>  	},
> @@ -1782,12 +2050,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FLW080A",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FLW080A,
> +		.probe		= probe_stm50flw0x0x,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_stm50flw0x0x,
>  		.erase		= erase_stm50flw0x0x,
>  		.write		= write_stm50flw0x0x,
>  	},
> @@ -1795,12 +2065,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FLW080B",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FLW080B,
> +		.probe		= probe_stm50flw0x0x,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_stm50flw0x0x,
>  		.erase		= erase_stm50flw0x0x,
>  		.write		= write_stm50flw0x0x,
>  	},
> @@ -1808,12 +2080,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FW002",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FW002,
> +		.probe		= probe_49lfxxxc,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_49lfxxxc,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -1821,12 +2095,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FW016",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FW016,
> +		.probe		= probe_82802ab,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_82802ab,
>  		.erase		= erase_82802ab,
>  		.write		= write_82802ab,
>  	},
> @@ -1834,12 +2110,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FW040",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FW040,
> +		.probe		= probe_82802ab,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_82802ab,
>  		.erase		= erase_82802ab,
>  		.write		= write_82802ab,
>  	},
> @@ -1847,12 +2125,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50FW080",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50FW080,
> +		.probe		= probe_82802ab,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_82802ab,
>  		.erase		= erase_82802ab,
>  		.write		= write_82802ab,
>  	},
> @@ -1860,12 +2140,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "M50LPW116",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= ST_M50LPW116,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 2048,
>  		.page_size	= 64 * 1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1873,12 +2155,14 @@
>  	{
>  		.vendor		= "SyncMOS",
>  		.name		= "S29C31004T",
> +		{
>  		.manufacture_id	= SYNCMOS_ID,
>  		.model_id	= S29C31004T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -1886,12 +2170,14 @@
>  	{
>  		.vendor		= "SyncMOS",
>  		.name		= "S29C51001T",
> +		{
>  		.manufacture_id	= SYNCMOS_ID,
>  		.model_id	= S29C51001T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -1899,12 +2185,14 @@
>  	{
>  		.vendor		= "SyncMOS",
>  		.name		= "S29C51002T",
> +		{
>  		.manufacture_id	= SYNCMOS_ID,
>  		.model_id	= S29C51002T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -1912,12 +2200,14 @@
>  	{
>  		.vendor		= "SyncMOS",
>  		.name		= "S29C51004T",
> +		{
>  		.manufacture_id	= SYNCMOS_ID,
>  		.model_id	= S29C51004T,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -1925,12 +2215,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W25x10",
> +		{
>  		.manufacture_id	= WINBOND_NEX_ID,
>  		.model_id	= W_25X10,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1939,12 +2231,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W25x20",
> +		{
>  		.manufacture_id	= WINBOND_NEX_ID,
>  		.model_id	= W_25X20,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1953,12 +2247,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W25x40",
> +		{
>  		.manufacture_id	= WINBOND_NEX_ID,
>  		.model_id	= W_25X40,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1967,12 +2263,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W25x80",
> +		{
>  		.manufacture_id	= WINBOND_NEX_ID,
>  		.model_id	= W_25X80,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 256,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_spi_rdid,
>  		.erase		= spi_chip_erase_c7,
>  		.write		= spi_chip_write,
>  		.read		= spi_chip_read,
> @@ -1981,12 +2279,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W29C011",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_29C011,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -1994,12 +2294,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W29C020C",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_29C020C,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -2007,12 +2309,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W29C040P",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_29C040P,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -2020,12 +2324,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W29EE011",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_29C011,
> +		.probe		= probe_w29ee011,
> +		},
>  		.total_size	= 128,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_w29ee011,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_jedec,
>  	},
> @@ -2033,12 +2339,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V040A",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V040A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -2046,12 +2354,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V040B",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V040B,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -2059,12 +2369,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V040C",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= 0x50,
> +		.probe		= probe_w39v040c,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_w39v040c,
>  		.erase		= erase_w39v040c,
>  		.write		= write_w39v040c,
>  	},
> @@ -2072,12 +2384,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V040FA",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V040FA,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -2085,12 +2399,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V080A",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V080A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_39sf020,
>  	},
> @@ -2098,12 +2414,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W49F002U",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_49F002U,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -2111,12 +2429,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W49V002A",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_49V002A,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -2124,12 +2444,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W49V002FA",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_49V002FA,
> +		.probe		= probe_jedec,
> +		},
>  		.total_size	= 256,
>  		.page_size	= 128,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_jedec,
>  		.erase		= erase_chip_jedec,
>  		.write		= write_49f002,
>  	},
> @@ -2137,12 +2459,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V080FA",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V080FA,
> +		.probe		= probe_winbond_fwhub,
> +		},
>  		.total_size	= 1024,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_OK_PREW,
> -		.probe		= probe_winbond_fwhub,
>  		.erase		= erase_winbond_fwhub,
>  		.write		= write_winbond_fwhub,
>  	},
> @@ -2150,12 +2474,14 @@
>  	{
>  		.vendor		= "Winbond",
>  		.name		= "W39V080FA (dual mode)",
> +		{
>  		.manufacture_id	= WINBOND_ID,
>  		.model_id	= W_39V080FA_DM,
> +		.probe		= probe_winbond_fwhub,
> +		},
>  		.total_size	= 512,
>  		.page_size	= 64*1024,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_winbond_fwhub,
>  		.erase		= erase_winbond_fwhub,
>  		.write		= write_winbond_fwhub,
>  	},
> @@ -2163,12 +2489,14 @@
>  	{
>  		.vendor		= "Atmel",
>  		.name		= "unknown Atmel SPI chip",
> +		{
>  		.manufacture_id	= ATMEL_ID,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -2176,12 +2504,14 @@
>  	{
>  		.vendor		= "EON",
>  		.name		= "unknown EON SPI chip",
> +		{
>  		.manufacture_id	= EON_ID_NOPREFIX,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -2189,12 +2519,14 @@
>  	{
>  		.vendor		= "Macronix",
>  		.name		= "unknown Macronix SPI chip",
> +		{
>  		.manufacture_id	= MX_ID,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -2202,12 +2534,14 @@
>  	{
>  		.vendor		= "PMC",
>  		.name		= "unknown PMC SPI chip",
> +		{
>  		.manufacture_id	= PMC_ID,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -2215,12 +2549,14 @@
>  	{
>  		.vendor		= "SST",
>  		.name		= "unknown SST SPI chip",
> +		{
>  		.manufacture_id	= SST_ID,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
> @@ -2228,12 +2564,14 @@
>  	{
>  		.vendor		= "ST",
>  		.name		= "unknown ST SPI chip",
> +		{
>  		.manufacture_id	= ST_ID,
>  		.model_id	= GENERIC_DEVICE_ID,
> +		.probe		= probe_spi_rdid,
> +		},
>  		.total_size	= 0,
>  		.page_size	= 256,
>  		.tested		= TEST_UNTESTED,
> -		.probe		= probe_spi_rdid,
>  		.erase		= NULL,
>  		.write		= NULL,
>  	},
>
>
>   


-- 
http://www.hailfinger.org/




From svn at coreboot.org  Thu May  7 02:21:02 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  7 May 2009 02:21:02 +0200
Subject: [coreboot] [v2] r4256 - trunk/util/superiotool
Message-ID: <mailman.3176.1355071537.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-05-07 02:21:02 +0200 (Thu, 07 May 2009)
New Revision: 4256

Modified:
   trunk/util/superiotool/smsc.c
Log:
Fix my last commit. I looked at the wrong dead laptop.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/util/superiotool/smsc.c
===================================================================
--- trunk/util/superiotool/smsc.c	2009-05-07 00:03:18 UTC (rev 4255)
+++ trunk/util/superiotool/smsc.c	2009-05-07 00:21:02 UTC (rev 4256)
@@ -531,7 +531,7 @@
 		{EOT}}},
 	{0x79, "SCH5504", {	/* From sensors-detect (no datasheet) */
 		{EOT}}},
-	{0x7a, "FDC37N869", {	/* Found in Toshiba Satellite A80-117. */
+	{0x7a, "LPC47N217", {	/* Found in Toshiba Satellite A80-117. */
 		{EOT}}},
 	{0x7c, "SCH3112", {
 		{EOT}}},




From svn at coreboot.org  Thu May  7 02:23:29 2009
From: svn at coreboot.org (coreboot)
Date: Thu, 07 May 2009 00:23:29 -0000
Subject: [coreboot] #131: New flashrom motherboard support
In-Reply-To: <045.fafa58fccf6f1868f71243ff245dc850@coreboot.org>
References: <045.fafa58fccf6f1868f71243ff245dc850@coreboot.org>
Message-ID: <054.f76d684ee81ec0253ce220bfc7c4857c@coreboot.org>

#131: New flashrom motherboard support
---------------------------------+------------------------------------------
   Reporter:  anonymous          |          Owner:  somebody        
       Type:  enhancement        |         Status:  new             
   Priority:  trivial            |      Milestone:  Going mainstream
  Component:  flashrom           |        Version:  v2              
   Keywords:  flashrom asus      |   Dependencies:                  
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by Fleencemern):

 Launched the mod wonderful program - Libertyreserve Bank

 It prime be a meticulous of the higher up-savoir faire programs of
 2009-2010 !

 Program application permit libretto and Anti-DDoS guardianship!!!

 Plans:

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 107% after 3 days

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 ______________________________________
 <a href=https://libertyreserveinvestments.biz>navigate money</a>

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131#comment:2>
coreboot <http://www.coreboot.org/>


From fengyuning1984 at gmail.com  Thu May  7 02:45:46 2009
From: fengyuning1984 at gmail.com (FENG Yu Ning)
Date: Thu, 7 May 2009 08:45:46 +0800
Subject: [coreboot] [flashrom] Transaction Error with opcode 0x03
	failed...
In-Reply-To: <4A01BFF6.4000203@icyb.net.ua>
References: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
	<a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
	<4A01BFF6.4000203@icyb.net.ua>
Message-ID: <a505dc9d0905061745m7576c6d0m45170df6a30b21a2@mail.gmail.com>

Andriy Gapon wrote:

> I wonder what the following means (on my machine):
> 0x54: 0x00000000 (FREG0)

All 0s value is confusing at the first sight. However, if you would
like to read the explanation once more and pay attention to the
detail, I believe you will get a different conclusion.

>> The value 0x0(23f)0(00b) means, ...
>> ... to 0x00(23f)fff ...

You probably have got it.

The explanation contains minor error, though. To be exact, bits 28 ..
16 of FREGn represent bits 24 .. 12 of the region's limit. That is one
bit more than my parentheses show. Bits 11 .. 0 of the region's limit,
I believe, is 0xfff, which is not clearly stated in the datasheet.
Bits 12 .. 0 of FREGn represent bits 24 .. 12 of the region's base.
The other (lower) bits of the region's base should be 0.

Therefore, 0x00000000 should mean a region from 0x0000000 to 0x0000fff.

> BTW:
> 0x50: 0x00000a0b (FRAP)

According to the datasheet, the bit n in bits 7 .. 0 indicates
software read access to FREGn (n is in [0, 4]). Similarly, the bit n
in bits 15 .. 8 indicates software write access to FREG(n-8) ((n-8) is
in [0, 4]). So the value means software can write to FREG1 and FREG3,
while it can read FREG0, 1 and 3. However, iirc, there is other
protection mechanism, so software may still be banned to write on part
of FREG1 or FREG3.

If you would like to get information from the source, dig into Chap 22
of the ICH9 datasheet. You may need multiple parses to find out what
you need. Besides, there are some mistakes in the datasheet, but that
should not affect if you are not reading it very carefully.

yu ning



From svn at coreboot.org  Thu May  7 02:48:48 2009
From: svn at coreboot.org (coreboot)
Date: Thu, 07 May 2009 00:48:48 -0000
Subject: [coreboot]  #133: Create a typical failures FAQ
Message-ID: <041.4330d86eb0cdc892e12aa1c343596b23@coreboot.org>

#133: Create a typical failures FAQ
---------------------------------------+------------------------------------
   Reporter:  stuge                    |          Owner:  somebody
       Type:  enhancement              |         Status:  new     
   Priority:  major                    |      Milestone:          
  Component:  flashrom                 |        Version:          
   Keywords:  faq documentation debug  |   Dependencies:          
Patchstatus:  there is no patch        |  
---------------------------------------+------------------------------------
 Briefly describe what flashrom needs to do to successfully identify, read
 and write/erase the different type of chips to optimize the remote
 debugging process with new users.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/133>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Thu May  7 02:50:41 2009
From: svn at coreboot.org (coreboot)
Date: Thu, 07 May 2009 00:50:41 -0000
Subject: [coreboot] #132: Add version number to flashrom output
In-Reply-To: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
References: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
Message-ID: <050.5dd230ec474b66ab109eb02f0b6c45a2@coreboot.org>

#132: Add version number to flashrom output
---------------------------------+------------------------------------------
   Reporter:  stuge              |          Owner:  hailfinger
       Type:  defect             |         Status:  assigned  
   Priority:  major              |      Milestone:            
  Component:  flashrom           |        Version:            
   Keywords:  ui debug info      |   Dependencies:            
Patchstatus:  there is no patch  |  
---------------------------------+------------------------------------------

Comment(by stuge):

 Awesome! Feel free to self ack.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/132#comment:2>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Thu May  7 02:59:53 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  7 May 2009 02:59:53 +0200
Subject: [coreboot] [flashrom] r471 - trunk
Message-ID: <mailman.3177.1355071537.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-05-07 02:59:53 +0200 (Thu, 07 May 2009)
New Revision: 471

Modified:
   trunk/flashrom.c
Log:
Always print the flashrom version as first output line.

Suggested by Peter Stuge.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/flashrom.c
===================================================================
--- trunk/flashrom.c	2009-05-06 21:54:22 UTC (rev 470)
+++ trunk/flashrom.c	2009-05-07 00:59:53 UTC (rev 471)
@@ -369,6 +369,8 @@
 	unsigned int exclude_start_position = 0, exclude_end_position = 0;	// [x,y)
 	char *tempstr = NULL, *tempstr2 = NULL;
 
+	print_version();
+
 	if (argc > 1) {
 		/* Yes, print them. */
 		int i;
@@ -438,7 +440,7 @@
 			exit(0);
 			break;
 		case 'R':
-			print_version();
+			/* print_version() is always called during startup. */
 			exit(0);
 			break;
 		case 'h':




From svn at coreboot.org  Thu May  7 03:00:48 2009
From: svn at coreboot.org (coreboot)
Date: Thu, 07 May 2009 01:00:48 -0000
Subject: [coreboot] #132: Add version number to flashrom output
In-Reply-To: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
References: <041.a85aba55dda48dc14e7c56a99d9dea58@coreboot.org>
Message-ID: <050.22692e5f3e3052dbef4e985432c45213@coreboot.org>

#132: Add version number to flashrom output
-------------------------+--------------------------------------------------
    Reporter:  stuge     |         Owner:  hailfinger       
        Type:  defect    |        Status:  closed           
    Priority:  major     |     Milestone:                   
   Component:  flashrom  |       Version:                   
  Resolution:  fixed     |      Keywords:  ui debug info    
Dependencies:            |   Patchstatus:  there is no patch
-------------------------+--------------------------------------------------
Changes (by hailfinger):

  * status:  assigned => closed
  * resolution:  => fixed


Comment:

 Fixed in r471.

-- 
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/132#comment:3>
coreboot <http://www.coreboot.org/>


From nadalizadeh at gmail.com  Thu May  7 03:26:16 2009
From: nadalizadeh at gmail.com (Ali Nadalizadeh)
Date: Thu, 7 May 2009 05:56:16 +0430
Subject: [coreboot] Failed flash, flashrom emergency help needed on ICH7
In-Reply-To: <4A01EA26.3000701@assembler.cz>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com> 
	<4A01EA26.3000701@assembler.cz>
Message-ID: <5e5c5ae40905061826p132fa394r55e946b86c202c95@mail.gmail.com>

lspci -xxx output attached

On Thu, May 7, 2009 at 12:21 AM, Rudolf Marek <r.marek at assembler.cz> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Hmm I checked the orig bios image for any special handling and there is
> none.
> Even it seems that EC has its own flash somewhere else. (this is good)
>
> Perhaps there are some locks in chip itself? Any expert here on that?
> Can we read the status reg from the chip? The WP# of the chip seems just to
> enable/disable modifications to the to the BP bits.
>
> I suspect the part flashing does not work well. There seems to  be no
> obstacles
> elsewhere.
>
> Can you post here lspci -xxx
>
> Rudolf
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.9 (GNU/Linux)
> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
> iEYEARECAAYFAkoB6iQACgkQ3J9wPJqZRNUwgACfZkN1B45fPlmQ0jV0NdMtOvVC
> 0P4AoIA6tVBC/XzOdleoBL7amNpRpIHJ
> =RWFH
> -----END PGP SIGNATURE-----
>


--
Ali Nadalizadeh
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090507/9872a413/attachment.html>
-------------- next part --------------
00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub (rev 03)
00: 86 80 a0 27 06 01 90 20 03 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 82 20
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)
00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00
10: 00 00 10 d8 01 18 00 00 08 00 00 c0 00 00 20 d8
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 83 20
30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00

00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller (rev 03)
00: 86 80 a6 27 07 00 90 00 03 00 80 03 00 00 80 00
10: 00 00 18 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 83 20
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00

00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 02)
00: 86 80 d8 27 06 01 10 00 02 00 03 04 10 00 00 00
10: 04 00 24 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 85 20
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00

00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 02)
00: 86 80 d0 27 07 04 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 02 03 00 20 20 00 20
20: 00 d4 f0 d5 01 d0 f1 d1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 04 00

00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 (rev 02)
00: 86 80 d4 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 04 05 00 30 30 00 20
20: 00 d6 f0 d7 01 d2 f1 d3 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 03 03 04 00

00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 02)
00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 18 00 00 00 00 00 00 00 00 00 00 aa 17 8a 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00

00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 02)
00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 18 00 00 00 00 00 00 00 00 00 00 aa 17 8b 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00

00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 02)
00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 18 00 00 00 00 00 00 00 00 00 00 aa 17 8c 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00

00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 02)
00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 18 00 00 00 00 00 00 00 00 00 00 aa 17 8d 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 00

00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 02)
00: 86 80 cc 27 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 40 44 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 8e 20
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
00: 86 80 48 24 07 01 10 00 e2 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 0a 0a 20 40 40 80 22
20: 00 d8 00 d8 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00

00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge (rev 02)
00: 86 80 b9 27 07 01 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 90 20
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 02)
00: 86 80 df 27 05 00 80 02 02 8a 01 01 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 11 18 00 00 00 00 00 00 00 00 00 00 aa 17 9b 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00

00:1f.2 SATA controller: Intel Corporation 82801GBM/GHM (ICH7 Family) SATA AHCI Controller (rev 02)
00: 86 80 c5 27 07 04 b0 02 02 01 06 01 00 00 00 00
10: d1 18 00 00 c5 18 00 00 c9 18 00 00 c1 18 00 00
20: b1 18 00 00 00 44 44 d8 00 00 00 00 aa 17 91 20
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 02 00 00

00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02)
00: 86 80 da 27 01 01 80 02 02 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: e1 18 00 00 00 00 00 00 00 00 00 00 aa 17 92 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00

04:00.0 Network controller: Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection (rev 02)
00: 86 80 27 42 06 05 10 00 02 00 80 02 10 00 00 00
10: 00 00 00 d6 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 11 10
30: 00 00 00 00 c8 00 00 00 00 00 00 00 03 01 00 00

0a:01.0 FireWire (IEEE 1394): Ricoh Co Ltd R5C832 IEEE 1394 Controller
00: 80 11 32 08 06 01 10 02 00 10 00 0c 00 20 80 00
10: 00 00 00 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 94 20
30: 00 00 00 00 dc 00 00 00 00 00 00 00 04 01 02 04

0a:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 19)
00: 80 11 22 08 06 01 10 02 19 00 05 08 00 20 80 00
10: 00 08 00 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 95 20
30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 02 00 00

0a:01.2 System peripheral: Ricoh Co Ltd R5C843 MMC Host Controller (rev 0a)
00: 80 11 92 05 00 00 10 02 0a 00 80 08 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 97 20
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 02 00 00

0a:01.3 System peripheral: Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter (rev 05)
00: 80 11 52 08 02 01 10 02 05 00 80 08 00 00 80 00
10: 00 14 00 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 98 20
30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 02 00 00

0a:01.4 System peripheral: Ricoh Co Ltd xD-Picture Card Controller (rev ff)
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

0a:07.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
00: ec 10 39 81 07 01 90 02 10 00 00 02 00 20 00 00
10: 01 40 00 00 00 18 00 d8 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 93 20
30: 00 00 00 00 50 00 00 00 00 00 00 00 04 01 20 40


From peter at stuge.se  Thu May  7 05:37:14 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 7 May 2009 05:37:14 +0200
Subject: [coreboot] Failed flash, flashrom emergency help needed on ICH7
In-Reply-To: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>
Message-ID: <20090507033714.3301.qmail@stuge.se>

Ali Nadalizadeh wrote:
> I'm also online on #coreboot as nadalizadeh

Some analysis after Ali worked with Carl-Daniel and me to debug this.

The chip needs a write enable command to set it's write enable latch
before each erase or write command.

flashrom sends this as a separate command, but for software sequenced
ICH SPI that doesn't work, it needs to go into the ICH PREOP register
and not be sent as an individual command.

Because this fails when trying to send an erase command, chip erase
aborts. Ignoring that write enable error allows the erase to
continue, and succeed.

This chip doesn't support writes of more than one byte at a time
using the 02 command, but the flashrom ICH SPI driver (and maybe
others) assumes that all chips support more data in one go. Many do.

Ali had to go, and we have to rest a little, right now the machine is
running AAI programming, writing two bytes at a time.

If that doesn't work either, the next step is to try the 02 byte
program command but actually send only a single byte at a time.
(force maxdata=1 somewhere suitable)

More updates this afternoon. I think it'll work in the end.


//Peter



From kevin at koconnor.net  Thu May  7 05:53:24 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 6 May 2009 23:53:24 -0400
Subject: [coreboot] [ANN] Port of GPL vgabios to gcc
Message-ID: <20090507035324.GA25815@morn.localdomain>

I have made an initial pass at porting the open source vgabios at:

http://www.nongnu.org/vgabios/

from bcc/as86 to gcc.

The new code can be found in the SeaBIOS git repository.  To download
and build the code use:

git clone git://git.linuxtogo.org/home/kevin/seabios.git
cd seabios/
make out/vgabios.bin

The resulting binary can be used on qemu.  For example:

cd seabios/
make
make out/vgabios.bin
cp out/*.bin ../testqemu/
qemu -L ../testqemu/ -hda myimage


This new vga code is still preliminary.  I can start qemu, but there
are known bugs and unimplemented features.

The goal of porting the vga bios to gcc is to make the code more
understandable and easier to modify.  The code could potentially be
enhanced to run on real hardware.  (The current code will only run on
emulators.)

-Kevin



From svn at coreboot.org  Thu May  7 07:47:05 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  7 May 2009 07:47:05 +0200
Subject: [coreboot] [v2] r4257 - in trunk/coreboot-v2/src/mainboard:
	rca/rm4100 thomson/ip1000
Message-ID: <mailman.3178.1355071537.16123.coreboot@coreboot.org>

Author: linux_junkie
Date: 2009-05-07 07:47:05 +0200 (Thu, 07 May 2009)
New Revision: 4257

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c
Log:
Trivial checksum fixup for irq tables on IP1000 and RM4100.
Signed-off-by: Joseph Smith <joe at settoplinux.org>
Acked-by: Joseph Smith <joe at settoplinux.org>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c	2009-05-07 00:21:02 UTC (rev 4256)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c	2009-05-07 05:47:05 UTC (rev 4257)
@@ -31,7 +31,7 @@
 	0x24c0,		 /* Device */
 	0,		 /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xcd,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
 		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c	2009-05-07 00:21:02 UTC (rev 4256)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c	2009-05-07 05:47:05 UTC (rev 4257)
@@ -31,7 +31,7 @@
 	0x24c0,		 /* Device */
 	0,		 /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xcd,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
 		{0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */




From joe at settoplinux.org  Thu May  7 08:01:18 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 07 May 2009 02:01:18 -0400
Subject: [coreboot] [PATCH] Disable AC97 modem early on IP1000
Message-ID: <4ac5d11995ac3ee312d764588fc39dcf@imap.1and1.com>


This patch disables the AC97 modem via the ICH4 LPC disable function
register early in the boot process. Leaving it enabled was causing resource
allocation problems, making IO read/writes under 0x200 fail. As I found out
by trail and error it has to be done right after the LAN Enable gpio pin is
driven high.

Tested on hardware.
Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Thu May  7 08:09:17 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 07 May 2009 02:09:17 -0400
Subject: [coreboot] [PATCH] Disable AC97 modem early on IP1000
In-Reply-To: <4ac5d11995ac3ee312d764588fc39dcf@imap.1and1.com>
References: <4ac5d11995ac3ee312d764588fc39dcf@imap.1and1.com>
Message-ID: <f925a30ca5b2b324e2ea4bb8d2fcf3a7@imap.1and1.com>



On Thu, 07 May 2009 02:01:18 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> 
> This patch disables the AC97 modem via the ICH4 LPC disable function
> register early in the boot process. Leaving it enabled was causing
> resource
> allocation problems, making IO read/writes under 0x200 fail. As I found
> out
> by trail and error it has to be done right after the LAN Enable gpio pin
> is
> driven high.
> 
> Tested on hardware.
> Signed-off-by: Joseph Smith <joe at settoplinux.org>
> 
oops patch attached...
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From joe at settoplinux.org  Thu May  7 08:12:00 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 07 May 2009 02:12:00 -0400
Subject: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for IP1000
	and RM4100
Message-ID: <e12ec56ac26976460c1dedd24d74e191@imap.1and1.com>

This patch sets up PIRQs in mainboard Config.lb for IP1000 and RM4100
instead of using the ones in i82801xx_lpc.c

Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From joe at settoplinux.org  Thu May  7 08:16:55 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 07 May 2009 02:16:55 -0400
Subject: [coreboot] [ANN] Port of GPL vgabios to gcc
In-Reply-To: <20090507035324.GA25815@morn.localdomain>
References: <20090507035324.GA25815@morn.localdomain>
Message-ID: <5964d7ad7320b517467812b4bdb10724@imap.1and1.com>




On Wed, 6 May 2009 23:53:24 -0400, Kevin O'Connor <kevin at koconnor.net>
wrote:
> I have made an initial pass at porting the open source vgabios at:
> 
> http://www.nongnu.org/vgabios/
> 
> from bcc/as86 to gcc.
> 
> The new code can be found in the SeaBIOS git repository.  To download
> and build the code use:
> 
> git clone git://git.linuxtogo.org/home/kevin/seabios.git
> cd seabios/
> make out/vgabios.bin
> 
> The resulting binary can be used on qemu.  For example:
> 
> cd seabios/
> make
> make out/vgabios.bin
> cp out/*.bin ../testqemu/
> qemu -L ../testqemu/ -hda myimage
> 
> 
> This new vga code is still preliminary.  I can start qemu, but there
> are known bugs and unimplemented features.
> 
> The goal of porting the vga bios to gcc is to make the code more
> understandable and easier to modify.  The code could potentially be
> enhanced to run on real hardware.  (The current code will only run on
> emulators.)
> 
Real Hardware? That would be really cool :-)

Great Work!!

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From paulepanter at users.sourceforge.net  Thu May  7 09:21:01 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 07 May 2009 09:21:01 +0200
Subject: [coreboot] [ANN] Port of GPL vgabios to gcc
In-Reply-To: <20090507035324.GA25815@morn.localdomain>
References: <20090507035324.GA25815@morn.localdomain>
Message-ID: <1241680861.5960.3.camel@mattotaupa.wohnung.familie-menzel.net>

Am Mittwoch, den 06.05.2009, 23:53 -0400 schrieb Kevin O'Connor:

[?]

> The new code can be found in the SeaBIOS git repository.  To download
> and build the code use:
> 
> git clone git://git.linuxtogo.org/home/kevin/seabios.git
> cd seabios/
> make out/vgabios.bin

I am wondering, if a separate repository would be more suitable for
example because of the commit log. Or are vgabios and SeaBIOS so similar
or going to be merged somehow?


Thanks for your work,

Paul
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From c-d.hailfinger.devel.2006 at gmx.net  Thu May  7 13:44:10 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 07 May 2009 13:44:10 +0200
Subject: [coreboot] [PATCH] flashrom: Check return codes of spi_write_enable
In-Reply-To: <20090507033714.3301.qmail@stuge.se>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>
	<20090507033714.3301.qmail@stuge.se>
Message-ID: <4A02C98A.7090504@gmx.net>

Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
should handle such special opcode failure gracefully on ICH and
compatible chipsets.

This fixes chip erase on almost all ICH+VIA SPI masters.

Thanks to Ali Nadalizadeh for helping track down this bug!

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Patch inline and attached.

Index: flashrom-spi_write_enable_error_checking/it87spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/it87spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/it87spi.c	(Arbeitskopie)
@@ -196,11 +196,16 @@
 }
 
 /* Page size is usually 256 bytes */
-static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
+static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
 {
 	int i;
+	int result;
 
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed\n");
+		return result;
+	}
 	OUTB(0x06, it8716f_flashport + 1);
 	OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
 	for (i = 0; i < 256; i++) {
@@ -212,6 +217,7 @@
 	 */
 	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 		usleep(1000);
+	return 0;
 }
 
 /*
@@ -222,12 +228,17 @@
 {
 	int total_size = 1024 * flash->total_size;
 	int i;
+	int result;
 
 	fast_spi = 0;
 
 	spi_disable_blockprotect();
 	for (i = 0; i < total_size; i++) {
-		spi_write_enable();
+		result = spi_write_enable();
+		if (result) {
+			printf_debug("spi_write_enable failed\n");
+			return result;
+		}
 		spi_byte_program(i, buf[i]);
 		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 			myusec_delay(10);
Index: flashrom-spi_write_enable_error_checking/spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/spi.c	(Arbeitskopie)
@@ -362,7 +362,16 @@
 	}
 	result = spi_write_enable();
 	if (result) {
-		printf_debug("spi_write_enable failed\n");
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
 		return result;
 	}
 	/* Send CE (Chip Erase) */
@@ -392,8 +401,17 @@
 	}
 	result = spi_write_enable();
 	if (result) {
-		printf_debug("spi_write_enable failed\n");
-		return result;
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
+		//return result;
 	}
 	/* Send CE (Chip Erase) */
 	result = spi_command(sizeof(cmd), 0, cmd, NULL);
@@ -424,11 +442,25 @@
 int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
+	int result;
 
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
+		return result;
+	}
 	/* Send BE (Block Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -447,11 +479,25 @@
 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
+	int result;
 
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
+		return result;
+	}
 	/* Send BE (Block Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -489,11 +535,26 @@
 int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE };
+	int result;
+	
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
 
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
+		return result;
+	}
 	/* Send SE (Sector Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -623,6 +684,8 @@
 {
 	uint32_t pos = 2, size = flash->total_size * 1024;
 	unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
+	int result;
+
 	switch (flashbus) {
 	case BUS_TYPE_WBSIO_SPI:
 		fprintf(stderr, "%s: impossible with Winbond SPI masters,"
@@ -632,7 +695,20 @@
 		break;
 	}
 	flash->erase(flash);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring");
+			break;
+		default:
+			printf_debug("\n");
+		}
+		return result;
+	}
 	spi_command(6, 0, w, NULL);
 	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 		myusec_delay(5); /* SST25VF040B Tbp is max 10us */
Index: flashrom-spi_write_enable_error_checking/wbsio_spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/wbsio_spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/wbsio_spi.c	(Arbeitskopie)
@@ -189,6 +189,7 @@
 int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
 {
 	int pos, size = flash->total_size * 1024;
+	int result;
 
 	if (flash->total_size > 1024) {
 		fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
@@ -196,7 +197,11 @@
 	}
 
 	flash->erase(flash);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result) {
+		printf_debug("spi_write_enable failed\n");
+		return result;
+	}
 	for (pos = 0; pos < size; pos++) {
 		spi_byte_program(pos, buf[pos]);
 		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)


-- 
http://www.hailfinger.org/

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From r.marek at assembler.cz  Thu May  7 13:33:55 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 07 May 2009 13:33:55 +0200
Subject: [coreboot] [ANN] Port of GPL vgabios to gcc
In-Reply-To: <20090507035324.GA25815@morn.localdomain>
References: <20090507035324.GA25815@morn.localdomain>
Message-ID: <4A02C723.1090102@assembler.cz>

Hi Kevin,

Great,  I think this is what libv or I need.  I have in plan to create 
some simple mode3 only VGA rom for K8M890.

I have some questions:

Have you spoken with orig authors? Maybe they want such rewrite too
Is it really GPLv3? I thought it was LGPL.

The resulting rom image is independed to seabios right?

Thanks,
Rudolf


Kevin O'Connor wrote:
> I have made an initial pass at porting the open source vgabios at:
>
> http://www.nongnu.org/vgabios/
>
> from bcc/as86 to gcc.
>
> The new code can be found in the SeaBIOS git repository.  To download
> and build the code use:
>
> git clone git://git.linuxtogo.org/home/kevin/seabios.git
> cd seabios/
> make out/vgabios.bin
>
> The resulting binary can be used on qemu.  For example:
>
> cd seabios/
> make
> make out/vgabios.bin
> cp out/*.bin ../testqemu/
> qemu -L ../testqemu/ -hda myimage
>
>
> This new vga code is still preliminary.  I can start qemu, but there
> are known bugs and unimplemented features.
>
> The goal of porting the vga bios to gcc is to make the code more
> understandable and easier to modify.  The code could potentially be
> enhanced to run on real hardware.  (The current code will only run on
> emulators.)
>
> -Kevin
>
>   




From c-d.hailfinger.devel.2006 at gmx.net  Thu May  7 14:18:29 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 07 May 2009 14:18:29 +0200
Subject: [coreboot] [PATCH] flashrom: Check return codes of
	spi_write_enable
In-Reply-To: <4A02C98A.7090504@gmx.net>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com>	<20090507033714.3301.qmail@stuge.se>
	<4A02C98A.7090504@gmx.net>
Message-ID: <4A02D195.8040505@gmx.net>

On 07.05.2009 13:44, Carl-Daniel Hailfinger wrote:
> Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
> should handle such special opcode failure gracefully on ICH and
> compatible chipsets.
>
> This fixes chip erase on almost all ICH+VIA SPI masters.
>
> Thanks to Ali Nadalizadeh for helping track down this bug!
>   

Improved version, refactored to isolate the impact to a single function.

As a bonus, all invocations of spi_write_enable() now have error checking.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-spi_write_enable_error_checking/it87spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/it87spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/it87spi.c	(Arbeitskopie)
@@ -196,11 +196,14 @@
 }
 
 /* Page size is usually 256 bytes */
-static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
+static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
 {
 	int i;
+	int result;
 
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	OUTB(0x06, it8716f_flashport + 1);
 	OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
 	for (i = 0; i < 256; i++) {
@@ -212,6 +215,7 @@
 	 */
 	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 		usleep(1000);
+	return 0;
 }
 
 /*
@@ -222,12 +226,15 @@
 {
 	int total_size = 1024 * flash->total_size;
 	int i;
+	int result;
 
 	fast_spi = 0;
 
 	spi_disable_blockprotect();
 	for (i = 0; i < total_size; i++) {
-		spi_write_enable();
+		result = spi_write_enable();
+		if (result)
+			return result;
 		spi_byte_program(i, buf[i]);
 		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 			myusec_delay(10);
Index: flashrom-spi_write_enable_error_checking/spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/spi.c	(Arbeitskopie)
@@ -88,9 +88,24 @@
 int spi_write_enable(void)
 {
 	const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
+	int result;
 
 	/* Send WREN (Write Enable) */
-	return spi_command(sizeof(cmd), 0, cmd, NULL);
+	result = spi_command(sizeof(cmd), 0, cmd, NULL);
+	if (result) {
+		printf_debug("spi_write_enable failed");
+		switch (flashbus) {
+		case BUS_TYPE_ICH7_SPI:
+		case BUS_TYPE_ICH9_SPI:
+		case BUS_TYPE_VIA_SPI:
+			printf_debug(" due to SPI master limitation, ignoring"
+				     " and hoping it will be run as PREOP\n");
+			return 0;
+		default:
+			printf_debug("\n");
+		}
+	}
+	return result;
 }
 
 int spi_write_disable(void)
@@ -361,10 +376,8 @@
 		return result;
 	}
 	result = spi_write_enable();
-	if (result) {
-		printf_debug("spi_write_enable failed\n");
+	if (result)
 		return result;
-	}
 	/* Send CE (Chip Erase) */
 	result = spi_command(sizeof(cmd), 0, cmd, NULL);
 	if (result) {
@@ -391,10 +404,8 @@
 		return result;
 	}
 	result = spi_write_enable();
-	if (result) {
-		printf_debug("spi_write_enable failed\n");
+	if (result)
 		return result;
-	}
 	/* Send CE (Chip Erase) */
 	result = spi_command(sizeof(cmd), 0, cmd, NULL);
 	if (result) {
@@ -424,11 +435,14 @@
 int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
+	int result;
 
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	/* Send BE (Block Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -447,11 +461,14 @@
 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
+	int result;
 
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	/* Send BE (Block Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -489,11 +506,15 @@
 int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
 {
 	unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE };
+	int result;
+	
 	cmd[1] = (addr & 0x00ff0000) >> 16;
 	cmd[2] = (addr & 0x0000ff00) >> 8;
 	cmd[3] = (addr & 0x000000ff);
 
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	/* Send SE (Sector Erase) */
 	spi_command(sizeof(cmd), 0, cmd, NULL);
 	/* Wait until the Write-In-Progress bit is cleared.
@@ -623,6 +644,8 @@
 {
 	uint32_t pos = 2, size = flash->total_size * 1024;
 	unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
+	int result;
+
 	switch (flashbus) {
 	case BUS_TYPE_WBSIO_SPI:
 		fprintf(stderr, "%s: impossible with Winbond SPI masters,"
@@ -632,7 +655,9 @@
 		break;
 	}
 	flash->erase(flash);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	spi_command(6, 0, w, NULL);
 	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
 		myusec_delay(5); /* SST25VF040B Tbp is max 10us */
Index: flashrom-spi_write_enable_error_checking/wbsio_spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/wbsio_spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/wbsio_spi.c	(Arbeitskopie)
@@ -189,6 +189,7 @@
 int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
 {
 	int pos, size = flash->total_size * 1024;
+	int result;
 
 	if (flash->total_size > 1024) {
 		fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
@@ -196,7 +197,9 @@
 	}
 
 	flash->erase(flash);
-	spi_write_enable();
+	result = spi_write_enable();
+	if (result)
+		return result;
 	for (pos = 0; pos < size; pos++) {
 		spi_byte_program(pos, buf[pos]);
 		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Index: flashrom-spi_write_enable_error_checking/sb600spi.c
===================================================================
--- flashrom-spi_write_enable_error_checking/sb600spi.c	(Revision 471)
+++ flashrom-spi_write_enable_error_checking/sb600spi.c	(Arbeitskopie)
@@ -68,6 +68,7 @@
 {
 	int rc = 0, i;
 	int total_size = flash->total_size * 1024;
+	int result;
 
 	/* Erase first */
 	printf("Erasing flash before programming... ");
@@ -77,7 +78,9 @@
 	printf("Programming flash");
 	for (i = 0; i < total_size; i++, buf++) {
 		spi_disable_blockprotect();
-		spi_write_enable();
+		result = spi_write_enable();
+		if (result)
+			return result;
 		spi_byte_program(i, *buf);
 		/* wait program complete. */
 		if (i % 0x8000 == 0)


-- 
http://www.hailfinger.org/

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From stanne at gmail.com  Thu May  7 14:23:51 2009
From: stanne at gmail.com (Stan Yong)
Date: Thu, 7 May 2009 20:23:51 +0800
Subject: [coreboot] [flashrom] Transaction Error with opcode 0x03
	failed...
In-Reply-To: <a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
References: <e30f44360905060233vee90cbcq22f097cdd13e8c59@mail.gmail.com>
	<a505dc9d0905060841r7c044191o3d6bab28279310b9@mail.gmail.com>
Message-ID: <e30f44360905070523q311c500ey65f5e5661a1eb458@mail.gmail.com>

Hi,

Thanks for the explanation. After looking at the ICH9 specification, i'm
thinking of modifying the FRAP register value in order to enable write and
read permission to all the region. However, i have a question:

How to exactly use flashrom to bring the SPI into descriptor mode so that i
can do a read and write to FRAP? Or is that even possible?

Thanks.

On Wed, May 6, 2009 at 11:41 PM, FENG Yu Ning <fengyuning1984 at gmail.com>wrote:

> Stan Yong wrote:
> > I'm having problems with the flashrom on my system. ...
> > Can provide some advice on this?
>
> I can only tell the reason. Your current BIOS prevents flashrom from
> reading certain part of the flash chip. I don't know if there is any
> way to bypass that setting.
>
> If you are interested in further explanation on the flashrom output,
> please read on.
>
> > ich_spi_read_page: offset=45056, number=256, buf=0163B020
> > BBAR: 0x0
> > Transaction error!
> > run OPCODE 0x03 failed
> > Error readingdone.
>
> Error occurs here, when flashrom tries to read data at offset 45056
> from the flash chip. 45056(dec) = b000(hex).
>
> Look at FREG2.
> > 0x5C: 0x023f000b (FREG2)
> The value 0x0(23f)0(00b) means, the area in the flash chip from
> 0x00(00b)000 to 0x00(23f)fff belongs to (F)lash (REG)ion (2), which
> stores data for the "Management Engine". That is, flashrom runs into
> error when it is trying to read FREG2.
>
> Now look at FRAP.
> > 0x50: 0x00001a1b (FRAP)
> The least significant byte '1b' indicates which regions software can
> read. Expand it to binary, 00011011. That means the software can read
> FREG0, FREG1, FREG3 and FREG4 but not FREG2. That is why flashrom runs
> into error at offset 45056.
>
> yu ning
>
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From nadalizadeh at gmail.com  Thu May  7 14:37:38 2009
From: nadalizadeh at gmail.com (Ali Nadalizadeh)
Date: Thu, 7 May 2009 17:07:38 +0430
Subject: [coreboot] [PATCH] flashrom: Check return codes of
	spi_write_enable
In-Reply-To: <4A02D195.8040505@gmx.net>
References: <5e5c5ae40905060952u45d1258bs18ac65c7664deeb9@mail.gmail.com> 
	<20090507033714.3301.qmail@stuge.se> <4A02C98A.7090504@gmx.net> 
	<4A02D195.8040505@gmx.net>
Message-ID: <5e5c5ae40905070537p45dbf35egbe9900116ee4b21d@mail.gmail.com>

Erasing Confirmed working on my hardware :
chip-set : "Intel ICH7M"
chip : "SST SST25VF080B"

Output image is now completely full of 0xFF (s)

Regards --
Ali Nadalizadeh

On Thu, May 7, 2009 at 4:48 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 07.05.2009 13:44, Carl-Daniel Hailfinger wrote:
> > Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
> > should handle such special opcode failure gracefully on ICH and
> > compatible chipsets.
> >
> > This fixes chip erase on almost all ICH+VIA SPI masters.
> >
> > Thanks to Ali Nadalizadeh for helping track down this bug!
> >
>
> Improved version, refactored to isolate the impact to a single function.
>
> As a bonus, all invocations of spi_write_enable() now have error checking.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Index: flashrom-spi_write_enable_error_checking/it87spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/it87spi.c  (Revision 471)
> +++ flashrom-spi_write_enable_error_checking/it87spi.c  (Arbeitskopie)
> @@ -196,11 +196,14 @@
>  }
>
>  /* Page size is usually 256 bytes */
> -static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t
> *bios)
> +static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t
> *bios)
>  {
>        int i;
> +       int result;
>
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        OUTB(0x06, it8716f_flashport + 1);
>        OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
>        for (i = 0; i < 256; i++) {
> @@ -212,6 +215,7 @@
>          */
>        while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>                usleep(1000);
> +       return 0;
>  }
>
>  /*
> @@ -222,12 +226,15 @@
>  {
>        int total_size = 1024 * flash->total_size;
>        int i;
> +       int result;
>
>        fast_spi = 0;
>
>        spi_disable_blockprotect();
>        for (i = 0; i < total_size; i++) {
> -               spi_write_enable();
> +               result = spi_write_enable();
> +               if (result)
> +                       return result;
>                spi_byte_program(i, buf[i]);
>                while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>                        myusec_delay(10);
> Index: flashrom-spi_write_enable_error_checking/spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/spi.c      (Revision 471)
> +++ flashrom-spi_write_enable_error_checking/spi.c      (Arbeitskopie)
> @@ -88,9 +88,24 @@
>  int spi_write_enable(void)
>  {
>        const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
> +       int result;
>
>        /* Send WREN (Write Enable) */
> -       return spi_command(sizeof(cmd), 0, cmd, NULL);
> +       result = spi_command(sizeof(cmd), 0, cmd, NULL);
> +       if (result) {
> +               printf_debug("spi_write_enable failed");
> +               switch (flashbus) {
> +               case BUS_TYPE_ICH7_SPI:
> +               case BUS_TYPE_ICH9_SPI:
> +               case BUS_TYPE_VIA_SPI:
> +                       printf_debug(" due to SPI master limitation,
> ignoring"
> +                                    " and hoping it will be run as
> PREOP\n");
> +                       return 0;
> +               default:
> +                       printf_debug("\n");
> +               }
> +       }
> +       return result;
>  }
>
>  int spi_write_disable(void)
> @@ -361,10 +376,8 @@
>                return result;
>         }
>        result = spi_write_enable();
> -       if (result) {
> -               printf_debug("spi_write_enable failed\n");
> +       if (result)
>                 return result;
> -       }
>        /* Send CE (Chip Erase) */
>        result = spi_command(sizeof(cmd), 0, cmd, NULL);
>         if (result) {
> @@ -391,10 +404,8 @@
>                return result;
>         }
>        result = spi_write_enable();
> -       if (result) {
> -               printf_debug("spi_write_enable failed\n");
> +       if (result)
>                 return result;
> -       }
>        /* Send CE (Chip Erase) */
>        result = spi_command(sizeof(cmd), 0, cmd, NULL);
>         if (result) {
> @@ -424,11 +435,14 @@
>  int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
>  {
>        unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
> +       int result;
>
>        cmd[1] = (addr & 0x00ff0000) >> 16;
>        cmd[2] = (addr & 0x0000ff00) >> 8;
>        cmd[3] = (addr & 0x000000ff);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        /* Send BE (Block Erase) */
>        spi_command(sizeof(cmd), 0, cmd, NULL);
>        /* Wait until the Write-In-Progress bit is cleared.
> @@ -447,11 +461,14 @@
>  int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
>  {
>        unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
> +       int result;
>
>        cmd[1] = (addr & 0x00ff0000) >> 16;
>        cmd[2] = (addr & 0x0000ff00) >> 8;
>        cmd[3] = (addr & 0x000000ff);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        /* Send BE (Block Erase) */
>        spi_command(sizeof(cmd), 0, cmd, NULL);
>        /* Wait until the Write-In-Progress bit is cleared.
> @@ -489,11 +506,15 @@
>  int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
>  {
>        unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE };
> +       int result;
> +
>        cmd[1] = (addr & 0x00ff0000) >> 16;
>        cmd[2] = (addr & 0x0000ff00) >> 8;
>        cmd[3] = (addr & 0x000000ff);
>
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        /* Send SE (Sector Erase) */
>        spi_command(sizeof(cmd), 0, cmd, NULL);
>        /* Wait until the Write-In-Progress bit is cleared.
> @@ -623,6 +644,8 @@
>  {
>        uint32_t pos = 2, size = flash->total_size * 1024;
>        unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
> +       int result;
> +
>        switch (flashbus) {
>        case BUS_TYPE_WBSIO_SPI:
>                fprintf(stderr, "%s: impossible with Winbond SPI masters,"
> @@ -632,7 +655,9 @@
>                 break;
>        }
>        flash->erase(flash);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        spi_command(6, 0, w, NULL);
>        while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>                myusec_delay(5); /* SST25VF040B Tbp is max 10us */
> Index: flashrom-spi_write_enable_error_checking/wbsio_spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/wbsio_spi.c        (Revision
> 471)
> +++ flashrom-spi_write_enable_error_checking/wbsio_spi.c
>  (Arbeitskopie)
> @@ -189,6 +189,7 @@
>  int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
>  {
>        int pos, size = flash->total_size * 1024;
> +       int result;
>
>        if (flash->total_size > 1024) {
>                fprintf(stderr, "%s: Winbond saved on 4 register bits so max
> chip size is 1024 KB!\n", __func__);
> @@ -196,7 +197,9 @@
>         }
>
>        flash->erase(flash);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        for (pos = 0; pos < size; pos++) {
>                spi_byte_program(pos, buf[pos]);
>                while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
> Index: flashrom-spi_write_enable_error_checking/sb600spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/sb600spi.c (Revision 471)
> +++ flashrom-spi_write_enable_error_checking/sb600spi.c (Arbeitskopie)
> @@ -68,6 +68,7 @@
>  {
>        int rc = 0, i;
>        int total_size = flash->total_size * 1024;
> +       int result;
>
>        /* Erase first */
>        printf("Erasing flash before programming... ");
> @@ -77,7 +78,9 @@
>        printf("Programming flash");
>        for (i = 0; i < total_size; i++, buf++) {
>                spi_disable_blockprotect();
> -               spi_write_enable();
> +               result = spi_write_enable();
> +               if (result)
> +                       return result;
>                spi_byte_program(i, *buf);
>                /* wait program complete. */
>                if (i % 0x8000 == 0)
>
>
> --
> http://www.hailfinger.org/
>
>
> Index: flashrom-spi_write_enable_error_checking/it87spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/it87spi.c  (Revision 471)
> +++ flashrom-spi_write_enable_error_checking/it87spi.c  (Arbeitskopie)
> @@ -196,11 +196,14 @@
>  }
>
>  /* Page size is usually 256 bytes */
> -static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t
> *bios)
> +static int it8716f_spi_page_program(int block, uint8_t *buf, uint8_t
> *bios)
>  {
>        int i;
> +       int result;
>
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        OUTB(0x06, it8716f_flashport + 1);
>        OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
>        for (i = 0; i < 256; i++) {
> @@ -212,6 +215,7 @@
>         */
>        while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>                usleep(1000);
> +       return 0;
>  }
>
>  /*
> @@ -222,12 +226,15 @@
>  {
>        int total_size = 1024 * flash->total_size;
>        int i;
> +       int result;
>
>        fast_spi = 0;
>
>        spi_disable_blockprotect();
>        for (i = 0; i < total_size; i++) {
> -               spi_write_enable();
> +               result = spi_write_enable();
> +               if (result)
> +                       return result;
>                spi_byte_program(i, buf[i]);
>                while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>                        myusec_delay(10);
> Index: flashrom-spi_write_enable_error_checking/spi.c
> ===================================================================
> --- flashrom-spi_write_enable_error_checking/spi.c      (Revision 471)
> +++ flashrom-spi_write_enable_error_checking/spi.c      (Arbeitskopie)
> @@ -88,9 +88,24 @@
>  int spi_write_enable(void)
>  {
>        const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
> +       int result;
>
>        /* Send WREN (Write Enable) */
> -       return spi_command(sizeof(cmd), 0, cmd, NULL);
> +       result = spi_command(sizeof(cmd), 0, cmd, NULL);
> +       if (result) {
> +               printf_debug("spi_write_enable failed");
> +               switch (flashbus) {
> +               case BUS_TYPE_ICH7_SPI:
> +               case BUS_TYPE_ICH9_SPI:
> +               case BUS_TYPE_VIA_SPI:
> +                       printf_debug(" due to SPI master limitation,
> ignoring"
> +                                    " and hoping it will be run as
> PREOP\n");
> +                       return 0;
> +               default:
> +                       printf_debug("\n");
> +               }
> +       }
> +       return result;
>  }
>
>  int spi_write_disable(void)
> @@ -361,10 +376,8 @@
>                return result;
>        }
>        result = spi_write_enable();
> -       if (result) {
> -               printf_debug("spi_write_enable failed\n");
> +       if (result)
>                return result;
> -       }
>        /* Send CE (Chip Erase) */
>        result = spi_command(sizeof(cmd), 0, cmd, NULL);
>        if (result) {
> @@ -391,10 +404,8 @@
>                return result;
>        }
>        result = spi_write_enable();
> -       if (result) {
> -               printf_debug("spi_write_enable failed\n");
> +       if (result)
>                return result;
> -       }
>        /* Send CE (Chip Erase) */
>        result = spi_command(sizeof(cmd), 0, cmd, NULL);
>        if (result) {
> @@ -424,11 +435,14 @@
>  int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
>  {
>        unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
> +       int result;
>
>        cmd[1] = (addr & 0x00ff0000) >> 16;
>        cmd[2] = (addr & 0x0000ff00) >> 8;
>        cmd[3] = (addr & 0x000000ff);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        /* Send BE (Block Erase) */
>        spi_command(sizeof(cmd), 0, cmd, NULL);
>        /* Wait until the Write-In-Progress bit is cleared.
> @@ -447,11 +461,14 @@
>  int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
>  {
>        unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
> +       int result;
>
>        cmd[1] = (addr & 0x00ff0000) >> 16;
>        cmd[2] = (addr & 0x0000ff00) >> 8;
>        cmd[3] = (addr & 0x000000ff);
> -       spi_write_enable();
> +       result = spi_write_enable();
> +       if (result)
> +               return result;
>        /* Send BE (Block Erase) */
>        spi_command(sizeof(cmd), 0, cmd, NULL);
>