[coreboot] cbfs XIP patch
c-d.hailfinger.devel.2006 at gmx.net
Tue May 5 21:35:00 CEST 2009
On 05.05.2009 19:54, Myles Watson wrote:
> On Tue, May 5, 2009 at 11:50 AM, Peter Stuge <peter at stuge.se> wrote:
>> ron minnich wrote:
>>> how many flash chips support 'erase byte' at this point (I honestly
>>> don't know!). I.e., isn't an update of any one byte in a block
>>> going to wipe out a whole block? How many cbfs files fit on neat
>>> 64k or 16k or whatever boundaries?
>> None have single byte erase blocks, but most of the SPI flash chips
>> can actually do 256 byte erase blocks.
> Since erase block granularity is chip dependent, shouldn't flashrom be
> in charge of touching the minimal number of blocks? I don't see how
> CBFS can know which chip it will be used in.
Yes. I need to resend the flashrom patches solving this.
>> I think it is important to keep the alignment in mind, so that files
>> can be fit onto boundaries. I also think we should try to do it in
>> the normal case.
> What's the most common boundary? 1K, 2K, 4K? Should we pick one that
> is reasonable?
There is no common boundary. It all depends on how much you're willing
to pay per chip. I've seen anything from 256 Bytes to 64 kBytes as erase
granularity for SPI chips currently in production. Of course, some chips
have non-uniform erase sizes. That makes it even harder to handle.
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