[coreboot] flashrom: State of development
c-d.hailfinger.devel.2006 at gmx.net
Fri May 8 03:05:00 CEST 2009
the following flashrom patches from me are pending:
- SB600 SPI hang fix. Needs a test on SPI and a test on LPC.
- VIA/ICH SPI workaround for standalone WRITE_ENABLE opcodes. This fix
is URGENT. The bug already messed up flash contents of one machine.
- SPI one-byte write support. This fix is URGENT. The bug already messed
up flash contents of one machine.
- ICH SPI delay change. Reduces a multi-hour flashing of an 8 Mbit chip
on ICH/VIA to one minute.
- Generic SPI chip detection.
- JEDEC probe check whether we really read the ID or just flash chip
- Better error handling in ICH SPI.
- Generic block-wise erase infrastructure.
- Block-wise erase for a dozen chips.
- Multiple probe functions per chip preparation (e.g. RDID, REMS, RES
- Explicit read functions for all chips. Needed for external flasher
- External flasher infrastructure ready for hooking up.
Some of them have been waiting for an ack since over 6 months, some are
I appreciate reviews. Resending patches is possible if needed.
The patches marked as URGENT will be self-acked and checked in unless I
get a review in the next 24 hours because I'm not in the mood for
debugging and fixing an almost-bricked laptop via IRC for over 16 hours
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