[coreboot] [v2] r4267 - trunk/coreboot-v2/src/superio/ite/it8718f

svn at coreboot.org svn at coreboot.org
Mon May 11 15:45:11 CEST 2009


Author: uwe
Date: 2009-05-11 15:45:11 +0200 (Mon, 11 May 2009)
New Revision: 4267

Modified:
   trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c
Log:
We should separate the it8718f_24mhz_clkin like the way IT8712 does.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by; Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c	2009-05-11 01:44:54 UTC (rev 4266)
+++ trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c	2009-05-11 13:45:11 UTC (rev 4267)
@@ -45,10 +45,9 @@
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8718F Super I/O chip. */
-static void it8718f_enable_serial(device_t dev, unsigned iobase)
+static void it8718f_enter_conf(void)
 {
-	/* (1) Enter the configuration state (MB PnP mode). */
+	/*  Enter the configuration state (MB PnP mode). */
 
 	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
 	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
@@ -57,7 +56,30 @@
 	outb(0x01, IT8718F_CONFIGURATION_PORT);
 	outb(0x55, IT8718F_CONFIGURATION_PORT);
 	outb(0x55, IT8718F_CONFIGURATION_PORT);
+}
 
+static void it8718f_exit_conf(void)
+{
+	/* Exit the configuration state (MB PnP mode). */
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+}
+
+static void it8718f_24mhz_clkin(void)
+{
+	it8718f_enter_conf();
+
+	/* Select 24MHz CLKIN (48MHZ default)*/
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
+
+	it8718f_exit_conf();
+}
+
+/* Enable the peripheral devices on the IT8718F Super I/O chip. */
+static void it8718f_enable_serial(device_t dev, unsigned iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8718f_enter_conf();
+
 	/* (2) Modify the data of configuration registers. */
 
 	/* Select the chip to configure (if there's more than one).
@@ -65,17 +87,14 @@
            If this register is not written, both chips are configured. */
 	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
 
-	/* Enable all devices. */
+	/* Enable serial port(s). */
 	it8718f_sio_write(IT8718F_SP1,  0x30, 0x1); /* Serial port 1 */
 	it8718f_sio_write(IT8718F_SP2,  0x30, 0x1); /* Serial port 2 */
 
-	/* Select 24MHz CLKIN (set bit 0). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01);
-
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+	it8718f_exit_conf();
 }
 





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