[coreboot] [v2] r4269 - in trunk/coreboot-v2/src: cpu/emulation/qemu-x86 mainboard/emulation/qemu-x86 southbridge/intel/i82371eb
svn at coreboot.org
svn at coreboot.org
Tue May 12 00:44:15 CEST 2009
Author: myles
Date: 2009-05-12 00:44:14 +0200 (Tue, 12 May 2009)
New Revision: 4269
Modified:
trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
Log:
This patch adds high table support to qemu. It was already added to
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-05-11 22:24:53 UTC (rev 4268)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-05-11 22:44:14 UTC (rev 4269)
@@ -65,6 +65,11 @@
return tolm;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {
@@ -110,7 +115,14 @@
/* Report the memory regions. */
idx = 10;
- ram_resource(dev, idx++, 0, tolmk);
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, tolmk - 768);
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
assign_resources(&dev->link[0]);
}
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-05-11 22:24:53 UTC (rev 4268)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-05-11 22:44:14 UTC (rev 4269)
@@ -31,6 +31,7 @@
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
+uses HAVE_HIGH_TABLES
uses CROSS_COMPILE
uses CC
uses HOSTCC
@@ -80,6 +81,8 @@
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
+default HAVE_HIGH_TABLES=1
+
##
## Build code to export a CMOS option table
##
Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-05-11 22:24:53 UTC (rev 4268)
+++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-05-11 22:44:14 UTC (rev 4269)
@@ -70,3 +70,9 @@
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
};
+
+static const struct pci_driver isa_SB_driver __pci_driver = {
+ .ops = &isa_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82371SB_ISA,
+};
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