[coreboot] [v2] r4238 - in trunk/coreboot-v2/src/northbridge: amd/amdfam10 amd/gx1 amd/gx2 amd/lx intel/e7501 intel/e7520 intel/e7525 intel/i3100 intel/i440bx intel/i82810 intel/i82830 intel/i855gme intel/i855pm via/cn700 via/cx700 via/vt8601 via/vt8623
Kevin O'Connor
kevin at koconnor.net
Sat May 16 04:01:09 CEST 2009
On Thu, Apr 30, 2009 at 03:58:42PM +0200, svn at coreboot.org wrote:
> Author: stepan
> Date: 2009-04-30 15:58:42 +0200 (Thu, 30 Apr 2009)
> New Revision: 4238
[...]
> Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
> ===================================================================
> --- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237)
> +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238)
> @@ -163,6 +163,12 @@
> return tolm;
> }
>
> +#if HAVE_HIGH_TABLES==1
> +/* maximum size of high tables in KB */
> +#define HIGH_TABLES_SIZE 64
> +extern uint64_t high_tables_base, high_tables_size;
> +#endif
> +
> static void pci_domain_set_resources(device_t dev)
> {
> /* The order is important to find the correct RAM size. */
> @@ -199,6 +205,13 @@
> /* The PCI hole does does not overlap the memory. */
> tolmk = tomk;
> }
> +
> +#if HAVE_HIGH_TABLES == 1
> + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
> + high_tables_size = HIGH_TABLES_SIZE* 1024;
> + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
> +#endif
> +
The above is not correct. It places the high tables over the vga
memory.
-Kevin
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