[coreboot] [PATCH] flashrom support for SiliconImage SATA controllers

Uwe Hermann uwe at hermann-uwe.de
Sun May 17 21:24:27 CEST 2009


On Sun, May 17, 2009 at 06:49:52PM +0200, Rudolf Marek wrote:
> This patch adds support for BIOS flashing on the all SiliconImage SATA
> controllers. It was easy because
> 
> 1) flashrom has now nice API
> 2) documentation is public on the web site
> 
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

But see below...


> PS: maybe we could write to that company and tell them. For Windows/Linux they
> force the customer to download freedos from sourceforge ;)

Sure, go ahead :)


> Index: sata_sil.c
> ===================================================================
> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> +++ sata_sil.c	2009-05-17 18:13:19.683305043 +0200
> +#define PCI_VENDOR_ID_SIL	0x1095
> +
> +uint8_t *sil_bar;
> +uint16_t id;
> +
> +struct pcidev_status satas_sil[] = {
> +	{0x1095, 0x0680, PCI_NT, "Silicon Image, Inc.", "PCI0680 Ultra ATA-133 Host Controller"},
> +	{0x1095, 0x3114, PCI_OK, "Silicon Image, Inc.", "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"},
> +	{0x1095, 0x3124, PCI_NT, "Silicon Image, Inc.", "SiI 3124 PCI-X Serial ATA Controller"},
> +	{0x1095, 0x3132, PCI_OK, "Silicon Image, Inc.", "SiI 3132 Serial ATA Raid II Controller"},
> +	{0x1095, 0x3512, PCI_NT, "Silicon Image, Inc.", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"},

Please drop the ", Inc." part from the strings for brevity.


> +	/* check if rom cycle are OK */

rom -> ROM


> +void satasil_chip_writeb(uint8_t val, chipaddr addr)
> +{
> +
> +	uint32_t ctrl_reg, addr_reg;

addr_reg should be data_reg, I think.


> +	while ((ctrl_reg = mmio_readl(sil_bar)) & (1 << 25)) ;
> +
> +	/* Mask out unused/reserved bits, set writes and start transaction */
> +	ctrl_reg &= 0xfcf80000;
> +	ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0xffffff);
> +
> +	addr_reg = (mmio_readl((sil_bar + 4)) & ~0xff) | val;
> +	mmio_writel(addr_reg, (sil_bar + 4));
> +	mmio_writel(ctrl_reg, sil_bar);
> +
> +	while (mmio_readl(sil_bar) & (1 << 25)) ;


Uwe.
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