[coreboot] I figured out the static problem.. But..

Joshua McDowell jmcdowell at issisolutions.com
Wed May 20 18:54:57 CEST 2009

Hash: SHA1

flashrom output with -V
- -bash-3.00# ./flashrom -f -r -V -c 28F320C3B test
flashrom v0.9.0-r535
Found candidate at: 00000500-00000c68
Found coreboot table at 0x00000500.
coreboot table found at 0x500.
coreboot header(24) checksum: 30c4 table(1896) checksum: 3619 entries: 13
Vendor ID: Intel, part ID: SE7520JR22D
Found chipset "Intel ICH5/ICH5R", enabling flash write...
BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1

Unknown vendor:board from coreboot table or -m option: Intel:SE7520JR22D

Calibrating delay loop... 1013M loops per second, 100 myus = 198 us. OK.
No EEPROM/flash device found.
Force read (-f -r -c) requested, forcing chip probe success:
flashrom does not support a flash chip named '28F320C3B'.
Run flashrom -L to view the hardware supported in this flashrom version.
- -bash-3.00#

Technical information from Intel

3.4.11     BIOS Flash
The BIOS supports the Intel® 28F320C3B flash part. The flash part is a
4-MB flash ROM with 2MB programmable. The flash ROM contains system
initialization routines, setup utility, and runtime support routines.
The exact layout is subject to change, as determined by Intel. A 128-
KB block is available for storing OEM code (user binary) and custom logos.

 Thanks in advance,

 Joshua McDowell
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

-------------- next part --------------
A non-text attachment was scrubbed...
Name: se7520jr2tpsrev1.pdf
Type: application/pdf
Size: 3159385 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090520/07be4585/attachment.pdf>

More information about the coreboot mailing list