[coreboot] [v2] r4317 - trunk/coreboot-v2/src/northbridge/via/vx800

Richard Smith smithbone at gmail.com
Thu May 28 10:07:08 CEST 2009

Peter Stuge wrote:
> svn at coreboot.org wrote:
>> Make directory hierarchy flat to match the same layout we use
>> for other chipsets, as suggested on IRC.
> I don't agree so much with this but oh well.
> Maybe there will be opportunity for unifying DDR2 code.

If you are going to flatten the structure then you should also probably 
correct the companion chip name.  The code base this was started from 
was vx800 but its been modified for the vx855.  At the time OLPC got the 
code the mods were already made so we don't know exactly what what 
changed from vx800 to vx855.

The vx855 is a subset of the vx800.  The code will probably work on a 
vx800 but I'm sure there are subtle differences.  Perhaps you should 
rename it to be vx8xx and then start dealing with the differences when 
you find them.

In other news... we have our Gen 1.5 hardware booting (OpenFirmware) and 
Linux. Most stuff seems to work but its still in testing.

The bad news is that the vx8xx code won't work on the gen 1.5 ATest 
board as written.  We ended up having to use different RAM chips and so 
there is not an SPD on the ATest.  Also there are various things 
different in the RAM subsystems between the vx555 demo board we had and 
the gen 1.5 Atest.  The code has various bits of hardcoded things for 
the demo board.

The good news is that all of these settings are in the OpenFirmware 
repository.  So you can go get the proper settings.

Is there any sort of facility in the config files for a SPDless board?

Bari:  Sorry I've not yet responded to your graphics email.. I'll try to 
scratch out some time tonight to respond with whats going on in graphics.

Richard A. Smith
smithbone at gmail.com

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