From hansolofalcon at worldnet.att.net  Sun Nov  1 04:21:55 2009
From: hansolofalcon at worldnet.att.net (Gregg C Levine)
Date: Sat, 31 Oct 2009 23:21:55 -0400
Subject: [coreboot] UPDATE YOUR REPOSITORIES
In-Reply-To: <4AEC017F.2060903@coresystems.de>
Message-ID: <2FD015842A334B5F96E57978A6BBAB8D@who8>

Hello!
Okay, suppose we haven't added anything to our checked out repositories, how
do we retrieve these updated ones. Just follow the usual steps for a
checkout of a new one?

--
Gregg C Levine hansolofalcon at worldnet.att.net
"The Force will be with you always." Obi-Wan Kenobi
? 


> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
On
> Behalf Of Stefan Reinauer
> Sent: Saturday, October 31, 2009 5:21 AM
> To: coreboot
> Subject: [coreboot] UPDATE YOUR REPOSITORIES
> 
> Hi,
> 
> as discussed over the last year we finally cleaned up the subversion
> repository structure of the coreboot repository.
> 
> The reasons for this change are:
> - checking out all required utilities with coreboot is easier
> - No more svn externals, as they break https checkouts
> - branching and merging to/from other repositories will be a lot easier.
> - our tree structure more similar to that of other projects
> 
> The tree now roughly looks like this:
> 
> {svn://coreboot.org/coreboot,https://svn.coreboot.org/coreboot}
> |
> +-+ branches
> | +-- coreboot-v1
> | +-- coreboot-v2-newbuild
> |
> +-- tags
> +-+ trunk
>   +-- COPYING
>   +-- documentation
>   +-- Makefile
>   +-- NEWS
>   +-- payloads
>   +-- README
>   +-- src
>   +-- targets
>   +-+ util
>     +-- ...
> 
> So please update your repositories... you can migrate your old
> repositories like this:
> 
> $ cd coreboot-v2
> # make sure all your new files are added with svn add
> $ svn diff > ../migration.diff
> $ cd ..
> $ svn co svn://coreboot.org/coreboot/trunk coreboot
> $ cd coreboot
> $ patch -p0 < ../migration.diff
> 
> That's it. The old repository (svn://coreboot.org/repos/) will stay
> around for another while so all of you have enough time to switch.
> It will, however, be read-only.
> 
> BTW: Those of you behind firewalls can now check out coreboot with a
> single line again:
> $ svn co https://svn.coreboot.org/coreboot/trunk  coreboot
> 
> The wiki, build scripts, and other config files were updated to make
> this as smooth as possible. If you are experiencing trouble despite
> this, please let me know.
> 
> Best regards,
> Stefan Reinauer
> 
> --
> coresystems GmbH b" Brahmsstr. 16 b" D-79104 Freiburg i. Br.
>       Tel.: +49 761 7668825 b" Fax: +49 761 7664613
> Email: info at coresystems.de  b" http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg b" HRB 7656
> GeschC$ftsfC<hrer: Stefan Reinauer b" Ust-IdNr.: DE245674866
> 
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From stepan at coresystems.de  Sun Nov  1 09:21:33 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 1 Nov 2009 09:21:33 +0100
Subject: [coreboot] UPDATE YOUR REPOSITORIES
In-Reply-To: <2FD015842A334B5F96E57978A6BBAB8D@who8>
References: <2FD015842A334B5F96E57978A6BBAB8D@who8>
Message-ID: <4088F067-2B6E-44C2-BDD8-3D6EABB3323F@coresystems.de>

Hi, Gregg,

On Nov 1, 2009, at 4:21, "Gregg C Levine" <hansolofalcon at worldnet.att.net 
 > wrote:

> Hello!
> Okay, suppose we haven't added anything to our checked out  
> repositories, how
> do we retrieve these updated ones. Just follow the usual steps for a
> checkout of a new one?


Absolutely!

In case of trouble check the download instructions in the coreboot  
wiki. I think I fixed them all. :-)

Stefan



>



From svn at coreboot.org  Sun Nov  1 10:18:24 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  1 Nov 2009 10:18:24 +0100
Subject: [coreboot] [v2] r4904 - trunk/src/boot
Message-ID: <mailman.3973.1355071650.16123.coreboot@coreboot.org>

Author: zbao
Date: 2009-11-01 10:18:23 +0100 (Sun, 01 Nov 2009)
New Revision: 4904

Modified:
   trunk/src/boot/selfboot.c
Log:
typo. trivial. Then -> Than.


Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Zheng Bao <zheng.bao at amd.com>


Modified: trunk/src/boot/selfboot.c
===================================================================
--- trunk/src/boot/selfboot.c	2009-10-31 22:13:04 UTC (rev 4903)
+++ trunk/src/boot/selfboot.c	2009-11-01 09:18:23 UTC (rev 4904)
@@ -105,7 +105,7 @@
  * - Nearly arbitrary standalone executables can be loaded.
  * - Coreboot is preserved, so it can be returned to.
  * - The implementation is still relatively simple,
- *   and much simpler then the general case implemented in kexec.
+ *   and much simpler than the general case implemented in kexec.
  * 
  */
 




From loic.grenie at gmail.com  Sun Nov  1 15:11:15 2009
From: loic.grenie at gmail.com (=?ISO-8859-1?Q?Lo=EFc_Greni=E9?=)
Date: Sun, 1 Nov 2009 15:11:15 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
Message-ID: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>

   Here is a patch for inteltool to print the registers values
  for the P31..Q35 chipset. The registers are (as far as I
  can tell) unchanged with respect to those of the PM965.
  I've no strong ideas on the names: I've chosen
  PCI_DEVICE_ID_INTEL_82G33 as Northbridge name, it
  can obviously be changed to anything else. I've given
  "P35/Q35/G33/Q33/G31/P31" as description, it can also
  be freely changed.

    Please consider for applying,

          Thanks,

                  Lo?c



From paulepanter at users.sourceforge.net  Sun Nov  1 15:42:08 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 01 Nov 2009 15:42:08 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
In-Reply-To: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
References: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
Message-ID: <1257086528.4598.24.camel@mattotaupa.wohnung.familie-menzel.net>

Dear Lo?c,


Am Sonntag, den 01.11.2009, 15:11 +0100 schrieb Lo?c Greni?:
> Here is a patch for inteltool to print the registers values
> for the P31..Q35 chipset.

I did not receive an attachment and it looks like the list did not too
[1].

Could you resend it please, so that the developers can review it.


Thanks,

Paul


[1] http://www.coreboot.org/pipermail/coreboot/2009-November/054010.html
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From loic.grenie at gmail.com  Sun Nov  1 21:24:09 2009
From: loic.grenie at gmail.com (=?ISO-8859-1?Q?Lo=EFc_Greni=E9?=)
Date: Sun, 1 Nov 2009 21:24:09 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
In-Reply-To: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
References: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
Message-ID: <9b06e8d20911011224y63158971uacf5654a7bb59a68@mail.gmail.com>

     Sorry for the forgotten patch !

? Here is a patch for inteltool to print the registers values
?for the P31..Q35 chipset. The registers are (as far as I
?can tell) unchanged with respect to those of the PM965.
?I've no strong ideas on the names: I've chosen
?PCI_DEVICE_ID_INTEL_82G33 as Northbridge name, it
?can obviously be changed to anything else. I've given
?"P35/Q35/G33/Q33/G31/P31" as description, it can also
?be freely changed.

? ?Please consider for applying,

? ? ? ? ?Thanks,

? ? ? ? ? ? ? ? ?Lo?c
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From paulepanter at users.sourceforge.net  Sun Nov  1 22:09:58 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 01 Nov 2009 22:09:58 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
In-Reply-To: <9b06e8d20911011224y63158971uacf5654a7bb59a68@mail.gmail.com>
References: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
	<9b06e8d20911011224y63158971uacf5654a7bb59a68@mail.gmail.com>
Message-ID: <1257109798.4598.91.camel@mattotaupa.wohnung.familie-menzel.net>

Am Sonntag, den 01.11.2009, 21:24 +0100 schrieb Lo?c Greni?:

[?]

>    Please consider for applying,

One more thing. Could you add your Signed-off-by line as explained in
the Sign-off Procedure [1]. So that the developers can acknowledge and
commit your patch.


Thanks,

Paul


[1] http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
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From Zheng.Bao at amd.com  Mon Nov  2 04:25:12 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Mon, 2 Nov 2009 11:25:12 +0800
Subject: [coreboot] The filo crashes if the filo and coreboot overlap.
In-Reply-To: <1257005604.23416.18.camel@tetris>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl>
	<1257005604.23416.18.camel@tetris>
Message-ID: <DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>

In relocate_segment().
If the coreboot and filo overlap, it will "slice off" a piece at the
beginning or end. A new segment is allocated. If it is inserted before
the "seg" that is being processed, is there any chance that the "new"
segment will be processed? I am confused about it. On my fam 10 board,
it seems that the "new" segment was not processed and an error happens
when the code jumps to filo which is actually middle of nowhere.


Zheng

-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
Patrick Georgi
Sent: Sunday, November 01, 2009 12:13 AM
To: Zheng Bao
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] The filo crashes if the filo and coreboot
overlap.

Am Samstag, den 31.10.2009, 15:43 +0000 schrieb Zheng Bao:
> The filo crashes if the filo and coreboot overlap.
> Since the CBFS is the must-have feature, my family 10
>  board crashes when it jumps to filo. I am trying to
>  find out why. I need help.
> Based on current code, the AMD Family 10 will cause the filo
> and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c
> will return 1. But I am not sure if it will make the system
> crashes.
What revision is that? There was an issue like that but I fixed it
several weeks ago.

> If anybody explains briefly what happens if they
> overlap.
When coreboot and payload overlap, coreboot uses a bounce buffer. The
bounce buffer is twice the size of coreboot. The first half is for the
part of the payload that overlaps coreboot, the other half is for
coreboot itself.

The SELF loader loads data that would overlap coreboot to the bounce
buffer, and jumps into jmp_to_elf_entry when it's done with loading.
The jmp_to_elf_entry function copies coreboot to the upper half of the
bounce buffer, and jumps in there, so the code is out of the way.

Then it copies the lower half to the coreboot area and jumps to the
entry point.

There are some complications to that because of the decompression
routine, so the code is not as nice as it should be. But I specifically
tested your scenario (payload from 1mb to 2.3mb or so, coreboot starting
at 2mb)

> The coreboot information:
> CONFIG_RAMBASE=0x00200000
Try changing that to 0x100000.


Patrick


-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot





From joe at settoplinux.org  Mon Nov  2 04:53:29 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sun, 01 Nov 2009 22:53:29 -0500
Subject: [coreboot] Error executing VGA ROM with coreboot
In-Reply-To: <20091031142916.GA26420@morn.localdomain>
References: <deba0e89e5b0eb2892d20bb322511ae5@imap.1and1.com>	<200910310746.n9V7k5gj004789@mail.iwavesystems.com>
	<20091031142916.GA26420@morn.localdomain>
Message-ID: <4AEE57B9.20404@settoplinux.org>

On 10/31/2009 10:29 AM, Kevin O'Connor wrote:
> On Sat, Oct 31, 2009 at 01:14:21PM +0530, Mansoor wrote:
> [...]
>> c000:0087 0f01                 ILLEGAL EXTENDED X86 OPCODE
>> c000:0087: 01 ILLEGAL EXTENDED X86 OPCODE!
>> halt_sys: file /prdmd/coreboot-v2/src/devices/../../util/x86emu/x86emu/ops2.c, line 60
>> halted
>> 	AX=0000  BX=0000  CX=0000  DX=0080  SP=ffec  BP=0000  SI=0000  DI=0057
>> 	DS=c000  ES=0000  SS=1000  CS=c000  IP=0089   NV UP EI PL NZ NA PO NC
>> c000:0089 e0                   ILLEGAL EXTENDED X86 OPCODE
>
> If I dissasemble 0f01e0 I get:
>
>     0:   0f 01 e0                smsww  %ax
>
> Though, that might differ depending on the next bytes?
>
> In any case, I get the feeling your rom may be about to enter 32bit
> mode..
>
> You might want to try running:
>
> objdump -m i386 -M i8086 -M suffix -D -b binary myvgarom.rom
>
> and see what it says is at offset 0x0087.
>
Interesting, the Atom has a 32-bit vga bios?
Mansoor please let us know what 0x0087 says.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From mansoor at iwavesystems.com  Mon Nov  2 06:37:04 2009
From: mansoor at iwavesystems.com (Mansoor)
Date: Mon, 2 Nov 2009 11:07:04 +0530
Subject: [coreboot] Error executing VGA ROM with coreboot
In-Reply-To: <20091031224403.10225.qmail@stuge.se>
Message-ID: <200911020538.nA25clOq021428@mail.iwavesystems.com>



> -----Original Message-----
> From: coreboot-bounces+mansoor=iwavesystems.com at coreboot.org
> [mailto:coreboot-bounces+mansoor=iwavesystems.com at coreboot.org] On Behalf
> Of Peter Stuge
> Sent: Sunday, November 01, 2009 4:14 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] Error executing VGA ROM with coreboot
> 
> Mansoor wrote:
> > I have attached the YABEL output.
> 
> Thanks. I think it is helpful. Please follow Kevin's suggestions to
> find out more about what the ROM is trying to do.
> 
> 
 Yes. I will do it

> > Even though coreboot does only the hardware initialization, it has
> > to do a VGA rom init for payloads other than seabios?
> 
> VGA is often not very important for payloads, and option ROMs in
> general fundamentally require a BIOS, which coreboot does not, and
> shall not, offer. If a BIOS environment is needed, then SeaBIOS is
> the way to go.
> 
> 
> > I my case I was planning to use FILO as payload to boot Linux. FILO
> > doesn't do any VGA init.
> 
> In theory it can, if libpayload has native support for your graphics
> hardware. Since this isn't the case, there is no init done. There
> exists only very few graphics drivers in libpayload, which would
> support the idea that graphics is not very important for payloads.
> 
I don't think libpayload has support for my hardware
> 
> I think there are a few options that you can explore further. First,
> maybe the graphics driver in Linux has the ability to initialize
> hardware completely? Because Linux will be started pretty quickly
> with coreboot+FILO, the delay from power on until graphics enabled
> will not be very long even if it is postponed to Linux.
> 
I tried this option. But it didn't initialize VGA

> Second, you can use both SeaBIOS and FILO together. SeaBIOS supports
> booting using another payload file than itself in CBFS. Normally this
> is used as a last resort when there is no local storage or option ROM
> to boot from, but that behavior should be very easy to change in
> SeaBIOS, so that FILO is always used for booting.
> 
> Using multiple payloads will increase boot time, but if legacy VGA
> ROM initialization is a hard requirement then I'm afraid there is no
> substitute for a BIOS environment, such as provided by SeaBIOS.
> 
Thanks for the detailed explanation. 
I am using this method as an alternative (coreboot loads SeaBIOS then
SeaBIOS loads FILO, FILO loads Linux) now. And it works fine. I am using
FILO because I need USB mass storage support. Extra boot time is the seaBIOS
hardware initialization time... and I say it is negligible compared to the
20-30 sec delay of factory BIOS.
  
> But, don't rule out the Linux graphics driver alternative. There
> exists at least one driver (for AMD Geode) which does this, one or
> several of the VIA hardware drivers may also be able to do it. Linux
> 2.6.31 got kernel modesetting support in the Intel framebuffer driver
> so there is a chance. Also, the Intel graphics drivers developers are
> very active in the Linux community, and maybe they can quickly add
> any features that are discovered to be missing at the moment.
> 
> 
> //Peter
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 
> --------------------------------------------------------------------------
> -----
> DISCLAIMER: This e-mail and any attachment (s) is for authorised use by
> the
> intended recipient (s) only. It may contain proprietary material,
> confidential
> information and/or be subject to the legal privilege of iWave Systems
> Technologies Private Limited. If you have received this message in error,
> please notify the originator immediately. If you are not the intended
> recipient, you are notified that you are strictly prohibited from
> retaining,
> using, copying, alerting or disclosing the content of this message. Thank
> you
> for your co-operation.
> --------------------------------------------------------------------------
> ----


------------------------------------------------------------------------------- 
DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the
intended recipient (s) only. It may contain proprietary material, confidential
information and/or be subject to the legal privilege of iWave Systems
Technologies Private Limited. If you have received this message in error,
please notify the originator immediately. If you are not the intended
recipient, you are notified that you are strictly prohibited from retaining,
using, copying, alerting or disclosing the content of this message. Thank you
for your co-operation. 
------------------------------------------------------------------------------




From Zheng.Bao at amd.com  Mon Nov  2 07:25:23 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Mon, 2 Nov 2009 14:25:23 +0800
Subject: [coreboot] coreboot hangs on my AMD fam10
	board(updatedebugmessage).
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17031A43B0@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17031A43B0@sbjgexmb1.amd.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B170329FD87@sbjgexmb1.amd.com>

Now I found that the system doesn't hang. It just decompresses the
image. It is unbearably slow. Do you guys know why it does so slowly?

Zheng

-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
Bao, Zheng
Sent: Monday, October 12, 2009 9:45 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] coreboot hangs on my AMD fam10
board(updatedebugmessage).


Ping. What is the way to solve this?

I can NOT merge the CBFS to our code for a long time.

Zheng
-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
Sent: Saturday, October 10, 2009 10:12 AM
To: coreboot at coreboot.org; Carl-Daniel Hailfinger
Subject: Re: [coreboot] coreboot hangs on my AMD fam10 board (update
debugmessage).

I update the code. It hangs at somewhere else. It seems to be what
Carl-Daniel said. Is there any workaround way to skip this and let do my
own job?

Zheng

-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006 at gmx.net] 
Sent: Saturday, October 10, 2009 9:16 AM
To: Bao, Zheng
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] coreboot hangs on my AMD fam10 board.

On 09.10.2009 08:10, Bao, Zheng wrote:
> Current coreboot seems to hang somewhere. Before the 60th anniversary
of
> People's Republic of China, I always disable the CBFS when I worked on
> my fam10 board, otherwise it would be error. But now, I can not find
> where I can disable it. It seems to stop at waiting AP cores. 
>
> I am wondering if it is caused by CBFS and if it happens on other
board.
> If any one can test it, I will be appreciating.
>   

We have not solved the SMP startup printk locking yet. That explains the
mangled log messages.
Unless I'm mistaken we still decompress some parts multiple times
concurrently to the same address and that can crash the code.
Overlapping stack might also crash the code during lzma decompression.
Decompression of AP code should happen on the BSP or on exactly one AP,
but not on all APs.


> coreboot-2.0.0-r623M_tilapia_fam10_Fallback Fri Oct  9 13:15:49 CST
2009
> starting...
> [...]
> Start other core - nodeid: 00  cores: 03
> started ap apicid:    cccooorrreeexxx:::      ---------   {{{
> AAAPPPIIICCC
> IIIDDD   ===   000312   NNNOOODDDEEEIIIDDD   ===   000000
> CCCOOORRREEEIIIDDD   ===   000321}}
> }   ---------
>   

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."






From loic.grenie at gmail.com  Mon Nov  2 10:12:54 2009
From: loic.grenie at gmail.com (=?ISO-8859-1?Q?Lo=EFc_Greni=E9?=)
Date: Mon, 2 Nov 2009 10:12:54 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
In-Reply-To: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
References: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
Message-ID: <9b06e8d20911020112t3c3ee114v306c8cd458961f66@mail.gmail.com>

 ? Here is a patch for inteltool to print the registers values
?for the P31..Q35 chipset. The registers are (as far as I
?can tell) unchanged with respect to those of the PM965.
?I've no strong ideas on the names: I've chosen
?PCI_DEVICE_ID_INTEL_82[PQG]3[135] as Northbridge
 names, they?can obviously be changed to anything else. I've
 given?"Q35", "P35/G33/G31/P31" and "Q33" as descriptions,
 they can also?be freely changed.

Signed-off-by: Lo?c Greni? <loic.grenie at gmail.com>
Description: adds 82Q35/P35/Q33/G33/G31/P31 capability.

? ?Please consider for applying,

? ? ? ? ?Thanks,

? ? ? ? ? ? ? ? ?Lo?c
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From smihael at gmail.com  Mon Nov  2 10:50:31 2009
From: smihael at gmail.com (Miha)
Date: Mon, 2 Nov 2009 10:50:31 +0100
Subject: [coreboot] MSI MS-7360
Message-ID: <d6f07c600911020150l4ada2bbama895bf7fe38a5508@mail.gmail.com>

Is this mainboard supported?

board:
http://eu.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=&cat3_no=&prod_no=1215(MSI
MS-7360)
proc: intel q660

Some usefull outputs:

*lspci -tvnn*
-[0000:00]-+-00.0  Intel Corporation 82G33/G31/P35/P31 Express DRAM
Controller [8086:29c0]
           +-01.0-[0000:01]--+-00.0  ATI Technologies Inc RV710 [Radeon HD
4550] [1002:9540]
           |                 \-00.1  ATI Technologies Inc R700 Audio Device
[Radeon HD 4000 Series] [1002:aa38]
           +-1a.0  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #4 [8086:2937]
           +-1a.1  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #5 [8086:2938]
           +-1a.7  Intel Corporation 82801I (ICH9 Family) USB2 EHCI
Controller #2 [8086:293c]
           +-1b.0  Intel Corporation 82801I (ICH9 Family) HD Audio
Controller [8086:293e]
           +-1c.0-[0000:02]--
           +-1c.4-[0000:03]----00.0  Marvell Technology Group Ltd. 88SE6121
SATA II Controller [11ab:6121]
           +-1c.5-[0000:04]----00.0  Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168]
           +-1d.0  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #1 [8086:2934]
           +-1d.1  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #2 [8086:2935]
           +-1d.2  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #3 [8086:2936]
           +-1d.3  Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #6 [8086:2939]
           +-1d.7  Intel Corporation 82801I (ICH9 Family) USB2 EHCI
Controller #1 [8086:293a]
           +-1e.0-[0000:05]--+-00.0  Philips Semiconductors
SAA7134/SAA7135HL Video Broadcast Decoder [1131:7134]
           |                 \-01.0  Silicon Image, Inc. PCI0680 Ultra
ATA-133 Host Controller [1095:0680]
           +-1f.0  Intel Corporation 82801IB (ICH9) LPC Interface Controller
[8086:2918]
           +-1f.2  Intel Corporation 82801IB (ICH9) 2 port SATA IDE
Controller [8086:2921]
           +-1f.3  Intel Corporation 82801I (ICH9 Family) SMBus Controller
[8086:2930]
           \-1f.5  Intel Corporation 82801I (ICH9 Family) 2 port SATA IDE
Controller [8086:2926]

*superiotool -dV  *
[...]
Probing for Fintek Super I/O at 0x4e...


Found Fintek F71882FG/F71883FG (vid=0x3419, id=0x4105) at 0x4e


Register dump:


idx 20 21 23 24 25 26 27 28  29 2a 2b 2c 2d


val 05 41 19 34 00 00 10 40  00 40 68 08 0e


def 05 41 19 34 00 00 00 00  00 00 00 08 08


LDN 0x00 (Floppy)


idx 30 60 61 70 74 f0 f2 f4


val 01 03 f0 06 02 0e ff 00


def 01 03 f0 06 02 0e 03 00


LDN 0x01 (COM1)


idx 30 60 61 70 f0


val 01 03 f8 04 00


def 01 03 f8 04 00


LDN 0x02 (COM2)


idx 30 60 61 70 f0 f1


val 00 02 f8 03 00 44


def 01 02 f8 03 00 04


LDN 0x03 (Parallel port)


idx 30 60 61 70 74 f0


val 01 03 78 07 04 3c


def 01 03 78 07 03 42


LDN 0x04 (Hardware monitor)


idx 30 60 61 70


val 01 0a 00 00


def 01 02 95 00


LDN 0x05 (Keyboard)


idx 30 60 61 70 72 f0


val 01 00 60 01 0c 83


def 01 00 60 00 00 83


LDN 0x06 (GPIO)


idx 70 e0 e1 e2 e3 d0 d1 d2  d3 c0 c1 c2 c3 b0 b1 b2  b3 f0 f1 f2 f3


val ff 00 ff 20 00 00 ff f7  00 00 0f 09 00 00 0f 09  00 00 ff c0 00


def 00 00 ff NA 00 00 ff NA  00 00 0f NA 00 00 0f NA  00 00 ff NA 00


LDN 0x07 (VID)


idx 30 60 61


val 01 0a e0


def 00 00 00


LDN 0x07 (SPI)


idx f0 f1 f2 f3 f4 f5 f6 f7  f8 fa fb fc fd fe ff


val 00 00 80 35 80 00 00 c7  77 3f 00 00 00 0f ff


def 10 04 01 00 00 00 00 00  00 00 00 00 00 00 00


LDN 0x0a (PME, ACPI)


idx 30 f0 f1 f4 f5


val 00 00 2b 06 1c


def 00 00 01 06 1c
Probing [...]

*flashrom -V*
flashrom v0.9.1-r706
No coreboot table found.
Found chipset "Intel ICH9", enabling flash write...
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode disabled
0xffe00000/0xffa00000 FWH decode disabled
0xffd80000/0xff980000 FWH decode disabled
0xffd00000/0xff900000 FWH decode disabled
0xffc80000/0xff880000 FWH decode disabled
0xffc00000/0xff800000 FWH decode disabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0

Root Complex Register Block address = 0xfed1c000
GCS = 0x551464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1
(SPI)
Top Swap : not enabled

SPIBAR = 0xfed1c000 + 0x3800

0x04: 0x2008 (HSFS)

FLOCKDN 0, FDV 0, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0

0x50: 0x00000202 (FRAP)

BMWAG 0, BMRAG 0, BRWA 2, BRRA 2

0x54: 0x00001fff (FREG0)

0x58: 0x00001fff (FREG1)

0x5C: 0x00001fff (FREG2)

0x60: 0x00001fff (FREG3)

0x64: 0x00001fff (FREG4)

0x74: 0x00000000 (PR0)

0x78: 0x00000000 (PR1)

0x7C: 0x00000000 (PR2)

0x80: 0x00000000 (PR3)

0x84: 0x00000000 (PR4)

0x90: 0x00420000 (SSFS, SSFC)

0x94: 0x0000     (PREOP)

0x96: 0xd43b     (OPTYPE)

0x98: 0x05d80302 (OPMENU)

0x9C: 0x0006019f (OPMENU+4)

0xA0: 0x00000000 (BBAR)

0xB0: 0x00000000 (FDOC)

Programming OPCODES...

program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190

done

SPI Read Configuration: prefetching disabled, caching enabled, OK.

This chipset supports the following protocols: LPC,FWH,SPI.

Calibrating delay loop... 685M loops per second, 100 myus = 200 us. OK.

Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT25DF021, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25F512B, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25FS010, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT25FS040, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT26DF041, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT26F004, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for AMIC A25L40P, 512 KB: RDID returned 0xef 0x30 0x14 0x00.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for Eon EN25B05, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B10, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B20, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B40, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B80, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B32, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25B64, 8192 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25D16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F05, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F10, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F20, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F40, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F80, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Eon EN25F32, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x55, id2 0x53


Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff


Probing for Macronix MX25L512, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L1005, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L2005, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L4005, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.

Probing for Numonyx M25PE10, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Numonyx M25PE20, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Numonyx M25PE40, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV010, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV020, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV040, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm25LV512, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for PMC Pm29F0002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for PMC Pm29F0002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff


Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for SST SST25VF016B, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for SST SST25VF032B, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for SST SST25VF040B, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for SST SST25VF040.REMS, 512 KB: REMS returned ef 13.
probe_spi_rems: id1 0xef, id2 0x13

Probing for SST SST25VF040B.REMS, 512 KB: REMS returned ef 13.
probe_spi_rems: id1 0xef, id2 0x13

Probing for SST SST25VF080B, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x42, id2 0xc1, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x55, id2 0x53


Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff


Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff


Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content

Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content

Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content

Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content


Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff


Probing for ST M25P05-A, 64 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M25P05.RES, 64 KB: RDID returned 0xef 0x30 0x14. Probing for
ST M25P10-A, 128 KB: RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic:
id1 0xef, id2 0x3014
Probing for ST M25P10.RES, 128 KB: RDID returned 0xef 0x30 0x14. Probing for
ST M25P20, 256 KB: RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1
0xef, id2 0x3014
Probing for ST M25P40, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M25P40-old, 512 KB: RDID returned 0xef 0x30 0x14. Probing for
ST M25P80, 1024 KB: RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic:
id1 0xef, id2 0x3014
Probing for ST M25P16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M25P32, 4096 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M25P64, 8192 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M25P128, 16384 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014

Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip
bus type Parallel are incompatible.

Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip
bus type Parallel are incompatible.

Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.

Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip
bus type Parallel are incompatible.
Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip
bus type Parallel are incompatible.
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x55, id2 0x53
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x55, id2 0x53
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x41, id2 0xcc
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x55, id2 0x53
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH,SPI
and chip bus type Parallel are incompatible.
Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W25x10, 128 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Winbond W25x20, 256 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Winbond W25x40, 512 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Winbond W25x80, 1024 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Chip status register is 00
Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000.
Probing for Winbond W25x16, 2048 KB: RDID returned 0xef 0x30 0x14.
probe_spi_rdid_generic: id1 0xef, id2 0x3014
Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x55, id2 0x53,
id1 parity violation
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x55, id2 0x53, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH,SPI and
chip bus type Parallel are incompatible.
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec: id1 0x41, id2 0xcc, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2
0xff
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1
0x55, id2 0x53
Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero
size at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero
size at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash
chip, zero size at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero
size at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero
size at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size
at 0x100000000.
RDID returned 0xef 0x30 0x14. probe_spi_rdid_generic: id1 0xef, id2 0x3014
Not unmapping zero size at (nil)
No operations were specified.

*lshw
                         *
smihael-desktop

    description: Desktop Computer

    product: MS-7360

    vendor: MICRO-STAR INTERNATIONAL CO.,LTD

    version: 1.0

    serial: To Be Filled By O.E.M.

    width: 64 bits

    capabilities: smbios-2.5 dmi-2.5 vsyscall64 vsyscall32

    configuration: boot=normal chassis=desktop
uuid=00000000-0000-0000-0000-001D92DC4DA8

  *-core

       description: Motherboard

       product: MS-7360

       vendor: MICRO-STAR INTERNATIONAL CO.,LTD

       physical id: 0

       version: 1.0

       serial: To be filled by O.E.M.

       slot: To Be Filled By O.E.M.

     *-firmware

          description: BIOS

          vendor: American Megatrends Inc.

          physical id: 0

          version: V1.7 (02/19/2008)

          size: 64KiB

          capacity: 960KiB

          capabilities: isa pci pnp apm upgrade shadowing escd cdboot
bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880
int5printscreen int9keyboard int14serial int17printer int10video acpi usb
ls120boot zipboot biosbootspecification

     *-cpu


          description: CPU


          product: Intel(R) Core(TM)2 Quad CPU    Q6600  @ 2.40GHz


          vendor: Intel Corp.


          physical id: 4


          bus info: cpu at 0


          version: Intel(R) Core(TM)2 Quad CPU    Q6600  @ 2.40GHz


          serial: To Be Filled By O.E.M.


          slot: CPU 1


          size: 2403MHz


          width: 64 bits


          clock: 267MHz


          capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8
apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss
ht tm pbe syscall x86-64 constant_tsc arch_perfmon pebs bts rep_good pni
dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm tpr_shadow
vnmi flexpriority
        *-cache:0


             description: L1 cache


             physical id: 5


             slot: L1-Cache


             size: 128KiB


             capacity: 128KiB


             capabilities: internal write-back data


        *-cache:1


             description: L2 cache


             physical id: 6


             slot: L2-Cache


             size: 8MiB


             capacity: 8MiB


             capabilities: internal write-back unified


     *-memory


          description: System Memory


          physical id: f


          slot: System board or motherboard


          size: 4GiB


        *-bank:0


             description: DIMM SDRAM Synchronous


             product: PartNum0


             vendor: Manufacturer0


             physical id: 0


             serial: SerNum0


             slot: DIMM0


             size: 2GiB


             width: 64 bits


        *-bank:1


             description: DIMM SDRAM Synchronous


             product: PartNum1


             vendor: Manufacturer1


             physical id: 1


             serial: SerNum1


             slot: DIMM1


             size: 2GiB


             width: 64 bits


        *-bank:2


             description: DIMM [empty]


             product: PartNum2


             vendor: Manufacturer2


             physical id: 2


             serial: SerNum2


             slot: DIMM2


        *-bank:3


             description: DIMM [empty]


             product: PartNum3


             vendor: Manufacturer3


             physical id: 3


             serial: SerNum3


             slot: DIMM3


     *-pci


          description: Host bridge


          product: 82G33/G31/P35/P31 Express DRAM Controller


          vendor: Intel Corporation


          physical id: 100


          bus info: pci at 0000:00:00.0


          version: 02


          width: 32 bits


          clock: 33MHz


        *-pci:0


             description: PCI bridge


             product: 82G33/G31/P35/P31 Express PCI Express Root Port


             vendor: Intel Corporation


             physical id: 1


             bus info: pci at 0000:00:01.0


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pci pm msi pciexpress bus_master cap_list


             configuration: driver=pcieport-driver


             resources: irq:24 ioport:b000(size=4096)
memory:fe800000-fe8fffff ioport:d0000000(size=268435456)

           *-display


                description: VGA compatible controller


                product: RV710 [Radeon HD 4550]


                vendor: ATI Technologies Inc


                physical id: 0


                bus info: pci at 0000:01:00.0


                version: 00


                width: 64 bits


                clock: 33MHz


                capabilities: pm pciexpress msi bus_master cap_list rom


                configuration: driver=fglrx_pci latency=0


                resources: irq:29 memory:d0000000-dfffffff(prefetchable)
memory:fe8f0000-fe8fffff ioport:b000(size=256)
memory:fe8c0000-fe8dffff(prefetchable)
           *-multimedia


                description: Audio device


                product: R700 Audio Device [Radeon HD 4000 Series]


                vendor: ATI Technologies Inc


                physical id: 0.1


                bus info: pci at 0000:01:00.1


                version: 00


                width: 64 bits


                clock: 33MHz


                capabilities: pm pciexpress msi bus_master cap_list


                configuration: driver=HDA Intel latency=0


                resources: irq:17 memory:fe8ec000-fe8effff


        *-usb:0


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #4


             vendor: Intel Corporation


             physical id: 1a


             bus info: pci at 0000:00:1a.0


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:16 ioport:ac00(size=32)


        *-usb:1


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #5


             vendor: Intel Corporation


             physical id: 1a.1


             bus info: pci at 0000:00:1a.1


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:21 ioport:a880(size=32)


        *-usb:2


             description: USB Controller


             product: 82801I (ICH9 Family) USB2 EHCI Controller #2


             vendor: Intel Corporation


             physical id: 1a.7


             bus info: pci at 0000:00:1a.7


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pm debug bus_master cap_list


             configuration: driver=ehci_hcd latency=0


             resources: irq:18 memory:fe7ffc00-fe7fffff


        *-multimedia


             description: Audio device


             product: 82801I (ICH9 Family) HD Audio Controller


             vendor: Intel Corporation


             physical id: 1b


             bus info: pci at 0000:00:1b.0


             version: 02


             width: 64 bits


             clock: 33MHz


             capabilities: pm msi pciexpress bus_master cap_list


             configuration: driver=HDA Intel latency=0


             resources: irq:22 memory:fe7f8000-fe7fbfff


        *-pci:1


             description: PCI bridge


             product: 82801I (ICH9 Family) PCI Express Port 1


             vendor: Intel Corporation


             physical id: 1c


             bus info: pci at 0000:00:1c.0


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pci pciexpress msi pm bus_master cap_list


             configuration: driver=pcieport-driver


             resources: irq:25


        *-pci:2


             description: PCI bridge


             product: 82801I (ICH9 Family) PCI Express Port 5


             vendor: Intel Corporation


             physical id: 1c.4


             bus info: pci at 0000:00:1c.4


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pci pciexpress msi pm bus_master cap_list


             configuration: driver=pcieport-driver


             resources: irq:26 ioport:c000(size=4096)
memory:fe900000-fe9fffff

           *-ide


                description: IDE interface


                product: 88SE6121 SATA II Controller


                vendor: Marvell Technology Group Ltd.


                physical id: 0


                bus info: pci at 0000:03:00.0


                logical name: scsi4


                version: b2


                width: 32 bits


                clock: 33MHz


                capabilities: ide pm msi pciexpress bus_master cap_list
emulated

                configuration: driver=pata_marvell latency=0


                resources: irq:16 ioport:cc00(size=8) ioport:c880(size=4)
ioport:c800(size=8) ioport:c480(size=4) ioport:c400(size=16)
memory:fe9ffc00-fe9fffff
              *-cdrom


                   description: DVD-RAM writer


                   product: DVD-RAM GSA-H55L


                   vendor: HL-DT-ST


                   physical id: 0.1.0


                   bus info: scsi at 4:0.1.0


                   logical name: /dev/cdrom


                   logical name: /dev/cdrw


                   logical name: /dev/dvd


                   logical name: /dev/dvdrw


                   logical name: /dev/scd0


                   logical name: /dev/sr0


                   version: 1.03


                   serial: [HL-DT-STDVD-RAM GSA-H55L1.0307/08/17 7U02


                   capabilities: removable audio cd-r cd-rw dvd dvd-r
dvd-ram

                   configuration: ansiversion=5 status=nodisc


        *-pci:3


             description: PCI bridge


             product: 82801I (ICH9 Family) PCI Express Port 6


             vendor: Intel Corporation


             physical id: 1c.5


             bus info: pci at 0000:00:1c.5


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pci pciexpress msi pm bus_master cap_list


             configuration: driver=pcieport-driver


             resources: irq:27 ioport:d000(size=4096)
memory:fea00000-feafffff

           *-network


                description: Ethernet interface


                product: RTL8111/8168B PCI Express Gigabit Ethernet
controller

                vendor: Realtek Semiconductor Co., Ltd.


                physical id: 0


                bus info: pci at 0000:04:00.0


                logical name: eth0


                version: 01


                serial: 00:1d:92:dc:4d:a8


                size: 100MB/s


                capacity: 1GB/s


                width: 64 bits


                clock: 33MHz


                capabilities: pm vpd msi pciexpress bus_master cap_list rom
ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd
autonegotiation
                configuration: autonegotiation=on broadcast=yes driver=r8169
driverversion=2.3LK-NAPI duplex=full ip=192.168.0.3 latency=0 link=yes
multicast=yes port=MII speed=100MB/s


                resources: irq:28 ioport:d800(size=256)
memory:feaff000-feafffff memory:feac0000-feadffff(prefetchable)

        *-usb:3


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #1


             vendor: Intel Corporation


             physical id: 1d


             bus info: pci at 0000:00:1d.0


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:23 ioport:a800(size=32)


        *-usb:4


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #2


             vendor: Intel Corporation


             physical id: 1d.1


             bus info: pci at 0000:00:1d.1


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:19 ioport:a480(size=32)


        *-usb:5


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #3


             vendor: Intel Corporation


             physical id: 1d.2


             bus info: pci at 0000:00:1d.2


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:18 ioport:a400(size=32)


        *-usb:6


             description: USB Controller


             product: 82801I (ICH9 Family) USB UHCI Controller #6


             vendor: Intel Corporation


             physical id: 1d.3


             bus info: pci at 0000:00:1d.3


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: bus_master cap_list


             configuration: driver=uhci_hcd latency=0


             resources: irq:16 ioport:a080(size=32)


        *-usb:7


             description: USB Controller


             product: 82801I (ICH9 Family) USB2 EHCI Controller #1


             vendor: Intel Corporation


             physical id: 1d.7


             bus info: pci at 0000:00:1d.7


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: pm debug bus_master cap_list


             configuration: driver=ehci_hcd latency=0


             resources: irq:23 memory:fe7ff800-fe7ffbff


        *-pci:4


             description: PCI bridge


             product: 82801 PCI Bridge


             vendor: Intel Corporation


             physical id: 1e


             bus info: pci at 0000:00:1e.0


             version: 92


             width: 32 bits


             clock: 33MHz


             capabilities: pci bus_master cap_list


             resources: ioport:e000(size=4096) memory:feb00000-febfffff
memory:f0000000-f00fffff(prefetchable)

           *-multimedia


                description: Multimedia controller


                product: SAA7134/SAA7135HL Video Broadcast Decoder


                vendor: Philips Semiconductors


                physical id: 0


                bus info: pci at 0000:05:00.0


                version: 01


                width: 32 bits


                clock: 33MHz


                capabilities: pm bus_master cap_list


                configuration: driver=saa7134 latency=64 maxlatency=248
mingnt=248

                resources: irq:16 memory:febffc00-febfffff


           *-storage


                description: RAID bus controller


                product: PCI0680 Ultra ATA-133 Host Controller


                vendor: Silicon Image, Inc.


                physical id: 1


                bus info: pci at 0000:05:01.0


                version: 02


                width: 32 bits


                clock: 33MHz


                capabilities: storage pm bus_master cap_list rom


                configuration: driver=pata_sil680 latency=64


                resources: irq:17 ioport:ec00(size=8) ioport:e880(size=4)
ioport:e800(size=8) ioport:e480(size=4) ioport:e400(size=16)
memory:febff800-febff8ff memory:f0000000-f007ffff(prefetchable)


        *-isa


             description: ISA bridge


             product: 82801IB (ICH9) LPC Interface Controller


             vendor: Intel Corporation


             physical id: 1f


             bus info: pci at 0000:00:1f.0


             version: 02


             width: 32 bits


             clock: 33MHz


             capabilities: isa bus_master cap_list


             configuration: latency=0


        *-ide:0


             description: IDE interface


             product: 82801IB (ICH9) 2 port SATA IDE Controller


             vendor: Intel Corporation


             physical id: 1f.2


             bus info: pci at 0000:00:1f.2


             version: 02


             width: 32 bits


             clock: 66MHz


             capabilities: ide pm bus_master cap_list


             configuration: driver=ata_piix latency=0


             resources: irq:19 ioport:a000(size=8) ioport:9c00(size=4)
ioport:9880(size=8) ioport:9800(size=4) ioport:9480(size=16)
ioport:9400(size=16)
        *-serial UNCLAIMED


             description: SMBus


             product: 82801I (ICH9 Family) SMBus Controller


             vendor: Intel Corporation


             physical id: 1f.3


             bus info: pci at 0000:00:1f.3


             version: 02


             width: 64 bits


             clock: 33MHz


             configuration: latency=0


             resources: memory:fe7ff400-fe7ff4ff ioport:400(size=32)


        *-ide:1


             description: IDE interface


             product: 82801I (ICH9 Family) 2 port SATA IDE Controller


             vendor: Intel Corporation


             physical id: 1f.5


             bus info: pci at 0000:00:1f.5


             logical name: scsi2


             version: 02


             width: 32 bits


             clock: 66MHz


             capabilities: ide pm bus_master cap_list emulated


             configuration: driver=ata_piix latency=0


             resources: irq:19 ioport:9000(size=8) ioport:8c00(size=4)
ioport:8880(size=8) ioport:8800(size=4) ioport:8480(size=16)
ioport:8400(size=16)
           *-disk


                description: ATA Disk


                product: WDC WD3200AAKS-0


                vendor: Western Digital


                physical id: 0.0.0


                bus info: scsi at 2:0.0.0


                logical name: /dev/sda


                version: 01.0


                serial: WD-WMAV28182961


                size: 298GiB (320GB)


                capabilities: partitioned partitioned:dos


                configuration: ansiversion=5 signature=0000eb03


              *-volume:0


                   description: Linux filesystem partition


                   physical id: 1


                   bus info: scsi at 2:0.0.0,1


                   logical name: /dev/sda1


                   logical name: /home


                   version: 3.6


                   serial: 8add16d7-3ab1-4579-bbca-0f45d168ff21


                   size: 178GiB


                   capacity: 178GiB


                   capabilities: primary journaled reiserfs initialized


                   configuration: filesystem=reiserfs hash=r5 label=HOME
mount.fstype=reiserfs mount.options=rw,relatime state=mounted

              *-volume:1
                   description: Extended partition
                   physical id: 2
                   bus info: scsi at 2:0.0.0,2
                   logical name: /dev/sda2
                   size: 119GiB
                   capacity: 119GiB
                   capabilities: primary extended partitioned
partitioned:extended
                 *-logicalvolume:0
                      description: Linux filesystem partition
                      physical id: 5
                      logical name: /dev/sda5
                      logical name: /
                      capacity: 24GiB
                      capabilities: bootable
                      configuration: mount.fstype=ext4
mount.options=rw,relatime,errors=remount-ro,barrier=1,data=ordered
state=mounted
                 *-logicalvolume:1
                      description: Linux filesystem partition
                      physical id: 6
                      logical name: /dev/sda6
                      capacity: 13GiB
                 *-logicalvolume:2
                      description: Linux filesystem partition
                      physical id: 7
                      logical name: /dev/sda7
                      capacity: 13GiB
                 *-logicalvolume:3
                      description: Linux filesystem partition
                      physical id: 8
                      logical name: /dev/sda8
                      capacity: 13GiB
                 *-logicalvolume:4
                      description: Linux filesystem partition
                      physical id: 9
                      logical name: /dev/sda9
                      capacity: 13GiB
                 *-logicalvolume:5
                      description: Linux filesystem partition
                      physical id: a
                      logical name: /dev/sda10
                      capacity: 13GiB
                 *-logicalvolume:6
                      description: Linux filesystem partition
                      physical id: b
                      logical name: /dev/sda11
                      capacity: 24GiB
                 *-logicalvolume:7
                      description: Linux swap / Solaris partition
                      physical id: c
                      logical name: /dev/sda12
                      capacity: 2000MiB
                      capabilities: nofs
  *-network DISABLED
       description: Ethernet interface
       physical id: 1
       logical name: vboxnet0
       serial: 0a:00:27:00:00:00
       capabilities: ethernet physical
       configuration: broadcast=yes multicast=yes

-- 
Lep pozdrav, Miha S.
Best regards, Miha S.
Vielen Gru?, Miha S.
-------------- next part --------------
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From peter at stuge.se  Mon Nov  2 12:11:03 2009
From: peter at stuge.se (Peter Stuge)
Date: Mon, 2 Nov 2009 12:11:03 +0100
Subject: [coreboot] Error executing VGA ROM with coreboot
In-Reply-To: <200911020538.nA25clOq021428@mail.iwavesystems.com>
References: <20091031224403.10225.qmail@stuge.se>
	<200911020538.nA25clOq021428@mail.iwavesystems.com>
Message-ID: <20091102111103.15618.qmail@stuge.se>

Mansoor wrote:
> > maybe the graphics driver in Linux has the ability to initialize
> > hardware completely?
> 
> I tried this option. But it didn't initialize VGA

Ok. If you prefer this solution you could, as I mentioned, try to
contact the Linux graphics driver developers. There are people from
Intel working actively there. Search keyword is drm-intel


> > Second, you can use both SeaBIOS and FILO together.
> 
> Thanks for the detailed explanation. 
> I am using this method as an alternative (coreboot loads SeaBIOS
> then SeaBIOS loads FILO, FILO loads Linux) now. And it works fine.

Nice!


> Extra boot time is the seaBIOS hardware initialization time... and
> I say it is negligible compared to the 20-30 sec delay of factory
> BIOS.

He-he. :)


//Peter



From andrew.goodbody at tadpole.com  Mon Nov  2 15:33:06 2009
From: andrew.goodbody at tadpole.com (Andrew Goodbody)
Date: Mon, 02 Nov 2009 14:33:06 +0000
Subject: [coreboot] [PATCH] D945GCLF
In-Reply-To: <4AE5F0B8.90807@coresystems.de>
References: <4AE5F0B8.90807@coresystems.de>
Message-ID: <4AEEEDA2.7030001@tadpole.com>

If anyone does want to work on the D945GCLF board then you need to 
update the sdram_enable_memory_clocks in 
northbridge/intel/i945/raminit.c in a way that does not break the mobile 
version. The desktop version of the chipset has more clocks and so uses 
more bits in C0DCLKDIS and C1DCLKDIS to control them. Instead of bits 
0&1 and 2&3, you need to use bits 0&1&2 and 3&4&5. A quick and dirty 
hack to get this going would seem to be to define OVERRIDE_CLOCK_DISABLE.

Sorry but I don't have time to do this myself but I thought the 
information might be useful to somebody. It should be enough to get RAM 
init working.

Andrew



From ward at gnu.org  Mon Nov  2 15:40:17 2009
From: ward at gnu.org (Ward Vandewege)
Date: Mon, 2 Nov 2009 09:40:17 -0500
Subject: [coreboot] coreboot hangs on my AMD
	fam10	board(updatedebugmessage).
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170329FD87@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17031A43B0@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FD87@sbjgexmb1.amd.com>
Message-ID: <20091102144017.GA27070@countzero.vandewege.net>

On Mon, Nov 02, 2009 at 02:25:23PM +0800, Bao, Zheng wrote:
> Now I found that the system doesn't hang. It just decompresses the
> image. It is unbearably slow. Do you guys know why it does so slowly?

Ah! I saw that too on Fam10. Mansoor suggested setting

  CONFIG_XIP_ROM_BASE

to solve this. Does that help?

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior Systems Administrator



From svn at coreboot.org  Mon Nov  2 16:01:50 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  2 Nov 2009 16:01:50 +0100
Subject: [coreboot] [v2] r4905 - trunk/util/inteltool
Message-ID: <mailman.3974.1355071650.16123.coreboot@coreboot.org>

Author: hailfinger
Date: 2009-11-02 16:01:49 +0100 (Mon, 02 Nov 2009)
New Revision: 4905

Modified:
   trunk/util/inteltool/inteltool.c
   trunk/util/inteltool/inteltool.h
   trunk/util/inteltool/memory.c
   trunk/util/inteltool/pcie.c
Log:
Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
The registers are (as far as I can tell) unchanged with respect to those
of the PM965.

Signed-off-by: Lo?\195?\175c Greni?\195?\169 <loic.grenie at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: trunk/util/inteltool/inteltool.c
===================================================================
--- trunk/util/inteltool/inteltool.c	2009-11-01 09:18:23 UTC (rev 4904)
+++ trunk/util/inteltool/inteltool.c	2009-11-02 15:01:49 UTC (rev 4905)
@@ -39,6 +39,9 @@
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },

Modified: trunk/util/inteltool/inteltool.h
===================================================================
--- trunk/util/inteltool/inteltool.h	2009-11-01 09:18:23 UTC (rev 4904)
+++ trunk/util/inteltool/inteltool.h	2009-11-02 15:01:49 UTC (rev 4905)
@@ -52,6 +52,9 @@
 #define PCI_DEVICE_ID_INTEL_82945GM		0x27a0
 #define PCI_DEVICE_ID_INTEL_PM965		0x2a00
 #define PCI_DEVICE_ID_INTEL_82975X		0x277c
+#define PCI_DEVICE_ID_INTEL_82Q35		0x29b0
+#define PCI_DEVICE_ID_INTEL_82G33		0x29c0
+#define PCI_DEVICE_ID_INTEL_82Q33		0x29d0
 #define PCI_DEVICE_ID_INTEL_X58			0x3405
 
 #define PCI_DEVICE_ID_INTEL_82443LX		0x7180

Modified: trunk/util/inteltool/memory.c
===================================================================
--- trunk/util/inteltool/memory.c	2009-11-01 09:18:23 UTC (rev 4904)
+++ trunk/util/inteltool/memory.c	2009-11-02 15:01:49 UTC (rev 4905)
@@ -40,6 +40,9 @@
 		mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82Q35:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
+ 	case PCI_DEVICE_ID_INTEL_82Q33:
  		mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
  		mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
  		break;

Modified: trunk/util/inteltool/pcie.c
===================================================================
--- trunk/util/inteltool/pcie.c	2009-11-01 09:18:23 UTC (rev 4904)
+++ trunk/util/inteltool/pcie.c	2009-11-02 15:01:49 UTC (rev 4905)
@@ -39,6 +39,9 @@
 		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82Q35:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
+ 	case PCI_DEVICE_ID_INTEL_82Q33:
  		epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
  		epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
  		break;
@@ -86,6 +89,9 @@
 		dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82Q35:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
+ 	case PCI_DEVICE_ID_INTEL_82Q33:
  		dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
  		dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
  		break;
@@ -135,6 +141,9 @@
 		pciexbar_reg = pci_read_long(nb, 0x48);
 		break;
  	case PCI_DEVICE_ID_INTEL_PM965:
+ 	case PCI_DEVICE_ID_INTEL_82Q35:
+ 	case PCI_DEVICE_ID_INTEL_82G33:
+ 	case PCI_DEVICE_ID_INTEL_82Q33:
  		pciexbar_reg = pci_read_long(nb, 0x60);
  		pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
  		break;




From c-d.hailfinger.devel.2006 at gmx.net  Mon Nov  2 16:03:00 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 02 Nov 2009 16:03:00 +0100
Subject: [coreboot] Intel P35/Q35/G33/Q33/G31/P31
In-Reply-To: <9b06e8d20911020112t3c3ee114v306c8cd458961f66@mail.gmail.com>
References: <9b06e8d20911010611y38b1f14ara54977485d17f130@mail.gmail.com>
	<9b06e8d20911020112t3c3ee114v306c8cd458961f66@mail.gmail.com>
Message-ID: <4AEEF4A4.2030707@gmx.net>

On 02.11.2009 10:12, Lo?c Greni? wrote:
>    Here is a patch for inteltool to print the registers values
>  for the P31..Q35 chipset. The registers are (as far as I
>  can tell) unchanged with respect to those of the PM965.
>  I've no strong ideas on the names: I've chosen
>  PCI_DEVICE_ID_INTEL_82[PQG]3[135] as Northbridge
>  names, they can obviously be changed to anything else. I've
>  given "Q35", "P35/G33/G31/P31" and "Q33" as descriptions,
>  they can also be freely changed.
>
> Signed-off-by: Lo?c Greni? <loic.grenie at gmail.com>
> Description: adds 82Q35/P35/Q33/G33/G31/P31 capability.
>   

Thanks for your patch!

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
and committed in r4905.

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."




From hng at lanl.gov  Mon Nov  2 20:01:20 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Mon, 02 Nov 2009 12:01:20 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910291201w3004f537r932049dbe1fc69fa@mail.gmail.com>	
	<4AE9FBB9.50901@lanl.gov>	
	<2831fecf0910291352w713aee6ejad58116739081730@mail.gmail.com>	
	<2831fecf0910291555r2e3c16d3uf2b98a7f8645037d@mail.gmail.com>	
	<1256861017.13389.5.camel@nibbler>	
	<65882F71165E484DA95FD5AA7FA8D397@chimp>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
Message-ID: <4AEF2C80.8070608@lanl.gov>

Myles,

Setting it to 1 or 2 gives what looks like the same output.  It causes 
coreboot to fail with the following error:

Initializing CBMEM area to 0x3fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 3fff0200...ok
High Tables Base is 3fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x3fff0400... done.
PIRQ table: 176 bytes.
Looking for bad PCIX MHz input
get_pbus: dev is NULL!

-- 
Hugh Greenberg


Myles Watson wrote:
> It turns out that SB_HT_CHAIN_ON_BUS_0 was set incorrectly.  I should 
> have had you test if it should have been 2, but at least setting it to 
> 1 should let SeaBIOS find your devices.
>
> Thanks,
> Myles



From mylesgw at gmail.com  Tue Nov  3 03:06:26 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 2 Nov 2009 19:06:26 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AEF2C80.8070608@lanl.gov>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910291201w3004f537r932049dbe1fc69fa@mail.gmail.com>	
	<4AE9FBB9.50901@lanl.gov>	
	<2831fecf0910291352w713aee6ejad58116739081730@mail.gmail.com>	
	<2831fecf0910291555r2e3c16d3uf2b98a7f8645037d@mail.gmail.com>	
	<1256861017.13389.5.camel@nibbler>	
	<65882F71165E484DA95FD5AA7FA8D397@chimp>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov>
Message-ID: <6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>

> Setting it to 1 or 2 gives what looks like the same output.  It causes
> coreboot to fail with the following error:
I guess I shouldn't have committed it until it worked, but 0 was the wrong
value.

> Initializing CBMEM area to 0x3fff0000 (65536 bytes)
> Adding CBMEM entry as no. 1
> Moving GDT to 3fff0200...ok
> High Tables Base is 3fff0000.
> Copying Interrupt Routing Table to 0x000f0000... done.
> Adding CBMEM entry as no. 2
> Copying Interrupt Routing Table to 0x3fff0400... done.
> PIRQ table: 176 bytes.
> Looking for bad PCIX MHz input
That message comes from mainboard/arima/hdama/mptable.c

The bus numbers are hard-coded.  The easiest thing to do would be to:

1. Choose 1 or 2 for that config value
2. Find the bus and device numbers in the output
3. Change the hard coded values

Thanks,
Myles




From Zheng.Bao at amd.com  Tue Nov  3 04:23:17 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Tue, 3 Nov 2009 11:23:17 +0800
Subject: [coreboot] [PATCH] The filo crashes if the filo and coreboot
	overlap.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl><1257005604.23416.18.camel@tetris>
	<DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>

If the coreboot and filo overlap, it will "slice off" a piece at the
beginning or end. In the beginning case, a new segment is inserted
before the current one.  The ptr will move forward and doesn't seem to
have any chance to process the "new" segment.

                ptr ---------+     move --->
                             |
                             V
        +--------+       +--------+
        |        |       |        |
        |  new   | <---> |current | <---> .....
        |        |       |        |
        +--------+       +--------+

Now we change the ptr to the previous one and restart the loop. The
new and current segment will both be processed.

      +----------------ptr      move --->
      |
      V
 +--------+        +--------+       +--------+
 |        |        |        |       |        |
 |  prev  | <--->  |  new   | <---> |current | <---> .....
 |        |        |        |       |        |
 +--------+        +--------+       +--------+

It is tested on my Family 10 board.

Zheng

Signed-off-by: Zheng Bao <zheng.bao at amd.com>


Index: src/boot/selfboot.c
===================================================================
--- src/boot/selfboot.c	(revision 4892)
+++ src/boot/selfboot.c	(working copy)
@@ -211,19 +211,21 @@
 	return !((end <= lb_start) || (start >= lb_end));
 }
 
-static void relocate_segment(unsigned long buffer, struct segment *seg)
+static int relocate_segment(unsigned long buffer, struct segment *seg)
 {
 	/* Modify all segments that want to load onto coreboot
 	 * to load onto the bounce buffer instead.
 	 */
-	unsigned long start, middle, end;
+	/* ret:  1 : A new segment is inserted before the seg.
+	 *       0 : A new segment is inserted after the seg, or no new
one. */
+	unsigned long start, middle, end, ret = 0;
 
 	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
 		lb_start, lb_end);
 
 	/* I don't conflict with coreboot so get out of here */
 	if (!overlaps_coreboot(seg))
-		return;
+		return 0;
 
 	start = seg->s_dstaddr;
 	middle = start + seg->s_filesz;
@@ -270,6 +272,8 @@
 				new->s_dstaddr, 
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
+
+			ret = 1;
 		}
 			
 		/* Slice off a piece at the end 
@@ -319,6 +323,8 @@
 		seg->s_dstaddr, 
 		seg->s_dstaddr + seg->s_filesz, 
 		seg->s_dstaddr + seg->s_memsz);
+
+	return ret;
 }
 
 
@@ -446,7 +452,10 @@
 		
 		/* Modify the segment to load onto the bounce_buffer if
necessary.
 		 */
-		relocate_segment(bounce_buffer, ptr);
+		if (relocate_segment(bounce_buffer, ptr)) {
+			ptr = (ptr->prev)->prev;
+			continue;
+		}
 
 		printk_debug("Post relocation: addr: 0x%016lx memsz:
0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);

-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
Sent: Monday, November 02, 2009 11:25 AM
To: Patrick Georgi
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] The filo crashes if the filo and coreboot
overlap.

In relocate_segment().
If the coreboot and filo overlap, it will "slice off" a piece at the
beginning or end. A new segment is allocated. If it is inserted before
the "seg" that is being processed, is there any chance that the "new"
segment will be processed? I am confused about it. On my fam 10 board,
it seems that the "new" segment was not processed and an error happens
when the code jumps to filo which is actually middle of nowhere.


Zheng

-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
Patrick Georgi
Sent: Sunday, November 01, 2009 12:13 AM
To: Zheng Bao
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] The filo crashes if the filo and coreboot
overlap.

Am Samstag, den 31.10.2009, 15:43 +0000 schrieb Zheng Bao:
> The filo crashes if the filo and coreboot overlap.
> Since the CBFS is the must-have feature, my family 10
>  board crashes when it jumps to filo. I am trying to
>  find out why. I need help.
> Based on current code, the AMD Family 10 will cause the filo
> and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c
> will return 1. But I am not sure if it will make the system
> crashes.
What revision is that? There was an issue like that but I fixed it
several weeks ago.

> If anybody explains briefly what happens if they
> overlap.
When coreboot and payload overlap, coreboot uses a bounce buffer. The
bounce buffer is twice the size of coreboot. The first half is for the
part of the payload that overlaps coreboot, the other half is for
coreboot itself.

The SELF loader loads data that would overlap coreboot to the bounce
buffer, and jumps into jmp_to_elf_entry when it's done with loading.
The jmp_to_elf_entry function copies coreboot to the upper half of the
bounce buffer, and jumps in there, so the code is out of the way.

Then it copies the lower half to the coreboot area and jumps to the
entry point.

There are some complications to that because of the decompression
routine, so the code is not as nice as it should be. But I specifically
tested your scenario (payload from 1mb to 2.3mb or so, coreboot starting
at 2mb)

> The coreboot information:
> CONFIG_RAMBASE=0x00200000
Try changing that to 0x100000.


Patrick


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coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot



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coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

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From stepan at coresystems.de  Tue Nov  3 10:59:45 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 03 Nov 2009 10:59:45 +0100
Subject: [coreboot] [PATCH] x86emu: add SMSW, RDMSR, WRMSR, INVD, WBINVD
Message-ID: <4AEFFF11.7060104@coresystems.de>

See patch..

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From stepan at coresystems.de  Tue Nov  3 13:02:17 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 03 Nov 2009 13:02:17 +0100
Subject: [coreboot] [PATCH] x86emu: add missing ops
In-Reply-To: <4AEFFF11.7060104@coresystems.de>
References: <4AEFFF11.7060104@coresystems.de>
Message-ID: <4AF01BC9.4000200@coresystems.de>

Stefan Reinauer wrote:
> See patch..
>
>   
Ok, new version: I added CPUID and removed a whole bunch of warnings, too.
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From peter at stuge.se  Tue Nov  3 13:58:41 2009
From: peter at stuge.se (Peter Stuge)
Date: Tue, 3 Nov 2009 13:58:41 +0100
Subject: [coreboot] [PATCH] x86emu: add missing ops
In-Reply-To: <4AF01BC9.4000200@coresystems.de>
References: <4AEFFF11.7060104@coresystems.de> <4AF01BC9.4000200@coresystems.de>
Message-ID: <20091103125841.30826.qmail@stuge.se>

Stefan Reinauer wrote:
> Ok, new version: I added CPUID and removed a whole bunch of
> warnings, too.

Looks fine.


> x86emu: Add support for the following opcodes:
> 
> * SMSW
> * INVD/WBINVD
> * RDMSR/WRMSR
> * CPUID
> 
> The implementation is kept very simple (mostly dummies) but it should get
> us successfully through the Poulsbo VGA OPROM code in order to determine
> further requirements.
> 
> Also, fix up a lot of warnings (mostly about missing prototypes for 
> functions that should be static anyways)
> 
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From stepan at coresystems.de  Tue Nov  3 15:12:12 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 03 Nov 2009 15:12:12 +0100
Subject: [coreboot] [PATCH] Atom 106cx fixes
Message-ID: <4AF03A3C.1080701@coresystems.de>

See patch
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From rminnich at gmail.com  Tue Nov  3 15:42:11 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Nov 2009 06:42:11 -0800
Subject: [coreboot] [PATCH] Atom 106cx fixes
In-Reply-To: <4AF03A3C.1080701@coresystems.de>
References: <4AF03A3C.1080701@coresystems.de>
Message-ID: <13426df10911030642w52e46aa8qe10af680798d6f07@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Tue Nov  3 15:59:44 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  3 Nov 2009 15:59:44 +0100
Subject: [coreboot] [v2] r4906 - in trunk/util/x86emu: include/x86emu x86emu
Message-ID: <mailman.3975.1355071650.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-03 15:59:43 +0100 (Tue, 03 Nov 2009)
New Revision: 4906

Modified:
   trunk/util/x86emu/include/x86emu/x86emu.h
   trunk/util/x86emu/x86emu/decode.c
   trunk/util/x86emu/x86emu/ops.c
   trunk/util/x86emu/x86emu/ops.h
   trunk/util/x86emu/x86emu/ops2.c
   trunk/util/x86emu/x86emu/prim_ops.c
   trunk/util/x86emu/x86emu/prim_ops.h
   trunk/util/x86emu/x86emu/sys.c
Log:
x86emu: Add support for the following opcodes:

* SMSW
* INVD/WBINVD
* RDMSR/WRMSR
* CPUID

The implementation is kept very simple (mostly dummies) but it should get
us successfully through the Poulsbo VGA OPROM code in order to determine
further requirements.

Also, fix up a lot of warnings (mostly about missing prototypes for 
functions that should be static anyways)

This version adds a break in smsw that was missing in the patch that was sent
to the list.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: trunk/util/x86emu/include/x86emu/x86emu.h
===================================================================
--- trunk/util/x86emu/include/x86emu/x86emu.h	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/include/x86emu/x86emu.h	2009-11-03 14:59:43 UTC (rev 4906)
@@ -44,6 +44,7 @@
 
 /* FIXME: redefine printk for the moment */
 #ifdef CONFIG_COREBOOT_V2
+#include <stddef.h>
 #include <console/console.h>
 #undef printk
 #define printk(x...) do_printk(BIOS_DEBUG, x)
@@ -160,7 +161,7 @@
 void 	X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
 void 	X86EMU_prepareForInt(int num);
 
-//void X86EMU_setMemBase(void *base, size_t size);
+void X86EMU_setMemBase(void *base, size_t size);
 
 /* decode.c */
 

Modified: trunk/util/x86emu/x86emu/decode.c
===================================================================
--- trunk/util/x86emu/x86emu/decode.c	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/decode.c	2009-11-03 14:59:43 UTC (rev 4906)
@@ -735,7 +735,7 @@
 Decodes scale/index of SIB byte and returns relevant offset part of 
 effective address.
 ****************************************************************************/
-unsigned decode_sib_si(
+static unsigned decode_sib_si(
     int scale,
     int index)
 {
@@ -785,7 +785,7 @@
 REMARKS:
 Decodes SIB addressing byte and returns calculated effective address.
 ****************************************************************************/
-unsigned decode_sib_address(
+static unsigned decode_sib_address(
     int mod)
 {
     int sib   = fetch_byte_imm();

Modified: trunk/util/x86emu/x86emu/ops.c
===================================================================
--- trunk/util/x86emu/x86emu/ops.c	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/ops.c	2009-11-03 14:59:43 UTC (rev 4906)
@@ -171,7 +171,7 @@
 REMARKS:
 Handles illegal opcodes.
 ****************************************************************************/
-void x86emuOp_illegal_op(
+static void x86emuOp_illegal_op(
     u8 op1)
 {
     START_OF_INSTR();
@@ -198,7 +198,7 @@
 REMARKS:
 Handles opcodes 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38
 ****************************************************************************/
-void x86emuOp_genop_byte_RM_R(u8 op1)
+static void x86emuOp_genop_byte_RM_R(u8 op1)
 {
     int mod, rl, rh;
     uint destoffset;
@@ -239,7 +239,7 @@
 REMARKS:
 Handles opcodes 0x01, 0x09, 0x11, 0x19, 0x21, 0x29, 0x31, 0x39
 ****************************************************************************/
-void x86emuOp_genop_word_RM_R(u8 op1)
+static void x86emuOp_genop_word_RM_R(u8 op1)
 {
     int mod, rl, rh;
     uint destoffset;
@@ -307,7 +307,7 @@
 REMARKS:
 Handles opcodes 0x02, 0x0a, 0x12, 0x1a, 0x22, 0x2a, 0x32, 0x3a
 ****************************************************************************/
-void x86emuOp_genop_byte_R_RM(u8 op1)
+static void x86emuOp_genop_byte_R_RM(u8 op1)
 {
     int mod, rl, rh;
     u8 *destreg, *srcreg;
@@ -343,7 +343,7 @@
 REMARKS:
 Handles opcodes 0x03, 0x0b, 0x13, 0x1b, 0x23, 0x2b, 0x33, 0x3b
 ****************************************************************************/
-void x86emuOp_genop_word_R_RM(u8 op1)
+static void x86emuOp_genop_word_R_RM(u8 op1)
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -400,7 +400,7 @@
 REMARKS:
 Handles opcodes 0x04, 0x0c, 0x14, 0x1c, 0x24, 0x2c, 0x34, 0x3c
 ****************************************************************************/
-void x86emuOp_genop_byte_AL_IMM(u8 op1)
+static void x86emuOp_genop_byte_AL_IMM(u8 op1)
 {
     u8 srcval;
 
@@ -421,7 +421,7 @@
 REMARKS:
 Handles opcodes 0x05, 0x0d, 0x15, 0x1d, 0x25, 0x2d, 0x35, 0x3d
 ****************************************************************************/
-void x86emuOp_genop_word_AX_IMM(u8 op1)
+static void x86emuOp_genop_word_AX_IMM(u8 op1)
 {
     u32 srcval;
 
@@ -452,7 +452,7 @@
 REMARKS:
 Handles opcode 0x06
 ****************************************************************************/
-void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tES\n");
@@ -466,7 +466,7 @@
 REMARKS:
 Handles opcode 0x07
 ****************************************************************************/
-void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("POP\tES\n");
@@ -480,7 +480,7 @@
 REMARKS:
 Handles opcode 0x0e
 ****************************************************************************/
-void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tCS\n");
@@ -494,7 +494,7 @@
 REMARKS:
 Handles opcode 0x0f. Escape for two-byte opcode (286 or better)
 ****************************************************************************/
-void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1))
 {
     u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
     INC_DECODED_INST_LEN(1);
@@ -505,7 +505,7 @@
 REMARKS:
 Handles opcode 0x16
 ****************************************************************************/
-void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tSS\n");
@@ -519,7 +519,7 @@
 REMARKS:
 Handles opcode 0x17
 ****************************************************************************/
-void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("POP\tSS\n");
@@ -533,7 +533,7 @@
 REMARKS:
 Handles opcode 0x1e
 ****************************************************************************/
-void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tDS\n");
@@ -547,7 +547,7 @@
 REMARKS:
 Handles opcode 0x1f
 ****************************************************************************/
-void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("POP\tDS\n");
@@ -561,7 +561,7 @@
 REMARKS:
 Handles opcode 0x26
 ****************************************************************************/
-void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("ES:\n");
@@ -578,7 +578,7 @@
 REMARKS:
 Handles opcode 0x27
 ****************************************************************************/
-void x86emuOp_daa(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_daa(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("DAA\n");
@@ -592,7 +592,7 @@
 REMARKS:
 Handles opcode 0x2e
 ****************************************************************************/
-void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("CS:\n");
@@ -606,7 +606,7 @@
 REMARKS:
 Handles opcode 0x2f
 ****************************************************************************/
-void x86emuOp_das(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_das(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("DAS\n");
@@ -620,7 +620,7 @@
 REMARKS:
 Handles opcode 0x36
 ****************************************************************************/
-void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("SS:\n");
@@ -634,7 +634,7 @@
 REMARKS:
 Handles opcode 0x37
 ****************************************************************************/
-void x86emuOp_aaa(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("AAA\n");
@@ -648,7 +648,7 @@
 REMARKS:
 Handles opcode 0x3e
 ****************************************************************************/
-void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("DS:\n");
@@ -662,7 +662,7 @@
 REMARKS:
 Handles opcode 0x3f
 ****************************************************************************/
-void x86emuOp_aas(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_aas(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("AAS\n");
@@ -676,7 +676,7 @@
 REMARKS:
 Handles opcode 0x40 - 0x47
 ****************************************************************************/
-void x86emuOp_inc_register(u8 op1)
+static void x86emuOp_inc_register(u8 op1)
 {
     START_OF_INSTR();
     op1 &= 0x7;
@@ -702,7 +702,7 @@
 REMARKS:
 Handles opcode 0x48 - 0x4F
 ****************************************************************************/
-void x86emuOp_dec_register(u8 op1)
+static void x86emuOp_dec_register(u8 op1)
 {
     START_OF_INSTR();
     op1 &= 0x7;
@@ -728,7 +728,7 @@
 REMARKS:
 Handles opcode 0x50 - 0x57
 ****************************************************************************/
-void x86emuOp_push_register(u8 op1)
+static void x86emuOp_push_register(u8 op1)
 {
     START_OF_INSTR();
     op1 &= 0x7;
@@ -754,7 +754,7 @@
 REMARKS:
 Handles opcode 0x58 - 0x5F
 ****************************************************************************/
-void x86emuOp_pop_register(u8 op1)
+static void x86emuOp_pop_register(u8 op1)
 {
     START_OF_INSTR();
     op1 &= 0x7;
@@ -780,7 +780,7 @@
 REMARKS:
 Handles opcode 0x60
 ****************************************************************************/
-void x86emuOp_push_all(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -820,7 +820,7 @@
 REMARKS:
 Handles opcode 0x61
 ****************************************************************************/
-void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -859,7 +859,7 @@
 REMARKS:
 Handles opcode 0x64
 ****************************************************************************/
-void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("FS:\n");
@@ -876,7 +876,7 @@
 REMARKS:
 Handles opcode 0x65
 ****************************************************************************/
-void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("GS:\n");
@@ -893,7 +893,7 @@
 REMARKS:
 Handles opcode 0x66 - prefix for 32-bit register
 ****************************************************************************/
-void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("DATA:\n");
@@ -907,7 +907,7 @@
 REMARKS:
 Handles opcode 0x67 - prefix for 32-bit address
 ****************************************************************************/
-void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("ADDR:\n");
@@ -921,7 +921,7 @@
 REMARKS:
 Handles opcode 0x68
 ****************************************************************************/
-void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
 {
     u32 imm;
 
@@ -946,7 +946,7 @@
 REMARKS:
 Handles opcode 0x69
 ****************************************************************************/
-void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1053,7 +1053,7 @@
 REMARKS:
 Handles opcode 0x6a
 ****************************************************************************/
-void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1))
 {
     s16 imm;
 
@@ -1074,7 +1074,7 @@
 REMARKS:
 Handles opcode 0x6b
 ****************************************************************************/
-void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1179,7 +1179,7 @@
 REMARKS:
 Handles opcode 0x6c
 ****************************************************************************/
-void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("INSB\n");
@@ -1193,7 +1193,7 @@
 REMARKS:
 Handles opcode 0x6d
 ****************************************************************************/
-void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -1212,7 +1212,7 @@
 REMARKS:
 Handles opcode 0x6e
 ****************************************************************************/
-void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("OUTSB\n");
@@ -1226,7 +1226,7 @@
 REMARKS:
 Handles opcode 0x6f
 ****************************************************************************/
-void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -1245,9 +1245,7 @@
 REMARKS:
 Handles opcode 0x70 - 0x7F
 ****************************************************************************/
-int x86emu_check_jump_condition(u8 op);
-
-void x86emuOp_jump_near_cond(u8 op1)
+static void x86emuOp_jump_near_cond(u8 op1)
 {
     s8 offset;
     u16 target;
@@ -1272,7 +1270,7 @@
 REMARKS:
 Handles opcode 0x80
 ****************************************************************************/
-void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -1351,7 +1349,7 @@
 REMARKS:
 Handles opcode 0x81
 ****************************************************************************/
-void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -1457,7 +1455,7 @@
 REMARKS:
 Handles opcode 0x82
 ****************************************************************************/
-void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -1534,7 +1532,7 @@
 REMARKS:
 Handles opcode 0x83
 ****************************************************************************/
-void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -1635,7 +1633,7 @@
 REMARKS:
 Handles opcode 0x84
 ****************************************************************************/
-void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg, *srcreg;
@@ -1669,7 +1667,7 @@
 REMARKS:
 Handles opcode 0x85
 ****************************************************************************/
-void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -1729,7 +1727,7 @@
 REMARKS:
 Handles opcode 0x86
 ****************************************************************************/
-void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg, *srcreg;
@@ -1769,7 +1767,7 @@
 REMARKS:
 Handles opcode 0x87
 ****************************************************************************/
-void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -1840,7 +1838,7 @@
 REMARKS:
 Handles opcode 0x88
 ****************************************************************************/
-void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg, *srcreg;
@@ -1872,7 +1870,7 @@
 REMARKS:
 Handles opcode 0x89
 ****************************************************************************/
-void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -1928,7 +1926,7 @@
 REMARKS:
 Handles opcode 0x8a
 ****************************************************************************/
-void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg, *srcreg;
@@ -1962,7 +1960,7 @@
 REMARKS:
 Handles opcode 0x8b
 ****************************************************************************/
-void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -2023,7 +2021,7 @@
 REMARKS:
 Handles opcode 0x8c
 ****************************************************************************/
-void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u16 *destreg, *srcreg;
@@ -2057,7 +2055,7 @@
 REMARKS:
 Handles opcode 0x8d
 ****************************************************************************/
-void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u16 *srcreg;
@@ -2089,7 +2087,7 @@
 REMARKS:
 Handles opcode 0x8e
 ****************************************************************************/
-void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u16 *destreg, *srcreg;
@@ -2129,7 +2127,7 @@
 REMARKS:
 Handles opcode 0x8f
 ****************************************************************************/
-void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -2183,7 +2181,7 @@
 REMARKS:
 Handles opcode 0x90
 ****************************************************************************/
-void x86emuOp_nop(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_nop(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("NOP\n");
@@ -2196,7 +2194,7 @@
 REMARKS:
 Handles opcode 0x91-0x97
 ****************************************************************************/
-void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1))
 {
     u32 tmp;
 
@@ -2231,7 +2229,7 @@
 REMARKS:
 Handles opcode 0x98
 ****************************************************************************/
-void x86emuOp_cbw(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -2261,7 +2259,7 @@
 REMARKS:
 Handles opcode 0x99
 ****************************************************************************/
-void x86emuOp_cwd(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -2292,7 +2290,7 @@
 REMARKS:
 Handles opcode 0x9a
 ****************************************************************************/
-void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 farseg, faroff;
 
@@ -2323,7 +2321,7 @@
 REMARKS:
 Handles opcode 0x9b
 ****************************************************************************/
-void x86emuOp_wait(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_wait(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("WAIT");
@@ -2337,7 +2335,7 @@
 REMARKS:
 Handles opcode 0x9c
 ****************************************************************************/
-void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
 {
     u32 flags;
 
@@ -2364,7 +2362,7 @@
 REMARKS:
 Handles opcode 0x9d
 ****************************************************************************/
-void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -2386,7 +2384,7 @@
 REMARKS:
 Handles opcode 0x9e
 ****************************************************************************/
-void x86emuOp_sahf(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("SAHF\n");
@@ -2403,7 +2401,7 @@
 REMARKS:
 Handles opcode 0x9f
 ****************************************************************************/
-void x86emuOp_lahf(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("LAHF\n");
@@ -2420,7 +2418,7 @@
 REMARKS:
 Handles opcode 0xa0
 ****************************************************************************/
-void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 offset;
 
@@ -2438,7 +2436,7 @@
 REMARKS:
 Handles opcode 0xa1
 ****************************************************************************/
-void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 offset;
 
@@ -2463,7 +2461,7 @@
 REMARKS:
 Handles opcode 0xa2
 ****************************************************************************/
-void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 offset;
 
@@ -2481,7 +2479,7 @@
 REMARKS:
 Handles opcode 0xa3
 ****************************************************************************/
-void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 offset;
 
@@ -2506,7 +2504,7 @@
 REMARKS:
 Handles opcode 0xa4
 ****************************************************************************/
-void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1))
 {
     u8  val;
     u32 count;
@@ -2545,7 +2543,7 @@
 REMARKS:
 Handles opcode 0xa5
 ****************************************************************************/
-void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
 {
     u32 val;
     int inc;
@@ -2597,7 +2595,7 @@
 REMARKS:
 Handles opcode 0xa6
 ****************************************************************************/
-void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1))
 {
     s8 val1, val2;
     int inc;
@@ -2644,7 +2642,7 @@
 REMARKS:
 Handles opcode 0xa7
 ****************************************************************************/
-void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
 {
     u32 val1,val2;
     int inc;
@@ -2707,7 +2705,7 @@
 REMARKS:
 Handles opcode 0xa8
 ****************************************************************************/
-void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1))
 {
     int imm;
 
@@ -2725,7 +2723,7 @@
 REMARKS:
 Handles opcode 0xa9
 ****************************************************************************/
-void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
 {
     u32 srcval;
 
@@ -2752,7 +2750,7 @@
 REMARKS:
 Handles opcode 0xaa
 ****************************************************************************/
-void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1))
 {
     int inc;
 
@@ -2789,7 +2787,7 @@
 REMARKS:
 Handles opcode 0xab
 ****************************************************************************/
-void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
 {
     int inc;
     u32 count;
@@ -2837,7 +2835,7 @@
 REMARKS:
 Handles opcode 0xac
 ****************************************************************************/
-void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1))
 {
     int inc;
 
@@ -2874,7 +2872,7 @@
 REMARKS:
 Handles opcode 0xad
 ****************************************************************************/
-void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
 {
     int inc;
     u32 count;
@@ -2922,7 +2920,7 @@
 REMARKS:
 Handles opcode 0xae
 ****************************************************************************/
-void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1))
 {
     s8 val2;
     int inc;
@@ -2981,7 +2979,7 @@
 REMARKS:
 Handles opcode 0xaf
 ****************************************************************************/
-void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
 {
     int inc;
     u32 val;
@@ -3063,7 +3061,7 @@
 REMARKS:
 Handles opcode 0xb0 - 0xb7
 ****************************************************************************/
-void x86emuOp_mov_byte_register_IMM(u8 op1)
+static void x86emuOp_mov_byte_register_IMM(u8 op1)
 {
     u8 imm, *ptr;
 
@@ -3083,7 +3081,7 @@
 REMARKS:
 Handles opcode 0xb8 - 0xbf
 ****************************************************************************/
-void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1))
 {
     u32 srcval;
 
@@ -3114,7 +3112,7 @@
 REMARKS:
 Handles opcode 0xc0
 ****************************************************************************/
-void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -3191,7 +3189,7 @@
 REMARKS:
 Handles opcode 0xc1
 ****************************************************************************/
-void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -3292,7 +3290,7 @@
 REMARKS:
 Handles opcode 0xc2
 ****************************************************************************/
-void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 imm;
 
@@ -3312,7 +3310,7 @@
 REMARKS:
 Handles opcode 0xc3
 ****************************************************************************/
-void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("RET\n");
@@ -3327,7 +3325,7 @@
 REMARKS:
 Handles opcode 0xc4
 ****************************************************************************/
-void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rh, rl;
     u16 *dstreg;
@@ -3355,7 +3353,7 @@
 REMARKS:
 Handles opcode 0xc5
 ****************************************************************************/
-void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rh, rl;
     u16 *dstreg;
@@ -3382,7 +3380,7 @@
 REMARKS:
 Handles opcode 0xc6
 ****************************************************************************/
-void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -3418,7 +3416,7 @@
 REMARKS:
 Handles opcode 0xc7
 ****************************************************************************/
-void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -3479,7 +3477,7 @@
 REMARKS:
 Handles opcode 0xc8
 ****************************************************************************/
-void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
 {
     u16 local,frame_pointer;
     u8  nesting;
@@ -3510,7 +3508,7 @@
 REMARKS:
 Handles opcode 0xc9
 ****************************************************************************/
-void x86emuOp_leave(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_leave(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("LEAVE\n");
@@ -3525,7 +3523,7 @@
 REMARKS:
 Handles opcode 0xca
 ****************************************************************************/
-void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 imm;
 
@@ -3546,7 +3544,7 @@
 REMARKS:
 Handles opcode 0xcb
 ****************************************************************************/
-void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("RETF\n");
@@ -3562,7 +3560,7 @@
 REMARKS:
 Handles opcode 0xcc
 ****************************************************************************/
-void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
 {
     u16 tmp;
 
@@ -3590,7 +3588,7 @@
 REMARKS:
 Handles opcode 0xcd
 ****************************************************************************/
-void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 tmp;
     u8 intnum;
@@ -3620,7 +3618,7 @@
 REMARKS:
 Handles opcode 0xce
 ****************************************************************************/
-void x86emuOp_into(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_into(u8 X86EMU_UNUSED(op1))
 {
     u16 tmp;
 
@@ -3649,7 +3647,7 @@
 REMARKS:
 Handles opcode 0xcf
 ****************************************************************************/
-void x86emuOp_iret(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_iret(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("IRET\n");
@@ -3667,7 +3665,7 @@
 REMARKS:
 Handles opcode 0xd0
 ****************************************************************************/
-void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -3740,7 +3738,7 @@
 REMARKS:
 Handles opcode 0xd1
 ****************************************************************************/
-void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -3839,7 +3837,7 @@
 REMARKS:
 Handles opcode 0xd2
 ****************************************************************************/
-void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -3914,7 +3912,7 @@
 REMARKS:
 Handles opcode 0xd3
 ****************************************************************************/
-void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -4011,7 +4009,7 @@
 REMARKS:
 Handles opcode 0xd4
 ****************************************************************************/
-void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
 {
     u8 a;
 
@@ -4034,7 +4032,7 @@
 REMARKS:
 Handles opcode 0xd5
 ****************************************************************************/
-void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
 {
     u8 a;
 
@@ -4053,7 +4051,7 @@
 REMARKS:
 Handles opcode 0xd7
 ****************************************************************************/
-void x86emuOp_xlat(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1))
 {
     u16 addr;
 
@@ -4072,7 +4070,7 @@
 REMARKS:
 Handles opcode 0xe0
 ****************************************************************************/
-void x86emuOp_loopne(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1))
 {
     s16 ip;
 
@@ -4096,7 +4094,7 @@
 REMARKS:
 Handles opcode 0xe1
 ****************************************************************************/
-void x86emuOp_loope(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_loope(u8 X86EMU_UNUSED(op1))
 {
     s16 ip;
 
@@ -4120,7 +4118,7 @@
 REMARKS:
 Handles opcode 0xe2
 ****************************************************************************/
-void x86emuOp_loop(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_loop(u8 X86EMU_UNUSED(op1))
 {
     s16 ip;
 
@@ -4144,7 +4142,7 @@
 REMARKS:
 Handles opcode 0xe3
 ****************************************************************************/
-void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
 {
     u16 target;
     s8  offset;
@@ -4168,7 +4166,7 @@
 REMARKS:
 Handles opcode 0xe4
 ****************************************************************************/
-void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
 {
     u8 port;
 
@@ -4186,7 +4184,7 @@
 REMARKS:
 Handles opcode 0xe5
 ****************************************************************************/
-void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1))
 {
     u8 port;
 
@@ -4212,7 +4210,7 @@
 REMARKS:
 Handles opcode 0xe6
 ****************************************************************************/
-void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1))
 {
     u8 port;
 
@@ -4230,7 +4228,7 @@
 REMARKS:
 Handles opcode 0xe7
 ****************************************************************************/
-void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1))
 {
     u8 port;
 
@@ -4256,7 +4254,7 @@
 REMARKS:
 Handles opcode 0xe8
 ****************************************************************************/
-void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1))
 {
     s16 ip;
 
@@ -4277,7 +4275,7 @@
 REMARKS:
 Handles opcode 0xe9
 ****************************************************************************/
-void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1))
 {
     int ip;
 
@@ -4297,7 +4295,7 @@
 REMARKS:
 Handles opcode 0xea
 ****************************************************************************/
-void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 cs, ip;
 
@@ -4319,7 +4317,7 @@
 REMARKS:
 Handles opcode 0xeb
 ****************************************************************************/
-void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1))
 {
     u16 target;
     s8 offset;
@@ -4340,7 +4338,7 @@
 REMARKS:
 Handles opcode 0xec
 ****************************************************************************/
-void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("IN\tAL,DX\n");
@@ -4354,7 +4352,7 @@
 REMARKS:
 Handles opcode 0xed
 ****************************************************************************/
-void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -4376,7 +4374,7 @@
 REMARKS:
 Handles opcode 0xee
 ****************************************************************************/
-void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("OUT\tDX,AL\n");
@@ -4390,7 +4388,7 @@
 REMARKS:
 Handles opcode 0xef
 ****************************************************************************/
-void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
@@ -4412,7 +4410,7 @@
 REMARKS:
 Handles opcode 0xf0
 ****************************************************************************/
-void x86emuOp_lock(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_lock(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("LOCK:\n");
@@ -4427,7 +4425,7 @@
 REMARKS:
 Handles opcode 0xf2
 ****************************************************************************/
-void x86emuOp_repne(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_repne(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("REPNE\n");
@@ -4443,7 +4441,7 @@
 REMARKS:
 Handles opcode 0xf3
 ****************************************************************************/
-void x86emuOp_repe(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_repe(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("REPE\n");
@@ -4459,7 +4457,7 @@
 REMARKS:
 Handles opcode 0xf4
 ****************************************************************************/
-void x86emuOp_halt(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_halt(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     DECODE_PRINTF("HALT\n");
@@ -4473,7 +4471,7 @@
 REMARKS:
 Handles opcode 0xf5
 ****************************************************************************/
-void x86emuOp_cmc(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1))
 {
     /* complement the carry flag. */
     START_OF_INSTR();
@@ -4488,7 +4486,7 @@
 REMARKS:
 Handles opcode 0xf6
 ****************************************************************************/
-void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     u8 *destreg;
@@ -4604,7 +4602,7 @@
 REMARKS:
 Handles opcode 0xf7
 ****************************************************************************/
-void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -4830,7 +4828,7 @@
 REMARKS:
 Handles opcode 0xf8
 ****************************************************************************/
-void x86emuOp_clc(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_clc(u8 X86EMU_UNUSED(op1))
 {
     /* clear the carry flag. */
     START_OF_INSTR();
@@ -4845,7 +4843,7 @@
 REMARKS:
 Handles opcode 0xf9
 ****************************************************************************/
-void x86emuOp_stc(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_stc(u8 X86EMU_UNUSED(op1))
 {
     /* set the carry flag. */
     START_OF_INSTR();
@@ -4860,7 +4858,7 @@
 REMARKS:
 Handles opcode 0xfa
 ****************************************************************************/
-void x86emuOp_cli(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cli(u8 X86EMU_UNUSED(op1))
 {
     /* clear interrupts. */
     START_OF_INSTR();
@@ -4875,7 +4873,7 @@
 REMARKS:
 Handles opcode 0xfb
 ****************************************************************************/
-void x86emuOp_sti(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_sti(u8 X86EMU_UNUSED(op1))
 {
     /* enable  interrupts. */
     START_OF_INSTR();
@@ -4890,7 +4888,7 @@
 REMARKS:
 Handles opcode 0xfc
 ****************************************************************************/
-void x86emuOp_cld(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_cld(u8 X86EMU_UNUSED(op1))
 {
     /* clear interrupts. */
     START_OF_INSTR();
@@ -4905,7 +4903,7 @@
 REMARKS:
 Handles opcode 0xfd
 ****************************************************************************/
-void x86emuOp_std(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_std(u8 X86EMU_UNUSED(op1))
 {
     /* clear interrupts. */
     START_OF_INSTR();
@@ -4920,7 +4918,7 @@
 REMARKS:
 Handles opcode 0xfe
 ****************************************************************************/
-void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rh, rl;
     u8 destval;
@@ -4984,7 +4982,7 @@
 REMARKS:
 Handles opcode 0xff
 ****************************************************************************/
-void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
+static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rh, rl;
     uint destoffset = 0;

Modified: trunk/util/x86emu/x86emu/ops.h
===================================================================
--- trunk/util/x86emu/x86emu/ops.h	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/ops.h	2009-11-03 14:59:43 UTC (rev 4906)
@@ -42,4 +42,6 @@
 extern void (*x86emu_optab[0x100])(u8 op1);
 extern void (*x86emu_optab2[0x100])(u8 op2);
 
+int x86emu_check_jump_condition(u8 op);
+
 #endif /* __X86EMU_OPS_H */

Modified: trunk/util/x86emu/x86emu/ops2.c
===================================================================
--- trunk/util/x86emu/x86emu/ops2.c	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/ops2.c	2009-11-03 14:59:43 UTC (rev 4906)
@@ -49,18 +49,129 @@
 REMARKS:
 Handles illegal opcodes.
 ****************************************************************************/
-void x86emuOp2_illegal_op(
-    u8 op2)
+static void x86emuOp2_illegal_op(u8 op2)
 {
     START_OF_INSTR();
     DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
     TRACE_REGS();
     printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
-        M.x86.R_CS, M.x86.R_IP-2,op2);
+        M.x86.R_CS, M.x86.R_IP-2, op2);
     HALT_SYS();
     END_OF_INSTR();
 }
 
+/****************************************************************************
+ * REMARKS:
+ * Handles opcode 0x0f,0x01
+ * ****************************************************************************/
+
+static void x86emuOp2_opc_01(u8 op2)
+{
+  int mod, rl, rh;
+  u16 *destreg;
+  uint destoffset;
+
+  START_OF_INSTR();
+  FETCH_DECODE_MODRM(mod, rh, rl);
+
+  switch(rh) {
+  case 4: // SMSW (Store Machine Status Word)
+          // Decode the mod byte to find the addressing
+          // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1)
+#define SMSW_INITIAL_VALUE	0x10
+    DECODE_PRINTF("SMSW\t");
+    switch (mod) {
+    case 0:
+      destoffset = decode_rm00_address(rl);
+      store_data_word(destoffset, SMSW_INITIAL_VALUE);
+      break;
+    case 1:
+      destoffset = decode_rm01_address(rl);
+      store_data_word(destoffset, SMSW_INITIAL_VALUE);
+      break;
+    case 2:
+      destoffset = decode_rm10_address(rl);
+      store_data_word(destoffset, SMSW_INITIAL_VALUE);
+      break;
+    case 3:
+      destreg = DECODE_RM_WORD_REGISTER(rl);
+      *destreg = SMSW_INITIAL_VALUE;
+      break;
+    }
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    DECODE_PRINTF("\n");
+    break;
+  default:
+    DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE IN 0F 01\n");
+    TRACE_REGS();
+    printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
+        M.x86.R_CS, M.x86.R_IP-2, op2);
+    HALT_SYS();
+    break;
+  }
+
+  END_OF_INSTR();
+}
+
+/****************************************************************************
+ * REMARKS:
+ * Handles opcode 0x0f,0x08
+ * ****************************************************************************/
+static void x86emuOp2_invd(u8 op2)
+{
+  START_OF_INSTR();
+  DECODE_PRINTF("INVD\n");
+  TRACE_AND_STEP();
+  DECODE_CLEAR_SEGOVR();
+  END_OF_INSTR();
+}
+
+/****************************************************************************
+ * REMARKS:
+ * Handles opcode 0x0f,0x09
+ * ****************************************************************************/
+static void x86emuOp2_wbinvd(u8 op2)
+{
+  START_OF_INSTR();
+  DECODE_PRINTF("WBINVD\n");
+  TRACE_AND_STEP();
+  DECODE_CLEAR_SEGOVR();
+  END_OF_INSTR();
+}
+
+/****************************************************************************
+ * REMARKS:
+ * Handles opcode 0x0f,0x30
+ * ****************************************************************************/
+static void x86emuOp2_wrmsr(u8 op2)
+{
+  /* dummy implementation, does nothing */
+
+  START_OF_INSTR();
+  DECODE_PRINTF("WRMSR\n");
+  TRACE_AND_STEP();
+  DECODE_CLEAR_SEGOVR();
+  END_OF_INSTR();
+}
+
+/****************************************************************************
+ * REMARKS:
+ * Handles opcode 0x0f,0x32
+ * ****************************************************************************/
+static void x86emuOp2_rdmsr(u8 op2)
+{
+  /* dummy implementation, always return 0 */
+
+  START_OF_INSTR();
+  DECODE_PRINTF("RDMSR\n");
+  TRACE_AND_STEP();
+  M.x86.R_EDX = 0;
+  M.x86.R_EAX = 0;
+  DECODE_CLEAR_SEGOVR();
+  END_OF_INSTR();
+}  
+
 #define xorl(a,b)   (((a) && !(b)) || (!(a) && (b)))
 
 /****************************************************************************
@@ -137,7 +248,7 @@
     }
 }
 
-void x86emuOp2_long_jump(u8 op2)
+static void x86emuOp2_long_jump(u8 op2)
 {
     s32 target;
     int cond;
@@ -161,18 +272,18 @@
 REMARKS:
 Handles opcode 0x0f,0xC8-0xCF
 ****************************************************************************/
-s32 x86emu_bswap(s32 reg)
+static s32 x86emu_bswap(s32 reg)
 {
    // perform the byte swap
    s32 temp = reg;
-   reg = (temp & 0xFF000000) >> 24;
-   reg |= (temp & 0xFF0000) >> 8;
-   reg |= (temp & 0xFF00) << 8;
-   reg |= (temp & 0xFF) << 24;
+   reg = (temp & 0xFF000000) >> 24 |
+         (temp & 0xFF0000) >> 8 |
+         (temp & 0xFF00) << 8 |
+         (temp & 0xFF) << 24;
    return reg;
 }
 
-void x86emuOp2_bswap(u8 op2)
+static void x86emuOp2_bswap(u8 op2)
 {
     /* byte swap 32 bit register */
     START_OF_INSTR();
@@ -220,12 +331,12 @@
 REMARKS:
 Handles opcode 0x0f,0x90-0x9F
 ****************************************************************************/
-void x86emuOp2_set_byte(u8 op2)
+static void x86emuOp2_set_byte(u8 op2)
 {
     int mod, rl, rh;
     uint destoffset;
     u8  *destreg;
-    char *name = 0;
+    const char *name = 0;
     int cond = 0;
 
     START_OF_INSTR();
@@ -316,7 +427,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa0
 ****************************************************************************/
-void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tFS\n");
@@ -330,7 +441,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa1
 ****************************************************************************/
-void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
 {
     START_OF_INSTR();
     DECODE_PRINTF("POP\tFS\n");
@@ -341,10 +452,24 @@
 }
 
 /****************************************************************************
+REMARKS: CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output
+Handles opcode 0x0f,0xa2
+****************************************************************************/
+static void x86emuOp2_cpuid(u8 X86EMU_UNUSED(op2))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("CPUID\n");
+    TRACE_AND_STEP();
+    x86emu_cpuid();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
 REMARKS:
 Handles opcode 0x0f,0xa3
 ****************************************************************************/
-void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -407,7 +532,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa4
 ****************************************************************************/
-void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -478,7 +603,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa5
 ****************************************************************************/
-void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -540,7 +665,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa8
 ****************************************************************************/
-void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2))
 {
     START_OF_INSTR();
     DECODE_PRINTF("PUSH\tGS\n");
@@ -554,7 +679,7 @@
 REMARKS:
 Handles opcode 0x0f,0xa9
 ****************************************************************************/
-void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2))
 {
     START_OF_INSTR();
     DECODE_PRINTF("POP\tGS\n");
@@ -568,7 +693,7 @@
 REMARKS:
 Handles opcode 0x0f,0xaa
 ****************************************************************************/
-void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -641,7 +766,7 @@
 REMARKS:
 Handles opcode 0x0f,0xac
 ****************************************************************************/
-void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -712,7 +837,7 @@
 REMARKS:
 Handles opcode 0x0f,0xad
 ****************************************************************************/
-void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint destoffset;
@@ -773,7 +898,7 @@
 REMARKS:
 Handles opcode 0x0f,0xaf
 ****************************************************************************/
-void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -865,7 +990,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb2
 ****************************************************************************/
-void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rh, rl;
     u16 *dstreg;
@@ -894,7 +1019,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb3
 ****************************************************************************/
-void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -966,7 +1091,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb4
 ****************************************************************************/
-void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rh, rl;
     u16 *dstreg;
@@ -995,7 +1120,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb5
 ****************************************************************************/
-void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rh, rl;
     u16 *dstreg;
@@ -1024,7 +1149,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb6
 ****************************************************************************/
-void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1087,7 +1212,7 @@
 REMARKS:
 Handles opcode 0x0f,0xb7
 ****************************************************************************/
-void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1122,7 +1247,7 @@
 REMARKS:
 Handles opcode 0x0f,0xba
 ****************************************************************************/
-void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1258,7 +1383,7 @@
 REMARKS:
 Handles opcode 0x0f,0xbb
 ****************************************************************************/
-void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1330,7 +1455,7 @@
 REMARKS:
 Handles opcode 0x0f,0xbc
 ****************************************************************************/
-void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1391,7 +1516,7 @@
 REMARKS:
 Handles opcode 0x0f,0xbd
 ****************************************************************************/
-void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1452,7 +1577,7 @@
 REMARKS:
 Handles opcode 0x0f,0xbe
 ****************************************************************************/
-void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1515,7 +1640,7 @@
 REMARKS:
 Handles opcode 0x0f,0xbf
 ****************************************************************************/
-void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
+static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
 {
     int mod, rl, rh;
     uint srcoffset;
@@ -1552,15 +1677,15 @@
 void (*x86emu_optab2[256])(u8) =
 {
 /*  0x00 */ x86emuOp2_illegal_op,  /* Group F (ring 0 PM)      */
-/*  0x01 */ x86emuOp2_illegal_op,  /* Group G (ring 0 PM)      */
+/*  0x01 */ x86emuOp2_opc_01,      /* Group G (ring 0 PM)      */
 /*  0x02 */ x86emuOp2_illegal_op,  /* lar (ring 0 PM)          */
 /*  0x03 */ x86emuOp2_illegal_op,  /* lsl (ring 0 PM)          */
 /*  0x04 */ x86emuOp2_illegal_op,
 /*  0x05 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
 /*  0x06 */ x86emuOp2_illegal_op,  /* clts (ring 0 PM)         */
 /*  0x07 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
-/*  0x08 */ x86emuOp2_illegal_op,  /* invd (ring 0 PM)         */
-/*  0x09 */ x86emuOp2_illegal_op,  /* wbinvd (ring 0 PM)       */
+/*  0x08 */ x86emuOp2_invd,        /* invd (ring 0 PM)         */
+/*  0x09 */ x86emuOp2_wbinvd,      /* wbinvd (ring 0 PM)       */
 /*  0x0a */ x86emuOp2_illegal_op,
 /*  0x0b */ x86emuOp2_illegal_op,
 /*  0x0c */ x86emuOp2_illegal_op,
@@ -1602,9 +1727,9 @@
 /*  0x2e */ x86emuOp2_illegal_op,
 /*  0x2f */ x86emuOp2_illegal_op,
 
-/*  0x30 */ x86emuOp2_illegal_op,
+/*  0x30 */ x86emuOp2_wrmsr,
 /*  0x31 */ x86emuOp2_illegal_op,
-/*  0x32 */ x86emuOp2_illegal_op,
+/*  0x32 */ x86emuOp2_rdmsr,
 /*  0x33 */ x86emuOp2_illegal_op,
 /*  0x34 */ x86emuOp2_illegal_op,
 /*  0x35 */ x86emuOp2_illegal_op,
@@ -1723,7 +1848,7 @@
 
 /*  0xa0 */ x86emuOp2_push_FS,
 /*  0xa1 */ x86emuOp2_pop_FS,
-/*  0xa2 */ x86emuOp2_illegal_op,
+/*  0xa2 */ x86emuOp2_cpuid,
 /*  0xa3 */ x86emuOp2_bt_R,
 /*  0xa4 */ x86emuOp2_shld_IMM,
 /*  0xa5 */ x86emuOp2_shld_CL,
@@ -1732,7 +1857,7 @@
 /*  0xa8 */ x86emuOp2_push_GS,
 /*  0xa9 */ x86emuOp2_pop_GS,
 /*  0xaa */ x86emuOp2_illegal_op,
-/*  0xab */ x86emuOp2_bt_R,
+/*  0xab */ x86emuOp2_bts_R,
 /*  0xac */ x86emuOp2_shrd_IMM,
 /*  0xad */ x86emuOp2_shrd_CL,
 /*  0xae */ x86emuOp2_illegal_op,

Modified: trunk/util/x86emu/x86emu/prim_ops.c
===================================================================
--- trunk/util/x86emu/x86emu/prim_ops.c	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/prim_ops.c	2009-11-03 14:59:43 UTC (rev 4906)
@@ -2448,3 +2448,49 @@
     return res;
 }
 
+/****************************************************************************
+REMARKS:
+CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output
+****************************************************************************/
+void x86emu_cpuid(void)
+{
+    u32 feature = M.x86.R_EAX;
+
+    switch (feature) {
+    case 0:
+        /* Regardless if we have real data from the hardware, the emulator
+         * will only support upto feature 1, which we set in register EAX.
+         * Registers EBX:EDX:ECX contain a string identifying the CPU.
+         */
+        M.x86.R_EAX = 1;
+        /* EBX:EDX:ECX = "GenuineIntel" */
+        M.x86.R_EBX = 0x756e6547;
+        M.x86.R_EDX = 0x49656e69;
+        M.x86.R_ECX = 0x6c65746e;
+        break;
+    case 1:
+        /* If we don't have x86 compatible hardware, we return values from an
+         * Intel 486dx4; which was one of the first processors to have CPUID.
+         */
+        M.x86.R_EAX = 0x00000480;
+        M.x86.R_EBX = 0x00000000;
+        M.x86.R_ECX = 0x00000000;
+        M.x86.R_EDX = 0x00000002;       /* VME */
+        /* In the case that we have hardware CPUID instruction, we make sure
+         * that the features reported are limited to TSC and VME.
+         */
+        M.x86.R_EDX &= 0x00000012;
+        break;
+    default:
+        /* Finally, we don't support any additional features.  Most CPUs
+         * return all zeros when queried for invalid or unsupported feature
+         * numbers.
+         */
+        M.x86.R_EAX = 0;
+        M.x86.R_EBX = 0;
+        M.x86.R_ECX = 0;
+        M.x86.R_EDX = 0;
+        break;
+    }
+}
+

Modified: trunk/util/x86emu/x86emu/prim_ops.h
===================================================================
--- trunk/util/x86emu/x86emu/prim_ops.h	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/prim_ops.h	2009-11-03 14:59:43 UTC (rev 4906)
@@ -134,7 +134,8 @@
 void    push_word (u16 w);
 void    push_long (u32 w);
 u16     pop_word (void);
-u32		pop_long (void);
+u32	pop_long (void);
+void	x86emu_cpuid (void);
 
 #if  defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM)
 

Modified: trunk/util/x86emu/x86emu/sys.c
===================================================================
--- trunk/util/x86emu/x86emu/sys.c	2009-11-02 15:01:49 UTC (rev 4905)
+++ trunk/util/x86emu/x86emu/sys.c	2009-11-03 14:59:43 UTC (rev 4906)
@@ -68,7 +68,7 @@
 /*----------------------------- Implementation ----------------------------*/
 
 /* compute a pointer. This replaces code scattered all over the place! */
-u8 *mem_ptr(u32 addr, int size)
+static u8 *mem_ptr(u32 addr, int size)
 {
 	u8 *retaddr = 0;
 




From svn at coreboot.org  Tue Nov  3 16:02:16 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Tue,  3 Nov 2009 16:02:16 +0100
Subject: [coreboot] [v2] r4907 - trunk/src/cpu/intel/model_106cx
Message-ID: <mailman.3976.1355071650.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-03 16:02:15 +0100 (Tue, 03 Nov 2009)
New Revision: 4907

Modified:
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c
Log:
Some fixes.
Atom does not like 36bit MTRRs in CAR setup.
Enable XIP setup again (works with 32bit MTRRs)
Keep code more similar to 6ex code..

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	2009-11-03 14:59:43 UTC (rev 4906)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	2009-11-03 15:02:15 UTC (rev 4907)
@@ -103,7 +103,6 @@
 	//movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
-#endif
 
 	post_code(0x29)
 	/* Enable Cache As RAM mode by disabling cache */
@@ -111,29 +110,33 @@
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-#if 0
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-	/* Enable cache for our code in Flash because we do CONFIG_XIP here */
+	/* Enable cache for our code in Flash because we do XIP here */
         movl    $MTRRphysBase_MSR(1), %ecx
         xorl    %edx, %edx
         movl    $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
         wrmsr
 
         movl    $MTRRphysMask_MSR(1), %ecx
-        movl    $0x0000000f, %edx
+        movl    $0x00000000, %edx
         movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
         wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
-#endif
 
 	post_code(0x2a)
         /* enable cache */
         movl	%cr0, %eax
 	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
-        movl	%eax, %cr0
+	movl	%eax, %cr0
+#endif
 
 	/* Set up stack pointer */
+#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+	/* leave some space for the struct ehci_debug_info */
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
+#else
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+#endif
 	movl	%eax, %esp
 
 	/* Restore the BIST result */

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c	2009-11-03 14:59:43 UTC (rev 4906)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c	2009-11-03 15:02:15 UTC (rev 4907)
@@ -60,7 +60,7 @@
 	"wrmsr\n"
 	"movl	$MTRRphysMask_MSR(0), %ecx\n"
 	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
-	"movl	$0x0000000f, %edx\n"	// 36bit address space
+	"movl	$0x00000000, %edx\n"
 	"wrmsr\n"
 	"movb	$0x35, %al\noutb %al, $0x80\n"
 #endif
@@ -97,7 +97,7 @@
 	"wrmsr\n"
 	"movl	$MTRRphysMask_MSR(0), %ecx\n"
 	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
-	"movl	$0x0000000f, %edx\n"	// 36bit address space
+	"movl	$0x00000000, %edx\n"
 	"wrmsr\n"
 
 	"movb	$0x39, %al\noutb %al, $0x80\n"




From stepan at coresystems.de  Tue Nov  3 16:04:18 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 03 Nov 2009 16:04:18 +0100
Subject: [coreboot] [PATCH] x86emu: add missing ops
In-Reply-To: <20091103125841.30826.qmail@stuge.se>
References: <4AEFFF11.7060104@coresystems.de> <4AF01BC9.4000200@coresystems.de>
	<20091103125841.30826.qmail@stuge.se>
Message-ID: <4AF04672.5060102@coresystems.de>

Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>> Ok, new version: I added CPUID and removed a whole bunch of
>> warnings, too.
>>     
>
> Looks fine.
>
>
>   
>> x86emu: Add support for the following opcodes:
>>
>> * SMSW
>> * INVD/WBINVD
>> * RDMSR/WRMSR
>> * CPUID
>>
>> The implementation is kept very simple (mostly dummies) but it should get
>> us successfully through the Poulsbo VGA OPROM code in order to determine
>> further requirements.
>>
>> Also, fix up a lot of warnings (mostly about missing prototypes for 
>> functions that should be static anyways)
>>
>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>     
>
> Acked-by: Peter Stuge <peter at stuge.se>
>
>   
Thanks, r4906



From stepan at coresystems.de  Tue Nov  3 16:04:33 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Tue, 03 Nov 2009 16:04:33 +0100
Subject: [coreboot] [PATCH] Atom 106cx fixes
In-Reply-To: <13426df10911030642w52e46aa8qe10af680798d6f07@mail.gmail.com>
References: <4AF03A3C.1080701@coresystems.de>
	<13426df10911030642w52e46aa8qe10af680798d6f07@mail.gmail.com>
Message-ID: <4AF04681.1090604@coresystems.de>

ron minnich wrote:
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
>   
thanks, r4907



From mch at virtutech.com  Tue Nov  3 16:31:32 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 03 Nov 2009 16:31:32 +0100
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
Message-ID: <4AF04CD4.1030007@virtutech.com>

I'm attaching patches for seabios to make it work on the Virtutech 
Simics x86-440bx model. Please let me know if there is some other list 
that is preferred for seabios patches.

Patches 1-6 and 9 are not really related to the Virtutech model at all, 
so those would be prime candidates to be included in the mainline version.

M.


From mch at virtutech.com  Tue Nov  3 12:49:27 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:49:27 +0100
Subject: [PATCH 01/10] Fit cpuflag in mptable (| has higher priority than ?:)
Message-ID: <mailman.3977.1355071650.16123.coreboot@coreboot.org>

---
 src/mptable.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 3945d2e..805fe1b 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -60,7 +60,7 @@ mptable_init(void)
         cpu->apicver = 0x11;
         /* cpu flags: enabled, bootstrap cpu */
         if (i < CountCPUs)
-            cpu->cpuflag = 1 | (i == 0) ? 2 : 0;
+            cpu->cpuflag = 1 | ((i == 0) ? 2 : 0);
         else
             cpu->cpuflag = 0;
         if (cpuid_signature) {
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.pat";
 filename*1="ch"


From mch at virtutech.com  Tue Nov  3 12:50:09 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:50:09 +0100
Subject: [PATCH 02/10] Only add the first logical CPU in each physical CPU to the MPS tables.
Message-ID: <mailman.3978.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |   26 ++++++++++++++++++++++----
 1 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 805fe1b..525188d 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -44,16 +44,32 @@ mptable_init(void)
     config->spec = 4;
     memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
     memcpy(config->productid, "0.1         ", sizeof(config->productid));
-    config->entrycount = MaxCountCPUs + 2 + 16;
     config->lapic = BUILD_APIC_ADDR;
 
     // CPU definitions.
     u32 cpuid_signature, ebx, ecx, cpuid_features;
     cpuid(1, &cpuid_signature, &ebx, &ecx, &cpuid_features);
     struct mpt_cpu *cpus = (void*)&config[1];
-    int i;
-    for (i = 0; i < MaxCountCPUs; i++) {
+    int i, actual_cpu_count;
+    for (i = 0, actual_cpu_count = 0; i < MaxCountCPUs; i++) {
         struct mpt_cpu *cpu = &cpus[i];
+        int log_cpus = (ebx >> 16) & 0xff;
+
+        /* Only populate the MPS tables with the first logical CPU in each
+           package */
+        if ((cpuid_features & (1 << 28)) &&
+            log_cpus > 1 &&
+            ((log_cpus <= 2 && (i & 1) != 0) ||
+             (log_cpus <= 4 && (i & 3) != 0) ||
+             (log_cpus <= 8 && (i & 7) != 0) ||
+             (log_cpus <= 16 && (i & 15) != 0) ||
+             (log_cpus <= 32 && (i & 31) != 0) ||
+             (log_cpus <= 64 && (i & 63) != 0) ||
+             (log_cpus <= 128 && (i & 127) != 0)))
+            continue;
+
+        actual_cpu_count++;
+
         memset(cpu, 0, sizeof(*cpu));
         cpu->type = MPT_TYPE_CPU;
         cpu->apicid = i;
@@ -72,8 +88,10 @@ mptable_init(void)
         }
     }
 
+    config->entrycount = actual_cpu_count + 2 + 16;
+
     /* isa bus */
-    struct mpt_bus *bus = (void*)&cpus[MaxCountCPUs];
+    struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
     memset(bus, 0, sizeof(*bus));
     bus->type = MPT_TYPE_BUS;
     memcpy(bus->bustype, "ISA   ", sizeof(bus->bustype));
-- 
1.6.2.5


--------------080100040501080908060605
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 name="0003-Limit-MPS-tables-to-15-CPUs-to-fit-with-4-bit-APIC-a.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0003-Limit-MPS-tables-to-15-CPUs-to-fit-with-4-bit-APIC-a.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 12:50:45 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:50:45 +0100
Subject: [PATCH 03/10] Limit MPS tables to 15 CPUs to fit with 4-bit APIC addressing.
Message-ID: <mailman.3979.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 525188d..7e8486d 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -86,6 +86,12 @@ mptable_init(void)
             cpu->cpusignature = 0x600;
             cpu->featureflag = 0x201;
         }
+
+        /* Limit the CPU count to 15 in the MPS tables, which is the limit in
+           the 4-bit legacy APIC addressing scheme. Operating systems can find
+           all CPUs through the ACPI tables. */
+        if (actual_cpu_count >= 15)
+            break;
     }
 
     config->entrycount = actual_cpu_count + 2 + 16;
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0004-Remove-device-access-from-loop-to-make-it-faster-whe.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0004-Remove-device-access-from-loop-to-make-it-faster-whe.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 12:51:17 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:17 +0100
Subject: [PATCH 04/10] Remove device access from loop to make it faster when running in emulation.
Message-ID: <mailman.3980.1355071651.16123.coreboot@coreboot.org>

---
 src/smp.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index a912857..71b0da8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -97,11 +97,13 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT)
+    if (CONFIG_COREBOOT) {
         msleep(10);
-    else
-        while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs))
-            ;
+    } else {
+        u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
+        while (cmos_smp_count + 1 != readl(&CountCPUs))
+             ;
+    }
 
     // Restore memory.
     *(u64*)BUILD_AP_BOOT_ADDR = old;
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0005-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0005-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 12:51:45 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:45 +0100
Subject: [PATCH 05/10] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
Message-ID: <mailman.3981.1355071651.16123.coreboot@coreboot.org>

---
 src/smp.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index 71b0da8..b0852f8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -13,6 +13,8 @@
 
 #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
 #define APIC_SVR     ((u8*)BUILD_APIC_ADDR + 0x0F0)
+#define APIC_LINT0   ((u8*)BUILD_APIC_ADDR + 0x350)
+#define APIC_LINT1   ((u8*)BUILD_APIC_ADDR + 0x360)
 
 #define APIC_ENABLED 0x0100
 
@@ -91,6 +93,12 @@ smp_probe(void)
     u32 val = readl(APIC_SVR);
     writel(APIC_SVR, val | APIC_ENABLED);
 
+    /* Set LINT0 as Ext_INT, level triggered */
+    writel(APIC_LINT0, 0x8700);
+
+    /* Set LINT1 as NMI, level triggered */
+    writel(APIC_LINT1, 0x8400);
+
     // broadcast SIPI
     writel(APIC_ICR_LOW, 0x000C4500);
     u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0006-Add-MPS-entries-for-LINT-interrupts.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename="0006-Add-MPS-entries-for-LINT-interrupts.patch"


From mch at virtutech.com  Tue Nov  3 12:52:07 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:52:07 +0100
Subject: [PATCH 06/10] Add MPS entries for LINT interrupts.
Message-ID: <mailman.3982.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |   23 +++++++++++++++++++++--
 src/mptable.h |    1 +
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 7e8486d..b91591d 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -22,7 +22,7 @@ mptable_init(void)
                   + sizeof(struct mpt_cpu) * MaxCountCPUs
                   + sizeof(struct mpt_bus)
                   + sizeof(struct mpt_ioapic)
-                  + sizeof(struct mpt_intsrc) * 16);
+                  + sizeof(struct mpt_intsrc) * 18);
     struct mptable_config_s *config = malloc_fseg(length);
     struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating));
     if (!config || !floating) {
@@ -94,7 +94,7 @@ mptable_init(void)
             break;
     }
 
-    config->entrycount = actual_cpu_count + 2 + 16;
+    config->entrycount = actual_cpu_count + 2 + 16 + 2;
 
     /* isa bus */
     struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
@@ -131,6 +131,25 @@ mptable_init(void)
         intsrc++;
     }
 
+    /* Local interrupt assignment */
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 3; /* ExtINT */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 0; /* LINTIN0 */
+    intsrc++;
+
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 1; /* NMI */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 1; /* LINTIN1 */
+    intsrc++;
+
     // Set checksum.
     config->length = (void*)intsrc - (void*)config;
     config->checksum -= checksum(config, config->length);
diff --git a/src/mptable.h b/src/mptable.h
index 4c4d52f..c4e3c51 100644
--- a/src/mptable.h
+++ b/src/mptable.h
@@ -38,6 +38,7 @@ struct mptable_config_s {
 #define MPT_TYPE_BUS 1
 #define MPT_TYPE_IOAPIC 2
 #define MPT_TYPE_INTSRC 3
+#define MPT_TYPE_LOCAL_INT 4
 
 struct mpt_cpu {
     u8 type;
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0007-Always-enable-the-IRQ0-override-if-the-VIRTUTECH_IRQ.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0007-Always-enable-the-IRQ0-override-if-the-VIRTUTECH_IRQ.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 13:41:24 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 13:41:24 +0100
Subject: [PATCH 07/10] Always enable the IRQ0 override if the VIRTUTECH_IRQ0_OVERRIDE option is set.
Message-ID: <mailman.3983.1355071651.16123.coreboot@coreboot.org>

---
 src/config.h   |    3 +++
 src/paravirt.c |    4 ++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/config.h b/src/config.h
index 3033133..71903bb 100644
--- a/src/config.h
+++ b/src/config.h
@@ -189,4 +189,7 @@
 #define DEBUG_HDL_pmm 1
 #define DEBUG_thread 1
 
+/* Options for running on the Virtutech Simics x86-440bx machine model */
+#define VIRTUTECH_IRQ0_OVERRIDE 1
+
 #endif // config.h
diff --git a/src/paravirt.c b/src/paravirt.c
index 6f48d2e..577c7e8 100644
--- a/src/paravirt.c
+++ b/src/paravirt.c
@@ -82,6 +82,9 @@ int qemu_cfg_show_boot_menu(void)
 
 int qemu_cfg_irq0_override(void)
 {
+#if VIRTUTECH_IRQ0_OVERRIDE
+    return 1;
+#else
     u8 v;
 
     if (!qemu_cfg_present)
@@ -90,6 +93,7 @@ int qemu_cfg_irq0_override(void)
     qemu_cfg_read_entry(&v, QEMU_CFG_IRQ0_OVERRIDE, sizeof(v));
 
     return v;
+#endif
 }
 
 u16 qemu_cfg_acpi_additional_tables(void)
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0008-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0008-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 13:43:13 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 13:43:13 +0100
Subject: [PATCH 08/10] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
Message-ID: <mailman.3984.1355071651.16123.coreboot@coreboot.org>

---
 src/config.h |    1 +
 src/shadow.c |   55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/src/config.h b/src/config.h
index 71903bb..754559b 100644
--- a/src/config.h
+++ b/src/config.h
@@ -191,5 +191,6 @@
 
 /* Options for running on the Virtutech Simics x86-440bx machine model */
 #define VIRTUTECH_IRQ0_OVERRIDE 1
+#define VIRTUTECH_PC_SHADOW 1
 
 #endif // config.h
diff --git a/src/shadow.c b/src/shadow.c
index f0f97c5..4b7f15c 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -9,6 +9,7 @@
 #include "pci.h" // pci_config_writeb
 #include "config.h" // CONFIG_*
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "ioport.h" // outb
 
 // Test if 'addr' is in the range from 'start'..'start+size'
 #define IN_RANGE(addr, start, size) ({   \
@@ -21,6 +22,40 @@
 // On the emulators, the bios at 0xf0000 is also at 0xffff0000
 #define BIOS_SRC_ADDR 0xffff0000
 
+#if VIRTUTECH_PC_SHADOW
+
+#define Read_Only 1
+#define Write_Only 2
+#define Read_Write 3
+
+static void modify_shadow(unsigned long start, unsigned long len, int mode)
+{
+    int start_loc = ((int)(start >> 10) - 640) >> 1;
+    int len_remaining = len >> 11;
+    int i;
+    for (i = 0; i < len_remaining; i++) {
+        outb(start_loc + i, 0xfff4);
+        if (mode == Read_Only) {
+            outb(1, 0xfff5);
+        } else if (mode == Read_Write) {
+            outb(3, 0xfff5);
+        } else if (mode == Write_Only) {
+            outb(2, 0xfff5);
+        } else {
+            outb(0, 0xfff5);
+        }
+    }
+}
+
+static void
+__copy_bios(void)
+{
+    // Copy bios.
+    memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
+}
+
+#else
+
 // Enable shadowing and copy bios.
 static void
 __make_bios_writable(u16 bdf)
@@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf)
     memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
 }
 
+#endif // VIRTUTECH_PC_SHADOW
+
 // Make the 0xc0000-0x100000 area read/writable.
 void
 make_bios_writable()
@@ -68,6 +105,19 @@ make_bios_writable()
 
     dprintf(3, "enabling shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    /* Read (and execute) from PCI, write to RAM */
+    modify_shadow(0xf0000, 0x10000, Write_Only);
+
+    /* Run the copy from the high address to avoid simulator flushes after each
+       write (the flushes ruin performance) */
+    u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
+    void (*func)(void) = (void*)pos;
+    func();
+
+    /* Keep BIOS read/write */
+    modify_shadow(0xf0000, 0x10000, Read_Write);
+#else
     // Locate chip controlling ram shadowing.
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
@@ -88,6 +138,7 @@ make_bios_writable()
     }
     // Ram already present - just enable writes
     __make_bios_writable(bdf);
+#endif
 }
 
 // Make the BIOS code segment area (0xf0000) read-only.
@@ -99,6 +150,9 @@ make_bios_readonly()
 
     dprintf(3, "locking shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    modify_shadow(0xf0000, 0x10000, Read_Only);
+#else
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
         dprintf(1, "Unable to lock ram - bridge not found\n");
@@ -122,4 +176,5 @@ make_bios_readonly()
 
     // Write protect 0xf0000-0x100000
     pci_config_writeb(bdf, 0x59, 0x10);
+#endif
 }
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0009-Properly-mask-value-for-MTRR-mask.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename="0009-Properly-mask-value-for-MTRR-mask.patch"


From mch at virtutech.com  Tue Nov  3 13:47:52 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 13:47:52 +0100
Subject: [PATCH 09/10] Properly mask value for MTRR mask.
Message-ID: <mailman.3985.1355071651.16123.coreboot@coreboot.org>

---
 src/mtrr.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mtrr.c b/src/mtrr.c
index a9cd5f7..6bd0dba 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -29,7 +29,7 @@ void mtrr_setup(void)
     if (CONFIG_COREBOOT)
         return;
 
-    u32 eax, ebx, ecx, cpuid_features;
+    u32 eax, ebx, ecx, edx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
     if (!(cpuid_features & CPUID_MTRR))
         return;
@@ -73,6 +73,16 @@ void mtrr_setup(void)
     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
     wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
-    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
+
+    int phys_bits = 36;
+    cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+    if (eax >= 0x80000008) {
+            /* Get physical bits from leaf 0x80000008 (if available) */
+            cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+            phys_bits = eax & 0xff;
+    }
+    u64 phys_mask = ((1ull << phys_bits) - 1);
+    wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800);
+
     wrmsr_smp(MSR_MTRRdefType, 0xc06);
 }
-- 
1.6.2.5


--------------080100040501080908060605
Content-Type: text/x-patch;
 name="0010-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0010-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc";
 filename*1="h"


From mch at virtutech.com  Tue Nov  3 14:46:52 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 14:46:52 +0100
Subject: [PATCH 10/10] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
Message-ID: <mailman.3986.1355071651.16123.coreboot@coreboot.org>

---
 src/config.h |    1 +
 src/smp.c    |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/config.h b/src/config.h
index 754559b..a9e79cb 100644
--- a/src/config.h
+++ b/src/config.h
@@ -192,5 +192,6 @@
 /* Options for running on the Virtutech Simics x86-440bx machine model */
 #define VIRTUTECH_IRQ0_OVERRIDE 1
 #define VIRTUTECH_PC_SHADOW 1
+#define USE_CMOS_BIOS_SMP_COUNT 0
 
 #endif // config.h
diff --git a/src/smp.c b/src/smp.c
index b0852f8..caec5f1 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -105,7 +105,7 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT) {
+    if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) {
         msleep(10);
     } else {
         u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
-- 
1.6.2.5


--------------080100040501080908060605--



From patrick at georgi-clan.de  Tue Nov  3 17:12:37 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 03 Nov 2009 17:12:37 +0100
Subject: [coreboot] [PATCH] The filo crashes if the filo and coreboot
	overlap.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl><1257005604.23416.18.camel@tetris>
	<DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
Message-ID: <4AF05675.1010400@georgi-clan.de>

Am 03.11.2009 04:23, schrieb Bao, Zheng:
> If the coreboot and filo overlap, it will "slice off" a piece at the
> beginning or end. In the beginning case, a new segment is inserted
> before the current one.  The ptr will move forward and doesn't seem to
> have any chance to process the "new" segment.
>    
You are aware that your patch only has an effect for non-compressed 
payloads?


Patrick



From hng at lanl.gov  Tue Nov  3 17:40:46 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Tue, 03 Nov 2009 09:40:46 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910291201w3004f537r932049dbe1fc69fa@mail.gmail.com>	
	<4AE9FBB9.50901@lanl.gov>	
	<2831fecf0910291352w713aee6ejad58116739081730@mail.gmail.com>	
	<2831fecf0910291555r2e3c16d3uf2b98a7f8645037d@mail.gmail.com>	
	<1256861017.13389.5.camel@nibbler>	
	<65882F71165E484DA95FD5AA7FA8D397@chimp>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
Message-ID: <4AF05D0E.1090509@lanl.gov>

Myles,

I'm not sure what you mean by: "Change the hard coded values." Where 
should I change them?

-- 
Hugh Greenberg


Myles Watson wrote:
>> Setting it to 1 or 2 gives what looks like the same output.  It causes
>> coreboot to fail with the following error:
>>     
> I guess I shouldn't have committed it until it worked, but 0 was the wrong
> value.
>
>   
>> Initializing CBMEM area to 0x3fff0000 (65536 bytes)
>> Adding CBMEM entry as no. 1
>> Moving GDT to 3fff0200...ok
>> High Tables Base is 3fff0000.
>> Copying Interrupt Routing Table to 0x000f0000... done.
>> Adding CBMEM entry as no. 2
>> Copying Interrupt Routing Table to 0x3fff0400... done.
>> PIRQ table: 176 bytes.
>> Looking for bad PCIX MHz input
>>     
> That message comes from mainboard/arima/hdama/mptable.c
>
> The bus numbers are hard-coded.  The easiest thing to do would be to:
>
> 1. Choose 1 or 2 for that config value
> 2. Find the bus and device numbers in the output
> 3. Change the hard coded values
>
> Thanks,
> Myles
>
>   



From marcj303 at gmail.com  Tue Nov  3 23:42:27 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 3 Nov 2009 15:42:27 -0700
Subject: [coreboot] [PATCH] The filo crashes if the filo and coreboot
	overlap.
In-Reply-To: <4AF05675.1010400@georgi-clan.de>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl>
	<1257005604.23416.18.camel@tetris>
	<DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
	<4AF05675.1010400@georgi-clan.de>
Message-ID: <534e5dc20911031442n1c4d9377na70165bce69104d8@mail.gmail.com>

On Tue, Nov 3, 2009 at 9:12 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 03.11.2009 04:23, schrieb Bao, Zheng:
>>
>> If the coreboot and filo overlap, it will "slice off" a piece at the
>> beginning or end. In the beginning case, a new segment is inserted
>> before the current one. ?The ptr will move forward and doesn't seem to
>> have any chance to process the "new" segment.
>>
>
> You are aware that your patch only has an effect for non-compressed
> payloads?
>

Patrick and Zheng,

I'm struggling to understand the bug. If the payload is uncompressed,
it can put a segment before coreboot in the bouncebuffer (this seems
to be the bug?). Then the loop needs to be re-run on the newly
split/added segment. If it is compressed, It will skip all of the
coreboot area and not allocate a segment before coreboot (put the
entire thing in the bounce buffer?).

Does this get back to the CONFIG_RAMBASE=0x00200000 on fam10?

Marc

-- 
http://marcjonesconsulting.com



From Zheng.Bao at amd.com  Wed Nov  4 03:34:48 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 4 Nov 2009 10:34:48 +0800
Subject: [coreboot] [PATCH] The filo crashes if the filo and coreboot
	overlap.
In-Reply-To: <534e5dc20911031442n1c4d9377na70165bce69104d8@mail.gmail.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl>
	<1257005604.23416.18.camel@tetris>
	<DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
	<4AF05675.1010400@georgi-clan.de>
	<534e5dc20911031442n1c4d9377na70165bce69104d8@mail.gmail.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032A02A4@sbjgexmb1.amd.com>

Marc and Patrick,
The LZMA compressing way doesn't work on my board. I haven't found any solution to resolve the overlapping in current code. ulzma() doesn't seem to know that overlapping happens. It is a problem that has to be solved.

Do you guys agree that my patch anyway fix the bug for non-compressed payloads?

Zheng

-----Original Message-----
From: Marc Jones [mailto:marcj303 at gmail.com] 
Sent: Wednesday, November 04, 2009 6:42 AM
To: Patrick Georgi
Cc: Bao, Zheng; coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] The filo crashes if the filo and coreboot overlap.

On Tue, Nov 3, 2009 at 9:12 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 03.11.2009 04:23, schrieb Bao, Zheng:
>>
>> If the coreboot and filo overlap, it will "slice off" a piece at the
>> beginning or end. In the beginning case, a new segment is inserted
>> before the current one. ?The ptr will move forward and doesn't seem to
>> have any chance to process the "new" segment.
>>
>
> You are aware that your patch only has an effect for non-compressed
> payloads?
>

Patrick and Zheng,

I'm struggling to understand the bug. If the payload is uncompressed,
it can put a segment before coreboot in the bouncebuffer (this seems
to be the bug?). Then the loop needs to be re-run on the newly
split/added segment. If it is compressed, It will skip all of the
coreboot area and not allocate a segment before coreboot (put the
entire thing in the bounce buffer?).

Does this get back to the CONFIG_RAMBASE=0x00200000 on fam10?

Marc

-- 
http://marcjonesconsulting.com





From rminnich at gmail.com  Wed Nov  4 04:04:11 2009
From: rminnich at gmail.com (ron minnich)
Date: Tue, 3 Nov 2009 19:04:11 -0800
Subject: [coreboot] [PATCH] x86emu: add SMSW, RDMSR, WRMSR, INVD, WBINVD
In-Reply-To: <4AEFFF11.7060104@coresystems.de>
References: <4AEFFF11.7060104@coresystems.de>
Message-ID: <13426df10911031904h3b016936qec7100065e85e88f@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From kevin at koconnor.net  Wed Nov  4 04:30:12 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 3 Nov 2009 22:30:12 -0500
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <4AF04CD4.1030007@virtutech.com>
References: <4AF04CD4.1030007@virtutech.com>
Message-ID: <20091104033012.GA32618@morn.localdomain>

On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
> I'm attaching patches for seabios to make it work on the Virtutech  
> Simics x86-440bx model. Please let me know if there is some other list  
> that is preferred for seabios patches.
>
> Patches 1-6 and 9 are not really related to the Virtutech model at all,  
> so those would be prime candidates to be included in the mainline 
> version.

Thanks Magnus.

Gleb I'm not sure if you're on the coreboot mailing list - can you
take a look at these patches as well?  A URL is at:

http://permalink.gmane.org/gmane.linux.bios/55487

-Kevin



From Zheng.Bao at amd.com  Wed Nov  4 07:11:43 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 4 Nov 2009 14:11:43 +0800
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in "CPU/1HT
	device" mode?
In-Reply-To: <8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703780@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17031A4AF1@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703783@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703786@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703789@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870378D@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703792@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5 129D6B1 7032A019D@sb jgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>

Hi, Myles,
About the HT code, I have a question.

I am debugging my board, which is Fam10+RS780+SB700. The CPU and RS780 are the two HT node. It seems like the RS690/SB600 board. In early_ht.c, the comment in enumertate_ht_chain() says,

#if CONFIG_HT_CHAIN_UNITID_BASE != 0 
/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), 
if so, don't need to go through the chain  */

I am wondering if the CONFIG_HT_CHAIN_UNITID_BASE is 0 in my case. If not, why in the supported RS690/SB600 board, the CONFIG_HT_CHAIN_UNITID_BASE is 0.

Thanks.

Zheng

________________________________________
From: Marc Jones [mailto:Marc.Jones at applieddesigncorp.com] 
Sent: Wednesday, November 04, 2009 7:31 AM
To: Bao, Zheng
Cc: Writer, Tim; Xie, Michael; Ni, John; Wang, Qingpei
Subject: RE: coreboot 780/710 review

Joe,
?
I am not sure that you made a good change. I don't completely understand the?defines?either.?These settings are for the pre-HT init and I don't know how much should be setup.? Some of the problems come in when the pre-HT init and the fam10 init don't agree on the UNITID setting. Do you know what the UNITIDs end up as with the legacy bios???
?
I?was not clear how?this?was breaking for you and what your change did. I think that setting CHAIN_UNITID_BASE=0 is wrong since you have two HT devices, CPU, 780/710? 780 is considered the SB since it is Alink to the 710 right? SB_HT_CHAIN_ON_BUS0=1 should put the SB on bus 0. I am not sure about UNITID_OFFSET being set or not. I think that some early HT SB (CHAIN_END_UNITID) had to be hardcoded to 0x6, but ATI doesn't have that problem and you can leave the default setting of 0x20. You can try asking on the coreboot list as well. Myles has been working on the HT code a lot.
I think that?these settings should work:
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
default CONFIG_HT_CHAIN_UNITID_BASE=1

#real SB Unit ID, default is 0x20, mean dont touch it at last
#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6

#make the SB HT chain on bus 0, default is not (0)
default CONFIG_SB_HT_CHAIN_ON_BUS0=1

#only offset for SB chain?, default is yes(1)
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
Also, Note that the coreboot svn was reorganized?yesterday.?Try to make a patch based on the new tree.
Marc
??




From shane_chao at yahoo.com  Wed Nov  4 04:27:41 2009
From: shane_chao at yahoo.com (shane chao)
Date: Tue, 3 Nov 2009 19:27:41 -0800 (PST)
Subject: [coreboot] Ubiquiti embedded boards and Atheros chipset
Message-ID: <539341.44586.qm@web51308.mail.re2.yahoo.com>

Hello,

Does coreboot have any plans to support Ubiquiti embedded boards such as the Ministation or Litestation2/5?  Those board are based on Atheros MIPS processors.

Thanks,
Shane




From elkton.gen at googlemail.com  Wed Nov  4 04:44:51 2009
From: elkton.gen at googlemail.com (elkton gen)
Date: Wed, 4 Nov 2009 03:44:51 +0000
Subject: [coreboot] PX10000G aka Pico ITX
Message-ID: <c526af120911031944x2af050b2t937f3e288578bae0@mail.gmail.com>

Hi,

I'm doing a project for my car and would like to have a very quick
booting system, therefore coreboot would be ideally suited.

http://en.wikipedia.org/wiki/Pico-ITX#PX10000G is the device I'm
targeting but you don't seem to support this, I would like to add this
device, it has:

VIA VX700 Chipset (you only support VX800 or CX700)
VIA C7-M Processor.
VIA VT6106S
VIA VT1708A

By the looks of it only the CPU is support.  So a bit of work to be done...

If anybody can point me to any datasheets for these parts and/or a
contact at VIA who might be helpful in getting access to the
information I require this, would be great.

Elkton.



From svn at coreboot.org  Wed Nov  4 13:18:44 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Wed,  4 Nov 2009 13:18:44 +0100
Subject: [coreboot] [v2] r4908 - in trunk/src/cpu/intel: . model_106cx
	socket_441
Message-ID: <mailman.3987.1355071651.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-04 13:18:44 +0100 (Wed, 04 Nov 2009)
New Revision: 4908

Added:
   trunk/src/cpu/intel/model_106cx/Kconfig
   trunk/src/cpu/intel/model_106cx/Makefile.inc
   trunk/src/cpu/intel/model_106cx/model_106cx_init.c
   trunk/src/cpu/intel/socket_441/Kconfig
   trunk/src/cpu/intel/socket_441/Makefile.inc
Removed:
   trunk/src/cpu/intel/model_106cx/model_6cx_init.c
Modified:
   trunk/src/cpu/intel/Kconfig
   trunk/src/cpu/intel/model_106cx/Config.lb
Log:
Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/src/cpu/intel/Kconfig
===================================================================
--- trunk/src/cpu/intel/Kconfig	2009-11-03 15:02:15 UTC (rev 4907)
+++ trunk/src/cpu/intel/Kconfig	2009-11-04 12:18:44 UTC (rev 4908)
@@ -3,6 +3,7 @@
 source src/cpu/intel/model_6ex/Kconfig
 source src/cpu/intel/model_6fx/Kconfig
 source src/cpu/intel/model_1067x/Kconfig
+source src/cpu/intel/model_106cx/Kconfig
 
 source src/cpu/intel/bga956/Kconfig
 source src/cpu/intel/ep80579/Kconfig
@@ -13,3 +14,4 @@
 #source src/cpu/intel/socket_mPGA603/Kconfig
 source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_PGA370/Kconfig
+source src/cpu/intel/socket_441/Kconfig

Modified: trunk/src/cpu/intel/model_106cx/Config.lb
===================================================================
--- trunk/src/cpu/intel/model_106cx/Config.lb	2009-11-03 15:02:15 UTC (rev 4907)
+++ trunk/src/cpu/intel/model_106cx/Config.lb	2009-11-04 12:18:44 UTC (rev 4908)
@@ -28,4 +28,4 @@
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 dir /cpu/intel/speedstep
-driver model_6cx_init.o
+driver model_106cx_init.o

Added: trunk/src/cpu/intel/model_106cx/Kconfig
===================================================================
--- trunk/src/cpu/intel/model_106cx/Kconfig	                        (rev 0)
+++ trunk/src/cpu/intel/model_106cx/Kconfig	2009-11-04 12:18:44 UTC (rev 4908)
@@ -0,0 +1,3 @@
+config CPU_INTEL_ATOM_230
+	bool
+	select SMP

Added: trunk/src/cpu/intel/model_106cx/Makefile.inc
===================================================================
--- trunk/src/cpu/intel/model_106cx/Makefile.inc	                        (rev 0)
+++ trunk/src/cpu/intel/model_106cx/Makefile.inc	2009-11-04 12:18:44 UTC (rev 4908)
@@ -0,0 +1 @@
+driver-y += model_106cx_init.o

Copied: trunk/src/cpu/intel/model_106cx/model_106cx_init.c (from rev 4907, trunk/src/cpu/intel/model_106cx/model_6cx_init.c)
===================================================================
--- trunk/src/cpu/intel/model_106cx/model_106cx_init.c	                        (rev 0)
+++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c	2009-11-04 12:18:44 UTC (rev 4908)
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <usbdebug_direct.h>
+
+static const uint32_t microcode_updates[] = {
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src) 
+{
+	while (*src) *dst++ = *src++;
+}
+
+static void fill_processor_name(char *processor_name)
+{
+	struct cpuid_result regs;
+	char temp_processor_name[49];
+	char *processor_name_start;
+	unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+	int i;
+
+	for (i=0; i<3; i++) {
+		regs = cpuid(0x80000002 + i);
+		name_as_ints[i*4 + 0] = regs.eax;
+		name_as_ints[i*4 + 1] = regs.ebx;
+		name_as_ints[i*4 + 2] = regs.ecx;
+		name_as_ints[i*4 + 3] = regs.edx;
+	}
+
+	temp_processor_name[48] = 0;
+
+	/* Skip leading spaces */
+	processor_name_start = temp_processor_name;
+	while (*processor_name_start == ' ') 
+		processor_name_start++;
+
+	memset(processor_name, 0, 49);
+	strcpy(processor_name, processor_name_start);
+}
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		msr.lo |= (1 << 2);
+		if (regs.ecx & CPUID_SMX)
+			msr.lo |= (1 << 1);
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+
+	msr.lo |= (1 << 0); /* Set lock bit */
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL	0xe2
+#define PMG_IO_BASE_ADDR	0xe3
+#define PMG_IO_CAPTURE_ADDR	0xe4
+#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
+#define PMB1 0x0	/* IO port that triggers SMI once cores are in the same state.
+			See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
+#define HIGHEST_CLEVEL		3
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 15); // Lock configuration
+	msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
+	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
+	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
+	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+	// set P_BLK address
+	msr = rdmsr(PMG_IO_BASE_ADDR);
+	msr.lo = (PMB0 + 4) | (PMB1 << 16);
+	wrmsr(PMG_IO_BASE_ADDR, msr);
+
+	// set C_LVL controls
+	msr = rdmsr(PMG_IO_CAPTURE_ADDR);
+	msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+	wrmsr(PMG_IO_CAPTURE_ADDR, msr);
+}
+
+#define IA32_MISC_ENABLE	0x1a0
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 3); 	/* TM1 enable */
+	msr.lo |= (1 << 13);	/* TM2 enable */
+	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
+
+	msr.lo |= (1 << 10);	/* FERR# multiplexing */
+
+	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
+	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+
+	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+
+static void model_106cx_init(device_t cpu)
+{
+	char processor_name[49];
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk_info("CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG_DIRECT
+	// Is this caution really needed?
+	if(!ehci_debug_addr) 
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs */
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+
+#if CONFIG_USBDEBUG_DIRECT
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+	/* Enable virtualization */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* TODO: PIC thermal sensor control */
+
+	/* Start up my cpu siblings */
+	intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_106cx_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
+

Deleted: trunk/src/cpu/intel/model_106cx/model_6cx_init.c
===================================================================
--- trunk/src/cpu/intel/model_106cx/model_6cx_init.c	2009-11-03 15:02:15 UTC (rev 4907)
+++ trunk/src/cpu/intel/model_106cx/model_6cx_init.c	2009-11-04 12:18:44 UTC (rev 4908)
@@ -1,224 +0,0 @@
-/*
- * This file is part of the coreboot project.
- * 
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/intel/hyperthreading.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <usbdebug_direct.h>
-
-static const uint32_t microcode_updates[] = {
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
-static inline void strcpy(char *dst, char *src) 
-{
-	while (*src) *dst++ = *src++;
-}
-
-static void fill_processor_name(char *processor_name)
-{
-	struct cpuid_result regs;
-	char temp_processor_name[49];
-	char *processor_name_start;
-	unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
-	int i;
-
-	for (i=0; i<3; i++) {
-		regs = cpuid(0x80000002 + i);
-		name_as_ints[i*4 + 0] = regs.eax;
-		name_as_ints[i*4 + 1] = regs.ebx;
-		name_as_ints[i*4 + 2] = regs.ecx;
-		name_as_ints[i*4 + 3] = regs.edx;
-	}
-
-	temp_processor_name[48] = 0;
-
-	/* Skip leading spaces */
-	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
-		processor_name_start++;
-
-	memset(processor_name, 0, 49);
-	strcpy(processor_name, processor_name_start);
-}
-
-#define IA32_FEATURE_CONTROL 0x003a
-
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
-static void enable_vmx(void)
-{
-	struct cpuid_result regs;
-	msr_t msr;
-
-	msr = rdmsr(IA32_FEATURE_CONTROL);
-
-	if (msr.lo & (1 << 0)) {
-		/* VMX locked. If we set it again we get an illegal
-		 * instruction
-		 */
-		return;
-	}
-
-	regs = cpuid(1);
-	if (regs.ecx & CPUID_VMX) {
-		msr.lo |= (1 << 2);
-		if (regs.ecx & CPUID_SMX)
-			msr.lo |= (1 << 1);
-	}
-
-	wrmsr(IA32_FEATURE_CONTROL, msr);
-
-	msr.lo |= (1 << 0); /* Set lock bit */
-
-	wrmsr(IA32_FEATURE_CONTROL, msr);
-}
-
-#define PMG_CST_CONFIG_CONTROL	0xe2
-#define PMG_IO_BASE_ADDR	0xe3
-#define PMG_IO_CAPTURE_ADDR	0xe4
-#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
-#define PMB1 0x0	/* IO port that triggers SMI once cores are in the same state.
-			See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
-#define HIGHEST_CLEVEL		3
-static void configure_c_states(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
-	msr.lo |= (1 << 15); // Lock configuration
-	msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
-	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
-	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
-	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
-
-	// set P_BLK address
-	msr = rdmsr(PMG_IO_BASE_ADDR);
-	msr.lo = (PMB0 + 4) | (PMB1 << 16);
-	wrmsr(PMG_IO_BASE_ADDR, msr);
-
-	// set C_LVL controls
-	msr = rdmsr(PMG_IO_CAPTURE_ADDR);
-	msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
-	wrmsr(PMG_IO_CAPTURE_ADDR, msr);
-}
-
-#define IA32_MISC_ENABLE	0x1a0
-static void configure_misc(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo |= (1 << 3); 	/* TM1 enable */
-	msr.lo |= (1 << 13);	/* TM2 enable */
-	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
-
-	msr.lo |= (1 << 10);	/* FERR# multiplexing */
-
-	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
-
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
-	wrmsr(IA32_MISC_ENABLE, msr);
-
-	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
-	wrmsr(IA32_MISC_ENABLE, msr);
-}
-
-#if CONFIG_USBDEBUG_DIRECT
-static unsigned ehci_debug_addr;
-#endif
-
-static void model_6ex_init(device_t cpu)
-{
-	char processor_name[49];
-
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-
-	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
-
-	/* Print processor name */
-	fill_processor_name(processor_name);
-	printk_info("CPU: %s.\n", processor_name);
-
-#if CONFIG_USBDEBUG_DIRECT
-	// Is this caution really needed?
-	if(!ehci_debug_addr) 
-		ehci_debug_addr = get_ehci_debug();
-	set_ehci_debug(0);
-#endif
-
-	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
-	x86_mtrr_check();
-
-#if CONFIG_USBDEBUG_DIRECT
-	set_ehci_debug(ehci_debug_addr);
-#endif
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-
-	/* Enable virtualization */
-	enable_vmx();
-
-	/* Configure C States */
-	configure_c_states();
-
-	/* Configure Enhanced SpeedStep and Thermal Sensors */
-	configure_misc();
-
-	/* TODO: PIC thermal sensor control */
-
-	/* Start up my cpu siblings */
-	intel_sibling_init(cpu);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init     = model_6ex_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */
-	{ X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */
-	{ X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
-

Added: trunk/src/cpu/intel/socket_441/Kconfig
===================================================================
--- trunk/src/cpu/intel/socket_441/Kconfig	                        (rev 0)
+++ trunk/src/cpu/intel/socket_441/Kconfig	2009-11-04 12:18:44 UTC (rev 4908)
@@ -0,0 +1,5 @@
+config CPU_INTEL_SOCKET_441
+	bool
+	select CPU_INTEL_MODEL_106CX
+	select MMX
+	select SSE

Added: trunk/src/cpu/intel/socket_441/Makefile.inc
===================================================================
--- trunk/src/cpu/intel/socket_441/Makefile.inc	                        (rev 0)
+++ trunk/src/cpu/intel/socket_441/Makefile.inc	2009-11-04 12:18:44 UTC (rev 4908)
@@ -0,0 +1,10 @@
+obj-y += socket_441.o
+subdirs-y += ../model_106cx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+




From zhangxc at brainaire.com  Wed Nov  4 14:05:49 2009
From: zhangxc at brainaire.com (zhangxc)
Date: Wed, 4 Nov 2009 21:05:49 +0800
Subject: [coreboot] Puzzles about coreboot when compiling "Kontron 986LCD-M"
Message-ID: <200911042105471259326@brainaire.com>

Hi Stepan,
Glad to know that you're developing  "Kontron 986LCD-M/mITX", and i'm trying to understand this excellent 986LCD-M board using Intel ICH7 as southbridge, i wanna create the bios image using Coreboot, but I even can't compile it after several tries.
--------
My platform: 
Fedora 8 (Linux localhost.localdomain 2.6.23.1-42.fc8 #1 SMP Tue Oct 30 13:55:12 EDT 2007 i686 i686 i386 GNU/Linux)
--------
Src code:
http://tracker.coreboot.org/trac/coreboot/browser/branches/coreboot-v2-newbuild
--------
My steps: Reference to "http://www.coreboot.org/Kontron_986LCD-M_mITX"
1 Install "iasl" utility, and choose "filo" as the payload, and generate the "filo.elf" successfully.
2 ./buildtarget kontron/986lcd-m --> This will generate a new directory (naming "kontron_986lcd_m") where the key Makefile lies
3 Enter into the new dir, and copy the "filo.elf" to this new dir, but rename it as "payload.elf"
4 make -s --> This will fail, the message is as follows:
     ...
/workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:25: warning: no previous prototype for soft_reset?
/workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:30: warning: no previous prototype for hard_reset?
input/output = 302368/124894 = 2.421
/usr/bin/ld: coreboot: section `.id' can't be allocated in segment 1
/usr/bin/ld: final link failed: Bad value
collect2: ld returned 1 exit status
make[1]: *** [coreboot] Error 1
make: *** [fallback/coreboot.rom] Error 2
------------------
So, what is the problem? What kind of platform have you tried, Stepan?
Thank you.
ps: I also tried using "make menuconfig" "make" for the codes at "http://tracker.coreboot.org/trac/coreboot/browser/trunk/"
the same mistake occurred.

2009-11-04 



Terry Zhang
Hardware R&D Engineer
Beijing Brainaire Storage Technologies Ltd.
Email: zhangxc at brainaire.com
Tel: 86-10-6297-9839
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From stepan at coresystems.de  Wed Nov  4 14:44:02 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 04 Nov 2009 14:44:02 +0100
Subject: [coreboot] Puzzles about coreboot when compiling "Kontron
	986LCD-M"
In-Reply-To: <200911042105471259326@brainaire.com>
References: <200911042105471259326@brainaire.com>
Message-ID: <4AF18522.2020508@coresystems.de>

zhangxc wrote:
> Hi Stepan,
> Glad to know that you're developing  "Kontron 986LCD-M/mITX", and i'm trying to understand this excellent 986LCD-M board using Intel ICH7 as southbridge, i wanna create the bios image using Coreboot, but I even can't compile it after several tries.
> --------
> My platform: 
> Fedora 8 (Linux localhost.localdomain 2.6.23.1-42.fc8 #1 SMP Tue Oct 30 13:55:12 EDT 2007 i686 i686 i386 GNU/Linux)
> --------
> Src code:
> http://tracker.coreboot.org/trac/coreboot/browser/branches/coreboot-v2-newbuild
This branch is not working correctly.. I suggest you use
http://tracker.coreboot.org/trac/coreboot/browser/trunk instead.

This can be checked out with subversion through

svn co svn://coreboot.org/coreboot/trunk coreboot
or if your company firewall blocks the svn ports:
svn co https://svn.coreboot.org/coreboot/trunk coreboot

> --------
> My steps: Reference to "http://www.coreboot.org/Kontron_986LCD-M_mITX"
> 1 Install "iasl" utility, and choose "filo" as the payload, and generate the "filo.elf" successfully.
> 2 ./buildtarget kontron/986lcd-m --> This will generate a new directory (naming "kontron_986lcd_m") where the key Makefile lies
> 3 Enter into the new dir, and copy the "filo.elf" to this new dir, but rename it as "payload.elf"
> 4 make -s --> This will fail, the message is as follows:
>      ...
> /workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:25: warning: no previous prototype for soft_reset?
> /workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:30: warning: no previous prototype for hard_reset?
> input/output = 302368/124894 = 2.421
> /usr/bin/ld: coreboot: section `.id' can't be allocated in segment 1
> /usr/bin/ld: final link failed: Bad value
> collect2: ld returned 1 exit status
> make[1]: *** [coreboot] Error 1
> make: *** [fallback/coreboot.rom] Error 2
> ------------------
> So, what is the problem? What kind of platform have you tried, Stepan?

This seems to be a problem with a buggy binutils package delivered with
Fedora 8.

To get reliable and comparable results, I'm only using the cross
toolchain built by the script coreboot/util/crossgcc/buildgcc ... It
will produce a known good toolchain.

> Thank you.
Good luck!

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From gleb at redhat.com  Wed Nov  4 15:40:11 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Wed, 4 Nov 2009 16:40:11 +0200
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <20091104033012.GA32618@morn.localdomain>
References: <4AF04CD4.1030007@virtutech.com>
	<20091104033012.GA32618@morn.localdomain>
Message-ID: <20091104144011.GR27911@redhat.com>

On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
> On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
> > I'm attaching patches for seabios to make it work on the Virtutech  
> > Simics x86-440bx model. Please let me know if there is some other list  
> > that is preferred for seabios patches.
> >
> > Patches 1-6 and 9 are not really related to the Virtutech model at all,  
> > so those would be prime candidates to be included in the mainline 
> > version.
> 
l> Thanks Magnus.
> 
> Gleb I'm not sure if you're on the coreboot mailing list - can you
> take a look at these patches as well?  A URL is at:
> 
> http://permalink.gmane.org/gmane.linux.bios/55487
> 
Can I get them in a mbox format somewhere? Want to tested them to be
sure. From review:
1:
 OK

2:
 What is the reason for this? x86info --mptable on my 4 core AMD shows
MP Table:
#       APIC ID Version State           Family  Model   Step    Flags
#        0       0x10    BSP, usable     16      4       1     0x178bfbff
#        1       0x10    AP, usable      16      4       1     0x178bfbff
#        2       0x10    AP, usable      16      4       1     0x178bfbff
#        3       0x10    AP, usable      16      4       1     0x178bfbff

3:
 And why is this? My mptable spec (from 1997) says that apic id is 8 bit
 and x86info --mptable on my Intel with 16 logical cpus shows:
MP Table:
#       APIC ID Version State           Family  Model   Step    Flags
#        0       0x15    BSP, usable     6       10      5       0x0381
#       16       0x15    AP, usable      6       10      5       0x0381
Interesting that on Intel only one entry per physical package.

4:
 I am not sure why we want to make it faster (waiting anyway) but OK.

5:
 OK. Wanted to add this by myself for a long time. We configure LINT0 inside KVM
 now, but this is BIOS job.

6:
 OK.

7:
 Don't like VIRTUTECH_IRQ0_OVERRIDE checking inside qemu_cfg_irq0_override().
 What about creating irq0_override() in generic code that will call
 qemu_cfg_irq0_override() if needed. Setting VIRTUTECH_IRQ0_OVERRIDE to
 1 by default is not a welcomed too :)

8:
 Do not set VIRTUTECH_PC_SHADOW to 1 by default please. Otherwise the
 code is not used by qemu so OK.

9:
 OK
 
10:
 USE_CMOS_BIOS_SMP_COUNT default to 1
 
--
			Gleb.



From mylesgw at gmail.com  Wed Nov  4 16:23:55 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 08:23:55 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF05D0E.1090509@lanl.gov>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910291201w3004f537r932049dbe1fc69fa@mail.gmail.com>	
	<4AE9FBB9.50901@lanl.gov>	
	<2831fecf0910291352w713aee6ejad58116739081730@mail.gmail.com>	
	<2831fecf0910291555r2e3c16d3uf2b98a7f8645037d@mail.gmail.com>	
	<1256861017.13389.5.camel@nibbler>	
	<65882F71165E484DA95FD5AA7FA8D397@chimp>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
	<4AF05D0E.1090509@lanl.gov>
Message-ID: <53EE93627FF84745B89CAD3F1266F70C@chimp>

> Myles,
> 
> I'm not sure what you mean by: "Change the hard coded values." Where
> should I change them?
Send me the latest output and I'll send you a patch to test.

Thanks,
Myles




From hng at lanl.gov  Wed Nov  4 17:01:18 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 09:01:18 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <53EE93627FF84745B89CAD3F1266F70C@chimp>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910291201w3004f537r932049dbe1fc69fa@mail.gmail.com>	
	<4AE9FBB9.50901@lanl.gov>	
	<2831fecf0910291352w713aee6ejad58116739081730@mail.gmail.com>	
	<2831fecf0910291555r2e3c16d3uf2b98a7f8645037d@mail.gmail.com>	
	<1256861017.13389.5.camel@nibbler>	
	<65882F71165E484DA95FD5AA7FA8D397@chimp>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
	<4AF05D0E.1090509@lanl.gov>
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
Message-ID: <4AF1A54E.4060702@lanl.gov>

Myles,

Attached is the latest output.  Thanks.

-- 
Hugh Greenberg




Myles Watson wrote:
>> Myles,
>>
>> I'm not sure what you mean by: "Change the hard coded values." Where
>> should I change them?
>>     
> Send me the latest output and I'll send you a patch to test.
>
> Thanks,
> Myles
>
>   
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From mylesgw at gmail.com  Wed Nov  4 18:02:09 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 10:02:09 -0700
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in
	"CPU/1HT device" mode?
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703780@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17031A4AF1@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703783@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703786@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703789@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870378D@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703792@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5 129D6B17032A019D@s bjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
Message-ID: <377D3F0E4E364903B8D148321EFA802E@chimp>

> Hi, Myles,
> About the HT code, I have a question.
> 
> I am debugging my board, which is Fam10+RS780+SB700. The CPU and RS780 are
> the two HT node. 
Aren't there three?  How is the SB700 connected to the RS780?

> It seems like the RS690/SB600 board. 
The RS690/SB600 board has three.

> In early_ht.c, the
> comment in enumertate_ht_chain() says, 
> #if CONFIG_HT_CHAIN_UNITID_BASE != 0
> /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht
> chain),
> if so, don't need to go through the chain  */
> 
> I am wondering if the CONFIG_HT_CHAIN_UNITID_BASE is 0 in my case. If not,
> why in the supported RS690/SB600 board, the CONFIG_HT_CHAIN_UNITID_BASE is
> 0.
Good question.  How does it end up being enumerated?

Does the lspci end up how you would expect/like on your board?

Part of the confusing part to me is that there are three enumerations that
can happen:

early_ht.c: Just enumerate the southbridge chain in case that's needed for
serial initialization or ROM access.

incoherent_ht.c: Enumerate all chains so that they can be optimized before
the first reset.

hypertransport.c: Enumerate the chains according to the device tree.

Thanks,
Myles 




From mylesgw at gmail.com  Wed Nov  4 18:33:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 11:33:54 -0600
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF1A54E.4060702@lanl.gov>
References: <4ADF378A.5050506@lanl.gov>
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>
	<4AEB71A8.2010604@lanl.gov>
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov> <6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
	<4AF05D0E.1090509@lanl.gov> <53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>
Message-ID: <2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>

Here's a patch that will either work or help us figure out what's going
wrong.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From stepan at coresystems.de  Wed Nov  4 19:04:29 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 04 Nov 2009 19:04:29 +0100
Subject: [coreboot] [PATCH] ACPI updates + S3 Resume without hole at 31MB
In-Reply-To: <4AE5DC09.9030604@coresystems.de>
References: <4AE5DC09.9030604@coresystems.de>
Message-ID: <4AF1C22D.2060300@coresystems.de>

Stefan Reinauer wrote:
> See patch. This works nicely on two i945 machines I have here
> (unfortunately not the Kontron 986lcd-m due to some other reason)
> Probably needs some fixing for the AMD board that Rudolf got running
> with Resume. Rudolf, can you jump in, I don't have that hardware..
>
> Stefan
>   

> * Simplify acpi_add_table
> * fix some comments
> * Simplify ACPI wakeup code and make it work without a memory hole
> * Add resume entries to global GDT so we don't need our own for resume.
> * add ECDT description to acpi.h for anyone who might need it  ;-) 
> * remove rather stupid math to get the right number of MAX_ACPI_TABLES
>   and just define a reasonable maximum for now.
>
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>


ping?

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From mark.marshall at csr.com  Wed Nov  4 19:05:53 2009
From: mark.marshall at csr.com (Mark Marshall)
Date: Wed, 04 Nov 2009 18:05:53 +0000
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <hc6lsa$hqg$1@ger.gmane.org>
References: <hc6lsa$hqg$1@ger.gmane.org>
Message-ID: <4AF1C281.3030502@csr.com>

Ping.

Mark Marshall wrote:
> Below are three small patches, they all seemed useful while I have been 
> working with VGA option ROMs.
> 
> Thanks for the great work.
> 
> MM
> 




From hng at lanl.gov  Wed Nov  4 19:06:30 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 11:06:30 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910301459j6ac915dax61aede742b9c3550@mail.gmail.com>	
	<4AEB71A8.2010604@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>	
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>	
	<4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>	
	<4AF05D0E.1090509@lanl.gov>
	<53EE93627FF84745B89CAD3F1266F70C@chimp>	
	<4AF1A54E.4060702@lanl.gov>
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>
Message-ID: <4AF1C2A6.80703@lanl.gov>

Myles,

It worked.  Coreboot boots with SB_HT_CHAIN_ON_BUS_0 set to one and the 
previous patch.  Seabios also detects the network devices without 
setting CONFIG_PCI_ROOT1 to 0x02.  Attached is the output.  Seabios was 
compiled with DEBUG_LEVEL set to 8.

-- 
Hugh Greenberg




Myles Watson wrote:
> Here's a patch that will either work or help us figure out what's 
> going wrong.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com <mailto:mylesgw at gmail.com>>
>
> Thanks,
> Myles
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From mylesgw at gmail.com  Wed Nov  4 19:21:29 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 12:21:29 -0600
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF1C2A6.80703@lanl.gov>
References: <4ADF378A.5050506@lanl.gov>
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>
	<4AEF2C80.8070608@lanl.gov> <6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
	<4AF05D0E.1090509@lanl.gov> <53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>
	<4AF1C2A6.80703@lanl.gov>
Message-ID: <2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>

On Wed, Nov 4, 2009 at 12:06 PM, Hugh Greenberg <hng at lanl.gov> wrote:

> Myles,
>
> It worked.  Coreboot boots with SB_HT_CHAIN_ON_BUS_0 set to one and the
> previous patch.  Seabios also detects the network devices without setting
> CONFIG_PCI_ROOT1 to 0x02.  Attached is the output.  Seabios was compiled
> with DEBUG_LEVEL set to 8.
>

ERROR - cound not find bus for node 0 chain 0, using defaults
ERROR - could not find PCI 1:01.0, using defaults
ERROR - could not find PCI 1:02.0, using defaults
Wrote the mp table end at: 000f0410 - 000f05e4
Adding CBMEM entry as no. 3
Looking for bad PCIX MHz input
Looking for bad Hot Swap Enable
OK 133MHz & Hot Swap is off
ERROR - cound not find bus for node 0 chain 0, using defaults
ERROR - could not find PCI 1:01.0, using defaults
ERROR - could not find PCI 1:02.0, using defaults
Wrote the mp table end at: 3fff1410 - 3fff15e4

It almost worked.  Can you try the attached patch?

Is it actually booting into Linux?

Thanks,
Myles
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From mylesgw at gmail.com  Wed Nov  4 19:53:17 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 11:53:17 -0700
Subject: [coreboot] failing fam10 code in coreboot
In-Reply-To: <4AF16B19.4030309@ziti.uni-heidelberg.de>
References: <4AE0196E.4020700@ziti.uni-heidelberg.de>
	<DD4107FB02D24FB9933EE58CC5DA4F0F@chimp>
	<4AF16B19.4030309@ziti.uni-heidelberg.de>
Message-ID: <83733B86F7DE4682B6819737D38A05A4@chimp>



> -----Original Message-----
> From: Maximilian Thuermer [mailto:Maximilian.Thuermer at ziti.uni-
> heidelberg.de]
> Sent: Wednesday, November 04, 2009 4:53 AM
> To: Myles Watson
> Subject: failing fam10 code in coreboot
> 
> Myles,
> 
> sorry it took so long to get back to you. I checked revs 4787 and 4788
> and attached the significant parts of the logs. You were right with the
> assumption that the problem first occured in rev 4788. I also attached
> the coreboot_ram.map files.
> Hope this helps tracking down the bug...
> 
> Best regards,
> 
> 
> Maximilian
> 
> Myles Watson wrote:
> >> I did a fresh svn co the other day and tried building and
> >> running a Tyan S2912_fam10 system. With older sources
> >> (rev 4729) everything worked just fine, with the newest checkout
> >> the booting process stops at setting MTRR registers or a little
> >> later (depending on the compiler used: 3.4.6 builds faster code
> >> and gets further than 4.3.3, both Ubuntu fashion).
> >> I tried tracking down the problem and it appeared to me as if
> >> the switch from CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP
> >>
> > It's possible.  Could you try Rev 4787 & 4788 to make sure, then send me
> the
> > logs from both?  I'm also interested in the coreboot_ram.map files.
That's really weird.  It looks like memory corruption, because CONFIG_RAMTOP
(the top of memory that coreboot_ram can use) shouldn't affect the variable
MTRR setup for the top of real RAM.

I'm surprised that there was a difference in the coreboot_ram.map file too.
I don't see how the changes affected the length of the stack!

Which toolchain did you use to build these two?  Are you using Kconfig or
./buildtarget?

Can you try making the stack a lot bigger and seeing if that helps?

CONFIG_STACK_SIZE is now 8K, but try 64K. (0x10000)

I can't see why CONFIG_RAMTOP is 16M.  Your coreboot_ram.map file says you
could fit under 2M.  That might not be true with a 64K stack, but for sure
4M.

Thanks,
Myles




From mylesgw at gmail.com  Wed Nov  4 19:58:03 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 11:58:03 -0700
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <4AF1C281.3030502@csr.com>
References: <hc6lsa$hqg$1@ger.gmane.org> <4AF1C281.3030502@csr.com>
Message-ID: <808D748A06A04C8DA0CC4E66ED079386@chimp>

> Ping.
The two x86emu fixes look fine to me, but I haven't tested them.

I don't think we should depend on the value from the card.  The point of
that check is to make sure we don't run the wrong types of ROMs.  One way to
work around it would be to correct the VGA BIOS from your card and put it
into CBFS.

Thanks,
Myles




From mylesgw at gmail.com  Wed Nov  4 20:50:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 13:50:54 -0600
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in
	"CPU/1HT device" mode?
In-Reply-To: <377D3F0E4E364903B8D148321EFA802E@chimp>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
	<377D3F0E4E364903B8D148321EFA802E@chimp>
Message-ID: <2831fecf0911041150l5bfec07ao54b0ddff7b3ec1da@mail.gmail.com>

On Wed, Nov 4, 2009 at 11:02 AM, Myles Watson <mylesgw at gmail.com> wrote:

> > Hi, Myles,
> > About the HT code, I have a question.
> >
> > I am debugging my board, which is Fam10+RS780+SB700. The CPU and RS780
> are
> > the two HT node.
>
Is there a SimNOW config that is close?  Could you make one?  That would
make it easier to help.

The latest public SimNOW has the RS780 and SB700.

Thanks,
Myles
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From hng at lanl.gov  Wed Nov  4 22:48:44 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 14:48:44 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov>	
	<2831fecf0910301638n2325154ex752cb2e7e82c54ca@mail.gmail.com>	
	<2831fecf0910311517i2d73f6f4o8b4d87aa18d645d8@mail.gmail.com>	
	<4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>	
	<4AF05D0E.1090509@lanl.gov>
	<53EE93627FF84745B89CAD3F1266F70C@chimp>	
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>
Message-ID: <4AF1F6BC.1050606@lanl.gov>

Attached is the latest output.  I don't see the errors anymore.  I just 
tried booting Linux with the latest rom and it booted.

-- 
Hugh Greenberg



Myles Watson wrote:
>
>
> On Wed, Nov 4, 2009 at 12:06 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     Myles,
>
>     It worked.  Coreboot boots with SB_HT_CHAIN_ON_BUS_0 set to one
>     and the previous patch.  Seabios also detects the network devices
>     without setting CONFIG_PCI_ROOT1 to 0x02.  Attached is the output.
>      Seabios was compiled with DEBUG_LEVEL set to 8.
>
>
> ERROR - cound not find bus for node 0 chain 0, using defaults
> ERROR - could not find PCI 1:01.0, using defaults
> ERROR - could not find PCI 1:02.0, using defaults
> Wrote the mp table end at: 000f0410 - 000f05e4
> Adding CBMEM entry as no. 3
> Looking for bad PCIX MHz input
> Looking for bad Hot Swap Enable
> OK 133MHz & Hot Swap is off
> ERROR - cound not find bus for node 0 chain 0, using defaults
> ERROR - could not find PCI 1:01.0, using defaults
> ERROR - could not find PCI 1:02.0, using defaults
> Wrote the mp table end at: 3fff1410 - 3fff15e4
>
> It almost worked.  Can you try the attached patch?
>
> Is it actually booting into Linux?
>
> Thanks,
> Myles
>
>
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From mylesgw at gmail.com  Wed Nov  4 22:53:47 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 14:53:47 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF1F6BC.1050606@lanl.gov>
References: <4ADF378A.5050506@lanl.gov> <4AEF2C80.8070608@lanl.gov>
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp> <4AF05D0E.1090509@lanl.gov>
	<53EE93627FF84745B89CAD3F1266F70C@chimp> <4AF1A54E.4060702@lanl.gov>
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>
	<4AF1C2A6.80703@lanl.gov>
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>
	<4AF1F6BC.1050606@lanl.gov>
Message-ID: <2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>

On Wed, Nov 4, 2009 at 2:48 PM, Hugh Greenberg <hng at lanl.gov> wrote:

> Attached is the latest output.  I don't see the errors anymore.  I just
> tried booting Linux with the latest rom and it booted.
>
Great!  So is everything finally working, or are you still fighting sporadic
hangs?

We should commit the fixes so they don't get lost.

Thanks,
Myles
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From mylesgw at gmail.com  Wed Nov  4 22:58:31 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 14:58:31 -0700
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in
	"CPU/1HT device" mode?
In-Reply-To: <377D3F0E4E364903B8D148321EFA802E@chimp>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
	<377D3F0E4E364903B8D148321EFA802E@chimp>
Message-ID: <2831fecf0911041358r6b037ad4u770aae1cf663e566@mail.gmail.com>

On Wed, Nov 4, 2009 at 10:02 AM, Myles Watson <mylesgw at gmail.com> wrote:

> > Hi, Myles,
> > About the HT code, I have a question.
> >
> > I am debugging my board, which is Fam10+RS780+SB700. The CPU and RS780
> are
> > the two HT node.
> Aren't there three?  How is the SB700 connected to the RS780?
>
> > It seems like the RS690/SB600 board.
> The RS690/SB600 board has three.
>
I looked again, and it doesn't.  Sorry about that.  It looked like three at
first because there are two 'chip' declarations on that HT link, but since
the second one doesn't start at 0.0, it doesn't get separated as a link in
the chain.


> > In early_ht.c, the
> > comment in enumertate_ht_chain() says,
> > #if CONFIG_HT_CHAIN_UNITID_BASE != 0
> > /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht
> > chain),
> > if so, don't need to go through the chain  */
> >
> > I am wondering if the CONFIG_HT_CHAIN_UNITID_BASE is 0 in my case. If
> not,
> > why in the supported RS690/SB600 board, the CONFIG_HT_CHAIN_UNITID_BASE
> is
> > 0.
>
I think it should be.  As long as it is the only member of the chain is
should work fine to just leave it at 0.

Thanks,
Myles
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From r.marek at assembler.cz  Wed Nov  4 23:04:14 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 04 Nov 2009 23:04:14 +0100
Subject: [coreboot] [PATCH] ACPI updates + S3 Resume without hole at 31MB
In-Reply-To: <4AF1C22D.2060300@coresystems.de>
References: <4AE5DC09.9030604@coresystems.de> <4AF1C22D.2060300@coresystems.de>
Message-ID: <4AF1FA5E.7090707@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi

Sorry I tried to get it working on K8 but got distracted by the network support
for SerialICE and network console for coreboot ;)

I think I can Acked-by: Rudolf Marek <r.marek at assembler.cz> Although I would
prefer to have the wakeup trampoline located in the cbmem area. The trick to run
in real mode higher than 1MB would work too and make things safer.

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkrx+l4ACgkQ3J9wPJqZRNX1nwCghMM2i01//qn+1h0DiCbHPYAN
3OsAoOHkKkfOQ7nza70OSi8OI05gQxSL
=cv2a
-----END PGP SIGNATURE-----



From hng at lanl.gov  Wed Nov  4 23:23:57 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 15:23:57 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov> <4AEF2C80.8070608@lanl.gov>	
	<6D90E8F74F9D41DF9E36278BC2C6EF7F@chimp>
	<4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>
Message-ID: <4AF1FEFD.8030007@lanl.gov>

Myles,

Everything seems to be working well.  I had one sporadic hang while 
testing at what looked to be at the same place as the initial first 
hang.  That was the only instance since I moved to gcc 3.4. We were 
testing so many things that I don't remember the exact scenario.   I'm 
satisfied though.  If I see it happening again, I'll try to capture it 
and send it to you.

You deserve a medal for this.  Thanks a lot.

-- 
Hugh Greenberg




Myles Watson wrote:
>
>
> On Wed, Nov 4, 2009 at 2:48 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     Attached is the latest output.  I don't see the errors anymore.  I
>     just tried booting Linux with the latest rom and it booted.
>
> Great!  So is everything finally working, or are you still fighting 
> sporadic hangs?
>
> We should commit the fixes so they don't get lost.
>
> Thanks,
> Myles
>



From joe at settoplinux.org  Wed Nov  4 23:24:39 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Wed, 04 Nov 2009 17:24:39 -0500
Subject: [coreboot] [PATCH] ACPI updates + S3 Resume without hole at 31MB
In-Reply-To: <4AF1FA5E.7090707@assembler.cz>
References: <4AE5DC09.9030604@coresystems.de> <4AF1C22D.2060300@coresystems.de>
	<4AF1FA5E.7090707@assembler.cz>
Message-ID: <4cfd1a903c0a5342437bb4d5421d0334@imap.1and1.com>




On Wed, 04 Nov 2009 23:04:14 +0100, Rudolf Marek <r.marek at assembler.cz>
wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Hi
> 
> Sorry I tried to get it working on K8 but got distracted by the network
> support
> for SerialICE and network console for coreboot ;)
> 
Sorry to get off subject, but what is this all about, do tell :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From mylesgw at gmail.com  Wed Nov  4 23:34:02 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 16:34:02 -0600
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF1FEFD.8030007@lanl.gov>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>
	<53EE93627FF84745B89CAD3F1266F70C@chimp> <4AF1A54E.4060702@lanl.gov>
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>
	<4AF1C2A6.80703@lanl.gov>
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>
	<4AF1F6BC.1050606@lanl.gov>
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>
	<4AF1FEFD.8030007@lanl.gov>
Message-ID: <2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>

On Wed, Nov 4, 2009 at 4:23 PM, Hugh Greenberg <hng at lanl.gov> wrote:

> Myles,
>
> Everything seems to be working well.  I had one sporadic hang while testing
> at what looked to be at the same place as the initial first hang.  That was
> the only instance since I moved to gcc 3.4. We were testing so many things
> that I don't remember the exact scenario.   I'm satisfied though.  If I see
> it happening again, I'll try to capture it and send it to you.
>
Sounds good.  I'd be interested in whether or not it hangs with the newer
gcc still, too.  Since everything else is working, it would be nice to know
if that's really an issue.


> You deserve a medal for this.  Thanks a lot.

No problem.  Would you mind sending svn diff from your working tree so I can
make a patch?  I've lost track of which patches you're using.

Thanks,
Myles
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From hng at lanl.gov  Wed Nov  4 23:37:43 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 15:37:43 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
Message-ID: <4AF20237.6030904@lanl.gov>

Attached is the output from svn diff.   I'll test it with gcc 4.4 and 
let you know if it hangs or not.

-- 
Hugh Greenberg



Myles Watson wrote:
>
>
> On Wed, Nov 4, 2009 at 4:23 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     Myles,
>
>     Everything seems to be working well.  I had one sporadic hang
>     while testing at what looked to be at the same place as the
>     initial first hang.  That was the only instance since I moved to
>     gcc 3.4. We were testing so many things that I don't remember the
>     exact scenario.   I'm satisfied though.  If I see it happening
>     again, I'll try to capture it and send it to you.
>
> Sounds good.  I'd be interested in whether or not it hangs with the 
> newer gcc still, too.  Since everything else is working, it would be 
> nice to know if that's really an issue.
>  
>
>     You deserve a medal for this.  Thanks a lot.
>
> No problem.  Would you mind sending svn diff from your working tree so 
> I can make a patch?  I've lost track of which patches you're using.
>
> Thanks,
> Myles
>
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From marcj303 at gmail.com  Wed Nov  4 23:40:17 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 4 Nov 2009 15:40:17 -0700
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in
	"CPU/1HT device" mode?
In-Reply-To: <377D3F0E4E364903B8D148321EFA802E@chimp>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
	<377D3F0E4E364903B8D148321EFA802E@chimp>
Message-ID: <534e5dc20911041440l75e26df7r26b3e93441294b20@mail.gmail.com>

On Wed, Nov 4, 2009 at 10:02 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> Hi, Myles,
>> About the HT code, I have a question.
>>
>> I am debugging my board, which is Fam10+RS780+SB700. The CPU and RS780 are
>> the two HT node.
> Aren't there three? ?How is the SB700 connected to the RS780?
>
>> It seems like the RS690/SB600 board.
> The RS690/SB600 board has three.

There is just the CPU and 690 or 780. The AMD 600 or 700 is connect
with Alink, not HT.


>
> early_ht.c: Just enumerate the southbridge chain in case that's needed for
> serial initialization or ROM access.
>
> incoherent_ht.c: Enumerate all chains so that they can be optimized before
> the first reset.
>
> hypertransport.c: Enumerate the chains according to the device tree.

Is early_ht.c, enumerate_ht_chain(), even needed. The subtractive path
should work. Maybe depends on the southbridge/configuration.

For Fam10, I think that where problems happen is the early_ht.c sets
values that are found and used by the AGESA based code that has a
slightly different search algorithm. This happens in ht3init.c,
process_link(). Failures in process_link() cause the system to halt
even if it could continue based on the early setup.

Marc

-- 
http://marcjonesconsulting.com



From mylesgw at gmail.com  Wed Nov  4 23:46:00 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 15:46:00 -0700
Subject: [coreboot] what should CONFIG_HT_CHAIN_UNITID_BASE be in
	"CPU/1HT device" mode?
In-Reply-To: <534e5dc20911041440l75e26df7r26b3e93441294b20@mail.gmail.com>
References: <DD1CC71B621B004FA76856E5129D6B17031A4919@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032497CA@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB528703799@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170324987F@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB52870379B@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B170329FDC2@sbjgexmb1.amd.com>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A5@HAWAII.applieddesigncorp.local>
	<8EA6D5C2305F4743BCD98ECB4A3DB5287037A7@HAWAII.applieddesigncorp.local>
	<DD1CC71B621B004FA76856E5129D6B17032A03C3@sbjgexmb1.amd.com>
	<377D3F0E4E364903B8D148321EFA802E@chimp>
	<534e5dc20911041440l75e26df7r26b3e93441294b20@mail.gmail.com>
Message-ID: <AA518F310CD1404EA554E5F605C78731@chimp>

> There is just the CPU and 690 or 780. The AMD 600 or 700 is connect
> with Alink, not HT.
You're right.  I didn't look closely enough.

> > early_ht.c: Just enumerate the southbridge chain in case that's needed
> for
> > serial initialization or ROM access.
> >
> > incoherent_ht.c: Enumerate all chains so that they can be optimized
> before
> > the first reset.
> >
> > hypertransport.c: Enumerate the chains according to the device tree.
> 
> Is early_ht.c, enumerate_ht_chain(), even needed. The subtractive path
> should work. Maybe depends on the southbridge/configuration.
For K8, early_ht.c doesn't even get compiled in if you set
CONFIG_HT_CHAIN_UNITID_BASE to 0.

It's needed for the case where there is a tunnel, then the southbridge.
Serengeti Cheetah is a good example.  You can't get to the southbridge until
you've moved the 8131 or 8132 out of the way.

> For Fam10, I think that where problems happen is the early_ht.c sets
> values that are found and used by the AGESA based code that has a
> slightly different search algorithm. This happens in ht3init.c,
> process_link(). Failures in process_link() cause the system to halt
> even if it could continue based on the early setup.
I wish I knew more about Fam10, but I don't have a board, so I haven't been
that motivated to look into it further.

Thanks,
Myles





From hng at lanl.gov  Thu Nov  5 00:52:46 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 16:52:46 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
Message-ID: <4AF213CE.8060305@lanl.gov>

Yes, it is still hanging occasionally with a newer gcc.  I thought I put 
all the debug stuff back in, but I apparently didn't get it all.   Below 
is the output.  I will put the remaining debug statements back in for 
this hang again and send the output.

coreboot-2.3 Wed Nov  4 16:40:23 MST 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
ht reset -


coreboot-2.3 Wed Nov  4 16:40:23 MST 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3

-- 
Hugh Greenberg




Myles Watson wrote:
>
>
> On Wed, Nov 4, 2009 at 4:23 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     Myles,
>
>     Everything seems to be working well.  I had one sporadic hang
>     while testing at what looked to be at the same place as the
>     initial first hang.  That was the only instance since I moved to
>     gcc 3.4. We were testing so many things that I don't remember the
>     exact scenario.   I'm satisfied though.  If I see it happening
>     again, I'll try to capture it and send it to you.
>
> Sounds good.  I'd be interested in whether or not it hangs with the 
> newer gcc still, too.  Since everything else is working, it would be 
> nice to know if that's really an issue.
>  
>
>     You deserve a medal for this.  Thanks a lot.
>
> No problem.  Would you mind sending svn diff from your working tree so 
> I can make a patch?  I've lost track of which patches you're using.
>
> Thanks,
> Myles
>



From mylesgw at gmail.com  Thu Nov  5 01:06:28 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 17:06:28 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF213CE.8060305@lanl.gov>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
	<4AF213CE.8060305@lanl.gov>
Message-ID: <DA2B2D493A494064AE8A9D6A06FD5A38@chimp>

> Yes, it is still hanging occasionally with a newer gcc.  
Too bad.  Occasionally like 1-in-3?  I don't have any idea what the compiler
would have to do with non-deterministic hangs.

> I thought I put
> all the debug stuff back in, but I apparently didn't get it all.   Below
> is the output.  I will put the remaining debug statements back in for
> this hang again and send the output.
OK.  The other thing to find out is if you still need the "Forcing Type 1"
hack.  Everything else is nearly trivial since it only affects your board,
and you've tested it.

Thanks,
Myles




From hng at lanl.gov  Thu Nov  5 01:16:49 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 17:16:49 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <DA2B2D493A494064AE8A9D6A06FD5A38@chimp>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
	<4AF213CE.8060305@lanl.gov>
	<DA2B2D493A494064AE8A9D6A06FD5A38@chimp>
Message-ID: <4AF21971.1080802@lanl.gov>

Sometimes it takes a very long time to reproduce.   It is very random.  
I just tried about 30 times and I was not able to reproduce it.  Ok, I 
will see if I still need that.

-- 
Hugh Greenberg
Los Alamos National Laboratory, CCS-1
Email: hng at lanl.gov
Phone: (505) 665-6471



Myles Watson wrote:
>> Yes, it is still hanging occasionally with a newer gcc.  
>>     
> Too bad.  Occasionally like 1-in-3?  I don't have any idea what the compiler
> would have to do with non-deterministic hangs.
>
>   
>> I thought I put
>> all the debug stuff back in, but I apparently didn't get it all.   Below
>> is the output.  I will put the remaining debug statements back in for
>> this hang again and send the output.
>>     
> OK.  The other thing to find out is if you still need the "Forcing Type 1"
> hack.  Everything else is nearly trivial since it only affects your board,
> and you've tested it.
>
> Thanks,
> Myles
>
>   



From hng at lanl.gov  Thu Nov  5 01:40:47 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Wed, 04 Nov 2009 17:40:47 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <DA2B2D493A494064AE8A9D6A06FD5A38@chimp>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
	<4AF213CE.8060305@lanl.gov>
	<DA2B2D493A494064AE8A9D6A06FD5A38@chimp>
Message-ID: <4AF21F0F.6050305@lanl.gov>

It doesn't seem like I need the forcing type 1 hack anymore.

I reproduced the hang with some of the debugging statements back in. I 
hope that is all you need. Here is the output:

coreboot-2.3 Wed Nov 4 17:28:13 MST 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1
dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
ht reset -


coreboot-2.3 Wed Nov 4 17:28:13 MST 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
started ap apicid:
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
Before starting clocks: Before memreset:

-- 
Hugh Greenberg




Myles Watson wrote:
>> Yes, it is still hanging occasionally with a newer gcc.  
>>     
> Too bad.  Occasionally like 1-in-3?  I don't have any idea what the compiler
> would have to do with non-deterministic hangs.
>
>   
>> I thought I put
>> all the debug stuff back in, but I apparently didn't get it all.   Below
>> is the output.  I will put the remaining debug statements back in for
>> this hang again and send the output.
>>     
> OK.  The other thing to find out is if you still need the "Forcing Type 1"
> hack.  Everything else is nearly trivial since it only affects your board,
> and you've tested it.
>
> Thanks,
> Myles
>
>   



From Zheng.Bao at amd.com  Thu Nov  5 02:28:27 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 5 Nov 2009 09:28:27 +0800
Subject: [coreboot] [PATCH] The filo crashes if the filo and
	corebootoverlap.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl><1257005604.23416.18.camel@tetris><DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032A05E7@sbjgexmb1.amd.com>

Ping, before we forget.
Can anyone ack or nack this?

Zheng


-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
Sent: Tuesday, November 03, 2009 11:23 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] The filo crashes if the filo and
corebootoverlap.

If the coreboot and filo overlap, it will "slice off" a piece at the
beginning or end. In the beginning case, a new segment is inserted
before the current one.  The ptr will move forward and doesn't seem to
have any chance to process the "new" segment.

                ptr ---------+     move --->
                             |
                             V
        +--------+       +--------+
        |        |       |        |
        |  new   | <---> |current | <---> .....
        |        |       |        |
        +--------+       +--------+

Now we change the ptr to the previous one and restart the loop. The
new and current segment will both be processed.

      +----------------ptr      move --->
      |
      V
 +--------+        +--------+       +--------+
 |        |        |        |       |        |
 |  prev  | <--->  |  new   | <---> |current | <---> .....
 |        |        |        |       |        |
 +--------+        +--------+       +--------+

It is tested on my Family 10 board.

Zheng

Signed-off-by: Zheng Bao <zheng.bao at amd.com>


Index: src/boot/selfboot.c
===================================================================
--- src/boot/selfboot.c	(revision 4892)
+++ src/boot/selfboot.c	(working copy)
@@ -211,19 +211,21 @@
 	return !((end <= lb_start) || (start >= lb_end));
 }
 
-static void relocate_segment(unsigned long buffer, struct segment *seg)
+static int relocate_segment(unsigned long buffer, struct segment *seg)
 {
 	/* Modify all segments that want to load onto coreboot
 	 * to load onto the bounce buffer instead.
 	 */
-	unsigned long start, middle, end;
+	/* ret:  1 : A new segment is inserted before the seg.
+	 *       0 : A new segment is inserted after the seg, or no new
one. */
+	unsigned long start, middle, end, ret = 0;
 
 	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
 		lb_start, lb_end);
 
 	/* I don't conflict with coreboot so get out of here */
 	if (!overlaps_coreboot(seg))
-		return;
+		return 0;
 
 	start = seg->s_dstaddr;
 	middle = start + seg->s_filesz;
@@ -270,6 +272,8 @@
 				new->s_dstaddr, 
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
+
+			ret = 1;
 		}
 			
 		/* Slice off a piece at the end 
@@ -319,6 +323,8 @@
 		seg->s_dstaddr, 
 		seg->s_dstaddr + seg->s_filesz, 
 		seg->s_dstaddr + seg->s_memsz);
+
+	return ret;
 }
 
 
@@ -446,7 +452,10 @@
 		
 		/* Modify the segment to load onto the bounce_buffer if
necessary.
 		 */
-		relocate_segment(bounce_buffer, ptr);
+		if (relocate_segment(bounce_buffer, ptr)) {
+			ptr = (ptr->prev)->prev;
+			continue;
+		}
 
 		printk_debug("Post relocation: addr: 0x%016lx memsz:
0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);

-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
Sent: Monday, November 02, 2009 11:25 AM
To: Patrick Georgi
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] The filo crashes if the filo and coreboot
overlap.

In relocate_segment().
If the coreboot and filo overlap, it will "slice off" a piece at the
beginning or end. A new segment is allocated. If it is inserted before
the "seg" that is being processed, is there any chance that the "new"
segment will be processed? I am confused about it. On my fam 10 board,
it seems that the "new" segment was not processed and an error happens
when the code jumps to filo which is actually middle of nowhere.


Zheng

-----Original Message-----
From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
Patrick Georgi
Sent: Sunday, November 01, 2009 12:13 AM
To: Zheng Bao
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] The filo crashes if the filo and coreboot
overlap.

Am Samstag, den 31.10.2009, 15:43 +0000 schrieb Zheng Bao:
> The filo crashes if the filo and coreboot overlap.
> Since the CBFS is the must-have feature, my family 10
>  board crashes when it jumps to filo. I am trying to
>  find out why. I need help.
> Based on current code, the AMD Family 10 will cause the filo
> and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c
> will return 1. But I am not sure if it will make the system
> crashes.
What revision is that? There was an issue like that but I fixed it
several weeks ago.

> If anybody explains briefly what happens if they
> overlap.
When coreboot and payload overlap, coreboot uses a bounce buffer. The
bounce buffer is twice the size of coreboot. The first half is for the
part of the payload that overlaps coreboot, the other half is for
coreboot itself.

The SELF loader loads data that would overlap coreboot to the bounce
buffer, and jumps into jmp_to_elf_entry when it's done with loading.
The jmp_to_elf_entry function copies coreboot to the upper half of the
bounce buffer, and jumps in there, so the code is out of the way.

Then it copies the lower half to the coreboot area and jumps to the
entry point.

There are some complications to that because of the decompression
routine, so the code is not as nice as it should be. But I specifically
tested your scenario (payload from 1mb to 2.3mb or so, coreboot starting
at 2mb)

> The coreboot information:
> CONFIG_RAMBASE=0x00200000
Try changing that to 0x100000.


Patrick


-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot



-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot





From mylesgw at gmail.com  Thu Nov  5 05:47:34 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 4 Nov 2009 21:47:34 -0700
Subject: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
In-Reply-To: <4AF21F0F.6050305@lanl.gov>
References: <4ADF378A.5050506@lanl.gov> <4AF05D0E.1090509@lanl.gov>	
	<53EE93627FF84745B89CAD3F1266F70C@chimp>
	<4AF1A54E.4060702@lanl.gov>	
	<2831fecf0911040933s95a5bc9ja750ce221132a26f@mail.gmail.com>	
	<4AF1C2A6.80703@lanl.gov>	
	<2831fecf0911041021j1a32bdb1id4942a4254f647b@mail.gmail.com>	
	<4AF1F6BC.1050606@lanl.gov>	
	<2831fecf0911041353g420cc16fl4327ca06afcd16c7@mail.gmail.com>	
	<4AF1FEFD.8030007@lanl.gov>
	<2831fecf0911041434i322bd37fme5e6e36556a77fcd@mail.gmail.com>
	<4AF213CE.8060305@lanl.gov>
	<DA2B2D493A494064AE8A9D6A06FD5A38@chimp>
	<4AF21F0F.6050305@lanl.gov>
Message-ID: <6EBFC70630F245DF88CBB7CC3DD9B5E6@chimp>


> It doesn't seem like I need the forcing type 1 hack anymore.
Good.

> I reproduced the hang with some of the debugging statements back in.
Thanks.

> I hope that is all you need.
Yeah.  It took a little too long to figure that one out :)  I think we'll
call it good for now.

> Here is the output:
> Ram3
> Before starting clocks: Before memreset:
I guess we should put the timeout back in so that it doesn't hang.  I really
don't understand why that would be compiler dependent.

I'll send the patch to the list tomorrow.

Thanks,
Myles





From pjoanes at hotmail.com  Wed Nov  4 18:32:51 2009
From: pjoanes at hotmail.com (Peter Joanes)
Date: Wed, 4 Nov 2009 17:32:51 +0000
Subject: [coreboot] CPU Frequency setting
Message-ID: <SNT129-W412CB9A97EA7458D7A97DEA3B10@phx.gbl>





I would like to ask whether it might be possible to modify the
S2882 Coreboot config so that it includes a way to set the processor
frequency.
I have recently attempted to upgrade my S2882 based
system, but encountered stability problems which (after much
experimenting) seem simply to be a case of the board not being able to
handle the 2.8Ghz Opteron 254's I have put in it (which are shown as
supported on http://www.tyan.com/support_download_cpu2.aspx?socketid=9
).
If the machine completes booting, I can set the frequency to
2.6Ghz, and then all is fine, so I would like to exclude the 2.8Ghz
frequency earlier in the process (perhaps using Coreboot or maybe a slightly-modified bootloader).

Thanks,
-        Peter.
 		 	   		  
_________________________________________________________________
New Windows 7: Simplify what you do everyday. Find the right PC for you.
http://www.microsoft.com/uk/windows/buy/
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From svn at coreboot.org  Thu Nov  5 09:10:12 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 08:10:12 +0000
Subject: [coreboot] [v2] r4909 - trunk/src/devices
Message-ID: <mailman.3988.1355071651.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 08:10:12 +0000 (Thu, 05 Nov 2009)
New Revision: 4909

Modified:
   trunk/src/devices/pci_rom.c
Log:
When loading an option ROM use the class stored in the device to
decide whether the option ROM is a special VGA type.

An S3 card that I've got has the wrong class in the VGA BIOS.
(A Stealth 64 DRAM T PCI, from 1994 - BIOS V2.02)

Signed-off-by: Mark Marshall <mark.marshall at csr.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/src/devices/pci_rom.c
===================================================================
--- trunk/src/devices/pci_rom.c	2009-11-04 12:18:44 UTC (rev 4908)
+++ trunk/src/devices/pci_rom.c	2009-11-05 08:10:12 UTC (rev 4909)
@@ -116,7 +116,10 @@
 
 	rom_size = rom_header->size * 512;
 
-	if (PCI_CLASS_DISPLAY_VGA == rom_data->class_hi) {
+	// We check to see if the device thinks it is a VGA device not
+	// whether the ROM image is for a VGA device because some
+	// devices have a mismatch between the hardware and the ROM
+ 	if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {
 #if CONFIG_CONSOLE_VGA == 1 && CONFIG_CONSOLE_VGA_MULTI == 0
 		extern device_t vga_pri;	// the primary vga device, defined in device.c
 		if (dev != vga_pri) return NULL; // only one VGA supported




From svn at coreboot.org  Thu Nov  5 10:03:05 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 09:03:05 +0000
Subject: [coreboot] [v2] r4910 - trunk/util/x86emu
Message-ID: <mailman.3989.1355071651.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 09:03:04 +0000 (Thu, 05 Nov 2009)
New Revision: 4910

Modified:
   trunk/util/x86emu/x86_interrupts.c
Log:
Use more care when implementing the PCI BIOS functions.


The READ_CONF and WRITE_CONF functions would both do the wrong thing
if the passed in BDF was not found.  We should return and error to the
caller, but not stop running the option ROM.

Signed-off-by: Mark Marshall <mark.marshall at csr.com>

I slightly reworked the patch:

The 'CHECK' function seemed to be both wrong code and the wrong
number. 

In fact the CHECK function was given the function number of
the "Microsoft Real-Time Compression Interface". Since this is definitely wrong 
I removed the code.

Dropped some unneeded scopes, too, to make the code easier to read.

Acked-by: Stefan Reinauer <stepan at coresystems.de>




Modified: trunk/util/x86emu/x86_interrupts.c
===================================================================
--- trunk/util/x86emu/x86_interrupts.c	2009-11-05 08:10:12 UTC (rev 4909)
+++ trunk/util/x86emu/x86_interrupts.c	2009-11-05 09:03:04 UTC (rev 4910)
@@ -34,19 +34,22 @@
 #endif
 
 enum {
-	CHECK = 0xb001,
-	FINDDEV = 0xb102,
-	READCONFBYTE = 0xb108,
-	READCONFWORD = 0xb109,
-	READCONFDWORD = 0xb10a,
-	WRITECONFBYTE = 0xb10b,
-	WRITECONFWORD = 0xb10c,
-	WRITECONFDWORD = 0xb10d
+	PCIBIOS_CHECK = 0xb101,
+	PCIBIOS_FINDDEV = 0xb102,
+	PCIBIOS_READCONFBYTE = 0xb108,
+	PCIBIOS_READCONFWORD = 0xb109,
+	PCIBIOS_READCONFDWORD = 0xb10a,
+	PCIBIOS_WRITECONFBYTE = 0xb10b,
+	PCIBIOS_WRITECONFWORD = 0xb10c,
+	PCIBIOS_WRITECONFDWORD = 0xb10d
 };
 
 // errors go in AH. Just set these up so that word assigns
 // will work. KISS.
 enum {
+	PCIBIOS_SUCCESSFUL = 0x0000,
+	PCIBIOS_UNSUPPORTED = 0x8100,
+	PCIBIOS_BADVENDOR = 0x8300,
 	PCIBIOS_NODEV = 0x8600,
 	PCIBIOS_BADREG = 0x8700
 };
@@ -63,7 +66,7 @@
 
 int int1a_handler(struct eregs *regs)
 {
-	unsigned short func = (unsigned short) regs->eax;
+	unsigned short func = (unsigned short)regs->eax;
 	int retval = 0;
 	unsigned short devid, vendorid, devfn;
 	/* Use short to get rid of gabage in upper half of 32-bit register */
@@ -71,14 +74,13 @@
 	unsigned char bus;
 	struct device *dev;
 
-	switch(func) {
-	case  CHECK:
-		regs->edx = 0x4350;
-		regs->ecx = 0x2049;
+	switch (func) {
+	case PCIBIOS_CHECK:
+		regs->edx = 0x20494350;	/* ' ICP' */
+		regs->edi = 0x00000000;	/* protected mode entry */
 		retval = 0;
 		break;
-	case FINDDEV:
-	{
+	case PCIBIOS_FINDDEV:
 		devid = regs->ecx;
 		vendorid = regs->edx;
 		devindex = regs->esi;
@@ -98,7 +100,7 @@
 			// busnum is an unsigned char;
 			// devfn is an int, so we mask it off.
 			busdevfn = (dev->bus->secondary << 8)
-				| (dev->path.pci.devfn & 0xff);
+			    | (dev->path.pci.devfn & 0xff);
 			printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
 			regs->ebx = busdevfn;
 			retval = 0;
@@ -106,15 +108,13 @@
 			regs->eax = PCIBIOS_NODEV;
 			retval = -1;
 		}
-	}
-	break;
-	case READCONFDWORD:
-	case READCONFWORD:
-	case READCONFBYTE:
-	case WRITECONFDWORD:
-	case WRITECONFWORD:
-	case WRITECONFBYTE:
-	{
+		break;
+	case PCIBIOS_READCONFDWORD:
+	case PCIBIOS_READCONFWORD:
+	case PCIBIOS_READCONFBYTE:
+	case PCIBIOS_WRITECONFDWORD:
+	case PCIBIOS_WRITECONFWORD:
+	case PCIBIOS_WRITECONFBYTE:
 		unsigned long dword;
 		unsigned short word;
 		unsigned char byte;
@@ -124,49 +124,48 @@
 		bus = regs->ebx >> 8;
 		reg = regs->edi;
 		dev = dev_find_slot(bus, devfn);
-		if (! dev) {
+		if (!dev) {
 			printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
 			// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
 			regs->eax = PCIBIOS_BADREG;
 			retval = -1;
+			return retval;
 		}
-		switch(func) {
-		case READCONFBYTE:
+		switch (func) {
+		case PCIBIOS_READCONFBYTE:
 			byte = pci_read_config8(dev, reg);
 			regs->ecx = byte;
 			break;
-		case READCONFWORD:
+		case PCIBIOS_READCONFWORD:
 			word = pci_read_config16(dev, reg);
 			regs->ecx = word;
 			break;
-		case READCONFDWORD:
+		case PCIBIOS_READCONFDWORD:
 			dword = pci_read_config32(dev, reg);
 			regs->ecx = dword;
 			break;
-		case WRITECONFBYTE:
+		case PCIBIOS_WRITECONFBYTE:
 			byte = regs->ecx;
 			pci_write_config8(dev, reg, byte);
 			break;
-		case WRITECONFWORD:
+		case PCIBIOS_WRITECONFWORD:
 			word = regs->ecx;
 			pci_write_config16(dev, reg, word);
 			break;
-		case WRITECONFDWORD:
+		case PCIBIOS_WRITECONFDWORD:
 			dword = regs->ecx;
 			pci_write_config32(dev, reg, dword);
 			break;
 		}
 
-		if (retval)
-			retval = PCIBIOS_BADREG;
 		printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n",
 			     func, bus, devfn, reg, regs->ecx);
 		regs->eax = 0;
 		retval = 0;
-	}
-	break;
+		break;
 	default:
-		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n",  func);
+		printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
+		retval = -1;
 		break;
 	}
 




From svn at coreboot.org  Thu Nov  5 10:09:20 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 09:09:20 +0000
Subject: [coreboot] [v2] r4911 - trunk/util/x86emu
Message-ID: <mailman.3990.1355071651.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 09:09:20 +0000 (Thu, 05 Nov 2009)
New Revision: 4911

Modified:
   trunk/util/x86emu/x86_asm.S
Log:

Get the passed in Bus/Device/Function from the correct location on the
stack.

Signed-off-by: Mark Marshall <mark.marshall at csr.com>

Clarified the comment and
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/x86emu/x86_asm.S
===================================================================
--- trunk/util/x86emu/x86_asm.S	2009-11-05 09:03:04 UTC (rev 4910)
+++ trunk/util/x86emu/x86_asm.S	2009-11-05 09:09:20 UTC (rev 4911)
@@ -68,8 +68,10 @@
 
 	/* Get devfn into %ecx */
 	movl    %esp, %ebp
-	// FIXME: Should this function be called with regparm=0?
-	movl    8(%ebp), %ecx
+	/* This function is called with regparm=0 and we have
+	 * to skip the 32 byte from pushal:
+	 */
+	movl    36(%ebp), %ecx
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)




From stepan at coresystems.de  Thu Nov  5 10:15:25 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 05 Nov 2009 10:15:25 +0100
Subject: [coreboot] [PATCH] The filo crashes if the filo
	and	corebootoverlap.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17032A05E7@sbjgexmb1.amd.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl><1257005604.23416.18.camel@tetris><DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032A05E7@sbjgexmb1.amd.com>
Message-ID: <4AF297AD.40707@coresystems.de>

Bao, Zheng wrote:
> Ping, before we forget.
> Can anyone ack or nack this?
>
> Zheng
>
>
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
> Sent: Tuesday, November 03, 2009 11:23 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] The filo crashes if the filo and
> corebootoverlap.
>
> If the coreboot and filo overlap, it will "slice off" a piece at the
> beginning or end. In the beginning case, a new segment is inserted
> before the current one.  The ptr will move forward and doesn't seem to
> have any chance to process the "new" segment.
>
>                 ptr ---------+     move --->
>                              |
>                              V
>         +--------+       +--------+
>         |        |       |        |
>         |  new   | <---> |current | <---> .....
>         |        |       |        |
>         +--------+       +--------+
>
> Now we change the ptr to the previous one and restart the loop. The
> new and current segment will both be processed.
>
>       +----------------ptr      move --->
>       |
>       V
>  +--------+        +--------+       +--------+
>  |        |        |        |       |        |
>  |  prev  | <--->  |  new   | <---> |current | <---> .....
>  |        |        |        |       |        |
>  +--------+        +--------+       +--------+
>
> It is tested on my Family 10 board.
>
>   

Very nice explanation... :-)

Acked-by: Stefan Reinauer <stepan at coresystems.de>





> Zheng
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
>
> Index: src/boot/selfboot.c
> ===================================================================
> --- src/boot/selfboot.c	(revision 4892)
> +++ src/boot/selfboot.c	(working copy)
> @@ -211,19 +211,21 @@
>  	return !((end <= lb_start) || (start >= lb_end));
>  }
>  
> -static void relocate_segment(unsigned long buffer, struct segment *seg)
> +static int relocate_segment(unsigned long buffer, struct segment *seg)
>  {
>  	/* Modify all segments that want to load onto coreboot
>  	 * to load onto the bounce buffer instead.
>  	 */
> -	unsigned long start, middle, end;
> +	/* ret:  1 : A new segment is inserted before the seg.
> +	 *       0 : A new segment is inserted after the seg, or no new
> one. */
> +	unsigned long start, middle, end, ret = 0;
>  
>  	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
>  		lb_start, lb_end);
>  
>  	/* I don't conflict with coreboot so get out of here */
>  	if (!overlaps_coreboot(seg))
> -		return;
> +		return 0;
>  
>  	start = seg->s_dstaddr;
>  	middle = start + seg->s_filesz;
> @@ -270,6 +272,8 @@
>  				new->s_dstaddr, 
>  				new->s_dstaddr + new->s_filesz,
>  				new->s_dstaddr + new->s_memsz);
> +
> +			ret = 1;
>  		}
>  			
>  		/* Slice off a piece at the end 
> @@ -319,6 +323,8 @@
>  		seg->s_dstaddr, 
>  		seg->s_dstaddr + seg->s_filesz, 
>  		seg->s_dstaddr + seg->s_memsz);
> +
> +	return ret;
>  }
>  
>  
> @@ -446,7 +452,10 @@
>  		
>  		/* Modify the segment to load onto the bounce_buffer if
> necessary.
>  		 */
> -		relocate_segment(bounce_buffer, ptr);
> +		if (relocate_segment(bounce_buffer, ptr)) {
> +			ptr = (ptr->prev)->prev;
> +			continue;
> +		}
>  
>  		printk_debug("Post relocation: addr: 0x%016lx memsz:
> 0x%016lx filesz: 0x%016lx\n",
>  			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
>
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
> Sent: Monday, November 02, 2009 11:25 AM
> To: Patrick Georgi
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] The filo crashes if the filo and coreboot
> overlap.
>
> In relocate_segment().
> If the coreboot and filo overlap, it will "slice off" a piece at the
> beginning or end. A new segment is allocated. If it is inserted before
> the "seg" that is being processed, is there any chance that the "new"
> segment will be processed? I am confused about it. On my fam 10 board,
> it seems that the "new" segment was not processed and an error happens
> when the code jumps to filo which is actually middle of nowhere.
>
>
> Zheng
>
> -----Original Message-----
> From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
> [mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
> Patrick Georgi
> Sent: Sunday, November 01, 2009 12:13 AM
> To: Zheng Bao
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] The filo crashes if the filo and coreboot
> overlap.
>
> Am Samstag, den 31.10.2009, 15:43 +0000 schrieb Zheng Bao:
>   
>> The filo crashes if the filo and coreboot overlap.
>> Since the CBFS is the must-have feature, my family 10
>>  board crashes when it jumps to filo. I am trying to
>>  find out why. I need help.
>> Based on current code, the AMD Family 10 will cause the filo
>> and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c
>> will return 1. But I am not sure if it will make the system
>> crashes.
>>     
> What revision is that? There was an issue like that but I fixed it
> several weeks ago.
>
>   
>> If anybody explains briefly what happens if they
>> overlap.
>>     
> When coreboot and payload overlap, coreboot uses a bounce buffer. The
> bounce buffer is twice the size of coreboot. The first half is for the
> part of the payload that overlaps coreboot, the other half is for
> coreboot itself.
>
> The SELF loader loads data that would overlap coreboot to the bounce
> buffer, and jumps into jmp_to_elf_entry when it's done with loading.
> The jmp_to_elf_entry function copies coreboot to the upper half of the
> bounce buffer, and jumps in there, so the code is out of the way.
>
> Then it copies the lower half to the coreboot area and jumps to the
> entry point.
>
> There are some complications to that because of the decompression
> routine, so the code is not as nice as it should be. But I specifically
> tested your scenario (payload from 1mb to 2.3mb or so, coreboot starting
> at 2mb)
>
>   
>> The coreboot information:
>> CONFIG_RAMBASE=0x00200000
>>     
> Try changing that to 0x100000.
>
>
> Patrick
>
>
>   


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From stepan at coresystems.de  Thu Nov  5 10:18:09 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 05 Nov 2009 10:18:09 +0100
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <4AF1C281.3030502@csr.com>
References: <hc6lsa$hqg$1@ger.gmane.org> <4AF1C281.3030502@csr.com>
Message-ID: <4AF29851.9000902@coresystems.de>

Mark Marshall wrote:
> Ping.
>
> Mark Marshall wrote:
>> Below are three small patches, they all seemed useful while I have
>> been working with VGA option ROMs.
>>
>> Thanks for the great work.
>>
>> MM
>>
>
>
Awesome!

r4909 - r4911

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From info at coresystems.de  Thu Nov  5 10:27:09 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 05 Nov 2009 09:27:09 +0000
Subject: [coreboot] build service results for r4910
Message-ID: <E1N5ycX-000330-CX@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4910 to
the coreboot repository. This caused the following 
changes:

Change Log:
Use more care when implementing the PCI BIOS functions.


The READ_CONF and WRITE_CONF functions would both do the wrong thing
if the passed in BDF was not found.  We should return and error to the
caller, but not stop running the option ROM.

Signed-off-by: Mark Marshall <mark.marshall at csr.com>

I slightly reworked the patch:

The 'CHECK' function seemed to be both wrong code and the wrong
number.

In fact the CHECK function was given the function number of
the "Microsoft Real-Time Compression Interface". Since this is definitely wrong
I removed the code.

Dropped some unneeded scopes, too, to make the code easier to read.

Acked-by: Stefan Reinauer <stepan at coresystems.de>




Build Log:
Compilation of emulation:qemu-x86 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4910&device=qemu-x86&vendor=emulation&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mch at virtutech.com  Thu Nov  5 10:30:49 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 05 Nov 2009 10:30:49 +0100
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <20091104144011.GR27911@redhat.com>
References: <4AF04CD4.1030007@virtutech.com>	<20091104033012.GA32618@morn.localdomain>
	<20091104144011.GR27911@redhat.com>
Message-ID: <4AF29B49.7090001@virtutech.com>

On 11/04/2009 03:40 PM, Gleb Natapov wrote:
> On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
>    
>> On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
>>      
>>> I'm attaching patches for seabios to make it work on the Virtutech
>>> Simics x86-440bx model. Please let me know if there is some other list
>>> that is preferred for seabios patches.
>>>
>>> Patches 1-6 and 9 are not really related to the Virtutech model at all,
>>> so those would be prime candidates to be included in the mainline
>>> version.
>>>        
>>      
> l>  Thanks Magnus.
>    
>> Gleb I'm not sure if you're on the coreboot mailing list - can you
>> take a look at these patches as well?  A URL is at:
>>
>> http://permalink.gmane.org/gmane.linux.bios/55487
>>
>>      
> Can I get them in a mbox format somewhere? Want to tested them to be
> sure. From review:
> 1:
>   OK
>
> 2:
>   What is the reason for this? x86info --mptable on my 4 core AMD shows
> MP Table:
> #       APIC ID Version State           Family  Model   Step    Flags
> #        0       0x10    BSP, usable     16      4       1     0x178bfbff
> #        1       0x10    AP, usable      16      4       1     0x178bfbff
> #        2       0x10    AP, usable      16      4       1     0x178bfbff
> #        3       0x10    AP, usable      16      4       1     0x178bfbff
>    
I can think of two reasons for only listing one CPU per package. The 
first would be performance, in that the OS needs to be aware of 
multi-threading in order not to slow down high priority tasks with stuff 
that is usually free when running on multiple processors (like 
spinlocks). The second reason would be that logical CPUs in the same 
package share some MSRs, and an OS that isn't aware of that may cease to 
work in such an environment.

Related link:

http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/

> 3:
>   And why is this? My mptable spec (from 1997) says that apic id is 8 bit
>   and x86info --mptable on my Intel with 16 logical cpus shows:
> MP Table:
> #       APIC ID Version State           Family  Model   Step    Flags
> #        0       0x15    BSP, usable     6       10      5       0x0381
> #       16       0x15    AP, usable      6       10      5       0x0381
> Interesting that on Intel only one entry per physical package.
>    
I don't really remember the reason for that limit. I simply added stuff 
from our BIOS to SeaBIOS until they generated identical MPS tables. Feel 
free to ignore this patch.
> 4:
>   I am not sure why we want to make it faster (waiting anyway) but OK.
>    
Virtutech Simics is often run with scripted input, and time is then 
compressed whenever possible to boost overall performance.

> 5:
>   OK. Wanted to add this by myself for a long time. We configure LINT0 inside KVM
>   now, but this is BIOS job.
>
> 6:
>   OK.
>
> 7:
>   Don't like VIRTUTECH_IRQ0_OVERRIDE checking inside qemu_cfg_irq0_override().
>   What about creating irq0_override() in generic code that will call
>   qemu_cfg_irq0_override() if needed. Setting VIRTUTECH_IRQ0_OVERRIDE to
>   1 by default is not a welcomed too :)
>    
I'll add a QEMU compatible paravirt device for Simics, and then we can 
live without this patch.
> 8:
>   Do not set VIRTUTECH_PC_SHADOW to 1 by default please. Otherwise the
>   code is not used by qemu so OK.
>
> 9:
>   OK
>
> 10:
>   USE_CMOS_BIOS_SMP_COUNT default to 1
>    
I'm attaching the (modified) patches.

M.


From mch at virtutech.com  Tue Nov  3 12:49:27 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:49:27 +0100
Subject: [PATCH 1/8] Fit cpuflag in mptable (| has higher priority than ?:)
Message-ID: <mailman.3991.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 3945d2e..805fe1b 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -60,7 +60,7 @@ mptable_init(void)
         cpu->apicver = 0x11;
         /* cpu flags: enabled, bootstrap cpu */
         if (i < CountCPUs)
-            cpu->cpuflag = 1 | (i == 0) ? 2 : 0;
+            cpu->cpuflag = 1 | ((i == 0) ? 2 : 0);
         else
             cpu->cpuflag = 0;
         if (cpuid_signature) {
-- 
1.6.2.5


--------------010303080000070006010407
Content-Type: text/x-patch;
 name="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.patch"
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 filename*0="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.pat";
 filename*1="ch"


From mch at virtutech.com  Tue Nov  3 12:50:09 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:50:09 +0100
Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
Message-ID: <mailman.3992.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |   26 ++++++++++++++++++++++----
 1 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 805fe1b..525188d 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -44,16 +44,32 @@ mptable_init(void)
     config->spec = 4;
     memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
     memcpy(config->productid, "0.1         ", sizeof(config->productid));
-    config->entrycount = MaxCountCPUs + 2 + 16;
     config->lapic = BUILD_APIC_ADDR;
 
     // CPU definitions.
     u32 cpuid_signature, ebx, ecx, cpuid_features;
     cpuid(1, &cpuid_signature, &ebx, &ecx, &cpuid_features);
     struct mpt_cpu *cpus = (void*)&config[1];
-    int i;
-    for (i = 0; i < MaxCountCPUs; i++) {
+    int i, actual_cpu_count;
+    for (i = 0, actual_cpu_count = 0; i < MaxCountCPUs; i++) {
         struct mpt_cpu *cpu = &cpus[i];
+        int log_cpus = (ebx >> 16) & 0xff;
+
+        /* Only populate the MPS tables with the first logical CPU in each
+           package */
+        if ((cpuid_features & (1 << 28)) &&
+            log_cpus > 1 &&
+            ((log_cpus <= 2 && (i & 1) != 0) ||
+             (log_cpus <= 4 && (i & 3) != 0) ||
+             (log_cpus <= 8 && (i & 7) != 0) ||
+             (log_cpus <= 16 && (i & 15) != 0) ||
+             (log_cpus <= 32 && (i & 31) != 0) ||
+             (log_cpus <= 64 && (i & 63) != 0) ||
+             (log_cpus <= 128 && (i & 127) != 0)))
+            continue;
+
+        actual_cpu_count++;
+
         memset(cpu, 0, sizeof(*cpu));
         cpu->type = MPT_TYPE_CPU;
         cpu->apicid = i;
@@ -72,8 +88,10 @@ mptable_init(void)
         }
     }
 
+    config->entrycount = actual_cpu_count + 2 + 16;
+
     /* isa bus */
-    struct mpt_bus *bus = (void*)&cpus[MaxCountCPUs];
+    struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
     memset(bus, 0, sizeof(*bus));
     bus->type = MPT_TYPE_BUS;
     memcpy(bus->bustype, "ISA   ", sizeof(bus->bustype));
-- 
1.6.2.5


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 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 12:51:17 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:17 +0100
Subject: [PATCH 3/8] Remove device access from loop to make it faster when running in emulation.
Message-ID: <mailman.3993.1355071651.16123.coreboot@coreboot.org>

---
 src/smp.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index a912857..71b0da8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -97,11 +97,13 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT)
+    if (CONFIG_COREBOOT) {
         msleep(10);
-    else
-        while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs))
-            ;
+    } else {
+        u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
+        while (cmos_smp_count + 1 != readl(&CountCPUs))
+             ;
+    }
 
     // Restore memory.
     *(u64*)BUILD_AP_BOOT_ADDR = old;
-- 
1.6.2.5


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Content-Disposition: attachment;
 filename*0="0004-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.pa";
 filename*1="tch"


From mch at virtutech.com  Tue Nov  3 12:51:45 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:45 +0100
Subject: [PATCH 4/8] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
Message-ID: <mailman.3994.1355071651.16123.coreboot@coreboot.org>

---
 src/smp.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index 71b0da8..b0852f8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -13,6 +13,8 @@
 
 #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
 #define APIC_SVR     ((u8*)BUILD_APIC_ADDR + 0x0F0)
+#define APIC_LINT0   ((u8*)BUILD_APIC_ADDR + 0x350)
+#define APIC_LINT1   ((u8*)BUILD_APIC_ADDR + 0x360)
 
 #define APIC_ENABLED 0x0100
 
@@ -91,6 +93,12 @@ smp_probe(void)
     u32 val = readl(APIC_SVR);
     writel(APIC_SVR, val | APIC_ENABLED);
 
+    /* Set LINT0 as Ext_INT, level triggered */
+    writel(APIC_LINT0, 0x8700);
+
+    /* Set LINT1 as NMI, level triggered */
+    writel(APIC_LINT1, 0x8400);
+
     // broadcast SIPI
     writel(APIC_ICR_LOW, 0x000C4500);
     u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
-- 
1.6.2.5


--------------010303080000070006010407
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 filename="0005-Add-MPS-entries-for-LINT-interrupts.patch"


From mch at virtutech.com  Thu Nov  5 10:20:34 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:20:34 +0100
Subject: [PATCH 5/8] Add MPS entries for LINT interrupts.
Message-ID: <mailman.3995.1355071651.16123.coreboot@coreboot.org>

---
 src/mptable.c |   23 +++++++++++++++++++++--
 src/mptable.h |    1 +
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 525188d..51b50db 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -22,7 +22,7 @@ mptable_init(void)
                   + sizeof(struct mpt_cpu) * MaxCountCPUs
                   + sizeof(struct mpt_bus)
                   + sizeof(struct mpt_ioapic)
-                  + sizeof(struct mpt_intsrc) * 16);
+                  + sizeof(struct mpt_intsrc) * 18);
     struct mptable_config_s *config = malloc_fseg(length);
     struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating));
     if (!config || !floating) {
@@ -88,7 +88,7 @@ mptable_init(void)
         }
     }
 
-    config->entrycount = actual_cpu_count + 2 + 16;
+    config->entrycount = actual_cpu_count + 2 + 16 + 2;
 
     /* isa bus */
     struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
@@ -125,6 +125,25 @@ mptable_init(void)
         intsrc++;
     }
 
+    /* Local interrupt assignment */
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 3; /* ExtINT */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 0; /* LINTIN0 */
+    intsrc++;
+
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 1; /* NMI */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 1; /* LINTIN1 */
+    intsrc++;
+
     // Set checksum.
     config->length = (void*)intsrc - (void*)config;
     config->checksum -= checksum(config, config->length);
diff --git a/src/mptable.h b/src/mptable.h
index 4c4d52f..c4e3c51 100644
--- a/src/mptable.h
+++ b/src/mptable.h
@@ -38,6 +38,7 @@ struct mptable_config_s {
 #define MPT_TYPE_BUS 1
 #define MPT_TYPE_IOAPIC 2
 #define MPT_TYPE_INTSRC 3
+#define MPT_TYPE_LOCAL_INT 4
 
 struct mpt_cpu {
     u8 type;
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 10:23:26 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:23:26 +0100
Subject: [PATCH 6/8] Properly mask value for MTRR mask.
Message-ID: <mailman.3996.1355071651.16123.coreboot@coreboot.org>

---
 src/mtrr.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mtrr.c b/src/mtrr.c
index a9cd5f7..6bd0dba 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -29,7 +29,7 @@ void mtrr_setup(void)
     if (CONFIG_COREBOOT)
         return;
 
-    u32 eax, ebx, ecx, cpuid_features;
+    u32 eax, ebx, ecx, edx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
     if (!(cpuid_features & CPUID_MTRR))
         return;
@@ -73,6 +73,16 @@ void mtrr_setup(void)
     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
     wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
-    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
+
+    int phys_bits = 36;
+    cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+    if (eax >= 0x80000008) {
+            /* Get physical bits from leaf 0x80000008 (if available) */
+            cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+            phys_bits = eax & 0xff;
+    }
+    u64 phys_mask = ((1ull << phys_bits) - 1);
+    wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800);
+
     wrmsr_smp(MSR_MTRRdefType, 0xc06);
 }
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 10:25:05 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:25:05 +0100
Subject: [PATCH 7/8] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
Message-ID: <mailman.3997.1355071652.16123.coreboot@coreboot.org>

---
 src/config.h |    3 +++
 src/shadow.c |   55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 0 deletions(-)

diff --git a/src/config.h b/src/config.h
index 3033133..f2c08ff 100644
--- a/src/config.h
+++ b/src/config.h
@@ -189,4 +189,7 @@
 #define DEBUG_HDL_pmm 1
 #define DEBUG_thread 1
 
+/* Options for running on the Virtutech Simics x86-440bx machine model */
+#define VIRTUTECH_PC_SHADOW 0
+
 #endif // config.h
diff --git a/src/shadow.c b/src/shadow.c
index f0f97c5..4b7f15c 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -9,6 +9,7 @@
 #include "pci.h" // pci_config_writeb
 #include "config.h" // CONFIG_*
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "ioport.h" // outb
 
 // Test if 'addr' is in the range from 'start'..'start+size'
 #define IN_RANGE(addr, start, size) ({   \
@@ -21,6 +22,40 @@
 // On the emulators, the bios at 0xf0000 is also at 0xffff0000
 #define BIOS_SRC_ADDR 0xffff0000
 
+#if VIRTUTECH_PC_SHADOW
+
+#define Read_Only 1
+#define Write_Only 2
+#define Read_Write 3
+
+static void modify_shadow(unsigned long start, unsigned long len, int mode)
+{
+    int start_loc = ((int)(start >> 10) - 640) >> 1;
+    int len_remaining = len >> 11;
+    int i;
+    for (i = 0; i < len_remaining; i++) {
+        outb(start_loc + i, 0xfff4);
+        if (mode == Read_Only) {
+            outb(1, 0xfff5);
+        } else if (mode == Read_Write) {
+            outb(3, 0xfff5);
+        } else if (mode == Write_Only) {
+            outb(2, 0xfff5);
+        } else {
+            outb(0, 0xfff5);
+        }
+    }
+}
+
+static void
+__copy_bios(void)
+{
+    // Copy bios.
+    memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
+}
+
+#else
+
 // Enable shadowing and copy bios.
 static void
 __make_bios_writable(u16 bdf)
@@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf)
     memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
 }
 
+#endif // VIRTUTECH_PC_SHADOW
+
 // Make the 0xc0000-0x100000 area read/writable.
 void
 make_bios_writable()
@@ -68,6 +105,19 @@ make_bios_writable()
 
     dprintf(3, "enabling shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    /* Read (and execute) from PCI, write to RAM */
+    modify_shadow(0xf0000, 0x10000, Write_Only);
+
+    /* Run the copy from the high address to avoid simulator flushes after each
+       write (the flushes ruin performance) */
+    u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
+    void (*func)(void) = (void*)pos;
+    func();
+
+    /* Keep BIOS read/write */
+    modify_shadow(0xf0000, 0x10000, Read_Write);
+#else
     // Locate chip controlling ram shadowing.
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
@@ -88,6 +138,7 @@ make_bios_writable()
     }
     // Ram already present - just enable writes
     __make_bios_writable(bdf);
+#endif
 }
 
 // Make the BIOS code segment area (0xf0000) read-only.
@@ -99,6 +150,9 @@ make_bios_readonly()
 
     dprintf(3, "locking shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    modify_shadow(0xf0000, 0x10000, Read_Only);
+#else
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
         dprintf(1, "Unable to lock ram - bridge not found\n");
@@ -122,4 +176,5 @@ make_bios_readonly()
 
     // Write protect 0xf0000-0x100000
     pci_config_writeb(bdf, 0x59, 0x10);
+#endif
 }
-- 
1.6.2.5


--------------010303080000070006010407
Content-Type: text/x-patch;
 name="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc";
 filename*1="h"


From mch at virtutech.com  Thu Nov  5 10:26:40 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:26:40 +0100
Subject: [PATCH 8/8] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
Message-ID: <mailman.3998.1355071652.16123.coreboot@coreboot.org>

---
 src/config.h |    1 +
 src/smp.c    |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/config.h b/src/config.h
index f2c08ff..e9d63e7 100644
--- a/src/config.h
+++ b/src/config.h
@@ -191,5 +191,6 @@
 
 /* Options for running on the Virtutech Simics x86-440bx machine model */
 #define VIRTUTECH_PC_SHADOW 0
+#define USE_CMOS_BIOS_SMP_COUNT 1
 
 #endif // config.h
diff --git a/src/smp.c b/src/smp.c
index b0852f8..caec5f1 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -105,7 +105,7 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT) {
+    if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) {
         msleep(10);
     } else {
         u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
-- 
1.6.2.5


--------------010303080000070006010407--



From r.marek at assembler.cz  Thu Nov  5 10:32:48 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 05 Nov 2009 10:32:48 +0100
Subject: [coreboot] [RFC] network console for coreboot and ethernet support
	for SerialICE
Message-ID: <4AF29BC0.5070107@assembler.cz>

Hello all,

You may ask what is it all about? Well, for SerialICE we have no RAM, therefore 
sending through network adapter is not quite easy - you can't even place a 
descriptors for DMA in RAM ;) For coreboot we have CAR but same problem, DMA 
wants a working memory. Remember those old days with Novell Netware? Packwars? 
Netwars? This time is connected with a NE2000 cards. To reduce a cost it is 
nearly an reference design of the NS8390 chip. No external DMA, insane registers 
;) The Novell needed very cheap Ethernet adapters - because their business was 
to license of Nowell Netware per node. They simple needed to make the ethernet 
adapters affordable. As the consequence of this NE2000 chips survived even to 
PCI era. The Realtek made some chip called RTL8029AS. This chip is still quite 
wide spread. I bet you have some 10Mbit/s ethernet cards around (twisted pair) 
most likely with this chip...

End of story? No! The sweet features of this chip:

* insane registers
* no DMA, only PIO
* 8bit/16 IO bit access
* 10Mbit/Full duplex ;)
* Nice hardware bugs ;) ?
* 16KB SRAM for TX/RX buffers

Now you know ;) The idea is to create the packets in the card SRAM, construct 
some UDP packets with destination eth address as broadcasts. This will ensure we 
need no ARP. Packets can be also received, parsing of packets is like reading a 
very long FIFO byte to byte or word by word. Therefore I think one could have 
this card plugged to some PCI slot in the system and use it for quite fast IO.

The K8 HT chain most likely works to SB so the PCI adpaters are accessible early 
too. The only way which needs to be set is the IO resource and enable decoding 
of this resource in PCI_CMD. I think problems will only arise if the bus for PCI 
slot is not the primary. For the coreboot, I think we can use pci_find_device to 
"dynamically" read the current IO port from PCI BAR.

What do you think? I and agaran (aka Maciej) started to hack this together. We 
used GPXE as code base for this, now we are able to send/receive data in linux 
userspace application.

The usage idea is to have 8029 card as the "console" similar way as linux 
netconsole for coreboot. The SerialICE could be changed to use the network 
instead of slow serial.

Any clue what might cause that this does not work?

Rudolf






From info at coresystems.de  Thu Nov  5 10:55:01 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 05 Nov 2009 09:55:01 +0000
Subject: [coreboot] build service results for r4911
Message-ID: <E1N5z3V-0007aV-L4@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4911 to
the coreboot repository. This caused the following 
changes:

Change Log:

Get the passed in Bus/Device/Function from the correct location on the
stack.

Signed-off-by: Mark Marshall <mark.marshall at csr.com>

Clarified the comment and
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4911&device=qemu-x86&vendor=emulation&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From gleb at redhat.com  Thu Nov  5 10:54:47 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Thu, 5 Nov 2009 11:54:47 +0200
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <4AF29B49.7090001@virtutech.com>
References: <4AF04CD4.1030007@virtutech.com>
	<20091104033012.GA32618@morn.localdomain>
	<20091104144011.GR27911@redhat.com>
	<4AF29B49.7090001@virtutech.com>
Message-ID: <20091105095447.GV27911@redhat.com>

On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
> On 11/04/2009 03:40 PM, Gleb Natapov wrote:
> >On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
> >>On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
> >>>I'm attaching patches for seabios to make it work on the Virtutech
> >>>Simics x86-440bx model. Please let me know if there is some other list
> >>>that is preferred for seabios patches.
> >>>
> >>>Patches 1-6 and 9 are not really related to the Virtutech model at all,
> >>>so those would be prime candidates to be included in the mainline
> >>>version.
> >l>  Thanks Magnus.
> >>Gleb I'm not sure if you're on the coreboot mailing list - can you
> >>take a look at these patches as well?  A URL is at:
> >>
> >>http://permalink.gmane.org/gmane.linux.bios/55487
> >>
> >Can I get them in a mbox format somewhere? Want to tested them to be
> >sure. From review:
> >1:
> >  OK
> >
> >2:
> >  What is the reason for this? x86info --mptable on my 4 core AMD shows
> >MP Table:
> >#       APIC ID Version State           Family  Model   Step    Flags
> >#        0       0x10    BSP, usable     16      4       1     0x178bfbff
> >#        1       0x10    AP, usable      16      4       1     0x178bfbff
> >#        2       0x10    AP, usable      16      4       1     0x178bfbff
> >#        3       0x10    AP, usable      16      4       1     0x178bfbff
> I can think of two reasons for only listing one CPU per package. The
> first would be performance, in that the OS needs to be aware of
> multi-threading in order not to slow down high priority tasks with
> stuff that is usually free when running on multiple processors (like
> spinlocks). The second reason would be that logical CPUs in the same
> package share some MSRs, and an OS that isn't aware of that may
> cease to work in such an environment.
> 
> Related link:
> 
> http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
> 
This list talks about HT. Why not add entry for each core though? I am
not aware of any MSRs shared between cores
 
> >From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
> From: Magnus Christensson <mch at virtutech.com>
> Date: Tue, 3 Nov 2009 12:50:09 +0100
> Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
> 
> ---
>  src/mptable.c |   26 ++++++++++++++++++++++----
>  1 files changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mptable.c b/src/mptable.c
> index 805fe1b..525188d 100644
> --- a/src/mptable.c
> +++ b/src/mptable.c
> @@ -44,16 +44,32 @@ mptable_init(void)
>      config->spec = 4;
>      memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
>      memcpy(config->productid, "0.1         ", sizeof(config->productid));
> -    config->entrycount = MaxCountCPUs + 2 + 16;
>      config->lapic = BUILD_APIC_ADDR;
>  
>      // CPU definitions.
>      u32 cpuid_signature, ebx, ecx, cpuid_features;
>      cpuid(1, &cpuid_signature, &ebx, &ecx, &cpuid_features);
>      struct mpt_cpu *cpus = (void*)&config[1];
> -    int i;
> -    for (i = 0; i < MaxCountCPUs; i++) {
> +    int i, actual_cpu_count;
> +    for (i = 0, actual_cpu_count = 0; i < MaxCountCPUs; i++) {
>          struct mpt_cpu *cpu = &cpus[i];
> +        int log_cpus = (ebx >> 16) & 0xff;
> +
> +        /* Only populate the MPS tables with the first logical CPU in each
> +           package */
> +        if ((cpuid_features & (1 << 28)) &&
> +            log_cpus > 1 &&
> +            ((log_cpus <= 2 && (i & 1) != 0) ||
> +             (log_cpus <= 4 && (i & 3) != 0) ||
> +             (log_cpus <= 8 && (i & 7) != 0) ||
> +             (log_cpus <= 16 && (i & 15) != 0) ||
> +             (log_cpus <= 32 && (i & 31) != 0) ||
> +             (log_cpus <= 64 && (i & 63) != 0) ||
> +             (log_cpus <= 128 && (i & 127) != 0)))
> +            continue;
> +
Isn't this the same as (i & (log_cpus - 1) != 0)?

--
			Gleb.



From svn at coreboot.org  Thu Nov  5 11:02:59 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 10:02:59 +0000
Subject: [coreboot] [v2] r4912 - trunk/src/boot
Message-ID: <mailman.3999.1355071652.16123.coreboot@coreboot.org>

Author: zbao
Date: 2009-11-05 10:02:59 +0000 (Thu, 05 Nov 2009)
New Revision: 4912

Modified:
   trunk/src/boot/selfboot.c
Log:
If the coreboot and filo overlap, it will "slice off" a piece at the
"beginning" or "end". In the beginning case, a new segment is inserted
before the current one.  But the ptr will move forward and doesn't
seem to have any other chance to process the "new" segment.

                ptr ---------+     move --->
                             |
                             V
        +--------+       +--------+
        |        |       |        |
        |  new   | <---> |current | <---> .....
        |        |       |        |
        +--------+       +--------+

Now we change the ptr to the previous one and restart the loop. The
new and current segment will both be processed. Even if the current
segment is done twice, no new segment will come up and ptr will move
forward as we expect.

      +----------------ptr      move --->
      |
      V
 +--------+        +--------+       +--------+
 |        |        |        |       |        |
 |  prev  | <--->  |  new   | <---> |current | <---> .....
 |        |        |        |       |        |
 +--------+        +--------+       +--------+

It is tested and fixes the crashing on my AMD Family 10 board.

Some trailing whitespaces were deleted.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/src/boot/selfboot.c
===================================================================
--- trunk/src/boot/selfboot.c	2009-11-05 09:09:20 UTC (rev 4911)
+++ trunk/src/boot/selfboot.c	2009-11-05 10:02:59 UTC (rev 4912)
@@ -60,7 +60,7 @@
 
 struct verify_callback {
 	struct verify_callback *next;
-	int (*callback)(struct verify_callback *vcb, 
+	int (*callback)(struct verify_callback *vcb,
 		Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head);
 	unsigned long desc_offset;
 	unsigned long desc_addr;
@@ -88,7 +88,7 @@
 	return (void *) -1;
 }
 
-/* The problem:  
+/* The problem:
  * Static executables all want to share the same addresses
  * in memory because only a few addresses are reliably present on
  * a machine, and implementing general relocation is hard.
@@ -97,16 +97,16 @@
  * - Allocate a buffer the size of the coreboot image plus additional
  *   required space.
  * - Anything that would overwrite coreboot copy into the lower part of
- *   the buffer. 
+ *   the buffer.
  * - After loading an ELF image copy coreboot to the top of the buffer.
  * - Then jump to the loaded image.
- * 
+ *
  * Benefits:
  * - Nearly arbitrary standalone executables can be loaded.
  * - Coreboot is preserved, so it can be returned to.
  * - The implementation is still relatively simple,
  *   and much simpler than the general case implemented in kexec.
- * 
+ *
  */
 
 static unsigned long bounce_size, bounce_buffer;
@@ -138,7 +138,7 @@
 			msize = unpack_lb64(mem->map[i].size);
 		mend = mstart + msize;
 		tbuffer = mend - lb_size;
-		if (tbuffer < buffer) 
+		if (tbuffer < buffer)
 			continue;
 		buffer = tbuffer;
 	}
@@ -190,10 +190,10 @@
 			mstart = unpack_lb64(mem->map[i].start);
 			mend = mstart + unpack_lb64(mem->map[i].size);
 			printk_err("  [0x%016lx, 0x%016lx) %s\n",
-				(unsigned long)mstart, 
-				(unsigned long)mend, 
+				(unsigned long)mstart,
+				(unsigned long)mend,
 				(mtype == LB_MEM_RAM)?"RAM":"Reserved");
-			
+
 		}
 		return 0;
 	}
@@ -211,25 +211,27 @@
 	return !((end <= lb_start) || (start >= lb_end));
 }
 
-static void relocate_segment(unsigned long buffer, struct segment *seg)
+static int relocate_segment(unsigned long buffer, struct segment *seg)
 {
 	/* Modify all segments that want to load onto coreboot
 	 * to load onto the bounce buffer instead.
 	 */
-	unsigned long start, middle, end;
+	/* ret:  1 : A new segment is inserted before the seg.
+	 *       0 : A new segment is inserted after the seg, or no new one. */
+	unsigned long start, middle, end, ret = 0;
 
-	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
+	printk_spew("lb: [0x%016lx, 0x%016lx)\n",
 		lb_start, lb_end);
 
 	/* I don't conflict with coreboot so get out of here */
 	if (!overlaps_coreboot(seg))
-		return;
+		return 0;
 
 	start = seg->s_dstaddr;
 	middle = start + seg->s_filesz;
 	end = start + seg->s_memsz;
 
-	printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
+	printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 		start, middle, end);
 
 	if (seg->compression == CBFS_COMPRESS_NONE) {
@@ -265,15 +267,17 @@
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
-			
-			printk_spew("   early: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-				new->s_dstaddr, 
+
+			printk_spew("   early: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+				new->s_dstaddr,
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
+
+			ret = 1;
 		}
-			
-		/* Slice off a piece at the end 
-		 * that doesn't conflict with coreboot 
+
+		/* Slice off a piece at the end
+		 * that doesn't conflict with coreboot
 		 */
 		if (end > lb_end) {
 			unsigned long len = lb_end - start;
@@ -301,29 +305,31 @@
 			seg->phdr_next->phdr_prev = new;
 			seg->phdr_next = new;
 
-			printk_spew("   late: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-				new->s_dstaddr, 
+			printk_spew("   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+				new->s_dstaddr,
 				new->s_dstaddr + new->s_filesz,
 				new->s_dstaddr + new->s_memsz);
 		}
 	}
 
 	/* Now retarget this segment onto the bounce buffer */
-	/* sort of explanation: the buffer is a 1:1 mapping to coreboot. 
+	/* sort of explanation: the buffer is a 1:1 mapping to coreboot.
 	 * so you will make the dstaddr be this buffer, and it will get copied
 	 * later to where coreboot lives.
 	 */
 	seg->s_dstaddr = buffer + (seg->s_dstaddr - lb_start);
 
-	printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-		seg->s_dstaddr, 
-		seg->s_dstaddr + seg->s_filesz, 
+	printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n",
+		seg->s_dstaddr,
+		seg->s_dstaddr + seg->s_filesz,
 		seg->s_dstaddr + seg->s_memsz);
+
+	return ret;
 }
 
 
 static int build_self_segment_list(
-	struct segment *head, 
+	struct segment *head,
 	struct lb_memory *mem,
 	struct cbfs_payload *payload, u32 *entry)
 {
@@ -345,7 +351,7 @@
 
 		case PAYLOAD_SEGMENT_CODE:
 		case PAYLOAD_SEGMENT_DATA:
-			printk_debug("  %s (compression=%x)\n", 
+			printk_debug("  %s (compression=%x)\n",
 					segment->type == PAYLOAD_SEGMENT_CODE ?  "code" : "data",
 					ntohl(segment->compression));
 			new = malloc(sizeof(*new));
@@ -394,7 +400,7 @@
 
 		segment++;
 
-		// FIXME: Explain what this is 
+		// FIXME: Explain what this is
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohl((u32) segment->load_addr))
 				break;
@@ -422,7 +428,7 @@
 	struct cbfs_payload *payload)
 {
 	struct segment *ptr;
-	
+
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
 		if (!overlaps_coreboot(ptr)) continue;
@@ -443,10 +449,13 @@
 		unsigned char *dest, *src;
 		printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
-		
+
 		/* Modify the segment to load onto the bounce_buffer if necessary.
 		 */
-		relocate_segment(bounce_buffer, ptr);
+		if (relocate_segment(bounce_buffer, ptr)) {
+			ptr = (ptr->prev)->prev;
+			continue;
+		}
 
 		printk_debug("Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
 			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
@@ -454,7 +463,7 @@
 		/* Compute the boundaries of the segment */
 		dest = (unsigned char *)(ptr->s_dstaddr);
 		src = (unsigned char *)(ptr->s_srcaddr);
-		
+
 		/* Copy data from the initial buffer */
 		if (ptr->s_filesz) {
 			unsigned char *middle, *end;
@@ -496,7 +505,7 @@
 			if (middle < end) {
 				printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n",
 					(unsigned long)middle, (unsigned long)(end - middle));
-			
+
 				/* Zero the extra bytes */
 				memset(middle, 0, end - middle);
 			}




From Zheng.Bao at amd.com  Thu Nov  5 11:04:22 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Thu, 5 Nov 2009 18:04:22 +0800
Subject: [coreboot] [PATCH] The filo crashes if the filo
	and	corebootoverlap.
In-Reply-To: <4AF297AD.40707@coresystems.de>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl><1257005604.23416.18.camel@tetris><DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B17032A05E7@sbjgexmb1.amd.com>
	<4AF297AD.40707@coresystems.de>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032F33AE@sbjgexmb1.amd.com>

r4912.
Delete some trailing whitespace.

-----Original Message-----
From: Stefan Reinauer [mailto:stepan at coresystems.de] 
Sent: Thursday, November 05, 2009 5:15 PM
To: Bao, Zheng
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [PATCH] The filo crashes if the filo and corebootoverlap.

Bao, Zheng wrote:
> Ping, before we forget.
> Can anyone ack or nack this?
>
> Zheng
>
>
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
> Sent: Tuesday, November 03, 2009 11:23 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] The filo crashes if the filo and
> corebootoverlap.
>
> If the coreboot and filo overlap, it will "slice off" a piece at the
> beginning or end. In the beginning case, a new segment is inserted
> before the current one.  The ptr will move forward and doesn't seem to
> have any chance to process the "new" segment.
>
>                 ptr ---------+     move --->
>                              |
>                              V
>         +--------+       +--------+
>         |        |       |        |
>         |  new   | <---> |current | <---> .....
>         |        |       |        |
>         +--------+       +--------+
>
> Now we change the ptr to the previous one and restart the loop. The
> new and current segment will both be processed.
>
>       +----------------ptr      move --->
>       |
>       V
>  +--------+        +--------+       +--------+
>  |        |        |        |       |        |
>  |  prev  | <--->  |  new   | <---> |current | <---> .....
>  |        |        |        |       |        |
>  +--------+        +--------+       +--------+
>
> It is tested on my Family 10 board.
>
>   

Very nice explanation... :-)

Acked-by: Stefan Reinauer <stepan at coresystems.de>





> Zheng
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
>
> Index: src/boot/selfboot.c
> ===================================================================
> --- src/boot/selfboot.c	(revision 4892)
> +++ src/boot/selfboot.c	(working copy)
> @@ -211,19 +211,21 @@
>  	return !((end <= lb_start) || (start >= lb_end));
>  }
>  
> -static void relocate_segment(unsigned long buffer, struct segment *seg)
> +static int relocate_segment(unsigned long buffer, struct segment *seg)
>  {
>  	/* Modify all segments that want to load onto coreboot
>  	 * to load onto the bounce buffer instead.
>  	 */
> -	unsigned long start, middle, end;
> +	/* ret:  1 : A new segment is inserted before the seg.
> +	 *       0 : A new segment is inserted after the seg, or no new
> one. */
> +	unsigned long start, middle, end, ret = 0;
>  
>  	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
>  		lb_start, lb_end);
>  
>  	/* I don't conflict with coreboot so get out of here */
>  	if (!overlaps_coreboot(seg))
> -		return;
> +		return 0;
>  
>  	start = seg->s_dstaddr;
>  	middle = start + seg->s_filesz;
> @@ -270,6 +272,8 @@
>  				new->s_dstaddr, 
>  				new->s_dstaddr + new->s_filesz,
>  				new->s_dstaddr + new->s_memsz);
> +
> +			ret = 1;
>  		}
>  			
>  		/* Slice off a piece at the end 
> @@ -319,6 +323,8 @@
>  		seg->s_dstaddr, 
>  		seg->s_dstaddr + seg->s_filesz, 
>  		seg->s_dstaddr + seg->s_memsz);
> +
> +	return ret;
>  }
>  
>  
> @@ -446,7 +452,10 @@
>  		
>  		/* Modify the segment to load onto the bounce_buffer if
> necessary.
>  		 */
> -		relocate_segment(bounce_buffer, ptr);
> +		if (relocate_segment(bounce_buffer, ptr)) {
> +			ptr = (ptr->prev)->prev;
> +			continue;
> +		}
>  
>  		printk_debug("Post relocation: addr: 0x%016lx memsz:
> 0x%016lx filesz: 0x%016lx\n",
>  			ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz);
>
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
> Sent: Monday, November 02, 2009 11:25 AM
> To: Patrick Georgi
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] The filo crashes if the filo and coreboot
> overlap.
>
> In relocate_segment().
> If the coreboot and filo overlap, it will "slice off" a piece at the
> beginning or end. A new segment is allocated. If it is inserted before
> the "seg" that is being processed, is there any chance that the "new"
> segment will be processed? I am confused about it. On my fam 10 board,
> it seems that the "new" segment was not processed and an error happens
> when the code jumps to filo which is actually middle of nowhere.
>
>
> Zheng
>
> -----Original Message-----
> From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
> [mailto:coreboot-bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of
> Patrick Georgi
> Sent: Sunday, November 01, 2009 12:13 AM
> To: Zheng Bao
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] The filo crashes if the filo and coreboot
> overlap.
>
> Am Samstag, den 31.10.2009, 15:43 +0000 schrieb Zheng Bao:
>   
>> The filo crashes if the filo and coreboot overlap.
>> Since the CBFS is the must-have feature, my family 10
>>  board crashes when it jumps to filo. I am trying to
>>  find out why. I need help.
>> Based on current code, the AMD Family 10 will cause the filo
>> and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c
>> will return 1. But I am not sure if it will make the system
>> crashes.
>>     
> What revision is that? There was an issue like that but I fixed it
> several weeks ago.
>
>   
>> If anybody explains briefly what happens if they
>> overlap.
>>     
> When coreboot and payload overlap, coreboot uses a bounce buffer. The
> bounce buffer is twice the size of coreboot. The first half is for the
> part of the payload that overlaps coreboot, the other half is for
> coreboot itself.
>
> The SELF loader loads data that would overlap coreboot to the bounce
> buffer, and jumps into jmp_to_elf_entry when it's done with loading.
> The jmp_to_elf_entry function copies coreboot to the upper half of the
> bounce buffer, and jumps in there, so the code is out of the way.
>
> Then it copies the lower half to the coreboot area and jumps to the
> entry point.
>
> There are some complications to that because of the decompression
> routine, so the code is not as nice as it should be. But I specifically
> tested your scenario (payload from 1mb to 2.3mb or so, coreboot starting
> at 2mb)
>
>   
>> The coreboot information:
>> CONFIG_RAMBASE=0x00200000
>>     
> Try changing that to 0x100000.
>
>
> Patrick
>
>
>   


-- 
coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 * Fax: +49 761 7664613
Email: info at coresystems.de  * http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg * HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer * Ust-IdNr.: DE245674866






From mch at virtutech.com  Thu Nov  5 11:24:17 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 05 Nov 2009 11:24:17 +0100
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <20091105095447.GV27911@redhat.com>
References: <4AF04CD4.1030007@virtutech.com>	<20091104033012.GA32618@morn.localdomain>	<20091104144011.GR27911@redhat.com>	<4AF29B49.7090001@virtutech.com>
	<20091105095447.GV27911@redhat.com>
Message-ID: <4AF2A7D1.6010809@virtutech.com>

On 11/05/2009 10:54 AM, Gleb Natapov wrote:
> On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
>    
>> On 11/04/2009 03:40 PM, Gleb Natapov wrote:
>>      
>>> On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
>>>        
>>>> On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
>>>>          
>>>>> I'm attaching patches for seabios to make it work on the Virtutech
>>>>> Simics x86-440bx model. Please let me know if there is some other list
>>>>> that is preferred for seabios patches.
>>>>>
>>>>> Patches 1-6 and 9 are not really related to the Virtutech model at all,
>>>>> so those would be prime candidates to be included in the mainline
>>>>> version.
>>>>>            
>>> l>   Thanks Magnus.
>>>        
>>>> Gleb I'm not sure if you're on the coreboot mailing list - can you
>>>> take a look at these patches as well?  A URL is at:
>>>>
>>>> http://permalink.gmane.org/gmane.linux.bios/55487
>>>>
>>>>          
>>> Can I get them in a mbox format somewhere? Want to tested them to be
>>> sure. From review:
>>> 1:
>>>   OK
>>>
>>> 2:
>>>   What is the reason for this? x86info --mptable on my 4 core AMD shows
>>> MP Table:
>>> #       APIC ID Version State           Family  Model   Step    Flags
>>> #        0       0x10    BSP, usable     16      4       1     0x178bfbff
>>> #        1       0x10    AP, usable      16      4       1     0x178bfbff
>>> #        2       0x10    AP, usable      16      4       1     0x178bfbff
>>> #        3       0x10    AP, usable      16      4       1     0x178bfbff
>>>        
>> I can think of two reasons for only listing one CPU per package. The
>> first would be performance, in that the OS needs to be aware of
>> multi-threading in order not to slow down high priority tasks with
>> stuff that is usually free when running on multiple processors (like
>> spinlocks). The second reason would be that logical CPUs in the same
>> package share some MSRs, and an OS that isn't aware of that may
>> cease to work in such an environment.
>>
>> Related link:
>>
>> http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
>>
>>      
> This list talks about HT. Why not add entry for each core though? I am
> not aware of any MSRs shared between cores
>    
Some MSRs are shared between cores, for example lots of the memory check 
MSRs in Nehalem, although an OS that knows about MCs would probably also 
know something about how they are shared. Adding multiple cores to the 
MPS tables would probably not break anything. One reason why they are 
still filtered out in at least some cases could be that multiple cores 
and threads are flagged with the same bit (the HTT bit).

>
>    
>> > From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
>> From: Magnus Christensson<mch at virtutech.com>
>> Date: Tue, 3 Nov 2009 12:50:09 +0100
>> Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
>>
>> ---
>>   src/mptable.c |   26 ++++++++++++++++++++++----
>>   1 files changed, 22 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/mptable.c b/src/mptable.c
>> index 805fe1b..525188d 100644
>> --- a/src/mptable.c
>> +++ b/src/mptable.c
>> @@ -44,16 +44,32 @@ mptable_init(void)
>>       config->spec = 4;
>>       memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
>>       memcpy(config->productid, "0.1         ", sizeof(config->productid));
>> -    config->entrycount = MaxCountCPUs + 2 + 16;
>>       config->lapic = BUILD_APIC_ADDR;
>>
>>       // CPU definitions.
>>       u32 cpuid_signature, ebx, ecx, cpuid_features;
>>       cpuid(1,&cpuid_signature,&ebx,&ecx,&cpuid_features);
>>       struct mpt_cpu *cpus = (void*)&config[1];
>> -    int i;
>> -    for (i = 0; i<  MaxCountCPUs; i++) {
>> +    int i, actual_cpu_count;
>> +    for (i = 0, actual_cpu_count = 0; i<  MaxCountCPUs; i++) {
>>           struct mpt_cpu *cpu =&cpus[i];
>> +        int log_cpus = (ebx>>  16)&  0xff;
>> +
>> +        /* Only populate the MPS tables with the first logical CPU in each
>> +           package */
>> +        if ((cpuid_features&  (1<<  28))&&
>> +            log_cpus>  1&&
>> +            ((log_cpus<= 2&&  (i&  1) != 0) ||
>> +             (log_cpus<= 4&&  (i&  3) != 0) ||
>> +             (log_cpus<= 8&&  (i&  7) != 0) ||
>> +             (log_cpus<= 16&&  (i&  15) != 0) ||
>> +             (log_cpus<= 32&&  (i&  31) != 0) ||
>> +             (log_cpus<= 64&&  (i&  63) != 0) ||
>> +             (log_cpus<= 128&&  (i&  127) != 0)))
>> +            continue;
>> +
>>      
> Isn't this the same as (i&  (log_cpus - 1) != 0)?
>    
Yes, as long as log_cpus is a power of 2. But not if it's for example 3.

M.

> --
> 			Gleb.
>
>    




From info at coresystems.de  Thu Nov  5 11:29:31 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 05 Nov 2009 10:29:31 +0000
Subject: [coreboot] build service results for r4912
Message-ID: <E1N5zat-0004wt-3E@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "zbao" checked in revision 4912 to
the coreboot repository. This caused the following 
changes:

Change Log:
If the coreboot and filo overlap, it will "slice off" a piece at the
"beginning" or "end". In the beginning case, a new segment is inserted
before the current one.  But the ptr will move forward and doesn't
seem to have any other chance to process the "new" segment.

                ptr ---------+     move --->
                             |
                             V
        +--------+       +--------+
        |        |       |        |
        |  new   | <---> |current | <---> .....
        |        |       |        |
        +--------+       +--------+

Now we change the ptr to the previous one and restart the loop. The
new and current segment will both be processed. Even if the current
segment is done twice, no new segment will come up and ptr will move
forward as we expect.

      +----------------ptr      move --->
      |
      V
 +--------+        +--------+       +--------+
 |        |        |        |       |        |
 |  prev  | <--->  |  new   | <---> |current | <---> .....
 |        |        |        |       |        |
 +--------+        +--------+       +--------+

It is tested and fixes the crashing on my AMD Family 10 board.

Some trailing whitespaces were deleted.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Build Log:
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4912&device=qemu-x86&vendor=emulation&num=2


If something broke during this checkin please be a pain 
in zbao's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From gleb at redhat.com  Thu Nov  5 11:49:53 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Thu, 5 Nov 2009 12:49:53 +0200
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <4AF2A7D1.6010809@virtutech.com>
References: <4AF04CD4.1030007@virtutech.com>
	<20091104033012.GA32618@morn.localdomain>
	<20091104144011.GR27911@redhat.com>
	<4AF29B49.7090001@virtutech.com>
	<20091105095447.GV27911@redhat.com>
	<4AF2A7D1.6010809@virtutech.com>
Message-ID: <20091105104953.GA15913@redhat.com>

On Thu, Nov 05, 2009 at 11:24:17AM +0100, Magnus Christensson wrote:
> On 11/05/2009 10:54 AM, Gleb Natapov wrote:
> >On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
> >>On 11/04/2009 03:40 PM, Gleb Natapov wrote:
> >>>On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
> >>>>On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
> >>>>>I'm attaching patches for seabios to make it work on the Virtutech
> >>>>>Simics x86-440bx model. Please let me know if there is some other list
> >>>>>that is preferred for seabios patches.
> >>>>>
> >>>>>Patches 1-6 and 9 are not really related to the Virtutech model at all,
> >>>>>so those would be prime candidates to be included in the mainline
> >>>>>version.
> >>>l>   Thanks Magnus.
> >>>>Gleb I'm not sure if you're on the coreboot mailing list - can you
> >>>>take a look at these patches as well?  A URL is at:
> >>>>
> >>>>http://permalink.gmane.org/gmane.linux.bios/55487
> >>>>
> >>>Can I get them in a mbox format somewhere? Want to tested them to be
> >>>sure. From review:
> >>>1:
> >>>  OK
> >>>
> >>>2:
> >>>  What is the reason for this? x86info --mptable on my 4 core AMD shows
> >>>MP Table:
> >>>#       APIC ID Version State           Family  Model   Step    Flags
> >>>#        0       0x10    BSP, usable     16      4       1     0x178bfbff
> >>>#        1       0x10    AP, usable      16      4       1     0x178bfbff
> >>>#        2       0x10    AP, usable      16      4       1     0x178bfbff
> >>>#        3       0x10    AP, usable      16      4       1     0x178bfbff
> >>I can think of two reasons for only listing one CPU per package. The
> >>first would be performance, in that the OS needs to be aware of
> >>multi-threading in order not to slow down high priority tasks with
> >>stuff that is usually free when running on multiple processors (like
> >>spinlocks). The second reason would be that logical CPUs in the same
> >>package share some MSRs, and an OS that isn't aware of that may
> >>cease to work in such an environment.
> >>
> >>Related link:
> >>
> >>http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
> >>
> >This list talks about HT. Why not add entry for each core though? I am
> >not aware of any MSRs shared between cores
> Some MSRs are shared between cores, for example lots of the memory
> check MSRs in Nehalem, although an OS that knows about MCs would
> probably also know something about how they are shared. Adding
> multiple cores to the MPS tables would probably not break anything.
> One reason why they are still filtered out in at least some cases
> could be that multiple cores and threads are flagged with the same
> bit (the HTT bit).
> 
OK. I don't think it is very important for modern guests anyway.

> >
> >>> From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
> >>From: Magnus Christensson<mch at virtutech.com>
> >>Date: Tue, 3 Nov 2009 12:50:09 +0100
> >>Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
> >>
> >>---
> >>  src/mptable.c |   26 ++++++++++++++++++++++----
> >>  1 files changed, 22 insertions(+), 4 deletions(-)
> >>
> >>diff --git a/src/mptable.c b/src/mptable.c
> >>index 805fe1b..525188d 100644
> >>--- a/src/mptable.c
> >>+++ b/src/mptable.c
> >>@@ -44,16 +44,32 @@ mptable_init(void)
> >>      config->spec = 4;
> >>      memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
> >>      memcpy(config->productid, "0.1         ", sizeof(config->productid));
> >>-    config->entrycount = MaxCountCPUs + 2 + 16;
> >>      config->lapic = BUILD_APIC_ADDR;
> >>
> >>      // CPU definitions.
> >>      u32 cpuid_signature, ebx, ecx, cpuid_features;
> >>      cpuid(1,&cpuid_signature,&ebx,&ecx,&cpuid_features);
> >>      struct mpt_cpu *cpus = (void*)&config[1];
> >>-    int i;
> >>-    for (i = 0; i<  MaxCountCPUs; i++) {
> >>+    int i, actual_cpu_count;
> >>+    for (i = 0, actual_cpu_count = 0; i<  MaxCountCPUs; i++) {
> >>          struct mpt_cpu *cpu =&cpus[i];
> >>+        int log_cpus = (ebx>>  16)&  0xff;
> >>+
> >>+        /* Only populate the MPS tables with the first logical CPU in each
> >>+           package */
> >>+        if ((cpuid_features&  (1<<  28))&&
> >>+            log_cpus>  1&&
> >>+            ((log_cpus<= 2&&  (i&  1) != 0) ||
> >>+             (log_cpus<= 4&&  (i&  3) != 0) ||
> >>+             (log_cpus<= 8&&  (i&  7) != 0) ||
> >>+             (log_cpus<= 16&&  (i&  15) != 0) ||
> >>+             (log_cpus<= 32&&  (i&  31) != 0) ||
> >>+             (log_cpus<= 64&&  (i&  63) != 0) ||
> >>+             (log_cpus<= 128&&  (i&  127) != 0)))
> >>+            continue;
> >>+
> >Isn't this the same as (i&  (log_cpus - 1) != 0)?
> Yes, as long as log_cpus is a power of 2. But not if it's for example 3.
> 
How about this:

static inline unsigned long fls(unsigned long word)
{
        asm("bsr %1,%0"
            : "=r" (word)
            : "rm" (word));
        return word + 1;
}

log_cpus = 1UL << fls(atoi(log_cpus) - 1)

(i & (log_cpus - 1) != 0)

--
			Gleb.



From svn at coreboot.org  Thu Nov  5 13:38:34 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 12:38:34 +0000
Subject: [coreboot] [v2] r4913 - in trunk/src: include/pc80 pc80
Message-ID: <mailman.4000.1355071652.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 12:38:34 +0000 (Thu, 05 Nov 2009)
New Revision: 4913

Added:
   trunk/src/include/pc80/i8254.h
   trunk/src/pc80/i8254.c
Modified:
   trunk/src/pc80/Config.lb
   trunk/src/pc80/Makefile.inc
Log:
http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html

This function is not called right now,... Please step in and fix up your code,
folks.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Added: trunk/src/include/pc80/i8254.h
===================================================================
--- trunk/src/include/pc80/i8254.h	                        (rev 0)
+++ trunk/src/include/pc80/i8254.h	2009-11-05 12:38:34 UTC (rev 4913)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef PC80_I8254_H
+#define PC80_I8254_H
+
+/* Ports for the 8254 timer chip */
+#define TIMER0_PORT	0x40
+#define TIMER1_PORT	0x41
+#define TIMER2_PORT     0x42
+#define TIMER_MODE_PORT 0x43
+
+/* Meaning of the mode bits */
+#define TIMER0_SEL      0x00
+#define TIMER1_SEL      0x40
+#define TIMER2_SEL      0x80
+#define READBACK_SEL    0xC0
+
+#define LATCH_COUNT     0x00
+#define LOBYTE_ACCESS   0x10
+#define HIBYTE_ACCESS   0x20
+#define WORD_ACCESS     0x30
+
+#define MODE0           0x00
+#define MODE1           0x02
+#define MODE2           0x04
+#define MODE3           0x06
+#define MODE4           0x08
+#define MODE5           0x0A
+
+#define BINARY_COUNT    0x00
+#define BCD_COUNT       0x01
+
+/* Timers tick over at this rate */
+#define TICKS_PER_MS    1193
+
+/* Parallel Peripheral Controller Port B */
+#define PPC_PORTB       0x61
+
+/* Meaning of the port bits */
+#define PPCB_T2OUT      0x20    /* Bit 5 */
+#define PPCB_SPKR       0x02    /* Bit 1 */
+#define PPCB_T2GATE     0x01    /* Bit 0 */
+
+#endif

Modified: trunk/src/pc80/Config.lb
===================================================================
--- trunk/src/pc80/Config.lb	2009-11-05 10:02:59 UTC (rev 4912)
+++ trunk/src/pc80/Config.lb	2009-11-05 12:38:34 UTC (rev 4913)
@@ -5,7 +5,6 @@
 object mc146818rtc.o
 object isa-dma.o
 object i8259.o 
-#object udelay_timer2.o CONFIG_UDELAY_TIMER2
 
 if CONFIG_UDELAY_IO
 	object udelay_io.o

Modified: trunk/src/pc80/Makefile.inc
===================================================================
--- trunk/src/pc80/Makefile.inc	2009-11-05 10:02:59 UTC (rev 4912)
+++ trunk/src/pc80/Makefile.inc	2009-11-05 12:38:34 UTC (rev 4913)
@@ -1,7 +1,6 @@
 obj-y += mc146818rtc.o
 obj-y += isa-dma.o
 obj-y += i8259.o 
-#obj-y += udelay_timer2.o CONFIG_UDELAY_TIMER2
 obj-$(CONFIG_UDELAY_IO) += udelay_io.o
 obj-y += keyboard.o
 

Added: trunk/src/pc80/i8254.c
===================================================================
--- trunk/src/pc80/i8254.c	                        (rev 0)
+++ trunk/src/pc80/i8254.c	2009-11-05 12:38:34 UTC (rev 4913)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <pc80/i8254.h>
+#include <console/console.h>
+
+/* Initialize i8254 timers */
+
+void setup_i8254(void)
+{
+	/* Timer 0 (taken from biosemu) */
+	outb(TIMER0_SEL|WORD_ACCESS|MODE3|BINARY_COUNT, TIMER_MODE_PORT);
+	outb(0x00, TIMER0_PORT);
+	outb(0x00, TIMER0_PORT);
+
+	/* Timer 1 */
+	outb(TIMER1_SEL|LOBYTE_ACCESS|MODE3|BINARY_COUNT, TIMER_MODE_PORT);
+	outb(0x12, TIMER1_PORT);
+}
+
+#ifdef CONFIG_UDELAY_TIMER2
+static void load_timer2(unsigned int ticks)
+{
+        /* Set up the timer gate, turn off the speaker */
+        outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
+        outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT);
+        outb(ticks & 0xFF, TIMER2_PORT);
+        outb(ticks >> 8, TIMER2_PORT);
+}
+
+
+void udelay(int usecs)
+{
+        load_timer2((usecs*TICKS_PER_MS)/1000);
+        while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0)
+                ;
+}
+#endif




From nathan at traverse.com.au  Thu Nov  5 13:42:40 2009
From: nathan at traverse.com.au (Nathan Williams)
Date: Thu, 05 Nov 2009 23:42:40 +1100
Subject: [coreboot] GeodeLX RAM initialisation issue
Message-ID: <4AF2C840.5050104@traverse.com.au>

Hi I am trying to sort out a RAM issue with coreboot on a motherboard we 
have designed at my work.

The board uses the AMD LX800 and CS5536 companion chipset.

I have been using coreboot-v3 and based my board port on the Alix 1.C 
code.  We have a SODIMM socket, so I used the initram.c from the 
amd/db800 code because it does SPD.

The symptoms are that sometimes a boot will die during disable_car() in
arch/x86/geodelx/stage1.c:

         /* OK, here is the theory: we should be able to copy
          * the data back over itself, and the wbinvd should then
          * flush to memory. Let's see.
          */
         __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), 
"S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
         __asm__ __volatile__ ("wbinvd\n");


Sometimes it boots fine and appears to be quite stable.  If I run 
software like mprime95 to "Torture Test" the system, it doesn't fail.

However, there is one strange phenomenon that I've noticed.  If I remove 
the RTC battery backup and Linux forces a fsck because the last boot 
time was in the future.  If Linux fixes a couple of errors and reboots 
automatically in 5 seconds, during the reboot it's almost guaranteed 
that coreboot will get stuck in disable_car().  I don't know if this is 
useful, or just a coincidence.  In my build I have also disabled the 
CMOS Option Table (CONFIG_OPTION_TABLE) in case something there might be 
causing the problem.

Initially I thought it was a hardware problem with our PCBs, but have 
tested with a bios chip from an AMD reference design board (EmbeddedBIOS 
v5.3) which booted Linux fine without any problems, so I have concluded 
that my problem must be something I'm doing (or not doing) in coreboot.

I have checked all the SPD values against the datasheet for the Hynix 
RAM chips (256MiB 333MHz).  I tried using the non-SPD method as in the 
Alix 1.C code and specified all the RAM parameters.  I have also tried 
to follow sdram_enable() and other functions in 
northbridge/amd/geodelx/raminit.c to check against the AMD LX databook's
section 6.1.3 BIOS Initialization Sequence, though I admit I could have 
easily missed something here.

I would be most grateful of any suggestions for helping me work out 
what's going wrong.

Regards,
Nathan



From svn at coreboot.org  Thu Nov  5 13:44:51 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 12:44:51 +0000
Subject: [coreboot] [v2] r4914 - trunk/util/x86emu
Message-ID: <mailman.4001.1355071652.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 12:44:50 +0000 (Thu, 05 Nov 2009)
New Revision: 4914

Modified:
   trunk/util/x86emu/x86_interrupts.c
Log:
fix Qemu

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/util/x86emu/x86_interrupts.c
===================================================================
--- trunk/util/x86emu/x86_interrupts.c	2009-11-05 12:38:34 UTC (rev 4913)
+++ trunk/util/x86emu/x86_interrupts.c	2009-11-05 12:44:50 UTC (rev 4914)
@@ -73,6 +73,9 @@
 	short devindex;
 	unsigned char bus;
 	struct device *dev;
+	u32 dword;
+	u16 word;
+	u8 byte, reg;
 
 	switch (func) {
 	case PCIBIOS_CHECK:
@@ -115,11 +118,6 @@
 	case PCIBIOS_WRITECONFDWORD:
 	case PCIBIOS_WRITECONFWORD:
 	case PCIBIOS_WRITECONFBYTE:
-		unsigned long dword;
-		unsigned short word;
-		unsigned char byte;
-		unsigned char reg;
-
 		devfn = regs->ebx & 0xff;
 		bus = regs->ebx >> 8;
 		reg = regs->edi;




From info at coresystems.de  Thu Nov  5 14:02:24 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 05 Nov 2009 13:02:24 +0000
Subject: [coreboot] build service results for r4913
Message-ID: <E1N61yq-0004EE-25@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4913 to
the coreboot repository. This caused the following 
changes:

Change Log:
http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html

This function is not called right now,... Please step in and fix up your code,
folks.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of emulation:qemu-x86 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4913&device=qemu-x86&vendor=emulation&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mch at virtutech.com  Thu Nov  5 14:02:09 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 05 Nov 2009 14:02:09 +0100
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <20091105104953.GA15913@redhat.com>
References: <4AF04CD4.1030007@virtutech.com>	<20091104033012.GA32618@morn.localdomain>	<20091104144011.GR27911@redhat.com>	<4AF29B49.7090001@virtutech.com>	<20091105095447.GV27911@redhat.com>	<4AF2A7D1.6010809@virtutech.com>
	<20091105104953.GA15913@redhat.com>
Message-ID: <4AF2CCD1.9010709@virtutech.com>

On 11/05/2009 11:49 AM, Gleb Natapov wrote:
> On Thu, Nov 05, 2009 at 11:24:17AM +0100, Magnus Christensson wrote:
>    
>> On 11/05/2009 10:54 AM, Gleb Natapov wrote:
>>      
>>> On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
>>>        
>>>> On 11/04/2009 03:40 PM, Gleb Natapov wrote:
>>>>          
>>>>> On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
>>>>>            
>>>>>> On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
>>>>>>              
>>>>>>> I'm attaching patches for seabios to make it work on the Virtutech
>>>>>>> Simics x86-440bx model. Please let me know if there is some other list
>>>>>>> that is preferred for seabios patches.
>>>>>>>
>>>>>>> Patches 1-6 and 9 are not really related to the Virtutech model at all,
>>>>>>> so those would be prime candidates to be included in the mainline
>>>>>>> version.
>>>>>>>                
>>>>> l>    Thanks Magnus.
>>>>>            
>>>>>> Gleb I'm not sure if you're on the coreboot mailing list - can you
>>>>>> take a look at these patches as well?  A URL is at:
>>>>>>
>>>>>> http://permalink.gmane.org/gmane.linux.bios/55487
>>>>>>
>>>>>>              
>>>>> Can I get them in a mbox format somewhere? Want to tested them to be
>>>>> sure. From review:
>>>>> 1:
>>>>>   OK
>>>>>
>>>>> 2:
>>>>>   What is the reason for this? x86info --mptable on my 4 core AMD shows
>>>>> MP Table:
>>>>> #       APIC ID Version State           Family  Model   Step    Flags
>>>>> #        0       0x10    BSP, usable     16      4       1     0x178bfbff
>>>>> #        1       0x10    AP, usable      16      4       1     0x178bfbff
>>>>> #        2       0x10    AP, usable      16      4       1     0x178bfbff
>>>>> #        3       0x10    AP, usable      16      4       1     0x178bfbff
>>>>>            
>>>> I can think of two reasons for only listing one CPU per package. The
>>>> first would be performance, in that the OS needs to be aware of
>>>> multi-threading in order not to slow down high priority tasks with
>>>> stuff that is usually free when running on multiple processors (like
>>>> spinlocks). The second reason would be that logical CPUs in the same
>>>> package share some MSRs, and an OS that isn't aware of that may
>>>> cease to work in such an environment.
>>>>
>>>> Related link:
>>>>
>>>> http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
>>>>
>>>>          
>>> This list talks about HT. Why not add entry for each core though? I am
>>> not aware of any MSRs shared between cores
>>>        
>> Some MSRs are shared between cores, for example lots of the memory
>> check MSRs in Nehalem, although an OS that knows about MCs would
>> probably also know something about how they are shared. Adding
>> multiple cores to the MPS tables would probably not break anything.
>> One reason why they are still filtered out in at least some cases
>> could be that multiple cores and threads are flagged with the same
>> bit (the HTT bit).
>>
>>      
> OK. I don't think it is very important for modern guests anyway.
>    
Right. Anything modern should look at the ACPI tables.

>    
>>>        
>>>>>  From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
>>>>>            
>>>> From: Magnus Christensson<mch at virtutech.com>
>>>> Date: Tue, 3 Nov 2009 12:50:09 +0100
>>>> Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
>>>>
>>>> ---
>>>>   src/mptable.c |   26 ++++++++++++++++++++++----
>>>>   1 files changed, 22 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/src/mptable.c b/src/mptable.c
>>>> index 805fe1b..525188d 100644
>>>> --- a/src/mptable.c
>>>> +++ b/src/mptable.c
>>>> @@ -44,16 +44,32 @@ mptable_init(void)
>>>>       config->spec = 4;
>>>>       memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
>>>>       memcpy(config->productid, "0.1         ", sizeof(config->productid));
>>>> -    config->entrycount = MaxCountCPUs + 2 + 16;
>>>>       config->lapic = BUILD_APIC_ADDR;
>>>>
>>>>       // CPU definitions.
>>>>       u32 cpuid_signature, ebx, ecx, cpuid_features;
>>>>       cpuid(1,&cpuid_signature,&ebx,&ecx,&cpuid_features);
>>>>       struct mpt_cpu *cpus = (void*)&config[1];
>>>> -    int i;
>>>> -    for (i = 0; i<   MaxCountCPUs; i++) {
>>>> +    int i, actual_cpu_count;
>>>> +    for (i = 0, actual_cpu_count = 0; i<   MaxCountCPUs; i++) {
>>>>           struct mpt_cpu *cpu =&cpus[i];
>>>> +        int log_cpus = (ebx>>   16)&   0xff;
>>>> +
>>>> +        /* Only populate the MPS tables with the first logical CPU in each
>>>> +           package */
>>>> +        if ((cpuid_features&   (1<<   28))&&
>>>> +            log_cpus>   1&&
>>>> +            ((log_cpus<= 2&&   (i&   1) != 0) ||
>>>> +             (log_cpus<= 4&&   (i&   3) != 0) ||
>>>> +             (log_cpus<= 8&&   (i&   7) != 0) ||
>>>> +             (log_cpus<= 16&&   (i&   15) != 0) ||
>>>> +             (log_cpus<= 32&&   (i&   31) != 0) ||
>>>> +             (log_cpus<= 64&&   (i&   63) != 0) ||
>>>> +             (log_cpus<= 128&&   (i&   127) != 0)))
>>>> +            continue;
>>>> +
>>>>          
>>> Isn't this the same as (i&   (log_cpus - 1) != 0)?
>>>        
>> Yes, as long as log_cpus is a power of 2. But not if it's for example 3.
>>
>>      
> How about this:
>
> static inline unsigned long fls(unsigned long word)
> {
>          asm("bsr %1,%0"
>              : "=r" (word)
>              : "rm" (word));
>          return word + 1;
> }
>
> log_cpus = 1UL<<  fls(atoi(log_cpus) - 1)
>
> (i&  (log_cpus - 1) != 0)
>    
Why atoi? Other than that it looks correct (assuming that the inline asm 
syntax is correct which I'm not fluent in).

M.




From gleb at redhat.com  Thu Nov  5 14:04:39 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Thu, 5 Nov 2009 15:04:39 +0200
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <4AF2CCD1.9010709@virtutech.com>
References: <4AF04CD4.1030007@virtutech.com>
	<20091104033012.GA32618@morn.localdomain>
	<20091104144011.GR27911@redhat.com>
	<4AF29B49.7090001@virtutech.com>
	<20091105095447.GV27911@redhat.com>
	<4AF2A7D1.6010809@virtutech.com>
	<20091105104953.GA15913@redhat.com>
	<4AF2CCD1.9010709@virtutech.com>
Message-ID: <20091105130439.GX27911@redhat.com>

On Thu, Nov 05, 2009 at 02:02:09PM +0100, Magnus Christensson wrote:
> On 11/05/2009 11:49 AM, Gleb Natapov wrote:
> >On Thu, Nov 05, 2009 at 11:24:17AM +0100, Magnus Christensson wrote:
> >>On 11/05/2009 10:54 AM, Gleb Natapov wrote:
> >>>On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
> >>>>On 11/04/2009 03:40 PM, Gleb Natapov wrote:
> >>>>>On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
> >>>>>>On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
> >>>>>>>I'm attaching patches for seabios to make it work on the Virtutech
> >>>>>>>Simics x86-440bx model. Please let me know if there is some other list
> >>>>>>>that is preferred for seabios patches.
> >>>>>>>
> >>>>>>>Patches 1-6 and 9 are not really related to the Virtutech model at all,
> >>>>>>>so those would be prime candidates to be included in the mainline
> >>>>>>>version.
> >>>>>l>    Thanks Magnus.
> >>>>>>Gleb I'm not sure if you're on the coreboot mailing list - can you
> >>>>>>take a look at these patches as well?  A URL is at:
> >>>>>>
> >>>>>>http://permalink.gmane.org/gmane.linux.bios/55487
> >>>>>>
> >>>>>Can I get them in a mbox format somewhere? Want to tested them to be
> >>>>>sure. From review:
> >>>>>1:
> >>>>>  OK
> >>>>>
> >>>>>2:
> >>>>>  What is the reason for this? x86info --mptable on my 4 core AMD shows
> >>>>>MP Table:
> >>>>>#       APIC ID Version State           Family  Model   Step    Flags
> >>>>>#        0       0x10    BSP, usable     16      4       1     0x178bfbff
> >>>>>#        1       0x10    AP, usable      16      4       1     0x178bfbff
> >>>>>#        2       0x10    AP, usable      16      4       1     0x178bfbff
> >>>>>#        3       0x10    AP, usable      16      4       1     0x178bfbff
> >>>>I can think of two reasons for only listing one CPU per package. The
> >>>>first would be performance, in that the OS needs to be aware of
> >>>>multi-threading in order not to slow down high priority tasks with
> >>>>stuff that is usually free when running on multiple processors (like
> >>>>spinlocks). The second reason would be that logical CPUs in the same
> >>>>package share some MSRs, and an OS that isn't aware of that may
> >>>>cease to work in such an environment.
> >>>>
> >>>>Related link:
> >>>>
> >>>>http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
> >>>>
> >>>This list talks about HT. Why not add entry for each core though? I am
> >>>not aware of any MSRs shared between cores
> >>Some MSRs are shared between cores, for example lots of the memory
> >>check MSRs in Nehalem, although an OS that knows about MCs would
> >>probably also know something about how they are shared. Adding
> >>multiple cores to the MPS tables would probably not break anything.
> >>One reason why they are still filtered out in at least some cases
> >>could be that multiple cores and threads are flagged with the same
> >>bit (the HTT bit).
> >>
> >OK. I don't think it is very important for modern guests anyway.
> Right. Anything modern should look at the ACPI tables.
> 
> >>>>> From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
> >>>>From: Magnus Christensson<mch at virtutech.com>
> >>>>Date: Tue, 3 Nov 2009 12:50:09 +0100
> >>>>Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
> >>>>
> >>>>---
> >>>>  src/mptable.c |   26 ++++++++++++++++++++++----
> >>>>  1 files changed, 22 insertions(+), 4 deletions(-)
> >>>>
> >>>>diff --git a/src/mptable.c b/src/mptable.c
> >>>>index 805fe1b..525188d 100644
> >>>>--- a/src/mptable.c
> >>>>+++ b/src/mptable.c
> >>>>@@ -44,16 +44,32 @@ mptable_init(void)
> >>>>      config->spec = 4;
> >>>>      memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
> >>>>      memcpy(config->productid, "0.1         ", sizeof(config->productid));
> >>>>-    config->entrycount = MaxCountCPUs + 2 + 16;
> >>>>      config->lapic = BUILD_APIC_ADDR;
> >>>>
> >>>>      // CPU definitions.
> >>>>      u32 cpuid_signature, ebx, ecx, cpuid_features;
> >>>>      cpuid(1,&cpuid_signature,&ebx,&ecx,&cpuid_features);
> >>>>      struct mpt_cpu *cpus = (void*)&config[1];
> >>>>-    int i;
> >>>>-    for (i = 0; i<   MaxCountCPUs; i++) {
> >>>>+    int i, actual_cpu_count;
> >>>>+    for (i = 0, actual_cpu_count = 0; i<   MaxCountCPUs; i++) {
> >>>>          struct mpt_cpu *cpu =&cpus[i];
> >>>>+        int log_cpus = (ebx>>   16)&   0xff;
> >>>>+
> >>>>+        /* Only populate the MPS tables with the first logical CPU in each
> >>>>+           package */
> >>>>+        if ((cpuid_features&   (1<<   28))&&
> >>>>+            log_cpus>   1&&
> >>>>+            ((log_cpus<= 2&&   (i&   1) != 0) ||
> >>>>+             (log_cpus<= 4&&   (i&   3) != 0) ||
> >>>>+             (log_cpus<= 8&&   (i&   7) != 0) ||
> >>>>+             (log_cpus<= 16&&   (i&   15) != 0) ||
> >>>>+             (log_cpus<= 32&&   (i&   31) != 0) ||
> >>>>+             (log_cpus<= 64&&   (i&   63) != 0) ||
> >>>>+             (log_cpus<= 128&&   (i&   127) != 0)))
> >>>>+            continue;
> >>>>+
> >>>Isn't this the same as (i&   (log_cpus - 1) != 0)?
> >>Yes, as long as log_cpus is a power of 2. But not if it's for example 3.
> >>
> >How about this:
> >
> >static inline unsigned long fls(unsigned long word)
> >{
> >         asm("bsr %1,%0"
> >             : "=r" (word)
> >             : "rm" (word));
> >         return word + 1;
> >}
> >
> >log_cpus = 1UL<<  fls(atoi(log_cpus) - 1)
> >
> >(i&  (log_cpus - 1) != 0)
> Why atoi? Other than that it looks correct (assuming that the inline
> asm syntax is correct which I'm not fluent in).
> 
atoi because of wrong cut&paste :) Drop it. Asm is from Linux so syntax is correct.

--
			Gleb.



From info at coresystems.de  Thu Nov  5 14:28:30 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 05 Nov 2009 13:28:30 +0000
Subject: [coreboot] build service results for r4914
Message-ID: <E1N62O6-00081H-Qs@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 4914 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix Qemu

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of emulation:qemu-x86 has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mch at virtutech.com  Thu Nov  5 15:00:45 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 05 Nov 2009 15:00:45 +0100
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <20091105130439.GX27911@redhat.com>
References: <4AF04CD4.1030007@virtutech.com>	<20091104033012.GA32618@morn.localdomain>	<20091104144011.GR27911@redhat.com>	<4AF29B49.7090001@virtutech.com>	<20091105095447.GV27911@redhat.com>	<4AF2A7D1.6010809@virtutech.com>	<20091105104953.GA15913@redhat.com>	<4AF2CCD1.9010709@virtutech.com>
	<20091105130439.GX27911@redhat.com>
Message-ID: <4AF2DA8D.1070302@virtutech.com>

On 11/05/2009 02:04 PM, Gleb Natapov wrote:
> On Thu, Nov 05, 2009 at 02:02:09PM +0100, Magnus Christensson wrote:
>    
>> On 11/05/2009 11:49 AM, Gleb Natapov wrote:
>>      
>>> On Thu, Nov 05, 2009 at 11:24:17AM +0100, Magnus Christensson wrote:
>>>        
>>>> On 11/05/2009 10:54 AM, Gleb Natapov wrote:
>>>>          
>>>>> On Thu, Nov 05, 2009 at 10:30:49AM +0100, Magnus Christensson wrote:
>>>>>            
>>>>>> On 11/04/2009 03:40 PM, Gleb Natapov wrote:
>>>>>>              
>>>>>>> On Tue, Nov 03, 2009 at 10:30:12PM -0500, Kevin O'Connor wrote:
>>>>>>>                
>>>>>>>> On Tue, Nov 03, 2009 at 04:31:32PM +0100, Magnus Christensson wrote:
>>>>>>>>                  
>>>>>>>>> I'm attaching patches for seabios to make it work on the Virtutech
>>>>>>>>> Simics x86-440bx model. Please let me know if there is some other list
>>>>>>>>> that is preferred for seabios patches.
>>>>>>>>>
>>>>>>>>> Patches 1-6 and 9 are not really related to the Virtutech model at all,
>>>>>>>>> so those would be prime candidates to be included in the mainline
>>>>>>>>> version.
>>>>>>>>>                    
>>>>>>> l>     Thanks Magnus.
>>>>>>>                
>>>>>>>> Gleb I'm not sure if you're on the coreboot mailing list - can you
>>>>>>>> take a look at these patches as well?  A URL is at:
>>>>>>>>
>>>>>>>> http://permalink.gmane.org/gmane.linux.bios/55487
>>>>>>>>
>>>>>>>>                  
>>>>>>> Can I get them in a mbox format somewhere? Want to tested them to be
>>>>>>> sure. From review:
>>>>>>> 1:
>>>>>>>   OK
>>>>>>>
>>>>>>> 2:
>>>>>>>   What is the reason for this? x86info --mptable on my 4 core AMD shows
>>>>>>> MP Table:
>>>>>>> #       APIC ID Version State           Family  Model   Step    Flags
>>>>>>> #        0       0x10    BSP, usable     16      4       1     0x178bfbff
>>>>>>> #        1       0x10    AP, usable      16      4       1     0x178bfbff
>>>>>>> #        2       0x10    AP, usable      16      4       1     0x178bfbff
>>>>>>> #        3       0x10    AP, usable      16      4       1     0x178bfbff
>>>>>>>                
>>>>>> I can think of two reasons for only listing one CPU per package. The
>>>>>> first would be performance, in that the OS needs to be aware of
>>>>>> multi-threading in order not to slow down high priority tasks with
>>>>>> stuff that is usually free when running on multiple processors (like
>>>>>> spinlocks). The second reason would be that logical CPUs in the same
>>>>>> package share some MSRs, and an OS that isn't aware of that may
>>>>>> cease to work in such an environment.
>>>>>>
>>>>>> Related link:
>>>>>>
>>>>>> http://software.intel.com/en-us/articles/hyper-threading-implications-and-setup-on-microsoft-operating-systems/
>>>>>>
>>>>>>              
>>>>> This list talks about HT. Why not add entry for each core though? I am
>>>>> not aware of any MSRs shared between cores
>>>>>            
>>>> Some MSRs are shared between cores, for example lots of the memory
>>>> check MSRs in Nehalem, although an OS that knows about MCs would
>>>> probably also know something about how they are shared. Adding
>>>> multiple cores to the MPS tables would probably not break anything.
>>>> One reason why they are still filtered out in at least some cases
>>>> could be that multiple cores and threads are flagged with the same
>>>> bit (the HTT bit).
>>>>
>>>>          
>>> OK. I don't think it is very important for modern guests anyway.
>>>        
>> Right. Anything modern should look at the ACPI tables.
>>
>>      
>>>>>>>  From a41c206097e801de29668f99ae9b9342614c716d Mon Sep 17 00:00:00 2001
>>>>>>>                
>>>>>> From: Magnus Christensson<mch at virtutech.com>
>>>>>> Date: Tue, 3 Nov 2009 12:50:09 +0100
>>>>>> Subject: [PATCH 2/8] Only add the first logical CPU in each physical CPU to the MPS tables.
>>>>>>
>>>>>> ---
>>>>>>   src/mptable.c |   26 ++++++++++++++++++++++----
>>>>>>   1 files changed, 22 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/src/mptable.c b/src/mptable.c
>>>>>> index 805fe1b..525188d 100644
>>>>>> --- a/src/mptable.c
>>>>>> +++ b/src/mptable.c
>>>>>> @@ -44,16 +44,32 @@ mptable_init(void)
>>>>>>       config->spec = 4;
>>>>>>       memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
>>>>>>       memcpy(config->productid, "0.1         ", sizeof(config->productid));
>>>>>> -    config->entrycount = MaxCountCPUs + 2 + 16;
>>>>>>       config->lapic = BUILD_APIC_ADDR;
>>>>>>
>>>>>>       // CPU definitions.
>>>>>>       u32 cpuid_signature, ebx, ecx, cpuid_features;
>>>>>>       cpuid(1,&cpuid_signature,&ebx,&ecx,&cpuid_features);
>>>>>>       struct mpt_cpu *cpus = (void*)&config[1];
>>>>>> -    int i;
>>>>>> -    for (i = 0; i<    MaxCountCPUs; i++) {
>>>>>> +    int i, actual_cpu_count;
>>>>>> +    for (i = 0, actual_cpu_count = 0; i<    MaxCountCPUs; i++) {
>>>>>>           struct mpt_cpu *cpu =&cpus[i];
>>>>>> +        int log_cpus = (ebx>>    16)&    0xff;
>>>>>> +
>>>>>> +        /* Only populate the MPS tables with the first logical CPU in each
>>>>>> +           package */
>>>>>> +        if ((cpuid_features&    (1<<    28))&&
>>>>>> +            log_cpus>    1&&
>>>>>> +            ((log_cpus<= 2&&    (i&    1) != 0) ||
>>>>>> +             (log_cpus<= 4&&    (i&    3) != 0) ||
>>>>>> +             (log_cpus<= 8&&    (i&    7) != 0) ||
>>>>>> +             (log_cpus<= 16&&    (i&    15) != 0) ||
>>>>>> +             (log_cpus<= 32&&    (i&    31) != 0) ||
>>>>>> +             (log_cpus<= 64&&    (i&    63) != 0) ||
>>>>>> +             (log_cpus<= 128&&    (i&    127) != 0)))
>>>>>> +            continue;
>>>>>> +
>>>>>>              
>>>>> Isn't this the same as (i&    (log_cpus - 1) != 0)?
>>>>>            
>>>> Yes, as long as log_cpus is a power of 2. But not if it's for example 3.
>>>>
>>>>          
>>> How about this:
>>>
>>> static inline unsigned long fls(unsigned long word)
>>> {
>>>          asm("bsr %1,%0"
>>>              : "=r" (word)
>>>              : "rm" (word));
>>>          return word + 1;
>>> }
>>>
>>> log_cpus = 1UL<<   fls(atoi(log_cpus) - 1)
>>>
>>> (i&   (log_cpus - 1) != 0)
>>>        
>> Why atoi? Other than that it looks correct (assuming that the inline
>> asm syntax is correct which I'm not fluent in).
>>
>>      
> atoi because of wrong cut&paste :) Drop it. Asm is from Linux so syntax is correct.
>    
Ok. Changed patches attached.

M.


From mch at virtutech.com  Thu Nov  5 14:44:01 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 14:44:01 +0100
Subject: [PATCH 1/9] Fix cpuflag in mptable (| has higher priority than ?:)
Message-ID: <mailman.4002.1355071652.16123.coreboot@coreboot.org>

---
 src/mptable.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 3945d2e..805fe1b 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -60,7 +60,7 @@ mptable_init(void)
         cpu->apicver = 0x11;
         /* cpu flags: enabled, bootstrap cpu */
         if (i < CountCPUs)
-            cpu->cpuflag = 1 | (i == 0) ? 2 : 0;
+            cpu->cpuflag = 1 | ((i == 0) ? 2 : 0);
         else
             cpu->cpuflag = 0;
         if (cpuid_signature) {
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 14:51:51 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 14:51:51 +0100
Subject: [PATCH 2/9] Only add the first logical CPU in each physical CPU to the MPS tables.
Message-ID: <mailman.4003.1355071652.16123.coreboot@coreboot.org>

---
 src/mptable.c |   28 ++++++++++++++++++++++++----
 1 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 805fe1b..0c07cfb 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -10,6 +10,15 @@
 #include "mptable.h" // MPTABLE_SIGNATURE
 #include "paravirt.h"
 
+static inline unsigned long
+fls(unsigned long word)
+{
+    asm("bsr %1,%0"
+        : "=r" (word)
+        : "rm" (word));
+    return word + 1;
+}
+
 void
 mptable_init(void)
 {
@@ -44,16 +53,25 @@ mptable_init(void)
     config->spec = 4;
     memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid));
     memcpy(config->productid, "0.1         ", sizeof(config->productid));
-    config->entrycount = MaxCountCPUs + 2 + 16;
     config->lapic = BUILD_APIC_ADDR;
 
     // CPU definitions.
     u32 cpuid_signature, ebx, ecx, cpuid_features;
     cpuid(1, &cpuid_signature, &ebx, &ecx, &cpuid_features);
     struct mpt_cpu *cpus = (void*)&config[1];
-    int i;
-    for (i = 0; i < MaxCountCPUs; i++) {
+    int i, actual_cpu_count;
+    for (i = 0, actual_cpu_count = 0; i < MaxCountCPUs; i++) {
         struct mpt_cpu *cpu = &cpus[i];
+        int log_cpus = (ebx >> 16) & 0xff;
+        log_cpus = 1UL << fls(log_cpus - 1); /* round up to power of 2 */
+
+        /* Only populate the MPS tables with the first logical CPU in each
+           package */
+        if ((cpuid_features & (1 << 28)) && (i & (log_cpus - 1)) != 0)
+            continue;
+
+        actual_cpu_count++;
+
         memset(cpu, 0, sizeof(*cpu));
         cpu->type = MPT_TYPE_CPU;
         cpu->apicid = i;
@@ -72,8 +90,10 @@ mptable_init(void)
         }
     }
 
+    config->entrycount = actual_cpu_count + 2 + 16;
+
     /* isa bus */
-    struct mpt_bus *bus = (void*)&cpus[MaxCountCPUs];
+    struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
     memset(bus, 0, sizeof(*bus));
     bus->type = MPT_TYPE_BUS;
     memcpy(bus->bustype, "ISA   ", sizeof(bus->bustype));
-- 
1.6.2.5


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From mch at virtutech.com  Tue Nov  3 12:51:17 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:17 +0100
Subject: [PATCH 3/9] Remove device access from loop to make it faster when running in emulation.
Message-ID: <mailman.4004.1355071652.16123.coreboot@coreboot.org>

---
 src/smp.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index a912857..71b0da8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -97,11 +97,13 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT)
+    if (CONFIG_COREBOOT) {
         msleep(10);
-    else
-        while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs))
-            ;
+    } else {
+        u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
+        while (cmos_smp_count + 1 != readl(&CountCPUs))
+             ;
+    }
 
     // Restore memory.
     *(u64*)BUILD_AP_BOOT_ADDR = old;
-- 
1.6.2.5


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From mch at virtutech.com  Tue Nov  3 12:51:45 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Tue, 3 Nov 2009 12:51:45 +0100
Subject: [PATCH 4/9] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
Message-ID: <mailman.4005.1355071652.16123.coreboot@coreboot.org>

---
 src/smp.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/smp.c b/src/smp.c
index 71b0da8..b0852f8 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -13,6 +13,8 @@
 
 #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
 #define APIC_SVR     ((u8*)BUILD_APIC_ADDR + 0x0F0)
+#define APIC_LINT0   ((u8*)BUILD_APIC_ADDR + 0x350)
+#define APIC_LINT1   ((u8*)BUILD_APIC_ADDR + 0x360)
 
 #define APIC_ENABLED 0x0100
 
@@ -91,6 +93,12 @@ smp_probe(void)
     u32 val = readl(APIC_SVR);
     writel(APIC_SVR, val | APIC_ENABLED);
 
+    /* Set LINT0 as Ext_INT, level triggered */
+    writel(APIC_LINT0, 0x8700);
+
+    /* Set LINT1 as NMI, level triggered */
+    writel(APIC_LINT1, 0x8400);
+
     // broadcast SIPI
     writel(APIC_ICR_LOW, 0x000C4500);
     u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 10:20:34 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:20:34 +0100
Subject: [PATCH 5/9] Add MPS entries for LINT interrupts.
Message-ID: <mailman.4006.1355071652.16123.coreboot@coreboot.org>

---
 src/mptable.c |   23 +++++++++++++++++++++--
 src/mptable.h |    1 +
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/mptable.c b/src/mptable.c
index 0c07cfb..b93d50a 100644
--- a/src/mptable.c
+++ b/src/mptable.c
@@ -31,7 +31,7 @@ mptable_init(void)
                   + sizeof(struct mpt_cpu) * MaxCountCPUs
                   + sizeof(struct mpt_bus)
                   + sizeof(struct mpt_ioapic)
-                  + sizeof(struct mpt_intsrc) * 16);
+                  + sizeof(struct mpt_intsrc) * 18);
     struct mptable_config_s *config = malloc_fseg(length);
     struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating));
     if (!config || !floating) {
@@ -90,7 +90,7 @@ mptable_init(void)
         }
     }
 
-    config->entrycount = actual_cpu_count + 2 + 16;
+    config->entrycount = actual_cpu_count + 2 + 16 + 2;
 
     /* isa bus */
     struct mpt_bus *bus = (void*)&cpus[actual_cpu_count];
@@ -127,6 +127,25 @@ mptable_init(void)
         intsrc++;
     }
 
+    /* Local interrupt assignment */
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 3; /* ExtINT */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 0; /* LINTIN0 */
+    intsrc++;
+
+    intsrc->type = MPT_TYPE_LOCAL_INT;
+    intsrc->irqtype = 1; /* NMI */
+    intsrc->irqflag = 0; /* PO, EL default */
+    intsrc->srcbus = 0;
+    intsrc->srcbusirq = 0;
+    intsrc->dstapic = 0; /* BSP == APIC #0 */
+    intsrc->dstirq = 1; /* LINTIN1 */
+    intsrc++;
+
     // Set checksum.
     config->length = (void*)intsrc - (void*)config;
     config->checksum -= checksum(config, config->length);
diff --git a/src/mptable.h b/src/mptable.h
index 4c4d52f..c4e3c51 100644
--- a/src/mptable.h
+++ b/src/mptable.h
@@ -38,6 +38,7 @@ struct mptable_config_s {
 #define MPT_TYPE_BUS 1
 #define MPT_TYPE_IOAPIC 2
 #define MPT_TYPE_INTSRC 3
+#define MPT_TYPE_LOCAL_INT 4
 
 struct mpt_cpu {
     u8 type;
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 10:23:26 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:23:26 +0100
Subject: [PATCH 6/9] Properly mask value for MTRR mask.
Message-ID: <mailman.4007.1355071652.16123.coreboot@coreboot.org>

---
 src/mtrr.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mtrr.c b/src/mtrr.c
index a9cd5f7..6bd0dba 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -29,7 +29,7 @@ void mtrr_setup(void)
     if (CONFIG_COREBOOT)
         return;
 
-    u32 eax, ebx, ecx, cpuid_features;
+    u32 eax, ebx, ecx, edx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
     if (!(cpuid_features & CPUID_MTRR))
         return;
@@ -73,6 +73,16 @@ void mtrr_setup(void)
     wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
     wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
-    wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
+
+    int phys_bits = 36;
+    cpuid(0x80000000u, &eax, &ebx, &ecx, &edx);
+    if (eax >= 0x80000008) {
+            /* Get physical bits from leaf 0x80000008 (if available) */
+            cpuid(0x80000008u, &eax, &ebx, &ecx, &edx);
+            phys_bits = eax & 0xff;
+    }
+    u64 phys_mask = ((1ull << phys_bits) - 1);
+    wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800);
+
     wrmsr_smp(MSR_MTRRdefType, 0xc06);
 }
-- 
1.6.2.5


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From mch at virtutech.com  Thu Nov  5 10:25:05 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:25:05 +0100
Subject: [PATCH 7/9] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
Message-ID: <mailman.4008.1355071652.16123.coreboot@coreboot.org>

---
 src/config.h |    3 +++
 src/shadow.c |   55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 0 deletions(-)

diff --git a/src/config.h b/src/config.h
index 3033133..f2c08ff 100644
--- a/src/config.h
+++ b/src/config.h
@@ -189,4 +189,7 @@
 #define DEBUG_HDL_pmm 1
 #define DEBUG_thread 1
 
+/* Options for running on the Virtutech Simics x86-440bx machine model */
+#define VIRTUTECH_PC_SHADOW 0
+
 #endif // config.h
diff --git a/src/shadow.c b/src/shadow.c
index f0f97c5..4b7f15c 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -9,6 +9,7 @@
 #include "pci.h" // pci_config_writeb
 #include "config.h" // CONFIG_*
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "ioport.h" // outb
 
 // Test if 'addr' is in the range from 'start'..'start+size'
 #define IN_RANGE(addr, start, size) ({   \
@@ -21,6 +22,40 @@
 // On the emulators, the bios at 0xf0000 is also at 0xffff0000
 #define BIOS_SRC_ADDR 0xffff0000
 
+#if VIRTUTECH_PC_SHADOW
+
+#define Read_Only 1
+#define Write_Only 2
+#define Read_Write 3
+
+static void modify_shadow(unsigned long start, unsigned long len, int mode)
+{
+    int start_loc = ((int)(start >> 10) - 640) >> 1;
+    int len_remaining = len >> 11;
+    int i;
+    for (i = 0; i < len_remaining; i++) {
+        outb(start_loc + i, 0xfff4);
+        if (mode == Read_Only) {
+            outb(1, 0xfff5);
+        } else if (mode == Read_Write) {
+            outb(3, 0xfff5);
+        } else if (mode == Write_Only) {
+            outb(2, 0xfff5);
+        } else {
+            outb(0, 0xfff5);
+        }
+    }
+}
+
+static void
+__copy_bios(void)
+{
+    // Copy bios.
+    memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
+}
+
+#else
+
 // Enable shadowing and copy bios.
 static void
 __make_bios_writable(u16 bdf)
@@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf)
     memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
 }
 
+#endif // VIRTUTECH_PC_SHADOW
+
 // Make the 0xc0000-0x100000 area read/writable.
 void
 make_bios_writable()
@@ -68,6 +105,19 @@ make_bios_writable()
 
     dprintf(3, "enabling shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    /* Read (and execute) from PCI, write to RAM */
+    modify_shadow(0xf0000, 0x10000, Write_Only);
+
+    /* Run the copy from the high address to avoid simulator flushes after each
+       write (the flushes ruin performance) */
+    u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
+    void (*func)(void) = (void*)pos;
+    func();
+
+    /* Keep BIOS read/write */
+    modify_shadow(0xf0000, 0x10000, Read_Write);
+#else
     // Locate chip controlling ram shadowing.
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
@@ -88,6 +138,7 @@ make_bios_writable()
     }
     // Ram already present - just enable writes
     __make_bios_writable(bdf);
+#endif
 }
 
 // Make the BIOS code segment area (0xf0000) read-only.
@@ -99,6 +150,9 @@ make_bios_readonly()
 
     dprintf(3, "locking shadow ram\n");
 
+#if VIRTUTECH_PC_SHADOW
+    modify_shadow(0xf0000, 0x10000, Read_Only);
+#else
     int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
     if (bdf < 0) {
         dprintf(1, "Unable to lock ram - bridge not found\n");
@@ -122,4 +176,5 @@ make_bios_readonly()
 
     // Write protect 0xf0000-0x100000
     pci_config_writeb(bdf, 0x59, 0x10);
+#endif
 }
-- 
1.6.2.5


--------------020508030901070003090208
Content-Type: text/x-patch;
 name="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
 filename*0="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc";
 filename*1="h"


From mch at virtutech.com  Thu Nov  5 10:26:40 2009
From: mch at virtutech.com (Magnus Christensson)
Date: Thu, 5 Nov 2009 10:26:40 +0100
Subject: [PATCH 8/9] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
Message-ID: <mailman.4009.1355071652.16123.coreboot@coreboot.org>

---
 src/config.h |    1 +
 src/smp.c    |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/config.h b/src/config.h
index f2c08ff..e9d63e7 100644
--- a/src/config.h
+++ b/src/config.h
@@ -191,5 +191,6 @@
 
 /* Options for running on the Virtutech Simics x86-440bx machine model */
 #define VIRTUTECH_PC_SHADOW 0
+#define USE_CMOS_BIOS_SMP_COUNT 1
 
 #endif // config.h
diff --git a/src/smp.c b/src/smp.c
index b0852f8..caec5f1 100644
--- a/src/smp.c
+++ b/src/smp.c
@@ -105,7 +105,7 @@ smp_probe(void)
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
     // Wait for other CPUs to process the SIPI.
-    if (CONFIG_COREBOOT) {
+    if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) {
         msleep(10);
     } else {
         u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
-- 
1.6.2.5


--------------020508030901070003090208--



From stepan at coresystems.de  Thu Nov  5 16:00:06 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 05 Nov 2009 16:00:06 +0100
Subject: [coreboot] [PATCH] cleanup x86emu without yabel
Message-ID: <4AF2E876.6000102@coresystems.de>

See patch

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From rminnich at gmail.com  Thu Nov  5 17:03:06 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 08:03:06 -0800
Subject: [coreboot] [RFC] network console for coreboot and ethernet
	support for SerialICE
In-Reply-To: <4AF29BC0.5070107@assembler.cz>
References: <4AF29BC0.5070107@assembler.cz>
Message-ID: <13426df10911050803he2751k61ebc033d792ed71@mail.gmail.com>

I think it's a pretty neat idea ... seems like it might work :-)

ron



From mylesgw at gmail.com  Thu Nov  5 17:17:35 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 10:17:35 -0600
Subject: [coreboot] CPU Frequency setting
In-Reply-To: <SNT129-W412CB9A97EA7458D7A97DEA3B10@phx.gbl>
References: <SNT129-W412CB9A97EA7458D7A97DEA3B10@phx.gbl>
Message-ID: <2831fecf0911050817q13403927q9aeb63451ec7d982@mail.gmail.com>

On Wed, Nov 4, 2009 at 11:32 AM, Peter Joanes <pjoanes at hotmail.com> wrote:

>  I would like to ask whether it might be possible to modify the S2882
> Coreboot config so that it includes a way to set the processor frequency.
>
It's definitely possible.  The quickest way would probably to insert the
code in src/mainboard/tyan/s2882/cache_as_ram_auto.c before the ht_reset.

Thanks,
Myles
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From rminnich at gmail.com  Thu Nov  5 17:33:47 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 08:33:47 -0800
Subject: [coreboot] GeodeLX RAM initialisation issue
In-Reply-To: <4AF2C840.5050104@traverse.com.au>
References: <4AF2C840.5050104@traverse.com.au>
Message-ID: <13426df10911050833w288ab0f2qd440185183b4b16f@mail.gmail.com>

This is a new one. We've never seen it on the geodes we have.

It is possible your geodes are newer and there is something we are
doing wrong for the part.

It is also possible that a "reset" from linux on coreboot is not
"complete" enough, as it might be on the embedded bios. In my case I
would start there.

ron



From mylesgw at gmail.com  Thu Nov  5 17:42:43 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 09:42:43 -0700
Subject: [coreboot] [PATCH] cleanup x86emu without yabel
In-Reply-To: <4AF2E876.6000102@coresystems.de>
References: <4AF2E876.6000102@coresystems.de>
Message-ID: <38E7F65DD95A41D180ECF8B3B4287AE7@chimp>


+#ifdef CONFIG_COREBOOT_V2
+		dev = dev_find_device(X86_DX, X86_CX, dev);

This looks wrong.  I know it really isn't part of the patch, but isn't
CONFIG_COREBOOT_V2 always defined?  I guess it isn't in v3...

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles





From stepan at coresystems.de  Thu Nov  5 17:57:59 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 05 Nov 2009 17:57:59 +0100
Subject: [coreboot] [PATCH] cleanup x86emu without yabel
In-Reply-To: <38E7F65DD95A41D180ECF8B3B4287AE7@chimp>
References: <4AF2E876.6000102@coresystems.de>
	<38E7F65DD95A41D180ECF8B3B4287AE7@chimp>
Message-ID: <4AF30417.3010509@coresystems.de>

Myles Watson wrote:
> +#ifdef CONFIG_COREBOOT_V2
> +		dev = dev_find_device(X86_DX, X86_CX, dev);
>
> This looks wrong.  I know it really isn't part of the patch, but isn't
> CONFIG_COREBOOT_V2 always defined?  I guess it isn't in v3...
It should be always defined in v2, and never in v2... Not sure if things
changed meanwhile, but that part of the code is not new, just copied..

We could make v2 more similar to v3

svn mv src/include/console/* src/include

and

s/dev_find_device/dev_find_pci_device/

if you feel like we should drop the define.

(Or we just drop the define since x86emu is no longer shared with v3)

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From mylesgw at gmail.com  Thu Nov  5 18:02:17 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 11:02:17 -0600
Subject: [coreboot] [PATCH] cleanup x86emu without yabel
In-Reply-To: <4AF30417.3010509@coresystems.de>
References: <4AF2E876.6000102@coresystems.de>
	<38E7F65DD95A41D180ECF8B3B4287AE7@chimp>
	<4AF30417.3010509@coresystems.de>
Message-ID: <2831fecf0911050902k4b7c3e2dy8e86169a4d7a4815@mail.gmail.com>

On Thu, Nov 5, 2009 at 10:57 AM, Stefan Reinauer <stepan at coresystems.de>wrote:

> Myles Watson wrote:
> > +#ifdef CONFIG_COREBOOT_V2
> > +             dev = dev_find_device(X86_DX, X86_CX, dev);
> >
> > This looks wrong.  I know it really isn't part of the patch, but isn't
> > CONFIG_COREBOOT_V2 always defined?  I guess it isn't in v3...
> It should be always defined in v2, and never in v2... Not sure if things
> changed meanwhile, but that part of the code is not new, just copied..
>
That's what I meant by "not part of the patch"


> We could make v2 more similar to v3
>
> svn mv src/include/console/* src/include
>
> and
>
> s/dev_find_device/dev_find_pci_device/
>
> if you feel like we should drop the define.
>
> (Or we just drop the define since x86emu is no longer shared with v3)
>
Either way is fine.

Thanks,
Myles
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From marcj303 at gmail.com  Thu Nov  5 18:10:54 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 5 Nov 2009 10:10:54 -0700
Subject: [coreboot] GeodeLX RAM initialisation issue
In-Reply-To: <13426df10911050833w288ab0f2qd440185183b4b16f@mail.gmail.com>
References: <4AF2C840.5050104@traverse.com.au>
	<13426df10911050833w288ab0f2qd440185183b4b16f@mail.gmail.com>
Message-ID: <534e5dc20911050910r765107e8g11f17e215af5437@mail.gmail.com>

On Thu, Nov 5, 2009 at 9:33 AM, ron minnich <rminnich at gmail.com> wrote:
> This is a new one. We've never seen it on the geodes we have.
>
> It is possible your geodes are newer and there is something we are
> doing wrong for the part.
>
> It is also possible that a "reset" from linux on coreboot is not
> "complete" enough, as it might be on the embedded bios. In my case I
> would start there.
>

Good point. The bios has a number of ways to cause a reset that
coreboot doesn't have. I don't know how many different ways Linux will
attempt a reset. If it always works when you hit the reset button, you
will need to look at the software reset path.

When linux does the reset, is the coreboot output the same? Does it do
the "Resetting the processor"?

A few things you can look at are a memory test prior to the wbind and
you can also try dumping the MC registers to see if they are getting
setup differently on the failing case.

Marc

-- 
http://marcjonesconsulting.com



From svn at coreboot.org  Thu Nov  5 18:24:03 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 17:24:03 +0000
Subject: [coreboot] [v2] r4915 - trunk/util/x86emu
Message-ID: <mailman.4010.1355071652.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 17:24:03 +0000 (Thu, 05 Nov 2009)
New Revision: 4915

Removed:
   trunk/util/x86emu/pcbios/
Modified:
   trunk/util/x86emu/Config.lb
   trunk/util/x86emu/Makefile
   trunk/util/x86emu/Makefile.inc
   trunk/util/x86emu/biosemu.c
Log:
biosemu (non-yabel) cleanup
* Drop pcbios folder that only exists for a single function
* include int1a handler in biosemu.c
* Wipe a lot of dead code, and set up F segment correctly
* include return value check from yabel.

On the long run we should teach yabel to be able to run with a reduced feature
set, ie. no emulation of (almost) all system hardware. Then we could drop the
non-yabel x86emu.
But for now this patch cleans up the non-yabel biosemu.c to a state where it's
not all that ugly anymore..

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Myles Watson <mylesgw at gmail.com>



Modified: trunk/util/x86emu/Config.lb
===================================================================
--- trunk/util/x86emu/Config.lb	2009-11-05 12:44:50 UTC (rev 4914)
+++ trunk/util/x86emu/Config.lb	2009-11-05 17:24:03 UTC (rev 4915)
@@ -11,7 +11,6 @@
     object x86_asm.S
   else
     object biosemu.o
-    dir pcbios
     dir x86emu
   end
 end

Modified: trunk/util/x86emu/Makefile
===================================================================
--- trunk/util/x86emu/Makefile	2009-11-05 12:44:50 UTC (rev 4914)
+++ trunk/util/x86emu/Makefile	2009-11-05 17:24:03 UTC (rev 4915)
@@ -22,7 +22,7 @@
 
 X86EMU_SRC  = debug.c decode.c fpu.c ops.c ops2.c prim_ops.c sys.c
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
-BIOSEMU_SRC = biosemu.c pcbios/pcibios.c
+BIOSEMU_SRC = biosemu.c
 endif
 
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL),y)

Modified: trunk/util/x86emu/Makefile.inc
===================================================================
--- trunk/util/x86emu/Makefile.inc	2009-11-05 12:44:50 UTC (rev 4914)
+++ trunk/util/x86emu/Makefile.inc	2009-11-05 17:24:03 UTC (rev 4915)
@@ -20,7 +20,6 @@
 
 subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += x86emu
 obj-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += biosemu.o
-subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += pcbios
 
 obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86.o
 obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86_asm.o

Modified: trunk/util/x86emu/biosemu.c
===================================================================
--- trunk/util/x86emu/biosemu.c	2009-11-05 12:44:50 UTC (rev 4914)
+++ trunk/util/x86emu/biosemu.c	2009-11-05 17:24:03 UTC (rev 4915)
@@ -36,6 +36,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+#include <string.h>
 #ifdef CONFIG_COREBOOT_V2
 #include <arch/io.h>
 #include <console/console.h>
@@ -47,11 +48,40 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-
 #include <x86emu/x86emu.h>
+#include "x86emu/prim_ops.h"
 
-#include "pcbios/pcibios.h"
+#define DATA_SEGMENT 0x2000
+#define STACK_SEGMENT 0x1000	//1000:xxxx
+#define STACK_START_OFFSET 0xfffe
+#define INITIAL_EBDA_SEGMENT 0xF600	// segment of the Extended BIOS Data Area
+#define INITIAL_EBDA_SIZE 0x400	// size of the EBDA (at least 1KB!! since size is stored in KB!)
 
+enum {
+	PCI_BIOS_PRESENT	= 0xB101,
+	FIND_PCI_DEVICE		= 0xB102,
+	FIND_PCI_CLASS_CODE	= 0xB103,
+	GENERATE_SPECIAL_CYCLE	= 0xB106,
+	READ_CONFIG_BYTE	= 0xB108,
+	READ_CONFIG_WORD	= 0xB109,
+	READ_CONFIG_DWORD	= 0xB10A,
+	WRITE_CONFIG_BYTE	= 0xB10B,
+	WRITE_CONFIG_WORD	= 0xB10C,
+	WRITE_CONFIG_DWORD	= 0xB10D,
+	GET_IRQ_ROUTING_OPTIONS	= 0xB10E,
+	SET_PCI_IRQ		= 0xB10F
+};
+
+enum {
+	SUCCESSFUL		= 0x00,
+	FUNC_NOT_SUPPORTED	= 0x81,
+	BAD_VENDOR_ID		= 0x83,
+	DEVICE_NOT_FOUND	= 0x86,
+	BAD_REGISTER_NUMBER	= 0x87,
+	SET_FAILED		= 0x88,
+	BUFFER_TOO_SMALL	= 0x89
+};
+
 #define MEM_WB(where, what) wrb(where, what)
 #define MEM_WW(where, what) wrw(where, what)
 #define MEM_WL(where, what) wrl(where, what)
@@ -60,45 +90,8 @@
 #define MEM_RW(where) rdw(where)
 #define MEM_RL(where) rdl(where)
 
-u8 x_inb(u16 port);
-u16 x_inw(u16 port);
-void x_outb(u16 port, u8 val);
-void x_outw(u16 port, u16 val);
-u32 x_inl(u16 port);
-void x_outl(u16 port, u32 val);
-
-//
-void X86EMU_setMemBase(void *base, size_t size);
-
-/* general software interrupt handler */
-u32 getIntVect(int num)
+static u8 biosemu_inb(u16 port)
 {
-	return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4);
-}
-
-/* FIXME: There is already a push_word() in the emulator */
-void pushw(u16 val)
-{
-	X86_ESP -= 2;
-	MEM_WW(((u32) X86_SS << 4) + X86_SP, val);
-}
-
-int run_bios_int(int num)
-{
-	u32 eflags;
-
-	eflags = X86_EFLAGS;
-	pushw(eflags);
-	pushw(X86_CS);
-	pushw(X86_IP);
-	X86_CS = MEM_RW((num << 2) + 2);
-	X86_IP = MEM_RW(num << 2);
-
-	return 1;
-}
-
-u8 x_inb(u16 port)
-{
 	u8 val;
 
 	val = inb(port);
@@ -110,7 +103,7 @@
 	return val;
 }
 
-u16 x_inw(u16 port)
+static u16 biosemu_inw(u16 port)
 {
 	u16 val;
 
@@ -122,7 +115,7 @@
 	return val;
 }
 
-u32 x_inl(u16 port)
+static u32 biosemu_inl(u16 port)
 {
 	u32 val;
 
@@ -134,7 +127,7 @@
 	return val;
 }
 
-void x_outb(u16 port, u8 val)
+static void biosemu_outb(u16 port, u8 val)
 {
 #ifdef CONFIG_DEBUG
 	if (port != 0x43)
@@ -143,7 +136,7 @@
 	outb(val, port);
 }
 
-void x_outw(u16 port, u16 val)
+static void biosemu_outw(u16 port, u16 val)
 {
 #ifdef CONFIG_DEBUG
 	printk("outw(0x%04x, 0x%04x)\n", val, port);
@@ -151,7 +144,7 @@
 	outw(val, port);
 }
 
-void x_outl(u16 port, u32 val)
+static void biosemu_outl(u16 port, u32 val)
 {
 #ifdef CONFIG_DEBUG
 	printk("outl(0x%08x, 0x%04x)\n", val, port);
@@ -159,23 +152,245 @@
 	outl(val, port);
 }
 
-X86EMU_pioFuncs myfuncs = {
-	x_inb, x_inw, x_inl,
-	x_outb, x_outw, x_outl
+static X86EMU_pioFuncs biosemu_piofuncs = {
+	biosemu_inb,  biosemu_inw,  biosemu_inl,
+	biosemu_outb, biosemu_outw, biosemu_outl
 };
 
+/* Interrupt Handlers */
 
+static int int15_handler(void)
+{
+	/* This int15 handler is VIA Tech. and Intel specific. Other chipsets need other
+	 * handlers. The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 */
+	switch (X86_AX) {
+	case 0x5f19:
+		X86_EFLAGS |= FB_CF;	/* set carry flag */
+		break;
+	case 0x5f18:
+		X86_EAX = 0x5f;
+		// MCLK = 133, 32M frame buffer, 256 M main memory
+		X86_EBX = 0x545;
+		X86_ECX = 0x060;
+		X86_EFLAGS &= ~FB_CF;
+		break;
+	case 0x5f00:
+		X86_EAX = 0x8600;
+		X86_EFLAGS |= FB_CF;	/* set carry flag */
+		break;
+	case 0x5f01:
+		X86_EAX = 0x5f;
+		X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
+		X86_EFLAGS &= ~FB_CF;
+		break;
+	case 0x5f02:
+		X86_EAX = 0x5f;
+		X86_EBX = (X86_EBX & 0xffff0000) | 2;
+		X86_ECX = (X86_ECX & 0xffff0000) | 0x401;  // PAL + crt only
+		X86_EDX = (X86_EDX & 0xffff0000) | 0;  // TV Layout - default
+		X86_EFLAGS &= ~FB_CF;
+		break;
+	case 0x5f0f:
+		X86_EAX = 0x860f;
+		X86_EFLAGS |= FB_CF;	/* set carry flag */
+		break;
+	/* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
 
+	case 0x5f35:
+		X86_EAX = 0x5f;
+		X86_ECX = BOOT_DISPLAY_DEFAULT;
+		X86_EFLAGS &= ~FB_CF;
+		break;
+	case 0x5f40:
+		X86_EAX = 0x5f;
+		X86_ECX = 3; // This is mainboard specific
+		printk("DISPLAY=%x\n", X86_ECX);
+		X86_EFLAGS &= ~FB_CF;
+		break;
+	default:
+		printk("Unknown INT15 function %04x!\n", X86_AX);
+		X86_EFLAGS |= FB_CF;	/* set carry flag */
+	}
+
+	return 1;
+}
+
+static int int1a_handler(void)
+{
+	int ret = 0;
+	struct device *dev = 0;
+
+	switch (X86_AX) {
+	case PCI_BIOS_PRESENT:
+		X86_AH	= 0x00;		/* no config space/special cycle support */
+		X86_AL	= 0x01;		/* config mechanism 1 */
+		X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24;
+		X86_EBX = 0x0210;	/* Version 2.10 */
+		X86_ECX = 0xFF00;	/* FIXME: Max bus number */
+		X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+		ret = 1;
+		break;
+	case FIND_PCI_DEVICE:
+		/* FIXME: support SI != 0 */
+#ifdef CONFIG_COREBOOT_V2
+		dev = dev_find_device(X86_DX, X86_CX, dev);
+#else
+		dev = dev_find_pci_device(X86_DX, X86_CX, dev);
+#endif
+		if (dev != 0) {
+			X86_BH = dev->bus->secondary;
+			X86_BL = dev->path.pci.devfn;
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */
+			ret = 0;
+		}
+		break;
+	case FIND_PCI_CLASS_CODE:
+		/* FixME: support SI != 0 */
+		dev = dev_find_class(X86_ECX, dev);
+		if (dev != 0) {
+			X86_BH = dev->bus->secondary;
+			X86_BL = dev->path.pci.devfn;
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */
+			ret = 0;
+		}
+		break;
+	case READ_CONFIG_BYTE:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			X86_CL = pci_read_config8(dev, X86_DI);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	case READ_CONFIG_WORD:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			X86_CX = pci_read_config16(dev, X86_DI);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	case READ_CONFIG_DWORD:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			X86_ECX = pci_read_config32(dev, X86_DI);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	case WRITE_CONFIG_BYTE:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			pci_write_config8(dev, X86_DI, X86_CL);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	case WRITE_CONFIG_WORD:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			pci_write_config16(dev, X86_DI, X86_CX);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	case WRITE_CONFIG_DWORD:
+		dev = dev_find_slot(X86_BH, X86_BL);
+		if (dev != 0) {
+			pci_write_config16(dev, X86_DI, X86_ECX);
+			X86_AH = SUCCESSFUL;
+			X86_EFLAGS &= ~FB_CF;	/* clear carry flag */
+			ret = 1;
+		} else {
+			X86_AH = DEVICE_NOT_FOUND;
+			X86_EFLAGS |= FB_CF;	/* set carry flag */	
+			ret = 0;
+		}
+		break;
+	default:
+		X86_AH = FUNC_NOT_SUPPORTED;
+		X86_EFLAGS |= FB_CF; 
+		break;
+	}
+
+	return ret;
+}
+
 /* Interrupt multiplexer */
 
-void do_int(int num)
+/* Find base address of interrupt handler */
+static u32 getIntVect(int num)
 {
+	return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4);
+}
+
+static int run_bios_int(int num)
+{
+	u32 eflags;
+
+	eflags = X86_EFLAGS;
+	push_word(eflags);
+	push_word(X86_CS);
+	push_word(X86_IP);
+	X86_CS = MEM_RW((num << 2) + 2);
+	X86_IP = MEM_RW(num << 2);
+
+	return 1;
+}
+
+static void do_int(int num)
+{
 	int ret = 0;
 
-	printk("int%x vector at %x\n", num, getIntVect(num));
+	printk("int%x (AX=%04x) vector at %x\n", num, X86_AX, getIntVect(num));
 
 	switch (num) {
-#ifndef _PC
 	case 0x10:
 	case 0x42:
 	case 0x6D:
@@ -188,9 +403,8 @@
 			ret = 1;
 		}
 		break;
-#endif
 	case 0x15:
-		//ret = int15_handler();
+		ret = int15_handler();
 		ret = 1;
 		break;
 	case 0x16:
@@ -198,7 +412,7 @@
 		ret = 0;
 		break;
 	case 0x1A:
-		ret = pcibios_handler();
+		ret = int1a_handler();
 		ret = 1;
 		break;
 	case 0xe6:
@@ -214,159 +428,124 @@
 
 }
 
-#if 0
-#define SYS_BIOS 0xf0000
 /*
  * here we are really paranoid about faking a "real"
  * BIOS. Most of this information was pulled from
  * dosemu.
  */
-#if 0
-void setup_int_vect(void)
+static void setup_system_bios(void)
 {
 	int i;
 
-	/* let the int vects point to the SYS_BIOS seg */
-	for (i = 0; i < 0x80; i++) {
-		MEM_WW(i << 2, 0);
-		MEM_WW((i << 2) + 2, SYS_BIOS >> 4);
-	}
+	/* Set up Interrupt Vectors. The IVT starts at 0x0000:0x0000
+	 * Additionally, we put some stub code into the F segment for
+	 * those pesky little buggers that jmp to the hard coded addresses
+	 * instead of calling int XX. This stub code looks like this
+	 *
+	 *  CD XX	int 0xXX
+	 *  C3		ret
+	 *  F4		hlt
+	 */
 
-	reset_int_vect();
-
-	/* font tables default location (int 1F) */
-	MEM_WW(0x1f << 2, 0xfa6e);
+	/* int 05 default location (Bound Exceeded) */
+	MEM_WL(0x05 << 2, 0xf000ff54);
+	MEM_WL(0xfff54, 0xf4c305cd);
+	/* int 08 default location (Double Fault) */
+	MEM_WL(0x08 << 2, 0xf000fea5);
+	MEM_WL(0xffea5, 0xf4c308cd);
+	/* int 0E default location (Page Fault) */
+	MEM_WL(0x0e << 2, 0xf000ef57);
+	MEM_WL(0xfef57, 0xf4c30ecd);
+	/* int 10 default location */
+	MEM_WL(0x10 << 2, 0xf000f065);
+	MEM_WL(0xff065, 0xf4c310cd);
 	/* int 11 default location (Get Equipment Configuration) */
-	MEM_WW(0x11 << 2, 0xf84d);
+	MEM_WL(0x11 << 2, 0xf000f84d);
+	MEM_WL(0xff84d, 0xf4c311cd);
 	/* int 12 default location (Get Conventional Memory Size) */
-	MEM_WW(0x12 << 2, 0xf841);
+	MEM_WL(0x12 << 2, 0xf000f841);
+	MEM_WL(0xff841, 0xf4c312cd);
+	/* int 13 default location (Disk) */
+	MEM_WL(0x13 << 2, 0xf000ec59);
+	MEM_WL(0xfec59, 0xf4c313cd);
+	/* int 14 default location (Disk) */
+	MEM_WL(0x14 << 2, 0xf000e739);
+	MEM_WL(0xfe739, 0xf4c314cd);
 	/* int 15 default location (I/O System Extensions) */
-	MEM_WW(0x15 << 2, 0xf859);
+	MEM_WL(0x15 << 2, 0xf000f859);
+	MEM_WL(0xf859, 0xf4c315cd);
+	/* int 16 default location */
+	MEM_WL(0x16 << 2, 0xf000e82e);
+	MEM_WL(0xfe82e, 0xf4c316cd);
+	/* int 17 default location (Parallel Port) */
+	MEM_WL(0x17 << 2, 0xf000efd2);
+	MEM_WL(0xfefd2, 0xf4c317cd);
 	/* int 1A default location (RTC, PCI and others) */
-	MEM_WW(0x1a << 2, 0xff6e);
-	/* int 05 default location (Bound Exceeded) */
-	MEM_WW(0x05 << 2, 0xff54);
-	/* int 08 default location (Double Fault) */
-	MEM_WW(0x08 << 2, 0xfea5);
-	/* int 13 default location (Disk) */
-	MEM_WW(0x13 << 2, 0xec59);
-	/* int 0E default location (Page Fault) */
-	MEM_WW(0x0e << 2, 0xef57);
-	/* int 17 default location (Parallel Port) */
-	MEM_WW(0x17 << 2, 0xefd2);
-	/* fdd table default location (int 1e) */
-	MEM_WW(0x1e << 2, 0xefc7);
+	MEM_WL(0x1a << 2, 0xf000fe6e);
+	MEM_WL(0xffe6e, 0xf4c31acd);
+	/* int 1E default location (FDD table) */
+	MEM_WL(0x1e << 2, 0xf000efc7);
+	MEM_WL(0xfefc7, 0xf4c31ecd);
+	/* font tables default location (int 1F) */
+	MEM_WL(0x1f << 2, 0xf000fa6e);
+	MEM_WL(0xffa6e, 0xf4c31fcd);
+	/* int 42 default location */
+	MEM_WL(0x42 << 2, 0xf000f065);
+	/* int 6D default location */
+	MEM_WL(0x6D << 2, 0xf000f065);
 
-	/* Set Equipment flag to VGA */
-	i = MEM_RB(0x0410) & 0xCF;
-	MEM_WB(0x0410, i);
-	/* XXX Perhaps setup more of the BDA here.  See also int42(0x00). */
-}
+	/* Clear EBDA */
+	for (i=(INITIAL_EBDA_SEGMENT << 4); 
+		i<(INITIAL_EBDA_SEGMENT << 4) + INITIAL_EBDA_SIZE; i++)
+		MEM_WB(i, 0);
+	/* at offset 0h in EBDA is the size of the EBDA in KB */
+	MEM_WW((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024);
 
-int setup_system_bios(void *base_addr)
-{
-	char *base = (char *) base_addr;
+	/* Clear BDA */
+	for (i=0x400; i<0x500; i+=4)
+		MEM_WL(i, 0);
 
-	/*
-	 * we trap the "industry standard entry points" to the BIOS
-	 * and all other locations by filling them with "hlt"
-	 * TODO: implement hlt-handler for these
-	 */
-	memset(base, 0xf4, 0x10000);
+	/* Set up EBDA */
+	MEM_WW(0x40e, INITIAL_EBDA_SEGMENT);
 
-	/* set bios date */
-	//strcpy(base + 0x0FFF5, "06/11/99");
-	/* set up eisa ident string */
-	//strcpy(base + 0x0FFD9, "PCI_ISA");
-	/* write system model id for IBM-AT */
-	//*((unsigned char *) (base + 0x0FFFE)) = 0xfc;
+	/* Set RAM size to 16MB (fake) */
+	MEM_WW(0x413, 16384);
 
-	return 1;
-}
-#endif
+	// TODO Set up more of BDA here
 
-void reset_int_vect(void)
-{
-	/*
-	 * This table is normally located at 0xF000:0xF0A4.  However, int 0x42,
-	 * function 0 (Mode Set) expects it (or a copy) somewhere in the bottom
-	 * 64kB.  Note that because this data doesn't survive POST, int 0x42 should
-	 * only be used during EGA/VGA BIOS initialisation.
-	 */
-	static const u8 VideoParms[] = {
-		/* Timing for modes 0x00 & 0x01 */
-		0x38, 0x28, 0x2d, 0x0a, 0x1f, 0x06, 0x19, 0x1c,
-		0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
-		/* Timing for modes 0x02 & 0x03 */
-		0x71, 0x50, 0x5a, 0x0a, 0x1f, 0x06, 0x19, 0x1c,
-		0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
-		/* Timing for modes 0x04, 0x05 & 0x06 */
-		0x38, 0x28, 0x2d, 0x0a, 0x7f, 0x06, 0x64, 0x70,
-		0x02, 0x01, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
-		/* Timing for mode 0x07 */
-		0x61, 0x50, 0x52, 0x0f, 0x19, 0x06, 0x19, 0x19,
-		0x02, 0x0d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
-		/* Display page lengths in little endian order */
-		0x00, 0x08,	/* Modes 0x00 and 0x01 */
-		0x00, 0x10,	/* Modes 0x02 and 0x03 */
-		0x00, 0x40,	/* Modes 0x04 and 0x05 */
-		0x00, 0x40,	/* Modes 0x06 and 0x07 */
-		/* Number of columns for each mode */
-		40, 40, 80, 80, 40, 40, 80, 80,
-		/* CGA Mode register value for each mode */
-		0x2c, 0x28, 0x2d, 0x29, 0x2a, 0x2e, 0x1e, 0x29,
-		/* Padding */
-		0x00, 0x00, 0x00, 0x00
-	};
-	int i;
+	/* setup original ROM BIOS Area (F000:xxxx) */
+	const char *date = "06/23/99";
+	for (i = 0; date[i]; i++)
+		MEM_WB(0xffff5 + i, date[i]);
+	/* set up eisa ident string */
+        const char *ident = "PCI_ISA";
+        for (i = 0; ident[i]; i++)
+                MEM_WB(0xfffd9 + i, ident[i]);
 
-	for (i = 0; i < sizeof(VideoParms); i++)
-		MEM_WB(i + (0x1000 - sizeof(VideoParms)), VideoParms[i]);
-	MEM_WW(0x1d << 2, 0x1000 - sizeof(VideoParms));
-	MEM_WW((0x1d << 2) + 2, 0);
-
-	printk(BIOS_DEBUG,"SETUP INT\n");
-	MEM_WW(0x10 << 2, 0xf065);
-	MEM_WW((0x10 << 2) + 2, SYS_BIOS >> 4);
-	MEM_WW(0x42 << 2, 0xf065);
-	MEM_WW((0x42 << 2) + 2, SYS_BIOS >> 4);
-	MEM_WW(0x6D << 2, 0xf065);
-	MEM_WW((0x6D << 2) + 2, SYS_BIOS >> 4);
+        // write system model id for IBM-AT
+        // according to "Ralf Browns Interrupt List" Int15 AH=C0 Table 515,
+        // model FC is the original AT and also used in all DOSEMU Versions.
+        MEM_WB(0xFFFFE, 0xfc);
 }
-#endif
 
+#define BIOSEMU_MEM_BASE 0x00000000
+#define BIOSEMU_MEM_SIZE 0x00100000
 void run_bios(struct device * dev, unsigned long addr)
 {
-#if 1
 	int i;
-	unsigned short initialcs = (addr & 0xF0000) >> 4;
-	unsigned short initialip = (addr + 3) & 0xFFFF;
-	unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn;
-
+	u16 initialcs = (addr & 0xF0000) >> 4;
+	u16 initialip = (addr + 3) & 0xFFFF;
+	u16 devfn = (dev->bus->secondary << 8) | dev->path.pci.devfn;
 	X86EMU_intrFuncs intFuncs[256];
 
-	X86EMU_setMemBase(0, 0x100000);
-	X86EMU_setupPioFuncs(&myfuncs);
+	X86EMU_setMemBase(BIOSEMU_MEM_BASE, BIOSEMU_MEM_SIZE);
+	X86EMU_setupPioFuncs(&biosemu_piofuncs);
 	for (i = 0; i < 256; i++)
 		intFuncs[i] = do_int;
 	X86EMU_setupIntrFuncs(intFuncs);
 
-	{
-		char *date = "01/01/99";
-		for (i = 0; date[i]; i++)
-			wrb(0xffff5 + i, date[i]);
-		wrb(0xffff7, '/');
-		wrb(0xffffa, '/');
-	}
+	setup_system_bios();
 
-	{
-	    /* FixME: move PIT init to its own file */
-	    outb(0x36, 0x43);
-	    outb(0x00, 0x40);
-	    outb(0x00, 0x40);
-	}
-	//setup_int_vect();
-
 	/* cpu setup */
 	X86_AX = devfn ? devfn : 0xff;
 	X86_DX = 0x80;
@@ -374,26 +553,37 @@
 	X86_CS = initialcs;
 
 	/* Initialize stack and data segment */
-	X86_SS = initialcs;
-	X86_SP = 0xfffe;
-	X86_DS = 0x0040;
-	X86_ES = 0x0000;
+	X86_SS = STACK_SEGMENT;
+	X86_SP = STACK_START_OFFSET;;
+	X86_DS = DATA_SEGMENT;
 
 	/* We need a sane way to return from bios
 	 * execution. A hlt instruction and a pointer
 	 * to it, both kept on the stack, will do.
 	 */
-	pushw(0xf4f4);		/* hlt; hlt */
-	pushw(X86_SS);
-	pushw(X86_SP + 2);
+	push_word(0xf4f4);		/* hlt; hlt */
+	push_word(X86_SS);
+	push_word(X86_SP + 2);
 
 #ifdef CONFIG_DEBUG
 	//X86EMU_trace_on();
 #endif
 
-	printk("entering emulator\n");
+	printk("Executing Initialization Vector...\n");
 	X86EMU_exec();
-	printk("exited emulator\n");
+	printk("Option ROM Exit Status: %04x\n", X86_AX);
 
-#endif
+	/* Check whether the stack is "clean" i.e. containing the HLT
+         * instruction we pushed before executing and pointing to the original
+	 * stack address... indicating that the initialization probably was
+	 * successful
+	 */
+	if ((pop_word() == 0xf4f4) && (X86_SS == STACK_SEGMENT)
+	    && (X86_SP == STACK_START_OFFSET)) {
+		printk("Stack is clean, initialization successfull!\n");
+	} else {
+		printk("Stack unclean, initialization probably NOT COMPLETE!!\n");
+		printk("SS:SP = %04x:%04x, expected: %04x:%04x\n",
+			X86_SS, X86_SP, STACK_SEGMENT, STACK_START_OFFSET);
+        }
 }




From mylesgw at gmail.com  Thu Nov  5 18:42:35 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 11:42:35 -0600
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in
	Config.lb/devicetree.cb
In-Reply-To: <2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
References: <20091028195821.GC22827@greenwood>
	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
Message-ID: <2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>

On Wed, Oct 28, 2009 at 2:18 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Wed, Oct 28, 2009 at 1:58 PM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
>
>> See patch.
>>
> I think it would be nice to figure out what we do with the "onboard" device
> at the same time.
>
Ping.  I think this patch is an improvement, but I didn't want the
opportunity to remove more dead code pass by.  Any comments?

 from src/drivers/pci/onboard.c:
>
> static void onboard_enable(device_t dev)
> {
>     struct drivers_pci_onboard_config *conf;
>         conf = dev->chip_info;
>     dev->rom_address = conf->rom_address;
> }
>
> Does it make sense to change ROM handling so that only "onboard" devices
> can have their ROMs run?  That's the way it used to be, right?
>
> Otherwise, maybe we don't need onboard anymore at all?
>

Thanks,
Myles
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From svn at coreboot.org  Thu Nov  5 19:06:43 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 18:06:43 +0000
Subject: [coreboot] [v2] r4916 - trunk/src/arch/i386/boot
Message-ID: <mailman.4011.1355071652.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 18:06:43 +0000 (Thu, 05 Nov 2009)
New Revision: 4916

Modified:
   trunk/src/arch/i386/boot/acpi.c
Log:
if x86emu was running for VGA init a corrupted low table RSDP
is generated in the F segment. Clear the memory before generating an
RSDP to fix the problem.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/src/arch/i386/boot/acpi.c
===================================================================
--- trunk/src/arch/i386/boot/acpi.c	2009-11-05 17:24:03 UTC (rev 4915)
+++ trunk/src/arch/i386/boot/acpi.c	2009-11-05 18:06:43 UTC (rev 4916)
@@ -424,6 +424,7 @@
 
 void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt)
 {
+	memset(rsdp, 0, sizeof(acpi_rsdp_t));
 	memcpy(rsdp->signature, RSDP_SIG, 8);
 	memcpy(rsdp->oem_id, OEM_ID, 6);
 	rsdp->length		= sizeof(acpi_rsdp_t);




From svn at coreboot.org  Thu Nov  5 19:08:16 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 18:08:16 +0000
Subject: [coreboot] [v2] r4917 - in trunk/src/mainboard: intel/d945gclf
	kontron/986lcd-m via/vt8454c
Message-ID: <mailman.4012.1355071652.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-05 18:08:16 +0000 (Thu, 05 Nov 2009)
New Revision: 4917

Modified:
   trunk/src/mainboard/intel/d945gclf/dmi.h
   trunk/src/mainboard/kontron/986lcd-m/dmi.h
   trunk/src/mainboard/via/vt8454c/dmi.h
Log:
fix length field in dmi tables. Newer DMI versions through errors

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/src/mainboard/intel/d945gclf/dmi.h
===================================================================
--- trunk/src/mainboard/intel/d945gclf/dmi.h	2009-11-05 18:06:43 UTC (rev 4916)
+++ trunk/src/mainboard/intel/d945gclf/dmi.h	2009-11-05 18:08:16 UTC (rev 4917)
@@ -1,11 +1,12 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -14,14 +15,15 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 #define DMI_TABLE_SIZE 0x55
 
 static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
 	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
 	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
 	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,

Modified: trunk/src/mainboard/kontron/986lcd-m/dmi.h
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/dmi.h	2009-11-05 18:06:43 UTC (rev 4916)
+++ trunk/src/mainboard/kontron/986lcd-m/dmi.h	2009-11-05 18:08:16 UTC (rev 4917)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,8 +22,8 @@
 #define DMI_TABLE_SIZE 0x55
 
 static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
 	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
 	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
 	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,

Modified: trunk/src/mainboard/via/vt8454c/dmi.h
===================================================================
--- trunk/src/mainboard/via/vt8454c/dmi.h	2009-11-05 18:06:43 UTC (rev 4916)
+++ trunk/src/mainboard/via/vt8454c/dmi.h	2009-11-05 18:08:16 UTC (rev 4917)
@@ -22,8 +22,8 @@
 #define DMI_TABLE_SIZE 0x55
 
 static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
 	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
 	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
 	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,




From stepan at coresystems.de  Thu Nov  5 19:12:54 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 05 Nov 2009 19:12:54 +0100
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries
	in	Config.lb/devicetree.cb
In-Reply-To: <2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
References: <20091028195821.GC22827@greenwood>	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
	<2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
Message-ID: <4AF315A6.10605@coresystems.de>

Myles Watson wrote:
>
>
> On Wed, Oct 28, 2009 at 2:18 PM, Myles Watson <mylesgw at gmail.com
> <mailto:mylesgw at gmail.com>> wrote:
>
>
>
>     On Wed, Oct 28, 2009 at 1:58 PM, Uwe Hermann <uwe at hermann-uwe.de
>     <mailto:uwe at hermann-uwe.de>> wrote:
>
>         See patch.
>
>     I think it would be nice to figure out what we do with the
>     "onboard" device at the same time.
>
> Ping.  I think this patch is an improvement, but I didn't want the
> opportunity to remove more dead code pass by.  Any comments?
Acked-by: Stefan Reinauer <stepan at coresystems.de> for removing all the
->onboard stuff.

>
>      from src/drivers/pci/onboard.c:
>
>     static void onboard_enable(device_t dev)
>     {
>         struct drivers_pci_onboard_config *conf;
>             conf = dev->chip_info;
>         dev->rom_address = conf->rom_address;
>     }
>
>     Does it make sense to change ROM handling so that only "onboard"
>     devices can have their ROMs run?  That's the way it used to be, right?
>
No. Plugin cards (graphics cards) need to have their ROM run, too.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From rminnich at gmail.com  Thu Nov  5 19:18:54 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 10:18:54 -0800
Subject: [coreboot] GeodeLX RAM initialisation issue
In-Reply-To: <534e5dc20911050910r765107e8g11f17e215af5437@mail.gmail.com>
References: <4AF2C840.5050104@traverse.com.au>
	<13426df10911050833w288ab0f2qd440185183b4b16f@mail.gmail.com>
	<534e5dc20911050910r765107e8g11f17e215af5437@mail.gmail.com>
Message-ID: <13426df10911051018s55a3d07akc7bbdbc2695687dc@mail.gmail.com>

On Thu, Nov 5, 2009 at 9:10 AM, Marc Jones <marcj303 at gmail.com> wrote:

> If it always works when you hit the reset button, you
> will need to look at the software reset path.


I like that test!

ron



From mylesgw at gmail.com  Thu Nov  5 19:22:09 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 12:22:09 -0600
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in
	Config.lb/devicetree.cb
In-Reply-To: <4AF315A6.10605@coresystems.de>
References: <20091028195821.GC22827@greenwood>
	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
	<2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
	<4AF315A6.10605@coresystems.de>
Message-ID: <2831fecf0911051022p5e6a4b57na8856c3cec88cee9@mail.gmail.com>

On Thu, Nov 5, 2009 at 12:12 PM, Stefan Reinauer <stepan at coresystems.de>wrote:

> Myles Watson wrote:
> >
> >
> > On Wed, Oct 28, 2009 at 2:18 PM, Myles Watson <mylesgw at gmail.com
> > <mailto:mylesgw at gmail.com>> wrote:
> >
> >
> >
> >     On Wed, Oct 28, 2009 at 1:58 PM, Uwe Hermann <uwe at hermann-uwe.de
> >     <mailto:uwe at hermann-uwe.de>> wrote:
> >
> >         See patch.
> >
> >     I think it would be nice to figure out what we do with the
> >     "onboard" device at the same time.
> >
> > Ping.  I think this patch is an improvement, but I didn't want the
> > opportunity to remove more dead code pass by.  Any comments?
> Acked-by: Stefan Reinauer <stepan at coresystems.de> for removing all the
> ->onboard stuff.
>
> >
> >      from src/drivers/pci/onboard.c:
> >
> >     static void onboard_enable(device_t dev)
> >     {
> >         struct drivers_pci_onboard_config *conf;
> >             conf = dev->chip_info;
> >         dev->rom_address = conf->rom_address;
> >     }
> >
> >     Does it make sense to change ROM handling so that only "onboard"
> >     devices can have their ROMs run?  That's the way it used to be,
> right?
> >
> No. Plugin cards (graphics cards) need to have their ROM run, too.
>
I meant should "onboard" devices be the only ones allowed to have ROMs in
CBFS, but I can see that that wasn't right either.  It just seems like when
we made the change to CBFS we allowed a lot more devices to have ROMs in
CBFS, and I was wondering if that was intentional, or a side-effect.

Thanks,
Myles
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From rminnich at gmail.com  Thu Nov  5 19:25:07 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 10:25:07 -0800
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in
	Config.lb/devicetree.cb
In-Reply-To: <2831fecf0911051022p5e6a4b57na8856c3cec88cee9@mail.gmail.com>
References: <20091028195821.GC22827@greenwood>
	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
	<2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
	<4AF315A6.10605@coresystems.de>
	<2831fecf0911051022p5e6a4b57na8856c3cec88cee9@mail.gmail.com>
Message-ID: <13426df10911051025t6fc3dbc3yb832605a1f741219@mail.gmail.com>

On Thu, Nov 5, 2009 at 10:22 AM, Myles Watson <mylesgw at gmail.com> wrote:

> I meant should "onboard" devices be the only ones allowed to have ROMs in
> CBFS, but I can see that that wasn't right either.? It just seems like when
> we made the change to CBFS we allowed a lot more devices to have ROMs in
> CBFS, and I was wondering if that was intentional, or a side-effect.

from my point of view, it fixed a problem that we also fixed in v3 --
it was really, really hard to have lots of ROM images in coreboot
before we went to LAR/CBFS. So we fixed a shortcoming.

It was incredibly painful (IMHO) to add rom images before we got CBFS.

What's interesting is we can even add (e.g.) an upgraded ROM image to
CBFS that might over-ride the ROM image on an add-in card. Hence you
can "upgrade" the rom image on a card without having to reflash the
card -- just put it in CBFS. We've never done this but the possibility
is there.

ron



From mylesgw at gmail.com  Thu Nov  5 19:49:22 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 12:49:22 -0600
Subject: [coreboot] [PATCH] fix arima/hdama mptable.c
Message-ID: <2831fecf0911051049r65a0a97cxd99821fe7620165d@mail.gmail.com>

Fix hard-coded paths and some warnings.

This patch enables Hugh to boot successfully every time with gcc 3.4, and
most of the time (~29/30) with gcc 4.4.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Thu Nov  5 19:51:21 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 12:51:21 -0600
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in
	Config.lb/devicetree.cb
In-Reply-To: <13426df10911051025t6fc3dbc3yb832605a1f741219@mail.gmail.com>
References: <20091028195821.GC22827@greenwood>
	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
	<2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
	<4AF315A6.10605@coresystems.de>
	<2831fecf0911051022p5e6a4b57na8856c3cec88cee9@mail.gmail.com>
	<13426df10911051025t6fc3dbc3yb832605a1f741219@mail.gmail.com>
Message-ID: <2831fecf0911051051o5b6632f4rd58e09619f266d69@mail.gmail.com>

On Thu, Nov 5, 2009 at 12:25 PM, ron minnich <rminnich at gmail.com> wrote:

> On Thu, Nov 5, 2009 at 10:22 AM, Myles Watson <mylesgw at gmail.com> wrote:
>
> > I meant should "onboard" devices be the only ones allowed to have ROMs in
> > CBFS, but I can see that that wasn't right either.  It just seems like
> when
> > we made the change to CBFS we allowed a lot more devices to have ROMs in
> > CBFS, and I was wondering if that was intentional, or a side-effect.
>
> from my point of view, it fixed a problem that we also fixed in v3 --
> it was really, really hard to have lots of ROM images in coreboot
> before we went to LAR/CBFS. So we fixed a shortcoming.
>
> It was incredibly painful (IMHO) to add rom images before we got CBFS.
>
> What's interesting is we can even add (e.g.) an upgraded ROM image to
> CBFS that might over-ride the ROM image on an add-in card. Hence you
> can "upgrade" the rom image on a card without having to reflash the
> card -- just put it in CBFS. We've never done this but the possibility
> is there.
>

Great.  I just wanted to make sure we didn't need onboard any more.

Uwe:
Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From guy at traverse.com.au  Thu Nov  5 20:55:19 2009
From: guy at traverse.com.au (Guy Ellis)
Date: Fri, 06 Nov 2009 06:55:19 +1100
Subject: [coreboot] Coreboot V2 or V3 for Geode LX800 ?
Message-ID: <4.3.2.7.2.20091106064350.02d2dda0@mail.internode.on.net>

Hi all,

We want to use coreboot on a new product we have designed at work.
The PCB is a variant of  the AMD NAS reference design (LX800 and CS5536)

Coreboot V3 seems to be a fork going nowhere?
Where is the best place to start - Coreboot V2 or V3 for the LX800?

Cheers,

  - Guy.




From mylesgw at gmail.com  Thu Nov  5 21:03:49 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 14:03:49 -0600
Subject: [coreboot] [PATCH] Ron's v3 code ported to v2
Message-ID: <2831fecf0911051203t353010b2ie1287bfd4f9295be@mail.gmail.com>

This was helpful in figuring out what was going on with arima/hdama.  A very
similar one could be written for fam10.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From svn at coreboot.org  Thu Nov  5 21:06:19 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 20:06:19 +0000
Subject: [coreboot] [v2] r4918 - trunk/src/devices
Message-ID: <mailman.4013.1355071652.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-05 20:06:19 +0000 (Thu, 05 Nov 2009)
New Revision: 4918

Modified:
   trunk/src/devices/pci_device.c
Log:
Don't try to set fixed resources.  Trivial.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/src/devices/pci_device.c
===================================================================
--- trunk/src/devices/pci_device.c	2009-11-05 18:08:16 UTC (rev 4917)
+++ trunk/src/devices/pci_device.c	2009-11-05 20:06:19 UTC (rev 4918)
@@ -479,6 +479,11 @@
 		return;
 	}
 
+	/* If this resource is fixed don't worry about it. */
+	if (resource->flags & IORESOURCE_FIXED) {
+		return;
+	}
+
 	/* If I have already stored this resource don't worry about it. */
 	if (resource->flags & IORESOURCE_STORED) {
 		return;




From rminnich at gmail.com  Thu Nov  5 21:44:47 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 12:44:47 -0800
Subject: [coreboot] [PATCH] Ron's v3 code ported to v2
In-Reply-To: <2831fecf0911051203t353010b2ie1287bfd4f9295be@mail.gmail.com>
References: <2831fecf0911051203t353010b2ie1287bfd4f9295be@mail.gmail.com>
Message-ID: <13426df10911051244y955678cw9e63a40de2651aec@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From rminnich at gmail.com  Thu Nov  5 21:45:42 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Nov 2009 12:45:42 -0800
Subject: [coreboot] Coreboot V2 or V3 for Geode LX800 ?
In-Reply-To: <4.3.2.7.2.20091106064350.02d2dda0@mail.internode.on.net>
References: <4.3.2.7.2.20091106064350.02d2dda0@mail.internode.on.net>
Message-ID: <13426df10911051245j3c8390e2q3eda7a503c9c414d@mail.gmail.com>

Get v3 working. Then, back your changes into v2. V3 is really not
under development, but it works very well for geode. But v2 is the
future, since it's evolving to be v4.

ron



From svn at coreboot.org  Thu Nov  5 22:02:36 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  5 Nov 2009 21:02:36 +0000
Subject: [coreboot] [v2] r4919 - trunk/src/northbridge/amd/amdk8
Message-ID: <mailman.4014.1355071652.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-05 21:02:35 +0000 (Thu, 05 Nov 2009)
New Revision: 4919

Added:
   trunk/src/northbridge/amd/amdk8/util.c
Modified:
   trunk/src/northbridge/amd/amdk8/Makefile.inc
   trunk/src/northbridge/amd/amdk8/amdk8.h
Log:
Add debugging utility file for dumping routing registers on K8.

Ported from Ron's code in v3.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/src/northbridge/amd/amdk8/Makefile.inc
===================================================================
--- trunk/src/northbridge/amd/amdk8/Makefile.inc	2009-11-05 20:06:19 UTC (rev 4918)
+++ trunk/src/northbridge/amd/amdk8/Makefile.inc	2009-11-05 21:02:35 UTC (rev 4919)
@@ -3,6 +3,10 @@
 obj-y += get_sblk_pci1234.o
 obj-$(CONFIG_GENERATE_ACPI_TABLES) += amdk8_acpi.o
 
+# Enable this if you want to check the values of the PCI routing registers.
+# Call show_all_routes() anywhere amdk8.h is included.
+#obj-y += util.o
+
 # Not sure what to do with these yet. How did raminit_test even work?
 # Should be a target in -y form.
 #if CONFIG_K8_REV_F_SUPPORT

Modified: trunk/src/northbridge/amd/amdk8/amdk8.h
===================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8.h	2009-11-05 20:06:19 UTC (rev 4918)
+++ trunk/src/northbridge/amd/amdk8/amdk8.h	2009-11-05 21:02:35 UTC (rev 4919)
@@ -8,4 +8,6 @@
         #include "amdk8_pre_f.h"
 #endif
 
+void showallroutes(int level, device_t dev);
+
 #endif /* AMDK8_H */

Added: trunk/src/northbridge/amd/amdk8/util.c
===================================================================
--- trunk/src/northbridge/amd/amdk8/util.c	                        (rev 0)
+++ trunk/src/northbridge/amd/amdk8/util.c	2009-11-05 21:02:35 UTC (rev 4919)
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Vincent Legoll <vincent.legoll at gmail.com>
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+/*
+ * K8 northbridge utilities (dump routing registers).
+ * Designed to be called at any time.
+ * It can be called before RAM is set up by including this file.
+ * It can be called after RAM is set up by including amdk8.h and enabling the
+ * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc.
+ */
+#ifndef __ROMCC__
+#include <console/console.h>
+#include <string.h>
+#include <device/pci.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include <device/pci_ops.h>
+#include "amdk8.h"
+#endif
+
+/* Function 1 */
+/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at
+ * 0x78, 0xb8, and 0xd8
+ */
+#define DRAM_ROUTE_START	0x40
+#define DRAM_ROUTE_END		0x78
+#define MMIO_ROUTE_START	0x80
+#define MMIO_ROUTE_END		0xb8
+#define PCIIO_ROUTE_START	0xc0
+#define PCIIO_ROUTE_END		0xd8
+#define CONFIG_ROUTE_START	0xe0
+#define CONFIG_ROUTE_END	0xec
+
+#define PCI_IO_BASE0		0xc0
+#define PCI_IO_BASE1		0xc8
+#define PCI_IO_BASE2		0xd0
+#define PCI_IO_BASE3		0xd8
+#define PCI_IO_BASE_VGA_EN	(1 << 4)
+#define PCI_IO_BASE_NO_ISA	(1 << 5)
+
+#define BITS(r, shift, mask) (((r>>shift)&mask))
+
+/**
+ * Return "R" if the register has read-enable bit set.
+ */
+static const char *re(u32 i)
+{
+	return ((i & 1) ? "R" : "");
+}
+
+/**
+ * Return "W" if the register has write-enable bit set.
+ */
+static const char *we(u32 i)
+{
+	return ((i & 1) ? "W" : "");
+}
+
+/**
+ * Return a string containing the interleave settings.
+ */
+static const char *ileave(u32 base)
+{
+	switch ((base >> 8) & 7) {
+	case 0:
+		return "No interleave";
+	case 1:
+		return "2 nodes";
+	case 3:
+		return "4 nodes";
+	case 7:
+		return "8 nodes";
+	default:
+		return "Reserved";
+	}
+}
+
+/**
+ * Return the node number.
+ * For one case (config registers) these are not the right bit fields.
+ */
+static int node(u32 reg)
+{
+	return BITS(reg, 0, 0x7);
+}
+
+/**
+ * Return the link number.
+ * For one case (config registers) these are not the right bit fields.
+ */
+static int link(u32 reg)
+{
+	return BITS(reg, 4, 0x3);
+}
+
+/**
+ * Print the DRAM routing info for one base/limit pair.
+ *
+ * Show base, limit, dest node, dest link on that node, read and write
+ * enable, and interleave information.
+ *
+ * @param level Printing level
+ * @param which Register number
+ * @param base Base register
+ * @param lim Limit register
+ */
+static void showdram(int level, u8 which, u32 base, u32 lim)
+{
+	do_printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
+	       which, (((u64) base & 0xffff0000) << 8),
+	       (((u64) lim & 0xffff0000) << 8) + 0xffffff,
+	       node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
+}
+
+/**
+ * Print the config routing info for a config register.
+ *
+ * Show base, limit, dest node, dest link on that node, read and write
+ * enable, and device number compare enable
+ *
+ * @param level Printing level
+ * @param which Register number
+ * @param reg Config register
+ */
+static void showconfig(int level, u8 which, u32 reg)
+{
+	/* Don't use node() and link() here. */
+	do_printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n",
+	       which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff),
+	       BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
+	       re(reg), we(reg),
+	       BITS(reg, 2, 0x1)?"dev":"bus");
+}
+
+/**
+ * Print the PCIIO routing info for one base/limit pair.
+ *
+ * Show base, limit, dest node, dest link on that node, read and write
+ * enable, and VGA and ISA Enable.
+ *
+ * @param level Printing level
+ * @param which Register number
+ * @param base Base register
+ * @param lim Limit register
+ */
+static void showpciio(int level, u8 which, u32 base, u32 lim)
+{
+	do_printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
+	       which, BITS(base, 12, 0x3fff) << 12,
+	       (BITS(lim, 12, 0x3fff) << 12) + 0xfff, node(lim), link(lim),
+	       re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1));
+}
+
+/**
+ * Print the MMIO routing info for one base/limit pair.
+ *
+ * Show base, limit, dest node, dest link on that node, read and write
+ * enable, and CPU Disable, Lock, and Non-posted.
+ *
+ * @param level Printing level
+ * @param which Register number
+ * @param base Base register
+ * @param lim Limit register
+ */
+static void showmmio(int level, u8 which, u32 base, u32 lim)
+{
+	do_printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, "
+	       "CPU disable %d, Lock %d, Non posted %d\n",
+	       which, ((u64) BITS(base, 0, 0xffffff00)) << 8,
+	       (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, node(lim),
+	       link(lim), re(base), we(base), BITS(base, 4, 0x1),
+	       BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
+}
+
+/**
+ * Show all DRAM routing registers. This function is callable at any time.
+ *
+ * @param level The debug level.
+ * @param dev A 32-bit number in the standard bus/dev/fn format which is used
+ *            raw config space.
+ */
+static void showalldram(int level, device_t dev)
+{
+	u8 reg;
+	for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
+		u32 base = pci_read_config32(dev, reg);
+		u32 lim = pci_read_config32(dev, reg + 4);
+		if (base || lim!=(reg-DRAM_ROUTE_START)/8)
+			showdram(level, reg, base, lim);
+	}
+}
+
+/**
+ * Show all MMIO routing registers. This function is callable at any time.
+ *
+ * @param level The debug level.
+ * @param dev A 32-bit number in the standard bus/dev/fn format which is used
+ *            raw config space.
+ */
+static void showallmmio(int level, device_t dev)
+{
+	u8 reg;
+	for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
+		u32 base = pci_read_config32(dev, reg);
+		u32 lim = pci_read_config32(dev, reg + 4);
+		if (base || lim)
+			showmmio(level, reg, base, lim);
+	}
+}
+
+/**
+ * Show all PCIIO routing registers. This function is callable at any time.
+ *
+ * @param level The debug level.
+ * @param dev A 32-bit number in the standard bus/dev/fn format which is used
+ *            raw config space.
+ */
+static void showallpciio(int level, device_t dev)
+{
+	u8 reg;
+	for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
+		u32 base = pci_read_config32(dev, reg);
+		u32 lim = pci_read_config32(dev, reg + 4);
+		if (base || lim)
+			showpciio(level, reg, base, lim);
+	}
+}
+
+/**
+ * Show all config routing registers. This function is callable at any time.
+ *
+ * @param level The debug level.
+ * @param dev A 32-bit number in the standard bus/dev/fn format which is used
+ *            raw config space.
+ */
+static void showallconfig(int level, device_t dev)
+{
+	u8 reg;
+	for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
+		u32 val = pci_read_config32(dev, reg);
+		if (val)
+			showconfig(level, reg, val);
+	}
+}
+
+/**
+ * Show all routing registers. This function is callable at any time.
+ *
+ * @param level The debug level.
+ * @param dev A 32-bit number in the standard bus/dev/fn format which is used
+ *            raw config space.
+ */
+void showallroutes(int level, device_t dev)
+{
+	showalldram(level, dev);
+	showallmmio(level, dev);
+	showallpciio(level, dev);
+	showallconfig(level, dev);
+}




From mylesgw at gmail.com  Thu Nov  5 22:03:03 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 5 Nov 2009 15:03:03 -0600
Subject: [coreboot] [PATCH] Ron's v3 code ported to v2
In-Reply-To: <13426df10911051244y955678cw9e63a40de2651aec@mail.gmail.com>
References: <2831fecf0911051203t353010b2ie1287bfd4f9295be@mail.gmail.com>
	<13426df10911051244y955678cw9e63a40de2651aec@mail.gmail.com>
Message-ID: <2831fecf0911051303w383c6616r940d7315734d4e@mail.gmail.com>

On Thu, Nov 5, 2009 at 2:44 PM, ron minnich <rminnich at gmail.com> wrote:

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
Rev 4919.

Thanks,
Myles
-------------- next part --------------
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From Zheng.Bao at amd.com  Fri Nov  6 10:38:30 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 6 Nov 2009 17:38:30 +0800
Subject: [coreboot] The Linux report ACPI error since r4915.
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032F36A8@sbjgexmb1.amd.com>

Does it happen on your board.
Output is attached.

Zheng



-------------


coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov  6 18:42:14 CST
2009 starting...

BSP Family_Model: 00100f22 
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x1022, current patch id = 0x00000000
microcode: patch id to apply = 0x01000095
microcode: updated to patch id = 0x01000095  success

cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  00 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600a681 
  F3x84: a0e641e6 
  F3xD4: c8810f25 
  F3xD8: 03001815 
  F3xDC: 00005128 
Wait all core0s started 
Wait all core0s started done
start_other_cores()
init node: 00  cores: 03 
Start other core - nodeid: 00  cores: 03
started ap apicid:    cccooorrreeexxx:::      ---------   {{{
AAAPPPIIICCCIIIDDD   ===   000231   NNNOOODDDEE
EIIIDDD   ===   000000   CCCOOORRREEEIIIDDD   ===   000321}}}
---------


AmPmmiii scccrtrrooaocccrtooodeddeede::::    0eeeq1qquuuAiPiivv
vaaastllleaeennrntttt   edrrre:eevv v   0iii2Addd P      ===st   a
000xrxx11t1000ed2222:22,, ,   0ccc3uuur
rrrrrreseenn7nttt8   0_pppaeaattatcccrhhhly   _iiidsdd  e ===tu
p000x(xx00)0000
000000g00e0000t_0000c00p


u_rev mmEmAiiicXccrr=rooo0cccx1oood0ddee0e:::f2   p2ppaa.attt
ccchhhC   PUiiid dd  R ttteooov    iaaapspppp plllK8yyy _  ==1=
0.000xxx00
0111r00000s000078000909955_5p


ormmmi_iiciccrrnroooitcccooodd
deee:::   uuupppdddaaattteeeddd   tttooo   pppaaatttccchhh   iiiddd
===   000xxx000111000000000000999555      sssuuuccccccee
essssss


sb

7
0cccpp0puuu_SSSeaeeetrttAAlAMMMy_DDDMsMMSSeSRRtR   up()   ddd
ooosbnnne7ee0


0_iiidnnnieiittvt___icfffieiiddsdvvv_iiipoddd_r__aa_apppin(((sissttttaa(
aggg)eee1
11))s)b   aa7appp00iii_cccidiidded:::vi   000c32e1s_


FpFFIIoIDDDr_VVVIiIIDnDD  i ooot(nnn )  AA:APPP S::: M  0B0032u1s 


Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x28ae00c1 0x30015047 
FIDVID on BSP, APIC_id: 00
BSP fid = 10500
Wait for AP stage 1: ap_apicid = 1
	readback = 1010501
	common_fid(packed) = 10500
Wait for AP stage 1: ap_apicid = 2
	readback = 2010501
	common_fid(packed) = 10500
Wait for AP stage 1: ap_apicid = 3
	readback = 3010501
	common_fid(packed) = 10500
common_fid = 10500
FID Change Node:00, F3xD4: c8810f25 
End FIDVIDMSR 0xc0010071 0x28ae00c1 0x30015047 
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
...WARM RESET...




coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov  6 18:42:14 CST
2009 starting...

BSP Family_Model: 00100f22 
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00 
cpu_init_detectedx = 00000000 
microcode: equivalent rev id  = 0x1022, current patch id = 0x00000000
microcode: patch id to apply = 0x01000095
microcode: updated to patch id = 0x01000095  success

cpuSetAMDMSR  done
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  00 
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00 
  F3x80: e600a681 
  F3x84: a0e641e6 
  F3xD4: c8810f25 
  F3xD8: 03001815 
  F3xDC: 00005128 
Wait all core0s started 
Wait all core0s started done
start_other_cores()
init node: 00  cores: 03 
Start other core - nodeid: 00  cores: 03
started ap apicid:    cccooorrreeexxx:::      ---------   {{{
AAAPPPIIICCCIIIDDD   ===   000123   NNNOOODDDEE
EIIIDDD   ===   000000   CCCOOORRREEEIIIDDD   ===   000213}}}
---------


APmmmiii cscctrrrooaorcccoootdeddeeed::::    ee0eq1qquuuAiiiPv
vvsaaalltlaeeennnrtttt   errdr:eeevv v 0  iii2dAdd   P    s===  t 0
a00xxxr1t11e00022d22:22,,,  0  3cccuuu
rrrrrrreese7nnnttt8 0  ppp_aaeaatttccrchlhh   y_iiiddds e  ===t  u
p000xx(x0)0000000
0000ge00000t00_00000cpu


_rev mEmmiiiAccXc=rrroo0ocxccooo1d0ddeee0::f:2   ppp2a.aattt
ccchhhC  P Uiiidd d R  tttevooo    aiaapppsp ppKlllyy8y_   ==1= 0
000.xxx
000111r000s0000070800099905_55p

o
rmmmiii_ciccrrrnooiotcccoood
ddeee:::   uuupppdddaaattteeeddd   tttooo   pppaaatttccchhh   iiiddd
===   000xxx000111000000000000999555      sssuuucccccceee
ssssss


s
b

7cccppp0uu0u_SSSeeeetattAAArMMlMyDDDMM_MSsSSRRRe t  up( )  dddo
oonnnseebe7

0
0iiin_nniiidtettv___ffifciiidddevsvv_iiiddpdo___sssrt_ttaaaiggngieee22t2
(  aaa)pppiii
ccsciibi7ddd:::0 0  000_13d2e

v
ices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x28ae00c1 0x30013047 
End FIDVIDMSR 0xc0010071 0x28ae00c1 0x30003007 
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
mctAutoInitMCT_D: mct_init Node 00000000
mctAutoInitMCT_D: clear_legacy_Mode
mctAutoInitMCT_D: mct_InitialMCT_D
	mct_InitialMCT_D: Set Cl, Wb
mctAutoInitMCT_D: mctSMBhub_Init
mctAutoInitMCT_D: mct_initDCT
	mct_initDCT: DCTInit_D 0
	 DIMMPresence: i=00000000
	 DIMMPresence: smbaddr=00000050
	 DIMMPresence: i=00000001
	 DIMMPresence: smbaddr=00000051
	 DIMMPresence: i=00000002
	 DIMMPresence: smbaddr=00000052
	 DIMMPresence: i=00000003
	 DIMMPresence: smbaddr=00000053
	 DIMMPresence: i=00000004
	 DIMMPresence: smbaddr=00000000
	 DIMMPresence: i=00000005
	 DIMMPresence: smbaddr=00000000
	 DIMMPresence: i=00000006
	 DIMMPresence: smbaddr=00000000
	 DIMMPresence: i=00000007
	 DIMMPresence: smbaddr=00000000
	 DIMMPresence: DIMMValid=00000003
	 DIMMPresence: DIMMPresent=00000003
	 DIMMPresence: RegDIMMPresent=00000000
	 DIMMPresence: DimmECCPresent=00000000
	 DIMMPresence: DimmPARPresent=00000000
	 DIMMPresence: Dimmx4Present=00000000
	 DIMMPresence: Dimmx8Present=00000003
	 DIMMPresence: Dimmx16Present=00000000
	 DIMMPresence: DimmPlPresent=00000003
	 DIMMPresence: DimmDRPresent=00000000
	 DIMMPresence: DimmQRPresent=00000000
	 DIMMPresence: DATAload[0]=00000001
	 DIMMPresence: MAload[0]=00000008
	 DIMMPresence: MAdimms[0]=00000001
	 DIMMPresence: DATAload[1]=00000001
	 DIMMPresence: MAload[1]=00000008
	 DIMMPresence: MAdimms[1]=00000001
	 DIMMPresence: Status 00001000
	 DIMMPresence: ErrStatus 00000000
	 DIMMPresence: ErrCode 00000000
	 DIMMPresence: Done
		DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 00001000
SPDCalcWidth: ErrStatus 00000010
SPDCalcWidth: ErrCode 00000000
SPDCalcWidth: Done
		DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 00000004
SPDGetTCL_D: DIMMAutoSpeed 00000004
SPDGetTCL_D: Status 00001000
SPDGetTCL_D: ErrStatus 00000010
SPDGetTCL_D: ErrCode 00000000
SPDGetTCL_D: Done
AutoCycTiming: DramTimingLo 007dfb35
AutoCycTiming: DramTimingHi 00220300
AutoCycTiming: Status 00001000
AutoCycTiming: ErrStatus 00000010
AutoCycTiming: ErrCode 00000000
AutoCycTiming: Done
		DCTInit_D: AutoCycTiming_D Done
AutoConfig_D: DCT: 00000000
SPDSetBanks: Status 00001000
SPDSetBanks: ErrStatus 00000010
SPDSetBanks: ErrCode 00000000
SPDSetBanks: Done
AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register =
00004003
AfterStitch DCT0 and DCT1: DRAM Controller Select High Register =
00004000
AfterStitch pDCTstat->NodeSysBase = 00000000
mct_AfterStitchMemory: pDCTstat->NodeSysLimit 003fffff
StitchMemory: Status 00001000
StitchMemory: ErrStatus 00000010
StitchMemory: ErrCode 00000000
StitchMemory: Done
InterleaveBanks_D: Status 00001000
InterleaveBanks_D: ErrStatus 00000090
InterleaveBanks_D: ErrCode 00000000
InterleaveBanks_D: Done
DramTimingLo: val=00000002
DramTimingLo: val=00000000
DramTimingLo: val=00000008
DramTimingLo: val=00000008
DramTimingLo: val=00000002
DramTimingLo: val=00000000
DramTimingLo: val=00000002
DramTimingLo: val=00000000
AutoConfig_D: DramControl: 00000005
AutoConfig_D: DramTimingLo: 5d7dfb35
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 00010010
AutoConfig_D: DramConfigHi: 7f48800b
AutoConfig: Status 00001000
AutoConfig: ErrStatus 00000090
AutoConfig: ErrCode 00000000
AutoConfig: Done
		DCTInit_D: AutoConfig_D Done
dct: 00000000
Speed: 00000004
4 CH_ODC_CTL: 20113222
4 CH_ADDR_TMG: 00202520
		DCTInit_D: PlatformSpec_D Done
		DCTInit_D: StartupDCT_D
			StartupDCT_D: MemClkFreqVal
			StartupDCT_D: DqsRcvEnTrain set 
			StartupDCT_D: DramInit 
	mct_initDCT: DCTInit_D 1
		DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 00001000
SPDCalcWidth: ErrStatus 00000090
SPDCalcWidth: ErrCode 00000000
SPDCalcWidth: Done
		DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: DramTimingLo 007dfb35
AutoCycTiming: DramTimingHi 00220300
AutoCycTiming: Status 00001000
AutoCycTiming: ErrStatus 00000090
AutoCycTiming: ErrCode 00000000
AutoCycTiming: Done
		DCTInit_D: AutoCycTiming_D Done
AutoConfig_D: DCT: 00000001
SPDSetBanks: Status 00001000
SPDSetBanks: ErrStatus 00000090
SPDSetBanks: ErrCode 00000000
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 00000000
mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007ffffe
StitchMemory: Status 00001000
StitchMemory: ErrStatus 00000090
StitchMemory: ErrCode 00000000
StitchMemory: Done
InterleaveBanks_D: Status 00001000
InterleaveBanks_D: ErrStatus 00000090
InterleaveBanks_D: ErrCode 00000000
InterleaveBanks_D: Done
DramTimingLo: val=00000002
DramTimingLo: val=00000000
DramTimingLo: val=00000008
DramTimingLo: val=00000008
DramTimingLo: val=00000002
DramTimingLo: val=00000000
DramTimingLo: val=00000002
DramTimingLo: val=00000000
AutoConfig_D: DramControl: 00000005
AutoConfig_D: DramTimingLo: 5d7dfb35
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 00010010
AutoConfig_D: DramConfigHi: 7f48800b
AutoConfig: Status 00001000
AutoConfig: ErrStatus 00000090
AutoConfig: ErrCode 00000000
AutoConfig: Done
		DCTInit_D: AutoConfig_D Done
dct: 00000001
Speed: 00000004
4 CH_ODC_CTL: 20113222
4 CH_ADDR_TMG: 00202520
		DCTInit_D: PlatformSpec_D Done
		DCTInit_D: StartupDCT_D
			StartupDCT_D: MemClkFreqVal
			StartupDCT_D: DqsRcvEnTrain set 
			StartupDCT_D: DramInit 
mctAutoInitMCT_D: mct_init Node 00000001
mctAutoInitMCT_D: mct_init Node 00000002
mctAutoInitMCT_D: mct_init Node 00000003
mctAutoInitMCT_D: mct_init Node 00000004
mctAutoInitMCT_D: mct_init Node 00000005
mctAutoInitMCT_D: mct_init Node 00000006
mctAutoInitMCT_D: mct_init Node 00000007
mctAutoInitMCT_D: SyncDCTsReady_D
mct_SyncDCTsReady: Node 00000000
mct_SyncDCTsReady: DramEnabled
mctAutoInitMCT_D: HTMemMapInit_D
 Node: 00  base: 00  limit: 7fffff  BottomIO: e00000
mctAutoInitMCT_D: CPUMemTyping_D
	 CPUMemTyping: Cache32bTOP:00800000
	 CPUMemTyping: Bottom32bIO:00800000
	 CPUMemTyping: Bottom40bIO:00000000
mctAutoInitMCT_D: DQSTiming_D
DQSTiming_D: mct_BeforeDQSTrain_D:
DQSTiming_D: TrainReceiverEn_D FirstPass:
TrainRcvrEn: 1
TrainRcvrEn: 2
TrainRcvrEn: 3
TrainRcvrEn: 4
			Rank not enabled_D
			Rank not enabled_D
			Rank not enabled_D
			Rank not enabled_D
			Rank not enabled_D
			Rank not enabled_D
TrainRcvrEn: mct_DisableDQSRcvEn_D
TrainRcvrEn: Status 00001000
TrainRcvrEn: ErrStatus 00000090
TrainRcvrEn: ErrCode 00000000
TrainRcvrEn: Done
DQSTiming_D: mct_TrainDQSPos_D
TrainDQSRdWrPos: Status 00001200
TrainDQSRdWrPos: TrainErrors 00000000
TrainDQSRdWrPos: ErrStatus 00000090
TrainDQSRdWrPos: ErrCode 00000000
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 00001200
TrainDQSRdWrPos: TrainErrors 00000000
TrainDQSRdWrPos: ErrStatus 00000090
TrainDQSRdWrPos: ErrCode 00000000
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 00001200
TrainDQSRdWrPos: TrainErrors 00000000
TrainDQSRdWrPos: ErrStatus 00000090
TrainDQSRdWrPos: ErrCode 00000000
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 00001200
TrainDQSRdWrPos: TrainErrors 00000000
TrainDQSRdWrPos: ErrStatus 00000090
TrainDQSRdWrPos: ErrCode 00000000
TrainDQSRdWrPos: Done
DQSTiming_D: mctSetEccDQSRcvrEn_D
DQSTiming_D: TrainMaxReadLatency_D
DQSTiming_D: mct_EndDQSTraining_D
DQSTiming_D: MCTMemClr_D
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 00001200
InterleaveNodes_D: ErrStatus 00000090
InterleaveNodes_D: ErrCode 00000000
InterleaveNodes_D: Done
InterleaveChannels: F2x110 DRAM Controller Select Low Register =
00000584
InterleaveChannels_D: Node 00000000
InterleaveChannels_D: Status 00001200
InterleaveChannels_D: ErrStatus 00000090
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000001
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000002
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000003
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000004
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000005
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000006
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Node 00000007
InterleaveChannels_D: Status 00001000
InterleaveChannels_D: ErrStatus 00000000
InterleaveChannels_D: ErrCode 00000000
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
 ECCInit 0 
 ECCInit 1 
 ECCInit 2 
 ECCInit 3 
	mct_FinalMCT_D: Clr Cl, Wb
All Done
raminit_amdmct end:

*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf98
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now 
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1024000 bytes), entry @
0x200000
Stage: done loading.
Jumping to image.
coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov  6 18:42:14 CST
2009 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:03.0: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:05.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 0, 0 resources
PCI: 00:07.0: enabled 0, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:09.0: enabled 1, 0 resources
PCI: 00:0a.0: enabled 1, 0 resources
PCI: 00:11.0: enabled 1, 0 resources
PCI: 00:12.0: enabled 1, 0 resources
PCI: 00:12.1: enabled 1, 0 resources
PCI: 00:12.2: enabled 1, 0 resources
PCI: 00:13.0: enabled 1, 0 resources
PCI: 00:13.1: enabled 1, 0 resources
PCI: 00:13.2: enabled 1, 0 resources
PCI: 00:14.5: enabled 1, 0 resources
PCI: 00:14.0: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 0 resources
PCI: 00:14.2: enabled 1, 0 resources
PCI: 00:14.3: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.6: enabled 1, 1 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
PCI: 00:18.4: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PCI: 00:05.0: enabled 1, 0 resources
   PCI: 00:02.0: enabled 1, 0 resources
   PCI: 00:03.0: enabled 1, 0 resources
   PCI: 00:04.0: enabled 1, 0 resources
   PCI: 00:05.0: enabled 0, 0 resources
   PCI: 00:06.0: enabled 0, 0 resources
   PCI: 00:07.0: enabled 0, 0 resources
   PCI: 00:08.0: enabled 0, 0 resources
   PCI: 00:09.0: enabled 1, 0 resources
   PCI: 00:0a.0: enabled 1, 0 resources
   PCI: 00:11.0: enabled 1, 0 resources
   PCI: 00:12.0: enabled 1, 0 resources
   PCI: 00:12.1: enabled 1, 0 resources
   PCI: 00:12.2: enabled 1, 0 resources
   PCI: 00:13.0: enabled 1, 0 resources
   PCI: 00:13.1: enabled 1, 0 resources
   PCI: 00:13.2: enabled 1, 0 resources
   PCI: 00:14.5: enabled 1, 0 resources
   PCI: 00:14.0: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
   PCI: 00:14.1: enabled 1, 0 resources
   PCI: 00:14.2: enabled 1, 0 resources
   PCI: 00:14.3: enabled 1, 0 resources
    PNP: 002e.0: enabled 0, 3 resources
    PNP: 002e.1: enabled 1, 2 resources
    PNP: 002e.2: enabled 0, 2 resources
    PNP: 002e.3: enabled 0, 2 resources
    PNP: 002e.4: enabled 0, 0 resources
    PNP: 002e.5: enabled 1, 3 resources
    PNP: 002e.6: enabled 1, 1 resources
    PNP: 002e.7: enabled 0, 0 resources
    PNP: 002e.8: enabled 0, 2 resources
    PNP: 002e.9: enabled 0, 1 resources
    PNP: 002e.a: enabled 0, 0 resources
   PCI: 00:14.4: enabled 1, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
  PCI: 00:18.4: enabled 1, 0 resources
Mainboard MAHOGANY Enable. dev=0x00223470
mahogany_enable, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
mahogany_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
mahogany_enable: uma size 0x10000000, memory start 0x70000000
PCI: Using configuration type 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
PCI: 00:18.0 links increase to 8
  PCI: 00:18.3 siblings=3
CPU: APIC: 00 enabled
malloc Enter, size 1100, free_mem_ptr 0023a000
malloc 0023a000
CPU: APIC: 01 enabled
malloc Enter, size 1100, free_mem_ptr 0023a44c
malloc 0023a44c
CPU: APIC: 02 enabled
malloc Enter, size 1100, free_mem_ptr 0023a898
malloc 0023a898
CPU: APIC: 03 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
PCI: 00:18.5, bad id 0xffffffff
PCI: 00:18.6, bad id 0xffffffff
PCI: 00:18.7, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
rs780_enable: dev=00225b30, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x00225b30, dev=0x00227d90, port=0x00000008
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] ops
PCI: 00:00.0 [1022/9600] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0180
PCI: 00:00.0 count: 000c static_count: 0015
PCI: 00:00.0 [1022/9600] enabled next_unitid: 0015
PCI: 00:14.0
PCI: 00:14.1
PCI: 00:14.2
PCI: 00:14.3
PCI: 00:14.4
HT: Left over static devices.  Check your Config.lb
PCI: pci_scan_bus for bus 00
rs780_enable: dev=00225b30, VID_DID=0x96001022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00225b30, dev=0x00227d90, port=0x00000008
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9600] enabled
rs780_enable: dev=00225f7c, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=002263c8, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00225b30, dev=0x002263c8, port=0x2.
rs780_gfx_init step1.
rs780_gfx_init step2.
misc 28 = 541
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
PcieLinkTraining port=2:lc current state=4000102
Disabling static device: PCI: 00:02.0
PCI: 00:02.1, bad id 0xffffffff
PCI: 00:02.2, bad id 0xffffffff
PCI: 00:02.3, bad id 0xffffffff
PCI: 00:02.4, bad id 0xffffffff
PCI: 00:02.5, bad id 0xffffffff
PCI: 00:02.6, bad id 0xffffffff
PCI: 00:02.7, bad id 0xffffffff
rs780_enable: dev=00226814, VID_DID=0x960b1022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00225b30, dev=0x00226814, port=0x3.
rs780_gfx_init step1.
rs780_gfx_init step2.
misc 28 = 541
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
PcieLinkTraining port=3:lc current state=4000102
Disabling static device: PCI: 00:03.0
PCI: 00:03.1, bad id 0xffffffff
PCI: 00:03.2, bad id 0xffffffff
PCI: 00:03.3, bad id 0xffffffff
PCI: 00:03.4, bad id 0xffffffff
PCI: 00:03.5, bad id 0xffffffff
PCI: 00:03.6, bad id 0xffffffff
PCI: 00:03.7, bad id 0xffffffff
rs780_enable: dev=00226c60, VID_DID=0x96041022
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00225b30, dev=0x00226c60, port=0x00000004
PcieLinkTraining port=4:lc current state=10203
PcieTrainPort port=0x4 result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/9604] enabled
rs780_enable: dev=002270ac, VID_DID=0x96051022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:05.1, bad id 0xffffffff
PCI: 00:05.2, bad id 0xffffffff
PCI: 00:05.3, bad id 0xffffffff
PCI: 00:05.4, bad id 0xffffffff
PCI: 00:05.5, bad id 0xffffffff
PCI: 00:05.6, bad id 0xffffffff
PCI: 00:05.7, bad id 0xffffffff
rs780_enable: dev=002274f8, VID_DID=0x96061022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:06.1, bad id 0xffffffff
PCI: 00:06.2, bad id 0xffffffff
PCI: 00:06.3, bad id 0xffffffff
PCI: 00:06.4, bad id 0xffffffff
PCI: 00:06.5, bad id 0xffffffff
PCI: 00:06.6, bad id 0xffffffff
PCI: 00:06.7, bad id 0xffffffff
rs780_enable: dev=00227944, VID_DID=0x96071022
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
PCI: 00:07.1, bad id 0xffffffff
PCI: 00:07.2, bad id 0xffffffff
PCI: 00:07.3, bad id 0xffffffff
PCI: 00:07.4, bad id 0xffffffff
PCI: 00:07.5, bad id 0xffffffff
PCI: 00:07.6, bad id 0xffffffff
PCI: 00:07.7, bad id 0xffffffff
rs780_enable: dev=00227d90, VID_DID=0xffffffff
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3()
PCI: 00:08.1, bad id 0xffffffff
PCI: 00:08.2, bad id 0xffffffff
PCI: 00:08.3, bad id 0xffffffff
PCI: 00:08.4, bad id 0xffffffff
PCI: 00:08.5, bad id 0xffffffff
PCI: 00:08.6, bad id 0xffffffff
PCI: 00:08.7, bad id 0xffffffff
rs780_enable: dev=002281dc, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00225b30, dev=0x002281dc, port=0x00000009
PcieLinkTraining port=9:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
PcieTrainPort port=0x9 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=00228628, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00225b30, dev=0x00228628, port=0x0000000a
PcieLinkTraining port=a:lc current state=10203
PcieTrainPort port=0xa result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
sb700_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb700_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb700_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb700_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
PCI: 00:12.3, bad id 0xffffffff
PCI: 00:12.4, bad id 0xffffffff
PCI: 00:12.5, bad id 0xffffffff
PCI: 00:12.6, bad id 0xffffffff
PCI: 00:12.7, bad id 0xffffffff
sb700_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb700_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb700_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
PCI: 00:13.3, bad id 0xffffffff
PCI: 00:13.4, bad id 0xffffffff
PCI: 00:13.5, bad id 0xffffffff
PCI: 00:13.6, bad id 0xffffffff
PCI: 00:13.7, bad id 0xffffffff
sb700_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb700_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb700_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb700_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb700_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb700_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:14.6, bad id 0xffffffff
PCI: 00:14.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0 [1002/9615] ops
rs780_internal_gfx_enable dev = 0x00228a78, nb_dev = 0x00225b30.
sysmem = 0_80000000
PCI: 01:05.0 [1002/9615] enabled
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0, bad id 0xffffffff
PCI: 02:01.0, bad id 0xffffffff
PCI: 02:02.0, bad id 0xffffffff
PCI: 02:03.0, bad id 0xffffffff
PCI: 02:04.0, bad id 0xffffffff
PCI: 02:05.0, bad id 0xffffffff
PCI: 02:06.0, bad id 0xffffffff
PCI: 02:07.0, bad id 0xffffffff
PCI: 02:08.0, bad id 0xffffffff
PCI: 02:09.0, bad id 0xffffffff
PCI: 02:0a.0, bad id 0xffffffff
PCI: 02:0b.0, bad id 0xffffffff
PCI: 02:0c.0, bad id 0xffffffff
PCI: 02:0d.0, bad id 0xffffffff
PCI: 02:0e.0, bad id 0xffffffff
PCI: 02:0f.0, bad id 0xffffffff
PCI: 02:10.0, bad id 0xffffffff
PCI: 02:11.0, bad id 0xffffffff
PCI: 02:12.0, bad id 0xffffffff
PCI: 02:13.0, bad id 0xffffffff
PCI: 02:14.0, bad id 0xffffffff
PCI: 02:15.0, bad id 0xffffffff
PCI: 02:16.0, bad id 0xffffffff
PCI: 02:17.0, bad id 0xffffffff
PCI: 02:18.0, bad id 0xffffffff
PCI: 02:19.0, bad id 0xffffffff
PCI: 02:1a.0, bad id 0xffffffff
PCI: 02:1b.0, bad id 0xffffffff
PCI: 02:1c.0, bad id 0xffffffff
PCI: 02:1d.0, bad id 0xffffffff
PCI: 02:1e.0, bad id 0xffffffff
PCI: 02:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
malloc Enter, size 1100, free_mem_ptr 0023ace4
malloc 0023ace4
PCI: 03:00.0 [10ec/8168] enabled
PCI: 03:01.0, bad id 0xffffffff
PCI: 03:02.0, bad id 0xffffffff
PCI: 03:03.0, bad id 0xffffffff
PCI: 03:04.0, bad id 0xffffffff
PCI: 03:05.0, bad id 0xffffffff
PCI: 03:06.0, bad id 0xffffffff
PCI: 03:07.0, bad id 0xffffffff
PCI: 03:08.0, bad id 0xffffffff
PCI: 03:09.0, bad id 0xffffffff
PCI: 03:0a.0, bad id 0xffffffff
PCI: 03:0b.0, bad id 0xffffffff
PCI: 03:0c.0, bad id 0xffffffff
PCI: 03:0d.0, bad id 0xffffffff
PCI: 03:0e.0, bad id 0xffffffff
PCI: 03:0f.0, bad id 0xffffffff
PCI: 03:10.0, bad id 0xffffffff
PCI: 03:11.0, bad id 0xffffffff
PCI: 03:12.0, bad id 0xffffffff
PCI: 03:13.0, bad id 0xffffffff
PCI: 03:14.0, bad id 0xffffffff
PCI: 03:15.0, bad id 0xffffffff
PCI: 03:16.0, bad id 0xffffffff
PCI: 03:17.0, bad id 0xffffffff
PCI: 03:18.0, bad id 0xffffffff
PCI: 03:19.0, bad id 0xffffffff
PCI: 03:1a.0, bad id 0xffffffff
PCI: 03:1b.0, bad id 0xffffffff
PCI: 03:1c.0, bad id 0xffffffff
PCI: 03:1d.0, bad id 0xffffffff
PCI: 03:1e.0, bad id 0xffffffff
PCI: 03:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=003
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0, bad id 0xffffffff
PCI: 04:01.0, bad id 0xffffffff
PCI: 04:02.0, bad id 0xffffffff
PCI: 04:03.0, bad id 0xffffffff
PCI: 04:04.0, bad id 0xffffffff
PCI: 04:05.0, bad id 0xffffffff
PCI: 04:06.0, bad id 0xffffffff
PCI: 04:07.0, bad id 0xffffffff
PCI: 04:08.0, bad id 0xffffffff
PCI: 04:09.0, bad id 0xffffffff
PCI: 04:0a.0, bad id 0xffffffff
PCI: 04:0b.0, bad id 0xffffffff
PCI: 04:0c.0, bad id 0xffffffff
PCI: 04:0d.0, bad id 0xffffffff
PCI: 04:0e.0, bad id 0xffffffff
PCI: 04:0f.0, bad id 0xffffffff
PCI: 04:10.0, bad id 0xffffffff
PCI: 04:11.0, bad id 0xffffffff
PCI: 04:12.0, bad id 0xffffffff
PCI: 04:13.0, bad id 0xffffffff
PCI: 04:14.0, bad id 0xffffffff
PCI: 04:15.0, bad id 0xffffffff
PCI: 04:16.0, bad id 0xffffffff
PCI: 04:17.0, bad id 0xffffffff
PCI: 04:18.0, bad id 0xffffffff
PCI: 04:19.0, bad id 0xffffffff
PCI: 04:1a.0, bad id 0xffffffff
PCI: 04:1b.0, bad id 0xffffffff
PCI: 04:1c.0, bad id 0xffffffff
PCI: 04:1d.0, bad id 0xffffffff
PCI: 04:1e.0, bad id 0xffffffff
PCI: 04:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=004
do_pci_scan_bridge returns max 4
scan_static_bus for PCI: 00:14.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_static_bus for PCI: 00:14.0 done
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 05
PCI: 05:00.0, bad id 0xffffffff
PCI: 05:01.0, bad id 0xffffffff
PCI: 05:02.0, bad id 0xffffffff
PCI: 05:03.0, bad id 0xffffffff
PCI: 05:04.0, bad id 0xffffffff
PCI: 05:05.0, bad id 0xffffffff
PCI: 05:06.0, bad id 0xffffffff
PCI: 05:07.0, bad id 0xffffffff
PCI: 05:08.0, bad id 0xffffffff
PCI: 05:09.0, bad id 0xffffffff
PCI: 05:0a.0, bad id 0xffffffff
PCI: 05:0b.0, bad id 0xffffffff
PCI: 05:0c.0, bad id 0xffffffff
PCI: 05:0d.0, bad id 0xffffffff
PCI: 05:0e.0, bad id 0xffffffff
PCI: 05:0f.0, bad id 0xffffffff
PCI: 05:10.0, bad id 0xffffffff
PCI: 05:11.0, bad id 0xffffffff
PCI: 05:12.0, bad id 0xffffffff
PCI: 05:13.0, bad id 0xffffffff
PCI: 05:14.0, bad id 0xffffffff
PCI: 05:15.0, bad id 0xffffffff
PCI: 05:16.0, bad id 0xffffffff
PCI: 05:17.0, bad id 0xffffffff
PCI: 05:18.0, bad id 0xffffffff
PCI: 05:19.0, bad id 0xffffffff
PCI: 05:1a.0, bad id 0xffffffff
PCI: 05:1b.0, bad id 0xffffffff
PCI: 05:1c.0, bad id 0xffffffff
PCI: 05:1d.0, bad id 0xffffffff
PCI: 05:1e.0, bad id 0xffffffff
PCI: 05:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
PCI: pci_scan_bus returning with max=005
PCI: pci_scan_bus returning with max=005
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
rs780_gfx_read_resources.
PCI: 01:05.0 register 24(ffffffff), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 2 link: 0
PCI: 00:04.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PNP: 002e.6 missing read_resources
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 5 link: 0
PCI: 00:14.4 read_resources bus 5 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.0 read_resources bus 0 link: 4
PCI: 00:18.0 read_resources bus 0 link: 4 done
PCI: 00:18.0 read_resources bus 0 link: 5
PCI: 00:18.0 read_resources bus 0 link: 5 done
PCI: 00:18.0 read_resources bus 0 link: 6
PCI: 00:18.0 read_resources bus 0 link: 6 done
PCI: 00:18.0 read_resources bus 0 link: 7
PCI: 00:18.0 read_resources bus 0 link: 7 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
   APIC: 02 links 0 child on link 0 NULL
   APIC: 03 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff
flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100
   PCI: 00:18.0 links 8 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff
flags 81200 index 10b0
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff
flags 80200 index 10b8
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags
80100 index 10d8
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffffffffffff flags 201 index 1c
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff
flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffff flags 81202 index 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff
flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit
ffffffff flags 200 index 18
     PCI: 01:05.0 resource base fff00000 size 100 align 0 gran 0 limit 0
flags c0002200 index 30
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:03.0 links 0 child on link 0 NULL
    PCI: 00:04.0 links 1 child on link 0 NULL
    PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
flags 80102 index 1c
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24
    PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:06.0 links 0 child on link 0 NULL
    PCI: 00:07.0 links 0 child on link 0 NULL
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
flags 80102 index 1c
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24
    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff
flags 100 index 10
     PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffffffffffff flags 201 index 18
     PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit
ffffffffffffffff flags 1201 index 20
     PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit
ffffffff flags 2200 index 30
    PCI: 00:0a.0 links 1 child on link 0 NULL
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
flags 80102 index 1c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
    PCI: 00:11.0 links 0 child on link 0 NULL
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
100 index 10
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
100 index 14
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
100 index 18
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
100 index 1c
    PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags
100 index 20
    PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit
ffffffff flags 200 index 24
    PCI: 00:12.0 links 0 child on link 0 NULL
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 10
    PCI: 00:12.1 links 0 child on link 0 NULL
    PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 10
    PCI: 00:12.2 links 0 child on link 0 NULL
    PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
    PCI: 00:13.0 links 0 child on link 0 NULL
    PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 10
    PCI: 00:13.1 links 0 child on link 0 NULL
    PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 10
    PCI: 00:13.2 links 0 child on link 0 NULL
    PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
    PCI: 00:14.0 links 1 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit
ffffffff flags 80000200 index 74
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff
flags 80000100 index 90
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
    PCI: 00:14.1 links 0 child on link 0 NULL
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags
100 index 10
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags
100 index 14
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags
100 index 18
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags
100 index 1c
    PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags
100 index 20
    PCI: 00:14.2 links 0 child on link 0 NULL
    PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 201 index 10
    PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff
flags 200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags
c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.a links 0 child on link 0 NULL
    PCI: 00:14.4 links 1 child on link 0 NULL
    PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff
flags 80102 index 1c
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 81202 index 24
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
    PCI: 00:14.5 links 0 child on link 0 NULL
    PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 10
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit
ffffffff flags 200 index 94
   PCI: 00:18.4 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: 1ffffff
PCI: 01:05.0 14 *  [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran:
12 limit: ffff done
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff done
PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff
PCI: 03:00.0 10 *  [0x0 - 0xff] io
PCI: 00:09.0 compute_resources_io: base: 100 size: 1000 align: 12 gran:
12 limit: ffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:09.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:11.0 20 *  [0x2000 - 0x200f] io
PCI: 00:14.1 20 *  [0x2010 - 0x201f] io
PCI: 00:11.0 10 *  [0x2020 - 0x2027] io
PCI: 00:11.0 18 *  [0x2028 - 0x202f] io
PCI: 00:14.1 10 *  [0x2030 - 0x2037] io
PCI: 00:14.1 18 *  [0x2038 - 0x203f] io
PCI: 00:11.0 14 *  [0x2040 - 0x2043] io
PCI: 00:11.0 1c *  [0x2044 - 0x2047] io
PCI: 00:14.1 14 *  [0x2048 - 0x204b] io
PCI: 00:14.1 1c *  [0x204c - 0x204f] io
PCI: 00:18.0 compute_resources_io: base: 2050 size: 3000 align: 12 gran:
12 limit: ffff done
PCI: 00:18.0 10d8 *  [0x0 - 0x2fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12
gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffff
PCI: 01:05.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000
align: 28 gran: 20 limit: ffffffff done
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffffffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffffffffff done
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffffffffff
PCI: 03:00.0 20 *  [0x0 - 0xffff] prefmem
PCI: 00:09.0 compute_resources_prefmem: base: 10000 size: 100000 align:
20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffffffffff
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffffffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
20 limit: ffffffff done
PCI: 00:01.0 24 *  [0x0 - 0xfffffff] prefmem
PCI: 00:09.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 10100000 size: 10100000
align: 28 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 01:05.0 18 *  [0x0 - 0xffff] mem
PCI: 00:01.0 compute_resources_mem: base: 10000 size: 100000 align: 20
gran: 20 limit: ffffffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 03:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 03:00.0 18 *  [0x20000 - 0x20fff] mem
PCI: 00:09.0 compute_resources_mem: base: 21000 size: 100000 align: 20
gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:00.0 1c *  [0x0 - 0xfffffff] mem
PCI: 00:01.0 20 *  [0x10000000 - 0x100fffff] mem
PCI: 00:09.0 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:14.2 10 *  [0x10200000 - 0x10203fff] mem
PCI: 00:12.0 10 *  [0x10204000 - 0x10204fff] mem
PCI: 00:12.1 10 *  [0x10205000 - 0x10205fff] mem
PCI: 00:13.0 10 *  [0x10206000 - 0x10206fff] mem
PCI: 00:13.1 10 *  [0x10207000 - 0x10207fff] mem
PCI: 00:14.5 10 *  [0x10208000 - 0x10208fff] mem
PCI: 00:11.0 24 *  [0x10209000 - 0x102093ff] mem
PCI: 00:12.2 10 *  [0x10209400 - 0x102094ff] mem
PCI: 00:13.2 10 *  [0x10209500 - 0x102095ff] mem
PCI: 00:14.3 a0 *  [0x10209600 - 0x10209600] mem
PCI: 00:18.0 compute_resources_mem: base: 10209601 size: 10300000 align:
28 gran: 20 limit: ffffffff done
PCI: 00:18.0 10b8 *  [0x0 - 0x102fffff] mem
PCI: 00:18.0 10b0 *  [0x20000000 - 0x300fffff] prefmem
PCI: 00:18.3 94 *  [0x34000000 - 0x37ffffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000
align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.1
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.1
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: I2C: 01:52
constrain_resources: I2C: 01:53
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.1
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.6
skipping PNP: 002e.6 at 70 fixed resource, size=0!
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
	lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12
gran:0 limit:ffff
Assigned: PCI: 00:18.0 10d8 *  [0x1000 - 0x3fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000
align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12
limit:ffff
Assigned: PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:09.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:11.0 20 *  [0x3000 - 0x300f] io
Assigned: PCI: 00:14.1 20 *  [0x3010 - 0x301f] io
Assigned: PCI: 00:11.0 10 *  [0x3020 - 0x3027] io
Assigned: PCI: 00:11.0 18 *  [0x3028 - 0x302f] io
Assigned: PCI: 00:14.1 10 *  [0x3030 - 0x3037] io
Assigned: PCI: 00:14.1 18 *  [0x3038 - 0x303f] io
Assigned: PCI: 00:11.0 14 *  [0x3040 - 0x3043] io
Assigned: PCI: 00:11.0 1c *  [0x3044 - 0x3047] io
Assigned: PCI: 00:14.1 14 *  [0x3048 - 0x304b] io
Assigned: PCI: 00:14.1 1c *  [0x304c - 0x304f] io
PCI: 00:18.0 allocate_resources_io: next_base: 3050 size: 3000 align: 12
gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff
Assigned: PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
gran: 12 done
PCI: 00:04.0 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:04.0 allocate_resources_io: next_base: ffff size: 0 align: 12
gran: 12 done
PCI: 00:09.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12
limit:ffff
Assigned: PCI: 03:00.0 10 *  [0x2000 - 0x20ff] io
PCI: 00:09.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12
gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12
gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12
gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000
align:28 gran:0 limit:febfffff
Assigned: PCI: 00:18.0 10b8 *  [0xc0000000 - 0xd02fffff] mem
Assigned: PCI: 00:18.0 10b0 *  [0xe0000000 - 0xf00fffff] prefmem
Assigned: PCI: 00:18.3 94 *  [0xf4000000 - 0xf7ffffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size:
38000000 align: 28 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:e0000000 size:10100000
align:28 gran:20 limit:febfffff
Assigned: PCI: 00:01.0 24 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:09.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: f0100000 size:
10100000 align: 28 gran: 20 done
PCI: 00:01.0 allocate_resources_prefmem: base:e0000000 size:10000000
align:28 gran:20 limit:febfffff
Assigned: PCI: 01:05.0 10 *  [0xe0000000 - 0xefffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: f0000000 size:
10000000 align: 28 gran: 20 done
PCI: 00:04.0 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:04.0 allocate_resources_prefmem: next_base: febfffff size: 0
align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_prefmem: base:f0000000 size:100000
align:20 gran:20 limit:febfffff
Assigned: PCI: 03:00.0 20 *  [0xf0000000 - 0xf000ffff] prefmem
PCI: 00:09.0 allocate_resources_prefmem: next_base: f0010000 size:
100000 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0
align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0
align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10300000
align:28 gran:20 limit:febfffff
Assigned: PCI: 00:00.0 1c *  [0xc0000000 - 0xcfffffff] mem
Assigned: PCI: 00:01.0 20 *  [0xd0000000 - 0xd00fffff] mem
Assigned: PCI: 00:09.0 20 *  [0xd0100000 - 0xd01fffff] mem
Assigned: PCI: 00:14.2 10 *  [0xd0200000 - 0xd0203fff] mem
Assigned: PCI: 00:12.0 10 *  [0xd0204000 - 0xd0204fff] mem
Assigned: PCI: 00:12.1 10 *  [0xd0205000 - 0xd0205fff] mem
Assigned: PCI: 00:13.0 10 *  [0xd0206000 - 0xd0206fff] mem
Assigned: PCI: 00:13.1 10 *  [0xd0207000 - 0xd0207fff] mem
Assigned: PCI: 00:14.5 10 *  [0xd0208000 - 0xd0208fff] mem
Assigned: PCI: 00:11.0 24 *  [0xd0209000 - 0xd02093ff] mem
Assigned: PCI: 00:12.2 10 *  [0xd0209400 - 0xd02094ff] mem
Assigned: PCI: 00:13.2 10 *  [0xd0209500 - 0xd02095ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xd0209600 - 0xd0209600] mem
PCI: 00:18.0 allocate_resources_mem: next_base: d0209601 size: 10300000
align: 28 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:d0000000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 01:05.0 18 *  [0xd0000000 - 0xd000ffff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: d0010000 size: 100000
align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:04.0 allocate_resources_mem: next_base: febfffff size: 0 align:
20 gran: 20 done
PCI: 00:09.0 allocate_resources_mem: base:d0100000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 03:00.0 30 *  [0xd0100000 - 0xd011ffff] mem
Assigned: PCI: 03:00.0 18 *  [0xd0120000 - 0xd0120fff] mem
PCI: 00:09.0 allocate_resources_mem: next_base: d0121000 size: 100000
align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align:
20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align:
20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=00300000, basek=00000300, limitk=00000000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 10b0 <- [0x00e0000000 - 0x00f00fffff] size 0x10100000 gran
0x14 prefmem <node 00 link 00>
PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00d02fffff] size 0x10300000 gran
0x14 mem <node 00 link 00>
PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran
0x0c io <node 00 link 00>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran
0x1c mem64
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran
0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran
0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran
0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran
0x1c prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran
0x08 io
PCI: 01:05.0 18 <- [0x00d0000000 - 0x00d000ffff] size 0x00010000 gran
0x10 mem
PCI: 01:05.0 30 <- [0x00fff00000 - 0x00fff000ff] size 0x00000100 gran
0x00 romem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran
0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran
0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran
0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00d0100000 - 0x00d01fffff] size 0x00100000 gran
0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran
0x08 io
PCI: 03:00.0 18 <- [0x00d0120000 - 0x00d0120fff] size 0x00001000 gran
0x0c mem64
PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f000ffff] size 0x00010000 gran
0x10 prefmem64
PCI: 03:00.0 30 <- [0x00d0100000 - 0x00d011ffff] size 0x00020000 gran
0x11 romem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran
0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 04 mem
PCI: 00:11.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran
0x03 io
PCI: 00:11.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran
0x02 io
PCI: 00:11.0 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran
0x03 io
PCI: 00:11.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran
0x02 io
PCI: 00:11.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran
0x04 io
PCI: 00:11.0 24 <- [0x00d0209000 - 0x00d02093ff] size 0x00000400 gran
0x0a mem
PCI: 00:12.0 10 <- [0x00d0204000 - 0x00d0204fff] size 0x00001000 gran
0x0c mem
PCI: 00:12.1 10 <- [0x00d0205000 - 0x00d0205fff] size 0x00001000 gran
0x0c mem
PCI: 00:12.2 10 <- [0x00d0209400 - 0x00d02094ff] size 0x00000100 gran
0x08 mem
PCI: 00:13.0 10 <- [0x00d0206000 - 0x00d0206fff] size 0x00001000 gran
0x0c mem
PCI: 00:13.1 10 <- [0x00d0207000 - 0x00d0207fff] size 0x00001000 gran
0x0c mem
PCI: 00:13.2 10 <- [0x00d0209500 - 0x00d02095ff] size 0x00000100 gran
0x08 mem
ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned
ERROR: PCI: 00:14.0 90 io size: 0x0000000010 not assigned
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran
0x03 io
PCI: 00:14.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran
0x02 io
PCI: 00:14.1 18 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran
0x03 io
PCI: 00:14.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran
0x02 io
PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran
0x04 io
PCI: 00:14.2 10 <- [0x00d0200000 - 0x00d0203fff] size 0x00004000 gran
0x0e mem64
PCI: 00:14.3 a0 <- [0x00d0209600 - 0x00d0209600] size 0x00000001 gran
0x00 mem
PCI: 00:14.3 03 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran
0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran
0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran
0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran
0x03 io
PNP: 002e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran
0x03 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran
0x00 irq
PNP: 002e.6 missing set_resources
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran
0x0c bus 05 io
PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 05 prefmem
PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
0x14 bus 05 mem
PCI: 00:14.5 10 <- [0x00d0208000 - 0x00d0208fff] size 0x00001000 gran
0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran
0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
   APIC: 01 links 0 child on link 0 NULL
   APIC: 02 links 0 child on link 0 NULL
   APIC: 03 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0
  PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit
ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0
limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0
flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0
limit 0 flags e0004200 index 20
   PCI: 00:18.0 links 8 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base e0000000 size 10100000 align 28 gran 20
limit febfffff flags 60081200 index 10b0
   PCI: 00:18.0 resource base c0000000 size 10300000 align 28 gran 20
limit febfffff flags 60080200 index 10b8
   PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff
flags 60080100 index 10d8
    PCI: 00:00.0 links 0 child on link 0 NULL
    PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28
limit febfffff flags 60000201 index 1c
    PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit
ffff flags 60080102 index 1c
    PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 20
limit febfffff flags 60081202 index 24
    PCI: 00:01.0 resource base d0000000 size 100000 align 20 gran 20
limit febfffff flags 60080202 index 20
     PCI: 01:05.0 links 0 child on link 0 NULL
     PCI: 01:05.0 resource base e0000000 size 10000000 align 28 gran 28
limit febfffff flags 60001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff
flags 60000100 index 14
     PCI: 01:05.0 resource base d0000000 size 10000 align 16 gran 16
limit febfffff flags 60000200 index 18
     PCI: 01:05.0 resource base fff00000 size 100 align 0 gran 0 limit 0
flags e0002200 index 30
    PCI: 00:02.0 links 0 child on link 0 NULL
    PCI: 00:03.0 links 0 child on link 0 NULL
    PCI: 00:04.0 links 1 child on link 0 NULL
    PCI: 00:04.0 resource base ffff size 0 align 12 gran 12 limit ffff
flags 60080102 index 1c
    PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
    PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
    PCI: 00:05.0 links 0 child on link 0 NULL
    PCI: 00:06.0 links 0 child on link 0 NULL
    PCI: 00:07.0 links 0 child on link 0 NULL
    PCI: 00:08.0 links 0 child on link 0 NULL
    PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0
    PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit
ffff flags 60080102 index 1c
    PCI: 00:09.0 resource base f0000000 size 100000 align 20 gran 20
limit febfffff flags 60081202 index 24
    PCI: 00:09.0 resource base d0100000 size 100000 align 20 gran 20
limit febfffff flags 60080202 index 20
     PCI: 03:00.0 links 0 child on link 0 NULL
     PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff
flags 60000100 index 10
     PCI: 03:00.0 resource base d0120000 size 1000 align 12 gran 12
limit febfffff flags 60000201 index 18
     PCI: 03:00.0 resource base f0000000 size 10000 align 16 gran 16
limit febfffff flags 60001201 index 20
     PCI: 03:00.0 resource base d0100000 size 20000 align 17 gran 17
limit febfffff flags 60002200 index 30
    PCI: 00:0a.0 links 1 child on link 0 NULL
    PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff
flags 60080102 index 1c
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
    PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
    PCI: 00:11.0 links 0 child on link 0 NULL
    PCI: 00:11.0 resource base 3020 size 8 align 3 gran 3 limit ffff
flags 60000100 index 10
    PCI: 00:11.0 resource base 3040 size 4 align 2 gran 2 limit ffff
flags 60000100 index 14
    PCI: 00:11.0 resource base 3028 size 8 align 3 gran 3 limit ffff
flags 60000100 index 18
    PCI: 00:11.0 resource base 3044 size 4 align 2 gran 2 limit ffff
flags 60000100 index 1c
    PCI: 00:11.0 resource base 3000 size 10 align 4 gran 4 limit ffff
flags 60000100 index 20
    PCI: 00:11.0 resource base d0209000 size 400 align 10 gran 10 limit
febfffff flags 60000200 index 24
    PCI: 00:12.0 links 0 child on link 0 NULL
    PCI: 00:12.0 resource base d0204000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
    PCI: 00:12.1 links 0 child on link 0 NULL
    PCI: 00:12.1 resource base d0205000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
    PCI: 00:12.2 links 0 child on link 0 NULL
    PCI: 00:12.2 resource base d0209400 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
    PCI: 00:13.0 links 0 child on link 0 NULL
    PCI: 00:13.0 resource base d0206000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
    PCI: 00:13.1 links 0 child on link 0 NULL
    PCI: 00:13.1 resource base d0207000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
    PCI: 00:13.2 links 0 child on link 0 NULL
    PCI: 00:13.2 resource base d0209500 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
    PCI: 00:14.0 links 1 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit
ffffffff flags 80000200 index 74
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff
flags 80000100 index 90
     I2C: 01:50 links 0 child on link 0 NULL
     I2C: 01:51 links 0 child on link 0 NULL
     I2C: 01:52 links 0 child on link 0 NULL
     I2C: 01:53 links 0 child on link 0 NULL
    PCI: 00:14.1 links 0 child on link 0 NULL
    PCI: 00:14.1 resource base 3030 size 8 align 3 gran 3 limit ffff
flags 60000100 index 10
    PCI: 00:14.1 resource base 3048 size 4 align 2 gran 2 limit ffff
flags 60000100 index 14
    PCI: 00:14.1 resource base 3038 size 8 align 3 gran 3 limit ffff
flags 60000100 index 18
    PCI: 00:14.1 resource base 304c size 4 align 2 gran 2 limit ffff
flags 60000100 index 1c
    PCI: 00:14.1 resource base 3010 size 10 align 4 gran 4 limit ffff
flags 60000100 index 20
    PCI: 00:14.2 links 0 child on link 0 NULL
    PCI: 00:14.2 resource base d0200000 size 4000 align 14 gran 14 limit
febfffff flags 60000201 index 10
    PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base d0209600 size 1 align 0 gran 0 limit
febfffff flags 60000200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags e0000200 index 3
     PNP: 002e.0 links 0 child on link 0 NULL
     PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags
c0000800 index 74
     PNP: 002e.1 links 0 child on link 0 NULL
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
     PNP: 002e.2 links 0 child on link 0 NULL
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
     PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 75
     PNP: 002e.3 links 0 child on link 0 NULL
     PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.4 links 0 child on link 0 NULL
     PNP: 002e.5 links 0 child on link 0 NULL
     PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
     PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
     PNP: 002e.6 links 0 child on link 0 NULL
     PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.7 links 0 child on link 0 NULL
     PNP: 002e.8 links 0 child on link 0 NULL
     PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags
c0000400 index 70
     PNP: 002e.9 links 0 child on link 0 NULL
     PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags
c0000100 index 60
     PNP: 002e.a links 0 child on link 0 NULL
    PCI: 00:14.4 links 1 child on link 0 NULL
    PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff
flags 60080102 index 1c
    PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
    PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
    PCI: 00:14.5 links 0 child on link 0 NULL
    PCI: 00:14.5 resource base d0208000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:18.1 links 0 child on link 0 NULL
   PCI: 00:18.2 links 0 child on link 0 NULL
   PCI: 00:18.3 links 0 child on link 0 NULL
   PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26
limit febfffff flags 60000200 index 94
   PCI: 00:18.4 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:00.0 subsystem <- 1022/2b80
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 01:05.0 subsystem <- 1022/2b80
PCI: 01:05.0 cmd <- 03
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 07
PCI: 03:00.0 cmd <- 03
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 00
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/2b80
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1022/2b80
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/2b80
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/2b80
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1022/2b80
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/2b80
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/2b80
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1022/2b80
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1022/2b80
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/2b80
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b
PNP: 002e.6 missing enable_resources
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 01
PCI: 00:14.5 subsystem <- 1022/2b80
PCI: 00:14.5 cmd <- 02
PCI: 00:18.1 subsystem <- 1022/2b80
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/2b80
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/2b80
PCI: 00:18.4 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x0000d000, offset=0x00200000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 100f22
CPU: family 10, model 02, stepping 02
nodeid = 00, coreid = 00
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 2048MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 2, base: 1792MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU model: AMD Phenom(tm)9600 Quad-Core Processor
siblings = 03, CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 100f22
Sending STARTUP #2 to 1.
After apic_write.
CPU: family 10, model 02, stepping 02
Startup point 1.
Waiting for send to finish...
+nodeid = 00, coreid = 01
After Startup.
Enabling cache
Asserting INIT.

Setting fixed MTRRs(0-88) type: UC
Waiting for send to finish...
+Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
Deasserting INIT.
Waiting for send to finish...
+DONE fixed MTRRs
#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
Startup point 1.
Waiting for send to finish...
+ADDRESS_MASK_HIGH=0xffff
Sending STARTUP #2 to 2.
After apic_write.
Setting variable MTRR 1, base: 2048MB, range:  256MB, type WB
Initializing CPU #2
ADDRESS_MASK_HIGH=0xffff
Startup point 1.
Waiting for send to finish...
+Setting variable MTRR 2, base: 1792MB, range:  256MB, type UC
CPU: vendor AMD device 100f22
After Startup.
ADDRESS_MASK_HIGH=0xffff
Asserting INIT.
DONE variable MTRRs
Clear out the extra MTRR's
Waiting for send to finish...
+call enable_var_mtrr()
Leave x86_setup_var_mtrrs
CPU: family 10, model 02, stepping 02

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Deasserting INIT.
Setting up local apic...Waiting for send to finish...
+ apic_id: 0x01 done.
#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
CPU model: AMD Phenom(tm)9600 Quad-Core Processor
Startup point 1.
Waiting for send to finish...
+siblings = 03, Sending STARTUP #2 to 3.
After apic_write.
CPU #1 initialized
Startup point 1.
Waiting for send to finish...
+nodeid = 00, coreid = 02
After Startup.
Waiting for 2 CPUS to stop
Enabling cache
Initializing CPU #3

Setting fixed MTRRs(0-88) type: UC
CPU: vendor AMD device 100f22
CPU: family 10, model 02, stepping 02
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
nodeid = 00, coreid = 03
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
Enabling cache

Setting fixed MTRRs(0-88) type: UC
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
ADDRESS_MASK_HIGH=0xffff
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
Setting variable MTRR 1, base: 2048MB, range:  256MB, type WB
DONE fixed MTRRs
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
Setting variable MTRR 2, base: 1792MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xffff
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 2048MB, range:  256MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
ADDRESS_MASK_HIGH=0xffff
call enable_var_mtrr()
Setting variable MTRR 2, base: 1792MB, range:  256MB, type UC
Leave x86_setup_var_mtrrs
ADDRESS_MASK_HIGH=0xffff

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

DONE variable MTRRs
Clear out the extra MTRR's
Setting up local apic...call enable_var_mtrr()
 apic_id: 0x02 done.
Leave x86_setup_var_mtrrs
CPU model: AMD Phenom(tm)9600 Quad-Core Processor

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

siblings = 03, Setting up local apic...CPU #2 initialized
 apic_id: 0x03 done.
Waiting for 1 CPUS to stop
CPU model: AMD Phenom(tm)9600 Quad-Core Processor
siblings = 03, CPU #3 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs780_ht.c
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=9615, vendor=1002.
MEMCLK = 3
NB HT speed = 1c750a60.
CPU HT speed = 87f50a60.
HT width = 11110020.
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
In cbfs, rom address for PCI: 01:05.0 = fff4db78
On mainboard, rom address for PCI: 01:05.0 = fff4db78
PCI Expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c0
PCI ROM Image, Vendor 1002, Device 9615,
PCI ROM Image,  Class Code 030000, Code Type 00
copying VGA ROM Image from fff4db78 to 0xc0000, 0xec00 bytes
Executing Initialization Vector...
Option ROM Exit Status: 0128
Stack is clean, initialization successfull!
PCI: 00:11.0 init
sata_bar0=3020
sata_bar1=3040
sata_bar2=3028
sata_bar3=3044
sata_bar4=3000
sata_bar5=d0209000
SATA port 0 status = 13
drive detection done after 0 ms
Primary Master device is ready after 1 tries
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.1 init
PCI: 00:12.2 init
usb2_bar0=d0209400
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
usb2_bar0=d0209500
PCI: 00:14.5 init
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
Invalid CMOS LB checksum
sm_init() end
PCI: 00:14.1 init
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780
Check 
CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000
CBFS:  Could not find file pci1002,439c.rom
In cbfs, rom address for PCI: 00:14.1 = 00000000
On mainboard, rom address for PCI: 00:14.1 = 0
PCI: 00:14.2 init
base = d0200000
codec_mask = 01
codec viddid: 10ec0888
Dev=PCI: 00:14.2
Default viddid=10ec0882
Reading viddid=10ec0888
No verb!
PCI: 00:14.3 init
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PCI: 00:14.4 init
PCI: 00:18.1 init
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780
Check 
CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000
CBFS:  Could not find file pci1022,1201.rom
In cbfs, rom address for PCI: 00:18.1 = 00000000
On mainboard, rom address for PCI: 00:18.1 = 0
PCI: 00:18.2 init
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780
Check 
CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000
CBFS:  Could not find file pci1022,1202.rom
In cbfs, rom address for PCI: 00:18.2 = 00000000
On mainboard, rom address for PCI: 00:18.2 = 0
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780
Check 
CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000
CBFS:  Could not find file pci1022,1204.rom
In cbfs, rom address for PCI: 00:18.4 = 00000000
On mainboard, rom address for PCI: 00:18.4 = 0
PCI: 03:00.0 init
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0
Check fallback/coreboot_ram
CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40
Check pci1002,9615.rom
CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780
Check 
CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000
CBFS:  Could not find file pci10ec,8168.rom
In cbfs, rom address for PCI: 03:00.0 = 00000000
On card, rom address for PCI: 03:00.0 = d0100000
PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect Expansion ROM Header Signature 0000
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:18.0: enabled 1, 3 resources
PCI: 00:00.0: enabled 1, 1 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 01:05.0: enabled 1, 4 resources
PCI: 00:02.0: enabled 0, 0 resources
PCI: 00:03.0: enabled 0, 0 resources
PCI: 00:04.0: enabled 1, 3 resources
PCI: 00:05.0: enabled 0, 0 resources
PCI: 00:06.0: enabled 0, 0 resources
PCI: 00:07.0: enabled 0, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:09.0: enabled 1, 3 resources
PCI: 00:0a.0: enabled 1, 3 resources
PCI: 00:11.0: enabled 1, 6 resources
PCI: 00:12.0: enabled 1, 1 resources
PCI: 00:12.1: enabled 1, 1 resources
PCI: 00:12.2: enabled 1, 1 resources
PCI: 00:13.0: enabled 1, 1 resources
PCI: 00:13.1: enabled 1, 1 resources
PCI: 00:13.2: enabled 1, 1 resources
PCI: 00:14.5: enabled 1, 1 resources
PCI: 00:14.0: enabled 1, 2 resources
I2C: 01:50: enabled 1, 0 resources
I2C: 01:51: enabled 1, 0 resources
I2C: 01:52: enabled 1, 0 resources
I2C: 01:53: enabled 1, 0 resources
PCI: 00:14.1: enabled 1, 5 resources
PCI: 00:14.2: enabled 1, 1 resources
PCI: 00:14.3: enabled 1, 4 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 4 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.4: enabled 0, 0 resources
PNP: 002e.5: enabled 1, 3 resources
PNP: 002e.6: enabled 1, 1 resources
PNP: 002e.7: enabled 0, 0 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 0, 0 resources
PCI: 00:14.4: enabled 1, 3 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 1 resources
PCI: 00:18.4: enabled 1, 0 resources
APIC: 01: enabled 1, 0 resources
APIC: 02: enabled 1, 0 resources
APIC: 03: enabled 1, 0 resources
PCI: 03:00.0: enabled 1, 4 resources
Initializing CBMEM area to 0x7fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 7fff0200...ok
High Tables Base is 7fff0000.
Writing IRQ routing tables to 0xf0000...done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x7fff0400...done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f054c
Adding CBMEM entry as no. 3
Wrote the mp table end at: 7fff1410 - 7fff154c
MP table: 332 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 7fff2400...
ACPI:    * HPET at 7fff24e8
ACPI: added table 1/40 Length now 40
ACPI:    * MADT at 7fff2520
ACPI: added table 2/40 Length now 44
ACPI:    * SRAT at 7fff2590
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000,
sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300,
sizek=001ffd00
ACPI: added table 3/40 Length now 48
ACPI:   * SLIT at 7fff2650
ACPI: added table 4/40 Length now 52
ACPI:    * SSDT at 7fff2680
ACPI: added table 5/40 Length now 56
ACPI:    * SSDT for PState at 7fff2cb5
ACPI:    * DSDT at 7fff2cb8
ACPI:    * DSDT @ 7fff2cb8 Length 298b
ACPI:	* FACS at 7fff5648
ACPI:    * FADT at 7fff5688
pm_base: 0x0800
ACPI: added table 6/40 Length now 60
ACPI: done.
ACPI tables: 13180 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 5
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 9fde
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x7fffe000
rom_table_end = 0x7fffe000
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x7fffe000 to 0x80000000 
Adding high table area
uma_memory_start=0x70000000, uma_memory_size=0x0 
Wrote coreboot table at: 7fffe000 - 7fffe8f0  checksum dfec
coreboot table: 2288 bytes.
 0. FREE SPACE 80000000 00000000
 1. GDT        7fff0200 00000200
 2. IRQ TABLE  7fff0400 00001000
 3. SMP TABLE  7fff1400 00001000
 4. ACPI       7fff2400 0000bc00
 5. COREBOOT   7fffe000 00002000
Check CBFS header at fff7efe0
magic is 4f524243
Found CBFS header at fff7efe0
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff00038
  parameter section (skipped)
Loading segment from rom address 0xfff00054
  data (compression=0)
malloc Enter, size 36, free_mem_ptr 0023b130
malloc 0023b130
  New segment dstaddr 0x100000 memsize 0x1650d0 srcaddr 0xfff000d8
filesize 0x15980
  (cleaned up) New segment addr 0x100000 size 0x1650d0 offset 0xfff000d8
filesize 0x15980
Loading segment from rom address 0xfff00070
  data (compression=0)
malloc Enter, size 36, free_mem_ptr 0023b154
malloc 0023b154
  New segment dstaddr 0x2650d0 memsize 0x48 srcaddr 0xfff15a58 filesize
0x48
  (cleaned up) New segment addr 0x2650d0 size 0x48 offset 0xfff15a58
filesize 0x48
Loading segment from rom address 0xfff0008c
  Entry Point 0x0010008c
Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000001650d0
filesz: 0x0000000000015980
lb: [0x0000000000200000, 0x00000000002fa000)
segment: [0x0000000000100000, 0x0000000000115980, 0x00000000002650d0)
malloc Enter, size 36, free_mem_ptr 0023b178
malloc 0023b178
   early: [0x0000000000100000, 0x0000000000115980, 0x0000000000200000)
 bounce: [0x000000006fe0c000, 0x000000006fe0c000, 0x000000006fe710d0)
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000100000
filesz: 0x0000000000015980
lb: [0x0000000000200000, 0x00000000002fa000)
Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000100000
filesz: 0x0000000000015980
it's not compressed!
[ 0x0000000000100000, 0000000000115980, 0x0000000000200000) <-
00000000fff000d8
Clearing Segment: addr: 0x0000000000115980 memsz: 0x00000000000ea680
dest 00100000, end 00200000, bouncebuffer 6fe0c000
Loading Segment: addr: 0x000000006fe0c000 memsz: 0x00000000000650d0
filesz: 0x0000000000000000
lb: [0x0000000000200000, 0x00000000002fa000)
Post relocation: addr: 0x000000006fe0c000 memsz: 0x00000000000650d0
filesz: 0x0000000000000000
Loading Segment: addr: 0x00000000002650d0 memsz: 0x0000000000000048
filesz: 0x0000000000000048
lb: [0x0000000000200000, 0x00000000002fa000)
segment: [0x00000000002650d0, 0x0000000000265118, 0x0000000000265118)
 bounce: [0x000000006fe710d0, 0x000000006fe71118, 0x000000006fe71118)
Post relocation: addr: 0x000000006fe710d0 memsz: 0x0000000000000048
filesz: 0x0000000000000048
it's not compressed!
[ 0x000000006fe710d0, 000000006fe71118, 0x000000006fe71118) <-
00000000fff15a58
dest 6fe710d0, end 6fe71118, bouncebuffer 6fe0c000
Loaded segments
Jumping to boot code at 10008c
entry    = 0x0010008c
lb_start = 0x00200000
lb_size  = 0x000fa000
adjust   = 0x6fd06000
buffer   = 0x6fe0c000
     elf_boot_notes = 0x0023174c
adjusted_boot_notes = 0x6ff3774c
FILO version 0.6.0 (baozheng at localhost.localdomain) Fri Oct 30 15:43:32
CST 2009
ERROR: No such CMOS option (boot_devices)
menu: hda1:/etc/grub.conf
 
IDE time outreset failed, but slave may existhda: LBA48 250GB:
ST3250620NS                             File not found.
FILO 0.6.0
lqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq
qqkx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xmqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq
qqqj      Use the ^ and v keys to select which entry is highlighted.
Press enter to boot the selected OS, 'e' to edit the      commands
before booting, 'a' to modify the kernel arguments      before booting,
or 'c' for a command-line. Ubuntu 8.04, kernel 2.6.24-amd2-generic
x   Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial
Ubuntu 8.04, kernel 2.6.27
Ubuntu 8.04, kernel 2.6.27-tilapia
Ubuntu 8.04, kernel 2.6.24-amd2-generic (recovery mode)
Ubuntu 8.04, memtest86+
The highlighted entry will be booted automatically in 3 seconds.    The
highlighted entry will be booted automatically in 2 seconds.    The
highlighted entry will be booted automatically in 1 seconds.
Booting 'Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial'
root  (hd0,0)root arg=(hd0,0)kernel  /boot/vmlinuz-2.6.24-amd2-generic
root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro
console=ttyS0,115200initrd  /boot/initrd.img-2.6.24-amd2-generic
Booting 'Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial'
root  (hd0,0)
root arg=(hd0,0)
kernel  /boot/vmlinuz-2.6.24-amd2-generic
root=UUID=7bb9e8a5-cbc0-4104-92a3-628 f56924494 ro console=ttyS0,115200
initrd  /boot/initrd.img-2.6.24-amd2-generic
Booting 'hda1:/boot/vmlinuz-2.6.24-amd2-generic
root=UUID=7bb9e8a5-cbc0-4104-92 a3-628f56924494 ro console=ttyS0,115200
initrd=hda1:/boot/initrd.img-2.6.24-amd 2-generic'
Found Linux version 2.6.24-amd2-generic (root at forsteri) #1 SMP Tue Jul
15 22:02:29 UTC 2008 bzImage.Loading kernel... okLoading initrd...
okJumping to entry point...[    0.000000] Linux version
2.6.24-amd2-generic (root at forsteri) (gcc version 4.2.3 (Ubuntu
4.2.3-2ubuntu7)) #1 SMP Tue Jul 15 22:
02:29 UTC 2008 (Ubuntu 2.6.24-amd2.2-generic)
[    0.000000] Command line:
root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro console=ttyS0,115200
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 0000000000001000 type 16
[    0.000000]  BIOS-e820: 0000000000001000 - 00000000000a0000 (usable)
[    0.000000]  BIOS-e820: 00000000000c0000 - 0000000070000000 (usable)
[    0.000000]  BIOS-e820: 0000000070000000 - 0000000080000000
(reserved)
[    0.000000] end_pfn_map = 524288
[    0.000000] DMI not present or invalid.
[    0.000000] ACPI: RSDP signature @ 0xFFFF8100000F0800 checksum 0
[    0.000000] ACPI: RSDP 000F0800, 0014 (r0 CORE  )
[    0.000000] ACPI: RSDT 7FFF2424, 003C (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: HPET 7FFF24E8, 0038 (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: APIC 7FFF2520, 006C (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: SRAT 7FFF2590, 00C0 (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: SLIT 7FFF2650, 002D (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: SSDT 7FFF2680, 0635 (r1 AMD-FA AMD-ACPI  6040000
INTL 20061109)
[    0.000000] ACPI: FACP 7FFF5688, 00F4 (r1 CORE   COREBOOT        0
CORE        0)
[    0.000000] ACPI: DSDT 7FFF2CB8, 298B (r2 AMD    MAHOGANY    10001
INTL 20061109)
[    0.000000] ACPI: FACS 7FFF5648, 0040
[    0.000000] SRAT: PXM 0 -> APIC 0 -> Node 0
[    0.000000] SRAT: PXM 0 -> APIC 1 -> Node 0
[    0.000000] SRAT: PXM 0 -> APIC 2 -> Node 0
[    0.000000] SRAT: PXM 0 -> APIC 3 -> Node 0
[    0.000000] SRAT: Node 0 PXM 0 0-a0000
[    0.000000] SRAT: Node 0 PXM 0 0-80000000
[    0.000000] Bootmem setup node 0 0000000000000000-0000000070000000
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA             1 ->     4096
[    0.000000]   DMA32        4096 ->  1048576
[    0.000000]   Normal    1048576 ->  1048576
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[2] active PFN ranges
[    0.000000]     0:        1 ->      160
[    0.000000]     0:      192 ->   458752
[    0.000000] ATI board detected. Disabling timer routing over 8254.
[    0.000000] ACPI: PM-Timer IO Port: 0x818
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] Processor #0 (Bootup-CPU)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] Processor #1
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
[    0.000000] Processor #2
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] enabled)
[    0.000000] Processor #3
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low
level)
[    0.000000] Setting APIC routing to flat
[    0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] swsusp: Registered nosave memory region: 00000000000a0000
- 00000000000c0000
[    0.000000] Allocating PCI resources starting at 88000000 (gap:
80000000:80000000)
[    0.000000] SMP: Allowing 4 CPUs, 0 hotplug CPUs
[    0.000000] PERCPU: Allocating 34656 bytes of per cpu data
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.
Total pages: 451239
[    0.000000] Policy zone: DMA32
[    0.000000] Kernel command line:
root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro console=ttyS0,115200
[    0.000000] Initializing CPU#0
[    0.000000] PID hash table entries: 4096 (order: 12, 32768 bytes)
[    0.000000] TSC calibrated against PM_TIMER
[   30.808538] Marking TSC unstable due to TSCs unsynchronized
[   30.808539] time.c: Detected 2305.849 MHz processor.
[   30.809256] Console: colour VGA+ 80x25
[   30.809274] console [ttyS0] enabled
[   31.168194] Checking aperture...
[   31.171423] CPU 0: aperture @ f4000000 size 64 MB
[   31.187758] Memory: 1797284k/1835008k available (2466k kernel code,
37592k reserved, 1313k data, 316k init)
[   31.197502] SLUB: Genslabs=12, HWalign=64, Order=0-1, MinObjects=4,
CPUs=4, Nodes=1
[   31.282464] Calibrating delay using timer specific routine.. 4616.27
BogoMIPS (lpj=9232540)
[   31.290838] Security Framework initialized
[   31.294933] SELinux:  Disabled at boot.
[   31.298776] AppArmor: AppArmor initialized
[   31.302867] Failure registering capabilities with primary security
module.
[   31.309876] Dentry cache hash table entries: 262144 (order: 9,
2097152 bytes)
[   31.318149] Inode-cache hash table entries: 131072 (order: 8, 1048576
bytes)
[   31.325661] Mount-cache hash table entries: 256
[   31.330294] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64
bytes/line)
[   31.337413] CPU: L2 Cache: 512K (64 bytes/line)
[   31.341937] CPU 0/0 -> Node 0
[   31.344907] CPU: Physical Processor ID: 0
[   31.348911] CPU: Processor Core ID: 0
[   31.352596] SMP alternatives: switching to UP code
[   31.357900] Early unpacking initramfs... done
[   31.605568] ACPI: Core revision 20070126
[   31.610445] ACPI Warning (tbutils-0217): Incorrect checksum in table
[DSDT] -  56, should be 15 [20070126]
[   31.620113] ACPI: Looking for DSDT in initramfs... error, file
/DSDT.aml not found.
[   31.628694] ACPI Warning (tbutils-0217): Incorrect checksum in table
[DSDT] -  56, should be 15 [20070126]
[   31.639376] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b2cc offset 25F0, ignoring [20070126]
[   31.650790] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b2d6 offset 25FA, ignoring [20070126]
[   31.662188] ACPI Error (psloop-0136): Found unknown opcode 38 at AML
address ffffc2000030b2dc offset 2600, ignoring [20070126]
[   31.673610] ACPI Error (psloop-0136): Found unknown opcode E8 at AML
address ffffc2000030b2e0 offset 2604, ignoring [20070126]
[   31.685022] ACPI Error (psloop-0136): Found unknown opcode F at AML
address ffffc2000030b2e4 offset 2608, ignoring [20070126]
[   31.696346] ACPI Error (psloop-0136): Found unknown opcode 4 at AML
address ffffc2000030b2e8 offset 260C, ignoring [20070126]
[   31.707669] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b2ec offset 2610, ignoring [20070126]
[   31.719098] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b2ed offset 2611, ignoring [20070126]
[   31.730440] ACPI Error (psloop-0136): Found unknown opcode 38 at AML
address ffffc2000030b2ef offset 2613, ignoring [20070126]
[   31.741846] ACPI Error (psloop-0136): Found unknown opcode 2 at AML
address ffffc2000030b2f4 offset 2618, ignoring [20070126]
[   31.753178] ACPI Error (psloop-0136): Found unknown opcode B4 at AML
address ffffc2000030b2f8 offset 261C, ignoring [20070126]
[   31.764594] ACPI Error (psloop-0136): Found unknown opcode C6 at AML
address ffffc2000030b2f9 offset 261D, ignoring [20070126]
[   31.776014] ACPI Error (psloop-0136): Found unknown opcode E8 at AML
address ffffc2000030b300 offset 2624, ignoring [20070126]
[   31.787443] ACPI Error (psloop-0136): Found unknown opcode 2 at AML
address ffffc2000030b304 offset 2628, ignoring [20070126]
[   31.798783] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b308 offset 262C, ignoring [20070126]
[   31.810103] ACPI Error (psloop-0136): Found unknown opcode 38 at AML
address ffffc2000030b30c offset 2630, ignoring [20070126]
[   31.821513] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b310 offset 2634, ignoring [20070126]
[   31.832922] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b311 offset 2635, ignoring [20070126]
[   31.844331] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b312 offset 2636, ignoring [20070126]
[   31.855743] ACPI Error (psloop-0136): Found unknown opcode 22 at AML
address ffffc2000030b319 offset 263D, ignoring [20070126]
[   31.867171] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b31a offset 263E, ignoring [20070126]
[   31.878598] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b31c offset 2640, ignoring [20070126]
[   31.890005] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b31d offset 2641, ignoring [20070126]
[   31.901336] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b320 offset 2644, ignoring [20070126]
[   31.912755] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b321 offset 2645, ignoring [20070126]
[   31.924172] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b322 offset 2646, ignoring [20070126]
[   31.935593] ACPI Error (psloop-0136): Found unknown opcode 22 at AML
address ffffc2000030b329 offset 264D, ignoring [20070126]
[   31.947021] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b32a offset 264E, ignoring [20070126]
[   31.958448] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b32c offset 2650, ignoring [20070126]
[   31.969854] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b32d offset 2651, ignoring [20070126]
[   31.981180] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b338 offset 265C, ignoring [20070126]
[   31.992599] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b33a offset 265E, ignoring [20070126]
[   32.004009] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b348 offset 266C, ignoring [20070126]
[   32.015435] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b34a offset 266E, ignoring [20070126]
[   32.026862] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b350 offset 2674, ignoring [20070126]
[   32.038276] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b351 offset 2675, ignoring [20070126]
[   32.049694] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b352 offset 2676, ignoring [20070126]
[   32.061114] ACPI Error (psloop-0136): Found unknown opcode 22 at AML
address ffffc2000030b359 offset 267D, ignoring [20070126]
[   32.072531] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b35a offset 267E, ignoring [20070126]
[   32.083950] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b35c offset 2680, ignoring [20070126]
[   32.095379] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b35d offset 2681, ignoring [20070126]
[   32.106721] ACPI Error (psloop-0136): Found unknown opcode 2 at AML
address ffffc2000030b364 offset 2688, ignoring [20070126]
[   32.118040] ACPI Error (psloop-0136): Found unknown opcode B4 at AML
address ffffc2000030b368 offset 268C, ignoring [20070126]
[   32.129449] ACPI Error (psloop-0136): Found unknown opcode C6 at AML
address ffffc2000030b369 offset 268D, ignoring [20070126]
[   32.140858] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b36a offset 268E, ignoring [20070126]
[   32.152269] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b370 offset 2694, ignoring [20070126]
[   32.163687] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b371 offset 2695, ignoring [20070126]
[   32.175116] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b372 offset 2696, ignoring [20070126]
[   32.186545] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b378 offset 269C, ignoring [20070126]
[   32.197949] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b37a offset 269E, ignoring [20070126]
[   32.209369] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b380 offset 26A4, ignoring [20070126]
[   32.220785] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b381 offset 26A5, ignoring [20070126]
[   32.232203] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b382 offset 26A6, ignoring [20070126]
[   32.243623] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b388 offset 26AC, ignoring [20070126]
[   32.254967] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b38c offset 26B0, ignoring [20070126]
[   32.266392] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b38d offset 26B1, ignoring [20070126]
[   32.277722] ACPI Error (psloop-0136): Found unknown opcode B4 at AML
address ffffc2000030b398 offset 26BC, ignoring [20070126]
[   32.289139] ACPI Error (psloop-0136): Found unknown opcode C6 at AML
address ffffc2000030b399 offset 26BD, ignoring [20070126]
[   32.300548] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b39a offset 26BE, ignoring [20070126]
[   32.311960] ACPI Error (psloop-0136): Found unknown opcode E8 at AML
address ffffc2000030b3a0 offset 26C4, ignoring [20070126]
[   32.323390] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b3a8 offset 26CC, ignoring [20070126]
[   32.334815] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b3aa offset 26CE, ignoring [20070126]
[   32.346231] ACPI Error (psloop-0136): Found unknown opcode E8 at AML
address ffffc2000030b3b0 offset 26D4, ignoring [20070126]
[   32.357646] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b3b4 offset 26D8, ignoring [20070126]
[   32.368972] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b3b8 offset 26DC, ignoring [20070126]
[   32.380304] ACPI Error (psloop-0136): Found unknown opcode 3F at AML
address ffffc2000030b3c1 offset 26E5, ignoring [20070126]
[   32.391720] ACPI Error (psloop-0136): Found unknown opcode 23 at AML
address ffffc2000030b3c2 offset 26E6, ignoring [20070126]
[   32.403144] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b3c6 offset 26EA, ignoring [20070126]
[   32.414570] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b3cc offset 26F0, ignoring [20070126]
[   32.425967] ACPI Error (psloop-0136): Found unknown opcode 40 at AML
address ffffc2000030b3d0 offset 26F4, ignoring [20070126]
[   32.437376] ACPI Error (psloop-0136): Found unknown opcode E1 at AML
address ffffc2000030b3d1 offset 26F5, ignoring [20070126]
[   32.448785] ACPI Error (psloop-0136): Found unknown opcode 21 at AML
address ffffc2000030b3d2 offset 26F6, ignoring [20070126]
[   32.460197] ACPI Error (psloop-0136): Found unknown opcode 22 at AML
address ffffc2000030b3d9 offset 26FD, ignoring [20070126]
[   32.471612] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b3da offset 26FE, ignoring [20070126]
[   32.483044] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b3dc offset 2700, ignoring [20070126]
[   32.494470] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b3dd offset 2701, ignoring [20070126]
[   32.505791] ACPI Error (psloop-0136): Found unknown opcode E8 at AML
address ffffc2000030b3e0 offset 2704, ignoring [20070126]
[   32.517208] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b3e4 offset 2708, ignoring [20070126]
[   32.528541] ACPI Error (psloop-0136): Found unknown opcode F8 at AML
address ffffc2000030b3ec offset 2710, ignoring [20070126]
[   32.539958] ACPI Error (psloop-0136): Found unknown opcode 3 at AML
address ffffc2000030b3ed offset 2711, ignoring [20070126]
[   32.551301] ACPI Error (psloop-0136): Found unknown opcode 20 at AML
address ffffc2000030b3f0 offset 2714, ignoring [20070126]
[   32.562736] ACPI Exception (tbxface-0629): AE_AML_NO_OPERAND, While
loading namespace from ACPI tables [20070126]
[   32.573022] ACPI: Unable to load the System Description Tables
[   32.619220] Using local APIC timer interrupts.
[   32.667025] Detected 12.531 MHz APIC timer.
[   32.671279] SMP alternatives: switching to SMP code
[   32.676594] Booting processor 1/4 APIC 0x1
[   32.690947] Initializing CPU#1
[   32.771197] Calibrating delay using timer specific routine.. 4611.76
BogoMIPS (lpj=9223539)
[   32.771203] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64
bytes/line)
[   32.771205] CPU: L2 Cache: 512K (64 bytes/line)
[   32.771207] CPU 1/1 -> Node 0
[   32.771209] CPU: Physical Processor ID: 0
[   32.771209] CPU: Processor Core ID: 1
[   32.771491] AMD Phenom(tm)9600 Quad-Core Processor stepping 02
[   32.771565] SMP alternatives: switching to SMP code
[   32.816188] Booting processor 2/4 APIC 0x2
[   32.830545] Initializing CPU#2
[   32.911170] Calibrating delay using timer specific routine.. 4611.78
BogoMIPS (lpj=9223567)
[   32.911176] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64
bytes/line)
[   32.911178] CPU: L2 Cache: 512K (64 bytes/line)
[   32.911180] CPU 2/2 -> Node 0
[   32.911182] CPU: Physical Processor ID: 0
[   32.911182] CPU: Processor Core ID: 2
[   32.911464] AMD Phenom(tm)9600 Quad-Core Processor stepping 02
[   32.911563] SMP alternatives: switching to SMP code
[   32.956200] Booting processor 3/4 APIC 0x3
[   32.970563] Initializing CPU#3
[   33.051143] Calibrating delay using timer specific routine.. 4611.78
BogoMIPS (lpj=9223571)
[   33.051149] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64
bytes/line)
[   33.051151] CPU: L2 Cache: 512K (64 bytes/line)
[   33.051153] CPU 3/3 -> Node 0
[   33.051155] CPU: Physical Processor ID: 0
[   33.051155] CPU: Processor Core ID: 3
[   33.051437] AMD Phenom(tm)9600 Quad-Core Processor stepping 02
[   33.051547] Brought up 4 CPUs
[   33.094311] net_namespace: 120 bytes
[   33.098243] Time:  9:24:48  Date: 11/06/09
[   33.102355] NET: Registered protocol family 16
[   33.106938] PCI: Using configuration type 1
[   33.111546] ACPI: Interpreter disabled.
[   33.115380] Linux Plug and Play Support v0.97 (c) Adam Belay
[   33.121048] pnp: PnP ACPI: disabled
[   33.124685] PCI: Probing PCI hardware
[   33.128553] pci 0000:00:11.0: set SATA to AHCI mode
[   33.134392] PCI: Transparent bridge - 0000:00:14.4
[   33.139876] PCI: Using IRQ router default [1022/9602] at 0000:00:01.0
[   33.155160] NET: Registered protocol family 8
[   33.159516] NET: Registered protocol family 20
[   33.164035] AppArmor: AppArmor Filesystem Enabled
[   33.169016] PCI: Bridge: 0000:00:01.0
[   33.172675] Time: acpi_pm clocksource has been installed.
[   33.178085]   IO window: 1000-1fff
[   33.181507]   MEM window: d0000000-d00fffff
[   33.185693]   PREFETCH window: e0000000-efffffff
[   33.190308] PCI: Bridge: 0000:00:04.0
[   33.193972]   IO window: disabled.
[   33.197370]   MEM window: disabled.
[   33.200866]   PREFETCH window: disabled.
[   33.204793] PCI: Bridge: 0000:00:09.0
[   33.208445]   IO window: 2000-2fff
[   33.211853]   MEM window: d0100000-d01fffff
[   33.216038]   PREFETCH window: f0000000-f00fffff
[   33.220654] PCI: Bridge: 0000:00:0a.0
[   33.224305]   IO window: disabled.
[   33.227714]   MEM window: disabled.
[   33.231207]   PREFETCH window: disabled.
[   33.235130] PCI: Bridge: 0000:00:14.4
[   33.238794]   IO window: disabled.
[   33.242203]   MEM window: disabled.
[   33.245693]   PREFETCH window: disabled.
[   33.249655] NET: Registered protocol family 2
[   33.292653] IP route cache hash table entries: 65536 (order: 7,
524288 bytes)
[   33.300351] TCP established hash table entries: 262144 (order: 10,
4194304 bytes)
[   33.309736] TCP bind hash table entries: 65536 (order: 8, 1048576
bytes)
[   33.316933] TCP: Hash tables configured (established 262144 bind
65536)
[   33.323536] TCP reno registered
[   33.336701] checking if image is initramfs... it is
[   33.816286] Freeing initrd memory: 7386k freed
[   33.824783] audit: initializing netlink socket (disabled)
[   33.830195] audit(1257499488.265:1): initialized
[   33.836519] VFS: Disk quotas dquot_6.5.1
[   33.840719] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[   33.847291] io scheduler noop registered
[   33.851217] io scheduler anticipatory registered
[   33.855833] io scheduler deadline registered
[   33.860177] io scheduler cfq registered (default)
[   33.865209] assign_interrupt_mode Found MSI capability
[   33.870431] assign_interrupt_mode Found MSI capability
[   33.875648] assign_interrupt_mode Found MSI capability
[   33.900367] Real Time Clock Driver v1.12ac
[   33.904752] Linux agpgart interface v0.102
[   33.908844] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ
sharing enabled
[   33.916768] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[   33.922906] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[   33.929523] RAMDISK driver initialized: 16 RAM disks of 65536K size
1024 blocksize
[   33.937128] input: Macintosh mouse button emulation as
/devices/virtual/input/input0
[   33.944940] PNP: No PS/2 controller found. Probing ports directly.
[   33.984577] serio: i8042 KBD port at 0x60,0x64 irq 1
[   34.004456] mice: PS/2 mouse device common for all mice
[   34.009709] cpuidle: using governor ladder
[   34.013807] cpuidle: using governor menu
[   34.017846] NET: Registered protocol family 1
[   34.022250] registered taskstats version 1
[   34.026445]   Magic number: 1:807:423
[   34.030203]
/root/build/ubuntu/linux-source/linux-source/drivers/rtc/hctosys.c:
unable to open rtc device (rtc0)
[   34.040348] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
[   34.046343] EDD information not available.
[   34.050439] Freeing unused kernel memory: 316k freed
Loading, please wait...
Begin: Loading essential drivers... ...
[   34.345531] thermal: Unknown symbol acpi_processor_set_thermal_limit
Done.
Begin: Running /scripts/init-premount ...
udevd[1248]: add_to_rules: unknown key 'TEST' in
/etc/udev/rules.d/05-options.rules:6
udevd[1248]: add_to_rules: unknown key 'WAIT_FOR' in
/etc/udev/rules.d/60-persistent-storage-tape.rules:17
udevd[1248]: add_to_rules: unknown key 'TEST' in
/etc/udev/rules.d/60-persistent-storage.rules:4
udevd[1248]: add_to_rules: unknown key 'TEST' in
/etc/udev/rules.d/60-persistent-storage.rules:18
[   34.498044] SCSI subsystem initialized
[   34.517535] usbcore: registered new interface driver usbfs
[   34.523326] usbcore: registered new interface driver hub
[   34.528983] usbcore: registered new device driver usb
[   34.548593] r8169 Gigabit Ethernet driver 2.2LK loaded
[   34.553987] PCI: No IRQ known for interrupt pin A of device
0000:03:00.0. Probably buggy MP table.
[   34.563605] eth0: RTL8168c/8111c at 0xffffc2000089e000,
00:24:21:39:cb:eb, XID 3c4000c0 IRQ 508
[   34.574416] PCI: No IRQ known for interrupt pin A of device
0000:00:12.0. Probably buggy MP table.
[   34.583801] ohci_hcd 0000:00:12.0: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:12.0 setup!
[   34.592556] ohci_hcd 0000:00:12.0: init 0000:00:12.0 fail, -19
[   34.598696] PCI: No IRQ known for interrupt pin A of device
0000:00:12.1. Probably buggy MP table.
[   34.607976] ohci_hcd 0000:00:12.1: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:12.1 setup!
[   34.616759] ohci_hcd 0000:00:12.1: init 0000:00:12.1 fail, -19
[   34.624155] PCI: No IRQ known for interrupt pin A of device
0000:00:13.0. Probably buggy MP table.
[   34.633529] ohci_hcd 0000:00:13.0: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:13.0 setup!
[   34.642368] ohci_hcd 0000:00:13.0: init 0000:00:13.0 fail, -19
[   34.648489] PCI: No IRQ known for interrupt pin A of device
0000:00:13.1. Probably buggy MP table.
[   34.657823] ohci_hcd 0000:00:13.1: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:13.1 setup!
[   34.666563] ohci_hcd 0000:00:13.1: init 0000:00:13.1 fail, -19
[   34.672723] PCI: No IRQ known for interrupt pin A of device
0000:00:11.0. Probably buggy MP table.
[   34.682189] ahci 0000:00:11.0: controller can't do PMP, turning off
CAP_PMP
[   35.692034] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps
0xf impl SATA mode
[   35.700442] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo
pio slum part 
[   35.708667] scsi0 : ahci
[   35.711374] scsi1 : ahci
[   35.714077] scsi2 : ahci
[   35.716789] scsi3 : ahci
[   35.719468] ata1: SATA max UDMA/133 abar m1024 at 0xd0209000 port
0xd0209100 irq 507
[   35.727269] ata2: SATA max UDMA/133 abar m1024 at 0xd0209000 port
0xd0209180 irq 507
[   35.735025] ata3: SATA max UDMA/133 abar m1024 at 0xd0209000 port
0xd0209200 irq 507
[   35.742837] ata4: SATA max UDMA/133 abar m1024 at 0xd0209000 port
0xd0209280 irq 507
[   36.223863] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[   36.273717] ata1.00: ATA-7: ST3250620NS, 3.AEG, max UDMA/133
[   36.279620] ata1.00: 488397168 sectors, multi 0: LBA48 NCQ (depth
31/32)
[   36.331860] ata1.00: configured for UDMA/133
[   36.663749] ata2: SATA link down (SStatus 0 SControl 300)
[   36.979668] ata3: SATA link down (SStatus 0 SControl 300)
[   37.296081] ata4: SATA link down (SStatus 0 SControl 300)
[   37.301787] scsi 0:0:0:0: Direct-Access     ATA      ST3250620NS
3.AE PQ: 0 ANSI: 5
[   37.310309] PCI: No IRQ known for interrupt pin C of device
0000:00:14.5. Probably buggy MP table.
[   37.319710] ohci_hcd 0000:00:14.5: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:14.5 setup!
[   37.328578] ohci_hcd 0000:00:14.5: init 0000:00:14.5 fail, -19
[   37.334792] PCI: No IRQ known for interrupt pin B of device
0000:00:12.2. Probably buggy MP table.
[   37.344141] ehci_hcd 0000:00:12.2: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:12.2 setup!
[   37.352927] ehci_hcd 0000:00:12.2: init 0000:00:12.2 fail, -19
[   37.359874] scsi4 : pata_atiixp
[   37.364477] scsi5 : pata_atiixp
[   37.367781] ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x3010
irq 14
[   37.375075] ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x3018
irq 15
[   37.382688] Driver 'sd' needs updating - please use bus_type methods
[   37.389403] sd 0:0:0:0: [sda] 488397168 512-byte hardware sectors
(250059 MB)
[   37.396940] sd 0:0:0:0: [sda] Write Protect is off
[   37.402041] sd 0:0:0:0: [sda] Write cache: enabled, read cache:
enabled, doesn't support DPO or FUA
[   37.411556] sd 0:0:0:0: [sda] 488397168 512-byte hardware sectors
(250059 MB)
[   37.419050] sd 0:0:0:0: [sda] Write Protect is off
[   37.424060] sd 0:0:0:0: [sda] Write cache: enabled, read cache:
enabled, doesn't support DPO or FUA
[   37.433536]  sda: sda1 sda2 < sda5 >
[   37.472526] sd 0:0:0:0: [sda] Attached SCSI disk
[   37.482891] sd 0:0:0:0: Attached scsi generic sg0 type 0
[   37.711268] PCI: No IRQ known for interrupt pin B of device
0000:00:13.2. Probably buggy MP table.
[   37.720635] ehci_hcd 0000:00:13.2: Found HC with no IRQ.  Check
BIOS/PCI 0000:00:13.2 setup!
[   37.729513] ehci_hcd 0000:00:13.2: init 0000:00:13.2 fail, -19
[   37.742756] Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
[   37.749332] ide: Assuming 33MHz system bus speed for PIO modes;
override with idebus=xx
Done.
Begin: Mounting root file system... ...
Begin: Running /scripts/local-top ...
Done.
Begin: Waiting for root file system... ...
-------------- next part --------------
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From stepan at coresystems.de  Fri Nov  6 12:14:50 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 06 Nov 2009 12:14:50 +0100
Subject: [coreboot] The Linux report ACPI error since r4915.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17032F36A8@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17032F36A8@sbjgexmb1.amd.com>
Message-ID: <4AF4052A.8040603@coresystems.de>

Bao, Zheng wrote:
> Does it happen on your board.
> Output is attached.
>   

Please try updating to r4916 (or HEAD)

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From peter at stuge.se  Fri Nov  6 14:31:14 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 14:31:14 +0100
Subject: [coreboot] [PATCH] fix arima/hdama mptable.c
In-Reply-To: <2831fecf0911051049r65a0a97cxd99821fe7620165d@mail.gmail.com>
References: <2831fecf0911051049r65a0a97cxd99821fe7620165d@mail.gmail.com>
Message-ID: <20091106133114.1530.qmail@stuge.se>

Myles Watson wrote:
> Fix hard-coded paths and some warnings.
> 
> This patch enables Hugh to boot successfully every time with gcc 3.4, and
> most of the time (~29/30) with gcc 4.4.
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>



From nathan at traverse.com.au  Fri Nov  6 15:57:05 2009
From: nathan at traverse.com.au (Nathan Williams)
Date: Sat, 07 Nov 2009 01:57:05 +1100
Subject: [coreboot] GeodeLX RAM initialisation issue
In-Reply-To: <534e5dc20911050910r765107e8g11f17e215af5437@mail.gmail.com>
References: <4AF2C840.5050104@traverse.com.au>	
	<13426df10911050833w288ab0f2qd440185183b4b16f@mail.gmail.com>
	<534e5dc20911050910r765107e8g11f17e215af5437@mail.gmail.com>
Message-ID: <4AF43941.4030903@traverse.com.au>

Marc Jones wrote:
> When linux does the reset, is the coreboot output the same? Does it do
> the "Resetting the processor"?

Yes, it does "Resetting the processor after PLL configuration for the 
changes to take effect"

I captured an example of my issue:

http://coreboot.pastebin.com/m7f5ed367

I made some more observations today:

 From Linux, a reboot from the command line works fine.  It only seems 
to  die when a fsck check fails on boot and forces a reboot.  The 
motherboard doesn't have a RTC backup battery at the moment, so to test 
I have been setting the clock in Linux, shutdown, remove the power 
supply for a few seconds, then boot up again.  Because the default time 
is in 1999, Linux runs a fsck which causes it to restart and die in 
coreboot.

Once coreboot crashes, a hardware reset doesn't fix it.  Coreboot will 
always stop at the same point.  Even removing power from the motherboard 
doesn't help.  However, I did find that by swapping the SODIMM to a 
different RAM module would boot.  I know it doesn't sound very 
scientific but it's what appeared to happen.

Is it possible that coreboot or maybe SeaBIOS is using incorrect values 
from non-volatile ram?

Another observation I made was that by setting the debug_level to 
BIOS_CRIT, instead of dying at the usual spot in disable_car() and 
stopping, coreboot would reset continuously (cycling every 1-2 seconds)

Another issue that's partly related is the ability for coreboot to set 
  the GeodeLink speed depending on the detected RAM speed.  As a 
work-around, we are only using 333MHz SODIMMs and have set the bootstrap 
bits for GLCP_SYS_RSTPLL[7:1] (section 6.14.2.13 of LX databook) to 
500Mhz CPU, 333MHz GLIU instead of bypass mode.  In bypass mode, the 
GLIU is 266MHz and some of our 333MHz RAM will fail in disable_car(). 
As a test, I have experimented with
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO) in initram.c in an attempt to 
change the GLIU to 333MHz.  I probably didn't have the correct bits set, 
so even though I managed to set GLIU, it failed the last test (DLL) in 
sdram_enable() and would reset.

Nathan



From peter at stuge.se  Fri Nov  6 15:59:29 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 15:59:29 +0100
Subject: [coreboot] [v2] r4912 - trunk/src/boot
Message-ID: <20091106145929.20741.qmail@stuge.se>

svn at coreboot.org wrote:
> If the coreboot and filo overlap,

Thank you for fixing this!


> Some trailing whitespaces were deleted.

Please make whitespace changes in separate commits, so that it is
easier to find the actual code changes. If there are both code and
whitespace changes on the same line I think that is fine, because the
point is to only change the lines where code is changed.

Whitespace fixes are trivial and do not need an ack, so they can
always be made directly, before or after other changes.


Thanks again! :)

//Peter



From peter at stuge.se  Fri Nov  6 16:25:54 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 16:25:54 +0100
Subject: [coreboot] Ubiquiti embedded boards and Atheros chipset
In-Reply-To: <539341.44586.qm@web51308.mail.re2.yahoo.com>
References: <539341.44586.qm@web51308.mail.re2.yahoo.com>
Message-ID: <20091106152554.26253.qmail@stuge.se>

shane chao wrote:
> Does coreboot have any plans to support Ubiquiti embedded boards
> such as the Ministation or Litestation2/5?

coreboot does not really have plans, but it's contributors might.


> Those board are based on Atheros MIPS processors.

Right now, coreboot only runs on PC boards. There have been other
architectures in the past and it is certainly possible to support
other architectures again. However, the tasks required by firmware on
such boards are usually fairly different from the tasks required by
firmware on PCs, so while coreboot does a really good job at bus
initialization, that may not be useful on a small board without any
dynamic configuration possibilities.

Please feel free to try it out if you want! Otherwise, maybe U-Boot
or pmon could work for you?


//Peter



From patrick at georgi-clan.de  Fri Nov  6 16:28:53 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 06 Nov 2009 16:28:53 +0100
Subject: [coreboot] [PATCH] The filo crashes if the filo and coreboot
 overlap.
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17032A02A4@sbjgexmb1.amd.com>
References: <COL112-W4844EC50B4531875887A27CDB50@phx.gbl>
	<1257005604.23416.18.camel@tetris>
	<DD1CC71B621B004FA76856E5129D6B170329FCCC@sbjgexmb1.amd.com>
	<DD1CC71B621B004FA76856E5129D6B170329FFA7@sbjgexmb1.amd.com>
	<4AF05675.1010400@georgi-clan.de>
	<534e5dc20911031442n1c4d9377na70165bce69104d8@mail.gmail.com>
	<DD1CC71B621B004FA76856E5129D6B17032A02A4@sbjgexmb1.amd.com>
Message-ID: <4AF440B5.2060509@georgi-clan.de>

Am 04.11.2009 03:34, schrieb Bao, Zheng:
> Marc and Patrick,
> The LZMA compressing way doesn't work on my board. I haven't found any solution to resolve the overlapping in current code. ulzma() doesn't seem to know that overlapping happens. It is a problem that has to be solved.
>    
Thanks for your fix, but I'd like to come back to the ulzma issue.

What do you mean, that LZMA compression doesn't work on your board? 
There is a known problem that decompression takes _very_ long (several 
minutes for a moderately sized payload such as FILO).
If it looks like the boards was stuck in the decompression phase, please 
try again and wait to see if it moves on eventually (15 minutes should 
be enough with some safety margin), so we know if you ran into that 
known issue, or if you found another bug.

If it's something entirely different, I'd also like to hear about it, of 
course :-)

As for ulzma():
ulzma really doesn't know about the overlap, but the compression related 
code compensates for that. The bounce buffer function returns the start 
address of the bounce buffer. The location that is used for 
decompression is (segment_start - RAMBASE + bouncebuffer_base).
If the segment starts before the rambase, the segment is decompressed to 
the bounce buffer and the memory region before it. Right after 
decompression, the memory region before the bounce buffer is copied.
That solution has its own share of problems, but the bounce buffer 
handling code is quite nasty, and I wanted to keep the changes as small 
as possible.


Thanks,
Patrick Georgi



From svn at coreboot.org  Fri Nov  6 16:31:49 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 15:31:49 +0000
Subject: [coreboot] [v2] r4920 - trunk/src/mainboard/arima/hdama
Message-ID: <mailman.4015.1355071652.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 15:31:49 +0000 (Fri, 06 Nov 2009)
New Revision: 4920

Modified:
   trunk/src/mainboard/arima/hdama/mptable.c
Log:
Remove hard coded bus numbers from arima/hdama mptable code and fix warnings.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/src/mainboard/arima/hdama/mptable.c
===================================================================
--- trunk/src/mainboard/arima/hdama/mptable.c	2009-11-05 21:02:35 UTC (rev 4919)
+++ trunk/src/mainboard/arima/hdama/mptable.c	2009-11-06 15:31:49 UTC (rev 4920)
@@ -17,7 +17,7 @@
  * Having the proper apicid's in the table so the non-bootstrap
  *  processors can be woken up should be enough.  Linux-2.6.11 work-around.
  */
-void smp_write_processors_inorder(struct mp_config_table *mc)
+static void smp_write_processors_inorder(struct mp_config_table *mc)
 {
         int boot_apic_id;
 	int order_id;
@@ -65,7 +65,7 @@
 
 	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 	if (!dev) {
-		return 0;
+		return 0xff;
 	}
 	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
 		uint32_t config_map;
@@ -89,25 +89,25 @@
 			return bus_base;
 		}
 	}
-	return 0;
+	return 0xff;
 }
 
-unsigned max_apicid(void)
+static unsigned max_apicid(void)
 {
-	unsigned max_apicid;
+	unsigned max;
 	device_t dev;
-	max_apicid = 0;
+	max = 0;
 	for(dev = all_devices; dev; dev = dev->next) {
 		if (dev->path.type != DEVICE_PATH_APIC)
 			continue;
-		if (dev->path.apic.apic_id > max_apicid) {
-			max_apicid = dev->path.apic.apic_id;
+		if (dev->path.apic.apic_id > max) {
+			max = dev->path.apic.apic_id;
 		}
 	}
-	return max_apicid;
+	return max;
 }
 
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "LNXI    ";
@@ -152,9 +152,9 @@
 
 		/* HT chain 0 */
 		bus_chain_0 = node_link_to_bus(0, 0);
-		if (bus_chain_0 == 0) {
+		if (bus_chain_0 == 0xff) {
 			printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
-			bus_chain_0 = 1;
+			bus_chain_0 = 0;
 		}
 
 		/* 8111 */
@@ -165,7 +165,7 @@
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
 
 			bus_8111_1 = 4;
 			bus_isa = 5;
@@ -177,7 +177,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
 
 			bus_8131_1 = 2;
 		}
@@ -188,7 +188,7 @@
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
 
 			bus_8131_2 = 3;
 		}
@@ -318,29 +318,38 @@
 	return smp_next_mpe_entry(mc);
 }
 
-void reboot_if_hotswap(void)
+static void reboot_if_hotswap(void)
 {
 	/* Hack patch work around for hot swap enable 33mhz problem */
 	device_t dev;
 	uint32_t data;
 	unsigned long htic;
 	int reset;
-	int i;
 
+	unsigned bus_chain_0 = node_link_to_bus(0, 0);
+
 	reset = 0;
 	printk_debug("Looking for bad PCIX MHz input\n");
-	dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
-	data = pci_read_config32(dev, 0xa0);
-	if(!(((data>>16)&0x03)==0x03)) {
-		reset=1;
-		printk_debug("Bad PCIX MHz - Reset\n");
+	dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
+	if (!dev)
+		printk_debug("Couldn't find %02x:02.0 \n", bus_chain_0);
+	else {
+		data = pci_read_config32(dev, 0xa0);
+		if(!(((data>>16)&0x03)==0x03)) {
+			reset=1;
+			printk_debug("Bad PCIX MHz - Reset\n");
+		}
 	}
 	printk_debug("Looking for bad Hot Swap Enable\n");
-	dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
-	data = pci_read_config32(dev, 0x48);
-	if(data & 0x0c) {
-		reset=1;
-		printk_debug("Bad Hot Swap start - Reset\n");
+	dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
+	if (!dev)
+		printk_debug("Couldn't find %02x:01.0 \n", bus_chain_0);
+	else {
+		data = pci_read_config32(dev, 0x48);
+		if(data & 0x0c) {
+			reset=1;
+			printk_debug("Bad Hot Swap start - Reset\n");
+		}
 	}
 	if(reset) {
 		/* enable cf9 */




From peter at stuge.se  Fri Nov  6 16:31:34 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 16:31:34 +0100
Subject: [coreboot] PX10000G aka Pico ITX
In-Reply-To: <c526af120911031944x2af050b2t937f3e288578bae0@mail.gmail.com>
References: <c526af120911031944x2af050b2t937f3e288578bae0@mail.gmail.com>
Message-ID: <20091106153135.27159.qmail@stuge.se>

Hi Elkton,

elkton gen wrote:
> http://en.wikipedia.org/wiki/Pico-ITX#PX10000G is the device I'm
> targeting but you don't seem to support this, I would like to add this
> device, it has:
> 
> VIA VX700 Chipset (you only support VX800 or CX700)
> VIA C7-M Processor.
> VIA VT6106S
> VIA VT1708A
> 
> By the looks of it only the CPU is support.  So a bit of work to be
> done...

Yes, but I believe VX700 is similar to CX700 so it may not be that
much.

Neither VT6106 ethernet nor VT1708 codec needs coreboot support.

If there is a superio chip you may need to add support for that.

I suggest that you start working from an existing board in coreboot
which uses the cx700 code.


> If anybody can point me to any datasheets for these parts

http://www.coreboot.org/Datasheets#VIA_CX700M.2FVX700


> and/or a contact at VIA who might be helpful in getting access to
> the information I require this, would be great.

There are no such contacts at VIA but there is a lot of information
available online, and please feel free to ask on this mailing list!


//Peter



From mylesgw at gmail.com  Fri Nov  6 16:32:15 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 09:32:15 -0600
Subject: [coreboot] [PATCH] fix arima/hdama mptable.c
In-Reply-To: <20091106133114.1530.qmail@stuge.se>
References: <2831fecf0911051049r65a0a97cxd99821fe7620165d@mail.gmail.com>
	<20091106133114.1530.qmail@stuge.se>
Message-ID: <2831fecf0911060732q38975adbwc12eac229e036319@mail.gmail.com>

On Fri, Nov 6, 2009 at 7:31 AM, Peter Stuge <peter at stuge.se> wrote:

> Myles Watson wrote:
> > Fix hard-coded paths and some warnings.
> >
> > This patch enables Hugh to boot successfully every time with gcc 3.4, and
> > most of the time (~29/30) with gcc 4.4.
> >
> > Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Acked-by: Peter Stuge <peter at stuge.se>
>
Rev 4920.

Thanks,
Myles
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From peter at stuge.se  Fri Nov  6 17:18:57 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 17:18:57 +0100
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <4AF29851.9000902@coresystems.de>
	<808D748A06A04C8DA0CC4E66ED079386@chimp>
References: <hc6lsa$hqg$1@ger.gmane.org> <4AF1C281.3030502@csr.com>
	<4AF29851.9000902@coresystems.de> <hc6lsa$hqg$1@ger.gmane.org>
	<4AF1C281.3030502@csr.com> <808D748A06A04C8DA0CC4E66ED079386@chimp>
Message-ID: <20091106161857.3916.qmail@stuge.se>

Myles Watson wrote:
> I don't think we should depend on the value from the card.  The
> point of that check is to make sure we don't run the wrong types of
> ROMs. One way to work around it would be to correct the VGA BIOS
> from your card and put it into CBFS.

Stefan Reinauer wrote:
> > Ping.
> 
> Awesome!

Stefan, what about Myles' comment above? I think it's a good point.


//Peter



From mylesgw at gmail.com  Fri Nov  6 17:31:24 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 10:31:24 -0600
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <20091106161857.3916.qmail@stuge.se>
References: <hc6lsa$hqg$1@ger.gmane.org> <4AF1C281.3030502@csr.com>
	<4AF29851.9000902@coresystems.de>
	<808D748A06A04C8DA0CC4E66ED079386@chimp>
	<20091106161857.3916.qmail@stuge.se>
Message-ID: <2831fecf0911060831i3d37a604o25338e62ab9d33f4@mail.gmail.com>

On Fri, Nov 6, 2009 at 10:18 AM, Peter Stuge <peter at stuge.se> wrote:

> Myles Watson wrote:
> > I don't think we should depend on the value from the card.  The
> > point of that check is to make sure we don't run the wrong types of
> > ROMs. One way to work around it would be to correct the VGA BIOS
> > from your card and put it into CBFS.
>
> Stefan, what about Myles' comment above? I think it's a good point.
>

We started discussing it off list.  This should catch the list up:

On Thu, Nov 5, 2009 at 11:03 AM, Stefan Reinauer <stepan at coresystems.de>wrote:

> Myles Watson wrote:
> > Did you see my concern with checking the device instead of the ROM?
> >
> > Thanks,
> > Myles
> oops sorry.. I missed that one..
>
No problem.


> Hm.. not sure.. that particular check does not seem to be a consistency
> check but rather a check to determine from which location to run the VGA
> OPROM from... Generally, VGA oproms should run from 0xc0000.
>
Yes.  His card is broken.  I just wanted to make sure the change doesn't
break other things to enable his 10-year-old card.


> Maybe we should add another check whether class of the card and class of
> the device are the same?
>
If we did, that would break his card again.

I guess someone will complain if/when it matters.  I'm not sure what the
"right" thing to do is.

Thanks,
Myles
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From mylesgw at gmail.com  Fri Nov  6 17:37:19 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 10:37:19 -0600
Subject: [coreboot] [PATCH] __ROMCC__ ifdefs
In-Reply-To: <2831fecf0910300624r4a23f007p69347683e0070a96@mail.gmail.com>
References: <2831fecf0910300624r4a23f007p69347683e0070a96@mail.gmail.com>
Message-ID: <2831fecf0911060837gb115f83i44f4460e7ae0fdf1@mail.gmail.com>

On Fri, Oct 30, 2009 at 7:24 AM, Myles Watson <mylesgw at gmail.com> wrote:

> I think it's time to separate the two meanings of __ROMCC__.  Right now it
> is used for:
> 1. Use simple functions and data types since we don't have RAM
> 2. Don't use prototypes, romcc doesn't support them.
>
> Right now the patch creates __PRE_RAMINIT__
>
> The name is not the most important part of the patch, and can easily be
> changed.
>
> Here are some of the suggestions so far:
> __PRE_RAM__
> __NO_RAM_YET__
> __DURING_RAMINIT__
> __USE_NO_RAM__
>
> Unless it was obvious to me which meaning was the correct one for a file, I
> added both for now.
>
> Abuild tested.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
Same patch with __PRE_RAM__

Still abuild-tested.

Thanks,
Myles
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From peter at stuge.se  Fri Nov  6 17:44:44 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 17:44:44 +0100
Subject: [coreboot] [PATCH] __ROMCC__ ifdefs
In-Reply-To: <2831fecf0911060837gb115f83i44f4460e7ae0fdf1@mail.gmail.com>
References: <2831fecf0910300624r4a23f007p69347683e0070a96@mail.gmail.com>
	<2831fecf0911060837gb115f83i44f4460e7ae0fdf1@mail.gmail.com>
Message-ID: <20091106164444.8722.qmail@stuge.se>

Myles Watson wrote:
> > I think it's time to separate the two meanings of __ROMCC__.
> >
> > Signed-off-by: Myles Watson <mylesgw at gmail.com>
> 
> Same patch with __PRE_RAM__
> 
> Still abuild-tested.

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Fri Nov  6 18:02:52 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 17:02:52 +0000
Subject: [coreboot] [v2] r4921 - in trunk/src: arch/i386/include/arch
	arch/i386/lib cpu/amd/dualcore cpu/amd/microcode
	cpu/amd/model_10xxx cpu/amd/quadcore cpu/x86/smm drivers
	include include/cpu/amd include/cpu/x86 lib
	mainboard/amd/dbm690t mainboard/amd/pistachio
	mainboard/amd/serengeti_cheetah
	mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama
	mainboard/asus/a8n_e mainboard/asus/a8v-e_se
	mainboard/asus/m2v-mx_se mainboard/broadcom/blast
	mainboard/dell/s1850 mainboard/gigabyte/ga_2761gxdk
	mainboard/gigabyte/m57sli mainboard/hp/dl145_g3
	mainboard/ibm/e325 mainboard/ibm/e326
	mainboard/intel/d945gclf mainboard/intel/eagleheights
	mainboard/intel/jarrell mainboard/intel/xe7501devkit
	mainboard/iwill/dk8_htx mainboard/iwill/dk8s2
	mainboard/iwill/dk8x mainboard/kontron/986lcd-m
	mainboard/kontron/kt690 mainboard/msi/ms7135
	mainboard/msi/ms7260 mainboard/msi/ms9185
	mainboard/msi/ms9282 mainboard/newisys/khepri
	mainboard/nvidia/l1_2pvv mainboard/sunw/ultra40
	mainboard/supermicro/h8dme mainboard/supermicro/h8dmr
	mainboard/supermicro/h8dmr_fam10 mainboard/supermicro/x6dai_g
	mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2
	mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2
	mainboard/technexion/tim5690 mainboard/technexion/tim8690
	mainboard/tyan/s2735 mainboard/tyan/s2850
	mainboard/tyan/s2875 mainboard/tyan/s2880
	mainboard/tyan/s2881 mainboard/tyan/s2882
	mainboard/tyan/s2885 mainboard/tyan/s2891
	mainboard/tyan/s2892 mainboard/tyan/s2895
	mainboard/tyan/s2912 mainboard/tyan/s2912_fam10
	mainboard/tyan/s4880 mainboard/tyan/s4882
	mainboard/via/epia-m700 northbridge/amd/amdfam10
	northbridge/amd/amdk8 northbridge/via/cn700
	northbridge/via/vx800/examples southbridge/amd/cs5530
	southbridge/intel/i82371eb southbridge/intel/i82801ca
	southbridge/intel/i82801gx southbridge/intel/i82801xx
Message-ID: <mailman.4016.1355071652.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 17:02:51 +0000 (Fri, 06 Nov 2009)
New Revision: 4921

Removed:
   trunk/src/drivers/pci/
Modified:
   trunk/src/arch/i386/include/arch/cpu.h
   trunk/src/arch/i386/include/arch/hlt.h
   trunk/src/arch/i386/include/arch/io.h
   trunk/src/arch/i386/lib/console_print.c
   trunk/src/cpu/amd/dualcore/dualcore_id.c
   trunk/src/cpu/amd/microcode/microcode.c
   trunk/src/cpu/amd/model_10xxx/apic_timer.c
   trunk/src/cpu/amd/model_10xxx/update_microcode.c
   trunk/src/cpu/amd/quadcore/quadcore_id.c
   trunk/src/cpu/x86/smm/smmrelocate.S
   trunk/src/include/assert.h
   trunk/src/include/cpu/amd/dualcore.h
   trunk/src/include/cpu/amd/model_fxx_rev.h
   trunk/src/include/cpu/amd/mtrr.h
   trunk/src/include/cpu/amd/quadcore.h
   trunk/src/include/cpu/x86/cache.h
   trunk/src/include/cpu/x86/lapic.h
   trunk/src/include/cpu/x86/msr.h
   trunk/src/include/cpu/x86/mtrr.h
   trunk/src/include/cpu/x86/tsc.h
   trunk/src/include/stdlib.h
   trunk/src/include/string.h
   trunk/src/lib/cbmem.c
   trunk/src/lib/usbdebug_direct.c
   trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
   trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c
   trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c
   trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
   trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c
   trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
   trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
   trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
   trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c
   trunk/src/mainboard/dell/s1850/reset.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
   trunk/src/mainboard/gigabyte/m57sli/apc_auto.c
   trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
   trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
   trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c
   trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c
   trunk/src/mainboard/intel/d945gclf/auto.c
   trunk/src/mainboard/intel/eagleheights/auto.c
   trunk/src/mainboard/intel/eagleheights/reset.c
   trunk/src/mainboard/intel/jarrell/reset.c
   trunk/src/mainboard/intel/xe7501devkit/auto.c
   trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
   trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
   trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
   trunk/src/mainboard/kontron/986lcd-m/auto.c
   trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c
   trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c
   trunk/src/mainboard/msi/ms7260/apc_auto.c
   trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c
   trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c
   trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c
   trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c
   trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c
   trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
   trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
   trunk/src/mainboard/supermicro/h8dme/apc_auto.c
   trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
   trunk/src/mainboard/supermicro/h8dmr/apc_auto.c
   trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
   trunk/src/mainboard/supermicro/x6dai_g/reset.c
   trunk/src/mainboard/supermicro/x6dhe_g/reset.c
   trunk/src/mainboard/supermicro/x6dhe_g2/reset.c
   trunk/src/mainboard/supermicro/x6dhr_ig/reset.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c
   trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
   trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2895/failover.c
   trunk/src/mainboard/tyan/s2912/apc_auto.c
   trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c
   trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c
   trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c
   trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c
   trunk/src/northbridge/amd/amdfam10/amdfam10.h
   trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c
   trunk/src/northbridge/amd/amdk8/amdk8_f.h
   trunk/src/northbridge/via/cn700/cn700.h
   trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
   trunk/src/southbridge/amd/cs5530/cs5530.h
   trunk/src/southbridge/intel/i82371eb/i82371eb.h
   trunk/src/southbridge/intel/i82801ca/i82801ca.h
   trunk/src/southbridge/intel/i82801gx/i82801gx.h
   trunk/src/southbridge/intel/i82801xx/i82801xx.h
Log:
Split the two usages of __ROMCC__:
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."

There are probably some places where both are tested, but only one is needed.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/src/arch/i386/include/arch/cpu.h
===================================================================
--- trunk/src/arch/i386/include/arch/cpu.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/arch/i386/include/arch/cpu.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -104,7 +104,7 @@
 #define X86_VENDOR_SIS       10 
 #define X86_VENDOR_UNKNOWN 0xff
 
-#if !defined( __ROMCC__ ) && defined( __GNUC__)
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__)
 #include <device/device.h>
 
 

Modified: trunk/src/arch/i386/include/arch/hlt.h
===================================================================
--- trunk/src/arch/i386/include/arch/hlt.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/arch/i386/include/arch/hlt.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #ifndef ARCH_HLT_H
 #define ARCH_HLT_H
 
-#if defined( __ROMCC__) && !defined(__GNUC__)
+#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__)
 static void hlt(void)
 {
 	__builtin_hlt();

Modified: trunk/src/arch/i386/include/arch/io.h
===================================================================
--- trunk/src/arch/i386/include/arch/io.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/arch/i386/include/arch/io.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -9,7 +9,7 @@
  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
  * versions of the single-IO instructions (inb_p/inw_p/..).
  */
-#if defined( __ROMCC__ ) && !defined (__GNUC__) 
+#if defined( __ROMCC__ ) && !defined (__GNUC__)
 static inline void outb(uint8_t value, uint16_t port)
 {
 	__builtin_outb(value, port);

Modified: trunk/src/arch/i386/lib/console_print.c
===================================================================
--- trunk/src/arch/i386/lib/console_print.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/arch/i386/lib/console_print.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -66,7 +66,7 @@
  * set in some auto.c files to trigger the simple device_t version to be used.
  * So __GNUCC__ does the right thing here.
  */
-#if defined (__GNUCC__)
+#if defined (__ROMCC__)
 #define STATIC
 #else
 #define STATIC static

Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c
===================================================================
--- trunk/src/cpu/amd/dualcore/dualcore_id.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/amd/dualcore/dualcore_id.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -2,7 +2,7 @@
 
 #include <arch/cpu.h>
 #include <cpu/amd/dualcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 #include <cpu/amd/model_fxx_msr.h>
 #endif
 

Modified: trunk/src/cpu/amd/microcode/microcode.c
===================================================================
--- trunk/src/cpu/amd/microcode/microcode.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/amd/microcode/microcode.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 
 #include <stdint.h>
 #include <console/console.h>

Modified: trunk/src/cpu/amd/model_10xxx/apic_timer.c
===================================================================
--- trunk/src/cpu/amd/model_10xxx/apic_timer.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/amd/model_10xxx/apic_timer.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,8 +23,8 @@
 #include <cpu/x86/lapic.h>
 
 /* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (ROMCC). Don't use init_timer() and  udelay is redirected
- * to udelay_tsc().
+ * pre-memory init (__PRE_RAM__). Don't use init_timer() and  udelay is
+ * redirected to udelay_tsc().
  */
 
 

Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c
===================================================================
--- trunk/src/cpu/amd/model_10xxx/update_microcode.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/amd/model_10xxx/update_microcode.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -29,7 +29,7 @@
 
 static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 
 /* From the Revision Guide :
  * Equivalent Processor Table for AMD Family 10h Processors

Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c
===================================================================
--- trunk/src/cpu/amd/quadcore/quadcore_id.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/amd/quadcore/quadcore_id.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
 
 #include <arch/cpu.h>
 #include <cpu/amd/quadcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 #include <cpu/amd/model_10xxx_msr.h>
 #endif
 

Modified: trunk/src/cpu/x86/smm/smmrelocate.S
===================================================================
--- trunk/src/cpu/x86/smm/smmrelocate.S	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/cpu/x86/smm/smmrelocate.S	2009-11-06 17:02:51 UTC (rev 4921)
@@ -22,7 +22,7 @@
 #include <arch/asm.h>
 
 // Make sure no stage 2 code is included:
-#define __ROMCC__
+#define __PRE_RAM__
 
 // FIXME: Is this piece of code southbridge specific, or 
 // can it be cleaned up so this include is not required?

Modified: trunk/src/include/assert.h
===================================================================
--- trunk/src/include/assert.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/assert.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -24,7 +24,7 @@
 // ROMCC doesn't support __FILE__ or __LINE__  :^{
 
 #if CONFIG_DEBUG
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 #define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
 #else
 #define ASSERT(x)	{ 				\
@@ -39,7 +39,7 @@
 #define ASSERT(x)	{ }
 #endif
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 #define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
 #else
 #define BUG()		{ 				\

Modified: trunk/src/include/cpu/amd/dualcore.h
===================================================================
--- trunk/src/include/cpu/amd/dualcore.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/amd/dualcore.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -15,7 +15,7 @@
 struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
 #endif
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 struct device;
 unsigned get_apicid_base(unsigned ioapic_num);
 void amd_sibling_init(struct device *cpu);

Modified: trunk/src/include/cpu/amd/model_fxx_rev.h
===================================================================
--- trunk/src/include/cpu/amd/model_fxx_rev.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/amd/model_fxx_rev.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -49,7 +49,7 @@
 }
 
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 static int is_e0_later_in_bsp(int nodeid)
 {
         uint32_t val;
@@ -96,7 +96,7 @@
         return (cpuid_eax(1) & 0xfff0f) <  0x40f02;
 }
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 //AMD_F0_SUPPORT
 static int is_cpu_f0_in_bsp(int nodeid)
 {

Modified: trunk/src/include/cpu/amd/mtrr.h
===================================================================
--- trunk/src/include/cpu/amd/mtrr.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/amd/mtrr.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -31,7 +31,7 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
-#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
+#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 void amd_setup_mtrrs(void);
 #endif /* __ROMCC__ */
 

Modified: trunk/src/include/cpu/amd/quadcore.h
===================================================================
--- trunk/src/include/cpu/amd/quadcore.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/amd/quadcore.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -34,7 +34,7 @@
 struct node_core_id get_node_core_id(u32 nb_cfg_54);
 #endif
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 struct device;
 u32 get_apicid_base(u32 ioapic_num);
 void amd_sibling_init(struct device *cpu);

Modified: trunk/src/include/cpu/x86/cache.h
===================================================================
--- trunk/src/include/cpu/x86/cache.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/x86/cache.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -41,7 +41,7 @@
 	wbinvd();
 }
 
-#if !defined( __ROMCC__)  && defined (__GNUC__)
+#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__)
 void x86_enable_cache(void);
 #endif /* !__ROMCC__ */
 

Modified: trunk/src/include/cpu/x86/lapic.h
===================================================================
--- trunk/src/include/cpu/x86/lapic.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/x86/lapic.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -68,7 +68,7 @@
 }
 #endif
 
-#if ! defined (__ROMCC__)
+#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
 
 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 
@@ -157,6 +157,6 @@
 #endif /* CONFIG_SMP */
 
 
-#endif /* !__ROMCC__ */
+#endif /* !__ROMCC__ && !__PRE_RAM__ */
 
 #endif /* CPU_X86_LAPIC_H */

Modified: trunk/src/include/cpu/x86/msr.h
===================================================================
--- trunk/src/include/cpu/x86/msr.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/x86/msr.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #ifndef CPU_X86_MSR_H
 #define CPU_X86_MSR_H
 
-#if defined( __ROMCC__) && !defined (__GNUC__)
+#if defined( __ROMCC__)
 
 typedef __builtin_msr_t msr_t;
 
@@ -43,7 +43,7 @@
 		);
 }
 
-#endif /* ROMCC__ && !__GNUC__ */
+#endif /* __ROMCC__ */
 
 
 #endif /* CPU_X86_MSR_H */

Modified: trunk/src/include/cpu/x86/mtrr.h
===================================================================
--- trunk/src/include/cpu/x86/mtrr.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/x86/mtrr.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -32,7 +32,7 @@
 #define MTRRfix4K_F8000_MSR 0x26f
 
 
-#if !defined(__ROMCC__) && !defined (ASSEMBLY)
+#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 
 #include <device/device.h>
 

Modified: trunk/src/include/cpu/x86/tsc.h
===================================================================
--- trunk/src/include/cpu/x86/tsc.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/cpu/x86/tsc.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -17,7 +17,7 @@
 	return res;
 }
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__)
 static inline unsigned long long rdtscll(void)
 {
 	unsigned long long val;

Modified: trunk/src/include/stdlib.h
===================================================================
--- trunk/src/include/stdlib.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/stdlib.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -11,7 +11,7 @@
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 #define MAX(a,b) ((a) > (b) ? (a) : (b))
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 void *malloc(size_t size);
 void free(void *ptr);
 #endif

Modified: trunk/src/include/string.h
===================================================================
--- trunk/src/include/string.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/include/string.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -8,7 +8,7 @@
 void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t n);
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 int sprintf(char * buf, const char *fmt, ...);
 #endif
 
@@ -41,7 +41,7 @@
 	return 0;
 }
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 static inline char *strdup(const char *s)
 {   
 	size_t sz = strlen(s) + 1;

Modified: trunk/src/lib/cbmem.c
===================================================================
--- trunk/src/lib/cbmem.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/lib/cbmem.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -45,7 +45,7 @@
 	u64 size;
 } __attribute__((packed));
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 struct cbmem_entry *bss_cbmem_toc;
 #endif
 
@@ -64,7 +64,7 @@
 	struct cbmem_entry *cbmem_toc;
 	cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 	bss_cbmem_toc = cbmem_toc;
 #endif
 	
@@ -91,7 +91,7 @@
 	cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
 
 	debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr);
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 	bss_cbmem_toc = cbmem_toc;
 #endif
 
@@ -102,7 +102,7 @@
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 	 cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
 #else
 	 cbmem_toc = bss_cbmem_toc;
@@ -158,7 +158,7 @@
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 	 cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
 #else
 	 cbmem_toc = bss_cbmem_toc;
@@ -175,7 +175,7 @@
 	return (void *)NULL;
 }
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 #if CONFIG_HAVE_ACPI_RESUME
 extern u8 acpi_slp_type;
 #endif
@@ -199,12 +199,12 @@
 	cbmem_arch_init();
 }
 
-#ifndef __ROMCC__
+#ifndef __PRE_RAM__
 void cbmem_list(void)
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 	 cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
 #else
 	 cbmem_toc = bss_cbmem_toc;

Modified: trunk/src/lib/usbdebug_direct.c
===================================================================
--- trunk/src/lib/usbdebug_direct.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/lib/usbdebug_direct.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -19,7 +19,7 @@
 /*
  *	2006.12.10 yhlu moved it to corbeoot and use struct instead
  */
-#ifndef __ROMCC__
+#if !defined(__ROMCC__)
 #include <console/console.h>
 #else
 #if CONFIG_USE_PRINTK_IN_CAR==0

Modified: trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1

Modified: trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1

Modified: trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
===================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -19,7 +19,7 @@
 
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define SYSTEM_TYPE 0	/* SERVER */
 //#define SYSTEM_TYPE 1	/* DESKTOP */

Modified: trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>

Modified: trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -22,7 +22,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 /* Used by it8712f_enable_serial(). */
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)

Modified: trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,7 +23,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,7 +23,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define QRANK_DIMM_SUPPORT 1
 

Modified: trunk/src/mainboard/dell/s1850/reset.c
===================================================================
--- trunk/src/mainboard/dell/s1850/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/dell/s1850/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -2,7 +2,7 @@
 
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/pci.h>
 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
 	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -22,7 +22,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -22,7 +22,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- trunk/src/mainboard/gigabyte/m57sli/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/gigabyte/m57sli/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -26,7 +26,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/intel/d945gclf/auto.c
===================================================================
--- trunk/src/mainboard/intel/d945gclf/auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/intel/d945gclf/auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__ 
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <string.h>
@@ -220,10 +220,10 @@
 #include <cbmem.h>
 
 // Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the 
+// __PRE_RAM__ being set during CAR stage (in order to compile the
 // BSS free versions of the functions). Either rewrite the code
 // to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
 //
 #include "lib/cbmem.c"
 

Modified: trunk/src/mainboard/intel/eagleheights/auto.c
===================================================================
--- trunk/src/mainboard/intel/eagleheights/auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/intel/eagleheights/auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  * MA 02110-1301 USA
  */
 
-#define __ROMCC__
+#define __PRE_RAM__
 
 #include <delay.h>
 

Modified: trunk/src/mainboard/intel/eagleheights/reset.c
===================================================================
--- trunk/src/mainboard/intel/eagleheights/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/intel/eagleheights/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/intel/jarrell/reset.c
===================================================================
--- trunk/src/mainboard/intel/jarrell/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/intel/jarrell/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/intel/xe7501devkit/auto.c
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/intel/xe7501devkit/auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,4 +1,5 @@
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>

Modified: trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/kontron/986lcd-m/auto.c
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/kontron/986lcd-m/auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -19,8 +19,8 @@
  * MA 02110-1301 USA
  */
 
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__ 
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <string.h>
@@ -359,10 +359,10 @@
 #include <cbmem.h>
 
 // Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the 
+// __PRE_RAM__ being set during CAR stage (in order to compile the
 // BSS free versions of the functions). Either rewrite the code
 // to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
 //
 #include "lib/cbmem.c"
 

Modified: trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -19,7 +19,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1

Modified: trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,7 +23,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/msi/ms7260/apc_auto.c
===================================================================
--- trunk/src/mainboard/msi/ms7260/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/msi/ms7260/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -21,7 +21,7 @@
 
 #define ASSEMBLY 1
 
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -21,7 +21,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 // #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 // #define DEBUG_SMBUS 1

Modified: trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -24,7 +24,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,7 +23,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -4,7 +4,7 @@
  * Additional (C) 2007 coresystems GmbH 
  */
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c
===================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 
 #define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/supermicro/h8dme/apc_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dme/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -17,7 +17,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dmr/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/supermicro/x6dai_g/reset.c
===================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/x6dai_g/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/supermicro/x6dhe_g/reset.c
===================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/x6dhe_g/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/reset.c
===================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/reset.c
===================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c
===================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>

Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1

Modified: trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1

Modified: trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define QRANK_DIMM_SUPPORT 1
 

Modified: trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1

Modified: trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define QRANK_DIMM_SUPPORT 1
 

Modified: trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define K8_ALLOCATE_IO_RANGE 1
 

Modified: trunk/src/mainboard/tyan/s2895/failover.c
===================================================================
--- trunk/src/mainboard/tyan/s2895/failover.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2895/failover.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s2912/apc_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2912/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2912/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0

Modified: trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -20,7 +20,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
 

Modified: trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
  
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c
===================================================================
--- trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -23,7 +23,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 

Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h
===================================================================
--- trunk/src/northbridge/amd/amdfam10/amdfam10.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/northbridge/amd/amdfam10/amdfam10.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -956,7 +956,7 @@
 
 #include "amdfam10_nums.h"
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 #if NODE_NUMS==64
 	 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
@@ -1086,7 +1086,7 @@
 
 #if CONFIG_AMDMCT == 0
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 static void soft_reset(void);
 #endif
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
@@ -1131,7 +1131,7 @@
 	}
 
 	for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
 		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
@@ -1148,7 +1148,7 @@
 		}
 	}
 	if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else

Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c
===================================================================
--- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 typedef struct sys_info sys_info_conf_t;
 #else
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
@@ -32,7 +32,7 @@
 {
 	device_t dev;
 	struct dram_base_mask_t d;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
 #else
 	dev = __f1_dev[0];
@@ -88,7 +88,7 @@
 #endif
 
 	for(i=0;i<nodes;i++) {
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 		dev = NODE_PCI(i, 1);
 #else
 		dev = __f1_dev[i];
@@ -108,7 +108,7 @@
 #endif
 	}
 
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(nodeid, 1);
 #else
 	dev = __f1_dev[nodeid];
@@ -122,7 +122,7 @@
 static void set_DctSelBaseAddr(u32 i, u32 sel_m)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 		dev = __f2_dev[i];
@@ -139,7 +139,7 @@
 static u32 get_DctSelBaseAddr(u32 i)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 		dev = __f2_dev[i];
@@ -156,7 +156,7 @@
 static void set_DctSelHiEn(u32 i, u32 val)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 		dev = __f2_dev[i];
@@ -172,7 +172,7 @@
 static u32 get_DctSelHiEn(u32 i)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 	dev = __f2_dev[i];
@@ -187,7 +187,7 @@
 static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 	dev = __f2_dev[i];
@@ -203,7 +203,7 @@
 static u32 get_DctSelBaseOffset(u32 i)
 {
 	device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 2);
 #else
 	dev = __f2_dev[i];
@@ -264,7 +264,7 @@
 	d = get_dram_base_mask(i);
 	d.mask += (carry_over>>9);
 	set_dram_base_mask(i,d, nodes);
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(i, 1);
 #else
 	dev = __f1_dev[i];
@@ -330,7 +330,7 @@
 	index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
 
 	// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(nodeid, 1);
 #else
 	dev = __f1_dev[nodeid];
@@ -393,7 +393,7 @@
 #endif
 		tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
 		for(i=0; i<nodes; i++) {
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -433,7 +433,7 @@
 	if(ht_c_index<4) {
 #endif
 		for(i=0; i<nodes; i++) {
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -480,7 +480,7 @@
 }
 #endif
 
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 					u32 io_min, u32 io_max, u32 nodes)
 {
@@ -494,7 +494,7 @@
 		/* io range allocation */
 		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
 		for(i=0; i<nodes; i++) {
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -503,7 +503,7 @@
 		}
 		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
 		for(i=0; i<nodes; i++){
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -546,7 +546,7 @@
 #endif
 		 /* io range allocation */
 		for(i=0; i<nodes; i++) {
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -584,7 +584,7 @@
 	for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
 		u32 i;
 		for(i=0; i<nodes; i++) {
-		#if defined(__ROMCC__)
+		#if defined(__PRE_RAM__)
 			dev = NODE_PCI(i, 1);
 		#else
 			dev = __f1_dev[i];
@@ -664,7 +664,7 @@
 	u32 dword;
 	device_t dev;
 
-#if defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 	dev = NODE_PCI(node, 0);
 #else
 	dev = __f0_dev[node];
@@ -677,7 +677,7 @@
 #endif
 }
 
-#if !defined(__ROMCC__)
+#if !defined(__PRE_RAM__)
 static u32 get_io_addr_index(u32 nodeid, u32 linkn)
 {
 	u32 index;

Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h
===================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8_f.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/northbridge/amd/amdk8/amdk8_f.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -518,7 +518,7 @@
 	uint32_t sbbusn;
 } __attribute__((packed));
 
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 static void soft_reset(void);
 #else
 void hard_reset(void);
@@ -562,7 +562,7 @@
 	}
 
 	for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
 #else
 		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
@@ -579,7 +579,7 @@
 		}
 	}
 	if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAM__
 		print_debug("mem trained failed\r\n");
 		soft_reset();
 #else

Modified: trunk/src/northbridge/via/cn700/cn700.h
===================================================================
--- trunk/src/northbridge/via/cn700/cn700.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/northbridge/via/cn700/cn700.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
 static void cn700_noop()
 {
 }

Modified: trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
===================================================================
--- trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c	2009-11-06 17:02:51 UTC (rev 4921)
@@ -19,7 +19,7 @@
  */
 
 #define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAM__
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 

Modified: trunk/src/southbridge/amd/cs5530/cs5530.h
===================================================================
--- trunk/src/southbridge/amd/cs5530/cs5530.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/southbridge/amd/cs5530/cs5530.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -21,7 +21,7 @@
 #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
 #define SOUTHBRIDGE_AMD_CS5530_CS5530_H
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 #include "chip.h"
 void cs5530_enable(device_t dev);
 #endif

Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -21,7 +21,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 #include "chip.h"
 void i82371eb_enable(device_t dev);
 void i82371eb_hard_reset(void);

Modified: trunk/src/southbridge/intel/i82801ca/i82801ca.h
===================================================================
--- trunk/src/southbridge/intel/i82801ca/i82801ca.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/southbridge/intel/i82801ca/i82801ca.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -1,7 +1,7 @@
 #ifndef I82801CA_H
 #define I82801CA_H
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801ca_enable(device_t dev);
 #endif

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h
===================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -41,7 +41,7 @@
 /* __ROMCC__ is set by auto.c to make sure
  * none of the stage2 data structures are included.
  */
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801gx_enable(device_t dev);
 #endif

Modified: trunk/src/southbridge/intel/i82801xx/i82801xx.h
===================================================================
--- trunk/src/southbridge/intel/i82801xx/i82801xx.h	2009-11-06 15:31:49 UTC (rev 4920)
+++ trunk/src/southbridge/intel/i82801xx/i82801xx.h	2009-11-06 17:02:51 UTC (rev 4921)
@@ -21,7 +21,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
 #define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
 
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801xx_enable(device_t dev);
 #endif




From svn at coreboot.org  Fri Nov  6 18:09:12 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 17:09:12 +0000
Subject: [coreboot] [v2] r4922 - in trunk/src/drivers: . pci pci/onboard
Message-ID: <mailman.4017.1355071653.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 17:09:11 +0000 (Fri, 06 Nov 2009)
New Revision: 4922

Added:
   trunk/src/drivers/pci/
   trunk/src/drivers/pci/Makefile.inc
   trunk/src/drivers/pci/onboard/
   trunk/src/drivers/pci/onboard/Config.lb
   trunk/src/drivers/pci/onboard/Makefile.inc
   trunk/src/drivers/pci/onboard/chip.h
   trunk/src/drivers/pci/onboard/onboard.c
Log:
Revert the deletion of drivers/pci/onboard that snuck in ahead of its time. 

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Added: trunk/src/drivers/pci/Makefile.inc
===================================================================
--- trunk/src/drivers/pci/Makefile.inc	                        (rev 0)
+++ trunk/src/drivers/pci/Makefile.inc	2009-11-06 17:09:11 UTC (rev 4922)
@@ -0,0 +1 @@
+subdirs-y += onboard

Added: trunk/src/drivers/pci/onboard/Config.lb
===================================================================
--- trunk/src/drivers/pci/onboard/Config.lb	                        (rev 0)
+++ trunk/src/drivers/pci/onboard/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
@@ -0,0 +1,4 @@
+config chip.h
+
+object onboard.o
+

Added: trunk/src/drivers/pci/onboard/Makefile.inc
===================================================================
--- trunk/src/drivers/pci/onboard/Makefile.inc	                        (rev 0)
+++ trunk/src/drivers/pci/onboard/Makefile.inc	2009-11-06 17:09:11 UTC (rev 4922)
@@ -0,0 +1 @@
+obj-y += onboard.o

Added: trunk/src/drivers/pci/onboard/chip.h
===================================================================
--- trunk/src/drivers/pci/onboard/chip.h	                        (rev 0)
+++ trunk/src/drivers/pci/onboard/chip.h	2009-11-06 17:09:11 UTC (rev 4922)
@@ -0,0 +1,11 @@
+#ifndef PCI_ONBOARD_H
+#define PCI_ONBOARD_H
+
+struct drivers_pci_onboard_config 
+{
+       unsigned long rom_address;
+};
+struct chip_operations;
+extern struct chip_operations drivers_pci_onboard_ops;
+
+#endif 

Added: trunk/src/drivers/pci/onboard/onboard.c
===================================================================
--- trunk/src/drivers/pci/onboard/onboard.c	                        (rev 0)
+++ trunk/src/drivers/pci/onboard/onboard.c	2009-11-06 17:09:11 UTC (rev 4922)
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2004 Tyan Computer
+ *  by yhlu at tyan.com
+ */
+
+#include <console/console.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+/*
+ * How to use the onboard device driver for option rom execution:
+ *
+ * 1. You need to add the driver to your mainboard Config.lb:
+ *
+ *      chip drivers/pci/onboard
+ *	    device pci x.0 on end
+ *          register "rom_address" = "0xfff80000"
+ *      end
+ * 2. Reduce the size of your normal (or fallback) image, by adding the
+ *    following lines to your target Config.lb, after romimage "normal"
+ *      # 48K for SCSI FW or ATI ROM
+ *      option CONFIG_ROM_SIZE = 512*1024-48*1024
+ * 3. Create your vgabios.bin, for example using awardeco and put it in the
+ *    directory of your target Config.lb. You can also read an option rom from
+ *    a running system, but this is unreliable, as some option roms are changed
+ *    during execution:
+ *      #  dd if=/dev/mem of=atix.rom skip=1536 count=96
+ * 4. After you built coreboot.rom, attach the option rom to your coreboot
+ *    image:
+ *      # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
+ *
+ * Alternatively you can use the following script "nsxv" to build your image
+ * Usage:
+ * # ./nsxv s2850
+ *     
+ *     #!/bin/bash
+ *     MBVENDOR=tyan
+ *     MBMODEL=$1
+ *     LBROOT=/home/yhlu/xx/xx
+ *     
+ *     echo $1
+ *     date
+ *     
+ *     cd "$LBROOT/freebios2/targets"
+ *     rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
+ *     ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
+ *     cd "$MBVENDOR/$MBMODEL/$MBMODEL"
+ *     #make clean
+ *     eval make &> "$LBROOT/x_m.txt"
+ *             if [ $? -eq 0 ]; then
+ *                     echo "ok."
+ *             else
+ *                     echo "FAILED! Log excerpt:"
+ *                     tail -n 15 "$LBROOT/x_m.txt"
+ *                     exit
+ *             fi
+ *     cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
+ *     cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
+ *     
+ *     date
+ *     
+ */
+
+static void onboard_enable(device_t dev) 
+{
+	struct drivers_pci_onboard_config *conf;
+        conf = dev->chip_info;
+	dev->rom_address = conf->rom_address;
+}
+
+struct chip_operations drivers_pci_onboard_ops = {
+	CHIP_NAME("Onboard PCI")
+	.enable_dev = onboard_enable,
+};




From svn at coreboot.org  Fri Nov  6 18:11:06 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 17:11:06 +0000
Subject: [coreboot] [v2] r4923 - in trunk/src: mainboard/amd/dbm690t
	mainboard/amd/pistachio mainboard/arima/hdama
	mainboard/asi/mb_5blmp mainboard/asus/mew-vm
	mainboard/broadcom/blast mainboard/digitallogic/msm586seg
	mainboard/gigabyte/ga_2761gxdk mainboard/hp/e_vectra_p2706t
	mainboard/ibm/e326 mainboard/intel/d945gclf
	mainboard/iwill/dk8_htx mainboard/kontron/986lcd-m
	mainboard/kontron/kt690 mainboard/mitac/6513wu
	mainboard/msi/ms6178 mainboard/msi/ms9185
	mainboard/msi/ms9282 mainboard/nec/powermate2000
	mainboard/rca/rm4100 mainboard/supermicro/h8dme
	mainboard/supermicro/h8dmr mainboard/supermicro/h8dmr_fam10
	mainboard/technexion/tim5690 mainboard/technexion/tim8690
	mainboard/technologic/ts5300 mainboard/thomson/ip1000
	mainboard/tyan/s2850 mainboard/tyan/s2875
	mainboard/tyan/s2880 mainboard/tyan/s2881
	mainboard/tyan/s2882 mainboard/tyan/s2912_fam10
	mainboard/tyan/s4880 mainboard/tyan/s4882
	mainboard/via/vt8454c southbridge/amd/rs690
Message-ID: <mailman.4018.1355071653.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 17:11:05 +0000 (Fri, 06 Nov 2009)
New Revision: 4923

Modified:
   trunk/src/mainboard/amd/dbm690t/Config.lb
   trunk/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/src/mainboard/amd/pistachio/Config.lb
   trunk/src/mainboard/amd/pistachio/devicetree.cb
   trunk/src/mainboard/arima/hdama/Config.lb
   trunk/src/mainboard/arima/hdama/devicetree.cb
   trunk/src/mainboard/asi/mb_5blmp/Config.lb
   trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
   trunk/src/mainboard/asus/mew-vm/Config.lb
   trunk/src/mainboard/asus/mew-vm/devicetree.cb
   trunk/src/mainboard/broadcom/blast/Config.lb
   trunk/src/mainboard/broadcom/blast/devicetree.cb
   trunk/src/mainboard/digitallogic/msm586seg/Config.lb
   trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
   trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
   trunk/src/mainboard/ibm/e326/Config.lb
   trunk/src/mainboard/ibm/e326/devicetree.cb
   trunk/src/mainboard/intel/d945gclf/Config.lb
   trunk/src/mainboard/intel/d945gclf/devicetree.cb
   trunk/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/src/mainboard/kontron/986lcd-m/Config.lb
   trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
   trunk/src/mainboard/kontron/kt690/Config.lb
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/mitac/6513wu/Config.lb
   trunk/src/mainboard/mitac/6513wu/devicetree.cb
   trunk/src/mainboard/msi/ms6178/Config.lb
   trunk/src/mainboard/msi/ms6178/devicetree.cb
   trunk/src/mainboard/msi/ms9185/Config.lb
   trunk/src/mainboard/msi/ms9185/devicetree.cb
   trunk/src/mainboard/msi/ms9282/Config.lb
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/nec/powermate2000/Config.lb
   trunk/src/mainboard/nec/powermate2000/devicetree.cb
   trunk/src/mainboard/rca/rm4100/Config.lb
   trunk/src/mainboard/rca/rm4100/devicetree.cb
   trunk/src/mainboard/supermicro/h8dme/Config.lb
   trunk/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
   trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
   trunk/src/mainboard/technexion/tim5690/Config.lb
   trunk/src/mainboard/technexion/tim5690/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Config.lb
   trunk/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/src/mainboard/technologic/ts5300/Config.lb
   trunk/src/mainboard/technologic/ts5300/devicetree.cb
   trunk/src/mainboard/thomson/ip1000/Config.lb
   trunk/src/mainboard/thomson/ip1000/devicetree.cb
   trunk/src/mainboard/tyan/s2850/Config.lb
   trunk/src/mainboard/tyan/s2850/devicetree.cb
   trunk/src/mainboard/tyan/s2875/Config.lb
   trunk/src/mainboard/tyan/s2875/devicetree.cb
   trunk/src/mainboard/tyan/s2880/Config.lb
   trunk/src/mainboard/tyan/s2880/devicetree.cb
   trunk/src/mainboard/tyan/s2881/Config.lb
   trunk/src/mainboard/tyan/s2881/devicetree.cb
   trunk/src/mainboard/tyan/s2882/Config.lb
   trunk/src/mainboard/tyan/s2882/devicetree.cb
   trunk/src/mainboard/tyan/s2912_fam10/Config.lb
   trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/src/mainboard/tyan/s4880/Config.lb
   trunk/src/mainboard/tyan/s4880/devicetree.cb
   trunk/src/mainboard/tyan/s4882/Config.lb
   trunk/src/mainboard/tyan/s4882/devicetree.cb
   trunk/src/mainboard/via/vt8454c/Config.lb
   trunk/src/mainboard/via/vt8454c/devicetree.cb
   trunk/src/southbridge/amd/rs690/chip.h
Log:
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.

Since we have CBFS setting rom_address in board files is no longer 
necessary.

Also, drop vga_rom_address from RS690 completely, it was never used 
in the code.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -157,7 +157,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -22,7 +22,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

Modified: trunk/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -158,7 +158,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -23,7 +23,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

Modified: trunk/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -179,7 +179,6 @@
 						device pci 1.0 off end	# LAN
 						chip drivers/pci/onboard
 							device pci 6.0 on end # ATI Rage XL
-							register "rom_address" = "0xfff80000"
 						end
 						## PCI Slot 5 (correct?)
 						#chip drivers/generic/generic

Modified: trunk/src/mainboard/arima/hdama/devicetree.cb
===================================================================
--- trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -75,7 +75,6 @@
 						device pci 1.0 off end	# LAN
 						chip drivers/pci/onboard
 							device pci 6.0 on end # ATI Rage XL
-							register "rom_address" = "0xfff80000"
 						end
 						## PCI Slot 5 (correct?)
 						#chip drivers/generic/generic

Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -138,9 +138,6 @@
       # device pci 12.4 on		# VGA (onboard)
       #   chip drivers/pci/onboard
       #     device pci 12.4 on end
-      #     register "rom_address" = "0xfffc0000" # 256 KB image
-      #     # register "rom_address" = "0xfff80000" # 512 KB image
-      #     # register "rom_address" = "0xfff00000" # 1 MB image
       #   end
       # end
       device pci 13.0 on end		# USB

Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -40,9 +40,6 @@
       # device pci 12.4 on		# VGA (onboard)
       #   chip drivers/pci/onboard
       #     device pci 12.4 on end
-      #     register "rom_address" = "0xfffc0000" # 256 KB image
-      #     # register "rom_address" = "0xfff80000" # 512 KB image
-      #     # register "rom_address" = "0xfff00000" # 1 MB image
       #   end
       # end
       device pci 13.0 on end		# USB

Modified: trunk/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -99,7 +99,6 @@
 		device pci 1.0 on # Onboard Video
 			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-			#	register "rom_address" = "0xfff80000"
 		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
@@ -109,7 +108,6 @@
 			device pci 1e.0 on # PCI Bridge
 				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-				#	register "rom_address" = "0xfff80000"
 			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge

Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -4,7 +4,6 @@
 		device pci 1.0 on # Onboard Video
 			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-			#	register "rom_address" = "0xfff80000"
 		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
@@ -14,7 +13,6 @@
 			device pci 1e.0 on # PCI Bridge
 				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-				#	register "rom_address" = "0xfff80000"
 			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge

Modified: trunk/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -211,7 +211,6 @@
                                         chip drivers/pci/onboard
                                               device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
                                                                     # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                              register "rom_address" = "0xfff80000"
                                         end
                                 end
                                         #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
@@ -220,7 +219,6 @@
 #                                        end
 #                                        chip drivers/pci/onboard
 #                                              device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                              register "rom_address" = "0xfff80000"
 #                                        end
 
 

Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb
===================================================================
--- trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -109,7 +109,6 @@
                                         chip drivers/pci/onboard
                                               device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
                                                                     # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                              register "rom_address" = "0xfff80000"
                                         end
                                 end
                                         #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
@@ -118,7 +117,6 @@
 #                                        end
 #                                        chip drivers/pci/onboard
 #                                              device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                              register "rom_address" = "0xfff80000"
 #                                        end
 
 

Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -108,7 +108,6 @@
 		end
 		chip drivers/pci/onboard
 			device pci 14.0 on end # 69000
-			register "rom_address" = "0x2000000"
 		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"

Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -7,7 +7,6 @@
 		end
 		chip drivers/pci/onboard
 			device pci 14.0 on end # 69000
-			register "rom_address" = "0x2000000"
 		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -180,7 +180,6 @@
 					device pci 1.0 on		# AGP bridge
 					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
-						register "rom_address" = "0xfff80000"
 					  end
 					end
                 			device pci 2.0 on # LPC

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -13,7 +13,6 @@
 					device pci 1.0 on		# AGP bridge
 					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
-						register "rom_address" = "0xfff80000"
 					  end
 					end
                 			device pci 2.0 on # LPC

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -78,7 +78,6 @@
     device pci 0.0 on end			# Host bridge
     chip drivers/pci/onboard			# Onboard VGA
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -9,7 +9,6 @@
     device pci 0.0 on end			# Host bridge
     chip drivers/pci/onboard			# Onboard VGA
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

Modified: trunk/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -127,7 +127,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end # ATI Rage XL
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/ibm/e326/devicetree.cb
===================================================================
--- trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -23,7 +23,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end # ATI Rage XL
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/intel/d945gclf/Config.lb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -152,9 +152,6 @@
 		device pci 01.0 off end # i945 PCIe root port
 		chip drivers/pci/onboard
 			device pci 02.0 on end # vga controller
-			# register "rom_address" = "0xfffc0000"	# 256 KB image
-			# register "rom_address" = "0xfff80000"	# 512 KB image
-			# register "rom_address" = "0xfff00000" # 1 MB image
 		end
 		device pci 02.1 on end # display controller
 

Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -30,9 +30,6 @@
 		device pci 01.0 off end # i945 PCIe root port
 		chip drivers/pci/onboard
 			device pci 02.0 on end # vga controller
-			# register "rom_address" = "0xfffc0000"	# 256 KB image
-			# register "rom_address" = "0xfff80000"	# 512 KB image
-			# register "rom_address" = "0xfff00000" # 1 MB image
 		end
 		device pci 02.1 on end # display controller
 

Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -234,7 +234,6 @@
 						device pci 1.0 off end
                                                 #chip drivers/pci/onboard
                                                 #        device pci 6.0 on end
-						#	register "rom_address" = "0xfff80000"
                                                 #end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -26,7 +26,6 @@
 						device pci 1.0 off end
                                                 #chip drivers/pci/onboard
                                                 #        device pci 6.0 on end
-						#	register "rom_address" = "0xfff80000"
                                                 #end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -155,9 +155,6 @@
 		# device pci 01.0 off end # i945 PCIe root port
 		chip drivers/pci/onboard
 			device pci 02.0 on end # vga controller
-			# register "rom_address" = "0xfffc0000"	# 256 KB image
-			# register "rom_address" = "0xfff80000"	# 512 KB image
-			register "rom_address" = "0xfff00000" # 1 MB image
 		end
 		device pci 02.1 on end # display controller
 

Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -11,9 +11,6 @@
 		device pci 01.0 off end # i945 PCIe root port
 		chip drivers/pci/onboard
 			device pci 02.0 on end # vga controller
-			# register "rom_address" = "0xfffc0000"	# 256 KB image
-			# register "rom_address" = "0xfff80000"	# 512 KB image
-			register "rom_address" = "0xfff00000" # 1 MB image
 		end
 		device pci 02.1 on end # display controller
 

Modified: trunk/src/mainboard/kontron/kt690/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -134,7 +134,6 @@
 #The variables belong to mainboard are defined here.
 
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -158,7 +157,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -168,7 +166,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff00000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -1,5 +1,4 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff0000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -23,7 +22,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff00000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -33,7 +31,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff00000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/mitac/6513wu/Config.lb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -82,7 +82,6 @@
     device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
     chip drivers/pci/onboard
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000" # 512 KB image
     end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"

Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -28,7 +28,6 @@
     device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
     chip drivers/pci/onboard
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000" # 512 KB image
     end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"

Modified: trunk/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -77,7 +77,6 @@
     device pci 0.0 on end			# Host bridge
     chip drivers/pci/onboard			# Onboard VGA
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -28,7 +28,6 @@
     device pci 0.0 on end			# Host bridge
     chip drivers/pci/onboard			# Onboard VGA
       device pci 1.0 on end
-      register "rom_address" = "0xfff80000"	# 512 KB image
     end
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"

Modified: trunk/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -211,7 +211,6 @@
                                         chip drivers/pci/onboard
                                               device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
                                                                     # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                              register "rom_address" = "0xfff80000"
                                         end
                                        #bx_a013+ start
                                        #chip drivers/pci/onboard    #SATA2
@@ -229,7 +228,6 @@
 #                                        end
 #                                        chip drivers/pci/onboard
 #                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                              register "rom_address" = "0xfff80000"
 #                                        end
 
                        end #  device pci 18.0

Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -77,7 +77,6 @@
                                         chip drivers/pci/onboard
                                               device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
                                                                     # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                              register "rom_address" = "0xfff80000"
                                         end
                                        #bx_a013+ start
                                        #chip drivers/pci/onboard    #SATA2
@@ -95,7 +94,6 @@
 #                                        end
 #                                        chip drivers/pci/onboard
 #                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                              register "rom_address" = "0xfff80000"
 #                                        end
 
                        end #  device pci 18.0

Modified: trunk/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -280,7 +280,6 @@
                                        device pci 6.0 on  #P2P
                                                chip drivers/pci/onboard
                                                        device pci 4.0 on end
-                                                       register "rom_address" = "0xfff80000"
                                                end
                                        end # P2P
                                        device pci 7.0 on end # reserve

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -139,7 +139,6 @@
                                        device pci 6.0 on  #P2P
                                                chip drivers/pci/onboard
                                                        device pci 4.0 on end
-                                                       register "rom_address" = "0xfff80000"
                                                end
                                        end # P2P
                                        device pci 7.0 on end # reserve

Modified: trunk/src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -78,7 +78,6 @@
     device pci 1.0 off				# Onboard video
       # chip drivers/pci/onboard
       #   device pci 1.0 on end
-      #   register "rom_address" = "0xfff80000"
       # end
     end
     chip southbridge/intel/i82801xx		# Southbridge

Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -9,7 +9,6 @@
     device pci 1.0 off				# Onboard video
       # chip drivers/pci/onboard
       #   device pci 1.0 on end
-      #   register "rom_address" = "0xfff80000"
       # end
     end
     chip southbridge/intel/i82801xx		# Southbridge

Modified: trunk/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -77,7 +77,6 @@
     device pci 0.0 on end		# Host bridge
     chip drivers/pci/onboard		# Onboard VGA
       device pci 2.0 on end		# VGA (Intel 82830 CGC)
-      register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"

Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb
===================================================================
--- trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -3,7 +3,6 @@
     device pci 0.0 on end		# Host bridge
     chip drivers/pci/onboard		# Onboard VGA
       device pci 2.0 on end		# VGA (Intel 82830 CGC)
-      register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"

Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -256,8 +256,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -94,8 +94,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -278,8 +278,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -114,8 +114,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -282,8 +282,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -116,8 +116,6 @@
                 			device pci 6.0 on  # PCI
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff00000" #for 1M
-#                                                        register "rom_address" = "0xfff80000" #for 512K
                                                 end
 					end
         	        		device pci 6.1 on end # AZA

Modified: trunk/src/mainboard/technexion/tim5690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -134,7 +134,6 @@
 #The variables belong to mainboard are defined here.
 
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff80000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #			1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -158,10 +157,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff80000" #512KB
-							#register "rom_address" = "0xfff00000" #1024KB
-							#register "rom_address" = "0xffe00000" #2048KB
-							#register "rom_address" = "0xffc00000" #4096KB
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -171,10 +166,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff80000"
-					#register "vga_rom_address" = "0xfff00000"
-					#register "vga_rom_address" = "0xffe00000"
-					#register "vga_rom_address" = "0xffc00000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technexion/tim5690/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -1,5 +1,4 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff80000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #			1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -23,10 +22,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff80000" #512KB
-							#register "rom_address" = "0xfff00000" #1024KB
-							#register "rom_address" = "0xffe00000" #2048KB
-							#register "rom_address" = "0xffc00000" #4096KB
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -36,10 +31,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff80000"
-					#register "vga_rom_address" = "0xfff00000"
-					#register "vga_rom_address" = "0xffe00000"
-					#register "vga_rom_address" = "0xffc00000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -134,7 +134,6 @@
 #The variables belong to mainboard are defined here.
 
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff80000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -158,7 +157,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff80000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -168,7 +166,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff80000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technexion/tim8690/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -1,5 +1,4 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define vga_rom_address = 0xfff80000
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 #			1: the system allows a PCIE link to be established on Dev2 or Dev3.
@@ -23,7 +22,6 @@
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 						chip drivers/pci/onboard
 							device pci 5.0 on end	# Internal Graphics 0x791F
-							register "rom_address" = "0xfff80000"
 						end
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@@ -33,7 +31,6 @@
 					device pci 6.0 on end # PCIE P2P bridge 0x7916
 					device pci 7.0 on end # PCIE P2P bridge 0x7917
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "vga_rom_address" = "0xfff80000"
 					register "gpp_configuration" = "4"
 					register "port_enable" = "0xfc"
 					register "gfx_dev2_dev3" = "1"

Modified: trunk/src/mainboard/technologic/ts5300/Config.lb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -109,7 +109,6 @@
 #		end
 #		chip drivers/pci/onboard
 #			device pci 14.0 on end # 69000
-#			register "rom_address" = "0x2000000"
 #		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"

Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/technologic/ts5300/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -7,7 +7,6 @@
 #		end
 #		chip drivers/pci/onboard
 #			device pci 14.0 on end # 69000
-#			register "rom_address" = "0x2000000"
 #		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"

Modified: trunk/src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -77,7 +77,6 @@
     device pci 0.0 on end		# Host bridge
     chip drivers/pci/onboard		# Onboard VGA
       device pci 2.0 on end		# VGA (Intel 82830 CGC)
-      register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"

Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -3,7 +3,6 @@
     device pci 0.0 on end		# Host bridge
     chip drivers/pci/onboard		# Onboard VGA
       device pci 2.0 on end		# VGA (Intel 82830 CGC)
-      register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"

Modified: trunk/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -121,7 +121,6 @@
                                                 #chip drivers/ati/ragexl
 						chip drivers/pci/onboard
                                                         device pci b.0 on end
-							register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -19,7 +19,6 @@
                                                 #chip drivers/ati/ragexl
 						chip drivers/pci/onboard
                                                         device pci b.0 on end
-							register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -125,7 +125,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -23,7 +23,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -140,7 +140,6 @@
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end #adti
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -38,7 +38,6 @@
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end #adti
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -141,7 +141,6 @@
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -39,7 +39,6 @@
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-							register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -141,7 +141,6 @@
                                         #       chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff00000"
                                                 end
                                                 chip drivers/pci/onboard 
                                                         device pci 8.0 on end #intel 10/100

Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -39,7 +39,6 @@
                                         #       chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff00000"
                                                 end
                                                 chip drivers/pci/onboard 
                                                         device pci 8.0 on end #intel 10/100

Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -281,7 +281,6 @@
 					device pci 6.0 on
 						chip drivers/pci/onboard
 							device pci 4.0 on end
-							register "rom_address" = "0xfff00000"
 						end
 					end # PCI
 					device pci 6.1 off end # AZA

Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -114,7 +114,6 @@
 					device pci 6.0 on
 						chip drivers/pci/onboard
 							device pci 4.0 on end
-							register "rom_address" = "0xfff00000"
 						end
 					end # PCI
 					device pci 6.1 off end # AZA

Modified: trunk/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -135,7 +135,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -38,7 +38,6 @@
 						device pci 1.0 off end
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
 					end
 					device pci 1.0 on

Modified: trunk/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -134,7 +134,6 @@
                                                 #chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end #SiI

Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -37,7 +37,6 @@
                                                 #chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 6.0 on end
-                                                        register "rom_address" = "0xfff80000"
                                                 end
                                                 chip drivers/pci/onboard
                                                         device pci 5.0 on end #SiI

Modified: trunk/src/mainboard/via/vt8454c/Config.lb
===================================================================
--- trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -123,9 +123,6 @@
 		device pci 1.0 on     # PCI Bridge
 			chip drivers/pci/onboard
 				device pci 0.0 on end
-				#register "rom_address" = "0xfffc0000" #256k image
-				register "rom_address" = "0xfff80000" #512k image
-				#register "rom_address" = "0xfff00000" #1024k image
 			end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA

Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
@@ -14,9 +14,6 @@
 		device pci 1.0 on     # PCI Bridge
 			chip drivers/pci/onboard
 				device pci 0.0 on end
-				#register "rom_address" = "0xfffc0000" #256k image
-				register "rom_address" = "0xfff80000" #512k image
-				#register "rom_address" = "0xfff00000" #1024k image
 			end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA

Modified: trunk/src/southbridge/amd/rs690/chip.h
===================================================================
--- trunk/src/southbridge/amd/rs690/chip.h	2009-11-06 17:09:11 UTC (rev 4922)
+++ trunk/src/southbridge/amd/rs690/chip.h	2009-11-06 17:11:05 UTC (rev 4923)
@@ -23,7 +23,6 @@
 /* Member variables are defined in Config.lb. */
 struct southbridge_amd_rs690_config
 {
-	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
 	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
 	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
 	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */




From mylesgw at gmail.com  Fri Nov  6 18:14:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 11:14:54 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
Message-ID: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>

PCI onboard was only used for ROM images at fixed offsets in flash.  Now
that we have CBFS, there is no use for it.

Fix qemu, since it is a special case where the ROM image ends up at 0xc0000
without any help from coreboot.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Abuild tested.  Boot tested on qemu.

Thanks,
Myles
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From info at coresystems.de  Fri Nov  6 18:21:07 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 06 Nov 2009 17:21:07 +0000
Subject: [coreboot] build service results for r4921
Message-ID: <E1N6SUl-0002m8-BJ@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4921 to
the coreboot repository. This caused the following 
changes:

Change Log:
Split the two usages of __ROMCC__:
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."

There are probably some places where both are tested, but only one is needed.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Configuration of amd:dbm690t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=dbm690t&vendor=amd&num=1
Configuration of amd:pistachio has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=pistachio&vendor=amd&num=1
Configuration of arima:hdama has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=hdama&vendor=arima&num=1
Configuration of broadcom:blast has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=blast&vendor=broadcom&num=1
Configuration of digitallogic:msm586seg has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=msm586seg&vendor=digitallogic&num=1
Configuration of gigabyte:ga_2761gxdk has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ga_2761gxdk&vendor=gigabyte&num=1
Configuration of hp:e_vectra_p2706t has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=e_vectra_p2706t&vendor=hp&num=1
Configuration of ibm:e326 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=e326&vendor=ibm&num=1
Configuration of intel:d945gclf has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=d945gclf&vendor=intel&num=1
Configuration of intel:xe7501devkit has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=xe7501devkit&vendor=intel&num=1
Configuration of kontron:986lcd-m has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=986lcd-m&vendor=kontron&num=1
Configuration of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=kt690&vendor=kontron&num=1
Configuration of mitac:6513wu has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=6513wu&vendor=mitac&num=1
Configuration of msi:ms6178 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms6178&vendor=msi&num=1
Configuration of msi:ms9185 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms9185&vendor=msi&num=1
Configuration of msi:ms9282 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms9282&vendor=msi&num=1
Configuration of rca:rm4100 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=rm4100&vendor=rca&num=1
Configuration of supermicro:h8dme has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dme&vendor=supermicro&num=1
Configuration of supermicro:h8dmr has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dmr&vendor=supermicro&num=1
Configuration of supermicro:h8dmr_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dmr_fam10&vendor=supermicro&num=1
Configuration of technexion:tim5690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=tim5690&vendor=technexion&num=1
Configuration of technexion:tim8690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=tim8690&vendor=technexion&num=1
Configuration of thomson:ip1000 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ip1000&vendor=thomson&num=1
Configuration of tyan:s2735 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2735&vendor=tyan&num=1
Configuration of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2850&vendor=tyan&num=1
Configuration of tyan:s2875 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2875&vendor=tyan&num=1
Configuration of tyan:s2880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2880&vendor=tyan&num=1
Configuration of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2881&vendor=tyan&num=1
Configuration of tyan:s2882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2882&vendor=tyan&num=1
Configuration of tyan:s2885 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2885&vendor=tyan&num=1
Configuration of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2891&vendor=tyan&num=1
Configuration of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2892&vendor=tyan&num=1
Configuration of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2895&vendor=tyan&num=1
Configuration of tyan:s2912_fam10 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2912_fam10&vendor=tyan&num=1
Configuration of tyan:s4880 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s4880&vendor=tyan&num=1
Configuration of tyan:s4882 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s4882&vendor=tyan&num=1
Configuration of via:vt8454c has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=vt8454c&vendor=via&num=1


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Fri Nov  6 18:32:33 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 17:32:33 +0000
Subject: [coreboot] [v2] r4924 - in trunk/src/mainboard: amd/dbm690t
	amd/pistachio gigabyte/m57sli technexion/tim8690
Message-ID: <mailman.4019.1355071653.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 17:32:32 +0000 (Fri, 06 Nov 2009)
New Revision: 4924

Modified:
   trunk/src/mainboard/amd/dbm690t/Config.lb
   trunk/src/mainboard/amd/pistachio/Config.lb
   trunk/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/src/mainboard/gigabyte/m57sli/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Config.lb
Log:
Remove some white space and comment differences from devicetree.cb and Config.lb
files.

These boards have non-trivial differences:
gigabyte/m57sli
kontron/986lcd-m
dell/s1850
via/epia-m700

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
+++ trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
@@ -136,7 +136,7 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 #Define gfx_tmds, 0: didn't support TMDS, 1: support

Modified: trunk/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
+++ trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
@@ -136,7 +136,7 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 #Define gfx_tmds, 0: didn't support TMDS, 1: support

Modified: trunk/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
+++ trunk/src/mainboard/gigabyte/m57sli/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
@@ -1,29 +1,29 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu at amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
 default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
-arch i386 end 
+arch i386 end
 
 ##
 ## Build the objects we have code for in this directory.
@@ -36,28 +36,28 @@
 if CONFIG_GENERATE_MP_TABLE object mptable.o end
 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
 
-	if CONFIG_USE_INIT	
+	if CONFIG_USE_INIT
 		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 	else
 		makerule ./cache_as_ram_auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 	end
 
 if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-        ldscript /arch/i386/init/ldscript_apc.lb
+	makerule ./apc_auto.o
+		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
+	end
+	ldscript /arch/i386/init/ldscript_apc.lb
     end
 end
 
@@ -79,32 +79,32 @@
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
+	if CONFIG_USE_INIT
+		ldscript /cpu/x86/32bit/entry32.lds
+	end
 
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
+	if CONFIG_USE_INIT
+		ldscript /cpu/amd/car/cache_as_ram.lds
+	end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
 if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+    if CONFIG_USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
     else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
     end
 else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+    if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
     else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
     end
 end
 
@@ -118,12 +118,12 @@
 ## ROMSTRAP table for MCP55
 ##
 if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
 else
-    if CONFIG_USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
@@ -135,7 +135,7 @@
 	mainboardinit cpu/amd/car/cache_as_ram.inc
 
 ###
-### This is the early phase of coreboot startup 
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -176,209 +176,187 @@
 end
 
 ##
-## Include the secondary Configuration files 
+## Include the secondary Configuration files
 ##
 config chip.h
 
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_AM2
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/ite/it8716f
-							# Floppy and any LDN
-							device pnp 2e.0 on
-                	               			# Watchdog from CLKIN, CLKIN = 24 MHz
-                	                 			irq 0x23 = 0x11 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+			device apic 0 on end
+		end
+end
+device pci_domain 0 on
+	chip northbridge/amd/amdk8 #mc0
+		device pci 18.0 on #  devices on link 0, link 0 == LDT 0
+			chip southbridge/nvidia/mcp55
+				device pci 0.0 on end # HT
+				device pci 1.0 on # LPC
+					chip superio/ite/it8716f
+						# Floppy and any LDN
+						device pnp 2e.0 on
+							# Watchdog from CLKIN, CLKIN = 24 MHz
+							irq 0x23 = 0x11
 							# Serial Flash (SPI only)
-								#0x24 = 0x1a
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.2 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.3 on #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.4 on #  EC
-                	                 			io 0x60 = 0x290
-                	                 			io 0x62 = 0x230
-                	                			irq 0x70 = 9
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-							end
-                	        			device pnp 2e.6 on #  Mouse
-                	                			irq 0x70 = 12
-							end
-	              	        			device pnp 2e.7 on #  GPIO, SPI flash
-								# pin 84 is not GP10
-								irq 0x25 = 0x0
-				# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
-								irq 0x26 = 0x43
-								# pin 13 is GP35
-								irq 0x27 = 0x20 
-								# pin 70 is not GP46
-								#irq 0x28 = 0x0
-				# pin 6,3,128,127,126 is GP63,64,65,66,67
-								irq 0x29 = 0x81
-				# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
-								#irq 0x2c = 0x1f
-				# Simple I/O base
-								io 0x62 = 0x800
-				# Serial Flash I/O (SPI only)
-								io 0x64 = 0x820
-				# watch dog force timeout (parallel flash only)
-								#irq 0x71 = 0x1
-								# No WDT interrupt
-								irq 0x72 = 0x0 
-					# GPIO pin set 1 disable internal pullup
-								irq 0xb8 = 0x0
-					# GPIO pin set 5 enable internal pullup
-								irq 0xbc = 0x01
-					# SIO pin set 1 alternate function
-								#irq 0xc0 = 0x0
-					# SIO pin set 2 mixed function
-								irq 0xc1 = 0x43
-					# SIO pin set 3 mixed function
-								irq 0xc2 = 0x20
-					# SIO pin set 4 alternate function
-								#irq 0xc3 = 0x0
-					# SIO pin set 1 input mode
-								#irq 0xc8 = 0x0
-					# SIO pin set 2 input mode
-								irq 0xc9 = 0x0
-					# SIO pin set 4 input mode
-								#irq 0xcb = 0x0
-					# Generate SMI# on EC IRQ
-								#irq 0xf0 = 0x10
-					# SMI# level trigger
-								#irq 0xf1 = 0x40
-					# HWMON alert beep pin location
-								irq 0xf6 = 0x28
-							end
-                	        			device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 10
-							end
-                	        			device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-                	        			device pnp 2e.a off end #  CIR
+							#0x24 = 0x1a
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
 						end
+						device pnp 2e.1 on # Com1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off # Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 on #  Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp 2e.4 on #  EC
+							io 0x60 = 0x290
+							io 0x62 = 0x230
+							irq 0x70 = 9
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 on #  Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on #  GPIO, SPI flash
+						# pin 84 is not GP10
+							irq 0x25 = 0x0
+						# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+							irq 0x26 = 0x43
+						# pin 13 is GP35
+							irq 0x27 = 0x20
+						# pin 70 is not GP46
+							#irq 0x28 = 0x0
+						# pin 6,3,128,127,126 is GP63,64,65,66,67
+							irq 0x29 = 0x81
+						# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+							#irq 0x2c = 0x1f
+						# Simple I/O base
+							io 0x62 = 0x800
+						# Serial Flash I/O (SPI only)
+							io 0x64 = 0x820
+						# watch dog force timeout (parallel flash only)
+							#irq 0x71 = 0x1
+						# No WDT interrupt
+							irq 0x72 = 0x0
+						# GPIO pin set 1 disable internal pullup
+							irq 0xb8 = 0x0
+						# GPIO pin set 5 enable internal pullup
+							irq 0xbc = 0x01
+						# SIO pin set 1 alternate function
+							#irq 0xc0 = 0x0
+						# SIO pin set 2 mixed function
+							irq 0xc1 = 0x43
+						# SIO pin set 3 mixed function
+							irq 0xc2 = 0x20
+						# SIO pin set 4 alternate function
+							#irq 0xc3 = 0x0
+						# SIO pin set 1 input mode
+							#irq 0xc8 = 0x0
+						# SIO pin set 2 input mode
+							irq 0xc9 = 0x0
+						# SIO pin set 4 input mode
+							#irq 0xcb = 0x0
+						# Generate SMI# on EC IRQ
+							#irq 0xf0 = 0x10
+						# SMI# level trigger
+							#irq 0xf1 = 0x40
+						# HWMON alert beep pin location
+							irq 0xf6 = 0x28
+						end
+						device pnp 2e.8 off #  MIDI
+							io 0x60 = 0x300
+							irq 0x70 = 10
+						end
+						device pnp 2e.9 off #  GAME
+							io 0x60 = 0x220
+						end
+						device pnp 2e.a off end #  CIR
 					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
+				end
+				device pci 1.1 on # SM 0
+					chip drivers/generic/generic #dimm 0-0-0
+						device i2c 50 on end
+					end
+					chip drivers/generic/generic #dimm 0-0-1
+						device i2c 51 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-0
+						device i2c 52 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-1
+						device i2c 53 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-0
+						device i2c 54 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-1
+						device i2c 55 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-0
+						device i2c 56 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-1
+						device i2c 57 on end
+					end
+				end # SM
 #WTF?!? We already have device pci 1.1 in the section above
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on end # PCI
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 off end # NIC
-        	       			device pci a.0 on end # PCI E 5
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
+				device pci 1.1 on # SM 1
+					chip drivers/generic/generic #MAC EEPROM
+						device i2c 51 on end
+					end
+				end # SM
+				device pci 2.0 on end # USB 1.1
+				device pci 2.1 on end # USB 2
+				device pci 4.0 on end # IDE
+				device pci 5.0 on end # SATA 0
+				device pci 5.1 on end # SATA 1
+				device pci 5.2 on end # SATA 2
+				device pci 6.0 on end # PCI
+				device pci 6.1 on end # AZA
+				device pci 8.0 on end # NIC
+				device pci 9.0 off end # NIC
+				device pci a.0 on end # PCI E 5
+				device pci b.0 on end # PCI E 4
+				device pci c.0 on end # PCI E 3
+				device pci d.0 on end # PCI E 2
+				device pci e.0 on end # PCI E 1
+				device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #device pci 18.0
 			device pci 18.0 on end # Link 1
 			device pci 18.0 on end
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
-#       end  
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	end
 end #root_complex

Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb
===================================================================
--- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb	2009-11-06 17:11:05 UTC (rev 4923)
+++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
@@ -5,11 +5,11 @@
 		end
 end
 device pci_domain 0 on
-	chip northbridge/amd/amdk8
-		device pci 18.0 on 
-			chip southbridge/nvidia/mcp55 
-				device pci 0.0 on end
-				device pci 1.0 on
+	chip northbridge/amd/amdk8 #mc0
+		device pci 18.0 on #  devices on link 0, link 0 == LDT 0
+			chip southbridge/nvidia/mcp55
+				device pci 0.0 on end # HT
+				device pci 1.0 on # LPC
 					chip superio/ite/it8716f
 						# Floppy and any LDN
 						device pnp 2e.0 on
@@ -52,7 +52,7 @@
 						# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
 							irq 0x26 = 0x43
 						# pin 13 is GP35
-							irq 0x27 = 0x20 
+							irq 0x27 = 0x20
 						# pin 70 is not GP46
 							#irq 0x28 = 0x0
 						# pin 6,3,128,127,126 is GP63,64,65,66,67
@@ -66,7 +66,7 @@
 						# watch dog force timeout (parallel flash only)
 							#irq 0x71 = 0x1
 						# No WDT interrupt
-							irq 0x72 = 0x0 
+							irq 0x72 = 0x0
 						# GPIO pin set 1 disable internal pullup
 							irq 0xb8 = 0x0
 						# GPIO pin set 5 enable internal pullup
@@ -99,11 +99,10 @@
 						device pnp 2e.9 off #  GAME
 							io 0x60 = 0x220
 						end
-						device pnp 2e.a off #  CIR
-						end
+						device pnp 2e.a off end #  CIR
 					end
 				end
-				device pci 1.1 on
+				device pci 1.1 on # SM 0
 					chip drivers/generic/generic #dimm 0-0-0
 						device i2c 50 on end
 					end
@@ -129,22 +128,22 @@
 						device i2c 57 on end
 					end
 				end # SM
-	                	device pci 2.0 on end # USB 1.1
-        	        	device pci 2.1 on end # USB 2
-                		device pci 4.0 on end # IDE
-	                	device pci 5.0 on end # SATA 0
-	                	device pci 5.1 on end # SATA 1
-	                	device pci 5.2 on end # SATA 2
-                		device pci 6.0 on end # PCI
-        	        	device pci 6.1 on end # AUDIO
-	                	device pci 8.0 on end # NIC
-	                	device pci 9.0 off end # N/A
-        	       		device pci a.0 on end # PCI E 5
-        	       		device pci b.0 on end # PCI E 4
-                		device pci c.0 on end # PCI E 3
-                		device pci d.0 on end # PCI E 2
-                		device pci e.0 on end # PCI E 1
-        	       		device pci f.0 on end # PCI E 0
+				device pci 2.0 on end # USB 1.1
+				device pci 2.1 on end # USB 2
+				device pci 4.0 on end # IDE
+				device pci 5.0 on end # SATA 0
+				device pci 5.1 on end # SATA 1
+				device pci 5.2 on end # SATA 2
+				device pci 6.0 on end # PCI
+				device pci 6.1 on end # AUDIO
+				device pci 8.0 on end # NIC
+				device pci 9.0 off end # N/A
+				device pci a.0 on end # PCI E 5
+				device pci b.0 on end # PCI E 4
+				device pci c.0 on end # PCI E 3
+				device pci d.0 on end # PCI E 2
+				device pci e.0 on end # PCI E 1
+				device pci f.0 on end # PCI E 0
 					register "ide0_enable" = "1"
 					register "sata0_enable" = "1"
 					register "sata1_enable" = "1"
@@ -153,13 +152,14 @@
 				end
 			end #device pci 18.0
 			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
 	end # PCI domain
 
-#	 chip drivers/generic/debug 
+#	chip drivers/generic/debug
 #		device pnp 0.0 off end # chip name
 #		device pnp 0.1 on end # pci_regs_all
 #		device pnp 0.2 on end # mem
@@ -170,6 +170,5 @@
 #		device pnp 0.7 off end # tsc
 #		device pnp 0.8 off  end # io
 #		device pnp 0.9 off end # io
-#	 end  
-
+#	end
 end #root_complex

Modified: trunk/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 17:11:05 UTC (rev 4923)
+++ trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
@@ -136,7 +136,7 @@
 #Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 #Define gfx_tmds, 0: didn't support TMDS, 1: support




From c-d.hailfinger.devel.2006 at gmx.net  Fri Nov  6 18:41:18 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 06 Nov 2009 18:41:18 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
Message-ID: <4AF45FBE.9050708@gmx.net>

On 06.11.2009 18:14, Myles Watson wrote:
> PCI onboard was only used for ROM images at fixed offsets in flash.  Now
> that we have CBFS, there is no use for it.
>
> Fix qemu, since it is a special case where the ROM image ends up at 0xc0000
> without any help from coreboot.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>   

The patch is missing.

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."




From mylesgw at gmail.com  Fri Nov  6 18:46:35 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 11:46:35 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <4AF45FBE.9050708@gmx.net>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
Message-ID: <2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>

On Fri, Nov 6, 2009 at 11:41 AM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 06.11.2009 18:14, Myles Watson wrote:
> > PCI onboard was only used for ROM images at fixed offsets in flash.  Now
> > that we have CBFS, there is no use for it.
> >
> > Fix qemu, since it is a special case where the ROM image ends up at
> 0xc0000
> > without any help from coreboot.
> >
> > Signed-off-by: Myles Watson <mylesgw at gmail.com>
> >
>
> The patch is missing.
>
Thanks.

Myles
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From info at coresystems.de  Fri Nov  6 18:52:53 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 06 Nov 2009 17:52:53 +0000
Subject: [coreboot] build service results for r4922
Message-ID: <E1N6SzV-0006bc-2K@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4922 to
the coreboot repository. This caused the following 
changes:

Change Log:
Revert the deletion of drivers/pci/onboard that snuck in ahead of its time.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Configuration of amd:dbm690t has been fixed
Configuration of amd:pistachio has been fixed
Configuration of arima:hdama has been fixed
Configuration of broadcom:blast has been fixed
Configuration of digitallogic:msm586seg has been fixed
Configuration of gigabyte:ga_2761gxdk has been fixed
Configuration of hp:e_vectra_p2706t has been fixed
Configuration of ibm:e326 has been fixed
Configuration of intel:d945gclf has been fixed
Configuration of intel:xe7501devkit has been fixed
Configuration of kontron:986lcd-m has been fixed
Configuration of kontron:kt690 has been fixed
Configuration of mitac:6513wu has been fixed
Configuration of msi:ms6178 has been fixed
Configuration of msi:ms9185 has been fixed
Configuration of msi:ms9282 has been fixed
Configuration of rca:rm4100 has been fixed
Configuration of supermicro:h8dme has been fixed
Configuration of supermicro:h8dmr has been fixed
Configuration of supermicro:h8dmr_fam10 has been fixed
Configuration of technexion:tim5690 has been fixed
Configuration of technexion:tim8690 has been fixed
Configuration of thomson:ip1000 has been fixed
Configuration of tyan:s2735 has been fixed
Configuration of tyan:s2850 has been fixed
Configuration of tyan:s2875 has been fixed
Configuration of tyan:s2880 has been fixed
Configuration of tyan:s2881 has been fixed
Configuration of tyan:s2882 has been fixed
Configuration of tyan:s2885 has been fixed
Configuration of tyan:s2891 has been fixed
Configuration of tyan:s2892 has been fixed
Configuration of tyan:s2895 has been fixed
Configuration of tyan:s2912_fam10 has been fixed
Configuration of tyan:s4880 has been fixed
Configuration of tyan:s4882 has been fixed
Configuration of via:vt8454c has been fixed


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Fri Nov  6 18:54:40 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 11:54:40 -0600
Subject: [coreboot] Defined but not used warnings
Message-ID: <2831fecf0911060954j1e724ff3k92b004910085f078@mail.gmail.com>

There are a lot of "defined but not used" warnings.  I'd like to build
without them, but I can't figure out the correct switch without disabling
other warnings that I want.  Does anyone know which flag to use?

Thanks,
Myles
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From mark.marshall at csr.com  Fri Nov  6 19:04:44 2009
From: mark.marshall at csr.com (Mark Marshall)
Date: Fri, 06 Nov 2009 18:04:44 +0000
Subject: [coreboot] [PATCH] Various x86emu fixes
In-Reply-To: <2831fecf0911060831i3d37a604o25338e62ab9d33f4@mail.gmail.com>
References: <hc6lsa$hqg$1@ger.gmane.org>
	<4AF1C281.3030502@csr.com>	<4AF29851.9000902@coresystems.de>	<808D748A06A04C8DA0CC4E66ED079386@chimp>	<20091106161857.3916.qmail@stuge.se>
	<2831fecf0911060831i3d37a604o25338e62ab9d33f4@mail.gmail.com>
Message-ID: <4AF4653C.5060608@csr.com>

Myles Watson wrote:
> 
> 
> On Fri, Nov 6, 2009 at 10:18 AM, Peter Stuge <peter at stuge.se 
> <mailto:peter at stuge.se>> wrote:
> 
>     Myles Watson wrote:
>      > I don't think we should depend on the value from the card.  The
>      > point of that check is to make sure we don't run the wrong types of
>      > ROMs. One way to work around it would be to correct the VGA BIOS
>      > from your card and put it into CBFS.
> 
>     Stefan, what about Myles' comment above? I think it's a good point.
> 
> 
> We started discussing it off list.  This should catch the list up:
> 
> On Thu, Nov 5, 2009 at 11:03 AM, Stefan Reinauer <stepan at coresystems.de 
> <mailto:stepan at coresystems.de>> wrote:
> 
>     Myles Watson wrote:
>      > Did you see my concern with checking the device instead of the ROM?
>      >
>      > Thanks,
>      > Myles
>     oops sorry.. I missed that one..
> 
> No problem.
>  
> 
>     Hm.. not sure.. that particular check does not seem to be a consistency
>     check but rather a check to determine from which location to run the VGA
>     OPROM from... Generally, VGA oproms should run from 0xc0000.
> 
> Yes.  His card is broken.  I just wanted to make sure the change doesn't 
> break other things to enable his 10-year-old card.
>  
> 
>     Maybe we should add another check whether class of the card and class of
>     the device are the same?
> 
> If we did, that would break his card again.
> 
> I guess someone will complain if/when it matters.  I'm not sure what the 
> "right" thing to do is.

I did think about this before I submitted my original patch, but didn't 
write my thoughts down anywhere, so here goes:

In pci_rom.c::pci_rom_brobe there is a check to see if the VID/PID of 
the device, as read from the PCI config space, matches the ROM image. 
This check was in the original code, and should be there.  I like it - 
it protects against user error.

There is also a check to see if the "class of device" as read from the 
PCI config space matches that contained in the ROM image.  This seems 
like a reasonable check to make, and to print a message if it fails, but 
I think the code should push on, even if this fails.

The change I made was a little later on, once we have decided to load 
the ROM image.  We have to do something different if the device we are 
loading the ROM for is a VGA (it has to be at 0xC000, and should be done 
early).  My change was to make this check based on the PCI config space 
- not the ROM image.  My thinking was along the lines that if someone 
made a PCI card that didn't declare itself to be a VGA in the PCI config 
space then most software wouldn't treat it as a VGA device.  (in other 
words the PCI config space is more likely to be correct than the ROM).

This also more closely matches my understanding of how this code might 
be called.  There would be one call early on where the first VGA device 
has it's ROM loaded, and then there would be a second pass where the non 
VGA devices have there ROMs loaded.

The final argument for having the code like I had it was that my PCI VGA 
card was quite popular, back in the day[*], and I assume that it must 
have worked with almost every motherboard out there, so legacy BIOSs 
must have been equally lax.

MM





From mylesgw at gmail.com  Fri Nov  6 19:08:39 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 12:08:39 -0600
Subject: [coreboot] [PATCH] __ROMCC__ ifdefs
In-Reply-To: <20091106164444.8722.qmail@stuge.se>
References: <2831fecf0910300624r4a23f007p69347683e0070a96@mail.gmail.com>
	<2831fecf0911060837gb115f83i44f4460e7ae0fdf1@mail.gmail.com>
	<20091106164444.8722.qmail@stuge.se>
Message-ID: <2831fecf0911061008s43ab0ea0w171ff2dfd1c41da2@mail.gmail.com>

> Acked-by: Peter Stuge <peter at stuge.se>
>
Rev 4921.

Thanks,
Myles
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From mylesgw at gmail.com  Fri Nov  6 19:10:18 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 12:10:18 -0600
Subject: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in
	Config.lb/devicetree.cb
In-Reply-To: <2831fecf0911051051o5b6632f4rd58e09619f266d69@mail.gmail.com>
References: <20091028195821.GC22827@greenwood>
	<2831fecf0910281318s70c5164g28040b41388b1046@mail.gmail.com>
	<2831fecf0911050942m4d23e76bka929a08c529a5e2c@mail.gmail.com>
	<4AF315A6.10605@coresystems.de>
	<2831fecf0911051022p5e6a4b57na8856c3cec88cee9@mail.gmail.com>
	<13426df10911051025t6fc3dbc3yb832605a1f741219@mail.gmail.com>
	<2831fecf0911051051o5b6632f4rd58e09619f266d69@mail.gmail.com>
Message-ID: <2831fecf0911061010y2c427cddm5f9036eb0da7bfd0@mail.gmail.com>

> Acked-by: Myles Watson <mylesgw at gmail.com>
>
Rev 4923.

Thanks,
Myles
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From peter at stuge.se  Fri Nov  6 19:41:35 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Nov 2009 19:41:35 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
Message-ID: <20091106184135.28623.qmail@stuge.se>

Myles Watson wrote:
> > > PCI onboard was only used for ROM images at fixed offsets in
> > > flash.  Now that we have CBFS, there is no use for it.
> > >
> > > Fix qemu, since it is a special case where the ROM image ends up
> > > at 0xc0000 without any help from coreboot.
> > >
> > > Signed-off-by: Myles Watson <mylesgw at gmail.com>

I am inclined to say:

Acked-by: Peter Stuge <peter at stuge.se>


But what about the PCI device ids which are being taken out of the
device tree? Are they guaranteed to be discovered through automatic
scanning?


//Peter



From rminnich at gmail.com  Fri Nov  6 19:44:04 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 6 Nov 2009 10:44:04 -0800
Subject: [coreboot] rev 5000 is coming!
Message-ID: <13426df10911061044r2a83ddc9v715e3df9a719f40d@mail.gmail.com>

Wow! what special event should be there for rev 5000?

ron



From mylesgw at gmail.com  Fri Nov  6 19:56:19 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 12:56:19 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <20091106184135.28623.qmail@stuge.se>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
Message-ID: <2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>

On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se> wrote:

> Myles Watson wrote:
> > > > PCI onboard was only used for ROM images at fixed offsets in
> > > > flash.  Now that we have CBFS, there is no use for it.
>
>  But what about the PCI device ids which are being taken out of the
> device tree? Are they guaranteed to be discovered through automatic
> scanning?
>
Yes.  If the couldn't be probed, they would have been disabled even though
they were found in the tree.

I wonder a little about the on_mainboard flag.  It's possible that some of
these devices would have had that flag set if they didn't need to have a
ROM.  I don't know of a good way to automatically figure out which devices
that would apply to.

Thanks,
Myles
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Nov  6 19:56:29 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 06 Nov 2009 19:56:29 +0100
Subject: [coreboot] rev 5000 is coming!
In-Reply-To: <13426df10911061044r2a83ddc9v715e3df9a719f40d@mail.gmail.com>
References: <13426df10911061044r2a83ddc9v715e3df9a719f40d@mail.gmail.com>
Message-ID: <4AF4715D.3090103@gmx.net>

On 06.11.2009 19:44, ron minnich wrote:
> Wow! what special event should be there for rev 5000?
>   

I have a few suggestions, not all of them should be taken seriously ;-)
- Rename coreboot to IncredibleInstantFirmware.
- Have a ready-made splashtop-like image for download.
- A ROM-o-matic clone which offers builing images from tested components.
- Paaaaaarty!
- Reorganize the source tree yet again.
- Add a "Donate" button to coreboot.org.
- Sell T-Shirts with coreboot logo (I have two, if you want pics).
- Offer prebuilt UEFI as payload.

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."




From mylesgw at gmail.com  Fri Nov  6 20:14:59 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 13:14:59 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
Message-ID: <2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>

On Fri, Nov 6, 2009 at 12:56 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se> wrote:
>
>> Myles Watson wrote:
>> > > > PCI onboard was only used for ROM images at fixed offsets in
>> > > > flash.  Now that we have CBFS, there is no use for it.
>>
>>  But what about the PCI device ids which are being taken out of the
>> device tree? Are they guaranteed to be discovered through automatic
>> scanning?
>>
> Yes.  If the couldn't be probed, they would have been disabled even though
> they were found in the tree.
>
> I wonder a little about the on_mainboard flag.  It's possible that some of
> these devices would have had that flag set if they didn't need to have a
> ROM.  I don't know of a good way to automatically figure out which devices
> that would apply to.
>
The rest of the story :)

The on_mainboard flag gets used to set subsystem IDs and
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST

Thanks,
Myles
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From mylesgw at gmail.com  Fri Nov  6 22:02:06 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 15:02:06 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
Message-ID: <2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>

On Fri, Nov 6, 2009 at 1:14 PM, Myles Watson <mylesgw at gmail.com> wrote:

>
>
> On Fri, Nov 6, 2009 at 12:56 PM, Myles Watson <mylesgw at gmail.com> wrote:
>
>>
>>
>> On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se> wrote:
>>
>>>  Myles Watson wrote:
>>> > > > PCI onboard was only used for ROM images at fixed offsets in
>>> > > > flash.  Now that we have CBFS, there is no use for it.
>>>
>>>  But what about the PCI device ids which are being taken out of the
>>> device tree? Are they guaranteed to be discovered through automatic
>>> scanning?
>>>
>> Yes.  If the couldn't be probed, they would have been disabled even though
>> they were found in the tree.
>>
>> I wonder a little about the on_mainboard flag.  It's possible that some of
>> these devices would have had that flag set if they didn't need to have a
>> ROM.  I don't know of a good way to automatically figure out which devices
>> that would apply to.
>>
> The rest of the story :)
>
> The on_mainboard flag gets used to set subsystem IDs and
> CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
>
I put all the devices back in the tree.  So they show up in static.c like
they should, they just don't have the onboard driver any more.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From teddks at gmail.com  Fri Nov  6 21:55:37 2009
From: teddks at gmail.com (Ted Smith)
Date: Fri, 06 Nov 2009 15:55:37 -0500
Subject: [coreboot] rev 5000 is coming!
In-Reply-To: <4AF4715D.3090103@gmx.net>
References: <13426df10911061044r2a83ddc9v715e3df9a719f40d@mail.gmail.com>
	<4AF4715D.3090103@gmx.net>
Message-ID: <1257540937.6923.3.camel@stormbringer>

On Fri, 2009-11-06 at 19:56 +0100, Carl-Daniel Hailfinger wrote:
> - Sell T-Shirts with coreboot logo (I have two, if you want pics).

I am a mundane luser who lurks this list admiring how well coreboot devs
get shit done, and would definitely buy one (or more!) of these. +1.
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Nov  6 22:34:32 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 06 Nov 2009 22:34:32 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>	<4AF45FBE.9050708@gmx.net>	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>	<20091106184135.28623.qmail@stuge.se>	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
Message-ID: <4AF49668.2000904@gmx.net>

On 06.11.2009 22:02, Myles Watson wrote:
> On Fri, Nov 6, 2009 at 1:14 PM, Myles Watson <mylesgw at gmail.com> wrote:
>
>   
>> On Fri, Nov 6, 2009 at 12:56 PM, Myles Watson <mylesgw at gmail.com> wrote:
>>
>>     
>>> On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se> wrote:
>>>
>>>       
>>>>  Myles Watson wrote:
>>>>         
>>>>>>> PCI onboard was only used for ROM images at fixed offsets in
>>>>>>> flash.  Now that we have CBFS, there is no use for it.
>>>>>>>               
>>>>  But what about the PCI device ids which are being taken out of the
>>>> device tree? Are they guaranteed to be discovered through automatic
>>>> scanning?
>>>>
>>>>         
>>> Yes.  If the couldn't be probed, they would have been disabled even though
>>> they were found in the tree.
>>>
>>> I wonder a little about the on_mainboard flag.  It's possible that some of
>>> these devices would have had that flag set if they didn't need to have a
>>> ROM.  I don't know of a good way to automatically figure out which devices
>>> that would apply to.
>>>
>>>       
>> The rest of the story :)
>>
>> The on_mainboard flag gets used to set subsystem IDs and
>> CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
>>
>>     
> I put all the devices back in the tree.  So they show up in static.c like
> they should, they just don't have the onboard driver any more.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>   

I really like this patch, and the effort you put into removing commented
out variants as well. A few minor cosmetic points, but other than that it is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
My comments are not strong requirements for a commit, I just would like
to know if some of this stuff was intentional.


> Index: svn/src/mainboard/asus/mew-vm/Config.lb
> ===================================================================
> --- svn.orig/src/mainboard/asus/mew-vm/Config.lb
> +++ svn/src/mainboard/asus/mew-vm/Config.lb
> @@ -97,18 +97,14 @@ chip northbridge/intel/i82810
>  	device pci_domain 0 on 
>  		device pci 0.0 on end # Host bridge
>  		device pci 1.0 on # Onboard Video
> -			#chip drivers/pci/onboard
>  			#	device pci 1.0 on end
>   

A device which hangs off itself? Kill?

> -		        #end
>  		end
>  		chip southbridge/intel/i82801xx # Southbridge
>        			register "ide0_enable" = "1"
>        			register "ide1_enable" = "1"
>  
>  			device pci 1e.0 on # PCI Bridge
> -				#chip drivers/pci/onboard
>  				#	device pci 1.0 on end
>   

Hm. Kill the above line? Could be a botched cut-n-paste.

> -			        #end
>  			end
>  			device pci 1f.0 on  # ISA/LPC? Bridge
>  				chip superio/smsc/lpc47b272
> Index: svn/src/mainboard/asus/mew-vm/devicetree.cb
> ===================================================================
> --- svn.orig/src/mainboard/asus/mew-vm/devicetree.cb
> +++ svn/src/mainboard/asus/mew-vm/devicetree.cb
> @@ -2,18 +2,14 @@ chip northbridge/intel/i82810
>  	device pci_domain 0 on 
>  		device pci 0.0 on end # Host bridge
>  		device pci 1.0 on # Onboard Video
> -			#chip drivers/pci/onboard
>  			#	device pci 1.0 on end
>   

See above.

> -		        #end
>  		end
>  		chip southbridge/intel/i82801xx # Southbridge
>        			register "ide0_enable" = "1"
>        			register "ide1_enable" = "1"
>  
>  			device pci 1e.0 on # PCI Bridge
> -				#chip drivers/pci/onboard
>  				#	device pci 1.0 on end
>   

Dito.

> -			        #end
>  			end
>  			device pci 1f.0 on  # ISA/LPC? Bridge
>  				chip superio/smsc/lpc47b272
> Index: svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> ===================================================================
> --- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> +++ svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> @@ -178,9 +178,7 @@ chip northbridge/amd/amdk8/root_complex
>  			        chip southbridge/sis/sis966
>  					device pci 0.0 on end   # Northbridge
>  					device pci 1.0 on		# AGP bridge
> -					  chip drivers/pci/onboard	# Integrated VGA
>  						device pci 0.0 on end
>   

This looks fishy, but then again, I never understood the v2 device tree
syntax completely.

> -					  end
>  					end
>                  			device pci 2.0 on # LPC
>  						chip superio/ite/it8716f
>   

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."




From mylesgw at gmail.com  Fri Nov  6 22:47:12 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 15:47:12 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <4AF49668.2000904@gmx.net>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
	<4AF49668.2000904@gmx.net>
Message-ID: <2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>

On Fri, Nov 6, 2009 at 3:34 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 06.11.2009 22:02, Myles Watson wrote:
> > On Fri, Nov 6, 2009 at 1:14 PM, Myles Watson <mylesgw at gmail.com> wrote:
> >
> >
> >> On Fri, Nov 6, 2009 at 12:56 PM, Myles Watson <mylesgw at gmail.com>
> wrote:
> >>
> >>
> >>> On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se> wrote:
> >>>
> >>>
> >>>>  Myles Watson wrote:
> >>>>
> >>>>>>> PCI onboard was only used for ROM images at fixed offsets in
> >>>>>>> flash.  Now that we have CBFS, there is no use for it.
> >>>>>>>
> >>>>  But what about the PCI device ids which are being taken out of the
> >>>> device tree? Are they guaranteed to be discovered through automatic
> >>>> scanning?
> >>>>
> >>>>
> >>> Yes.  If the couldn't be probed, they would have been disabled even
> though
> >>> they were found in the tree.
> >>>
> >>> I wonder a little about the on_mainboard flag.  It's possible that some
> of
> >>> these devices would have had that flag set if they didn't need to have
> a
> >>> ROM.  I don't know of a good way to automatically figure out which
> devices
> >>> that would apply to.
> >>>
> >>>
> >> The rest of the story :)
> >>
> >> The on_mainboard flag gets used to set subsystem IDs and
> >> CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
> >>
> >>
> > I put all the devices back in the tree.  So they show up in static.c like
> > they should, they just don't have the onboard driver any more.
> >
> > Signed-off-by: Myles Watson <mylesgw at gmail.com>
> >
>
> I really like this patch, and the effort you put into removing commented
> out variants as well. A few minor cosmetic points, but other than that it
> is
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
Thanks.


> > Index: svn/src/mainboard/asus/mew-vm/Config.lb
> > ===================================================================
> > --- svn.orig/src/mainboard/asus/mew-vm/Config.lb
> > +++ svn/src/mainboard/asus/mew-vm/Config.lb
> > @@ -97,18 +97,14 @@ chip northbridge/intel/i82810
> >       device pci_domain 0 on
> >               device pci 0.0 on end # Host bridge
> >               device pci 1.0 on # Onboard Video
> > -                     #chip drivers/pci/onboard
> >                       #       device pci 1.0 on end
> >
>
> A device which hangs off itself?

I couldn't tell.  The PCI devfn (1.0) doesn't help because a child device
will be on a different bus, so it's allowed to have the same devfn as its
parent.  That's why I left it.


>
> >                       device pci 1e.0 on # PCI Bridge
> > -                             #chip drivers/pci/onboard
> >                               #       device pci 1.0 on end
> >
>
> Hm. Kill the above line? Could be a botched cut-n-paste.
>
Could be.  Again, I couldn't tell.  Anyone with the board would know the
first time they booted, so it could be removed.  I was trying to be
minimally invasive.


>
> > Index: svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> > ===================================================================
> > --- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> > +++ svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> > @@ -178,9 +178,7 @@ chip northbridge/amd/amdk8/root_complex
> >                               chip southbridge/sis/sis966
> >                                       device pci 0.0 on end   #
> Northbridge
> >                                       device pci 1.0 on               #
> AGP bridge
> > -                                       chip drivers/pci/onboard      #
> Integrated VGA
> >                                               device pci 0.0 on end
> >
>
> This looks fishy, but then again, I never understood the v2 device tree
> syntax completely.
>
I'm not sure what looks fishy here.  This is the way I understand it:
1. Devices between the 'on' and 'end' tokens are children (or children of
children) of the device.
2. The 'chip' token assigns the driver for devices inside it.

So in this case, device 1.0 has an AGP bus with 0.0 hanging off of it.

Thanks,
Myles
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From c-d.hailfinger.devel.2006 at gmx.net  Fri Nov  6 23:31:06 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 06 Nov 2009 23:31:06 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>	
	<4AF45FBE.9050708@gmx.net>	
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>	
	<20091106184135.28623.qmail@stuge.se>	
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>	
	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>	
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>	
	<4AF49668.2000904@gmx.net>
	<2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
Message-ID: <4AF4A3AA.6010600@gmx.net>

On 06.11.2009 22:47, Myles Watson wrote:
> On Fri, Nov 6, 2009 at 3:34 PM, Carl-Daniel Hailfinger 
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>
>   
>> A device which hangs off itself?
>>     
>
> I couldn't tell.  The PCI devfn (1.0) doesn't help because a child device
> will be on a different bus, so it's allowed to have the same devfn as its
> parent.  That's why I left it.
>   

Ah.


>> Hm. Kill the above line? Could be a botched cut-n-paste.
>>     
> Could be.  Again, I couldn't tell.  Anyone with the board would know the
> first time they booted, so it could be removed.  I was trying to be
> minimally invasive.
>   

Right. Good goal.


> I'm not sure what looks fishy here.  This is the way I understand it:
> 1. Devices between the 'on' and 'end' tokens are children (or children of
> children) of the device.
> 2. The 'chip' token assigns the driver for devices inside it.
>
> So in this case, device 1.0 has an AGP bus with 0.0 hanging off of it.
>   

Thanks for the explanation.
Go ahead!

Regards,
Carl-Daniel

-- 
Developer quote of the week: 
"We are juggling too many chainsaws and flaming arrows and tigers."




From stepan at coresystems.de  Sat Nov  7 00:06:14 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 07 Nov 2009 00:06:14 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>	<4AF45FBE.9050708@gmx.net>	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>	<20091106184135.28623.qmail@stuge.se>	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
Message-ID: <4AF4ABE6.6030704@coresystems.de>

Myles Watson wrote:
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com <mailto:mylesgw at gmail.com>>

Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From stepan at coresystems.de  Sat Nov  7 00:19:43 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 07 Nov 2009 00:19:43 +0100
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>	<4AF45FBE.9050708@gmx.net>	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>	<20091106184135.28623.qmail@stuge.se>	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>	<4AF49668.2000904@gmx.net>
	<2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
Message-ID: <4AF4AF0F.2000107@coresystems.de>

Myles Watson wrote:
>
>
> On Fri, Nov 6, 2009 at 3:34 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net
> <mailto:c-d.hailfinger.devel.2006 at gmx.net>> wrote:
>
>     On 06.11.2009 22:02, Myles Watson wrote:
>     > On Fri, Nov 6, 2009 at 1:14 PM, Myles Watson <mylesgw at gmail.com
>     <mailto:mylesgw at gmail.com>> wrote:
>     >
>     >
>     >> On Fri, Nov 6, 2009 at 12:56 PM, Myles Watson
>     <mylesgw at gmail.com <mailto:mylesgw at gmail.com>> wrote:
>     >>
>     >>
>     >>> On Fri, Nov 6, 2009 at 12:41 PM, Peter Stuge <peter at stuge.se
>     <mailto:peter at stuge.se>> wrote:
>     >>>
>     >>>
>     >>>>  Myles Watson wrote:
>     >>>>
>     >>>>>>> PCI onboard was only used for ROM images at fixed offsets in
>     >>>>>>> flash.  Now that we have CBFS, there is no use for it.
>     >>>>>>>
>     >>>>  But what about the PCI device ids which are being taken out
>     of the
>     >>>> device tree? Are they guaranteed to be discovered through
>     automatic
>     >>>> scanning?
>     >>>>
>     >>>>
>     >>> Yes.  If the couldn't be probed, they would have been disabled
>     even though
>     >>> they were found in the tree.
>     >>>
>     >>> I wonder a little about the on_mainboard flag.  It's possible
>     that some of
>     >>> these devices would have had that flag set if they didn't need
>     to have a
>     >>> ROM.  I don't know of a good way to automatically figure out
>     which devices
>     >>> that would apply to.
>     >>>
>     >>>
>     >> The rest of the story :)
>     >>
>     >> The on_mainboard flag gets used to set subsystem IDs and
>     >> CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
>     >>
>     >>
>     > I put all the devices back in the tree.  So they show up in
>     static.c like
>     > they should, they just don't have the onboard driver any more.
>     >
>     > Signed-off-by: Myles Watson <mylesgw at gmail.com
>     <mailto:mylesgw at gmail.com>>
>     >
>
>     I really like this patch, and the effort you put into removing
>     commented
>     out variants as well. A few minor cosmetic points, but other than
>     that it is
>     Acked-by: Carl-Daniel Hailfinger
>     <c-d.hailfinger.devel.2006 at gmx.net
>     <mailto:c-d.hailfinger.devel.2006 at gmx.net>>
>
> Thanks.
>  
>
>     > Index: svn/src/mainboard/asus/mew-vm/Config.lb
>     > ===================================================================
>     > --- svn.orig/src/mainboard/asus/mew-vm/Config.lb
>     > +++ svn/src/mainboard/asus/mew-vm/Config.lb
>     > @@ -97,18 +97,14 @@ chip northbridge/intel/i82810
>     >       device pci_domain 0 on
>     >               device pci 0.0 on end # Host bridge
>     >               device pci 1.0 on # Onboard Video
>     > -                     #chip drivers/pci/onboard
>     >                       #       device pci 1.0 on end
>     >
>
>     A device which hangs off itself?
>
> I couldn't tell.  The PCI devfn (1.0) doesn't help because a child
> device will be on a different bus, so it's allowed to have the same
> devfn as its parent.  That's why I left it.
I was about to write the same comment as Carl-Daniel. But, on the i945
0:1.0 is a bridge of which the (on i945 external PCIe) graphics hangs off.
So, the second 1.0 is indeed most likely supposed to be a device hanging
off a bridge at 0:1.0.


>  
>
>
>     >                       device pci 1e.0 on # PCI Bridge
>     > -                             #chip drivers/pci/onboard
>     >                               #       device pci 1.0 on end
>     >
>
>     Hm. Kill the above line? Could be a botched cut-n-paste.
>
> Could be.  Again, I couldn't tell.  Anyone with the board would know
> the first time they booted, so it could be removed.  I was trying to
> be minimally invasive.
Good.


>
>     > Index: svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
>     > ===================================================================
>     > --- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
>     > +++ svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
>     > @@ -178,9 +178,7 @@ chip northbridge/amd/amdk8/root_complex
>     >                               chip southbridge/sis/sis966
>     >                                       device pci 0.0 on end   #
>     Northbridge
>     >                                       device pci 1.0 on        
>           # AGP bridge
>     > -                                       chip drivers/pci/onboard
>          # Integrated VGA
>     >                                               device pci 0.0 on end
>     >
>
>     This looks fishy, but then again, I never understood the v2 device
>     tree
>     syntax completely.
>

> I'm not sure what looks fishy here.  This is the way I understand it:
> 1. Devices between the 'on' and 'end' tokens are children (or children
> of children) of the device.
> 2. The 'chip' token assigns the driver for devices inside it.
>
> So in this case, device 1.0 has an AGP bus with 0.0 hanging off of it.
In which case the inner device pci 0.0 on end should be removed.
Otherwise it gets assigned an on_mainboard = 1, and be treated as an
on-mainboard graphics card even though it's an AGP plugin card.

Generally, the static tree should only contain devices that can not be
removed

But, to be sure we might want to trust the original authors of the
device trees that they knew what they were doing unless someone reports
a problem or fixes one.

Stefan




From svn at coreboot.org  Sat Nov  7 00:42:27 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  6 Nov 2009 23:42:27 +0000
Subject: [coreboot] [v2] r4925 - in trunk/src: devices drivers
	include/device mainboard/amd/dbm690t mainboard/amd/pistachio
	mainboard/arima/hdama mainboard/artecgroup/dbe61/realmode
	mainboard/asi/mb_5blmp mainboard/asus/mew-vm
	mainboard/broadcom/blast mainboard/digitallogic/msm586seg
	mainboard/emulation/qemu-x86 mainboard/gigabyte/ga_2761gxdk
	mainboard/hp/dl145_g3 mainboard/hp/e_vectra_p2706t
	mainboard/ibm/e326 mainboard/intel/d945gclf
	mainboard/intel/xe7501devkit mainboard/iwill/dk8_htx
	mainboard/kontron/986lcd-m mainboard/kontron/kt690
	mainboard/mitac/6513wu mainboard/msi/ms6178
	mainboard/msi/ms9185 mainboard/msi/ms9282
	mainboard/nec/powermate2000 mainboard/newisys/khepri
	mainboard/rca/rm4100 mainboard/sunw/ultra40
	mainboard/supermicro/h8dme mainboard/supermicro/h8dmr
	mainboard/supermicro/h8dmr_fam10 mainboard/technexion/tim5690
	mainboard/technexion/tim8690 mainboard/technologic/ts5300
	mainboard/thomson/ip1000 mainboard/tyan/s2735
	mainboard/tyan/s2850 mainboard/tyan/s2875
	mainboard/tyan/s2880 mainboard/tyan/s2881
	mainboard/tyan/s2882 mainboard/tyan/s2885
	mainboard/tyan/s2891 mainboard/tyan/s2892
	mainboard/tyan/s2895 mainboard/tyan/s2912_fam10
	mainboard/tyan/s4880 mainboard/tyan/s4882 mainboard/via/epia
	mainboard/via/vt8454c northbridge/via/cn400
	northbridge/via/cn700 northbridge/via/cx700
	northbridge/via/vt8623 northbridge/via/vx800
	southbridge/nvidia/ck804
Message-ID: <mailman.4020.1355071653.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009)
New Revision: 4925

Removed:
   trunk/src/drivers/pci/
Modified:
   trunk/src/devices/pci_device.c
   trunk/src/devices/pci_rom.c
   trunk/src/drivers/Makefile.inc
   trunk/src/include/device/device.h
   trunk/src/mainboard/amd/dbm690t/Config.lb
   trunk/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/src/mainboard/amd/pistachio/Config.lb
   trunk/src/mainboard/amd/pistachio/devicetree.cb
   trunk/src/mainboard/arima/hdama/Config.lb
   trunk/src/mainboard/arima/hdama/devicetree.cb
   trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
   trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
   trunk/src/mainboard/asi/mb_5blmp/Config.lb
   trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
   trunk/src/mainboard/asus/mew-vm/Config.lb
   trunk/src/mainboard/asus/mew-vm/devicetree.cb
   trunk/src/mainboard/broadcom/blast/Config.lb
   trunk/src/mainboard/broadcom/blast/devicetree.cb
   trunk/src/mainboard/digitallogic/msm586seg/Config.lb
   trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
   trunk/src/mainboard/emulation/qemu-x86/mainboard.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/src/mainboard/hp/dl145_g3/Config.lb
   trunk/src/mainboard/hp/dl145_g3/devicetree.cb
   trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
   trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
   trunk/src/mainboard/ibm/e326/Config.lb
   trunk/src/mainboard/ibm/e326/devicetree.cb
   trunk/src/mainboard/intel/d945gclf/Config.lb
   trunk/src/mainboard/intel/d945gclf/devicetree.cb
   trunk/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
   trunk/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/src/mainboard/kontron/986lcd-m/Config.lb
   trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
   trunk/src/mainboard/kontron/kt690/Config.lb
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/mitac/6513wu/Config.lb
   trunk/src/mainboard/mitac/6513wu/devicetree.cb
   trunk/src/mainboard/msi/ms6178/Config.lb
   trunk/src/mainboard/msi/ms6178/devicetree.cb
   trunk/src/mainboard/msi/ms9185/Config.lb
   trunk/src/mainboard/msi/ms9185/devicetree.cb
   trunk/src/mainboard/msi/ms9282/Config.lb
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/nec/powermate2000/Config.lb
   trunk/src/mainboard/nec/powermate2000/devicetree.cb
   trunk/src/mainboard/newisys/khepri/Config.lb
   trunk/src/mainboard/rca/rm4100/Config.lb
   trunk/src/mainboard/rca/rm4100/devicetree.cb
   trunk/src/mainboard/sunw/ultra40/Config.lb
   trunk/src/mainboard/sunw/ultra40/devicetree.cb
   trunk/src/mainboard/supermicro/h8dme/Config.lb
   trunk/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
   trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
   trunk/src/mainboard/technexion/tim5690/Config.lb
   trunk/src/mainboard/technexion/tim5690/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Config.lb
   trunk/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/src/mainboard/technologic/ts5300/Config.lb
   trunk/src/mainboard/technologic/ts5300/devicetree.cb
   trunk/src/mainboard/thomson/ip1000/Config.lb
   trunk/src/mainboard/thomson/ip1000/devicetree.cb
   trunk/src/mainboard/tyan/s2735/Config.lb
   trunk/src/mainboard/tyan/s2735/devicetree.cb
   trunk/src/mainboard/tyan/s2850/Config.lb
   trunk/src/mainboard/tyan/s2850/devicetree.cb
   trunk/src/mainboard/tyan/s2875/Config.lb
   trunk/src/mainboard/tyan/s2875/devicetree.cb
   trunk/src/mainboard/tyan/s2880/Config.lb
   trunk/src/mainboard/tyan/s2880/devicetree.cb
   trunk/src/mainboard/tyan/s2881/Config.lb
   trunk/src/mainboard/tyan/s2881/devicetree.cb
   trunk/src/mainboard/tyan/s2882/Config.lb
   trunk/src/mainboard/tyan/s2882/devicetree.cb
   trunk/src/mainboard/tyan/s2885/Config.lb
   trunk/src/mainboard/tyan/s2885/devicetree.cb
   trunk/src/mainboard/tyan/s2891/devicetree.cb
   trunk/src/mainboard/tyan/s2892/devicetree.cb
   trunk/src/mainboard/tyan/s2895/devicetree.cb
   trunk/src/mainboard/tyan/s2912_fam10/Config.lb
   trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/src/mainboard/tyan/s4880/Config.lb
   trunk/src/mainboard/tyan/s4880/devicetree.cb
   trunk/src/mainboard/tyan/s4882/Config.lb
   trunk/src/mainboard/tyan/s4882/devicetree.cb
   trunk/src/mainboard/via/epia/Config.lb
   trunk/src/mainboard/via/epia/devicetree.cb
   trunk/src/mainboard/via/vt8454c/Config.lb
   trunk/src/mainboard/via/vt8454c/devicetree.cb
   trunk/src/northbridge/via/cn400/vga.c
   trunk/src/northbridge/via/cn700/vga.c
   trunk/src/northbridge/via/cx700/cx700_vga.c
   trunk/src/northbridge/via/vt8623/northbridge.c
   trunk/src/northbridge/via/vx800/vga.c
   trunk/src/southbridge/nvidia/ck804/chip.h
   trunk/src/southbridge/nvidia/ck804/ck804.c
Log:
Remove drivers/pci/onboard.  The only purpose was for option ROMs, which are
now handled more generically using CBFS.

Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/src/devices/pci_device.c
===================================================================
--- trunk/src/devices/pci_device.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/devices/pci_device.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -285,11 +285,6 @@
 	unsigned long value;
 	resource_t moving;
 
-	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
-		/* Skip it if rom_address is not set in the MB Config.lb. */
-		return;
-	}
-
 	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
@@ -326,18 +321,6 @@
 		}
 		resource->flags = 0;
 	}
-
-	/* For on board device with embedded ROM image, the ROM image is at
-	 * fixed address specified in the Config.lb, the dev->rom_address is
-	 * inited by driver_pci_onboard_ops::enable_dev() */
-	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
-		resource->base = dev->rom_address;
-		/* The resource allocator needs the size to be non-zero. */
-		resource->size = 0x100;
-		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
-		    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-	}
-
 	compact_resources(dev);
 }
 

Modified: trunk/src/devices/pci_rom.c
===================================================================
--- trunk/src/devices/pci_rom.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/devices/pci_rom.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -31,42 +31,37 @@
 
 struct rom_header * pci_rom_probe(struct device *dev)
 {
-	unsigned long rom_address = 0;
 	struct rom_header *rom_header;
 	struct pci_data *rom_data;
 
-	void *v;
-	/* if it's in FLASH, then it's as if dev->on_mainboard was true */
-	v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
-	printk_debug("In cbfs, rom address for %s = %p\n", 
-			dev_path(dev), v);
-	if (v) {
-		dev->rom_address = (u32)v;
-		dev->on_mainboard = 1;
-	}
+	/* If it's in FLASH, then don't check device for ROM. */
+	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
-	if (dev->on_mainboard) {
-                // in case some device PCI_ROM_ADDRESS can not be set or readonly 
-		rom_address = dev->rom_address;
-		printk_debug("On mainboard, rom address for %s = %lx\n", 
-			dev_path(dev), rom_address);
+	if (rom_header) {
+		printk_debug("In cbfs, rom address for %s = %p\n",
+			     dev_path(dev), rom_header);
 	} else {
+		unsigned long rom_address;
+
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
-		printk_debug("On card, rom address for %s = %lx\n", 
-				dev_path(dev), rom_address);
-	}
 
-	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-		return NULL;
-	}
+		if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
+			#if CONFIG_BOARD_EMULATION_QEMU_X86
+			rom_address = 0xc0000;
+			#else
+			return NULL;
+			#endif
+		} else {
+			/* enable expansion ROM address decoding */
+			pci_write_config32(dev, PCI_ROM_ADDRESS,
+					   rom_address|PCI_ROM_ADDRESS_ENABLE);
+		}
 
-	if(!dev->on_mainboard) {
-		/* enable expansion ROM address decoding */
-		pci_write_config32(dev, PCI_ROM_ADDRESS,
-				   rom_address|PCI_ROM_ADDRESS_ENABLE);
+		printk_debug("On card, rom address for %s = %lx\n",
+				dev_path(dev), rom_address);
+		rom_header = (struct rom_header *)rom_address;
 	}
 
-	rom_header = (struct rom_header *)rom_address;
 	printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
 		    le32_to_cpu(rom_header->signature),
 		    rom_header->size * 512, le32_to_cpu(rom_header->data));
@@ -76,11 +71,12 @@
 		return NULL;
 	}
 
-	rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data));
+	rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+
 	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
-		printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
+		printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n",
 			   rom_data->vendor, rom_data->device);
 		return NULL;
 	}
@@ -90,7 +86,8 @@
 		    rom_data->type);
 	if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
 		printk_debug("Class Code mismatch ROM %08x, dev %08x\n", 
-			    (rom_data->class_hi << 8) | rom_data->class_lo, dev->class);
+			     (rom_data->class_hi << 8) | rom_data->class_lo,
+			     dev->class);
 		//return NULL;
 	}
 

Modified: trunk/src/drivers/Makefile.inc
===================================================================
--- trunk/src/drivers/Makefile.inc	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/drivers/Makefile.inc	2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,3 +1,2 @@
-subdirs-y += pci
 subdirs-y += generic/debug
 subdirs-y += ati/ragexl

Modified: trunk/src/include/device/device.h
===================================================================
--- trunk/src/include/device/device.h	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/include/device/device.h	2009-11-06 23:42:26 UTC (rev 4925)
@@ -70,7 +70,6 @@
 	unsigned int    enabled : 1;	/* set if we should enable the device */
 	unsigned int    initialized : 1; /* set if we have initialized the device */
 	unsigned int    on_mainboard : 1;
-	unsigned long   rom_address;
 
 	u8 command;
 

Modified: trunk/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -156,9 +156,7 @@
 					device pci 0.0 on end # HT  	0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 					device pci 0.0 on end # HT  	0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -177,9 +177,7 @@
 						device pci 0.1 on  end	# USB1
 						device pci 0.2 off end	# USB 2.0
 						device pci 1.0 off end	# LAN
-						chip drivers/pci/onboard
-							device pci 6.0 on end # ATI Rage XL
-						end
+						device pci 6.0 on end # ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip drivers/generic/generic
 						#	device pci 5.0 on

Modified: trunk/src/mainboard/arima/hdama/devicetree.cb
===================================================================
--- trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -73,9 +73,7 @@
 						device pci 0.1 on  end	# USB1
 						device pci 0.2 off end	# USB 2.0
 						device pci 1.0 off end	# LAN
-						chip drivers/pci/onboard
-							device pci 6.0 on end # ATI Rage XL
-						end
+						device pci 6.0 on end # ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip drivers/generic/generic
 						#	device pci 5.0 on

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h	2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,10 +1,6 @@
 #ifndef PCI_REALMODE_H
 #define PCI_REALMODE_H
 
-struct drivers_pci_realmode_config 
-{
-       unsigned long rom_address;
-};
 //struct chip_operations;
 extern struct chip_operations drivers_pci_realmode_ops;
 

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -74,36 +74,6 @@
   emulator to successfully run this bios.
 */
 
-
-
-
-/*
-  Modified to be an universal driver for loading VGA ROMs.
-  Aug 2006, anti.sullin at artecdesign.ee, Artec Design
-  
-  USAGE:
-  	define in your motherboard Config.lb file in device hierarchy 
-  	around the VGA pci device realmode chip and define its rom address.
-	Rom address is read from Config.lb, this rom is then copied to 0xC000 and then excecuted
-  	
-  		chip drivers/pci/realmode
-				device pci 1.1 on end  					# VGA
-				register "rom_address" = "0xfffc0000"	# at the beginning of 256k
-		end
-  	
-  	then, chip enable is called at this list first traversal, and this sets
-  	up device's init callback. Device init is called during last list traversal and
-  	so, other hw should be already initialized to run vga bios successfully.
-*/
-
-
-
-
-
-
-
-
-
 /* Declare a temporary global descriptor table - necessary because the
    Core part of the bios no longer sets up any 16 bit segments */
 __asm__ (
@@ -918,8 +888,6 @@
 
 	// code to make vga init go through the emulator - as of yet this does not workfor the epia-m
 	dev->on_mainboard=1;
-	dev->rom_address = (void *)cfg->rom_address;
-
 	pci_dev_init(dev);
 
 	// code to make vga init run in real mode - does work but against the current coreboot philosophy 

Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -135,11 +135,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -37,11 +37,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -97,18 +97,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -2,18 +2,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -207,21 +207,8 @@
                                         device pci 2.0 on end # USB        0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
-                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is in bcm5785_0 bus
                                 end
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end # fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb
===================================================================
--- trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -105,21 +105,8 @@
                                         device pci 2.0 on end # USB        0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
-                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is in bcm5785_0 bus
                                 end
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end # fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -102,13 +102,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,13 +1,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c
===================================================================
--- trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -16,7 +16,6 @@
 	 * force coreboot to use it.
 	 */
 	dev->on_mainboard = 1;
-	dev->rom_address = 0xc0000;
 
 	/* Now do the usual initialization */
 	pci_dev_init(dev);

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -178,9 +178,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   # Northbridge
 					device pci 1.0 on		# AGP bridge
-					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -11,9 +11,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   # Northbridge
 					device pci 1.0 on		# AGP bridge
-					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -195,15 +195,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard    #SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -72,15 +72,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard    #SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -76,9 +76,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -7,9 +7,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -125,9 +125,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end # ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/ibm/e326/devicetree.cb
===================================================================
--- trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end # ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/intel/d945gclf/Config.lb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -150,9 +150,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -28,9 +28,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -127,9 +127,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -25,9 +25,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -232,9 +232,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip drivers/pci/onboard
-                                                #        device pci 6.0 on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -24,9 +24,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip drivers/pci/onboard
-                                                #        device pci 6.0 on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -153,9 +153,7 @@
                 device pci 00.0 on end # host bridge
 		# autodetect 0:1.0 because it might or might not be there.
 		# device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -9,9 +9,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/kt690/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/mitac/6513wu/Config.lb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -80,9 +80,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -75,9 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -207,29 +207,8 @@
                                         device pci 2.0 on end # USB        0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
-                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard    #SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is in bcm5785_0 bus
                                 end
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end # fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -73,29 +73,8 @@
                                         device pci 2.0 on end # USB        0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
-                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard    #SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is in bcm5785_0 bus
                                 end
-                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end # fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -278,27 +278,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0 on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip drivers/pci/onboard
-                                                               device pci 4.0 on end  #pci_E lan1
-                                                               device pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0 on end  #pci_E lan1
+                                                       device pci 4.1 on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end # PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0 on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0 0x375
                                        device pci f.0 on end   #PCI E 0x377  pci_E slot

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -137,27 +137,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0 on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip drivers/pci/onboard
-                                                               device pci 4.0 on end  #pci_E lan1
-                                                               device pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0 on end  #pci_E lan1
+                                                       device pci 4.1 on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end # PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0 on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0 0x375
                                        device pci f.0 on end   #PCI E 0x377  pci_E slot

Modified: trunk/src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -75,11 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -6,11 +6,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -98,8 +98,6 @@
 
 config chip.h
 
-# FIXME: ROM for onboard VGA
-
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
 		chip cpu/amd/socket_940

Modified: trunk/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb
===================================================================
--- trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -210,8 +210,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" = "0xfff80000" # 64k
-#					register "raid_rom_address" = "0xfff90000"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
@@ -243,7 +241,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" = "0xfff80000" # 64k
                                         register "mac_eeprom_smbus" = "3"
                                         register "mac_eeprom_addr" = "0x51"
                         	end

Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -106,8 +106,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" = "0xfff80000" # 64k
-#					register "raid_rom_address" = "0xfff90000"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
@@ -139,7 +137,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" = "0xfff80000" # 64k
                                         register "mac_eeprom_smbus" = "3"
                                         register "mac_eeprom_addr" = "0x51"
                         	end

Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -254,9 +254,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -92,9 +92,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -276,9 +276,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -280,9 +280,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -114,9 +114,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/technexion/tim5690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT  	0x7910
 					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0 on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end	# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE P2P bridge	0x791b

Modified: trunk/src/mainboard/technologic/ts5300/Config.lb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -104,12 +104,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -2,12 +2,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -100,10 +100,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end # intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -117,12 +115,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -6,10 +6,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end # intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -23,12 +21,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -119,9 +119,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0 on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -17,9 +17,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0 on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -123,9 +123,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -113,10 +113,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end #broadcom
-							device pci 9.1 on end 
-                                                end
+                                                device pci 9.0 on end #broadcom
+						device pci 9.1 on end
 #                                                chip drivers/lsi/53c1030
 #                                                        device pci a.0 on end
 #                                                        device pci a.1 on end
@@ -135,12 +133,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end #some sata
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end #adti
-                                                end
+                                                device pci 5.0 on end #some sata
+                                                device pci 6.0 on end #adti
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -11,10 +11,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end #broadcom
-							device pci 9.1 on end 
-                                                end
+                                                device pci 9.0 on end #broadcom
+						device pci 9.1 on end
 #                                                chip drivers/lsi/53c1030
 #                                                        device pci a.0 on end
 #                                                        device pci a.1 on end
@@ -33,12 +31,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end #some sata
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end #adti
-                                                end
+                                                device pci 5.0 on end #some sata
+                                                device pci 6.0 on end #adti
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -115,14 +115,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # Broadcom 5704
-                                                        device pci 9.1 on end
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci a.0 on end # Adaptic
-                                                        device pci a.1 on end
-                                                end
+                                                device pci 9.0 on end # Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end # Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -136,12 +132,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end # SiI
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 5.0 on end # SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -13,14 +13,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # Broadcom 5704
-                                                        device pci 9.1 on end
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci a.0 on end # Adaptic
-                                                        device pci a.1 on end
-                                                end
+                                                device pci 9.0 on end # Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end # Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -34,12 +30,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end # SiI
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 5.0 on end # SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -114,14 +114,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on
-                                                chip drivers/pci/onboard 
-                                                        device pci 6.0 on end # adaptec
-                                                        device pci 6.1 on end
-                                                end 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # broadcom 5704
-                                                        device pci 9.1 on end
-                                                end
+                                                device pci 6.0 on end # adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end # broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -135,16 +131,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard  
-                                                        device pci 5.0 on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
-                                                chip drivers/pci/onboard 
-                                                        device pci 8.0 on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end #intel 10/100
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -12,14 +12,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on
-                                                chip drivers/pci/onboard 
-                                                        device pci 6.0 on end # adaptec
-                                                        device pci 6.1 on end
-                                                end 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # broadcom 5704
-                                                        device pci 9.1 on end
-                                                end
+                                                device pci 6.0 on end # adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end # broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -33,16 +29,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard  
-                                                        device pci 5.0 on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
-                                                chip drivers/pci/onboard 
-                                                        device pci 8.0 on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end #intel 10/100
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -121,9 +121,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end # broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -137,9 +135,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci b.0 on end # SiI 3114
-                                                end
+                                                device pci b.0 on end # SiI 3114
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -19,9 +19,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is mandatory
 					device pci 0.0 on 
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end # broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,9 +33,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci b.0 on end # SiI 3114
-                                                end
+                                                device pci b.0 on end # SiI 3114
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -104,9 +104,7 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 7.0 on end
-						end
+						device pci 7.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -127,10 +125,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0 on end
-							device pci 9.1 on end
-						end
+						device pci 9.0 on end
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -105,12 +105,9 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 6.0 on end
-						end
-						chip drivers/pci/onboard
-							device pci 8.0 on end
-						end
+						device pci 6.0 on end
+					#	end
+						device pci 8.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -131,10 +128,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0 on end # broadcom 5704
-							device pci 9.1 on end
-						end
+						device pci 9.0 on end # broadcom 5704
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -111,10 +111,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 6.0 on end # lsi scsi
-							device pci 6.1 on end
-						end
+						device pci 6.0 on end # lsi scsi
+						device pci 6.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -279,9 +279,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0 on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0 on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -116,10 +116,8 @@
 #                                                        device pci 4.1 on end
 #                                                        register "fw_address" = "0xfff8c000"
 #                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end
-                                                        device pci 9.1 on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -133,9 +131,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -19,10 +19,8 @@
 #                                                        device pci 4.1 on end
 #                                                        register "fw_address" = "0xfff8c000"
 #                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end
-                                                        device pci 9.1 on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -36,9 +34,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -114,10 +114,8 @@
 #							device pci 4.1 on end
 #							register "fw_address" = "0xfff8c000"
 #						end
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end #Broadcom
-                                                        device pci 9.1 on end
-                                                end 
+                                                device pci 9.0 on end #Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -132,12 +130,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip drivers/ati/ragexl
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end #SiI
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -17,10 +17,8 @@
 #							device pci 4.1 on end
 #							register "fw_address" = "0xfff8c000"
 #						end
-                                                chip drivers/pci/onboard
-                                                        device pci 9.0 on end #Broadcom
-                                                        device pci 9.1 on end
-                                                end 
+                                                device pci 9.0 on end #Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,12 +33,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip drivers/ati/ragexl
-                                                chip drivers/pci/onboard
-                                                        device pci 6.0 on end
-                                                end
-                                                chip drivers/pci/onboard
-                                                        device pci 5.0 on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end #SiI
 					end
 					device pci 1.0 on
 						chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/via/epia/Config.lb
===================================================================
--- trunk/src/mainboard/via/epia/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/epia/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -96,10 +96,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/epia/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -2,10 +2,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/vt8454c/Config.lb
===================================================================
--- trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -121,9 +121,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06 23:42:26 UTC (rev 4925)
@@ -12,9 +12,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/northbridge/via/cn400/vga.c
===================================================================
--- trunk/src/northbridge/via/cn400/vga.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/cn400/vga.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -121,15 +121,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cn700/vga.c
===================================================================
--- trunk/src/northbridge/via/cn700/vga.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/cn700/vga.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -101,15 +101,8 @@
 	memset(0xf0000, 0, 0x10000);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cx700/cx700_vga.c
===================================================================
--- trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -97,15 +97,8 @@
 	outb(reg8, SR_DATA);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -124,9 +124,6 @@
 	
 #if 0
 	/* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
-	dev->on_mainboard=1;
-	dev->rom_address = (void *)0xfffc0000;
-
 	pci_dev_init(dev);
 	
 	call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
@@ -167,17 +164,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-
-	dev->rom_address = (void *)0xfffc0000;
-	dev->on_mainboard=1;
-	pci_dev_read_resources(dev);
-
-}
-
 static struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/vx800/vga.c
===================================================================
--- trunk/src/northbridge/via/vx800/vga.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/vx800/vga.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -126,15 +126,8 @@
 
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 23:42:26 UTC (rev 4925)
@@ -7,8 +7,6 @@
 	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
-	unsigned long nic_rom_address;
-	unsigned long raid_rom_address;
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };

Modified: trunk/src/southbridge/nvidia/ck804/ck804.c
===================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -77,12 +77,10 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
 		devfn -= (3 << 3);
@@ -95,7 +93,6 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
 		devfn -= (5 << 3);
 		index = 14;
-		dev->rom_address = conf->raid_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
 		devfn -= (6 << 3);




From mylesgw at gmail.com  Sat Nov  7 00:43:42 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 17:43:42 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <4AF4A3AA.6010600@gmx.net>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
	<4AF49668.2000904@gmx.net>
	<2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
	<4AF4A3AA.6010600@gmx.net>
Message-ID: <2831fecf0911061543q64c0c45ak731ff314b9503add@mail.gmail.com>

> Go ahead!

Rev 4925.

Thanks,
Myles
-------------- next part --------------
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From mylesgw at gmail.com  Sat Nov  7 00:46:13 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 6 Nov 2009 17:46:13 -0600
Subject: [coreboot] [PATCH] Drop drivers/pci/onboard
In-Reply-To: <4AF4AF0F.2000107@coresystems.de>
References: <2831fecf0911060914h178daafdxf4a4f890aa2d60ac@mail.gmail.com>
	<4AF45FBE.9050708@gmx.net>
	<2831fecf0911060946meb058fao84008939cc880c00@mail.gmail.com>
	<20091106184135.28623.qmail@stuge.se>
	<2831fecf0911061056o4de4e534h6541540d8026cef4@mail.gmail.com>
	<2831fecf0911061114y2e645388v7ea59ccfd2ecd38d@mail.gmail.com>
	<2831fecf0911061302i37edc969n1ffe7501aa56bd33@mail.gmail.com>
	<4AF49668.2000904@gmx.net>
	<2831fecf0911061347o3bec459elfb309567d38bb119@mail.gmail.com>
	<4AF4AF0F.2000107@coresystems.de>
Message-ID: <2831fecf0911061546x191b2346s3494d5f1979ed13a@mail.gmail.com>

> >
> >     > Index: svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> >     > ===================================================================
> >     > --- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> >     > +++ svn/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
> >     > @@ -178,9 +178,7 @@ chip northbridge/amd/amdk8/root_complex
> >     >                               chip southbridge/sis/sis966
> >     >                                       device pci 0.0 on end   #
> >     Northbridge
> >     >                                       device pci 1.0 on
> >           # AGP bridge
> >     > -                                       chip drivers/pci/onboard
> >          # Integrated VGA
> >     >                                               device pci 0.0 on end
> >     >
> >
> >     This looks fishy, but then again, I never understood the v2 device
> >     tree
> >     syntax completely.
> >
>
> > I'm not sure what looks fishy here.  This is the way I understand it:
> > 1. Devices between the 'on' and 'end' tokens are children (or children
> > of children) of the device.
> > 2. The 'chip' token assigns the driver for devices inside it.
> >
> > So in this case, device 1.0 has an AGP bus with 0.0 hanging off of it.
> In which case the inner device pci 0.0 on end should be removed.
> Otherwise it gets assigned an on_mainboard = 1, and be treated as an
> on-mainboard graphics card even though it's an AGP plugin card.
>
Yeah.  I thought maybe it was on-mainboard AGP.


> Generally, the static tree should only contain devices that can not be
> removed
>
Agreed.  That gets a little problematic with some of the "stuff options"
where some of the boards have SCSI or an extra nic or...

But, to be sure we might want to trust the original authors of the
> device trees that they knew what they were doing unless someone reports
> a problem or fixes one.
>
Sounds good.

Thanks,
Myles
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From svn at coreboot.org  Sat Nov  7 01:08:22 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  7 Nov 2009 00:08:22 +0000
Subject: [coreboot] [v2] r4926 - in branches/coreboot-v1: src/arch/alpha
	src/arch/alpha/init src/arch/i386 src/arch/i386/init
	src/arch/ppc src/arch/ppc/init src/config src/lib util/config
Message-ID: <mailman.4021.1355071653.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-07 00:08:22 +0000 (Sat, 07 Nov 2009)
New Revision: 4926

Added:
   branches/coreboot-v1/src/arch/alpha/init/
   branches/coreboot-v1/src/arch/i386/init/
   branches/coreboot-v1/src/arch/ppc/init/
Removed:
   branches/coreboot-v1/src/arch/alpha/config/
   branches/coreboot-v1/src/arch/i386/config/
   branches/coreboot-v1/src/arch/ppc/config/
Modified:
   branches/coreboot-v1/src/arch/alpha/init/make.base
   branches/coreboot-v1/src/arch/i386/init/make.base
   branches/coreboot-v1/src/arch/ppc/init/make.base
   branches/coreboot-v1/src/config/Config
   branches/coreboot-v1/src/lib/clog2.c
   branches/coreboot-v1/util/config/NLBConfig.py
Log:
Some operating systems, such as Windows and Mac OS X use case insensitive
filesystems per default. On those systems checking out coreboot v1 would fail
because in src/arch/<ARCH> there's a file Config and a directory config.

I renamed the directory to init. The name is not good, but it's the same name
that is used for those files in v2.

Also change __FUNCTION__ to __func__ and print it via %s so that I could test
my changes by building the v1 Epia target on an OpenSUSE 11.1

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: branches/coreboot-v1/src/arch/alpha/init/make.base
===================================================================
--- branches/coreboot-v1/src/arch/alpha/config/make.base	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/src/arch/alpha/init/make.base	2009-11-07 00:08:22 UTC (rev 4926)
@@ -2,7 +2,7 @@
 rambase 0x8000
 
 option USE_DEFAULT_LAYOUT=1
-ldscript arch/alpha/config/ldscript.base USE_DEFAULT_LAYOUT
+ldscript arch/alpha/init/ldscript.base USE_DEFAULT_LAYOUT
 
 option MAX_CPUS=1
 

Modified: branches/coreboot-v1/src/arch/i386/init/make.base
===================================================================
--- branches/coreboot-v1/src/arch/i386/config/make.base	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/src/arch/i386/init/make.base	2009-11-07 00:08:22 UTC (rev 4926)
@@ -13,7 +13,7 @@
 # By default on x86 we have a memory hole between 640K and 1MB
 option MEMORY_HOLE=1
 
-ldscript arch/i386/config/ldscript.base
+ldscript arch/i386/init/ldscript.base
 
 # How do I add -mprefered-stack-boundary=2 if the compiler supports it?
 # On x86 tt results in a code size reduction.

Modified: branches/coreboot-v1/src/arch/ppc/init/make.base
===================================================================
--- branches/coreboot-v1/src/arch/ppc/config/make.base	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/src/arch/ppc/init/make.base	2009-11-07 00:08:22 UTC (rev 4926)
@@ -5,7 +5,7 @@
 # Reserve 8K for each stack
 option STACK_SIZE=0x2000
 
-ldscript arch/ppc/config/ldscript.base
+ldscript arch/ppc/init/ldscript.base
 
 dir /src/config
 

Modified: branches/coreboot-v1/src/config/Config
===================================================================
--- branches/coreboot-v1/src/config/Config	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/src/config/Config	2009-11-07 00:08:22 UTC (rev 4926)
@@ -55,7 +55,7 @@
 makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a
 addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1)
 
-option CRT0=$(TOP)/src/arch/$(ARCH)/config/crt0.base
+option CRT0=$(TOP)/src/arch/$(ARCH)/init/crt0.base
 makerule crt0.S: $(CRT0) ; cp $< $@
 
 # Force crt0.s (which has build time version code in it to rebuild every time)

Modified: branches/coreboot-v1/src/lib/clog2.c
===================================================================
--- branches/coreboot-v1/src/lib/clog2.c	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/src/lib/clog2.c	2009-11-07 00:08:22 UTC (rev 4926)
@@ -7,8 +7,8 @@
         unsigned long pow = sizeof(x) * 8 - 1;
 
         if (! x) {
-                printk_emerg(__FUNCTION__ 
-                        " called with invalid parameter of 0\n");
+                printk_emerg("%s called with invalid parameter of 0\n",
+				__func__);
                 return -1;
         }
         for(; i > x; i >>= 1, pow--)

Modified: branches/coreboot-v1/util/config/NLBConfig.py
===================================================================
--- branches/coreboot-v1/util/config/NLBConfig.py	2009-11-06 23:42:26 UTC (rev 4925)
+++ branches/coreboot-v1/util/config/NLBConfig.py	2009-11-07 00:08:22 UTC (rev 4926)
@@ -261,7 +261,7 @@
 def set_arch(dir, my_arch):
 	global arch, makebase
 	arch = my_arch
-	configpath = os.path.join(treetop, "src/arch/", my_arch, "config")
+	configpath = os.path.join(treetop, "src/arch/", my_arch, "init")
 	makebase = os.path.join(configpath, "make.base")
 	print "Now Process the ", my_arch, " base files"
 	if (debug):
@@ -1135,7 +1135,7 @@
 
 	for depfile in [ '%s' % top_config_file,    # This a duplicate, remove?
 			'$(TOP)/util/config/NLBConfig.py',
-			'$(TOP)/src/arch/$(ARCH)/config/make.base' ]:
+			'$(TOP)/src/arch/$(ARCH)/init/make.base' ]:
 		file.write("$(GENERATED): %s\n" % depfile)
 
 	file.write("$(GENERATED):\n")
@@ -1180,7 +1180,7 @@
 	
 # Set the default locations for config files.
 makebase = os.path.join(treetop, "util/config/make.base")
-crt0base = os.path.join(treetop, "arch/i386/config/crt0.base")
+crt0base = os.path.join(treetop, "arch/i386/init/crt0.base")
 doxyscriptbase = os.path.join(treetop, "src/config/doxyscript.base")
 
 # Now read in the customizing script...




From svn at coreboot.org  Sat Nov  7 01:45:18 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  7 Nov 2009 00:45:18 +0000
Subject: [coreboot] [commit] r4927 - in branches/coreboot-v1: . util/ADLO
	util/ADLO/bochs
Message-ID: <mailman.4022.1355071653.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-07 00:45:17 +0000 (Sat, 07 Nov 2009)
New Revision: 4927

Removed:
   branches/coreboot-v1/.cvsignore
   branches/coreboot-v1/util/ADLO/.cvsignore
   branches/coreboot-v1/util/ADLO/bochs/.cvsignore
Log:
drop obsolete .cvsignore files..
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Deleted: branches/coreboot-v1/.cvsignore
===================================================================
--- branches/coreboot-v1/.cvsignore	2009-11-07 00:08:22 UTC (rev 4926)
+++ branches/coreboot-v1/.cvsignore	2009-11-07 00:45:17 UTC (rev 4927)
@@ -1,12 +0,0 @@
-COPYING
-INSTALL
-install-sh
-missing
-mkinstalldirs
-aclocal.m4
-Makefile.in
-configure
-config.log
-config.cache
-config.status
-Makefile

Deleted: branches/coreboot-v1/util/ADLO/.cvsignore
===================================================================
--- branches/coreboot-v1/util/ADLO/.cvsignore	2009-11-07 00:08:22 UTC (rev 4926)
+++ branches/coreboot-v1/util/ADLO/.cvsignore	2009-11-07 00:45:17 UTC (rev 4927)
@@ -1 +0,0 @@
-payload

Deleted: branches/coreboot-v1/util/ADLO/bochs/.cvsignore
===================================================================
--- branches/coreboot-v1/util/ADLO/bochs/.cvsignore	2009-11-07 00:08:22 UTC (rev 4926)
+++ branches/coreboot-v1/util/ADLO/bochs/.cvsignore	2009-11-07 00:45:17 UTC (rev 4927)
@@ -1 +0,0 @@
-bochs-cvs




From fishbaoz at hotmail.com  Sun Nov  8 04:57:55 2009
From: fishbaoz at hotmail.com (Zheng Bao)
Date: Sun, 8 Nov 2009 03:57:55 +0000
Subject: [coreboot] [PATCH] Kconfig of socket_AM2r2
Message-ID: <COL112-W40B5C8B05C014BAC416933CDAD0@phx.gbl>


Complete the Kconfig of socket_AM2r2.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>


Index: src/cpu/amd/socket_AM2r2/Kconfig
===================================================================
--- src/cpu/amd/socket_AM2r2/Kconfig (revision 4914)
+++ src/cpu/amd/socket_AM2r2/Kconfig (working copy)
@@ -2,6 +2,7 @@
  bool
  select CPU_AMD_MODEL_10XXX
  select HT3_SUPPORT
+ select PCI_IO_CFG_EXT
 
 config CPU_SOCKET_TYPE
  hex
@@ -14,3 +15,32 @@
  default 0x0104
  depends on CPU_AMD_SOCKET_AM2R2
 
+config EXT_RT_TBL_SUPPORT
+ bool
+ default n
+ depends on CPU_AMD_SOCKET_AM2R2
+
+config EXT_CONF_SUPPORT
+ bool
+ default n
+ depends on CPU_AMD_SOCKET_AM2R2
+
+config CBB
+ hex
+ default 0x0
+ depends on CPU_AMD_SOCKET_AM2R2
+
+config CDB
+ hex
+ default 0x18
+ depends on CPU_AMD_SOCKET_AM2R2
+
+config XIP_ROM_BASE
+ hex
+ default 0xfff80000
+ depends on CPU_AMD_SOCKET_AM2R2
+
+config XIP_ROM_SIZE
+ hex
+ default 0x80000
+ depends on CPU_AMD_SOCKET_AM2R2

 		 	   		  
_________________________________________________________________
Windows Live: Keep your friends up to date with what you do online.
http://www.microsoft.com/middleeast/windows/windowslive/see-it-in-action/social-network-basics.aspx?ocid=PID23461::T:WLMTAGL:ON:WL:en-xm:SI_SB_1:092010
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From gleb at redhat.com  Sun Nov  8 14:47:19 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Sun, 8 Nov 2009 15:47:19 +0200
Subject: [coreboot] [PATCH] Seabios on Virtutech Simics x86-440bx model
In-Reply-To: <4AF2DA8D.1070302@virtutech.com>
References: <4AF04CD4.1030007@virtutech.com>
	<20091104033012.GA32618@morn.localdomain>
	<20091104144011.GR27911@redhat.com>
	<4AF29B49.7090001@virtutech.com>
	<20091105095447.GV27911@redhat.com>
	<4AF2A7D1.6010809@virtutech.com>
	<20091105104953.GA15913@redhat.com>
	<4AF2CCD1.9010709@virtutech.com>
	<20091105130439.GX27911@redhat.com>
	<4AF2DA8D.1070302@virtutech.com>
Message-ID: <20091108134719.GA4717@redhat.com>

On Thu, Nov 05, 2009 at 03:00:45PM +0100, Magnus Christensson wrote:
> Ok. Changed patches attached.
Looks good to me.

--
			Gleb.



From Zheng.Bao at amd.com  Mon Nov  9 10:01:36 2009
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Mon, 9 Nov 2009 17:01:36 +0800
Subject: [coreboot] [v2] r4925 makes my linux hang
In-Reply-To: <8f1fa25e-5e5d-407c-a131-d2d1b672c00a@VA3EHSMHS012.ehs.local>
References: <8f1fa25e-5e5d-407c-a131-d2d1b672c00a@VA3EHSMHS012.ehs.local>
Message-ID: <DD1CC71B621B004FA76856E5129D6B17032F3B29@sbjgexmb1.amd.com>

R4925 makes my linux hang. Output is attached.
My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700).
But dbm690t works well. I don't know why.

Zheng


-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of svn at coreboot.org
Sent: Saturday, November 07, 2009 7:42 AM
To: coreboot at coreboot.org
Subject: [coreboot] [v2] r4925 - in trunk/src: devices
driversinclude/device mainboard/amd/dbm690t
mainboard/amd/pistachiomainboard/arima/hdama
mainboard/artecgroup/dbe61/realmodemainboard/asi/mb_5blmp
mainboard/asus/mew-vmmainboard/broadcom/blast mainboard/digita

Author: myles
Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009)
New Revision: 4925

Removed:
   trunk/src/drivers/pci/
Modified:
   trunk/src/devices/pci_device.c
   trunk/src/devices/pci_rom.c
   trunk/src/drivers/Makefile.inc
   trunk/src/include/device/device.h
   trunk/src/mainboard/amd/dbm690t/Config.lb
   trunk/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/src/mainboard/amd/pistachio/Config.lb
   trunk/src/mainboard/amd/pistachio/devicetree.cb
   trunk/src/mainboard/arima/hdama/Config.lb
   trunk/src/mainboard/arima/hdama/devicetree.cb
   trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
   trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
   trunk/src/mainboard/asi/mb_5blmp/Config.lb
   trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
   trunk/src/mainboard/asus/mew-vm/Config.lb
   trunk/src/mainboard/asus/mew-vm/devicetree.cb
   trunk/src/mainboard/broadcom/blast/Config.lb
   trunk/src/mainboard/broadcom/blast/devicetree.cb
   trunk/src/mainboard/digitallogic/msm586seg/Config.lb
   trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
   trunk/src/mainboard/emulation/qemu-x86/mainboard.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/src/mainboard/hp/dl145_g3/Config.lb
   trunk/src/mainboard/hp/dl145_g3/devicetree.cb
   trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
   trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
   trunk/src/mainboard/ibm/e326/Config.lb
   trunk/src/mainboard/ibm/e326/devicetree.cb
   trunk/src/mainboard/intel/d945gclf/Config.lb
   trunk/src/mainboard/intel/d945gclf/devicetree.cb
   trunk/src/mainboard/intel/xe7501devkit/Config.lb
   trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
   trunk/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/src/mainboard/kontron/986lcd-m/Config.lb
   trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
   trunk/src/mainboard/kontron/kt690/Config.lb
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/mitac/6513wu/Config.lb
   trunk/src/mainboard/mitac/6513wu/devicetree.cb
   trunk/src/mainboard/msi/ms6178/Config.lb
   trunk/src/mainboard/msi/ms6178/devicetree.cb
   trunk/src/mainboard/msi/ms9185/Config.lb
   trunk/src/mainboard/msi/ms9185/devicetree.cb
   trunk/src/mainboard/msi/ms9282/Config.lb
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/nec/powermate2000/Config.lb
   trunk/src/mainboard/nec/powermate2000/devicetree.cb
   trunk/src/mainboard/newisys/khepri/Config.lb
   trunk/src/mainboard/rca/rm4100/Config.lb
   trunk/src/mainboard/rca/rm4100/devicetree.cb
   trunk/src/mainboard/sunw/ultra40/Config.lb
   trunk/src/mainboard/sunw/ultra40/devicetree.cb
   trunk/src/mainboard/supermicro/h8dme/Config.lb
   trunk/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
   trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
   trunk/src/mainboard/technexion/tim5690/Config.lb
   trunk/src/mainboard/technexion/tim5690/devicetree.cb
   trunk/src/mainboard/technexion/tim8690/Config.lb
   trunk/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/src/mainboard/technologic/ts5300/Config.lb
   trunk/src/mainboard/technologic/ts5300/devicetree.cb
   trunk/src/mainboard/thomson/ip1000/Config.lb
   trunk/src/mainboard/thomson/ip1000/devicetree.cb
   trunk/src/mainboard/tyan/s2735/Config.lb
   trunk/src/mainboard/tyan/s2735/devicetree.cb
   trunk/src/mainboard/tyan/s2850/Config.lb
   trunk/src/mainboard/tyan/s2850/devicetree.cb
   trunk/src/mainboard/tyan/s2875/Config.lb
   trunk/src/mainboard/tyan/s2875/devicetree.cb
   trunk/src/mainboard/tyan/s2880/Config.lb
   trunk/src/mainboard/tyan/s2880/devicetree.cb
   trunk/src/mainboard/tyan/s2881/Config.lb
   trunk/src/mainboard/tyan/s2881/devicetree.cb
   trunk/src/mainboard/tyan/s2882/Config.lb
   trunk/src/mainboard/tyan/s2882/devicetree.cb
   trunk/src/mainboard/tyan/s2885/Config.lb
   trunk/src/mainboard/tyan/s2885/devicetree.cb
   trunk/src/mainboard/tyan/s2891/devicetree.cb
   trunk/src/mainboard/tyan/s2892/devicetree.cb
   trunk/src/mainboard/tyan/s2895/devicetree.cb
   trunk/src/mainboard/tyan/s2912_fam10/Config.lb
   trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/src/mainboard/tyan/s4880/Config.lb
   trunk/src/mainboard/tyan/s4880/devicetree.cb
   trunk/src/mainboard/tyan/s4882/Config.lb
   trunk/src/mainboard/tyan/s4882/devicetree.cb
   trunk/src/mainboard/via/epia/Config.lb
   trunk/src/mainboard/via/epia/devicetree.cb
   trunk/src/mainboard/via/vt8454c/Config.lb
   trunk/src/mainboard/via/vt8454c/devicetree.cb
   trunk/src/northbridge/via/cn400/vga.c
   trunk/src/northbridge/via/cn700/vga.c
   trunk/src/northbridge/via/cx700/cx700_vga.c
   trunk/src/northbridge/via/vt8623/northbridge.c
   trunk/src/northbridge/via/vx800/vga.c
   trunk/src/southbridge/nvidia/ck804/chip.h
   trunk/src/southbridge/nvidia/ck804/ck804.c
Log:
Remove drivers/pci/onboard.  The only purpose was for option ROMs, which
are
now handled more generically using CBFS.

Simplify the option ROM code in device/pci_rom.c, since there are only
two ways
to get a ROM address now (CBFS and the device) and add an exception for
qemu.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/src/devices/pci_device.c
===================================================================
--- trunk/src/devices/pci_device.c	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/devices/pci_device.c	2009-11-06 23:42:26 UTC (rev
4925)
@@ -285,11 +285,6 @@
 	unsigned long value;
 	resource_t moving;
 
-	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
-		/* Skip it if rom_address is not set in the MB
Config.lb. */
-		return;
-	}
-
 	/* Initialize the resources to nothing. */
 	resource = new_resource(dev, index);
 
@@ -326,18 +321,6 @@
 		}
 		resource->flags = 0;
 	}
-
-	/* For on board device with embedded ROM image, the ROM image is
at
-	 * fixed address specified in the Config.lb, the
dev->rom_address is
-	 * inited by driver_pci_onboard_ops::enable_dev() */
-	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
-		resource->base = dev->rom_address;
-		/* The resource allocator needs the size to be non-zero.
*/
-		resource->size = 0x100;
-		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY
|
-		    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-	}
-
 	compact_resources(dev);
 }
 

Modified: trunk/src/devices/pci_rom.c
===================================================================
--- trunk/src/devices/pci_rom.c	2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/devices/pci_rom.c	2009-11-06 23:42:26 UTC (rev 4925)
@@ -31,42 +31,37 @@
 
 struct rom_header * pci_rom_probe(struct device *dev)
 {
-	unsigned long rom_address = 0;
 	struct rom_header *rom_header;
 	struct pci_data *rom_data;
 
-	void *v;
-	/* if it's in FLASH, then it's as if dev->on_mainboard was true
*/
-	v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
-	printk_debug("In cbfs, rom address for %s = %p\n", 
-			dev_path(dev), v);
-	if (v) {
-		dev->rom_address = (u32)v;
-		dev->on_mainboard = 1;
-	}
+	/* If it's in FLASH, then don't check device for ROM. */
+	rom_header = cbfs_load_optionrom(dev->vendor, dev->device,
NULL);
 
-	if (dev->on_mainboard) {
-                // in case some device PCI_ROM_ADDRESS can not be set
or readonly 
-		rom_address = dev->rom_address;
-		printk_debug("On mainboard, rom address for %s = %lx\n",

-			dev_path(dev), rom_address);
+	if (rom_header) {
+		printk_debug("In cbfs, rom address for %s = %p\n",
+			     dev_path(dev), rom_header);
 	} else {
+		unsigned long rom_address;
+
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
-		printk_debug("On card, rom address for %s = %lx\n", 
-				dev_path(dev), rom_address);
-	}
 
-	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-		return NULL;
-	}
+		if (rom_address == 0x00000000 || rom_address ==
0xffffffff) {
+			#if CONFIG_BOARD_EMULATION_QEMU_X86
+			rom_address = 0xc0000;
+			#else
+			return NULL;
+			#endif
+		} else {
+			/* enable expansion ROM address decoding */
+			pci_write_config32(dev, PCI_ROM_ADDRESS,
+
rom_address|PCI_ROM_ADDRESS_ENABLE);
+		}
 
-	if(!dev->on_mainboard) {
-		/* enable expansion ROM address decoding */
-		pci_write_config32(dev, PCI_ROM_ADDRESS,
-				   rom_address|PCI_ROM_ADDRESS_ENABLE);
+		printk_debug("On card, rom address for %s = %lx\n",
+				dev_path(dev), rom_address);
+		rom_header = (struct rom_header *)rom_address;
 	}
 
-	rom_header = (struct rom_header *)rom_address;
 	printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size
0x%04x, data ptr 0x%04x\n",
 		    le32_to_cpu(rom_header->signature),
 		    rom_header->size * 512,
le32_to_cpu(rom_header->data));
@@ -76,11 +71,12 @@
 		return NULL;
 	}
 
-	rom_data = (struct pci_data *) ((void *)rom_header +
le32_to_cpu(rom_header->data));
+	rom_data = (((void *)rom_header) +
le32_to_cpu(rom_header->data));
+
 	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device !=
rom_data->device) {
-		printk_err("Device or Vendor ID mismatch Vendor %04x,
Device %04x\n",
+		printk_err("ID mismatch: Vendor ID %04x, Device ID
%04x\n",
 			   rom_data->vendor, rom_data->device);
 		return NULL;
 	}
@@ -90,7 +86,8 @@
 		    rom_data->type);
 	if (dev->class != ((rom_data->class_hi << 8) |
rom_data->class_lo)) {
 		printk_debug("Class Code mismatch ROM %08x, dev %08x\n",

-			    (rom_data->class_hi << 8) |
rom_data->class_lo, dev->class);
+			     (rom_data->class_hi << 8) |
rom_data->class_lo,
+			     dev->class);
 		//return NULL;
 	}
 

Modified: trunk/src/drivers/Makefile.inc
===================================================================
--- trunk/src/drivers/Makefile.inc	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/drivers/Makefile.inc	2009-11-06 23:42:26 UTC (rev
4925)
@@ -1,3 +1,2 @@
-subdirs-y += pci
 subdirs-y += generic/debug
 subdirs-y += ati/ragexl

Modified: trunk/src/include/device/device.h
===================================================================
--- trunk/src/include/device/device.h	2009-11-06 17:32:32 UTC (rev
4924)
+++ trunk/src/include/device/device.h	2009-11-06 23:42:26 UTC (rev
4925)
@@ -70,7 +70,6 @@
 	unsigned int    enabled : 1;	/* set if we should enable the
device */
 	unsigned int    initialized : 1; /* set if we have initialized
the device */
 	unsigned int    on_mainboard : 1;
-	unsigned long   rom_address;
 
 	u8 command;
 

Modified: trunk/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/dbm690t/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/amd/pistachio/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -156,9 +156,7 @@
 					device pci 0.0 on end # HT
0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/amd/pistachio/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 					device pci 0.0 on end # HT
0x7910
 				#	device pci 0.1 off end # CLK
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/arima/hdama/Config.lb
===================================================================
--- trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/arima/hdama/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -177,9 +177,7 @@
 						device pci 0.1 on  end
# USB1
 						device pci 0.2 off end
# USB 2.0
 						device pci 1.0 off end
# LAN
-						chip drivers/pci/onboard
-							device pci 6.0
on end # ATI Rage XL
-						end
+						device pci 6.0 on end #
ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip
drivers/generic/generic
 						#	device pci 5.0
on

Modified: trunk/src/mainboard/arima/hdama/devicetree.cb
===================================================================
--- trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/arima/hdama/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -73,9 +73,7 @@
 						device pci 0.1 on  end
# USB1
 						device pci 0.2 off end
# USB 2.0
 						device pci 1.0 off end
# LAN
-						chip drivers/pci/onboard
-							device pci 6.0
on end # ATI Rage XL
-						end
+						device pci 6.0 on end #
ATI Rage XL
 						## PCI Slot 5 (correct?)
 						#chip
drivers/generic/generic
 						#	device pci 5.0
on

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h
2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,10 +1,6 @@
 #ifndef PCI_REALMODE_H
 #define PCI_REALMODE_H
 
-struct drivers_pci_realmode_config 
-{
-       unsigned long rom_address;
-};
 //struct chip_operations;
 extern struct chip_operations drivers_pci_realmode_ops;
 

Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
===================================================================
--- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
2009-11-06 23:42:26 UTC (rev 4925)
@@ -74,36 +74,6 @@
   emulator to successfully run this bios.
 */
 
-
-
-
-/*
-  Modified to be an universal driver for loading VGA ROMs.
-  Aug 2006, anti.sullin at artecdesign.ee, Artec Design
-  
-  USAGE:
-  	define in your motherboard Config.lb file in device hierarchy 
-  	around the VGA pci device realmode chip and define its rom
address.
-	Rom address is read from Config.lb, this rom is then copied to
0xC000 and then excecuted
-  	
-  		chip drivers/pci/realmode
-				device pci 1.1 on end
# VGA
-				register "rom_address" = "0xfffc0000"
# at the beginning of 256k
-		end
-  	
-  	then, chip enable is called at this list first traversal, and
this sets
-  	up device's init callback. Device init is called during last
list traversal and
-  	so, other hw should be already initialized to run vga bios
successfully.
-*/
-
-
-
-
-
-
-
-
-
 /* Declare a temporary global descriptor table - necessary because the
    Core part of the bios no longer sets up any 16 bit segments */
 __asm__ (
@@ -918,8 +888,6 @@
 
 	// code to make vga init go through the emulator - as of yet
this does not workfor the epia-m
 	dev->on_mainboard=1;
-	dev->rom_address = (void *)cfg->rom_address;
-
 	pci_dev_init(dev);
 
 	// code to make vga init run in real mode - does work but
against the current coreboot philosophy 

Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -135,11 +135,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -37,11 +37,6 @@
       device pci 12.2 on  end		# IDE
       device pci 12.3 on  end		# Audio
       device pci 12.4 on  end		# VGA (onboard)
-      # device pci 12.4 on		# VGA (onboard)
-      #   chip drivers/pci/onboard
-      #     device pci 12.4 on end
-      #   end
-      # end
       device pci 13.0 on end		# USB
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -97,18 +97,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb
===================================================================
--- trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/asus/mew-vm/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -2,18 +2,14 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end # Host bridge
 		device pci 1.0 on # Onboard Video
-			#chip drivers/pci/onboard
 			#	device pci 1.0 on end
-		        #end
 		end
 		chip southbridge/intel/i82801xx # Southbridge
       			register "ide0_enable" = "1"
       			register "ide1_enable" = "1"
 
 			device pci 1e.0 on # PCI Bridge
-				#chip drivers/pci/onboard
 				#	device pci 1.0 on end
-			        #end
 			end
 			device pci 1f.0 on  # ISA/LPC? Bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -207,21 +207,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb
===================================================================
--- trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/broadcom/blast/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -105,21 +105,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
-                                        end
+                                        device pci 4.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 5.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
-
 			end #  device pci 18.0
 
                         device pci 18.0 on end

Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/Config.lb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -102,13 +102,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
===================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -1,13 +1,8 @@
 chip cpu/amd/sc520
 	device pci_domain 0 on 
 		device pci 0.0 on end
-	
-		chip drivers/pci/onboard
-			device pci 12.0 on end # enet
-		end
-		chip drivers/pci/onboard
-			device pci 14.0 on end # 69000
-		end
+		device pci 12.0 on end # enet
+		device pci 14.0 on end # 69000
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c
===================================================================
--- trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c	2009-11-06
23:42:26 UTC (rev 4925)
@@ -16,7 +16,6 @@
 	 * force coreboot to use it.
 	 */
 	dev->on_mainboard = 1;
-	dev->rom_address = 0xc0000;
 
 	/* Now do the usual initialization */
 	pci_dev_init(dev);

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -178,9 +178,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   #
Northbridge
 					device pci 1.0 on
# AGP bridge
-					  chip drivers/pci/onboard
# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -11,9 +11,7 @@
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   #
Northbridge
 					device pci 1.0 on
# AGP bridge
-					  chip drivers/pci/onboard
# Integrated VGA
 						device pci 0.0 on end
-					  end
 					end
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f

Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -195,15 +195,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard
#SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -72,15 +72,6 @@
 					device pci 2.1 on end # USB
 					device pci 2.2 on end # USB
 					device pci 3.0 on end # VGA
-					
-					#bx_a013+ start
-					#chip drivers/pci/onboard
#SATA2
-					#	device pci 5.0 on end
-					#	device pci 5.1 on end
-					#	device pci 5.2 on end
-					#	device pci 5.3 on end
-					#end
-					#bx_a013+ end
 				end
 			end
 			device pci 18.0 on end

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -76,9 +76,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
===================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -7,9 +7,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/ibm/e326/Config.lb
===================================================================
--- trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/ibm/e326/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -125,9 +125,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end #
ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/ibm/e326/devicetree.cb
===================================================================
--- trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/ibm/e326/devicetree.cb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 on end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # ATI Rage XL
-                                                end
+                                               device pci 5.0 on end #
ATI Rage XL
 					end
 					device pci 1.0 on
 						chip superio/nsc/pc87366

Modified: trunk/src/mainboard/intel/d945gclf/Config.lb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -150,9 +150,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/d945gclf/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -28,9 +28,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -127,9 +127,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
===================================================================
--- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -25,9 +25,7 @@
 			device pci 1d.1 off end # USB (not populated)
 			device pci 1d.2 off end # USB (not populated)
 			device pci 1e.0 on # Hub to PCI bridge
-				chip drivers/pci/onboard # VGA ROM
-					device pci 0.0 on end
-				end
+				device pci 0.0 on end
 			end
 			device pci 1f.0 on # LPC bridge
 				chip superio/smsc/lpc47b272

Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -232,9 +232,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip
drivers/pci/onboard
-                                                #        device pci 6.0
on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb
===================================================================
--- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -24,9 +24,6 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                #chip
drivers/pci/onboard
-                                                #        device pci 6.0
on end
-                                                #end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -153,9 +153,7 @@
                 device pci 00.0 on end # host bridge
 		# autodetect 0:1.0 because it might or might not be
there.
 		# device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -9,9 +9,7 @@
         device pci_domain 0 on 
                 device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
-		chip drivers/pci/onboard
-			device pci 02.0 on end # vga controller
-		end
+		device pci 02.0 on end # vga controller
 		device pci 02.1 on end # display controller
 
                 chip southbridge/intel/i82801gx

Modified: trunk/src/mainboard/kontron/kt690/Config.lb
===================================================================
--- trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/kontron/kt690/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
===================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/mitac/6513wu/Config.lb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -80,9 +80,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller
Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb
===================================================================
--- trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/mitac/6513wu/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on                # PCI domain
     device pci 0.0 on end               # Graphics Memory Controller
Hub (GMCH)
-    chip drivers/pci/onboard
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end
     chip southbridge/intel/i82801xx     # Southbridge
       register "pirqa_routing" = "0x03"
       register "pirqb_routing" = "0x05"

Modified: trunk/src/mainboard/msi/ms6178/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms6178/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -75,9 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms6178/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -26,9 +26,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    chip drivers/pci/onboard			# Onboard VGA
-      device pci 1.0 on end
-    end
+    device pci 1.0 on end			# Onboard VGA
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms9185/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -207,29 +207,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard
#SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9185/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -73,29 +73,8 @@
                                         device pci 2.0 on end # USB
0x0223
                                         device pci 2.1 on end # USB
                                         device pci 2.2 on end # USB
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE
(6,,,,),
-                                        chip drivers/pci/onboard
-                                              device pci 3.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed, fake one to get the rom_address
-                                                                    #
if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if
CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                        end
-                                       #bx_a013+ start
-                                       #chip drivers/pci/onboard
#SATA2
-                                       #       device pci 5.0 on end
-                                       #       device pci 5.1 on end
-                                       #       device pci 5.2 on end
-                                       #       device pci 5.3 on end
-                                       #end
-                                       #bx_a013+ end
-
+                                        device pci 3.0 on end # it is
in bcm5785_0 bus
                                 end
-                                        #when
CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
-#                                        chip drivers/pci/onboard
-#                                              device pci 0.0 on end #
fake, will be disabled
-#                                        end
-#                                        chip drivers/pci/onboard
-#                                              device pci 4.0 on end #
it is in bcm5785_0 bus, but the device id can not be changed even unitid
is changed
-#                                        end
-
                        end #  device pci 18.0
                        device pci 18.1 on end
                        device pci 18.2 on end

Modified: trunk/src/mainboard/msi/ms9282/Config.lb
===================================================================
--- trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/msi/ms9282/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -278,27 +278,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0
on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip
drivers/pci/onboard
-                                                               device
pci 4.0 on end  #pci_E lan1
-                                                               device
pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0
on end  #pci_E lan1
+                                                       device pci 4.1
on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end #
PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0
on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0
0x375
                                        device pci f.0 on end   #PCI E
0x377  pci_E slot

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
===================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -137,27 +137,21 @@
                                        device pci 5.1 on  end # SATA 1
                                        device pci 5.2 on  end # SATA 2
                                        device pci 6.0 on  #P2P
-                                               chip drivers/pci/onboard
-                                                       device pci 4.0
on end
-                                               end
+                                               device pci 4.0 on end
                                        end # P2P
                                        device pci 7.0 on end # reserve
                                        device pci 8.0 on end # MAC0
                                        device pci 9.0 on end # MAC1
                                        device pci a.0 on
                                                device pci 0.0 on
-                                                       chip
drivers/pci/onboard
-                                                               device
pci 4.0 on end  #pci_E lan1
-                                                               device
pci 4.1 on end  #pci_E lan2
-                                                       end
+                                                       device pci 4.0
on end  #pci_E lan1
+                                                       device pci 4.1
on end  #pci_E lan2
                                                end
                                        end # 0x376
                                                device pci b.0 on  end #
PCI E 0x374
                                        device pci c.0 on  end
                                        device pci d.0 on   #SAS
-                                               chip drivers/pci/onboard
-                                                       device pci 0.0
on end
-                                               end
+                                               device pci 0.0 on end
                                        end # PCI E 1 0x378
                                        device pci e.0 on end # PCI E 0
0x375
                                        device pci f.0 on end   #PCI E
0x377  pci_E slot

Modified: trunk/src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -75,11 +75,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb
===================================================================
--- trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/nec/powermate2000/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -6,11 +6,7 @@
   end
   device pci_domain 0 on
     device pci 0.0 on end			# Host bridge
-    device pci 1.0 off				# Onboard video
-      # chip drivers/pci/onboard
-      #   device pci 1.0 on end
-      # end
-    end
+    device pci 1.0 off end			# Onboard video
     chip southbridge/intel/i82801xx		# Southbridge
       register "ide0_enable" = "1"
       register "ide1_enable" = "1"

Modified: trunk/src/mainboard/newisys/khepri/Config.lb
===================================================================
--- trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/newisys/khepri/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -98,8 +98,6 @@
 
 config chip.h
 
-# FIXME: ROM for onboard VGA
-
 chip northbridge/amd/amdk8/root_complex
 	device apic_cluster 0 on
 		chip cpu/amd/socket_940

Modified: trunk/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/rca/rm4100/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb
===================================================================
--- trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/rca/rm4100/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -210,8 +210,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" =
"0xfff80000" # 64k
-#					register "raid_rom_address" =
"0xfff90000"
 					register "mac_eeprom_smbus" =
"3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" =
"0x51"
 				end
@@ -243,7 +241,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" =
"0xfff80000" # 64k
                                         register "mac_eeprom_smbus" =
"3"
                                         register "mac_eeprom_addr" =
"0x51"
                         	end

Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb
===================================================================
--- trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/sunw/ultra40/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -106,8 +106,6 @@
         	                        register "ide1_enable" = "1"
                 	                register "sata0_enable" = "1"
                         	        register "sata1_enable" = "1"
-#					register "nic_rom_address" =
"0xfff80000" # 64k
-#					register "raid_rom_address" =
"0xfff90000"
 					register "mac_eeprom_smbus" =
"3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" =
"0x51"
 				end
@@ -139,7 +137,6 @@
                                 	device pci c.0 off end # PCI E 2
                                 	device pci d.0 off end # PCI E 1
                                 	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" =
"0xfff80000" # 64k
                                         register "mac_eeprom_smbus" =
"3"
                                         register "mac_eeprom_addr" =
"0x51"
                         	end

Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -254,9 +254,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -92,9 +92,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -276,9 +276,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -280,9 +280,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -114,9 +114,7 @@
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
                 			device pci 6.0 on  # PCI
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
         	        		device pci 6.1 on end # AZA
 	                		device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/technexion/tim5690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim5690/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -155,9 +155,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- trunk/src/mainboard/technexion/tim8690/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technexion/tim8690/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -20,9 +20,7 @@
 				chip southbridge/amd/rs690
 					device pci 0.0 on end # HT
0x7910
 					device pci 1.0 on  # Internal
Graphics P2P bridge 0x7912
-						chip drivers/pci/onboard
-							device pci 5.0
on end	# Internal Graphics 0x791F
-						end
+						device pci 5.0 on end
# Internal Graphics 0x791F
 					end
 					device pci 2.0 on end # PCIE P2P
bridge (external graphics) 0x7913
 					device pci 3.0 off end # PCIE
P2P bridge	0x791b

Modified: trunk/src/mainboard/technologic/ts5300/Config.lb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -104,12 +104,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb
===================================================================
--- trunk/src/mainboard/technologic/ts5300/devicetree.cb
2009-11-06 17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/technologic/ts5300/devicetree.cb
2009-11-06 23:42:26 UTC (rev 4925)
@@ -2,12 +2,6 @@
 	device pci_domain 0 on 
 		device pci 0.0 on end
 	
-#		chip drivers/pci/onboard
-#			device pci 12.0 on end # enet
-#		end
-#		chip drivers/pci/onboard
-#			device pci 14.0 on end # 69000
-#		end
 #		register "com1" = "{1}"
 #		register "com1" = "{1, 0, 0x3f8, 4}"
 	end

Modified: trunk/src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -75,9 +75,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb
===================================================================
--- trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/thomson/ip1000/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -1,9 +1,7 @@
 chip northbridge/intel/i82830		# Northbridge
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
-    chip drivers/pci/onboard		# Onboard VGA
-      device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    end
+    device pci 2.0 on end		# VGA (Intel 82830 CGC)
     chip southbridge/intel/i82801xx	# Southbridge
       register "pirqa_routing" = "0x05"
       register "pirqb_routing" = "0x06"

Modified: trunk/src/mainboard/tyan/s2735/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2735/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -100,10 +100,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end #
intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel
lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -117,12 +115,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel
lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2735/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -6,10 +6,8 @@
         		chip southbridge/intel/i82870
         	        	device pci 1c.0 on end
 		                device pci 1d.0 on 
-					chip drivers/pci/onboard
-                                        	device pci 1.0 on end #
intel lan
-                                                device pci 1.1 on end
-                                        end
+                                     	 device pci 1.0 on end # intel
lan
+                                        device pci 1.1 on end
 				end
         	                device pci 1e.0 on end
         	                device pci 1f.0 on end
@@ -23,12 +21,8 @@
         	        device pci 1d.3 on end
 		        device pci 1d.7 on end
 		        device pci 1e.0 on 
-                        	chip drivers/pci/onboard
-                                	device pci 1.0 on end # intel
lan 10/100
-                                end
-                                chip drivers/pci/onboard
-                                        device pci 2.0 on end # ati 
-                                end
+                             	device pci 1.0 on end # intel lan 10/100
+                                device pci 2.0 on end # ati
 			end
 		        device pci 1f.0 on
 				chip superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2850/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -119,9 +119,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0
on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2850/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -17,9 +17,7 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-						chip drivers/pci/onboard
-                                                        device pci b.0
on end
-                                                end
+                                                device pci b.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2875/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -123,9 +123,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2875/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -21,9 +21,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2880/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -113,10 +113,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #broadcom
-							device pci 9.1
on end 
-                                                end
+                                                device pci 9.0 on end
#broadcom
+						device pci 9.1 on end
 #                                                chip
drivers/lsi/53c1030
 #                                                        device pci a.0
on end
 #                                                        device pci a.1
on end
@@ -135,12 +133,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #some sata
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end #adti
-                                                end
+                                                device pci 5.0 on end
#some sata
+                                                device pci 6.0 on end
#adti
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2880/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -11,10 +11,8 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #broadcom
-							device pci 9.1
on end 
-                                                end
+                                                device pci 9.0 on end
#broadcom
+						device pci 9.1 on end
 #                                                chip
drivers/lsi/53c1030
 #                                                        device pci a.0
on end
 #                                                        device pci a.1
on end
@@ -33,12 +31,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #some sata
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end #adti
-                                                end
+                                                device pci 5.0 on end
#some sata
+                                                device pci 6.0 on end
#adti
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2881/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -115,14 +115,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # Broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci a.0
on end # Adaptic
-                                                        device pci a.1
on end
-                                                end
+                                                device pci 9.0 on end #
Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end #
Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -136,12 +132,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # SiI
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 5.0 on end #
SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2881/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -13,14 +13,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # Broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci a.0
on end # Adaptic
-                                                        device pci a.1
on end
-                                                end
+                                                device pci 9.0 on end #
Broadcom 5704
+                                                device pci 9.1 on end
+                                                device pci a.0 on end #
Adaptic
+                                                device pci a.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -34,12 +30,8 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end # SiI
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 5.0 on end #
SiI
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2882/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -114,14 +114,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard 
-                                                        device pci 6.0
on end # adaptec
-                                                        device pci 6.1
on end
-                                                end 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 6.0 on end #
adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end #
broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -135,16 +131,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard  
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard 
-                                                        device pci 8.0
on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end
#intel 10/100
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2882/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -12,14 +12,10 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on
-                                                chip
drivers/pci/onboard 
-                                                        device pci 6.0
on end # adaptec
-                                                        device pci 6.1
on end
-                                                end 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5704
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 6.0 on end #
adaptec
+                                                device pci 6.1 on end
+                                                device pci 9.0 on end #
broadcom 5704
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -33,16 +29,11 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard  
-                                                        device pci 5.0
on end
-                                                end
+                                                device pci 5.0 on end
                                         #       chip drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard 
-                                                        device pci 8.0
on end #intel 10/100
-                                                end
+                                                device pci 6.0 on end
+                                        #       end
+                                                device pci 8.0 on end
#intel 10/100
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s2885/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,9 +121,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end #
broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -137,9 +135,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci b.0
on end # SiI 3114
-                                                end
+                                                device pci b.0 on end #
SiI 3114
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2885/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -19,9 +19,7 @@
 				chip southbridge/amd/amd8131
 					# the on/off keyword is
mandatory
 					device pci 0.0 on 
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end # broadcom 5703
-                                                end
+                                                device pci 9.0 on end #
broadcom 5703
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,9 +33,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci b.0
on end # SiI 3114
-                                                end
+                                                device pci b.0 on end #
SiI 3114
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2891/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -104,9 +104,7 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 7.0
on end
-						end
+						device pci 7.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -127,10 +125,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0
on end
-							device pci 9.1
on end
-						end
+						device pci 9.0 on end
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2892/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -105,12 +105,9 @@
 					device pci 8.0 on end # SATA 0
 					device pci 9.0 on  # PCI
 					#	chip drivers/ati/ragexl
-						chip drivers/pci/onboard
-							device pci 6.0
on end
-						end
-						chip drivers/pci/onboard
-							device pci 8.0
on end
-						end
+						device pci 6.0 on end
+					#	end
+						device pci 8.0 on end
 					end
 					device pci a.0 off end # NIC
 					device pci b.0 off end # PCI E 3
@@ -131,10 +128,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 9.0
on end # broadcom 5704
-							device pci 9.1
on end
-						end
+						device pci 9.0 on end #
broadcom 5704
+						device pci 9.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2895/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -111,10 +111,8 @@
 					device pci 0.0 on end
 					device pci 0.1 on end
 					device pci 1.0 on
-						chip drivers/pci/onboard
-							device pci 6.0
on end # lsi scsi
-							device pci 6.1
on end
-						end
+						device pci 6.0 on end #
lsi scsi
+						device pci 6.1 on end
 					end
 					device pci 1.1 on end
 				end

Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -279,9 +279,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0
on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -112,9 +112,7 @@
 					device pci 5.1 on end # SATA 1
 					device pci 5.2 on end # SATA 2
 					device pci 6.0 on
-						chip drivers/pci/onboard
-							device pci 4.0
on end
-						end
+						device pci 4.0 on end
 					end # PCI
 					device pci 6.1 off end # AZA
 					device pci 8.0 on end # NIC

Modified: trunk/src/mainboard/tyan/s4880/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s4880/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -116,10 +116,8 @@
 #                                                        device pci 4.1
on end
 #                                                        register
"fw_address" = "0xfff8c000"
 #                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -133,9 +131,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4880/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -19,10 +19,8 @@
 #                                                        device pci 4.1
on end
 #                                                        register
"fw_address" = "0xfff8c000"
 #                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end
-                                                        device pci 9.1
on end
-                                                end
+                                                device pci 9.0 on end
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -36,9 +34,7 @@
 						device pci 0.1 on end
 						device pci 0.2 off end
 						device pci 1.0 off end
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
+                                                device pci 6.0 on end
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/Config.lb
===================================================================
--- trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/tyan/s4882/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -114,10 +114,8 @@
 #							device pci 4.1
on end
 #							register
"fw_address" = "0xfff8c000"
 #						end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #Broadcom
-                                                        device pci 9.1
on end
-                                                end 
+                                                device pci 9.0 on end
#Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -132,12 +130,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end
#SiI
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb
===================================================================
--- trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/tyan/s4882/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -17,10 +17,8 @@
 #							device pci 4.1
on end
 #							register
"fw_address" = "0xfff8c000"
 #						end
-                                                chip
drivers/pci/onboard
-                                                        device pci 9.0
on end #Broadcom
-                                                        device pci 9.1
on end
-                                                end 
+                                                device pci 9.0 on end
#Broadcom
+                                                device pci 9.1 on end
 					end
 					device pci 0.1 on end
 					device pci 1.0 on end
@@ -35,12 +33,9 @@
 						device pci 0.2 off end
 						device pci 1.0 off end
                                                 #chip
drivers/ati/ragexl
-                                                chip
drivers/pci/onboard
-                                                        device pci 6.0
on end
-                                                end
-                                                chip
drivers/pci/onboard
-                                                        device pci 5.0
on end #SiI
-                                                end
+                                                device pci 6.0 on end
+                                                #end
+                                                device pci 5.0 on end
#SiI
 					end
 					device pci 1.0 on
 						chip
superio/winbond/w83627hf

Modified: trunk/src/mainboard/via/epia/Config.lb
===================================================================
--- trunk/src/mainboard/via/epia/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/epia/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -96,10 +96,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/epia/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/epia/devicetree.cb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -2,10 +2,7 @@
 	device pci_domain 0 on
     		device pci 0.0 on end			# Northbridge
 #		device pci 0.1 on			# AGP bridge
-		#	chip drivers/pci/onboard	# Integrated VGA
-		#		device pci 0.0 on end
-		#		register "rom_adress" = "0xfff80000"
-		#	end
+		#	device pci 0.0 on end		# Integrated VGA
 #		end
 		chip southbridge/via/vt8231
 			register "enable_native_ide" = "0"

Modified: trunk/src/mainboard/via/vt8454c/Config.lb
===================================================================
--- trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/mainboard/via/vt8454c/Config.lb	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,9 +121,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb
===================================================================
--- trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/mainboard/via/vt8454c/devicetree.cb	2009-11-06
23:42:26 UTC (rev 4925)
@@ -12,9 +12,7 @@
 		device pci 0.4 on end # Power Management
 		device pci 0.7 on end # V-Link Controller
 		device pci 1.0 on     # PCI Bridge
-			chip drivers/pci/onboard
-				device pci 0.0 on end
-			end # Onboard Video
+			device pci 0.0 on end # Onboard Video
 		end # PCI Bridge
 		device pci f.0 on end # IDE/SATA
 		#device pci f.1 on end # IDE

Modified: trunk/src/northbridge/via/cn400/vga.c
===================================================================
--- trunk/src/northbridge/via/cn400/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cn400/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -121,15 +121,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cn700/vga.c
===================================================================
--- trunk/src/northbridge/via/cn700/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cn700/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -101,15 +101,8 @@
 	memset(0xf0000, 0, 0x10000);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static const struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/cx700/cx700_vga.c
===================================================================
--- trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/cx700/cx700_vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -97,15 +97,8 @@
 	outb(reg8, SR_DATA);
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = 0xfff80000;
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/northbridge/via/vt8623/northbridge.c
===================================================================
--- trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06
17:32:32 UTC (rev 4924)
+++ trunk/src/northbridge/via/vt8623/northbridge.c	2009-11-06
23:42:26 UTC (rev 4925)
@@ -124,9 +124,6 @@
 	
 #if 0
 	/* code to make vga init go through the emulator - as of yet
this does not workfor the epia-m */
-	dev->on_mainboard=1;
-	dev->rom_address = (void *)0xfffc0000;
-
 	pci_dev_init(dev);
 	
 	call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
@@ -167,17 +164,8 @@
 #endif
 }
 
-static void vga_read_resources(device_t dev)
-{
-
-	dev->rom_address = (void *)0xfffc0000;
-	dev->on_mainboard=1;
-	pci_dev_read_resources(dev);
-
-}
-
 static struct device_operations vga_operations = {
-	.read_resources   = vga_read_resources,
+	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = vga_init,

Modified: trunk/src/northbridge/via/vx800/vga.c
===================================================================
--- trunk/src/northbridge/via/vx800/vga.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/northbridge/via/vx800/vga.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -126,15 +126,8 @@
 
 }
 
-static void vga_read_resources(device_t dev)
-{
-	dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
-	dev->on_mainboard = 1;
-	pci_dev_read_resources(dev);
-}
-
 static struct device_operations vga_operations = {
-	.read_resources = vga_read_resources,
+	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = vga_init,

Modified: trunk/src/southbridge/nvidia/ck804/chip.h
===================================================================
--- trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/chip.h	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -7,8 +7,6 @@
 	unsigned int ide1_enable : 1;
 	unsigned int sata0_enable : 1;
 	unsigned int sata1_enable : 1;
-	unsigned long nic_rom_address;
-	unsigned long raid_rom_address;
 	unsigned int mac_eeprom_smbus;
 	unsigned int mac_eeprom_addr;
 };

Modified: trunk/src/southbridge/nvidia/ck804/ck804.c
===================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 17:32:32 UTC
(rev 4924)
+++ trunk/src/southbridge/nvidia/ck804/ck804.c	2009-11-06 23:42:26 UTC
(rev 4925)
@@ -77,12 +77,10 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
 		devfn -= (9 << 3);
 		index = 10;
-		dev->rom_address = conf->nic_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
 		devfn -= (3 << 3);
@@ -95,7 +93,6 @@
 	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
 		devfn -= (5 << 3);
 		index = 14;
-		dev->rom_address = conf->raid_rom_address;
 		break;
 	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
 		devfn -= (6 << 3);


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From librali1977 at gmail.com  Mon Nov  9 12:19:28 2009
From: librali1977 at gmail.com (Libra Li)
Date: Mon, 9 Nov 2009 19:19:28 +0800
Subject: [coreboot]  [PATCH] The LED post code for Technexion TIM-5690.
Message-ID: <df21912a0911090319n38fded97qaa24ecedd620635f@mail.gmail.com>

Hi,

    These are post codes for TIM-5690 LED debug message.
    It's easy show message.
    Thanks.

    Signed-off-by: Libra Li <libra.li at technexion.com>



Index: src/mainboard/technexion/tim5690/Makefile.inc
===================================================================
--- src/mainboard/technexion/tim5690/Makefile.inc    (revision 4927)
+++ src/mainboard/technexion/tim5690/Makefile.inc    (working copy)
@@ -29,6 +29,9 @@
 obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
 obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o

+# This is debug message for products of Technexion.
+obj-y += tn_post_code.o
+
 # This is part of the conversion to init-obj and away from included code.

 initobj-y += crt0.o
Index: src/mainboard/technexion/tim5690/cache_as_ram_auto.c
===================================================================
--- src/mainboard/technexion/tim5690/cache_as_ram_auto.c    (revision 4927)
+++ src/mainboard/technexion/tim5690/cache_as_ram_auto.c    (working copy)
@@ -100,6 +100,10 @@

 #include "cpu/amd/model_fxx/fidvid.c"

+#define TECHNEXION_EARLY_SETUP
+#include "tn_post_code.c"
+
+
 #if CONFIG_USE_FALLBACK_IMAGE == 1

 #include "northbridge/amd/amdk8/early_ht.c"
@@ -161,6 +165,8 @@
     struct cpuid_result cpuid1;
     struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);

+    technexion_post_code_init();
+    technexion_post_code(LED_MESSAGE_START);

     if (bist == 0) {
         bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -233,7 +239,11 @@
     /* It's the time to set ctrl now; */
     printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr:
%2x\n",
              sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
     fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+    technexion_post_code(LED_MESSAGE_RAM);
+
     sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

     rs690_before_pci_init();
Index: src/mainboard/technexion/tim5690/tn_post_code.c
===================================================================
--- src/mainboard/technexion/tim5690/tn_post_code.c    (revision 0)
+++ src/mainboard/technexion/tim5690/tn_post_code.c    (revision 0)
@@ -0,0 +1,207 @@
+
+#ifdef TECHNEXION_EARLY_SETUP
+
+#include <arch/cpu.h>
+#include "southbridge/amd/sb600/sb600.h"
+
+#else
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#endif
+
+#include "tn_post_code.h"
+
+
+#ifdef TECHNEXION_EARLY_SETUP
+
+// TechNexion's Post Code Initially.
+void technexion_post_code_init(void)
+{
+   uint8_t reg8_data;
+   device_t dev=0;
+
+   // SMBus Module and ACPI Block (Device 20, Function 0)
+   dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB600_SM), 0);
+
+   // LED[bit0]:GPIO0
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pmio_read(0x60);
+   reg8_data |= (1<<7);  // 1: GPIO if not used by SATA
+   pmio_write(0x60, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0x80);
+   reg8_data = ((reg8_data | (1<<0)) & ~(1<<4));
+   pci_write_config8(dev, 0x80, reg8_data);
+
+   // LED[bit1]:GPIO1
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pci_read_config8(dev, 0x80);
+   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   pci_write_config8(dev, 0x80, reg8_data);
+
+   // LED[bit2]:GPIO4
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pmio_read(0x5e);
+   reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA
+   pmio_write(0x5e, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa8);
+   reg8_data |= (1<<0);
+   pci_write_config8(dev, 0xa8, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa9);
+   reg8_data &= ~(1<<0);
+   pci_write_config8(dev, 0xa9, reg8_data);
+
+   // LED[bit3]:GPIO6
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pmio_read(0x60);
+   reg8_data |= (1<<7); // 1: GPIO if not used by SATA
+   pmio_write(0x60, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa8);
+   reg8_data |= (1<<2);
+   pci_write_config8(dev, 0xa8, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa9);
+   reg8_data &= ~(1<<2);
+   pci_write_config8(dev, 0xa9, reg8_data);
+   // LED[bit4]:GPIO7
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pci_read_config8(dev, 0xa8);
+   reg8_data |= (1<<3);
+   pci_write_config8(dev, 0xa8, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa9);
+   reg8_data &= ~(1<<3);
+   pci_write_config8(dev, 0xa9, reg8_data);
+
+   // LED[bit5]:GPIO8
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pci_read_config8(dev, 0xa8);
+   reg8_data |= (1<<4);
+   pci_write_config8(dev, 0xa8, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0xa9);
+   reg8_data &= ~(1<<4);
+   pci_write_config8(dev, 0xa9, reg8_data);
+
+   // LED[bit6]:GPIO10
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pci_read_config8(dev, 0xab);
+   reg8_data = ((reg8_data | (1<<0)) & ~(1<<1));
+   pci_write_config8(dev, 0xab, reg8_data);
+
+   // LED[bit7]:GPIO66
+   // This is reference SB600 RRG 4.1.1 GPIO
+   reg8_data = pmio_read(0x68);
+   reg8_data &= ~(1<<5); // 0: GPIO
+   pmio_write(0x68, reg8_data);
+
+   reg8_data = pci_read_config8(dev, 0x7e);
+   reg8_data = ((reg8_data | (1<<1)) & ~(1<<5));
+   pci_write_config8(dev, 0x7e, reg8_data);
+
+}
+
+#endif
+
+/* TechNexion's Post Code.
+ */
+void technexion_post_code(uint8_t udata8)
+{
+   uint8_t u8_data;
+   device_t dev=0;
+
+   // SMBus Module and ACPI Block (Device 20, Function 0)
+#ifdef TECHNEXION_EARLY_SETUP
+   dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB600_SM), 0);
+#else
+   dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0);
+#endif
+
+   udata8 = ~(udata8);
+
+   // LED[bit0]:GPIO0
+   u8_data = pci_read_config8(dev, 0x80);
+   if (udata8 & 0x1) {
+      u8_data |= (1<<0);
+   }
+   else {
+      u8_data &= ~(1<<0);
+   }
+   pci_write_config8(dev, 0x80, u8_data);
+
+   // LED[bit1]:GPIO1
+   u8_data = pci_read_config8(dev, 0x80);
+   if (udata8 & 0x2) {
+      u8_data |= (1<<1);
+   }
+   else {
+      u8_data &= ~(1<<1);
+   }
+   pci_write_config8(dev, 0x80, u8_data);
+
+   // LED[bit2]:GPIO4
+   u8_data = pci_read_config8(dev, 0xa8);
+   if (udata8 & 0x4) {
+      u8_data |= (1<<0);
+   }
+   else {
+      u8_data &= ~(1<<0);
+   }
+   pci_write_config8(dev, 0xa8, u8_data);
+
+   // LED[bit3]:GPIO6
+   u8_data = pci_read_config8(dev, 0xa8);
+   if (udata8 & 0x8) {
+      u8_data |= (1<<2);
+   }
+   else {
+      u8_data &= ~(1<<2);
+   }
+   pci_write_config8(dev, 0xa8, u8_data);
+
+   // LED[bit4]:GPIO7
+   u8_data = pci_read_config8(dev, 0xa8);
+   if (udata8 & 0x10) {
+      u8_data |= (1<<3);
+   }
+   else {
+      u8_data &= ~(1<<3);
+   }
+   pci_write_config8(dev, 0xa8, u8_data);
+
+   // LED[bit5]:GPIO8
+   u8_data = pci_read_config8(dev, 0xa8);
+   if (udata8 & 0x20) {
+      u8_data |= (1<<4);
+   }
+   else {
+      u8_data &= ~(1<<4);
+   }
+   pci_write_config8(dev, 0xa8, u8_data);
+
+   // LED[bit6]:GPIO10
+   u8_data = pci_read_config8(dev, 0xab);
+   if (udata8 & 0x40) {
+      u8_data |= (1<<0);
+   }
+   else {
+      u8_data &= ~(1<<0);
+   }
+   pci_write_config8(dev, 0xab, u8_data);
+
+   // LED[bit7]:GPIO66
+   u8_data = pci_read_config8(dev, 0x7e);
+   if (udata8 & 0x80) {
+      u8_data |= (1<<1);
+   }
+   else {
+      u8_data &= ~(1<<1);
+   }
+   pci_write_config8(dev, 0x7e, u8_data);
+
+}
Index: src/mainboard/technexion/tim5690/tn_post_code.h
===================================================================
--- src/mainboard/technexion/tim5690/tn_post_code.h    (revision 0)
+++ src/mainboard/technexion/tim5690/tn_post_code.h    (revision 0)
@@ -0,0 +1,15 @@
+
+
+#define LED_MESSAGE_START       0xFF
+#define LED_MESSAGE_FINISH      0x99
+#define LED_MESSAGE_RAM         0x01
+
+
+#ifdef TECHNEXION_EARLY_SETUP
+
+// TechNexion's Post Code Initially.
+void technexion_post_code_init(void);
+
+#endif
+
+void technexion_post_code(uint8_t udata8);
Index: src/mainboard/technexion/tim5690/mainboard.c
===================================================================
--- src/mainboard/technexion/tim5690/mainboard.c    (revision 4927)
+++ src/mainboard/technexion/tim5690/mainboard.c    (working copy)
@@ -27,6 +27,7 @@
 #include <device/pci_def.h>
 #include <../southbridge/amd/sb600/sb600.h>
 #include "chip.h"
+#include "tn_post_code.h"

 #define ADT7461_ADDRESS 0x4C
 #define ARA_ADDRESS     0x0C /* Alert Response Address */
@@ -44,12 +45,18 @@
 #define ADT7461_write_byte(address, val) \
     do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)

+/* previous
+ */
+void tim5690_enable(device_t dev);
+int add_mainboard_resources(struct lb_memory *mem);
+
+
 uint64_t uma_memory_base, uma_memory_size;


 /* set thermal config
  */
-static void set_thermal_config()
+static void set_thermal_config(void)
 {
     u8 byte;
     u16 word;
@@ -176,6 +183,7 @@
     lb_add_memory_range(mem, LB_MEM_RESERVED,
         uma_memory_base, uma_memory_size);
 #endif
+    technexion_post_code(LED_MESSAGE_FINISH);
 }

 struct chip_operations mainboard_ops = {
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From svn at coreboot.org  Mon Nov  9 12:53:42 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Mon,  9 Nov 2009 11:53:42 +0000
Subject: [coreboot] [commit] r4928 - trunk/src/mainboard/technexion/tim5690
Message-ID: <mailman.4023.1355071653.16123.coreboot@coreboot.org>

Author: stepan
Date: 2009-11-09 11:53:41 +0000 (Mon, 09 Nov 2009)
New Revision: 4928

Added:
   trunk/src/mainboard/technexion/tim5690/tn_post_code.c
   trunk/src/mainboard/technexion/tim5690/tn_post_code.h
Modified:
   trunk/src/mainboard/technexion/tim5690/Config.lb
   trunk/src/mainboard/technexion/tim5690/Makefile.inc
   trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
   trunk/src/mainboard/technexion/tim5690/mainboard.c
Log:
These are post codes for TIM-5690 LED debug message.

Signed-off-by: Libra Li <libra.li at technexion.com>
Added object reference to Config.lb, too and
Acked-by: Stefan Reinauer <stepan at coresystems.de>




Modified: trunk/src/mainboard/technexion/tim5690/Config.lb
===================================================================
--- trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-07 00:45:17 UTC (rev 4927)
+++ trunk/src/mainboard/technexion/tim5690/Config.lb	2009-11-09 11:53:41 UTC (rev 4928)
@@ -30,6 +30,7 @@
 ##
 
 driver mainboard.o
+obj