[coreboot] [PATCH]: Updated: Add the superio SMSC sch4304 support.
Bao, Zheng
Zheng.Bao at amd.com
Mon Nov 30 04:01:00 CET 2009
Add support of superio sch4304.
The datasheet of the sch4304 doesnt seems to be public. So the patch
should not be based on the information got from datasheet. Here is
the result of superiotool.
bash# ./superiotool
superiotool r4931
Found SMSC SCH4307 (id=0x90, rev=0x03) at 0x2e
So we can know the Device id is 0x90. The sub-devices which I enabled
are
the ones whose LDNs don't change at all. So I believe it doesn't hurt
anyone.
Maybe I am too sensitive, but I am not sure if the NDA is a problem
here.
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Index: src/superio/smsc/smscsuperio/superio.c
===================================================================
--- src/superio/smsc/smscsuperio/superio.c (revision 4967)
+++ src/superio/smsc/smscsuperio/superio.c (working copy)
@@ -61,6 +61,7 @@
#define SCH3112 0x7c
#define SCH5307 0x81 /* Rebranded LPC47B397(?) */
#define SCH5027D 0x89
+#define SCH4304 0x90 /* SCH4304, SCH4307 */
/* Register defines */
#define DEVICE_ID_REG 0x20 /* Device ID register */
@@ -137,6 +138,7 @@
{SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10,
-1, -1}},
{SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10,
-1, -1}},
{SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10,
-1, 11}},
+ {SCH4304, {0,-1, 4, -1, -1, 7, -1, -1, -1, -1, -1, -1, -1,
-1, -1}},
};
/**
-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
Sent: Thursday, November 26, 2009 4:48 PM
To: coreboot
Subject: Re: [coreboot] [PATCH]: Add superio SMSC sch4304 support.
The datasheet is not public now, isn't it?
Does coreboot has the NDA or something else to release sch4304?
Zheng
-----Original Message-----
From: Uwe Hermann [mailto:uwe at hermann-uwe.de]
Sent: Thursday, November 26, 2009 4:16 PM
To: Bao, Zheng
Cc: coreboot
Subject: Re: [coreboot] [PATCH]: Add superio SMSC sch4304 support.
Hi,
On Thu, Nov 26, 2009 at 10:11:43AM +0800, Bao, Zheng wrote:
> Does anyone review it before it is drowned?
I can't find the datasheet right now, but if the ID is 0x90 and
the numbers you added in that table are the Super I/O LDNs, then
this is
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
The Super I/O only has FDC PP SP1 SP2 KBC XBUS RT as LDNs, correct?
> // Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT
ACPI SMB
[...]
> {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10,
-1, -1}},
> {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10,
-1, -1}},
> {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10,
-1, 11}},
> + {SCH4304, {0, 3, 4, 5, -1, 7, -1, 11, -1, -1, -1, -1, 10,
-1, -1}},
Uwe.
--
http://www.hermann-uwe.de | http://www.randomprojects.org
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
A non-text attachment was scrubbed...
Name: winbond_w25x32_w24x64.patch
Type: application/octet-stream
Size: 1237 bytes
Desc: winbond_w25x32_w24x64.patch
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20091130/3c784944/attachment.obj>
More information about the coreboot
mailing list