From info at coresystems.de  Thu Oct  1 00:01:34 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 00:01:34 +0200
Subject: [coreboot] build service results for r4697
Message-ID: <E1Mt7Es-0004x2-0j@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 4697 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix payload loading in various corner cases when working
with the bounce buffer.
In particular, the not-so-rare configuration of AMD boards with RAMBASE at
2MB shouldn't crash anymore for payloads that take > 1MB in total

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4697&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4697&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4697&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 00:08:13 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 00:08:13 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
Message-ID: <4AC3D6CD.7000403@gmx.net>

On 30.09.2009 23:08, Stefan Reinauer wrote:
> On Sep 30, 2009, at 22:56, Peter Stuge <peter at stuge.se> wrote:
>> Patrick Georgi wrote:
>>> attached patch removes:
>>> - CONFIG_CBFS
>>> - stream boot code
>>
>> Wasn't this used for accessing large flash on m57sli?
>
> Yes.
>
> Anyone with such a setup willing to fix CBFS for that?

I don't have such a setup, but I remember the discussion about
supporting this for LAR in v3 and back then it was the consensus that
such boards would simply not be ported to v3. Given that v2 now has
CBFS, we need to either abandon large flash on M57SLI and similar boards
or fix CBFS somehow.

The horrible way out is to use accessor functions for every flash access
made by CBFS code. It also means you get to write your own streaming
version of memcmp, strstr, strlen etc.
The easy way out is to simply copy all of flash to RAM, then walk the
copy in RAM. It's a bit inefficient because you have to copy the whole
flash chip to RAM, but the code stays readable. Of course RAMinit and
bootblock have to be in the always-mapped region of the flash chip.


>> And does it have anything to do with the serial transfer stuff?
>> (Xmodem)
>
> Not possible anymore with CBFS.. Maybe we should make a minipayload
> for the functionality?

Interfacing the minipayload is probably going to be more pain than
simply linking in the xmodem code and calling it if all other options fail.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Thu Oct  1 00:32:49 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 15:32:49 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3D6CD.7000403@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
Message-ID: <13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>

can anyone even buy an m57sli any more? Was it an unfortunate mistake
-- never repeated -- that FLASH was not directly accessible? If the
m57sli is an exception and we'll never see this problem again, I say
we drop it. Copying all of flash into ram sounds bad. If we have to
cope with this problem in future, maybe we're stuck with accessor
functions.

But FLASH is so slow I doubt that the cost of an accessor function is
going to kill us. Function calls run in nanoseconds, and if SPI really
is only 40 MB/sec., then that's 25 ns/byte.

ron



From peter at stuge.se  Thu Oct  1 00:43:33 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 00:43:33 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
Message-ID: <20090930224333.14184.qmail@stuge.se>

ron minnich wrote:
> can anyone even buy an m57sli any more?

No, they are out of production and out of stock really everywhere.


> Was it an unfortunate mistake -- never repeated -- that FLASH was
> not directly accessible?

In the long term (a few years) the problem will go away as SPI
masters move into every chipset, but as long as boards are using
extra components between the CPU and the flash chip, there can be
issues like this.


> If the m57sli is an exception and we'll never see this problem
> again, I say we drop it. Copying all of flash into ram sounds bad.

It would be unfortunate to drop support for one of the most hack
friendly boards that we've seen in a while.


> But FLASH is so slow I doubt that the cost of an accessor function
> is going to kill us. Function calls run in nanoseconds, and if SPI
> really is only 40 MB/sec., then that's 25 ns/byte.

40 Mbyte/s seems way optimistic to me. In the ideal case it's
possible to stream all of the data out of the chip without overhead,
and even then it's CLK/8 Mbyte/s. I think the fastest CLK I've seen
recently is 90 MHz but the superio SPI masters only run at 16 MHz.
(=2Mbyte/s assuming no overhead, which is far from the norm, it's
common to have several bytes overhead for each 256 bytes of data)

Chipsets could run faster, but not all flash chips can run super fast
either. 25-33 somewhere would be the safe number. Max CLK seems to
increase with size and each flash chip product generation though.


//Peter



From rminnich at gmail.com  Thu Oct  1 00:46:58 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 15:46:58 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930224333.14184.qmail@stuge.se>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
Message-ID: <13426df10909301546mb782b25ud7a4fbc36aa33d57@mail.gmail.com>

On Wed, Sep 30, 2009 at 3:43 PM, Peter Stuge <peter at stuge.se> wrote:

> 40 Mbyte/s seems way optimistic to me

Yeah, I was going worst-case scenario (i.e. SPI is super-fast) and
even in that case
accessor functions would not hurt much if at all.

So if we absolutely *have* to do some sort of function interface,
well, it won't exactly kill us.

ron



From stepan at coresystems.de  Thu Oct  1 00:51:17 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 00:51:17 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <46F32041A2CB4C16A76C44EF06B9052E@chimp>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
Message-ID: <4AC3E0E5.6090005@coresystems.de>

Myles Watson wrote:
>> -#if CONFIG_CBFS == 1
>> -# if CONFIG_USE_FALLBACK_IMAGE == 1
>> +#if CONFIG_USE_FALLBACK_IMAGE == 1
>> str_coreboot_ram_name:	.string "fallback/coreboot_ram"
>> -# else
>> +#else
>> str_coreboot_ram_name:	.string "normal/coreboot_ram"
>> -# endif
>> #endif
>>     
>
> Since normal and failover aren't supported with CBFS, can they disappear
> too?
>   

No, we should get that back to life with CBFS asap.. it's one of
coreboot's key features..

Stefan





From mylesgw at gmail.com  Thu Oct  1 00:56:24 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 30 Sep 2009 16:56:24 -0600
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3E0E5.6090005@coresystems.de>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
Message-ID: <EE34A4A67F4C425B8D8599C00A6C6342@chimp>

> > Since normal and failover aren't supported with CBFS, can they disappear
> > too?
> >
> 
> No, we should get that back to life with CBFS asap.. it's one of
> coreboot's key features..

Good to know.  It seemed like it was being slowly removed.

I'm interested to see how it integrates with Kconfig.  It's not obvious to
me how it will work.

Thanks,
Myles




From stepan at coresystems.de  Thu Oct  1 01:00:03 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 01:00:03 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930224333.14184.qmail@stuge.se>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
Message-ID: <4AC3E2F3.6060509@coresystems.de>

Peter Stuge wrote:
>> If the m57sli is an exception and we'll never see this problem
>> again, I say we drop it. Copying all of flash into ram sounds bad.
>>     
>
> It would be unfortunate to drop support for one of the most hack
> friendly boards that we've seen in a while.
>
>   
I agree. I don't see why we should drop the board support just because
one hack does not work anymore.
(A hack nobody around seems to be using to begin with)

There is no problem with unmodified boards, and there is no problem with
modified boards with flash chips under a certain size. So unless someone
with a larger amount of m57sli boards, or motivation to come up with a
solution to get this fixed, I suggest we move on and improve life for
the other 99.99% coreboot users.


Stefan



From rminnich at gmail.com  Thu Oct  1 01:07:21 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 16:07:21 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3E2F3.6060509@coresystems.de>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
Message-ID: <13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>

Yes, I'm sorry, we keep board support, but stop worrying about huge
SPI anbd weird accessing of it.

As for fallback: we really need to bring it back at some point. I'm
speaking as someone whose life was saved because I did not destroy a
1024-node cluster with a bad bios image.

CBFS will give us a normal/fallback setup that people can understand.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 01:16:06 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 01:16:06 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
Message-ID: <4AC3E6B6.7000504@gmx.net>

On 01.10.2009 01:07, ron minnich wrote:
> Yes, I'm sorry, we keep board support, but stop worrying about huge
> SPI anbd weird accessing of it.
>
> As for fallback: we really need to bring it back at some point. I'm
> speaking as someone whose life was saved because I did not destroy a
> 1024-node cluster with a bad bios image.
>
> CBFS will give us a normal/fallback setup that people can understand.
>   

Could we simply reuse arch/x86/stage1.c from v3 and run a search+replace
lar->cbfs on that file? As a nice side benefit, we get global variables
and similar stuff.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From kevin at koconnor.net  Thu Oct  1 01:23:08 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 30 Sep 2009 19:23:08 -0400
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3E0E5.6090005@coresystems.de>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
Message-ID: <20090930232308.GA1720@morn.localdomain>

On Thu, Oct 01, 2009 at 12:51:17AM +0200, Stefan Reinauer wrote:
> Myles Watson wrote:
> > Since normal and failover aren't supported with CBFS, can they disappear
> > too?
> 
> No, we should get that back to life with CBFS asap.. it's one of
> coreboot's key features..

What's the use case for normal/failover?  I always envisioned it as a
software implementation of a "bios savior".  If so, building in a
serialice shell might be a simpler solution.

Am I missing an important use-case?

-Kevin



From rminnich at gmail.com  Thu Oct  1 01:26:44 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 16:26:44 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930232308.GA1720@morn.localdomain>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
Message-ID: <13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>

On Wed, Sep 30, 2009 at 4:23 PM, Kevin O'Connor <kevin at koconnor.net> wrote:

> What's the use case for normal/failover? ?I always envisioned it as a
> software implementation of a "bios savior". ?If so, building in a
> serialice shell might be a simpler solution.
>
> Am I missing an important use-case?

I'm flashing 1024 machines. power fails midway through. bad.

I flash a new bios that has worked in test. It fails on 10% of the
machines, in ways that could not be predicted because 10% of my
machines
have a manufacturing defect. This is what happened to me. Fallback saved me.

There are lots of use cases. It's why many vendors ship with a fallback.

ron



From rminnich at gmail.com  Thu Oct  1 01:27:28 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 16:27:28 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3E6B6.7000504@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<4AC3E6B6.7000504@gmx.net>
Message-ID: <13426df10909301627x221dbb3bs747b04fd02ee52da@mail.gmail.com>

On Wed, Sep 30, 2009 at 4:16 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Could we simply reuse arch/x86/stage1.c from v3 and run a search+replace
> lar->cbfs on that file? As a nice side benefit, we get global variables
> and similar stuff.

I've looked into doing just that. It's not as simple as it sounds. I'd
rather not open that can of worms just yet.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 01:31:33 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 01:31:33 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
Message-ID: <4AC3EA55.8090409@gmx.net>

On 01.10.2009 00:32, ron minnich wrote:
> can anyone even buy an m57sli any more? Was it an unfortunate mistake
> -- never repeated -- that FLASH was not directly accessible? If the
> m57sli is an exception and we'll never see this problem again, I say
> we drop it. Copying all of flash into ram sounds bad. If we have to
> cope with this problem in future, maybe we're stuck with accessor
> functions.
>
> But FLASH is so slow I doubt that the cost of an accessor function is
> going to kill us. Function calls run in nanoseconds, and if SPI really
> is only 40 MB/sec., then that's 25 ns/byte.
>   

The accessor function has the disadvantage of ruining readability of the
code, and it also has to perform these extremely slow accesses every
time someone walks the CBFS image.

AFAIK the M57SLI worst case read performance is ~400 kB/s, and the best
case is ~855 kB/s. Each one-byte read access to flash needs at least 2.5
us (microseconds), and a three-byte read access needs at least 3.5 us.
If your flash chip can handle 33 MHz with the normal read command
(instead of the fast read command), flash access latency will be cut in
half and data rate will be doubled.

While using accessor functions look somewhat beneficial from a
performance standpoint, using accessor functions to run the lzma
decompressor is waaaaay slower (I think by at least a factor of 4) than
copying the uncompressed code to RAMand decompressing it there.


My suggestion would be to drop support for these large flash chips on
M57SLI for now and use the copy-to-RAM mechanism once someone complains.
I think Harald Gutmann has such a board with big flash.

Regads,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 01:42:55 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 01:42:55 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301627x221dbb3bs747b04fd02ee52da@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>	
	<20090930205626.25395.qmail@stuge.se>	
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	
	<4AC3D6CD.7000403@gmx.net>	
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	
	<20090930224333.14184.qmail@stuge.se>	
	<4AC3E2F3.6060509@coresystems.de>	
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	
	<4AC3E6B6.7000504@gmx.net>
	<13426df10909301627x221dbb3bs747b04fd02ee52da@mail.gmail.com>
Message-ID: <4AC3ECFF.9050801@gmx.net>

On 01.10.2009 01:27, ron minnich wrote:
> On Wed, Sep 30, 2009 at 4:16 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> Could we simply reuse arch/x86/stage1.c from v3 and run a search+replace
>> lar->cbfs on that file? As a nice side benefit, we get global variables
>> and similar stuff.
>>     
>
> I've looked into doing just that. It's not as simple as it sounds.
>   

I'm surprised. My stage1 SMP patch was never merged IIRC, so stack
trashing is expected on any non-UP v3 boot. But other than that, v3
stage1 code worked pretty well. The ELFboot code in there should be
dropped (was default off anyway) and then we have a pretty readable startup.

> I'd rather not open that can of worms just yet.
>   

If you're talking about doing too many things at once, I fully agree.
Once the tree is CBFS-only and once Kconfig works for all actively
developed boards, we will have a mostly stable tree again and it would
be cool to look at importing stage1 (and possibly stage0) from v3.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Thu Oct  1 01:44:04 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 01:44:04 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301546mb782b25ud7a4fbc36aa33d57@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<13426df10909301546mb782b25ud7a4fbc36aa33d57@mail.gmail.com>
Message-ID: <20090930234404.24304.qmail@stuge.se>

ron minnich wrote:
> Yeah, I was going worst-case scenario (i.e. SPI is super-fast) and
> even in that case accessor functions would not hurt much if at all.

Ah!


> So if we absolutely *have* to do some sort of function interface,
> well, it won't exactly kill us.

I think it would be great to not have to deal with that in the common
case, but I think it can be useful for some boards - ie. if there is
would I think it would be best to make it optional.


//Peter



From stepan at coresystems.de  Thu Oct  1 01:45:35 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 01:45:35 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3E6B6.7000504@gmx.net>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<4AC3E6B6.7000504@gmx.net>
Message-ID: <4AC3ED9F.6030701@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 01.10.2009 01:07, ron minnich wrote:
>   
>> Yes, I'm sorry, we keep board support, but stop worrying about huge
>> SPI anbd weird accessing of it.
>>
>> As for fallback: we really need to bring it back at some point. I'm
>> speaking as someone whose life was saved because I did not destroy a
>> 1024-node cluster with a bad bios image.
>>
>> CBFS will give us a normal/fallback setup that people can understand.
>>   
>>     
>
> Could we simply reuse arch/x86/stage1.c from v3 and run a search+replace
> lar->cbfs on that file? As a nice side benefit, we get global variables
> and similar stuff.
>   

No search and replace blind copy of non-fitting code please. The least
we can use in v2 right now is a code quality drop to v3 level ..

One step after the other..

It's not enough to have one board running. If you have a solution to
safely bring over 200 boards, please do it!


Stefan




From stepan at coresystems.de  Thu Oct  1 01:49:16 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 01:49:16 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930232308.GA1720@morn.localdomain>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
Message-ID: <4AC3EE7C.1060309@coresystems.de>

Kevin O'Connor wrote:
> On Thu, Oct 01, 2009 at 12:51:17AM +0200, Stefan Reinauer wrote:
>   
>> Myles Watson wrote:
>>     
>>> Since normal and failover aren't supported with CBFS, can they disappear
>>> too?
>>>       
>> No, we should get that back to life with CBFS asap.. it's one of
>> coreboot's key features..
>>     
>
> What's the use case for normal/failover?  I always envisioned it as a
> software implementation of a "bios savior".  If so, building in a
> serialice shell might be a simpler solution.
>
>   
SerialICE is more or less a development tool.. it won't help you with
misflashed units in the field.

Safe updates and safe recovery is the key.

Details are quite open though, the fallback image could carry some kind
of shell, while the "real one" goes SeaBIOS; depending on how people
want to boot, and how they want to recover.

Stefan




From stepan at coresystems.de  Thu Oct  1 01:51:47 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 01:51:47 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <1254343315.9254.20.camel@tetris>
References: <1254343315.9254.20.camel@tetris>
Message-ID: <4AC3EF13.5050500@coresystems.de>

Patrick Georgi wrote:
> Hi,
>
> attached patch removes:
> - CONFIG_CBFS
> - anything that's conditional on CONFIG_CBFS == 0
> - files that were only included for CONFIG_CBFS == 0
> In particular:
> - elfboot
> - stream boot code
> - mini-filo and filesystems (depends on stream boot code)
>
> After this patch, there is no way to build an image that is not using
> CBFS anymore.
>
> I might not have caught everything, but an abuild run over everything
> built fine, and there is no mention of "CBFS" in the tree anymore that
> doesn't belong there.
> Kconfig is almost not affected, as it's CBFS-only, anyway. I only had to
> remove the CBFS configuration variable that defaulted to "true".
>
> I consider the tree ready for this as there are no known bugs anymore
> (except the one fixed by that other patch). Speak up if you disagree (I
> intend to wait with committing this patch until saturday evening CEST)
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>





From kevin at koconnor.net  Thu Oct  1 01:57:21 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 30 Sep 2009 19:57:21 -0400
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
Message-ID: <20090930235721.GA1833@morn.localdomain>

On Wed, Sep 30, 2009 at 04:26:44PM -0700, ron minnich wrote:
> On Wed, Sep 30, 2009 at 4:23 PM, Kevin O'Connor <kevin at koconnor.net> wrote:
> > What's the use case for normal/failover? ?I always envisioned it as a
> > software implementation of a "bios savior". ?If so, building in a
> > serialice shell might be a simpler solution.
> >
> > Am I missing an important use-case?
> 
> I'm flashing 1024 machines. power fails midway through. bad.

Ouch.  So, I guess we're saying it's a software "bios savior" that
doesn't require one to go hitting 1000 switches?

As an aside, to protect against a power failure, flashrom is going to
need to know that it shouldn't reflash the "fallback" parts of the
image.

> I flash a new bios that has worked in test. It fails on 10% of the
> machines, in ways that could not be predicted because 10% of my
> machines
> have a manufacturing defect. This is what happened to me. Fallback saved me.

Ouch - I guess hooking up a serialice console to 100 machines isn't an
appealing alternative.

Just to throw my 2cents in -- the coreboot fallback/normal thing has
been thoroughly confusing to me.  If this is being re-implemented it
would be nice to see this done in a way that makes sense to users.

One suggestion I have - assuming my "bios savior" analogy is correct -
would be to truly break up the fallback and normal parts.  A user that
wants fallback/normal should download two separate copies of
coreboot-v2 into two separate directories, and then run "make config ;
make" in both separate directories.  The "normal" config would take
the directory location of the "fallback" cbfs image, copy it into its
local directory, and then just add the cbfs files it needs.

In particular, I'd like to be able to go into my "normal" directory
and run "svn up", "make", and then "flashrom" - and be fairly
confident that I didn't just blow up my image.  As near as I can tell,
the current fallback/normal thing recompiles both fallback and normal
images, and there's a pretty good chance that both images are hosed
when code changes are made.  (Of course, as I said before,
fallback/normal has me perplexed, so maybe I just missed the boat.)

-Kevin



From peter at stuge.se  Thu Oct  1 01:58:16 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 01:58:16 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3EE7C.1060309@coresystems.de>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<4AC3EE7C.1060309@coresystems.de>
Message-ID: <20090930235816.26548.qmail@stuge.se>

Stefan Reinauer wrote:
> Safe updates and safe recovery is the key.
> 
> Details are quite open though, the fallback image could carry some
> kind of shell,

Maybe this touches on the panic room.


> depending on how people want to boot, and how they want to recover.

Yeah, this is important.

A panic room should not be too ambitious, or it might not be quite
as reliable as we would like. If very simple, it may not be a good
choice also for fallback.


//Peter



From svn at coreboot.org  Thu Oct  1 02:02:28 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 02:02:28 +0200
Subject: [coreboot] [v2] r4698 - trunk/coreboot-v2/src/mainboard/dell/s1850
Message-ID: <mailman.3769.1355071625.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-01 02:02:28 +0200 (Thu, 01 Oct 2009)
New Revision: 4698

Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
Log:
This is now set up more like the real hardware likes it. 
Some of this trickery was determined with serialice. 
There are several lovely undocumented features to the chipset. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-09-30 21:36:38 UTC (rev 4697)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-10-01 00:02:28 UTC (rev 4698)
@@ -173,8 +173,13 @@
 }
 
 /* end IPMI garbage */
+
 static void main(unsigned long bist)
 {
+	u8 b;
+	u16 w;
+	u32 l;
+	int do_reset;
 	/*
 	 * 
 	 * 
@@ -191,6 +196,80 @@
 		}
 	};
 
+	/* using SerialICE, we've seen this basic reset sequence on the dell. 
+	 * we don't understand it as it uses undocumented registers, but
+	 * we're going to clone it. 
+	 */
+	/* enable a hidden device. */
+	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
+	b |= 0x8;
+	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+
+	/* read-write lock in CMOS on LPC bridge on ICH5 */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
+
+	/* operate on undocumented device */
+	l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
+	l |= 0x1000;
+	pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
+
+	l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
+	l |= 0x8000;
+	pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
+
+	/* disable undocumented device */
+	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
+	b &= ~0x8;
+	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+	
+	/* set up LPC bridge bits, some of which reply on undocumented
+	 * registers
+	 */
+	
+	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
+	b |= 4;
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
+
+	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
+	b |= 2;
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
+
+	/* ACPI base address */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
+
+	/* Enable specific ACPI features */
+	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
+	b |= 0x10;
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
+
+	/* ACPI control */
+	w = inw(0x868);
+	outw(w|0x800, 0x868);
+	w = inw(0x866);
+	outw(w|2, 0x866);
+
+	/* SMBUS */
+	pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
+
+	/* unknown */
+	b = inb(0x8c2);
+	outb(0xdf, 0x8c2);
+
+	/* another device enable? */
+	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
+	b |= 2;
+	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
+	
+	/* ?? */
+	l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0);
+	do_reset = l & 0x8000000;
+	l |= 0x8000000;
+	pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l);
+
+	if (! do_reset) {
+		outb(2, 0xcf9);
+		outb(6, 0xcf9);
+	}
 	if (bist == 0) {
 		/* Skip this if there was a built in self test failure */
 		early_mtrr_init();




From rminnich at gmail.com  Thu Oct  1 02:05:00 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 17:05:00 -0700
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930235816.26548.qmail@stuge.se>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<4AC3EE7C.1060309@coresystems.de>
	<20090930235816.26548.qmail@stuge.se>
Message-ID: <13426df10909301705v5baf4a8fx2d7973fd9532d345@mail.gmail.com>

The fallback should work like the normal does. What you want, if
things go wrong, is something that works as much like what you're used
to as possible, so that you can recover easily.

The worst thing you can do, if things go wrong, is drop users into an
unfamiliar environment that sends them scurrying around looking for
the manuals.

The panic room should look just like the normal room, save it has a
big sign that says "Don't Panic".

ron



From peter at stuge.se  Thu Oct  1 02:05:55 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 02:05:55 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930235721.GA1833@morn.localdomain>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
	<20090930235721.GA1833@morn.localdomain>
Message-ID: <20091001000555.27764.qmail@stuge.se>

Kevin O'Connor wrote:
> As an aside, to protect against a power failure, flashrom is going
> to need to know that it shouldn't reflash the "fallback" parts of
> the image.

Yes. flashrom should know CBFS.



> truly break up the fallback and normal parts.

I see a few problem with normal and fallback as they have been in v2
previously;

It was not well understood how to produce them. It was not well
understood how they were combined. And finally it was not well
understood how one of the two were selected.

CBFS and Kconfig fixes the hard parts; the first two.

I see cbfstool being a crucial part of safe updates. Initially
cbfstool might have to be run manually (or even just flashrom) but
we should look into how Kconfig and the build system can take an
existing CBFS as input, and only build/replace the normal part.


> In particular, I'd like to be able to go into my "normal"
> directory and run "svn up", "make", and then "flashrom" - and be
> fairly confident that I didn't just blow up my image.

Two directories strikes me as pretty complicated but I do get your
point - it should be really easy to rebuild and flash normal, without
touching anything else.


//Peter



From stepan at coresystems.de  Thu Oct  1 02:11:40 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 02:11:40 +0200
Subject: [coreboot] [v2] r4698 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
Message-ID: <4AC3F3BC.8090300@coresystems.de>

svn at coreboot.org wrote:
> Author: rminnich
> Date: 2009-10-01 02:02:28 +0200 (Thu, 01 Oct 2009)
> New Revision: 4698
>
> Modified:
>    trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
> Log:
> This is now set up more like the real hardware likes it. 
> Some of this trickery was determined with serialice. 
> There are several lovely undocumented features to the chipset. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>
>
>
>   
:-) Nice

> Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
> ===================================================================
> --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-09-30 21:36:38 UTC (rev 4697)
> +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c	2009-10-01 00:02:28 UTC (rev 4698)
> @@ -173,8 +173,13 @@
>  }
>  
>  /* end IPMI garbage */
> +
>  static void main(unsigned long bist)
>  {
> +	u8 b;
> +	u16 w;
> +	u32 l;
> +	int do_reset;
>  	/*
>  	 * 
>  	 * 
> @@ -191,6 +196,80 @@
>  		}
>  	};
>  
> +	/* using SerialICE, we've seen this basic reset sequence on the dell. 
> +	 * we don't understand it as it uses undocumented registers, but
> +	 * we're going to clone it. 
> +	 */
> +	/* enable a hidden device. */
> +	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> +	b |= 0x8;
> +	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
> +
> +	/* read-write lock in CMOS on LPC bridge on ICH5 */
> +	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
> +
> +	/* operate on undocumented device */
>   
Can you dump the pci config space or read the pci id of that device?

> +	l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
> +	l |= 0x1000;
> +	pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
> +
> +	l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
> +	l |= 0x8000;
> +	pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
> +
> +	/* disable undocumented device */
> +	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> +	b &= ~0x8;
> +	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
> +	
> +	/* set up LPC bridge bits, some of which reply on undocumented
> +	 * registers
> +	 */
> +	
> +	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
> +	b |= 4;
> +	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
> +
> +	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
> +	b |= 2;
> +	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
> +
> +	/* ACPI base address */
> +	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
>   

bit 0 is hard wired to 1 so it doesn't matter much I guess.

> +
> +	/* Enable specific ACPI features */
> +	b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
> +	b |= 0x10;
> +	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
> +
> +	/* ACPI control */
> +	w = inw(0x868);
> +	outw(w|0x800, 0x868);
> +	w = inw(0x866);
> +	outw(w|2, 0x866);
>   
This is something in the TCO area, probably disabling the watchdog

> +
> +	/* SMBUS */
> +	pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
> +
> +	/* unknown */
> +	b = inb(0x8c2);
> +	outb(0xdf, 0x8c2);
> +
> +	/* another device enable? */
> +	b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> +	b |= 2;
> +	pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
> +	
> +	/* ?? */
> +	l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0);
> +	do_reset = l & 0x8000000;
> +	l |= 0x8000000;
> +	pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l);
> +
> +	if (! do_reset) {
> +		outb(2, 0xcf9);
> +		outb(6, 0xcf9);
> +	}
>  	if (bist == 0) {
>  		/* Skip this if there was a built in self test failure */
>  		early_mtrr_init();
>
>
>   




From stepan at coresystems.de  Thu Oct  1 02:13:00 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 02:13:00 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930235816.26548.qmail@stuge.se>
References: <1254343315.9254.20.camel@tetris>	<46F32041A2CB4C16A76C44EF06B9052E@chimp>	<4AC3E0E5.6090005@coresystems.de>	<20090930232308.GA1720@morn.localdomain>	<4AC3EE7C.1060309@coresystems.de>
	<20090930235816.26548.qmail@stuge.se>
Message-ID: <4AC3F40C.9040300@coresystems.de>

Peter Stuge wrote:
> Stefan Reinauer wrote:
>   
>> Safe updates and safe recovery is the key.
>>
>> Details are quite open though, the fallback image could carry some
>> kind of shell,
>>     
>
> Maybe this touches on the panic room.
>   
Got a pointer?

Stefan




From info at coresystems.de  Thu Oct  1 02:29:27 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 02:29:27 +0200
Subject: [coreboot] build service results for r4698
Message-ID: <E1Mt9Xz-0002qV-Iq@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4698 to
the coreboot repository. This caused the following 
changes:

Change Log:
This is now set up more like the real hardware likes it.
Some of this trickery was determined with serialice.
There are several lovely undocumented features to the chipset.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Thu Oct  1 02:44:47 2009
From: rminnich at gmail.com (ron minnich)
Date: Wed, 30 Sep 2009 17:44:47 -0700
Subject: [coreboot] [v2] r4698 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <4AC3F3BC.8090300@coresystems.de>
References: <4AC3F3BC.8090300@coresystems.de>
Message-ID: <13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>

On Wed, Sep 30, 2009 at 5:11 PM, Stefan Reinauer <stepan at coresystems.de> wrote:

> :-) Nice

Sorry. I just assumed nobody would even care about this antique. Hope
no one is too annoyed by the self-ack.


>> + ? ? /* operate on undocumented device */
>>
> Can you dump the pci config space or read the pci id of that device?

no, because the Dell BIOS turns it completely off.


>> + ? ? /* ACPI base address */
>> + ? ? pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
>>
>
> bit 0 is hard wired to 1 so it doesn't matter much I guess.


yes, I'm cloning what they do by watching IO with serialice. They did
not read it and or it in in this one case.

lotsa magic bits here. This is a really old part so I'm a little
surprised. Not too much, any more.

Going to have a long delay now while I convert to CAR. Also having a
meeting in 2 weeks that may kill the whole project.

ron



From eswierk at aristanetworks.com  Thu Oct  1 02:51:37 2009
From: eswierk at aristanetworks.com (Ed Swierk)
Date: Wed, 30 Sep 2009 17:51:37 -0700
Subject: [coreboot] [v2] r4698 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <4ac3f1a3.181abc0a.7f24.20ccSMTPIN_ADDED@mx.google.com>
References: <4ac3f1a3.181abc0a.7f24.20ccSMTPIN_ADDED@mx.google.com>
Message-ID: <9ae48b020909301751t3a85e708se97d5aa8cbae5ea8@mail.gmail.com>

On Wed, Sep 30, 2009 at 5:02 PM,  <svn at coreboot.org> wrote:
> + ? ? ? /* using SerialICE, we've seen this basic reset sequence on the dell.
> + ? ? ? ?* we don't understand it as it uses undocumented registers, but
> + ? ? ? ?* we're going to clone it.
> + ? ? ? ?*/
> + ? ? ? /* enable a hidden device. */
> + ? ? ? b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> + ? ? ? b |= 0x8;
> + ? ? ? pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
> +
> + ? ? ? /* read-write lock in CMOS on LPC bridge on ICH5 */
> + ? ? ? pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
> +
> + ? ? ? /* operate on undocumented device */
> + ? ? ? l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
> + ? ? ? l |= 0x1000;
> + ? ? ? pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
> +
> + ? ? ? l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
> + ? ? ? l |= 0x8000;
> + ? ? ? pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
> +
> + ? ? ? /* disable undocumented device */
> + ? ? ? b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> + ? ? ? b &= ~0x8;
> + ? ? ? pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);

http://downloadmirror.intel.com/8815/ENG/README.TXT offers a hint
about what this is doing, but doesn't really explain why:

"According MCH BSU 0.82, document#64:Required Register Settings. To
take full advantage of the changes in the MCH Silicon, for stability
on MCH B0 stepping and above, Intel recommends that BIOS clear bit 12
of D0:F2:R0A4h and set bit 15 of D0:F2:R09Ch very early during boot."

--Ed



From kevin at koconnor.net  Thu Oct  1 03:03:17 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 30 Sep 2009 21:03:17 -0400
Subject: [coreboot] SeaBIOS and USB UHCI keyboard support
In-Reply-To: <20090930191822.8795.qmail@stuge.se>
References: <20090929015323.GA26906@morn.localdomain>
	<4AC21DE8.5010200@coresystems.de>
	<20090930005336.GA29642@morn.localdomain>
	<20090930191822.8795.qmail@stuge.se>
Message-ID: <20091001010317.GB1981@morn.localdomain>

On Wed, Sep 30, 2009 at 09:18:21PM +0200, Peter Stuge wrote:
> Kevin O'Connor wrote:
> > The support in SeaBIOS is currently 1029 lines of code - it is a
> > direct, no nonsense, just make it work implementation.
> 
> I think that is wonderful! Good job!

Thanks!

> > The next thing I am planning to look at is basic ohci keyboard
> > support, and then fleshing out the current keyboard support (eg,
> > auto-repeat, keyboard leds).
> 
> The USB option ROM is still a tricky point. How to make it co-exist
> with USB support in SeaBIOS?

As Stefan pointed out, there can be only one driver of a usb
controller.  Anything else would be too fragile.

> If the option ROM works out well, maybe it could instead offer the
> keyboard services?

Yes - an option ROM can support keyboard.  However, a real 16bit
option ROM implementation is going to impose the same constraints on
libpayload as SeaBIOS.  Alternatively, the option rom could give up
support for vm86 mode callers and reserve lots of high ram to avoid
those constraints.  It still wouldn't be simple - the rom would need
to implement the bios calls for disk and kbd (seabios src/disk.c
src/kbd.c src/bregs.h src/entryfuncs.S = 1792 lines of code) and may
need to implement self uncompression (to reduce its rom code size).
I'd say it's doable, but not easy.

-Kevin



From peter at stuge.se  Thu Oct  1 03:25:50 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 03:25:50 +0200
Subject: [coreboot] [v2] r4698
	-	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <9ae48b020909301751t3a85e708se97d5aa8cbae5ea8@mail.gmail.com>
References: <4ac3f1a3.181abc0a.7f24.20ccSMTPIN_ADDED@mx.google.com>
	<9ae48b020909301751t3a85e708se97d5aa8cbae5ea8@mail.gmail.com>
Message-ID: <20091001012550.20810.qmail@stuge.se>

Ed Swierk wrote:
> http://downloadmirror.intel.com/8815/ENG/README.TXT offers a hint
> about what this is doing, but doesn't really explain why:
..
> for stability on MCH B0 stepping and above,

A secret/magic erratum. Yippee. :)


//Peter



From peter at stuge.se  Thu Oct  1 03:28:19 2009
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Oct 2009 03:28:19 +0200
Subject: [coreboot] SeaBIOS and USB UHCI keyboard support
In-Reply-To: <20091001010317.GB1981@morn.localdomain>
References: <20090929015323.GA26906@morn.localdomain>
	<4AC21DE8.5010200@coresystems.de>
	<20090930005336.GA29642@morn.localdomain>
	<20090930191822.8795.qmail@stuge.se>
	<20091001010317.GB1981@morn.localdomain>
Message-ID: <20091001012819.21492.qmail@stuge.se>

Kevin O'Connor wrote:
> > The USB option ROM is still a tricky point. How to make it co-exist
> > with USB support in SeaBIOS?
> 
> As Stefan pointed out, there can be only one driver of a usb
> controller.  Anything else would be too fragile.

Yeah. The debug port can be used in parallell with another USB stack,
but that's only good for debug transfers.


> > If the option ROM works out well, maybe it could instead offer
> > the keyboard services?
> 
> Yes - an option ROM can support keyboard.
..
> I'd say it's doable, but not easy.

I don't know what the result was/is from the GSoC project. You are
aware that there has been a GSoC project for a USB option ROM, right?


//Peter



From stepan at coresystems.de  Thu Oct  1 03:28:44 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 1 Oct 2009 03:28:44 +0200
Subject: [coreboot] [v2] r4698 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
References: <4AC3F3BC.8090300@coresystems.de>
	<13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
Message-ID: <DD395BBB-286C-47CA-8C7A-7A778222C87A@coresystems.de>



On Oct 1, 2009, at 2:44, ron minnich <rminnich at gmail.com> wrote:

> On Wed, Sep 30, 2009 at 5:11 PM, Stefan Reinauer <stepan at coresystems.de 
> > wrote:
>
>> :-) Nice
>
> Sorry. I just assumed nobody would even care about this antique. Hope
> no one is too annoyed by the self-ack.
>
>
>>> +     /* operate on undocumented device */
>>>
>> Can you dump the pci config space or read the pci id of that device?
>
> no, because the Dell BIOS turns it completely off.
>

There's a pci config space dumper in one or two of the debug.c versions




>
>>> +     /* ACPI base address */
>>> +     pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
>>>
>>
>> bit 0 is hard wired to 1 so it doesn't matter much I guess.
>
>
> yes, I'm cloning what they do by watching IO with serialice. They did
> not read it and or it in in this one case.
>
> lotsa magic bits here. This is a really old part so I'm a little
> surprised. Not too much, any more.
>
> Going to have a long delay now while I convert to CAR. Also having a
> meeting in 2 weeks that may kill the whole project.
>

Sure you want to add new points of failure? ;-)


> ron
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Stefan



From uwe at hermann-uwe.de  Thu Oct  1 03:30:40 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Oct 2009 03:30:40 +0200
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
Message-ID: <20091001013040.GC15511@greenwood>

Hi,

tried to boot-test the VIA p2500e yesterday, but tried a manual
non-kconfig build first, and that one doesn't successfully boot anymore
and thus needs to be fixed first.

The cfbs output was (I used a FILO payload):

Name                           Offset     Type         Size
fallback/payload               0x0        payload      85864
fallback/coreboot_ram          0x14fc0    stage        35069
                               0x1d900    null         337592

Here's a bootlog, there's a "hang" at the end, no further output on
serial afterwards. Any ideas what the issue may be?


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-------------- next part --------------
coreboot-2.0.0-r4697-pc2500e Thu Oct  1 00:04:48 CEST 2009 booting...
Calibrating delay loop...
end 2cb8ad7b3, start 1dc56e326
32-bit delta 3827
calibrate_tsc 32-bit result is 3827
clocks_per_usec: 3827
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 1, 0 resources
PCI: 00:00.3: enabled 1, 0 resources
PCI: 00:00.4: enabled 1, 0 resources
PCI: 00:00.7: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:0f.0: enabled 1, 0 resources
PCI: 00:0f.1: enabled 1, 0 resources
PCI: 00:10.0: enabled 1, 0 resources
PCI: 00:10.1: enabled 1, 0 resources
PCI: 00:10.2: enabled 1, 0 resources
PCI: 00:10.3: enabled 1, 0 resources
PCI: 00:10.4: enabled 1, 0 resources
PCI: 00:10.5: enabled 1, 0 resources
PCI: 00:11.0: enabled 1, 0 resources
PNP: 002e.0: enabled 1, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 1, 3 resources
PNP: 002e.4: enabled 1, 3 resources
PNP: 002e.5: enabled 0, 3 resources
PNP: 002e.6: enabled 0, 1 resources
PNP: 002e.7: enabled 1, 3 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 1, 2 resources
PCI: 00:11.5: enabled 1, 0 resources
PCI: 00:12.0: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:00.0: enabled 1, 0 resources
  PCI: 00:00.1: enabled 1, 0 resources
  PCI: 00:00.2: enabled 1, 0 resources
  PCI: 00:00.3: enabled 1, 0 resources
  PCI: 00:00.4: enabled 1, 0 resources
  PCI: 00:00.7: enabled 1, 0 resources
  PCI: 00:01.0: enabled 1, 0 resources
  PCI: 00:0f.0: enabled 1, 0 resources
  PCI: 00:0f.1: enabled 1, 0 resources
  PCI: 00:10.0: enabled 1, 0 resources
  PCI: 00:10.1: enabled 1, 0 resources
  PCI: 00:10.2: enabled 1, 0 resources
  PCI: 00:10.3: enabled 1, 0 resources
  PCI: 00:10.4: enabled 1, 0 resources
  PCI: 00:10.5: enabled 1, 0 resources
  PCI: 00:11.0: enabled 1, 0 resources
   PNP: 002e.0: enabled 1, 3 resources
   PNP: 002e.1: enabled 1, 2 resources
   PNP: 002e.2: enabled 0, 2 resources
   PNP: 002e.3: enabled 1, 3 resources
   PNP: 002e.4: enabled 1, 3 resources
   PNP: 002e.5: enabled 0, 3 resources
   PNP: 002e.6: enabled 0, 1 resources
   PNP: 002e.7: enabled 1, 3 resources
   PNP: 002e.8: enabled 0, 2 resources
   PNP: 002e.9: enabled 0, 1 resources
   PNP: 002e.a: enabled 1, 2 resources
  PCI: 00:11.5: enabled 1, 0 resources
  PCI: 00:12.0: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
scan_static_bus for Root Device
In cn700 enable_dev for device PCI_DOMAIN: 0000.
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
In cn700 enable_dev for device APIC_CLUSTER: 0.
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
In cn700 enable_dev for device PCI: 00:00.0.
PCI: 00:00.0 [1106/0314] ops
PCI: 00:00.0 [1106/0314] enabled
In cn700 enable_dev for device PCI: 00:00.1.
PCI: 00:00.1 [1106/1314] enabled
In cn700 enable_dev for device PCI: 00:00.2.
PCI: 00:00.2 [1106/2314] enabled
In cn700 enable_dev for device PCI: 00:00.3.
PCI: 00:00.3 [1106/3208] ops
PCI: 00:00.3 [1106/3208] enabled
In cn700 enable_dev for device PCI: 00:00.4.
PCI: 00:00.4 [1106/4314] enabled
PCI: 00:00.5, bad id 0xffffffff
PCI: 00:00.6, bad id 0xffffffff
In cn700 enable_dev for device PCI: 00:00.7.
PCI: 00:00.7 [1106/7314] enabled
In cn700 enable_dev for device PCI: 00:01.0.
PCI: 00:01.0 [1106/b198] bus ops
PCI: 00:01.0 [1106/b198] enabled
PCI: 00:02.0, bad id 0xffffffff
PCI: 00:03.0, bad id 0xffffffff
PCI: 00:04.0, bad id 0xffffffff
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0, bad id 0xffffffff
PCI: 00:07.0, bad id 0xffffffff
PCI: 00:08.0, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0 [1106/3149] ops
PCI: 00:0f.0 [1106/3149] enabled
PCI: 00:0f.1 [1106/0571] ops
PCI: 00:0f.1 [1106/0571] enabled
PCI: 00:0f.2, bad id 0xffffffff
PCI: 00:0f.3, bad id 0xffffffff
PCI: 00:0f.4, bad id 0xffffffff
PCI: 00:0f.5, bad id 0xffffffff
PCI: 00:0f.6, bad id 0xffffffff
PCI: 00:0f.7, bad id 0xffffffff
PCI: 00:10.0 [1106/3038] ops
PCI: 00:10.0 [1106/3038] enabled
PCI: 00:10.1 [1106/3038] ops
PCI: 00:10.1 [1106/3038] enabled
PCI: 00:10.2 [1106/3038] ops
PCI: 00:10.2 [1106/3038] enabled
PCI: 00:10.3 [1106/3038] ops
PCI: 00:10.3 [1106/3038] enabled
PCI: 00:10.4 [1106/3104] ops
PCI: 00:10.4 [1106/3104] enabled
PCI: 00:10.5 [1106/d104] enabled
PCI: 00:10.6, bad id 0xffffffff
PCI: 00:10.7, bad id 0xffffffff
PCI: 00:11.0 [1106/3227] bus ops
PCI: 00:11.0 [1106/3227] enabled
PCI: 00:11.1, bad id 0xffffffff
PCI: 00:11.2, bad id 0xffffffff
PCI: 00:11.3, bad id 0xffffffff
PCI: 00:11.4, bad id 0xffffffff
PCI: 00:11.5 [1106/3059] enabled
PCI: 00:11.6, bad id 0xffffffff
PCI: 00:11.7, bad id 0xffffffff
PCI: 00:12.0 [1106/3065] ops
PCI: 00:12.0 [1106/3065] enabled
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
malloc Enter, size 1100, free_mem_ptr 00022000
malloc 00022000
PCI: 01:00.0 [1106/3344] ops
PCI: 01:00.0 [1106/3344] enabled
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:11.0
PNP: 002e.0 enabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 enabled
PNP: 002e.4 enabled
PNP: 002e.5 disabled
PNP: 002e.6 disabled
PNP: 002e.7 enabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
scan_static_bus for PCI: 00:11.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 01:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:11.0 read_resources bus 0 link: 0
PCI: 00:11.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 Root Device
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.1 links 0 child on link 0 NULL
   PCI: 00:00.2 links 0 child on link 0 NULL
   PCI: 00:00.3 links 0 child on link 0 NULL
   PCI: 00:00.4 links 0 child on link 0 NULL
   PCI: 00:00.7 links 0 child on link 0 NULL
   PCI: 00:01.0 links 1 child on link 0 PCI: 00:01.0
    PCI: 01:00.0 links 0 child on link 0 NULL
    PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
    PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
    PCI: 01:00.0 resource base fff80000 size 100 align 16 gran 16 limit ffffffff flags c0002200 index 30
   PCI: 00:0f.0 links 0 child on link 0 NULL
   PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24
   PCI: 00:0f.1 links 0 child on link 0 NULL
   PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:10.0 links 0 child on link 0 NULL
   PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:10.1 links 0 child on link 0 NULL
   PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:10.2 links 0 child on link 0 NULL
   PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:10.3 links 0 child on link 0 NULL
   PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:10.4 links 0 child on link 0 NULL
   PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:10.5 links 0 child on link 0 NULL
   PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:11.0 links 1 child on link 0 PCI: 00:11.0
   PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e0000100 index 88
   PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e0000100 index 3
   PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e0000100 index d0
   PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags e0000200 index 44
   PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
    PNP: 002e.0 links 0 child on link 0 NULL
    PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 002e.1 links 0 child on link 0 NULL
    PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.2 links 0 child on link 0 NULL
    PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.3 links 0 child on link 0 NULL
    PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 002e.4 links 0 child on link 0 NULL
    PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62
    PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.5 links 0 child on link 0 NULL
    PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
    PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.6 links 0 child on link 0 NULL
    PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.7 links 0 child on link 0 NULL
    PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
    PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62
    PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 64
    PNP: 002e.8 links 0 child on link 0 NULL
    PNP: 002e.8 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 60
    PNP: 002e.8 resource base a size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.9 links 0 child on link 0 NULL
    PNP: 002e.9 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.a links 0 child on link 0 NULL
    PNP: 002e.a resource base 310 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
    PNP: 002e.a resource base b size 0 align 0 gran 0 limit 0 flags c0000400 index 70
   PCI: 00:11.5 links 0 child on link 0 NULL
   PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:12.0 links 0 child on link 0 NULL
   PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
  APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0
   APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:0f.0 24 *  [0x0 - 0xff] io
PCI: 00:11.5 10 *  [0x400 - 0x4ff] io
PCI: 00:12.0 10 *  [0x800 - 0x8ff] io
PCI: 00:10.0 20 *  [0xc00 - 0xc1f] io
PCI: 00:10.1 20 *  [0xc20 - 0xc3f] io
PCI: 00:10.2 20 *  [0xc40 - 0xc5f] io
PCI: 00:10.3 20 *  [0xc60 - 0xc7f] io
PCI: 00:0f.0 20 *  [0xc80 - 0xc8f] io
PCI: 00:0f.1 20 *  [0xc90 - 0xc9f] io
PCI: 00:0f.0 10 *  [0xca0 - 0xca7] io
PCI: 00:0f.0 18 *  [0xca8 - 0xcaf] io
PCI: 00:0f.0 14 *  [0xcb0 - 0xcb3] io
PCI: 00:0f.0 1c *  [0xcb4 - 0xcb7] io
PCI_DOMAIN: 0000 compute_resources_io: base: cb8 size: cb8 align: 8 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:10.4 10 *  [0x0 - 0xff] mem
PCI: 00:10.5 10 *  [0x100 - 0x1ff] mem
PCI: 00:12.0 14 *  [0x200 - 0x2ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 300 size: 300 align: 8 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:00.1
constrain_resources: PCI: 00:00.2
constrain_resources: PCI: 00:00.3
constrain_resources: PCI: 00:00.4
constrain_resources: PCI: 00:00.7
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:0f.1
constrain_resources: PCI: 00:10.0
constrain_resources: PCI: 00:10.1
constrain_resources: PCI: 00:10.2
constrain_resources: PCI: 00:10.3
constrain_resources: PCI: 00:10.4
constrain_resources: PCI: 00:10.5
constrain_resources: PCI: 00:11.0
constrain_resources: PNP: 002e.0
constrain_resources: PNP: 002e.1
constrain_resources: PNP: 002e.3
constrain_resources: PNP: 002e.4
constrain_resources: PNP: 002e.7
skipping PNP: 002e.7 at 60 fixed resource, size=0!
constrain_resources: PNP: 002e.a
skipping PNP: 002e.a at 60 fixed resource, size=0!
skipping PNP: 002e.a at 70 fixed resource, size=0!
constrain_resources: PCI: 00:11.5
constrain_resources: PCI: 00:12.0
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
	lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:cb8 align:8 gran:0 limit:ffff
Assigned: PCI: 00:0f.0 24 *  [0x1000 - 0x10ff] io
Assigned: PCI: 00:11.5 10 *  [0x1400 - 0x14ff] io
Assigned: PCI: 00:12.0 10 *  [0x1800 - 0x18ff] io
Assigned: PCI: 00:10.0 20 *  [0x1c00 - 0x1c1f] io
Assigned: PCI: 00:10.1 20 *  [0x1c20 - 0x1c3f] io
Assigned: PCI: 00:10.2 20 *  [0x1c40 - 0x1c5f] io
Assigned: PCI: 00:10.3 20 *  [0x1c60 - 0x1c7f] io
Assigned: PCI: 00:0f.0 20 *  [0x1c80 - 0x1c8f] io
Assigned: PCI: 00:0f.1 20 *  [0x1c90 - 0x1c9f] io
Assigned: PCI: 00:0f.0 10 *  [0x1ca0 - 0x1ca7] io
Assigned: PCI: 00:0f.0 18 *  [0x1ca8 - 0x1caf] io
Assigned: PCI: 00:0f.0 14 *  [0x1cb0 - 0x1cb3] io
Assigned: PCI: 00:0f.0 1c *  [0x1cb4 - 0x1cb7] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1cb8 size: cb8 align: 8 gran: 0 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:febffd00 size:300 align:8 gran:0 limit:febfffff
Assigned: PCI: 00:10.4 10 *  [0xfebffd00 - 0xfebffdff] mem
Assigned: PCI: 00:10.5 10 *  [0xfebffe00 - 0xfebffeff] mem
Assigned: PCI: 00:12.0 14 *  [0xfebfff00 - 0xfebfffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fec00000 size: 300 align: 8 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Entering cn700 pci_domain_set_resources.
Entering find_pci_tolm
Leaving find_pci_tolm
tomk is 0x80000
tom: 20000000, high_tables_base: 1fff0000, high_tables_size: 10000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:0f.0 10 <- [0x0000001ca0 - 0x0000001ca7] size 0x00000008 gran 0x03 io
PCI: 00:0f.0 14 <- [0x0000001cb0 - 0x0000001cb3] size 0x00000004 gran 0x02 io
PCI: 00:0f.0 18 <- [0x0000001ca8 - 0x0000001caf] size 0x00000008 gran 0x03 io
PCI: 00:0f.0 1c <- [0x0000001cb4 - 0x0000001cb7] size 0x00000004 gran 0x02 io
PCI: 00:0f.0 20 <- [0x0000001c80 - 0x0000001c8f] size 0x00000010 gran 0x04 io
PCI: 00:0f.0 24 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:0f.1 20 <- [0x0000001c90 - 0x0000001c9f] size 0x00000010 gran 0x04 io
PCI: 00:10.0 20 <- [0x0000001c00 - 0x0000001c1f] size 0x00000020 gran 0x05 io
PCI: 00:10.1 20 <- [0x0000001c20 - 0x0000001c3f] size 0x00000020 gran 0x05 io
PCI: 00:10.2 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
PCI: 00:10.3 20 <- [0x0000001c60 - 0x0000001c7f] size 0x00000020 gran 0x05 io
PCI: 00:10.4 10 <- [0x00febffd00 - 0x00febffdff] size 0x00000100 gran 0x08 mem
PCI: 00:10.5 10 <- [0x00febffe00 - 0x00febffeff] size 0x00000100 gran 0x08 mem
PCI: 00:11.0 01 <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x00 io
PCI: 00:11.0 assign_resources, bus 0 link: 0
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.3 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq
PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io
PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io
PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq
PNP: 002e.7 60 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 io
PNP: 002e.7 62 <- [0x0000000800 - 0x0000000807] size 0x00000008 gran 0x03 io
PNP: 002e.7 64 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io
PNP: 002e.a 60 <- [0x0000000310 - 0x000000030f] size 0x00000000 gran 0x00 io
PNP: 002e.a 70 <- [0x000000000b - 0x000000000a] size 0x00000000 gran 0x00 irq
PCI: 00:11.0 assign_resources, bus 0 link: 0
PCI: 00:11.5 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
PCI: 00:12.0 14 <- [0x00febfff00 - 0x00febfffff] size 0x00000100 gran 0x08 mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 Root Device
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 resource base 1000 size cb8 align 8 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base febffd00 size 300 align 8 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  PCI_DOMAIN: 0000 resource base c0000 size 1df40000 align 0 gran 0 limit 0 flags e0004200 index b
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.1 links 0 child on link 0 NULL
   PCI: 00:00.2 links 0 child on link 0 NULL
   PCI: 00:00.3 links 0 child on link 0 NULL
   PCI: 00:00.4 links 0 child on link 0 NULL
   PCI: 00:00.7 links 0 child on link 0 NULL
   PCI: 00:01.0 links 1 child on link 0 PCI: 00:01.0
    PCI: 01:00.0 links 0 child on link 0 NULL
    PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
    PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
    PCI: 01:00.0 resource base fff80000 size 100 align 16 gran 16 limit ffffffff flags c0002200 index 30
   PCI: 00:0f.0 links 0 child on link 0 NULL
   PCI: 00:0f.0 resource base 1ca0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:0f.0 resource base 1cb0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:0f.0 resource base 1ca8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:0f.0 resource base 1cb4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:0f.0 resource base 1c80 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:0f.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 24
   PCI: 00:0f.1 links 0 child on link 0 NULL
   PCI: 00:0f.1 resource base 1c90 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:10.0 links 0 child on link 0 NULL
   PCI: 00:10.0 resource base 1c00 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:10.1 links 0 child on link 0 NULL
   PCI: 00:10.1 resource base 1c20 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:10.2 links 0 child on link 0 NULL
   PCI: 00:10.2 resource base 1c40 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:10.3 links 0 child on link 0 NULL
   PCI: 00:10.3 resource base 1c60 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:10.4 links 0 child on link 0 NULL
   PCI: 00:10.4 resource base febffd00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:10.5 links 0 child on link 0 NULL
   PCI: 00:10.5 resource base febffe00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:11.0 links 1 child on link 0 PCI: 00:11.0
   PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e0000100 index 88
   PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e0000100 index 3
   PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e0000100 index d0
   PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags e0000200 index 44
   PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags e0000100 index 1
    PNP: 002e.0 links 0 child on link 0 NULL
    PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
    PNP: 002e.1 links 0 child on link 0 NULL
    PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 002e.2 links 0 child on link 0 NULL
    PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.3 links 0 child on link 0 NULL
    PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
    PNP: 002e.4 links 0 child on link 0 NULL
    PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62
    PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 002e.5 links 0 child on link 0 NULL
    PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
    PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.6 links 0 child on link 0 NULL
    PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.7 links 0 child on link 0 NULL
    PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags e0000100 index 60
    PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62
    PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 64
    PNP: 002e.8 links 0 child on link 0 NULL
    PNP: 002e.8 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 60
    PNP: 002e.8 resource base a size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.9 links 0 child on link 0 NULL
    PNP: 002e.9 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.a links 0 child on link 0 NULL
    PNP: 002e.a resource base 310 size 0 align 0 gran 0 limit 0 flags e0000100 index 60
    PNP: 002e.a resource base b size 0 align 0 gran 0 limit 0 flags e0000400 index 70
   PCI: 00:11.5 links 0 child on link 0 NULL
   PCI: 00:11.5 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
   PCI: 00:12.0 links 0 child on link 0 NULL
   PCI: 00:12.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
   PCI: 00:12.0 resource base febfff00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
  APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0
   APIC: 00 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:00.1 subsystem <- 1019/aa51
PCI: 00:00.1 cmd <- 06
PCI: 00:00.2 subsystem <- 1019/aa51
PCI: 00:00.2 cmd <- 06
PCI: 00:00.3 missing enable_resources
PCI: 00:00.4 subsystem <- 1019/aa51
PCI: 00:00.4 cmd <- 06
PCI: 00:00.7 subsystem <- 1019/aa51
PCI: 00:00.7 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 01:00.0 cmd <- 03
PCI: 00:0f.0 cmd <- 01
PCI: 00:0f.1 cmd <- 81
PCI: 00:10.0 cmd <- 01
PCI: 00:10.1 cmd <- 01
PCI: 00:10.2 cmd <- 01
PCI: 00:10.3 cmd <- 01
PCI: 00:10.4 cmd <- 02
PCI: 00:10.5 subsystem <- 1019/aa51
PCI: 00:10.5 cmd <- 02
PCI: 00:11.0 cmd <- 07
PCI: 00:11.5 subsystem <- 1019/aa51
PCI: 00:11.5 cmd <- 01
PCI: 00:12.0 cmd <- 83
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
Enabling AGP.
PCI: 00:00.1 init
PCI: 00:00.2 init
PCI: 00:00.3 init
PCI: 00:00.4 init
PCI: 00:00.7 init
PCI: 00:01.0 init
Setting up AGP bridge device
PCI: 00:0f.0 init
Configuring VIA SATA controller
PCI: 00:0f.1 init
Primary IDE interface enabled
Secondary IDE interface enabled
Enables in reg 0x40 read back as 0x4f
Enables in reg 0x42 read back as 0x9
PCI: 00:10.0 init
PCI: 00:10.1 init
PCI: 00:10.2 init
PCI: 00:10.3 init
PCI: 00:10.4 init
PCI: 00:10.5 init
PCI: 00:11.0 init
Entering vt8237r_init.
RTC Init
Invalid CMOS LB checksum
Keyboard init...
Leaving vt8237r_init.
PNP: 002e.0 init
PNP: 002e.1 init
PNP: 002e.3 init
PNP: 002e.4 init
FAN_CTL: reg = 0x02a9, read value = 0x50
FAN_CTL: reg = 0x02a9, writing value = 0xd7
PNP: 002e.7 init
PNP: 002e.a init
PCI: 00:11.5 init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Centaur device 6a9
CPU: family 06, model 0a, stepping 09
Detected VIA Model A C7-D
Enabling improved C7 clock and voltage.
Voltage: 1084mV (min 1084mV; max 1084mV)
CPU multiplier: 15x (min 15x; max 15x)
 msr.lo = f000f18
 new msr.lo = f18
Current voltage: 1084mV
Current CPU multiplier: 15x
Enabling cache

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base:    0MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 1, base:  256MB, range:  128MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 2, base:  384MB, range:   64MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 3, base:  448MB, range:   32MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU #0 initialized
All AP CPUs stopped
PCI: 01:00.0 init
Copying BOCHS BIOS to 0xf000
Initializing VGA
INSTALL REAL-MODE IDT
DO THE VGA BIOS
found VGA: vid=1106, did=3344
rom base, size: fff80000
BAD SIGNATURE 0x4c 0x41
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 1, 0 resources
PCI: 00:00.3: enabled 1, 0 resources
PCI: 00:00.4: enabled 1, 0 resources
PCI: 00:00.7: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:0f.0: enabled 1, 6 resources
PCI: 00:0f.1: enabled 1, 1 resources
PCI: 00:10.0: enabled 1, 1 resources
PCI: 00:10.1: enabled 1, 1 resources
PCI: 00:10.2: enabled 1, 1 resources
PCI: 00:10.3: enabled 1, 1 resources
PCI: 00:10.4: enabled 1, 1 resources
PCI: 00:10.5: enabled 1, 1 resources
PCI: 00:11.0: enabled 1, 5 resources
PNP: 002e.0: enabled 1, 3 resources
PNP: 002e.1: enabled 1, 2 resources
PNP: 002e.2: enabled 0, 2 resources
PNP: 002e.3: enabled 1, 3 resources
PNP: 002e.4: enabled 1, 3 resources
PNP: 002e.5: enabled 0, 3 resources
PNP: 002e.6: enabled 0, 1 resources
PNP: 002e.7: enabled 1, 3 resources
PNP: 002e.8: enabled 0, 2 resources
PNP: 002e.9: enabled 0, 1 resources
PNP: 002e.a: enabled 1, 2 resources
PCI: 00:11.5: enabled 1, 1 resources
PCI: 00:12.0: enabled 1, 2 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI: 01:00.0: enabled 1, 3 resources
High Tables Base is 1fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Copying Interrupt Routing Table to 0x1fff0000... done.
Wrote the mp table end at: 000f0410 - 000f0568
Wrote the mp table end at: 1fff0410 - 2001040e
Moving GDT to 0x20010800...ok
Multiboot Information structure has been written.
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum d3dd
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x20010c00
rom_table_end = 0x20010c00
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x20010c00 to 0x20020000 

From eswierk at aristanetworks.com  Thu Oct  1 03:35:56 2009
From: eswierk at aristanetworks.com (Ed Swierk)
Date: Wed, 30 Sep 2009 18:35:56 -0700
Subject: [coreboot] [v2] r4698 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
References: <4AC3F3BC.8090300@coresystems.de>
	<13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
Message-ID: <9ae48b020909301835i4af19b75h54733bff03efbdc0@mail.gmail.com>

On Wed, Sep 30, 2009 at 5:44 PM, ron minnich <rminnich at gmail.com> wrote:
> On Wed, Sep 30, 2009 at 5:11 PM, Stefan Reinauer <stepan at coresystems.de> wrote:
>>> + ? ? /* operate on undocumented device */
>>>
>> Can you dump the pci config space or read the pci id of that device?
>
> no, because the Dell BIOS turns it completely off.

It shouldn't harm anything to leave the undocumented device enabled.
Then you can boot Linux and sniff around with lspci.

--Ed



From stepan at coresystems.de  Thu Oct  1 04:13:02 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 1 Oct 2009 04:13:02 +0200
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
In-Reply-To: <20091001013040.GC15511@greenwood>
References: <20091001013040.GC15511@greenwood>
Message-ID: <3727BEFB-D550-4737-96EC-58670D0342E8@coresystems.de>

Can you try without cbfs? Did it work with cbfs before?

If the issue is new, can you bisect where it happened?

On Oct 1, 2009, at 3:30, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> Hi,
>
> tried to boot-test the VIA p2500e yesterday, but tried a manual
> non-kconfig build first, and that one doesn't successfully boot  
> anymore
> and thus needs to be fixed first.
>
> The cfbs output was (I used a FILO payload):
>
> Name                           Offset     Type         Size
> fallback/payload               0x0        payload      85864
> fallback/coreboot_ram          0x14fc0    stage        35069
>                               0x1d900    null         337592
>
> Here's a bootlog, there's a "hang" at the end, no further output on
> serial afterwards. Any ideas what the issue may be?
>
>
> Uwe.
> -- 
> http://www.hermann-uwe.de  | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
> <minicom_pc2500e_cbfs_nokconfig.txt>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



From mylesgw at gmail.com  Thu Oct  1 05:34:09 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 30 Sep 2009 21:34:09 -0600
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
In-Reply-To: <20091001013040.GC15511@greenwood>
References: <20091001013040.GC15511@greenwood>
Message-ID: <0245AF4550D4474DBCCE0C2083A3F306@chimp>



> -----Original Message-----
> From: coreboot-bounces+mylesgw=gmail.com at coreboot.org [mailto:coreboot-
> bounces+mylesgw=gmail.com at coreboot.org] On Behalf Of Uwe Hermann
> Sent: Wednesday, September 30, 2009 7:31 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
> 
> Hi,
> 
> tried to boot-test the VIA p2500e yesterday, but tried a manual
> non-kconfig build first, and that one doesn't successfully boot anymore
> and thus needs to be fixed first.
> 
> The cfbs output was (I used a FILO payload):
> 
> Name                           Offset     Type         Size
> fallback/payload               0x0        payload      85864
> fallback/coreboot_ram          0x14fc0    stage        35069
>                                0x1d900    null         337592
> 
> Here's a bootlog, there's a "hang" at the end, no further output on
> serial afterwards. Any ideas what the issue may be?
It doesn't look like a place I would expect CBFS to be the issue.

> tomk is 0x80000
> tom: 20000000, high_tables_base: 1fff0000, high_tables_size: 10000
512M of RAM = 0x20000000, 64K for high tables.
...
> High Tables Base is 1fff0000.
> Copying Interrupt Routing Table to 0x000f0000... done.
> Copying Interrupt Routing Table to 0x1fff0000... done.
> Wrote the mp table end at: 000f0410 - 000f0568
> Wrote the mp table end at: 1fff0410 - 2001040e
Writing high tables above RAM!  Why is the high MP table so much larger than
the low one?
 
> Moving GDT to 0x20010800...ok
> Multiboot Information structure has been written.
> Writing high table forward entry at 0x00000500
> Wrote coreboot table at: 00000500 - 00000518  checksum d3dd
> New low_table_end: 0x00000518
> Now going to write high coreboot table at 0x20010c00
> rom_table_end = 0x20010c00
> Adjust low_table_end from 0x00000518 to 0x00001000 
> Adjust rom_table_end from 0x20010c00 to 0x20020000
And more writing above RAM.

I don't know that that is the cause of your trouble, but it isn't good.  An
easy thing to try would be to increase high_tables_size to 0x40000 and see
if you get anything different.  I'm surprised that your mp table is so
large.  Maybe that's where the real problem is?

Thanks,
Myles




From patrick at georgi-clan.de  Thu Oct  1 08:50:43 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 01 Oct 2009 08:50:43 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <46F32041A2CB4C16A76C44EF06B9052E@chimp>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
Message-ID: <1254379843.21870.3.camel@tetris>

Am Mittwoch, den 30.09.2009, 15:41 -0600 schrieb Myles Watson:
> >Index: src/devices/pci_rom.c
> >===================================================================
> >--- src/devices/pci_rom.c	(Revision 4696)
> >+++ src/devices/pci_rom.c	(Arbeitskopie)
> >@@ -35,17 +35,15 @@
> > 	struct rom_header *rom_header;
> > 	struct pci_data *rom_data;
> 
> > 	if (dev->on_mainboard) {
> > 		/* this is here as a legacy path. We hope it goes away soon.
> >Users should not have to 
> 
> The legacy path is the non-CBFS path and should disappear
The comment is wrong. dev->on_mainboard is set by the CBFS loader a
couple of lines above. This distinction is mostly "ROM in flash" vs.
"ROM in option ROM" now.

Users won't have to calculate addresses with CBFS, so it's fine.
I'll kill the comment in the commit, thanks for the pointer!


> >-#if CONFIG_CBFS == 1
> >-# if CONFIG_USE_FALLBACK_IMAGE == 1
> >+#if CONFIG_USE_FALLBACK_IMAGE == 1
> > str_coreboot_ram_name:	.string "fallback/coreboot_ram"
> >-# else
> >+#else
> > str_coreboot_ram_name:	.string "normal/coreboot_ram"
> >-# endif
> > #endif
> 
> Since normal and failover aren't supported with CBFS, can they disappear
> too?
They are supported with CBFS on newconfig. It's Kconfig that doesn't
support these, but newconfig will have to stay for a while, and so do
these.


Patrick




From patrick at georgi-clan.de  Thu Oct  1 09:09:50 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 01 Oct 2009 09:09:50 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se> <4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
Message-ID: <1254380991.21870.21.camel@tetris>

Am Mittwoch, den 30.09.2009, 16:07 -0700 schrieb ron minnich:
> Yes, I'm sorry, we keep board support, but stop worrying about huge
> SPI anbd weird accessing of it.
> 
> As for fallback: we really need to bring it back at some point. I'm
> speaking as someone whose life was saved because I did not destroy a
> 1024-node cluster with a bad bios image.
> 
> CBFS will give us a normal/fallback setup that people can understand.
It will, but right now, CBFS is worse off than old-style.

I dropped fallback/normal support in Kconfig deliberately, not because
it is hard, but due to the current situation being a mess (~140 copies
of the fallback-or-normal decision function with minor changes), and
that we don't have a plan on how to safely update a CBFS image anyway.

Once we have a plan that's actually safe, does away with the copy&paste
(and the fallback/normal // failover/fallback/normal duality while we're
at it), I'm all for it.
But please not now, with the mess we have.

My plan for it, pending any better solution:
- unify the decision stuff into a single place
- move everything but the decision stuff out of the bootblock (so it
  essentially becomes immutable across updates)
- extend kconfig so it knows how to update existing images (by adding
  new files)
- somehow make flashrom smart enough to safely update the flash

The idea is that Kconfig continues to build only one image, but allows
to add to such an image later, when it's actually time to carry two
images.
The current approach of having two nearly identical images around made
sense in the old memory layout, but not with CBFS, in my opinion.

I have a prototype of the moving-code-around part of it done, on the
QEmu target. It runs raminit from a cbfs file, linked to a fixed address
within cbfs, which avoids weird compiler tricks. CBFS is only used to
allow multiple such images to coexist without the bootblock having to
know their addresses.

Open issues are:
We need early rom mapping and CMOS access for all boards. So far, only
the boards with failover layout are somewhat guaranteed to have code for
that.


Patrick




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 09:26:08 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 09:26:08 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20090930235721.GA1833@morn.localdomain>
References: <1254343315.9254.20.camel@tetris>	<46F32041A2CB4C16A76C44EF06B9052E@chimp>	<4AC3E0E5.6090005@coresystems.de>	<20090930232308.GA1720@morn.localdomain>	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
	<20090930235721.GA1833@morn.localdomain>
Message-ID: <4AC45990.4090409@gmx.net>

On 01.10.2009 01:57, Kevin O'Connor wrote:
> As an aside, to protect against a power failure, flashrom is going to
> need to know that it shouldn't reflash the "fallback" parts of the
> image.
>   

flashrom currently has a patch review bottleneck, so partial reflashing
is stalled.


> Just to throw my 2cents in -- the coreboot fallback/normal thing has
> been thoroughly confusing to me.  If this is being re-implemented it
> would be nice to see this done in a way that makes sense to users.
>
> One suggestion I have - assuming my "bios savior" analogy is correct -
> would be to truly break up the fallback and normal parts.  A user that
> wants fallback/normal should download two separate copies of
> coreboot-v2 into two separate directories, and then run "make config ;
> make" in both separate directories.  The "normal" config would take
> the directory location of the "fallback" cbfs image, copy it into its
> local directory, and then just add the cbfs files it needs.
>
> In particular, I'd like to be able to go into my "normal" directory
> and run "svn up", "make", and then "flashrom" - and be fairly
> confident that I didn't just blow up my image.  As near as I can tell,
> the current fallback/normal thing recompiles both fallback and normal
> images, and there's a pretty good chance that both images are hosed
> when code changes are made.

You do have a point.
In v3, you have an invariant boot block (which contains the CAR code,
serial code, generic PCI accessor functions and printk) and one
"initram" file and one "stage2" file. initram initializes RAM, stage2 is
roughly what coreboot_ram does now. AFAIK the v3 build process only
builds a "normal" image.

Two problem areas need to be looked at:
1. Can the new build reuse the old bootblock? Does the new build have to
know the old bootblock?
2. How do you merge old and new images?

1. is trivial to integrate in the v3 build and bootblock reuse is easy.
Of course you'd want to replace the bootblock (and the rest of the ROM)
if some bootblock code changed.

2. is a bit more problematic regardless of whether you have v2 or v3. If
you don't want to reflash the old parts of the image, you can't rename
them either. If the old part was called "fallback", it will still be
called "fallback" after flashing some new parts into the ROM. That means
each time you reflash, the new part's name will be the opposite of the
old part's name. Of course, with such a system, calling these things
"fallback" and "normal" makes no sense anymore. After all, we always
want to boot the newly flashed image first and the name doesn't tell us
which one is new. There are solutions to this, but the ones I see will
either require to change the CBFS data structure (LAR3 or CBFS2 anyone?)
or put a horrible hack on top of CBFS. Maybe someone else has better ideas.


Now on to flashrom. You suggested that flashrom should understand CBFS
and only flash the newly added parts of the image. (If I misunderstood
you, please accept my apologies.) Given that flashrom already has a
generic image layout feature, I propose to have cbfstool spit out an
image layout file which is then read by flashrom. This makes flashrom
independent of CBFS and that's a good thing (think upgrade).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 09:44:21 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 09:44:21 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <1254380991.21870.21.camel@tetris>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
Message-ID: <4AC45DD5.6050400@gmx.net>

On 01.10.2009 09:09, Patrick Georgi wrote:
> Am Mittwoch, den 30.09.2009, 16:07 -0700 schrieb ron minnich:
>   
>> CBFS will give us a normal/fallback setup that people can understand.
>>     
> It will, but right now, CBFS is worse off than old-style.
>
> [...]
> My plan for it, pending any better solution:
> - unify the decision stuff into a single place
>   

Agreed.


> - move everything but the decision stuff out of the bootblock (so it
>   essentially becomes immutable across updates)
>   

This means we either need a CBFS walker in ASM or compile it with ROMCC.
Even if that is possible (and IIRC you already have code for this) it
strikes me as a bad idea. I want to have as little asm code as possible
and I want to keep ROMCC out of the CAR images. Others may disagree with
me, but I thought I'd say this before the decision is finalized.


> - extend kconfig so it knows how to update existing images (by adding
>   new files)
>   

Sorry, I don't understand this. Did you mean the makefiles? I see no
relation between fallback/normal and Kconfig.


> - somehow make flashrom smart enough to safely update the flash
>   

Patches to add partial erase support for some chips are pending since
quite some time. We need more flashrom reviewers.


> The idea is that Kconfig continues to build only one image, but allows
> to add to such an image later, when it's actually time to carry two
> images.
>   

Ah. I always thought of Kconfig as a configuration system, not a build
system.


> The current approach of having two nearly identical images around made
> sense in the old memory layout, but not with CBFS, in my opinion.
>   

Agreed.


> I have a prototype of the moving-code-around part of it done, on the
> QEmu target. It runs raminit from a cbfs file, linked to a fixed address
> within cbfs, which avoids weird compiler tricks. CBFS is only used to
> allow multiple such images to coexist without the bootblock having to
> know their addresses.
>   

Is that the v3 model?


> Open issues are:
> We need early rom mapping and CMOS access for all boards. So far, only
> the boards with failover layout are somewhat guaranteed to have code for
> that.
>   

Early ROM mapping: Yes. Early CMOS access... hm maybe. Please note that
CMOS access will not solve the issue of deciding which image to boot
unless we decide to forbid clearing CMOS with a jumper. The information
about which image part is newer needs to be somewhere in the ROM image.
See my other mail in this thread for a bit more details.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 09:54:35 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 09:54:35 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC45DD5.6050400@gmx.net>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>
	<4AC45DD5.6050400@gmx.net>
Message-ID: <4AC4603B.7080508@gmx.net>

On 01.10.2009 09:44, Carl-Daniel Hailfinger wrote:
> On 01.10.2009 09:09, Patrick Georgi wrote:
>   
>> We need early rom mapping and CMOS access for all boards. So far, only
>> the boards with failover layout are somewhat guaranteed to have code for
>> that.
>>     
>
> Early ROM mapping: Yes. Early CMOS access... hm maybe. Please note that
> CMOS access will not solve the issue of deciding which image to boot
> unless we decide to forbid clearing CMOS with a jumper. The information
> about which image part is newer needs to be somewhere in the ROM image.
> See my other mail in this thread for a bit more details.
>   

Actually, the mail was not in this thread but rather in
Subject: Re: [coreboot] [PATCH]Remove non-CBFS

Date: Thu, 01 Oct 2009 09:26:08 +0200

Sorry for the incorrect pointer.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From patrick at georgi-clan.de  Thu Oct  1 10:17:42 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 01 Oct 2009 10:17:42 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC45DD5.6050400@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se> <4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>  <4AC45DD5.6050400@gmx.net>
Message-ID: <1254385062.21870.45.camel@tetris>

Am Donnerstag, den 01.10.2009, 09:44 +0200 schrieb Carl-Daniel
Hailfinger:
> > - move everything but the decision stuff out of the bootblock (so it
> >   essentially becomes immutable across updates)
> >   
> 
> This means we either need a CBFS walker in ASM or compile it with ROMCC.
I have a CBFS walker in ASM, and I'd prefer using romcc for some things
(eg. early HT init on K8).

> Even if that is possible (and IIRC you already have code for this) it
> strikes me as a bad idea. I want to have as little asm code as possible
> and I want to keep ROMCC out of the CAR images.
ROMCC is bad if it's used for the entire ram init code. Early init is
supposed to be a small piece of code, and that's what ROMCC is quite
good at.

>  Others may disagree with
> me, but I thought I'd say this before the decision is finalized.
I won't force the issue - but there must be a better way than having 140
copies of "if cmos say good, run normal, otherwise run fallback" around.
That's my main concern.

Having an immutable bootblock is only an attempt to have a more robust
update mechanism. Given that I personally won't update systems without
having recovery gear around, it doesn't actually affect me. But if we're
trying to enable updates, I'd rather have them as safe as possible, and
that's what this experiment is about.

> > - extend kconfig so it knows how to update existing images (by adding
> >   new files)
> >   
> 
> Sorry, I don't understand this. Did you mean the makefiles? I see no
> relation between fallback/normal and Kconfig.
If two images should be configurable in one pass, Kconfig must be
adapted for that - and it won't be pretty.

I'd rather have the system build _one_ image in one pass, and allow the
user to configure whether a new image is built, or an existing one is
extended with a new image.

This issue is more about what we can express sensibly in Kconfig, than
what the build system can do. The latter is more flexible, but it's
outright lost without being told what it's supposed to do.

> > The idea is that Kconfig continues to build only one image, but allows
> > to add to such an image later, when it's actually time to carry two
> > images.
> >   
> 
> Ah. I always thought of Kconfig as a configuration system, not a build
> system.
Right, but the makefile will only build what can be configured, so
they're really quite interdependent. I'm mixing up terminology there,
I'm sorry about that.

> > I have a prototype of the moving-code-around part of it done, on the
> > QEmu target. It runs raminit from a cbfs file, linked to a fixed address
> > within cbfs, which avoids weird compiler tricks. CBFS is only used to
> > allow multiple such images to coexist without the bootblock having to
> > know their addresses.
> >   
> 
> Is that the v3 model?
The prototype has a ROMCC/assembly bootblock, and raminit in CBFS (where
CAR would end up, too). So it's somewhat different from v3.

I started out from the QEmu decision code. In the end, it is an
experiment, and it's mostly based around my opinions, as outlined above.

But the only thing I _really_ care about is getting rid of the jmp
fallback_image junk in every single mainboard directory.

> Early ROM mapping: Yes. Early CMOS access... hm maybe. Please note that
> CMOS access will not solve the issue of deciding which image to boot
> unless we decide to forbid clearing CMOS with a jumper. The information
> about which image part is newer needs to be somewhere in the ROM image.
> See my other mail in this thread for a bit more details.
While we need some other way to determine which is the newest image (ie.
the one we'd preferably use), we also need a way to figure out that the
newest version didn't actually work on the last attempt. I know no other
place than CMOS to store such information (ie. mark boot as unclean,
boot into coreboot stage, which marks boot as clean right before
entering the payload - or maybe delegating that to the payload, not
sure)


Patrick




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 11:05:25 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 11:05:25 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <1254385062.21870.45.camel@tetris>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>
	<4AC45DD5.6050400@gmx.net> <1254385062.21870.45.camel@tetris>
Message-ID: <4AC470D5.5010803@gmx.net>

On 01.10.2009 10:17, Patrick Georgi wrote:
> Am Donnerstag, den 01.10.2009, 09:44 +0200 schrieb Carl-Daniel
> Hailfinger:
>   
>>> - move everything but the decision stuff out of the bootblock (so it
>>>   essentially becomes immutable across updates)
>>>   
>>>       
>> This means we either need a CBFS walker in ASM or compile it with ROMCC.
>>     
> I have a CBFS walker in ASM, and 
>
> I'd prefer using romcc for some things
> (eg. early HT init on K8).
>   

Unless I'm mistaken, K8 HT init is done with gcc code in CAR in v3.


>> Even if that is possible (and IIRC you already have code for this) it
>> strikes me as a bad idea. I want to have as little asm code as possible
>> and I want to keep ROMCC out of the CAR images.
>>     
> ROMCC is bad if it's used for the entire ram init code. Early init is
> supposed to be a small piece of code, and that's what ROMCC is quite
> good at.
>   

I still worry about romcc bugs (like sometimes ignoring code lines if
there is not enough whitespace before them) which I can't remember being
fixed (mostly due to the ability to work around them).


>>  Others may disagree with
>> me, but I thought I'd say this before the decision is finalized.
>>     
> I won't force the issue - but there must be a better way than having 140
> copies of "if cmos say good, run normal, otherwise run fallback" around.
> That's my main concern.
>   

OK, fully agreed. There is no need to duplicate (or even have 140 copies
of) code which essentially never changes.


> Having an immutable bootblock is only an attempt to have a more robust
> update mechanism. Given that I personally won't update systems without
> having recovery gear around, it doesn't actually affect me. But if we're
> trying to enable updates, I'd rather have them as safe as possible, and
> that's what this experiment is about.
>   

I see your point.


>>> - extend kconfig so it knows how to update existing images (by adding
>>>   new files)
>>>   
>>>       
>> Sorry, I don't understand this. Did you mean the makefiles? I see no
>> relation between fallback/normal and Kconfig.
>>     
> If two images should be configurable in one pass, Kconfig must be
> adapted for that - and it won't be pretty.
>   

True.


> I'd rather have the system build _one_ image in one pass, and allow the
> user to configure whether a new image is built, or an existing one is
> extended with a new image.
>   

Ah, that makes sense. Thanks for clarifying. I agree with this.


> This issue is more about what we can express sensibly in Kconfig, than
> what the build system can do. The latter is more flexible, but it's
> outright lost without being told what it's supposed to do.
>   

True.


>>> The idea is that Kconfig continues to build only one image, but allows
>>> to add to such an image later, when it's actually time to carry two
>>> images.
>>>   
>>>       
>> Ah. I always thought of Kconfig as a configuration system, not a build
>> system.
>>     
> Right, but the makefile will only build what can be configured, so
> they're really quite interdependent. I'm mixing up terminology there,
> I'm sorry about that.
>   

No problem. You explained everything in your followup mail and that's
what counts. ;-)


>>> I have a prototype of the moving-code-around part of it done, on the
>>> QEmu target. It runs raminit from a cbfs file, linked to a fixed address
>>> within cbfs, which avoids weird compiler tricks. CBFS is only used to
>>> allow multiple such images to coexist without the bootblock having to
>>> know their addresses.
>>>   
>>>       
>> Is that the v3 model?
>>     
> The prototype has a ROMCC/assembly bootblock, and raminit in CBFS (where
> CAR would end up, too). So it's somewhat different from v3.
>
> I started out from the QEmu decision code. In the end, it is an
> experiment, and it's mostly based around my opinions, as outlined above.
>   

Given the current state of the tree, your plans are definitely a hige
improvement. I can still send patches to make startup resemble v3 more
closely on top of this.


> But the only thing I _really_ care about is getting rid of the jmp
> fallback_image junk in every single mainboard directory.
>   

Yes!


>> Early ROM mapping: Yes. Early CMOS access... hm maybe. Please note that
>> CMOS access will not solve the issue of deciding which image to boot
>> unless we decide to forbid clearing CMOS with a jumper. The information
>> about which image part is newer needs to be somewhere in the ROM image.
>> See my other mail in this thread for a bit more details.
>>     
> While we need some other way to determine which is the newest image (ie.
> the one we'd preferably use), we also need a way to figure out that the
> newest version didn't actually work on the last attempt. I know no other
> place than CMOS to store such information (ie. mark boot as unclean,
> boot into coreboot stage, which marks boot as clean right before
> entering the payload - or maybe delegating that to the payload, not
> sure)
>   

Right. So we need two variables:
- One variable (in ROM) says which image is newer
- One variable (in CMOS/NVRAM) helps decide whether to boot the new or
the old image.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Thu Oct  1 11:42:45 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Oct 2009 11:42:45 +0200
Subject: [coreboot] [PATCH] simplify coreboot PCI code
In-Reply-To: <4AC1DF43.2020200@gmx.net>
References: <4ABFB3C5.8000203@coresystems.de>
	<4ABFCB11.2050601@gmx.net>	<4AC10E45.5080504@gmx.net>
	<4AC11F0E.5010501@coresystems.de> <4AC1DF43.2020200@gmx.net>
Message-ID: <4AC47995.6090600@gmx.net>

On 29.09.2009 12:19, Carl-Daniel Hailfinger wrote:
> On 28.09.2009 22:39, Stefan Reinauer wrote:
>   
>> Carl-Daniel Hailfinger wrote:
>>   
>>     
>>> On 27.09.2009 22:29, Carl-Daniel Hailfinger wrote:
>>>   
>>>     
>>>       
>>>> On 27.09.2009 20:49, Stefan Reinauer wrote:
>>>>   
>>>>     
>>>>       
>>>>         
>>>>> Simplify coreboot PCI handling
>>>>>
>>>>> This patch drops the conf1/conf2 autodetection and replaces it by 
>>>>> (usually northbridge specific) hardcodes. 
>>>>>
>>>>> This patch also adds pci_domain_init() which needs to be called by
>>>>> mainboard enable_dev() functions in order to be able to use the pci
>>>>> config space functions. This allows to drop i386 specific code from
>>>>> generic files again...
>>>>>
>>>>> There is an even better approach to the PCI config space access in mainboard
>>>>> specific init files problem, but that should go into another patch:
>>>>>
>>>>> static void init(struct device *dev)
>>>>> {
>>>>> 	// Do the stuff here!
>>>>> }
>>>>>
>>>>> static void enable_dev(struct device *dev)
>>>>> {
>>>>>    // Install an init function for this mainboard device
>>>>>    dev->ops->init = init;
>>>>> }
>>>>>
>>>>> struct chip_operations mainboard_ops = {
>>>>>   .enable_dev = enable_dev,
>>>>> };
>>>>>
>>>>> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
>>>>>   
>>>>>     
>>>>>       
>>>>>         
>>>>>           
>>>> I really like this patch. There are one or two things I don't understand
>>>> yet, but I hope stuff will become clearer tomorrow after testing. Will
>>>> ack after testing.
>>>>   
>>>>     
>>>>       
>>>>         
>>> Tested, ends up in a reboot loop. Sorry. Will post the logs (old vs.
>>> new) in an hour.
>>>   
>>>     
>>>       
>> Oh, sorry to hear that. I have to admit, I sent that patch untested, as
>> I wanted to get it out asap.
>>   
>>     
>
> Yes, and I appreciate that. Logs attached. I have cropped the reboot
> loop after the second iteration because the log was an exact repetition.
>
> Working log: minicom_2009-09-28T212527.cap
> Failing log: minicom_2009-09-28T212703.cap
>   

I kept only the RS690 changes and reverted the rest. Result attached.

Will debug further.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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From krasnaya.zvezda at gmail.com  Thu Oct  1 12:02:22 2009
From: krasnaya.zvezda at gmail.com (Marko Kraljevic)
Date: Thu, 01 Oct 2009 04:02:22 -0600
Subject: [coreboot] Advantech GX1 board "PCM-5825F" (lspci, superiotool, etc)
Message-ID: <4AC47E2E.4090404@gmail.com>

In reply to our conversation on #coreboot

See the attached files


Thanks,
mark

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From stepan at coresystems.de  Thu Oct  1 13:15:52 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 01 Oct 2009 13:15:52 +0200
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
In-Reply-To: <0245AF4550D4474DBCCE0C2083A3F306@chimp>
References: <20091001013040.GC15511@greenwood>
	<0245AF4550D4474DBCCE0C2083A3F306@chimp>
Message-ID: <4AC48F68.9000801@coresystems.de>

Myles Watson wrote:
>> High Tables Base is 1fff0000.
>> Copying Interrupt Routing Table to 0x000f0000... done.
>> Copying Interrupt Routing Table to 0x1fff0000... done.
>> Wrote the mp table end at: 000f0410 - 000f0568
>> Wrote the mp table end at: 1fff0410 - 2001040e
>>     
> Writing high tables above RAM!  Why is the high MP table so much larger than
> the low one?
>  
>   

Right! Good spotting... something is reaaaally fishy here... Almost 64k
mp table vs 300 bytes.


>> Moving GDT to 0x20010800...ok
>>     
And, this alone is good for quite a crash.


Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From joe at settoplinux.org  Thu Oct  1 15:48:49 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 09:48:49 -0400
Subject: [coreboot] [v2] r4698
	-	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
References: <4AC3F3BC.8090300@coresystems.de>
	<13426df10909301744p50a68657qbc0b44ad24ef8c89@mail.gmail.com>
Message-ID: <4AC4B341.2080309@settoplinux.org>

On 09/30/2009 08:44 PM, ron minnich wrote:
> On Wed, Sep 30, 2009 at 5:11 PM, Stefan Reinauer<stepan at coresystems.de>  wrote:
>
>> :-) Nice
>
> Sorry. I just assumed nobody would even care about this antique. Hope
> no one is too annoyed by the self-ack.
>
>
>>> +     /* operate on undocumented device */
>>>
>> Can you dump the pci config space or read the pci id of that device?
>
> no, because the Dell BIOS turns it completely off.
>
>
>>> +     /* ACPI base address */
>>> +     pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
>>>
>>
>> bit 0 is hard wired to 1 so it doesn't matter much I guess.
>
>
> yes, I'm cloning what they do by watching IO with serialice. They did
> not read it and or it in in this one case.
 >
Very cool, I have yet to play with serialice. If your watching IO then 
how do you know what the PCI regs are doing? If I could use serialice to 
capture PCI regs, it would solve alot of mysteries....

Or are you just using serialice to capture ACPI read/writes?
>
> lotsa magic bits here. This is a really old part so I'm a little
> surprised. Not too much, any more.
>
> Going to have a long delay now while I convert to CAR. Also having a
> meeting in 2 weeks that may kill the whole project.
>

bummer....would you continue it for personal interest?

---------------------------
 > +	/* ACPI control */
 > > +	w = inw(0x868);
 > > +	outw(w|0x800, 0x868);
 > > +	w = inw(0x866);
 > > +	outw(w|2, 0x866);
 > >
 > This is something in the TCO area, probably disabling the watchdog

Nice! If the TCO timer is not disabled you will reboot for ever....I 
beleive the OS re-enables it?




-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Thu Oct  1 16:06:31 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 10:06:31 -0400
Subject: [coreboot] serialice PCI capture
Message-ID: <4AC4B767.2060406@settoplinux.org>

Just a thought. YABEL can capture PCI read/writes from an option ROM, 
how hard would it be to get serialice to do the same with the bios?

This would solve many of life's mysteries.....

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From hng at lanl.gov  Thu Oct  1 16:54:14 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Thu, 01 Oct 2009 08:54:14 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
Message-ID: <4AC4C296.1050103@lanl.gov>

I am trying to put coreboot v2 on a tyan s2881 and I would like to use 
seabios and gpxe for the payload .  I successfully created the 
coreboot.rom by following the s2881 build tutorial and seabios 
tutorial.  I then tried to add gpxe to the coreboot rom and I received 
this output from cbfstool:

$./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add
../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99
Could not add the file to CBFS, it's probably too big.

$ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print
../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 
262144, romsize 524288, offset 0x0
Alignment: 64 bytes

Name                           Offset     Type         Size
normal/payload                 0x0        payload      65592
normal/coreboot_ram            0x10080    stage        56173
fallback/payload               0x1dc40    payload      65592
fallback/coreboot_ram          0x2dcc0    stage        55651
                               0x3b680    null         18744

I taked to Ron about this and he suggested to try the Kconfig build 
system as that would create a smaller rom.   That failed and I received 
this output:

$make
   GEN        build/build.h
   HOSTCC     build_opt_tbl
   OPTION     option_table.h
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:17:
/local/coreboot/coreboot-v2/build/option_table.h:45:1: warning:
"CMOS_VSTART_reserved_memory" redefined
/local/coreboot/coreboot-v2/build/option_table.h:1:1: warning: this is
the location of the previous definition
/local/coreboot/coreboot-v2/build/option_table.h:46:1: warning:
"CMOS_VLEN_reserved_memory" redefined
/local/coreboot/coreboot-v2/build/option_table.h:2:1: warning: this is
the location of the previous definition
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:19:
/local/coreboot/coreboot-v2/src/pc80/serial.c:74: warning: no previous
prototype for ?uart_init?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:21:
/local/coreboot/coreboot-v2/src/lib/ramtest.c:137: warning: no
previous prototype for ?ram_check?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:32:2:
error: #error This file needs CONFIG_USE_PRINTK_IN_CAR
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:
In function ?print_linkn_in?:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:37:
warning: implicit declaration of function ?printk_debug?
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:
In function ?ht_read_freq_cap?:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:138:
warning: implicit declaration of function ?printk_spew?
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:
In function ?ht_setup_chainx?:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:571:
warning: unused variable ?i?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:39:
/local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c: At top 
level:
/local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:6:
warning: no previous prototype for ?init_timer?
/local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:19:
warning: no previous prototype for ?udelay?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:40:
/local/coreboot/coreboot-v2/src/lib/delay.c:2: warning: no previous
prototype for ?mdelay?
/local/coreboot/coreboot-v2/src/lib/delay.c:9: warning: no previous
prototype for ?delay?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:23:
warning: redundant redeclaration of ?hard_reset?
/local/coreboot/coreboot-v2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c:39:
warning: previous definition of ?hard_reset? was here
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:576:2:
warning: #warning "FIXME: Implement a better test for Opterons"
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:1083:
warning: no previous prototype for ?memory_end_k?
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c: In
function ?sdram_set_spd_registers?:
/local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:2109:
warning: implicit declaration of function ?printk_err?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:90:
/local/coreboot/coreboot-v2/src/lib/generic_sdram.c: At top level:
/local/coreboot/coreboot-v2/src/lib/generic_sdram.c:15: warning: no
previous prototype for ?sdram_no_memory?
/local/coreboot/coreboot-v2/src/lib/generic_sdram.c:27: warning: no
previous prototype for ?sdram_initialize?
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:92:
/local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c: In
function ?do_k8_init_and_stop_secondaries?:
/local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c:78:
warning: unused variable ?apicid?
In file included from
/local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:4,
                from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97:
/local/coreboot/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c:19:5:
warning: "CONFIG_DCACHE_RAM_SIZE" is not defined
In file included from
/local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:6,
                from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97:
/local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c: In
function ?clear_init_ram?:
/local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14:
error: ?CONFIG_DCACHE_RAM_SIZE? undeclared (first use in this
function)
/local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14:
error: (Each undeclared identifier is reported only once
/local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14:
error: for each function it appears in.)
In file included from
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97:
/local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c: In
function ?post_cache_as_ram?:
/local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79:
error: ?CONFIG_DCACHE_RAM_SIZE? undeclared (first use in this
function)
/local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79:
error: ?CONFIG_DCACHE_RAM_BASE? undeclared (first use in this
function)
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:
At top level:
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:107:
warning: no previous prototype for ?failover_process?
/local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:155:
warning: no previous prototype for ?cache_as_ram_main?
make: *** [/local/coreboot/coreboot-v2/build/mainboard/tyan/s2881/auto.inc]
Error 1

Any ideas?  Thanks.

-- 
Hugh Greenberg
Email: hng at lanl.gov




From svn at coreboot.org  Thu Oct  1 17:41:39 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 17:41:39 +0200
Subject: [coreboot] [v2] r4699 - in trunk/coreboot-v2/src/mainboard/dell: .
	s1850
Message-ID: <mailman.3770.1355071626.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-01 17:41:39 +0200 (Thu, 01 Oct 2009)
New Revision: 4699

Added:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
Modified:
   trunk/coreboot-v2/src/mainboard/dell/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/failover.c
Log:
We need this to be Kconfig. The old way is not trusted by me.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/dell/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/Kconfig	2009-10-01 00:02:28 UTC (rev 4698)
+++ trunk/coreboot-v2/src/mainboard/dell/Kconfig	2009-10-01 15:41:39 UTC (rev 4699)
@@ -1 +1,8 @@
-#
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_DELL
+
+source "src/mainboard/dell/s1850/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:41:39 UTC (rev 4699)
@@ -0,0 +1,66 @@
+config BOARD_DELL_S1850
+	bool "Dell S1850"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MPGA604
+	select NORTHBRIDGE_INTEL_E7520
+	select SOUTHBRIDGE_INTEL_I82801ER
+	select SUPERIO_NSC_PC8374
+	select PIRQ_TABLE
+	help
+	  Dell S1850mainboard.
+
+config MAINBOARD_DIR
+	string
+	default dell/s1850
+	depends on BOARD_DELL_S1850
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_TYAN_S2881
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_TYAN_S2881
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "s1850"
+	depends on BOARD_DELL_S1850
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x016c
+	depends on BOARD_DELL_S1850
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_DELL_S1850
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_DELL_S1850
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_DELL_S1850
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_DELL_S1850
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_DELL_S1850
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_DELL_S1850
+

Added: trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	2009-10-01 15:41:39 UTC (rev 4699)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/failover.c	2009-10-01 00:02:28 UTC (rev 4698)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/failover.c	2009-10-01 15:41:39 UTC (rev 4699)
@@ -13,6 +13,8 @@
 
 static unsigned long main(unsigned long bist)
 {
+	/* skip all this nonsense as we are not doing fallback yet */
+	goto fallback_image;
 	/* Did just the cpu reset? */
 	if (memory_initialized()) {
 	 	if (last_boot_normal()) {




From svn at coreboot.org  Thu Oct  1 17:47:15 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 17:47:15 +0200
Subject: [coreboot] [v2] r4700 - trunk/coreboot-v2/src/mainboard/dell/s1850
Message-ID: <mailman.3771.1355071626.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-01 17:47:14 +0200 (Thu, 01 Oct 2009)
New Revision: 4700

Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
Log:
typo

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:41:39 UTC (rev 4699)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:47:14 UTC (rev 4700)
@@ -17,12 +17,12 @@
 config LB_CKS_RANGE_END
 	int
 	default 122
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_DELL_S1850
 
 config LB_CKS_LOC
 	int
         default 123
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_DELL_S1850
 
 config MAINBOARD_PART_NUMBER
 	string




From svn at coreboot.org  Thu Oct  1 17:59:50 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 17:59:50 +0200
Subject: [coreboot] [v2] r4701 - trunk/coreboot-v2/src/mainboard/dell/s1850
Message-ID: <mailman.3772.1355071626.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-01 17:59:49 +0200 (Thu, 01 Oct 2009)
New Revision: 4701

Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
Log:
OK, this builds and even looks right. dell needs its own Makefile.inc because 
it is a P4 and it needs SSE for romcc not to go into infinite loop. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:47:14 UTC (rev 4700)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
@@ -4,6 +4,7 @@
 	select CPU_INTEL_SOCKET_MPGA604
 	select NORTHBRIDGE_INTEL_E7520
 	select SOUTHBRIDGE_INTEL_I82801ER
+	select SOUTHBRIDGE_INTEL_PXHD
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
 	help

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	2009-10-01 15:47:14 UTC (rev 4700)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc	2009-10-01 15:59:49 UTC (rev 4701)
@@ -18,5 +18,46 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-include $(src)/mainboard/Makefile.romccboard.inc
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/cpu_reset.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += failover.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += ../../../../src/cpu/x86/sse/enable_sse.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/sse/disable_sse.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
 
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+driver-y += mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+ifdef POST_EVALUATION
+
+ROMCCFLAGS ?= -mcpu=p4
+
+$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
+	$(obj)/romcc $(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
+
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+else
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c
+	$(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+endif
+
+endif
+




From info at coresystems.de  Thu Oct  1 18:04:34 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 18:04:34 +0200
Subject: [coreboot] build service results for r4699
Message-ID: <E1MtO8w-0003Mh-1H@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4699 to
the coreboot repository. This caused the following 
changes:

Change Log:
We need this to be Kconfig. The old way is not trusted by me.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4699&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4699&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4699&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Thu Oct  1 18:04:54 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 10:04:54 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <4AC4C296.1050103@lanl.gov>
References: <4AC4C296.1050103@lanl.gov>
Message-ID: <2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>

On Thu, Oct 1, 2009 at 8:54 AM, Hugh Greenberg <hng at lanl.gov> wrote:
> I am trying to put coreboot v2 on a tyan s2881 and I would like to use
> seabios and gpxe for the payload . ?I successfully created the coreboot.rom
> by following the s2881 build tutorial and seabios tutorial. ?I then tried to
> add gpxe to the coreboot rom and I received this output from cbfstool:
>
> $./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add
> ../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99
> Could not add the file to CBFS, it's probably too big.
>
> $ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print
> ../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 262144,
> romsize 524288, offset 0x0
> Alignment: 64 bytes

> Name ? ? ? ? ? ? ? ? ? ? ? ? ? Offset ? ? Type ? ? ? ? Size
> normal/payload ? ? ? ? ? ? ? ? 0x0 ? ? ? ?payload ? ? ?65592
> normal/coreboot_ram ? ? ? ? ? ?0x10080 ? ?stage ? ? ? ?56173
> fallback/payload ? ? ? ? ? ? ? 0x1dc40 ? ?payload ? ? ?65592
> fallback/coreboot_ram ? ? ? ? ?0x2dcc0 ? ?stage ? ? ? ?55651
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0x3b680 ? ?null ? ? ? ? 18744
I didn't see how big the gpxe ROM is.  That might influence which of
these choices you make.

You could:
1. shrink your bootblock (CONFIG_ROM_IMAGE_SIZE)
2. do fallback-only (Remove anything that says normal in
targets/tyan/s2881/s2881/Config.lb)

>
> I taked to Ron about this and he suggested to try the Kconfig build system
> as that would create a smaller rom. ? That failed and I received this
> output:

3. Apply the attached patch (updated version of one that is waiting to
be reviewed.)

Thanks,
Myles
-------------- next part --------------
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From rminnich at gmail.com  Thu Oct  1 18:14:02 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 09:14:02 -0700
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
Message-ID: <13426df10910010914i5a28df39sf5cec23f6e9726a9@mail.gmail.com>

That patch looks fine to me, is there an issue?

ron



From mylesgw at gmail.com  Thu Oct  1 18:17:45 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 10:17:45 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <13426df10910010914i5a28df39sf5cec23f6e9726a9@mail.gmail.com>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<13426df10910010914i5a28df39sf5cec23f6e9726a9@mail.gmail.com>
Message-ID: <2831fecf0910010917n8da33dava657da64748ba0e8@mail.gmail.com>

On Thu, Oct 1, 2009 at 10:14 AM, ron minnich <rminnich at gmail.com> wrote:
> That patch looks fine to me, is there an issue?
Not that I know of.  It was just waiting for review.  I just forgot to
include my sign off with the updated patch.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



From rminnich at gmail.com  Thu Oct  1 18:19:38 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 09:19:38 -0700
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <2831fecf0910010917n8da33dava657da64748ba0e8@mail.gmail.com>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<13426df10910010914i5a28df39sf5cec23f6e9726a9@mail.gmail.com>
	<2831fecf0910010917n8da33dava657da64748ba0e8@mail.gmail.com>
Message-ID: <13426df10910010919y3d7c2ddel6b43b21d1849418c@mail.gmail.com>

On Thu, Oct 1, 2009 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Oct 1, 2009 at 10:14 AM, ron minnich <rminnich at gmail.com> wrote:
>> That patch looks fine to me, is there an issue?
> Not that I know of. ?It was just waiting for review. ?I just forgot to
> include my sign off with the updated patch.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From svn at coreboot.org  Thu Oct  1 18:24:58 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 18:24:58 +0200
Subject: [coreboot] [v2] r4702 - in trunk/coreboot-v2/src: cpu cpu/amd
	cpu/amd/model_fxx cpu/amd/socket_940 cpu/amd/socket_AM2
	cpu/amd/socket_F cpu/amd/socket_S1G1 northbridge/amd/amdk8
Message-ID: <mailman.3773.1355071626.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-10-01 18:24:58 +0200 (Thu, 01 Oct 2009)
New Revision: 4702

Modified:
   trunk/coreboot-v2/src/cpu/Kconfig
   trunk/coreboot-v2/src/cpu/amd/Kconfig
   trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig
   trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig
   trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig
   trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig
   trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig
   trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig
Log:
Fix Kconfig build for K8 boards.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/cpu/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -25,7 +25,3 @@
 	bool
 	default y if MAX_CPUS != 1
 	default n
-
-config CPU_SOCKET_TYPE
-	hex
-	default 0

Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -1,3 +1,7 @@
+config K8_REV_F_SUPPORT
+	bool
+	default n
+
 #source src/cpu/amd/socket_754/Kconfig
 #source src/cpu/amd/socket_939/Kconfig
 source src/cpu/amd/socket_940/Kconfig

Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -1,3 +1,7 @@
+config CPU_AMD_MODEL_FXX
+	bool
+	default n
+
 config HAVE_INIT_TIMER
 	bool
 	default y

Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -1,11 +1,10 @@
 config CPU_AMD_SOCKET_940
 	bool
 	default n
-	#Opteron K8 1G HT Support
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 
-config K8_REV_F_SUPPORT
-	bool
-	default n
+config CPU_SOCKET_TYPE
+	hex
+	default 0x0
 	depends on CPU_AMD_SOCKET_940

Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -4,6 +4,7 @@
 	select K8_REV_F_SUPPORT
 	# Opteron K8 1G HT support
 	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_MODEL_FXX
 
 config CPU_SOCKET_TYPE
 	hex

Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -2,8 +2,8 @@
 	bool
 	default n
 	select K8_REV_F_SUPPORT
-	# Opteron K8 1G HT support
 	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_MODEL_FXX
 
 config CPU_SOCKET_TYPE
 	hex

Modified: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -3,6 +3,7 @@
 	default n
 	select K8_REV_F_SUPPORT
 	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_MODEL_FXX
 
 config CPU_SOCKET_TYPE
 	hex

Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig	2009-10-01 15:59:49 UTC (rev 4701)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
@@ -27,6 +27,11 @@
 	default 0x4000000
 	depends on NORTHBRIDGE_AMD_AMDK8
 
+config K8_HT_FREQ_1G_SUPPORT
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AMDK8
+
 config HYPERTRANSPORT_PLUGIN_SUPPORT
 	bool
 	default y




From mylesgw at gmail.com  Thu Oct  1 18:25:45 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 10:25:45 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <13426df10910010919y3d7c2ddel6b43b21d1849418c@mail.gmail.com>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<13426df10910010914i5a28df39sf5cec23f6e9726a9@mail.gmail.com>
	<2831fecf0910010917n8da33dava657da64748ba0e8@mail.gmail.com>
	<13426df10910010919y3d7c2ddel6b43b21d1849418c@mail.gmail.com>
Message-ID: <2831fecf0910010925j3b1d63b5wc51188d714846ffa@mail.gmail.com>

On Thu, Oct 1, 2009 at 10:19 AM, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Oct 1, 2009 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> On Thu, Oct 1, 2009 at 10:14 AM, ron minnich <rminnich at gmail.com> wrote:
>>> That patch looks fine to me, is there an issue?
>> Not that I know of. ?It was just waiting for review. ?I just forgot to
>> include my sign off with the updated patch.
>>
>> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Rev 4702.

Thanks,
Myles



From info at coresystems.de  Thu Oct  1 18:30:20 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 18:30:20 +0200
Subject: [coreboot] build service results for r4700
Message-ID: <E1MtOXs-0006cF-PY@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4700 to
the coreboot repository. This caused the following 
changes:

Change Log:
typo

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4700&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4700&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4700&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Thu Oct  1 18:35:40 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 09:35:40 -0700
Subject: [coreboot] patch: remove total impact
Message-ID: <13426df10910010935j75e2e014ta0859cead614293b@mail.gmail.com>


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From mylesgw at gmail.com  Thu Oct  1 18:48:35 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 10:48:35 -0600
Subject: [coreboot] patch: remove total impact
In-Reply-To: <13426df10910010935j75e2e014ta0859cead614293b@mail.gmail.com>
References: <13426df10910010935j75e2e014ta0859cead614293b@mail.gmail.com>
Message-ID: <B74A097D1C2C4A2EB67EF331522C2C99@chimp>

> Get rid of the total impact. Vendor died 5 years ago and nobody cares.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles




From harald.gutmann at gmx.net  Thu Oct  1 18:50:30 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Thu, 1 Oct 2009 18:50:30 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC3EA55.8090409@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<4AC3EA55.8090409@gmx.net>
Message-ID: <200910011850.30596.harald.gutmann@gmx.net>

On Thursday 01 October 2009 01:31:33 Carl-Daniel Hailfinger wrote:
> While using accessor functions look somewhat beneficial from a
> performance standpoint, using accessor functions to run the lzma
> decompressor is waaaaay slower (I think by at least a factor of 4) than
> copying the uncompressed code to RAMand decompressing it there.
> 
> 
> My suggestion would be to drop support for these large flash chips on
> M57SLI for now and use the copy-to-RAM mechanism once someone complains.
> I think Harald Gutmann has such a board with big flash.
Yes, you're right I've that board with a 4MB (32Mbit) chip, but right now I 
just use a 512kb chip as I never got a kernel image working directly from 
flash.


> 
> Regads,
> Carl-Daniel
> 

Regards,
Harald



From svn at coreboot.org  Thu Oct  1 18:51:36 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 18:51:36 +0200
Subject: [coreboot] [v2] r4703 - in trunk/coreboot-v2/src: . mainboard
Message-ID: <mailman.3774.1355071626.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-01 18:51:36 +0200 (Thu, 01 Oct 2009)
New Revision: 4703

Removed:
   trunk/coreboot-v2/src/mainboard/totalimpact/
Modified:
   trunk/coreboot-v2/src/Kconfig
   trunk/coreboot-v2/src/mainboard/Kconfig
Log:
Get rid of the total impact. Vendor died 5 years ago and nobody cares.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>



Modified: trunk/coreboot-v2/src/Kconfig
===================================================================
--- trunk/coreboot-v2/src/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
+++ trunk/coreboot-v2/src/Kconfig	2009-10-01 16:51:36 UTC (rev 4703)
@@ -152,7 +152,7 @@
 
 config HAVE_HARD_RESET
 	bool
-	default n
+	default 0
 
 config HAVE_INIT_TIMER
 	bool

Modified: trunk/coreboot-v2/src/mainboard/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-01 16:24:58 UTC (rev 4702)
+++ trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-01 16:51:36 UTC (rev 4703)
@@ -92,8 +92,6 @@
 	bool "TeleVideo"
 config VENDOR_THOMSON
 	bool "Thomson"
-config VENDOR_TOTAL_IMPACT
-	bool "Total Impact"
 config VENDOR_TYAN
 	bool "Tyan"
 config VENDOR_VIA
@@ -323,11 +321,6 @@
 
 config MAINBOARD_VENDOR
 	string
-	default "Total Impact"
-	depends on VENDOR_TOTAL_IMPACT
-
-config MAINBOARD_VENDOR
-	string
 	default "Tyan"
 	depends on VENDOR_TYAN
 
@@ -390,7 +383,6 @@
 source "src/mainboard/technologic/Kconfig"
 source "src/mainboard/televideo/Kconfig"
 source "src/mainboard/thomson/Kconfig"
-source "src/mainboard/totalimpact/Kconfig"
 source "src/mainboard/tyan/Kconfig"
 source "src/mainboard/via/Kconfig"
 




From rminnich at gmail.com  Thu Oct  1 18:59:59 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 09:59:59 -0700
Subject: [coreboot] remove motorola PPC boards
Message-ID: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>

I'm pretty sure I'm catching all the Kconfig upper-level stuff but you
can check me.

ron
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From info at coresystems.de  Thu Oct  1 19:05:22 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 19:05:22 +0200
Subject: [coreboot] build service results for r4701
Message-ID: <E1MtP5m-00041c-1E@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4701 to
the coreboot repository. This caused the following 
changes:

Change Log:
OK, this builds and even looks right. dell needs its own Makefile.inc because
it is a P4 and it needs SSE for romcc not to go into infinite loop.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4701&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4701&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4701&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Thu Oct  1 19:16:06 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 11:16:06 -0600
Subject: [coreboot] remove motorola PPC boards
In-Reply-To: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
References: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
Message-ID: <2831fecf0910011016q2444f381ic5d92dbcc94d8e89@mail.gmail.com>

On Thu, Oct 1, 2009 at 10:59 AM, ron minnich <rminnich at gmail.com> wrote:
> I'm pretty sure I'm catching all the Kconfig upper-level stuff but you
> can check me.
If you remove this section in src/config/Options.lb:
###############################################
# Options for motorola/sandpoint
###############################################
...

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



From patrick at georgi-clan.de  Thu Oct  1 19:24:15 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 01 Oct 2009 19:24:15 +0200
Subject: [coreboot] [v2] r4701 -
 trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
Message-ID: <1254417855.533.1.camel@tetris>

Am Donnerstag, den 01.10.2009, 17:59 +0200 schrieb svn at coreboot.org:
> Author: rminnich
> Date: 2009-10-01 17:59:49 +0200 (Thu, 01 Oct 2009)
> New Revision: 4701
> 
> Modified:
>    trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
>    trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
> Log:
> OK, this builds and even looks right. dell needs its own Makefile.inc because 
> it is a P4 and it needs SSE for romcc not to go into infinite loop. 
Just setting ROMCCFLAGS should be enough, right?

ROMCCFLAGS := -mcpu=p4
include $(src)/mainboard/Makefile.romccboard.inc

> -include $(src)/mainboard/Makefile.romccboard.inc
> [..]
> +
> +ROMCCFLAGS ?= -mcpu=p4
> +





From info at coresystems.de  Thu Oct  1 19:40:28 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 19:40:28 +0200
Subject: [coreboot] build service results for r4702
Message-ID: <E1MtPdk-0000vo-3n@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4702 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix Kconfig build for K8 boards.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4702&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4702&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of totalimpact:briq is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4702&device=briq&vendor=totalimpact&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From r.marek at assembler.cz  Thu Oct  1 19:51:04 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 01 Oct 2009 19:51:04 +0200
Subject: [coreboot] ROMSIP missing for kbuild based build
Message-ID: <4AC4EC08.8080507@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

Just FYI,

I'm missing the ROMSTRAP aka ROMSIP in image generated with new kbuild method.
Try it for M2V-MX SE. It causes random HT errors and will not boot the board
sometimes.

You should see at the end:

good:

0007FF80 AA 00 44 50 ? C2 0F 97 61 ? AA 00 44 50 ? C2 0F 97 61 ? AA 00 44 50 ?
C2 0F 97 61  ..DP...a..DP...a..DP...a
0007FF98 AA 00 44 50 ? C2 0F 97 61 ? AA 00 44 50 ? C2 0F 97 61 ? 00 00 00 00 ?
00 00 00 00  ..DP...a..DP...a........
0007FFB0 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ?
00 00 00 00  ........................
0007FFC8 00 00 00 00 ? 00 00 00 00 ? 80 FF 0F 00 ? FF FF FF FF ? FF FF FF FF ?
FF FF FF FF  ........................
0007FFE0 FF FF FF FF ? FF FF FF FF ? FF FF FF FF ? FF FF FF FF ? E9 11 00 FF ?
FF 00 00 00  ........................
0007FFF8 E9 5F 00 FF ? E0 FF FD FF ?
            ._......


bad:
0007FF80 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ?
00 00 00 00  ........................
0007FF98 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ?
00 00 00 00  ........................
0007FFB0 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ?
00 00 00 00  ........................
0007FFC8 00 00 00 00 ? 00 00 00 00 ? 00 00 00 00 ? 00 41 53 55 ? 53 00 4D 32 ?
56 2D 4D 58  .............ASUS.M2V-MX
0007FFE0 20 53 45 00 ? 2B 00 00 00 ? 26 00 00 00 ? 00 00 08 00 ? E9 11 00 FF ?
FF 00 00 00   SE.+...&...............
0007FFF8 E9 5F 00 FF ? E0 FF FE FF ?
            ._......


Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkrE7AgACgkQ3J9wPJqZRNXDQgCdE+H/uI6eH1YBDyJ/YnK4UhqB
jnwAoII+vQQHbNJgu0cZ2YhtET//U/nV
=rOp2
-----END PGP SIGNATURE-----



From mylesgw at gmail.com  Thu Oct  1 19:56:20 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 11:56:20 -0600
Subject: [coreboot] [v2] r4701 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <1254417855.533.1.camel@tetris>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
Message-ID: <2831fecf0910011056idd4f79blbad853b90b8f0dd@mail.gmail.com>

On Thu, Oct 1, 2009 at 11:24 AM, Patrick Georgi <patrick at georgi-clan.de> wrote:
>> Modified:
>> ? ?trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
>> ? ?trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc
>> Log:
>> OK, this builds and even looks right. dell needs its own Makefile.inc because
>> it is a P4 and it needs SSE for romcc not to go into infinite loop.
> Just setting ROMCCFLAGS should be enough, right?
Almost.  See patch.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From mylesgw at gmail.com  Thu Oct  1 20:02:46 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 12:02:46 -0600
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <4AC4EC08.8080507@assembler.cz>
References: <4AC4EC08.8080507@assembler.cz>
Message-ID: <2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>

> I'm missing the ROMSTRAP aka ROMSIP in image generated with new kbuild method.
> Try it for M2V-MX SE. It causes random HT errors and will not boot the board
> sometimes.
Try the attached patch.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From info at coresystems.de  Thu Oct  1 20:04:35 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 20:04:35 +0200
Subject: [coreboot] build service results for r4703
Message-ID: <E1MtQ15-0004AZ-RP@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4703 to
the coreboot repository. This caused the following 
changes:

Change Log:
Get rid of the total impact. Vendor died 5 years ago and nobody cares.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4703&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4703&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From r.marek at assembler.cz  Thu Oct  1 20:06:47 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 01 Oct 2009 20:06:47 +0200
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
Message-ID: <4AC4EFB7.6070101@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Thank you for quick response:

    LINK       coreboot
/usr/bin/ld: section .romstrap loaded at [00000000fffffff0,0000000100000043]
overlaps section .reset loaded at [00000000fffffff0,00000000ffffffff]
/usr/bin/ld: /mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot: section .romstrap
vma 0xfffffff0 overlaps previous sections
collect2: ld returned 1 exit status
make: *** [/mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot] Error 1

Rudolf
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iEYEARECAAYFAkrE77cACgkQ3J9wPJqZRNV87QCfcvGkKGznVYxKOyrgvkOysDw0
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=iZI0
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From mylesgw at gmail.com  Thu Oct  1 20:13:34 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 12:13:34 -0600
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <4AC4EFB7.6070101@assembler.cz>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
Message-ID: <2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>

On Thu, Oct 1, 2009 at 12:06 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Thank you for quick response:
>
> ? ?LINK ? ? ? coreboot
> /usr/bin/ld: section .romstrap loaded at [00000000fffffff0,0000000100000043]
> overlaps section .reset loaded at [00000000fffffff0,00000000ffffffff]
> /usr/bin/ld: /mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot: section .romstrap
> vma 0xfffffff0 overlaps previous sections
> collect2: ld returned 1 exit status
> make: *** [/mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot] Error 1

    LINK       coreboot
    OBJCOPY    coreboot.bootblock
    CC         build/lib/version.o
    AR         coreboot.a
    CC         coreboot_ram.o
    CC         coreboot_ram
    PAYLOAD    none (as specified by user)

I didn't configure the build at all.  I just ran
./util/kbuildall/kbuildall asus/m2v-mx_se.

I'll help you track it down, but it works for me.

Thanks,
Myles



From rminnich at gmail.com  Thu Oct  1 20:15:32 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 11:15:32 -0700
Subject: [coreboot] [v2] r4701 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <1254417855.533.1.camel@tetris>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
Message-ID: <13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>

But I need to inlude the sse regiisters.

Here is a possibility

crt0-$(CONFIG_CPU_INTEL_P4) += ../../../../src/cpu/x86/sse/enable_sse.inc

that ok? I can put that in.

ron



From mylesgw at gmail.com  Thu Oct  1 20:17:41 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 12:17:41 -0600
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
Message-ID: <2831fecf0910011117v12a28258o5b5f1dadf26a0fcf@mail.gmail.com>

On Thu, Oct 1, 2009 at 12:13 PM, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Oct 1, 2009 at 12:06 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>> Thank you for quick response:
>>
>> ? ?LINK ? ? ? coreboot
>> /usr/bin/ld: section .romstrap loaded at [00000000fffffff0,0000000100000043]
>> overlaps section .reset loaded at [00000000fffffff0,00000000ffffffff]
>> /usr/bin/ld: /mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot: section .romstrap
>> vma 0xfffffff0 overlaps previous sections
>> collect2: ld returned 1 exit status
>> make: *** [/mnt/disc3/Moje_dilna/coreboot-v2/build/coreboot] Error 1
>
> ? ?LINK ? ? ? coreboot
> ? ?OBJCOPY ? ?coreboot.bootblock
> ? ?CC ? ? ? ? build/lib/version.o
> ? ?AR ? ? ? ? coreboot.a
> ? ?CC ? ? ? ? coreboot_ram.o
> ? ?CC ? ? ? ? coreboot_ram
> ? ?PAYLOAD ? ?none (as specified by user)
>
> I didn't configure the build at all. ?I just ran
> ./util/kbuildall/kbuildall asus/m2v-mx_se.

It looks like a dependency problem somewhere.  I replicated it.

Try
rm -rf build
make oldconfig
make

(make clean didn't do it for me)

Thanks,
Myles



From r.marek at assembler.cz  Thu Oct  1 20:19:26 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 01 Oct 2009 20:19:26 +0200
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
References: <4AC4EC08.8080507@assembler.cz>	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
Message-ID: <4AC4F2AE.5080704@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

Well I did just make clean which was not enough.

Thank you now the ROMSIP is there again

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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=VR9p
-----END PGP SIGNATURE-----



From uwe at hermann-uwe.de  Thu Oct  1 20:20:53 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Oct 2009 20:20:53 +0200
Subject: [coreboot] remove motorola PPC boards
In-Reply-To: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
References: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
Message-ID: <20091001182053.GE15511@greenwood>


> Get rid of the motorola PPC boards. They are long dead and they clutter 
> up the automatic build process with errors. Nobody cares about these.

Just for the record -- I will violently NACK any patches which remove
boards for the sole reason of "long dead", "old board", "vendor died",
or similar reasons.

This is pretty much the only exception as it's a PowerPC board and we
should indeed drop those, u-boot and others are way better suited
for this stuff.

But for pretty much all other boards, please do not attempt to remove
them. Thanks!


> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Don't forget to also remove target/motorola/* and target/totalimpact*.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From svn at coreboot.org  Thu Oct  1 20:23:28 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Thu,  1 Oct 2009 20:23:28 +0200
Subject: [coreboot] [v2] r4704 -
	trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
Message-ID: <mailman.3775.1355071626.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-10-01 20:23:28 +0200 (Thu, 01 Oct 2009)
New Revision: 4704

Modified:
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Makefile.inc
Log:
Add romstrap to asus/m2v-mx_se in Kconfig.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Rudolf Marek <r.marek at assembler.cz>


Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Makefile.inc	2009-10-01 16:51:36 UTC (rev 4703)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Makefile.inc	2009-10-01 18:23:28 UTC (rev 4704)
@@ -31,6 +31,7 @@
 initobj-y += crt0.o
 # FIXME in $(top)/Makefile
 crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/southbridge/via/k8t890/romstrap.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
 crt0-y += ../../../../src/arch/i386/lib/id.inc
@@ -39,6 +40,7 @@
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/southbridge/via/k8t890/romstrap.lds
 ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
 ldscript-y += ../../../../src/arch/i386/lib/id.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds




From mylesgw at gmail.com  Thu Oct  1 20:24:40 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 12:24:40 -0600
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <4AC4F2AE.5080704@assembler.cz>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
	<4AC4F2AE.5080704@assembler.cz>
Message-ID: <2831fecf0910011124x3bfe3b6ci97900801cfc34e7a@mail.gmail.com>

> Thank you now the ROMSIP is there again
I'm glad it was an easy fix :)

> Acked-by: Rudolf Marek <r.marek at assembler.cz>

Rev 4704.

Thanks,
Myles



From uwe at hermann-uwe.de  Thu Oct  1 20:29:08 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Oct 2009 20:29:08 +0200
Subject: [coreboot] [v2] r4701 -
 trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
Message-ID: <20091001182908.GF15511@greenwood>

On Thu, Oct 01, 2009 at 11:15:32AM -0700, ron minnich wrote:
> But I need to inlude the sse regiisters.
> 
> Here is a possibility
> 
> crt0-$(CONFIG_CPU_INTEL_P4) += ../../../../src/cpu/x86/sse/enable_sse.inc
> 
> that ok? I can put that in.

Here's what I did for GX1 support (patch not yet finished and not yet
submitted):

+ifeq ($(CONFIG_CPU_AMD_GX1),y)
+crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
+crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
+crt0-y += auto.inc
+else
 crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
 crt0-y += auto.inc
 crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+endif

Something similar can be done for SSE, probably with a kconfig
variable CONFIG_HAVE_SSE which is set (or not) per board or more
likely per chipset.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Thu Oct  1 20:37:36 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 11:37:36 -0700
Subject: [coreboot] remove motorola PPC boards
In-Reply-To: <20091001182053.GE15511@greenwood>
References: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
	<20091001182053.GE15511@greenwood>
Message-ID: <13426df10910011137h155933bfh124ddb1e59c52456@mail.gmail.com>

On Thu, Oct 1, 2009 at 11:20 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> Just for the record -- I will violently NACK any patches which remove
> boards for the sole reason of "long dead", "old board", "vendor died",
> or similar reasons.

ok. That said, if there is a board that might hold up progress because
it is very odd in some way, then it is a candiidate for removal.

I mainly started on the PPC because we have not had a maintainer in
years, and we have not had a tester in over 5 years. And I keep
getting warnings that they don't build.

>
> This is pretty much the only exception as it's a PowerPC board and we
> should indeed drop those, u-boot and others are way better suited
> for this stuff.


yes.

ron



From rminnich at gmail.com  Thu Oct  1 20:40:23 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 11:40:23 -0700
Subject: [coreboot] [v2] r4701 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <20091001182908.GF15511@greenwood>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
	<20091001182908.GF15511@greenwood>
Message-ID: <13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>

On Thu, Oct 1, 2009 at 11:29 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> +ifeq ($(CONFIG_CPU_AMD_GX1),y)
> +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
> +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
> +crt0-y += auto.inc

let's stick with the standard way of doing this. It makes any
automated tools easier.

crt0-$(CONFIG_CPU_AMD_GX1) += ./../../../src/cpu/amd/model_gx1/cpu_setup.inc
crt0-$(CONFIG_CPU_AMD_GX1) +=../../../../src/cpu/amd/model_gx1/gx_setup.inc

Pretty much all the crt0-y in that makefile should actually have
conditional variables if we really want to make it that general.

and so on.

thanks

ron



From info at coresystems.de  Thu Oct  1 20:46:22 2009
From: info at coresystems.de (coreboot information)
Date: Thu, 01 Oct 2009 20:46:22 +0200
Subject: [coreboot] build service results for r4704
Message-ID: <E1MtQfW-0000ih-Mu@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4704 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add romstrap to asus/m2v-mx_se in Kconfig.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Rudolf Marek <r.marek at assembler.cz>


Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4704&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4704&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2


If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From uwe at hermann-uwe.de  Thu Oct  1 20:59:32 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Thu, 1 Oct 2009 20:59:32 +0200
Subject: [coreboot] [v2] r4701 -
 trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
	<20091001182908.GF15511@greenwood>
	<13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>
Message-ID: <20091001185932.GE5738@greenwood>

On Thu, Oct 01, 2009 at 11:40:23AM -0700, ron minnich wrote:
> On Thu, Oct 1, 2009 at 11:29 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> 
> > +ifeq ($(CONFIG_CPU_AMD_GX1),y)
> > +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
> > +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
> > +crt0-y += auto.inc
> 
> let's stick with the standard way of doing this. It makes any
> automated tools easier.
> 
> crt0-$(CONFIG_CPU_AMD_GX1) += ./../../../src/cpu/amd/model_gx1/cpu_setup.inc
> crt0-$(CONFIG_CPU_AMD_GX1) +=../../../../src/cpu/amd/model_gx1/gx_setup.inc

In general, yes. But in the GX1 case I think it cannot be done this way
(but please correct me if I'm wrong), see full patch:


> +ifeq ($(CONFIG_CPU_AMD_GX1),y)
> +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
> +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
> +crt0-y += auto.inc
> +else
>  crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
>  crt0-y += auto.inc
>  crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
> +endif

In the GX1 case we need to include cpu_setup.inc, then gx_setup.inc,
then auto.inc. However, enable_mmx.inc and disable_mmx.inc must _not_
be included in the GX1 case. Hence the ifeq/else construct.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Thu Oct  1 21:03:37 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 12:03:37 -0700
Subject: [coreboot] [v2] r4701 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <20091001185932.GE5738@greenwood>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
	<20091001182908.GF15511@greenwood>
	<13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>
	<20091001185932.GE5738@greenwood>
Message-ID: <13426df10910011203v14ba4746k710ad205c879ae80@mail.gmail.com>

On Thu, Oct 1, 2009 at 11:59 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
> On Thu, Oct 01, 2009 at 11:40:23AM -0700, ron minnich wrote:
>> On Thu, Oct 1, 2009 at 11:29 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:
>>
>> > +ifeq ($(CONFIG_CPU_AMD_GX1),y)
>> > +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
>> > +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
>> > +crt0-y += auto.inc
>>
>> let's stick with the standard way of doing this. It makes any
>> automated tools easier.
>>
>> crt0-$(CONFIG_CPU_AMD_GX1) += ./../../../src/cpu/amd/model_gx1/cpu_setup.inc
>> crt0-$(CONFIG_CPU_AMD_GX1) +=../../../../src/cpu/amd/model_gx1/gx_setup.inc
>
> In general, yes. But in the GX1 case I think it cannot be done this way
> (but please correct me if I'm wrong), see full patch:
>
>
>> +ifeq ($(CONFIG_CPU_AMD_GX1),y)
>> +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
>> +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
>> +crt0-y += auto.inc
>> +else
>> ?crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
>> ?crt0-y += auto.inc
>> ?crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
>> +endif
>
> In the GX1 case we need to include cpu_setup.inc, then gx_setup.inc,
> then auto.inc. However, enable_mmx.inc and disable_mmx.inc must _not_
> be included in the GX1 case. Hence the ifeq/else construct.

I understand your point. You are correct about the mmx stuff. So what
must happen is that the mmx stuff must ALSO be conditional. Hence my
point, that
to make this Makefile completely general, we need to make ALL of the
crt0-y entries conditional.

thanks

ron



From r.marek at assembler.cz  Thu Oct  1 22:44:18 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 01 Oct 2009 22:44:18 +0200
Subject: [coreboot] [PATCH] update from revision guide for fam 0fh
Message-ID: <4AC514A2.6050108@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

New revision guide September 2009 3.46
Lets add some more CPUs.

I also checked the Errata which we dont handle:

89, 169, 254,  292, (238 no resume?)

284, 325 (no resume?), 342 requires mcode.

Btw where to get the microcode for the fam 0fh?

here seems to be just for fam10h

http://www.amd64.org/support/microcode.html


Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

(compile tested)

Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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From marcj303 at gmail.com  Thu Oct  1 22:52:55 2009
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 1 Oct 2009 14:52:55 -0600
Subject: [coreboot] Resend: [PATCH] add h8dmr fam10 target
In-Reply-To: <20090930144820.GA2980@countzero.vandewege.net>
References: <20090922131715.GA16574@countzero.vandewege.net>
	<20090922132906.22600.qmail@stuge.se>
	<20090930144820.GA2980@countzero.vandewege.net>
Message-ID: <534e5dc20910011352k3f96cdd9n8e179bc5469423fb@mail.gmail.com>

On Wed, Sep 30, 2009 at 8:48 AM, Ward Vandewege <ward at gnu.org> wrote:
> On Tue, Sep 22, 2009 at 03:29:05PM +0200, Peter Stuge wrote:
>> Ward Vandewege wrote:
>> > Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912
>> > fam10 and h8dmr k8 targets.
>> >
>> > Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
>> > this, and to Arne for doing the s2912 fam10 port.
>> >
>> > Build and boot tested.
>> >
>> > Signed-off-by: Ward Vandewege <ward at gnu.org>
>>
>> Acked-by: Peter Stuge <peter at stuge.se>
>
> r4693.
>
> Thanks,
> Ward.
>

Kudos for this port and check-in! Great to see Fam10 support expanding.

Marc




-- 
http://marcjonesconsulting.com



From joe at settoplinux.org  Fri Oct  2 00:04:46 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 18:04:46 -0400
Subject: [coreboot] serialice PCI capture
In-Reply-To: <4AC4B767.2060406@settoplinux.org>
References: <4AC4B767.2060406@settoplinux.org>
Message-ID: <8bbe928fcf1ce2928b0a1958f224d63f@imap.1and1.com>




On Thu, 01 Oct 2009 10:06:31 -0400, Joseph Smith <joe at settoplinux.org>
wrote:
> Just a thought. YABEL can capture PCI read/writes from an option ROM,
> how hard would it be to get serialice to do the same with the bios?
> 
> This would solve many of life's mysteries.....
> 

Hmm, it appears serialice has PCI access functions.... :-)
-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From rminnich at gmail.com  Fri Oct  2 00:12:37 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 15:12:37 -0700
Subject: [coreboot] patch: add config for MMX and SSE
Message-ID: <13426df10910011512h4234d07fna29d0a59914eeca9@mail.gmail.com>

attached

This would work, but if you have a better idea, just let us  know.

BTW, on another note: I think we should keep arch/whatever and
cpu/whatever, because The Day Is Coming when we'll need to run in
64-bit mode, if only to clear the memory.

ron
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From svn at coreboot.org  Fri Oct  2 00:34:19 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 00:34:19 +0200
Subject: [coreboot] [v2] r4705 - in trunk/coreboot-v2/src:
	cpu/intel/model_6fx northbridge/intel/i945
Message-ID: <mailman.3776.1355071626.16123.coreboot@coreboot.org>

Author: stuge
Date: 2009-10-02 00:34:18 +0200 (Fri, 02 Oct 2009)
New Revision: 4705

Modified:
   trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c
   trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c
Log:
Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts

Sorry, but I've forgotten where I found them. :\

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c	2009-10-01 18:23:28 UTC (rev 4704)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c	2009-10-01 22:34:18 UTC (rev 4705)
@@ -278,6 +278,7 @@
 	{ X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */
 	{ X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */
 	{ X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */
+	{ X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */
 	{ 0, 0 },
 };
 

Modified: trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c	2009-10-01 18:23:28 UTC (rev 4704)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c	2009-10-01 22:34:18 UTC (rev 4705)
@@ -44,6 +44,18 @@
 	case 3:
 		fsb = 667;
 		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
 	}
 
 	msr = rdmsr(0x198);




From r.marek at assembler.cz  Fri Oct  2 00:36:06 2009
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 02 Oct 2009 00:36:06 +0200
Subject: [coreboot] XMM stack
Message-ID: <4AC52ED6.3060003@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hello,

I made some fix for xmmstack.c found in SerialICE.

leal (%esp), %ecx


Its simple:

- --- old.c	2009-05-14 15:43:45.000000000 +0200
+++ xmmstack.c	2009-10-02 00:19:52.755673296 +0200
@@ -547,9 +547,23 @@ getxmml:\n\
             continue;
         }
 #endif
+
+   fprintf(w,"#%s #ORIG\n", buf);
+
+	/* leal is tricky */
+        if (regexp("^leal\\s+(\\d*)\\(\\%esp\\)\\s*,\\s*(.*)$",buf,len,find))
+        {
+            fprintf(w,"movl %%dr2,%%esp #NOSTACK\n");
+            fprintf(w,"%s\n",buf);
+            fprintf(w,"movl %%esp,%%dr2 #NOSTACK\n");
+            continue;
+        }
+

It makes things compile. Maybe there are other issues don't know.

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEUEARECAAYFAkrFLtYACgkQ3J9wPJqZRNUJoQCYpHICI6k4ZwECnwRrN/FDtEjm
1QCfUMWXts0lv7iH2W6n8dC7C9iNBKg=
=xgZx
-----END PGP SIGNATURE-----



From peter at stuge.se  Fri Oct  2 00:37:38 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 00:37:38 +0200
Subject: [coreboot] Rename ROM_IMAGE_SIZE to BOOTBLOCK_SIZE?
Message-ID: <20091001223739.17912.qmail@stuge.se>

Myles Watson wrote:
> 1. shrink your bootblock (CONFIG_ROM_IMAGE_SIZE)

Is this variable still around with Kconfig? How about the attached
patch? It has not been tested yet.


//Peter
-------------- next part --------------
Rename ROM_IMAGE_SIZE to BOOTBLOCK_SIZE

This was generated by:

grep -lr ROM_IMAGE_SIZE .|grep -v '/\.svn/'|xargs sed -i s,ROM_IMAGE_SIZE,BOOTBLOCK_SIZE,g

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: src/southbridge/via/k8t890/romstrap.lds
===================================================================
--- src/southbridge/via/k8t890/romstrap.lds	(revision 4704)
+++ src/southbridge/via/k8t890/romstrap.lds	(working copy)
@@ -22,7 +22,7 @@
 /* Modified for K8T890 ROM strap by Rudolf Marek <r.marek at assembler.cz>. */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
Index: src/southbridge/nvidia/ck804/romstrap.lds
===================================================================
--- src/southbridge/nvidia/ck804/romstrap.lds	(revision 4704)
+++ src/southbridge/nvidia/ck804/romstrap.lds	(working copy)
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
Index: src/southbridge/nvidia/ck804/id.inc
===================================================================
--- src/southbridge/nvidia/ck804/id.inc	(revision 4704)
+++ src/southbridge/nvidia/ck804/id.inc	(working copy)
@@ -8,7 +8,7 @@
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor       /* Reverse offset to the vendor ID */
 .long __id_end + 0x80 - part         /* Reverse offset to the part number */
-.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this ROM image */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_BOOTBLOCK_SIZE  /* Size of this ROM image */
 	.globl __id_end
 
 __id_end:
Index: src/southbridge/nvidia/ck804/id.lds
===================================================================
--- src/southbridge/nvidia/ck804/id.lds	(revision 4704)
+++ src/southbridge/nvidia/ck804/id.lds	(working copy)
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
Index: src/southbridge/nvidia/mcp55/romstrap.lds
===================================================================
--- src/southbridge/nvidia/mcp55/romstrap.lds	(revision 4704)
+++ src/southbridge/nvidia/mcp55/romstrap.lds	(working copy)
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
Index: src/southbridge/nvidia/mcp55/id.inc
===================================================================
--- src/southbridge/nvidia/mcp55/id.inc	(revision 4704)
+++ src/southbridge/nvidia/mcp55/id.inc	(working copy)
@@ -29,7 +29,7 @@
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_BOOTBLOCK_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
Index: src/southbridge/nvidia/mcp55/id.lds
===================================================================
--- src/southbridge/nvidia/mcp55/id.lds	(revision 4704)
+++ src/southbridge/nvidia/mcp55/id.lds	(working copy)
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
Index: src/southbridge/sis/sis966/romstrap.lds
===================================================================
--- src/southbridge/sis/sis966/romstrap.lds	(revision 4704)
+++ src/southbridge/sis/sis966/romstrap.lds	(working copy)
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
Index: src/southbridge/sis/sis966/id.inc
===================================================================
--- src/southbridge/sis/sis966/id.inc	(revision 4704)
+++ src/southbridge/sis/sis966/id.inc	(working copy)
@@ -29,7 +29,7 @@
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x80 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x80 - part    /* Reverse offset to the part number */
-.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_BOOTBLOCK_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
Index: src/southbridge/sis/sis966/id.lds
===================================================================
--- src/southbridge/sis/sis966/id.lds	(revision 4704)
+++ src/southbridge/sis/sis966/id.lds	(working copy)
@@ -20,7 +20,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x80) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
Index: src/cpu/x86/32bit/reset32.lds
===================================================================
--- src/cpu/x86/32bit/reset32.lds	(revision 4704)
+++ src/cpu/x86/32bit/reset32.lds	(working copy)
@@ -4,7 +4,7 @@
  */
 
 SECTIONS {
-	_ROMTOP = CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10;
+	_ROMTOP = CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x10;
 	. = _ROMTOP;
 	.reset (.): {
 		*(.reset)
Index: src/cpu/x86/16bit/reset16.lds
===================================================================
--- src/cpu/x86/16bit/reset16.lds	(revision 4704)
+++ src/cpu/x86/16bit/reset16.lds	(working copy)
@@ -5,7 +5,7 @@
 
 SECTIONS {
 	/* Trigger an error if I have an unuseable start address */
-	_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE");
+	_bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_BOOTBLOCK_SIZE");
 	_ROMTOP = 0xfffffff0;
 	. = _ROMTOP;
 	.reset . : {
Index: src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- src/mainboard/iwill/dk8_htx/Options.lb	(revision 4704)
+++ src/mainboard/iwill/dk8_htx/Options.lb	(working copy)
@@ -20,7 +20,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -107,7 +107,7 @@
 ##
 
 #FALLBACK: 256K-8K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 8K
 default CONFIG_FAILOVER_SIZE=0x02000
 
@@ -235,8 +235,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- src/mainboard/iwill/dk8s2/Options.lb	(revision 4704)
+++ src/mainboard/iwill/dk8s2/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -66,7 +66,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -136,8 +136,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- src/mainboard/iwill/dk8x/Options.lb	(revision 4704)
+++ src/mainboard/iwill/dk8x/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -66,7 +66,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -135,8 +135,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/axus/tc320/Options.lb
===================================================================
--- src/mainboard/axus/tc320/Options.lb	(revision 4704)
+++ src/mainboard/axus/tc320/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,8 +86,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
 default CONFIG_PIRQ_ROUTE = 1
 default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_USE_OPTION_TABLE = 0
Index: src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- src/mainboard/bcom/winnetp680/Options.lb	(revision 4704)
+++ src/mainboard/bcom/winnetp680/Options.lb	(working copy)
@@ -39,7 +39,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -83,8 +83,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 10
 default CONFIG_HAVE_ACPI_TABLES = 0
 default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
Index: src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- src/mainboard/bcom/winnet100/Options.lb	(revision 4704)
+++ src/mainboard/bcom/winnet100/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,8 +86,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
 default CONFIG_PIRQ_ROUTE = 1
 default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_USE_OPTION_TABLE = 0
Index: src/mainboard/televideo/tc7020/Options.lb
===================================================================
--- src/mainboard/televideo/tc7020/Options.lb	(revision 4704)
+++ src/mainboard/televideo/tc7020/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -87,8 +87,8 @@
 default CONFIG_HAVE_PIRQ_TABLE = 1
 default CONFIG_IRQ_SLOT_COUNT = 3	# Soldered NIC, internal USB, mini PCI slot
 default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_USE_OPTION_TABLE = 0
Index: src/mainboard/broadcom/blast/Options.lb
===================================================================
--- src/mainboard/broadcom/blast/Options.lb	(revision 4704)
+++ src/mainboard/broadcom/blast/Options.lb	(working copy)
@@ -16,7 +16,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -81,7 +81,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -168,8 +168,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/thomson/ip1000/Options.lb
===================================================================
--- src/mainboard/thomson/ip1000/Options.lb	(revision 4704)
+++ src/mainboard/thomson/ip1000/Options.lb	(working copy)
@@ -52,7 +52,7 @@
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_SIZE
@@ -66,9 +66,9 @@
 uses CONFIG_XIP_ROM_BASE
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default CONFIG_HAVE_PIRQ_TABLE = 1
Index: src/mainboard/supermicro/x6dai_g/Options.lb
===================================================================
--- src/mainboard/supermicro/x6dai_g/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/x6dai_g/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dmr/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/h8dmr/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -128,7 +128,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -251,8 +251,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0xf000
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 0xf000
 
 
 ##
Index: src/mainboard/supermicro/x6dhe_g/Options.lb
===================================================================
--- src/mainboard/supermicro/x6dhe_g/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/x6dhe_g/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dme/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/h8dme/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -135,7 +135,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -258,8 +258,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/supermicro/x6dhe_g2/Options.lb
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/x6dhe_g2/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/supermicro/h8dmr_fam10/Options.lb
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/h8dmr_fam10/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -131,7 +131,7 @@
 
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_BOOTBLOCK_SIZE
 default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
@@ -262,8 +262,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0x1e000
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 0x1e000
 
 ##
 ## Use a 32K stack
Index: src/mainboard/supermicro/x6dhr_ig/Options.lb
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/x6dhr_ig/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/supermicro/x6dhr_ig2/Options.lb
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/Options.lb	(revision 4704)
+++ src/mainboard/supermicro/x6dhr_ig2/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/Options.lb	(revision 4704)
+++ src/mainboard/soyo/sy-6ba-plus-iii/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/a-trend/atc-6240/Options.lb
===================================================================
--- src/mainboard/a-trend/atc-6240/Options.lb	(revision 4704)
+++ src/mainboard/a-trend/atc-6240/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/a-trend/atc-6220/Options.lb
===================================================================
--- src/mainboard/a-trend/atc-6220/Options.lb	(revision 4704)
+++ src/mainboard/a-trend/atc-6220/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- src/mainboard/kontron/986lcd-m/Options.lb	(revision 4704)
+++ src/mainboard/kontron/986lcd-m/Options.lb	(working copy)
@@ -44,7 +44,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 # Payload
@@ -219,7 +219,7 @@
 ##
 
 default CONFIG_XIP_ROM_SIZE = 128 * 1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_BOOTBLOCK_SIZE )
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -236,8 +236,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 0x10000
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 0x10000
 
 ##
 ## Use a small 32K stack
@@ -254,7 +254,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM
Index: src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- src/mainboard/gigabyte/m57sli/Options.lb	(revision 4704)
+++ src/mainboard/gigabyte/m57sli/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -134,7 +134,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -267,8 +267,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Options.lb	(revision 4704)
+++ src/mainboard/gigabyte/ga_2761gxdk/Options.lb	(working copy)
@@ -43,7 +43,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -133,7 +133,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -258,8 +258,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/Options.lb	(revision 4704)
+++ src/mainboard/gigabyte/ga-6bxc/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- src/mainboard/digitallogic/msm800sev/Options.lb	(revision 4704)
+++ src/mainboard/digitallogic/msm800sev/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -99,9 +99,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/digitallogic/adl855pc/Options.lb
===================================================================
--- src/mainboard/digitallogic/adl855pc/Options.lb	(revision 4704)
+++ src/mainboard/digitallogic/adl855pc/Options.lb	(working copy)
@@ -19,7 +19,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -83,9 +83,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/digitallogic/msm586seg/Options.lb
===================================================================
--- src/mainboard/digitallogic/msm586seg/Options.lb	(revision 4704)
+++ src/mainboard/digitallogic/msm586seg/Options.lb	(working copy)
@@ -20,7 +20,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -91,9 +91,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/motorola/sandpoint/Options.lb
===================================================================
--- src/mainboard/motorola/sandpoint/Options.lb	(revision 4704)
+++ src/mainboard/motorola/sandpoint/Options.lb	(working copy)
@@ -31,7 +31,7 @@
 uses CONFIG_AUTOBOOT_CMDLINE
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_RESET
 uses CONFIG_EXCEPTION_VECTORS
 uses CONFIG_ROMBASE
@@ -97,8 +97,8 @@
 default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
 # coreboot must fit into 128KB
-default CONFIG_ROM_IMAGE_SIZE=131072
-default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE}
+default CONFIG_BOOTBLOCK_SIZE=131072
+default CONFIG_ROM_SIZE={CONFIG_BOOTBLOCK_SIZE+CONFIG_PAYLOAD_SIZE}
 default CONFIG_PAYLOAD_SIZE=262144
 
 # Set stack and heap sizes (stage 2)
Index: src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb
===================================================================
--- src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	(revision 4704)
+++ src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb	(working copy)
@@ -28,7 +28,7 @@
 uses CONFIG_AUTOBOOT_CMDLINE
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_RESET
 uses CONFIG_EXCEPTION_VECTORS
 uses CONFIG_ROMBASE
@@ -94,7 +94,7 @@
 default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
 
 # coreboot must fit into 128KB
-default CONFIG_ROM_IMAGE_SIZE=160*1024
+default CONFIG_BOOTBLOCK_SIZE=160*1024
 default CONFIG_ROM_SIZE=384*1024
 default CONFIG_PAYLOAD_SIZE=262144
 
Index: src/mainboard/mitac/6513wu/Options.lb
===================================================================
--- src/mainboard/mitac/6513wu/Options.lb	(revision 4704)
+++ src/mainboard/mitac/6513wu/Options.lb	(working copy)
@@ -42,7 +42,7 @@
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_ROM_SECTION_OFFSET
@@ -74,8 +74,8 @@
 
 # ROM layout
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_ROM_PAYLOAD = 1
 default CONFIG_CBFS=1
Index: src/mainboard/emulation/qemu-x86/Config.lb
===================================================================
--- src/mainboard/emulation/qemu-x86/Config.lb	(revision 4704)
+++ src/mainboard/emulation/qemu-x86/Config.lb	(working copy)
@@ -5,14 +5,14 @@
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default CONFIG_ROM_SIZE = 256 * 1024 
-default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_ROM_SECTION_SIZE   = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SIZE - CONFIG_BOOTBLOCK_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
@@ -28,7 +28,7 @@
 ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
 default CONFIG_XIP_ROM_SIZE=32*1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE )
 
 ##
 ## Set all of the defaults for an x86 architecture
Index: src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- src/mainboard/emulation/qemu-x86/Options.lb	(revision 4704)
+++ src/mainboard/emulation/qemu-x86/Options.lb	(working copy)
@@ -21,7 +21,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -101,9 +101,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/olpc/btest/Options.lb
===================================================================
--- src/mainboard/olpc/btest/Options.lb	(revision 4704)
+++ src/mainboard/olpc/btest/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -87,9 +87,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/olpc/rev_a/Options.lb
===================================================================
--- src/mainboard/olpc/rev_a/Options.lb	(revision 4704)
+++ src/mainboard/olpc/rev_a/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -87,9 +87,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/technologic/ts5300/Options.lb
===================================================================
--- src/mainboard/technologic/ts5300/Options.lb	(revision 4704)
+++ src/mainboard/technologic/ts5300/Options.lb	(working copy)
@@ -20,7 +20,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -106,9 +106,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/pistachio/Options.lb
===================================================================
--- src/mainboard/amd/pistachio/Options.lb	(revision 4704)
+++ src/mainboard/amd/pistachio/Options.lb	(working copy)
@@ -37,7 +37,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -106,7 +106,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -201,8 +201,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- src/mainboard/amd/dbm690t/Options.lb	(revision 4704)
+++ src/mainboard/amd/dbm690t/Options.lb	(working copy)
@@ -37,7 +37,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -106,9 +106,9 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+#default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #256K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -203,8 +203,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/rumba/Options.lb
===================================================================
--- src/mainboard/amd/rumba/Options.lb	(revision 4704)
+++ src/mainboard/amd/rumba/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,9 +86,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- src/mainboard/amd/serengeti_cheetah/Options.lb	(revision 4704)
+++ src/mainboard/amd/serengeti_cheetah/Options.lb	(working copy)
@@ -20,7 +20,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -106,7 +106,7 @@
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
 
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
@@ -234,8 +234,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/norwich/Options.lb
===================================================================
--- src/mainboard/amd/norwich/Options.lb	(revision 4704)
+++ src/mainboard/amd/norwich/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -99,9 +99,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	(revision 4704)
+++ src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	(working copy)
@@ -39,7 +39,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -132,7 +132,7 @@
 ##
 
 #FALLBACK: 1024K - 8K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 8k
 default CONFIG_FAILOVER_SIZE=0x02000
 
@@ -270,8 +270,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/amd/db800/Options.lb
===================================================================
--- src/mainboard/amd/db800/Options.lb	(revision 4704)
+++ src/mainboard/amd/db800/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -99,9 +99,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/biostar/m6tba/Options.lb
===================================================================
--- src/mainboard/biostar/m6tba/Options.lb	(revision 4704)
+++ src/mainboard/biostar/m6tba/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/nec/powermate2000/Options.lb
===================================================================
--- src/mainboard/nec/powermate2000/Options.lb	(revision 4704)
+++ src/mainboard/nec/powermate2000/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -73,8 +73,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/azza/pt-6ibd/Options.lb
===================================================================
--- src/mainboard/azza/pt-6ibd/Options.lb	(revision 4704)
+++ src/mainboard/azza/pt-6ibd/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/rca/rm4100/Options.lb
===================================================================
--- src/mainboard/rca/rm4100/Options.lb	(revision 4704)
+++ src/mainboard/rca/rm4100/Options.lb	(working copy)
@@ -52,7 +52,7 @@
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_SIZE
@@ -66,9 +66,9 @@
 uses CONFIG_XIP_ROM_BASE
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_UDELAY_TSC = 1
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default CONFIG_HAVE_PIRQ_TABLE = 1
Index: src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- src/mainboard/iei/nova4899r/Options.lb	(revision 4704)
+++ src/mainboard/iei/nova4899r/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -96,9 +96,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/iei/pcisa-lx-800-r10/Options.lb
===================================================================
--- src/mainboard/iei/pcisa-lx-800-r10/Options.lb	(revision 4704)
+++ src/mainboard/iei/pcisa-lx-800-r10/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -84,8 +84,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 9
 default CONFIG_PIRQ_ROUTE = 1
 default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_DCACHE_RAM = 1
 default CONFIG_DCACHE_RAM_BASE = 0xc8000
 default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
Index: src/mainboard/iei/juki-511p/Config.lb
===================================================================
--- src/mainboard/iei/juki-511p/Config.lb	(revision 4704)
+++ src/mainboard/iei/juki-511p/Config.lb	(working copy)
@@ -8,7 +8,7 @@
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
@@ -24,7 +24,7 @@
 ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
 default CONFIG_XIP_ROM_SIZE=65536
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE )
 
 ##
 ## Set all of the defaults for an x86 architecture
Index: src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- src/mainboard/iei/juki-511p/Options.lb	(revision 4704)
+++ src/mainboard/iei/juki-511p/Options.lb	(working copy)
@@ -23,7 +23,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,9 +86,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- src/mainboard/hp/dl145_g3/Options.lb	(revision 4704)
+++ src/mainboard/hp/dl145_g3/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -121,7 +121,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_BOOTBLOCK_SIZE
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -235,8 +235,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2912/Options.lb
===================================================================
--- src/mainboard/tyan/s2912/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2912/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -131,7 +131,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -258,8 +258,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2850/Options.lb
===================================================================
--- src/mainboard/tyan/s2850/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2850/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -74,7 +74,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -152,8 +152,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2735/Options.lb
===================================================================
--- src/mainboard/tyan/s2735/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2735/Options.lb	(working copy)
@@ -16,7 +16,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -76,7 +76,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ###
 ### Build options
@@ -166,8 +166,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2880/Options.lb
===================================================================
--- src/mainboard/tyan/s2880/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2880/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -74,7 +74,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -152,8 +152,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2881/Options.lb
===================================================================
--- src/mainboard/tyan/s2881/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2881/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -79,7 +79,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -169,8 +169,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s1846/Options.lb
===================================================================
--- src/mainboard/tyan/s1846/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s1846/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -77,8 +77,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/tyan/s4880/Options.lb
===================================================================
--- src/mainboard/tyan/s4880/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s4880/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -78,7 +78,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -161,8 +161,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2891/Options.lb
===================================================================
--- src/mainboard/tyan/s2891/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2891/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -88,7 +88,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ###
 ### Build options
@@ -208,8 +208,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2882/Options.lb
===================================================================
--- src/mainboard/tyan/s2882/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2882/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -74,7 +74,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -152,8 +152,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2892/Options.lb
===================================================================
--- src/mainboard/tyan/s2892/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2892/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -82,7 +82,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ###
 ### Build options
@@ -196,8 +196,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s4882/Options.lb
===================================================================
--- src/mainboard/tyan/s4882/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s4882/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -78,7 +78,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -160,8 +160,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2875/Options.lb
===================================================================
--- src/mainboard/tyan/s2875/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2875/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -74,7 +74,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 
 ##
@@ -153,8 +153,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2885/Options.lb
===================================================================
--- src/mainboard/tyan/s2885/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2885/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -85,7 +85,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -179,8 +179,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2895/Options.lb
===================================================================
--- src/mainboard/tyan/s2895/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2895/Options.lb	(working copy)
@@ -17,7 +17,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -93,7 +93,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -215,8 +215,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- src/mainboard/tyan/s2912_fam10/Options.lb	(revision 4704)
+++ src/mainboard/tyan/s2912_fam10/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -134,7 +134,7 @@
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
 
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
@@ -267,8 +267,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- src/mainboard/artecgroup/dbe61/Options.lb	(revision 4704)
+++ src/mainboard/artecgroup/dbe61/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -99,9 +99,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- src/mainboard/pcengines/alix1c/Options.lb	(revision 4704)
+++ src/mainboard/pcengines/alix1c/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -117,9 +117,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- src/mainboard/asi/mb_5blgp/Options.lb	(revision 4704)
+++ src/mainboard/asi/mb_5blgp/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,8 +86,8 @@
 default CONFIG_HAVE_OPTION_TABLE = 0
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_USE_OPTION_TABLE = 0
Index: src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- src/mainboard/asi/mb_5blmp/Options.lb	(revision 4704)
+++ src/mainboard/asi/mb_5blmp/Options.lb	(working copy)
@@ -15,7 +15,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -83,9 +83,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/via/epia-m700/Options.lb
===================================================================
--- src/mainboard/via/epia-m700/Options.lb	(revision 4704)
+++ src/mainboard/via/epia-m700/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -123,8 +123,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 13
 default CONFIG_HAVE_ACPI_TABLES = 1
 default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
 default CONFIG_STACK_SIZE = 16 * 1024
 default CONFIG_HEAP_SIZE = 20 * 1024
Index: src/mainboard/via/vt8454c/Options.lb
===================================================================
--- src/mainboard/via/vt8454c/Options.lb	(revision 4704)
+++ src/mainboard/via/vt8454c/Options.lb	(working copy)
@@ -40,7 +40,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 
@@ -156,9 +156,9 @@
 ### LinuxBIOS layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow linuxBIOS to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/via/epia-m/Options.lb
===================================================================
--- src/mainboard/via/epia-m/Options.lb	(revision 4704)
+++ src/mainboard/via/epia-m/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -99,9 +99,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/via/epia-n/Options.lb
===================================================================
--- src/mainboard/via/epia-n/Options.lb	(revision 4704)
+++ src/mainboard/via/epia-n/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -96,11 +96,11 @@
 default CONFIG_IRQ_SLOT_COUNT = 7
 default CONFIG_HAVE_ACPI_TABLES = 1
 default CONFIG_HAVE_OPTION_TABLE = 1
-#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
+#default CONFIG_BOOTBLOCK_SIZE = 67 * 1024
 #default CONFIG_PAYLOAD_SIZE = 125 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 default CONFIG_PAYLOAD_SIZE = 256 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
Index: src/mainboard/via/epia-cn/Options.lb
===================================================================
--- src/mainboard/via/epia-cn/Options.lb	(revision 4704)
+++ src/mainboard/via/epia-cn/Options.lb	(working copy)
@@ -39,7 +39,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -84,8 +84,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 9
 default CONFIG_HAVE_ACPI_TABLES = 0
 default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
Index: src/mainboard/via/epia/Options.lb
===================================================================
--- src/mainboard/via/epia/Options.lb	(revision 4704)
+++ src/mainboard/via/epia/Options.lb	(working copy)
@@ -27,7 +27,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -109,9 +109,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/via/pc2500e/Options.lb
===================================================================
--- src/mainboard/via/pc2500e/Options.lb	(revision 4704)
+++ src/mainboard/via/pc2500e/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
@@ -73,8 +73,8 @@
 uses CONFIG_IOAPIC
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_IOAPIC = 0
 default CONFIG_VIDEO_MB = 32
 default CONFIG_CONSOLE_SERIAL8250 = 1
Index: src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- src/mainboard/lippert/roadrunner-lx/Options.lb	(revision 4704)
+++ src/mainboard/lippert/roadrunner-lx/Options.lb	(working copy)
@@ -45,7 +45,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -127,9 +127,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/lippert/frontrunner/Options.lb
===================================================================
--- src/mainboard/lippert/frontrunner/Options.lb	(revision 4704)
+++ src/mainboard/lippert/frontrunner/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,9 +86,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/lippert/spacerunner-lx/Options.lb
===================================================================
--- src/mainboard/lippert/spacerunner-lx/Options.lb	(revision 4704)
+++ src/mainboard/lippert/spacerunner-lx/Options.lb	(working copy)
@@ -45,7 +45,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -127,9 +127,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## enable CACHE_AS_RAM specifics
Index: src/mainboard/abit/be6-ii_v2_0/Options.lb
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/Options.lb	(revision 4704)
+++ src/mainboard/abit/be6-ii_v2_0/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -77,8 +77,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	(revision 4704)
+++ src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/dell/s1850/Options.lb
===================================================================
--- src/mainboard/dell/s1850/Options.lb	(revision 4704)
+++ src/mainboard/dell/s1850/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -129,8 +129,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 
 ##
 ## Use a small 8K stack
@@ -147,7 +147,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/msi/ms7135/Options.lb
===================================================================
--- src/mainboard/msi/ms7135/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms7135/Options.lb	(working copy)
@@ -39,7 +39,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -112,7 +112,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=(4*1024)
@@ -227,8 +227,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/msi/ms6119/Options.lb
===================================================================
--- src/mainboard/msi/ms6119/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms6119/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/msi/ms6147/Options.lb
===================================================================
--- src/mainboard/msi/ms6147/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms6147/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/msi/ms9282/Options.lb
===================================================================
--- src/mainboard/msi/ms9282/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms9282/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -112,7 +112,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ###
 ### Build options
@@ -216,8 +216,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/msi/ms6178/Options.lb
===================================================================
--- src/mainboard/msi/ms6178/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms6178/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -75,8 +75,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/msi/ms9185/Options.lb
===================================================================
--- src/mainboard/msi/ms9185/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms9185/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -118,7 +118,7 @@
 
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -236,8 +236,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/msi/ms7260/Options.lb
===================================================================
--- src/mainboard/msi/ms7260/Options.lb	(revision 4704)
+++ src/mainboard/msi/ms7260/Options.lb	(working copy)
@@ -37,7 +37,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -101,7 +101,7 @@
 uses CONFIG_USE_PRINTK_IN_CAR
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_FAILOVER_SIZE = 4 * 1024
 default CONFIG_LB_MEM_TOPK = 2048	# 1MB more for pgtbl.
 default CONFIG_HAVE_FALLBACK_BOOT = 1
@@ -169,7 +169,7 @@
 default CONFIG_MAINBOARD_VENDOR = "MSI"
 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 default CONFIG_STACK_SIZE = 0x2000
 default CONFIG_HEAP_SIZE = 0x8000
 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
Index: src/mainboard/arima/hdama/Options.lb
===================================================================
--- src/mainboard/arima/hdama/Options.lb	(revision 4704)
+++ src/mainboard/arima/hdama/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -76,7 +76,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -150,8 +150,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- src/mainboard/sunw/ultra40/Options.lb	(revision 4704)
+++ src/mainboard/sunw/ultra40/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -82,7 +82,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ###
 ### Build options
@@ -184,8 +184,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- src/mainboard/advantech/pcm-5820/Options.lb	(revision 4704)
+++ src/mainboard/advantech/pcm-5820/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -86,8 +86,8 @@
 default CONFIG_HAVE_OPTION_TABLE = 0
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_USE_OPTION_TABLE = 0
Index: src/mainboard/embeddedplanet/ep405pc/Options.lb
===================================================================
--- src/mainboard/embeddedplanet/ep405pc/Options.lb	(revision 4704)
+++ src/mainboard/embeddedplanet/ep405pc/Options.lb	(working copy)
@@ -34,7 +34,7 @@
 #uses CONFIG_IDE_SWAB
 uses CONFIG_IDE_OFFSET 
 uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_RESET
 uses CONFIG_EXCEPTION_VECTORS
 uses CONFIG_ROMBASE
@@ -106,7 +106,7 @@
 default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
 
 default CONFIG_ROM_SIZE=1048576
-default CONFIG_ROM_IMAGE_SIZE=160*1024
+default CONFIG_BOOTBLOCK_SIZE=160*1024
 
 ## Board has fixed size RAM
 default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
Index: src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- src/mainboard/eaglelion/5bcm/Options.lb	(revision 4704)
+++ src/mainboard/eaglelion/5bcm/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -89,9 +89,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/newisys/khepri/Options.lb
===================================================================
--- src/mainboard/newisys/khepri/Options.lb	(revision 4704)
+++ src/mainboard/newisys/khepri/Options.lb	(working copy)
@@ -14,7 +14,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -73,7 +73,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -151,8 +151,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- src/mainboard/jetway/j7f24/Options.lb	(revision 4704)
+++ src/mainboard/jetway/j7f24/Options.lb	(working copy)
@@ -39,7 +39,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -84,8 +84,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 10
 default CONFIG_HAVE_ACPI_TABLES = 0
 default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
Index: src/mainboard/technexion/tim8690/Options.lb
===================================================================
--- src/mainboard/technexion/tim8690/Options.lb	(revision 4704)
+++ src/mainboard/technexion/tim8690/Options.lb	(working copy)
@@ -37,7 +37,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -106,7 +106,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -202,8 +202,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/ibm/e326/Options.lb
===================================================================
--- src/mainboard/ibm/e326/Options.lb	(revision 4704)
+++ src/mainboard/ibm/e326/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -67,7 +67,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -140,8 +140,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/ibm/e325/Options.lb
===================================================================
--- src/mainboard/ibm/e325/Options.lb	(revision 4704)
+++ src/mainboard/ibm/e325/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -65,7 +65,7 @@
 ##
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Build code for the fallback boot
@@ -134,8 +134,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- src/mainboard/nvidia/l1_2pvv/Options.lb	(revision 4704)
+++ src/mainboard/nvidia/l1_2pvv/Options.lb	(working copy)
@@ -41,7 +41,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -131,7 +131,7 @@
 ##
 
 #FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 #FAILOVER: 4K
 default CONFIG_FAILOVER_SIZE=0x01000
 
@@ -256,8 +256,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536 - CONFIG_FAILOVER_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- src/mainboard/intel/xe7501devkit/Options.lb	(revision 4704)
+++ src/mainboard/intel/xe7501devkit/Options.lb	(working copy)
@@ -54,7 +54,7 @@
 ## These are defined in target Config.lb, don't add here
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_FALLBACK_SIZE
 uses COREBOOT_EXTRA_VERSION
 
@@ -73,13 +73,13 @@
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
 default CONFIG_ROM_SIZE=2097152
-default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Build code for the fallback boot?
 ##
 default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 
 ## Delay timer options
Index: src/mainboard/intel/truxton/Options.lb
===================================================================
--- src/mainboard/intel/truxton/Options.lb	(revision 4704)
+++ src/mainboard/intel/truxton/Options.lb	(working copy)
@@ -31,7 +31,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -134,8 +134,8 @@
 ### Coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -152,7 +152,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM
Index: src/mainboard/intel/mtarvon/Options.lb
===================================================================
--- src/mainboard/intel/mtarvon/Options.lb	(revision 4704)
+++ src/mainboard/intel/mtarvon/Options.lb	(working copy)
@@ -31,7 +31,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -132,8 +132,8 @@
 ### Coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -150,7 +150,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM
Index: src/mainboard/intel/eagleheights/Options.lb
===================================================================
--- src/mainboard/intel/eagleheights/Options.lb	(revision 4704)
+++ src/mainboard/intel/eagleheights/Options.lb	(working copy)
@@ -43,7 +43,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 # Payload
@@ -228,8 +228,8 @@
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -246,7 +246,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE=CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM
Index: src/mainboard/intel/jarrell/Options.lb
===================================================================
--- src/mainboard/intel/jarrell/Options.lb	(revision 4704)
+++ src/mainboard/intel/jarrell/Options.lb	(working copy)
@@ -13,7 +13,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -143,8 +143,8 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
 
 ##
 ## Use a small 8K stack
@@ -161,7 +161,7 @@
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Coreboot C code runs at this location in RAM
Index: src/mainboard/asus/mew-am/Options.lb
===================================================================
--- src/mainboard/asus/mew-am/Options.lb	(revision 4704)
+++ src/mainboard/asus/mew-am/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/p2b/Options.lb
===================================================================
--- src/mainboard/asus/p2b/Options.lb	(revision 4704)
+++ src/mainboard/asus/p2b/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -77,8 +77,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/p2b-d/Options.lb
===================================================================
--- src/mainboard/asus/p2b-d/Options.lb	(revision 4704)
+++ src/mainboard/asus/p2b-d/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -80,8 +80,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/p2b-f/Options.lb
===================================================================
--- src/mainboard/asus/p2b-f/Options.lb	(revision 4704)
+++ src/mainboard/asus/p2b-f/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- src/mainboard/asus/a8v-e_se/Options.lb	(revision 4704)
+++ src/mainboard/asus/a8v-e_se/Options.lb	(working copy)
@@ -33,7 +33,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -95,7 +95,7 @@
 uses CONFIG_USE_PRINTK_IN_CAR
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_HAVE_HARD_RESET = 0
 default CONFIG_HAVE_PIRQ_TABLE = 0
@@ -148,7 +148,7 @@
 default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
 # default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 256 * 1024
 # More 1M for pgtbl.
Index: src/mainboard/asus/p3b-f/Options.lb
===================================================================
--- src/mainboard/asus/p3b-f/Options.lb	(revision 4704)
+++ src/mainboard/asus/p3b-f/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -76,8 +76,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/p2b-ds/Options.lb
===================================================================
--- src/mainboard/asus/p2b-ds/Options.lb	(revision 4704)
+++ src/mainboard/asus/p2b-ds/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -80,8 +80,8 @@
 default CONFIG_IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
 default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 36 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_STACK_SIZE = 8 * 1024
 default CONFIG_HEAP_SIZE = 16 * 1024
 default CONFIG_HAVE_OPTION_TABLE = 0
Index: src/mainboard/asus/mew-vm/Options.lb
===================================================================
--- src/mainboard/asus/mew-vm/Options.lb	(revision 4704)
+++ src/mainboard/asus/mew-vm/Options.lb	(working copy)
@@ -18,7 +18,7 @@
 uses CONFIG_HEAP_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
@@ -83,9 +83,9 @@
 ### coreboot layout values
 ###
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_BOOTBLOCK_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 ##
 ## Use a small 8K stack
Index: src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- src/mainboard/asus/a8n_e/Options.lb	(revision 4704)
+++ src/mainboard/asus/a8n_e/Options.lb	(working copy)
@@ -38,7 +38,7 @@
 uses CONFIG_FAILOVER_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -100,8 +100,8 @@
 uses CONFIG_USE_PRINTK_IN_CAR
 
 default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 default CONFIG_FAILOVER_SIZE = 4 * 1024
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_HAVE_FAILOVER_BOOT = 1
Index: src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- src/mainboard/asus/m2v-mx_se/Options.lb	(revision 4704)
+++ src/mainboard/asus/m2v-mx_se/Options.lb	(working copy)
@@ -33,7 +33,7 @@
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
@@ -174,8 +174,8 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
+default CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 #
 # CBFS
 #
Index: src/config/nofailovercalculation.lb
===================================================================
--- src/config/nofailovercalculation.lb	(revision 4704)
+++ src/config/nofailovercalculation.lb	(working copy)
@@ -19,7 +19,7 @@
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
@@ -34,4 +34,4 @@
 ## CONFIG_XIP_ROM_SIZE must be a power of 2 and is set in mainboard Config.lb
 ## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
 ##
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_BOOTBLOCK_SIZE )
Index: src/config/failovercalculation.lb
===================================================================
--- src/config/failovercalculation.lb	(revision 4704)
+++ src/config/failovercalculation.lb	(working copy)
@@ -24,7 +24,7 @@
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
+default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
@@ -41,12 +41,12 @@
 ##
 
 if CONFIG_USE_FAILOVER_IMAGE
-	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_BOOTBLOCK_SIZE)
 else
     if CONFIG_USE_FALLBACK_IMAGE
-	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE + CONFIG_FAILOVER_SIZE)
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_BOOTBLOCK_SIZE + CONFIG_FAILOVER_SIZE)
     else
-	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE)
+	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_BOOTBLOCK_SIZE)
     end
 end
 
Index: src/config/Options.lb
===================================================================
--- src/config/Options.lb	(revision 4704)
+++ src/config/Options.lb	(working copy)
@@ -228,7 +228,7 @@
 	export used
 	comment "Size of your ROM"
 end
-define CONFIG_ROM_IMAGE_SIZE
+define CONFIG_BOOTBLOCK_SIZE
 	default 65535
 	format "0x%x"
 	export always
@@ -247,7 +247,7 @@
 	comment "Default rom section offset"
 end
 define CONFIG_PAYLOAD_SIZE
-	default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE}
+	default {CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE}
 	format "0x%x"
 	export always
 	comment "Default payload size"
Index: src/northbridge/via/vx800/romstrap.lds
===================================================================
--- src/northbridge/via/vx800/romstrap.lds	(revision 4704)
+++ src/northbridge/via/vx800/romstrap.lds	(working copy)
@@ -19,7 +19,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
 	.romstrap (.): {
 		*(.romstrap)
 	}
Index: src/arch/i386/Kconfig
===================================================================
--- src/arch/i386/Kconfig	(revision 4704)
+++ src/arch/i386/Kconfig	(working copy)
@@ -41,7 +41,7 @@
 	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
 	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
 
-config ROM_IMAGE_SIZE
+config BOOTBLOCK_SIZE
 	hex
 	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
 	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
Index: src/arch/i386/Config.lb
===================================================================
--- src/arch/i386/Config.lb	(revision 4704)
+++ src/arch/i386/Config.lb	(working copy)
@@ -105,7 +105,7 @@
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
+		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_BOOTBLOCK_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
 		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
 	end
 end
Index: src/arch/i386/init/ldscript_fallback.lb
===================================================================
--- src/arch/i386/init/ldscript_fallback.lb	(revision 4704)
+++ src/arch/i386/init/ldscript_fallback.lb	(working copy)
@@ -45,7 +45,7 @@
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_BOOTBLOCK_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_BOOTBLOCK_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
===================================================================
--- src/arch/i386/init/ldscript_fallback_cbfs.lb	(revision 4704)
+++ src/arch/i386/init/ldscript_fallback_cbfs.lb	(working copy)
@@ -38,7 +38,7 @@
 
 	/* cut _start into last 64k*/
 	_x = .;
-	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
+	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_BOOTBLOCK_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_BOOTBLOCK_SIZE) : _x;
 
 	/* This section might be better named .setup */
 	.rom . : {
Index: src/arch/i386/lib/id.inc
===================================================================
--- src/arch/i386/lib/id.inc	(revision 4704)
+++ src/arch/i386/lib/id.inc	(working copy)
@@ -8,7 +8,7 @@
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_BOOTBLOCK_SIZE  /* Size of this romimage */
 	.globl __id_end
 
 __id_end:
Index: src/arch/i386/lib/id.lds
===================================================================
--- src/arch/i386/lib/id.lds	(revision 4704)
+++ src/arch/i386/lib/id.lds	(working copy)
@@ -1,5 +1,5 @@
 SECTIONS {
-	. = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start);
+	. = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - 0x10) - (__id_end - __id_start);
 	.id (.): {
 		*(.id)
 	}
Index: documentation/LinuxBIOS-AMD64.tex
===================================================================
--- documentation/LinuxBIOS-AMD64.tex	(revision 4704)
+++ documentation/LinuxBIOS-AMD64.tex	(working copy)
@@ -286,7 +286,7 @@
 All local configuration variables have to be declared before they can be
 used. Example:
 \begin{verbatim}
-        uses CONFIG_ROM_IMAGE_SIZE
+        uses CONFIG_BOOTBLOCK_SIZE
 \end{verbatim}
 
 \textbf{NOTE:} Only configuration variables known to the configuration
@@ -303,7 +303,7 @@
 Example:
 
 \begin{verbatim}
-        default CONFIG_ROM_IMAGE_SIZE=0x10000
+        default CONFIG_BOOTBLOCK_SIZE=0x10000
 \end{verbatim}
 
 It is also possible to assign the value of one configuration variable to
@@ -366,7 +366,7 @@
 \begin{verbatim}
 romimage "normal"
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=0x10000
+        option CONFIG_BOOTBLOCK_SIZE=0x10000
         option COREBOOT_EXTRA_VERSION=".0Normal"
         mainboard amd/solo
         payload /suse/stepan/tg3ide_
@@ -460,7 +460,7 @@
 
 Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
 
-\item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim}
+\item \begin{verbatim}CONFIG_BOOTBLOCK_SIZE\end{verbatim}
 
 Default image size. Defaults to \texttt{65535} bytes.
 
@@ -1773,7 +1773,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover"
 end
Index: documentation/RFC/config.tex
===================================================================
--- documentation/RFC/config.tex	(revision 4704)
+++ documentation/RFC/config.tex	(working copy)
@@ -261,7 +261,7 @@
 #
 ### The linuxBIOS bootloader.
 ###
-option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE)
 option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 #
 
@@ -275,7 +275,7 @@
 export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
 export CONFIG_ARCH:=i386
 export CONFIG_RAMBASE:=0x4000
-export CONFIG_ROM_IMAGE_SIZE:=65535
+export CONFIG_BOOTBLOCK_SIZE:=65535
 export CONFIG_PAYLOAD_SIZE:=131073
 export CONFIG_MAX_CPUS:=1
 export CONFIG_HEAP_SIZE:=8192
Index: targets/iwill/dk8_htx/Config-abuild.lb
===================================================================
--- targets/iwill/dk8_htx/Config-abuild.lb	(revision 4704)
+++ targets/iwill/dk8_htx/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/iwill/dk8_htx/Config.lb
===================================================================
--- targets/iwill/dk8_htx/Config.lb	(revision 4704)
+++ targets/iwill/dk8_htx/Config.lb	(working copy)
@@ -12,10 +12,10 @@
 #        option CONFIG_ROM_SIZE = 458752 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -38,10 +38,10 @@
 romimage "fallback" 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -65,7 +65,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/iwill/dk8s2/Config.lb
===================================================================
--- targets/iwill/dk8s2/Config.lb	(revision 4704)
+++ targets/iwill/dk8s2/Config.lb	(working copy)
@@ -63,8 +63,8 @@
 #option CONFIG_FALLBACK_SIZE=98304
 option CONFIG_FALLBACK_SIZE=131072
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+option CONFIG_BOOTBLOCK_SIZE=65536
  
 
 ###
@@ -133,14 +133,14 @@
 	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
 	option CONFIG_ROM_SECTION_OFFSET= 0
 
-	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE)
 	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 	option CONFIG_ROMBASE      = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
 
 #	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
         option CONFIG_XIP_ROM_SIZE = 65536
 
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
+	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE)
 
 	payload /usr/src/filo-0.4.1_btext/filo.elf
 #	payload /usr/src/filo-0.4.2/filo.elf
@@ -152,13 +152,13 @@
 	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
 	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
 
-	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE)
 	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 	option CONFIG_ROMBASE      = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
 
 #	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
 	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
+	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE)
 
 	payload ../../../payloads/filo.elf
 #	payload /usr/src/filo-0.4.2/filo.elf
Index: targets/iwill/dk8x/Config.lb
===================================================================
--- targets/iwill/dk8x/Config.lb	(revision 4704)
+++ targets/iwill/dk8x/Config.lb	(working copy)
@@ -63,8 +63,8 @@
 #option CONFIG_FALLBACK_SIZE=98304
 option CONFIG_FALLBACK_SIZE=131072
 
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
+## CONFIG_BOOTBLOCK_SIZE is the amount of space to allow coreboot to occupy.
+option CONFIG_BOOTBLOCK_SIZE=65536
  
 
 ###
@@ -133,14 +133,14 @@
 	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
 	option CONFIG_ROM_SECTION_OFFSET= 0
 
-	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE)
 	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 	option CONFIG_ROMBASE      = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
 
 #	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
         option CONFIG_XIP_ROM_SIZE = 65536
 
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
+	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE)
 
 	payload /usr/src/filo-0.4.1_btext/filo.elf
 #	payload /usr/src/filo-0.4.2/filo.elf
@@ -152,13 +152,13 @@
 	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
 	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
 
-	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+	option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_BOOTBLOCK_SIZE)
 	option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 	option CONFIG_ROMBASE      = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE)
 
 #	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
 	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
+	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_BOOTBLOCK_SIZE - CONFIG_XIP_ROM_SIZE)
 
 	payload ../../../payloads/filo.elf
 #	payload /usr/src/filo-0.4.2/filo.elf
Index: targets/bcom/winnetp680/Config-abuild.lb
===================================================================
--- targets/bcom/winnetp680/Config-abuild.lb	(revision 4704)
+++ targets/bcom/winnetp680/Config-abuild.lb	(working copy)
@@ -14,7 +14,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/bcom/winnet100/Config.lb
===================================================================
--- targets/bcom/winnet100/Config.lb	(revision 4704)
+++ targets/bcom/winnet100/Config.lb	(working copy)
@@ -38,14 +38,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Normal"
 	payload ../../../../../../../images/etherboot.elf
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 	payload ../../../../../../../images/etherboot.elf
 end
Index: targets/televideo/tc7020/Config.lb
===================================================================
--- targets/televideo/tc7020/Config.lb	(revision 4704)
+++ targets/televideo/tc7020/Config.lb	(working copy)
@@ -36,14 +36,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Normal"
 	payload /tmp/filo.elf
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 	payload /tmp/filo.elf
 end
Index: targets/broadcom/blast/Config.lb
===================================================================
--- targets/broadcom/blast/Config.lb	(revision 4704)
+++ targets/broadcom/blast/Config.lb	(working copy)
@@ -13,10 +13,10 @@
 #       64K for Etherboot
 #       option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -38,10 +38,10 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/supermicro/h8dmr/Config-abuild.lb
===================================================================
--- targets/supermicro/h8dmr/Config-abuild.lb	(revision 4704)
+++ targets/supermicro/h8dmr/Config-abuild.lb	(working copy)
@@ -23,7 +23,7 @@
 
 romimage "failover"
   option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
   option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
Index: targets/supermicro/h8dmr/Config.lb.kernel
===================================================================
--- targets/supermicro/h8dmr/Config.lb.kernel	(revision 4704)
+++ targets/supermicro/h8dmr/Config.lb.kernel	(working copy)
@@ -30,10 +30,10 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x18000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -65,7 +65,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dmr/Config.lb
===================================================================
--- targets/supermicro/h8dmr/Config.lb	(revision 4704)
+++ targets/supermicro/h8dmr/Config.lb	(working copy)
@@ -35,7 +35,7 @@
 
 romimage "failover"
   option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
   option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
Index: targets/supermicro/h8dmr/Config-lab.lb
===================================================================
--- targets/supermicro/h8dmr/Config-lab.lb	(revision 4704)
+++ targets/supermicro/h8dmr/Config-lab.lb	(working copy)
@@ -31,7 +31,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
+	option CONFIG_BOOTBLOCK_SIZE=0x18000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
@@ -40,7 +40,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dme/Config-abuild.lb
===================================================================
--- targets/supermicro/h8dme/Config-abuild.lb	(revision 4704)
+++ targets/supermicro/h8dme/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION=".0-failover"
 end
Index: targets/supermicro/h8dme/Config.lb.kernel
===================================================================
--- targets/supermicro/h8dme/Config.lb.kernel	(revision 4704)
+++ targets/supermicro/h8dme/Config.lb.kernel	(working copy)
@@ -27,7 +27,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
+	option CONFIG_BOOTBLOCK_SIZE=0x18000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 
@@ -36,7 +36,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dme/Config.lb
===================================================================
--- targets/supermicro/h8dme/Config.lb	(revision 4704)
+++ targets/supermicro/h8dme/Config.lb	(working copy)
@@ -22,7 +22,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 	payload ../payload.elf
@@ -31,7 +31,7 @@
 romimage "fallback"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf
@@ -40,7 +40,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dme/Config-lab.lb
===================================================================
--- targets/supermicro/h8dme/Config-lab.lb	(revision 4704)
+++ targets/supermicro/h8dme/Config-lab.lb	(working copy)
@@ -28,7 +28,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x18000
+	option CONFIG_BOOTBLOCK_SIZE=0x18000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
@@ -37,7 +37,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dmr_fam10/Config-abuild.lb
===================================================================
--- targets/supermicro/h8dmr_fam10/Config-abuild.lb	(revision 4704)
+++ targets/supermicro/h8dmr_fam10/Config-abuild.lb	(working copy)
@@ -23,7 +23,7 @@
 
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
Index: targets/supermicro/h8dmr_fam10/Config.lb.kernel
===================================================================
--- targets/supermicro/h8dmr_fam10/Config.lb.kernel	(revision 4704)
+++ targets/supermicro/h8dmr_fam10/Config.lb.kernel	(working copy)
@@ -30,10 +30,10 @@
 	option USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x18000
-#	option ROM_IMAGE_SIZE=0x15800
-#	option ROM_IMAGE_SIZE=0x13800
+#	option BOOTBLOCK_SIZE=0x19800
+	option BOOTBLOCK_SIZE=0x18000
+#	option BOOTBLOCK_SIZE=0x15800
+#	option BOOTBLOCK_SIZE=0x13800
 	option XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -65,7 +65,7 @@
 romimage "failover"
 	option USE_FAILOVER_IMAGE=1
         option USE_FALLBACK_IMAGE=0
-        option ROM_IMAGE_SIZE=FAILOVER_SIZE
+        option BOOTBLOCK_SIZE=FAILOVER_SIZE
         option XIP_ROM_SIZE=FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/supermicro/h8dmr_fam10/Config.lb
===================================================================
--- targets/supermicro/h8dmr_fam10/Config.lb	(revision 4704)
+++ targets/supermicro/h8dmr_fam10/Config.lb	(working copy)
@@ -37,7 +37,7 @@
 
 romimage "failover"
   option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
   option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
Index: targets/supermicro/h8dmr_fam10/Config-lab.lb
===================================================================
--- targets/supermicro/h8dmr_fam10/Config-lab.lb	(revision 4704)
+++ targets/supermicro/h8dmr_fam10/Config-lab.lb	(working copy)
@@ -30,7 +30,7 @@
 
 romimage "failover"
   option CONFIG_USE_FAILOVER_IMAGE=1
-  option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+  option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
   option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
Index: targets/gigabyte/m57sli/Config-abuild.lb
===================================================================
--- targets/gigabyte/m57sli/Config-abuild.lb	(revision 4704)
+++ targets/gigabyte/m57sli/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/gigabyte/m57sli/Config.lb.kernel
===================================================================
--- targets/gigabyte/m57sli/Config.lb.kernel	(revision 4704)
+++ targets/gigabyte/m57sli/Config.lb.kernel	(working copy)
@@ -32,10 +32,10 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -67,7 +67,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/gigabyte/m57sli/Config.lb
===================================================================
--- targets/gigabyte/m57sli/Config.lb	(revision 4704)
+++ targets/gigabyte/m57sli/Config.lb	(working copy)
@@ -34,10 +34,10 @@
 #        option CONFIG_ROM_SIZE = 479232
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -63,10 +63,10 @@
 romimage "fallback" 
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -97,7 +97,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/gigabyte/m57sli/Config-lab.lb
===================================================================
--- targets/gigabyte/m57sli/Config-lab.lb	(revision 4704)
+++ targets/gigabyte/m57sli/Config-lab.lb	(working copy)
@@ -32,7 +32,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
@@ -41,7 +41,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/gigabyte/ga_2761gxdk/Config-abuild.lb
===================================================================
--- targets/gigabyte/ga_2761gxdk/Config-abuild.lb	(revision 4704)
+++ targets/gigabyte/ga_2761gxdk/Config-abuild.lb	(working copy)
@@ -48,7 +48,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION=".0-Failover"
 end
Index: targets/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- targets/gigabyte/ga_2761gxdk/Config.lb	(revision 4704)
+++ targets/gigabyte/ga_2761gxdk/Config.lb	(working copy)
@@ -29,7 +29,7 @@
         option CONFIG_ROM_SIZE = (512*1024 - 32*1024)
 
         option CONFIG_USE_FAILOVER_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
+        option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x40000
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #	payload ../../../../payloads/filo_uda1.elf
@@ -39,7 +39,7 @@
 romimage "fallback"
         option CONFIG_USE_FAILOVER_IMAGE=0
         option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
+        option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x40000
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #	payload ../../../../payloads/filo_uda1.elf
@@ -49,7 +49,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/digitallogic/msm800sev/Config.lb
===================================================================
--- targets/digitallogic/msm800sev/Config.lb	(revision 4704)
+++ targets/digitallogic/msm800sev/Config.lb	(working copy)
@@ -11,9 +11,9 @@
 ##
 option CONFIG_ROM_SIZE = 1024*1024 - 36 * 1024
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE=64*1024
+option CONFIG_BOOTBLOCK_SIZE=64*1024
 
 option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
 
Index: targets/digitallogic/adl855pc/Config.lb
===================================================================
--- targets/digitallogic/adl855pc/Config.lb	(revision 4704)
+++ targets/digitallogic/adl855pc/Config.lb	(working copy)
@@ -8,14 +8,14 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 	payload /etc/hosts
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /etc/hosts
 end
Index: targets/digitallogic/msm586seg/Config.lb
===================================================================
--- targets/digitallogic/msm586seg/Config.lb	(revision 4704)
+++ targets/digitallogic/msm586seg/Config.lb	(working copy)
@@ -11,7 +11,7 @@
 
 #romimage "normal"
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=0x10000
 #	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /etc/hosts
 #end
@@ -21,9 +21,9 @@
 #	option CONFIG_ROM_SIZE=512*1024
 #	option CONFIG_ROM_SECTION_SIZE=512*1024
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000
-	option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000
-#	option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=32 * 1024 # 0x8000
+	option CONFIG_BOOTBLOCK_SIZE=128 * 1024 # 0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=512 * 1024 # 0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../../filo.elf
 #	payload ../../eepro100--ide_disk.zelf
Index: targets/emulation/qemu-x86/Config-car.lb
===================================================================
--- targets/emulation/qemu-x86/Config-car.lb	(revision 4704)
+++ targets/emulation/qemu-x86/Config-car.lb	(working copy)
@@ -16,7 +16,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION="-GRUB2"
 #	payload /home/stepan/core.img
 	payload ../payload.elf
Index: targets/olpc/btest/Config.lb
===================================================================
--- targets/olpc/btest/Config.lb	(revision 4704)
+++ targets/olpc/btest/Config.lb	(working copy)
@@ -16,7 +16,7 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 3
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
+	option CONFIG_BOOTBLOCK_SIZE=32*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /tmp/olpcpayload.elf
 end
Index: targets/olpc/rev_a/Config.kernel.lb
===================================================================
--- targets/olpc/rev_a/Config.kernel.lb	(revision 4704)
+++ targets/olpc/rev_a/Config.kernel.lb	(working copy)
@@ -8,7 +8,7 @@
 
 #romimage "normal"
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=0x10000
 #	option COREBOOT_EXTRA_VERSION=".0Normal"
 ##	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 ##	payload ../../../../tg3--ide_disk.zelf	
@@ -20,7 +20,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/olpc/rev_a/Config.lb
===================================================================
--- targets/olpc/rev_a/Config.lb	(revision 4704)
+++ targets/olpc/rev_a/Config.lb	(working copy)
@@ -12,7 +12,7 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
+	option CONFIG_BOOTBLOCK_SIZE=32*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /tmp/olpcpayload.elf
 end
Index: targets/olpc/rev_a/Config.SPI.lb
===================================================================
--- targets/olpc/rev_a/Config.SPI.lb	(revision 4704)
+++ targets/olpc/rev_a/Config.SPI.lb	(working copy)
@@ -16,7 +16,7 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
+	option CONFIG_BOOTBLOCK_SIZE=32*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /tmp/olpcpayload.elf
 end
Index: targets/olpc/rev_a/Config.1M.lb
===================================================================
--- targets/olpc/rev_a/Config.1M.lb	(revision 4704)
+++ targets/olpc/rev_a/Config.1M.lb	(working copy)
@@ -15,7 +15,7 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32*1024
+	option CONFIG_BOOTBLOCK_SIZE=32*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /tmp/olpcpayload.elf
 end
Index: targets/technologic/ts5300/Config.lb
===================================================================
--- targets/technologic/ts5300/Config.lb	(revision 4704)
+++ targets/technologic/ts5300/Config.lb	(working copy)
@@ -10,7 +10,7 @@
 
 #romimage "normal"
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=0x10000
 #	option COREBOOT_EXTRA_VERSION=".0-Normal"
 #	payload /etc/hosts
 #end
@@ -20,10 +20,10 @@
 #	option CONFIG_ROM_SIZE=512*1024
 #	option CONFIG_ROM_SECTION_SIZE=512*1024
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=32 * 1024 # 0x8000
-#	option CONFIG_ROM_IMAGE_SIZE=48 * 1024 # 0x8000
-#	option CONFIG_ROM_IMAGE_SIZE=64 * 1024 # 0x10000
-#	option CONFIG_ROM_IMAGE_SIZE=512 * 1024 # 0x10000
+	option CONFIG_BOOTBLOCK_SIZE=32 * 1024 # 0x8000
+#	option CONFIG_BOOTBLOCK_SIZE=48 * 1024 # 0x8000
+#	option CONFIG_BOOTBLOCK_SIZE=64 * 1024 # 0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=512 * 1024 # 0x10000
 #	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	option COREBOOT_EXTRA_VERSION=".0"
 	payload /home/stepan/filo-ts5300.elf
Index: targets/amd/pistachio/Config-abuild.lb
===================================================================
--- targets/amd/pistachio/Config-abuild.lb	(revision 4704)
+++ targets/amd/pistachio/Config-abuild.lb	(working copy)
@@ -13,7 +13,7 @@
 option CONFIG_ROM_SIZE=1024*1024
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
         option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
@@ -21,7 +21,7 @@
 
 romimage "fallback"
         option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
+        option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
Index: targets/amd/pistachio/Config.lb
===================================================================
--- targets/amd/pistachio/Config.lb	(revision 4704)
+++ targets/amd/pistachio/Config.lb	(working copy)
@@ -6,14 +6,14 @@
 romimage "normal"
 	option CONFIG_ROM_SIZE = 1024*1024 - 55808
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
Index: targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- targets/amd/dbm690t/Config-abuild.lb	(revision 4704)
+++ targets/amd/dbm690t/Config-abuild.lb	(working copy)
@@ -13,7 +13,7 @@
 option CONFIG_ROM_SIZE=1024*1024
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
         option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
@@ -21,7 +21,7 @@
 
 romimage "fallback"
         option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x20000
+        option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
Index: targets/amd/dbm690t/Config.lb
===================================================================
--- targets/amd/dbm690t/Config.lb	(revision 4704)
+++ targets/amd/dbm690t/Config.lb	(working copy)
@@ -6,14 +6,14 @@
 romimage "normal"
 	option CONFIG_ROM_SIZE = 1024*1024 - 55808
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
Index: targets/amd/rumba/Config.lb
===================================================================
--- targets/amd/rumba/Config.lb	(revision 4704)
+++ targets/amd/rumba/Config.lb	(working copy)
@@ -8,7 +8,7 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -20,7 +20,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/amd/rumba/Config.nofallback.lb
===================================================================
--- targets/amd/rumba/Config.nofallback.lb	(revision 4704)
+++ targets/amd/rumba/Config.nofallback.lb	(working copy)
@@ -8,7 +8,7 @@
 
 #romimage "normal"
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x10000
+#	option CONFIG_BOOTBLOCK_SIZE=0x10000
 #	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -20,7 +20,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/amd/serengeti_cheetah/Config-abuild.lb
===================================================================
--- targets/amd/serengeti_cheetah/Config-abuild.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/amd/serengeti_cheetah/Config.lb
===================================================================
--- targets/amd/serengeti_cheetah/Config.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah/Config.lb	(working copy)
@@ -15,10 +15,10 @@
 #        option CONFIG_ROM_SIZE = 458752 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -44,10 +44,10 @@
 romimage "fallback" 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -77,7 +77,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/amd/serengeti_cheetah/Config-lab.lb
===================================================================
--- targets/amd/serengeti_cheetah/Config-lab.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah/Config-lab.lb	(working copy)
@@ -14,7 +14,7 @@
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x1a000
+	option CONFIG_BOOTBLOCK_SIZE=0x1a000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 	payload ../payload.elf.lzma
Index: targets/amd/norwich/Config.lb
===================================================================
--- targets/amd/norwich/Config.lb	(revision 4704)
+++ targets/amd/norwich/Config.lb	(working copy)
@@ -40,7 +40,7 @@
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../payload.elf
 end
Index: targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===================================================================
--- targets/amd/serengeti_cheetah_fam10/Config-abuild.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah_fam10/Config-abuild.lb	(working copy)
@@ -14,7 +14,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x3f000
+	option CONFIG_BOOTBLOCK_SIZE=0x3f000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
@@ -22,7 +22,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION=".0-failover"
 end
Index: targets/amd/serengeti_cheetah_fam10/Config.lb
===================================================================
--- targets/amd/serengeti_cheetah_fam10/Config.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah_fam10/Config.lb	(working copy)
@@ -38,8 +38,8 @@
 #	option CONFIG_ROM_SIZE = 0x100000
 #	option CONFIG_USE_FAILOVER_IMAGE=0
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x30000
+#	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x30000
 #	option CONFIG_XIP_ROM_SIZE=0x40000
 #	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #	payload ../payload.elf
@@ -48,10 +48,10 @@
 romimage "fallback"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x7f000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x7f000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x80000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf
@@ -60,7 +60,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/amd/serengeti_cheetah_fam10/Config-lab.lb
===================================================================
--- targets/amd/serengeti_cheetah_fam10/Config-lab.lb	(revision 4704)
+++ targets/amd/serengeti_cheetah_fam10/Config-lab.lb	(working copy)
@@ -35,7 +35,7 @@
 romimage "fallback"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x30000
+	option CONFIG_BOOTBLOCK_SIZE=0x30000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
@@ -44,7 +44,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/amd/db800/Config.lb
===================================================================
--- targets/amd/db800/Config.lb	(revision 4704)
+++ targets/amd/db800/Config.lb	(working copy)
@@ -40,7 +40,7 @@
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../payload.elf
 end
Index: targets/iei/nova4899r/Config.lb
===================================================================
--- targets/iei/nova4899r/Config.lb	(revision 4704)
+++ targets/iei/nova4899r/Config.lb	(working copy)
@@ -38,7 +38,7 @@
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload /opt/coreboot-SVN/filo.elf
 end
Index: targets/iei/pcisa-lx-800-r10/Config.lb
===================================================================
--- targets/iei/pcisa-lx-800-r10/Config.lb	(revision 4704)
+++ targets/iei/pcisa-lx-800-r10/Config.lb	(working copy)
@@ -38,7 +38,7 @@
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 80 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 80 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 	payload ../payload.elf
 end
Index: targets/iei/juki-511p/Config.lb
===================================================================
--- targets/iei/juki-511p/Config.lb	(revision 4704)
+++ targets/iei/juki-511p/Config.lb	(working copy)
@@ -29,7 +29,7 @@
 option CONFIG_PRECOMPRESSED_PAYLOAD=0
 
 romimage "fallback"
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION="-filo"
 	payload ../../filo.elf
 end
Index: targets/tyan/s2912/Config-abuild.lb
===================================================================
--- targets/tyan/s2912/Config-abuild.lb	(revision 4704)
+++ targets/tyan/s2912/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/tyan/s2912/Config.lb.kernel
===================================================================
--- targets/tyan/s2912/Config.lb.kernel	(revision 4704)
+++ targets/tyan/s2912/Config.lb.kernel	(working copy)
@@ -32,10 +32,10 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -67,7 +67,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/tyan/s2912/Config.lb
===================================================================
--- targets/tyan/s2912/Config.lb	(revision 4704)
+++ targets/tyan/s2912/Config.lb	(working copy)
@@ -36,10 +36,10 @@
 #        option CONFIG_ROM_SIZE = 479232
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -64,10 +64,10 @@
 romimage "fallback" 
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -97,7 +97,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/tyan/s2850/Config.lb
===================================================================
--- targets/tyan/s2850/Config.lb	(revision 4704)
+++ targets/tyan/s2850/Config.lb	(working copy)
@@ -14,11 +14,11 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13c00
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -37,11 +37,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13c00
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2735/Config.lb
===================================================================
--- targets/tyan/s2735/Config.lb	(revision 4704)
+++ targets/tyan/s2735/Config.lb	(working copy)
@@ -14,7 +14,7 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=0x11800
+        option CONFIG_BOOTBLOCK_SIZE=0x11800
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -29,7 +29,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-        option CONFIG_ROM_IMAGE_SIZE=0x11800
+        option CONFIG_BOOTBLOCK_SIZE=0x11800
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2880/Config.lb
===================================================================
--- targets/tyan/s2880/Config.lb	(revision 4704)
+++ targets/tyan/s2880/Config.lb	(working copy)
@@ -14,11 +14,11 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -36,11 +36,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2881/Config.lb
===================================================================
--- targets/tyan/s2881/Config.lb	(revision 4704)
+++ targets/tyan/s2881/Config.lb	(working copy)
@@ -16,10 +16,10 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -38,10 +38,10 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2881/Config-lab.lb
===================================================================
--- targets/tyan/s2881/Config-lab.lb	(revision 4704)
+++ targets/tyan/s2881/Config-lab.lb	(working copy)
@@ -14,7 +14,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
Index: targets/tyan/s4880/Config.lb
===================================================================
--- targets/tyan/s4880/Config.lb	(revision 4704)
+++ targets/tyan/s4880/Config.lb	(working copy)
@@ -14,9 +14,9 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19c00
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -33,9 +33,9 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19c00
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2891/Config-abuild.lb
===================================================================
--- targets/tyan/s2891/Config-abuild.lb	(revision 4704)
+++ targets/tyan/s2891/Config-abuild.lb	(working copy)
@@ -12,14 +12,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/tyan/s2891/Config.lb.com2
===================================================================
--- targets/tyan/s2891/Config.lb.com2	(revision 4704)
+++ targets/tyan/s2891/Config.lb.com2	(working copy)
@@ -14,9 +14,9 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+	option CONFIG_BOOTBLOCK_SIZE=0x15800
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -35,9 +35,9 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+	option CONFIG_BOOTBLOCK_SIZE=0x15800
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2891/Config.lb
===================================================================
--- targets/tyan/s2891/Config.lb	(revision 4704)
+++ targets/tyan/s2891/Config.lb	(working copy)
@@ -16,10 +16,10 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -39,10 +39,10 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13000
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13000
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2891/Config-lab.lb
===================================================================
--- targets/tyan/s2891/Config-lab.lb	(revision 4704)
+++ targets/tyan/s2891/Config-lab.lb	(working copy)
@@ -14,7 +14,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
Index: targets/tyan/s2882/Config.lb
===================================================================
--- targets/tyan/s2882/Config.lb	(revision 4704)
+++ targets/tyan/s2882/Config.lb	(working copy)
@@ -14,9 +14,9 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -33,9 +33,9 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#        option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#        option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
         option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2882/Config-lab.lb
===================================================================
--- targets/tyan/s2882/Config-lab.lb	(revision 4704)
+++ targets/tyan/s2882/Config-lab.lb	(working copy)
@@ -14,7 +14,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
Index: targets/tyan/s2892/Config-abuild.lb
===================================================================
--- targets/tyan/s2892/Config-abuild.lb	(revision 4704)
+++ targets/tyan/s2892/Config-abuild.lb	(working copy)
@@ -12,14 +12,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/tyan/s2892/Config.lb
===================================================================
--- targets/tyan/s2892/Config.lb	(revision 4704)
+++ targets/tyan/s2892/Config.lb	(working copy)
@@ -16,11 +16,11 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16380
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16380
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -39,11 +39,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16380
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16380
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2892/Config-lab.lb
===================================================================
--- targets/tyan/s2892/Config-lab.lb	(revision 4704)
+++ targets/tyan/s2892/Config-lab.lb	(working copy)
@@ -11,7 +11,7 @@
 option CONFIG_CONSOLE_SERIAL8250 = 1
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_XIP_ROM_SIZE = 0x20000
-option CONFIG_ROM_IMAGE_SIZE = 0x18000
+option CONFIG_BOOTBLOCK_SIZE = 0x18000
 option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
 
 # Tyan s2892
Index: targets/tyan/s4882/Config.lb
===================================================================
--- targets/tyan/s4882/Config.lb	(revision 4704)
+++ targets/tyan/s4882/Config.lb	(working copy)
@@ -14,11 +14,11 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19c00
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16200
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -37,11 +37,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19000
-#	option CONFIG_ROM_IMAGE_SIZE=0x19c00
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19000
+#	option CONFIG_BOOTBLOCK_SIZE=0x19c00
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16200
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2875/Config.lb
===================================================================
--- targets/tyan/s2875/Config.lb	(revision 4704)
+++ targets/tyan/s2875/Config.lb	(working copy)
@@ -14,11 +14,11 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -36,11 +36,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2885/Config.lb
===================================================================
--- targets/tyan/s2885/Config.lb	(revision 4704)
+++ targets/tyan/s2885/Config.lb	(working copy)
@@ -14,10 +14,10 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 512*1024-64*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16200
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -38,10 +38,10 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x16200
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x16200
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/tyan/s2895/Config.lb
===================================================================
--- targets/tyan/s2895/Config.lb	(revision 4704)
+++ targets/tyan/s2895/Config.lb	(working copy)
@@ -9,7 +9,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 	payload ../payload.elf
@@ -18,7 +18,7 @@
 romimage "fallback" 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf
Index: targets/tyan/s2895/Config-lab.lb
===================================================================
--- targets/tyan/s2895/Config-lab.lb	(revision 4704)
+++ targets/tyan/s2895/Config-lab.lb	(working copy)
@@ -8,7 +8,7 @@
 option CONFIG_CONSOLE_SERIAL8250 = 1
 option CONFIG_CONSOLE_VGA = 1
 option CONFIG_XIP_ROM_SIZE = 0x20000
-option CONFIG_ROM_IMAGE_SIZE = 0x18000
+option CONFIG_BOOTBLOCK_SIZE = 0x18000
 option CONFIG_HAVE_FAILOVER_BOOT = 0
 option CONFIG_FAILOVER_SIZE = 0
 option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
Index: targets/tyan/s2912_fam10/Config-abuild.lb
===================================================================
--- targets/tyan/s2912_fam10/Config-abuild.lb	(revision 4704)
+++ targets/tyan/s2912_fam10/Config-abuild.lb	(working copy)
@@ -45,7 +45,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION=".0-Failover"
 end
Index: targets/tyan/s2912_fam10/Config.lb.kernel
===================================================================
--- targets/tyan/s2912_fam10/Config.lb.kernel	(revision 4704)
+++ targets/tyan/s2912_fam10/Config.lb.kernel	(working copy)
@@ -32,10 +32,10 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -67,7 +67,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/tyan/s2912_fam10/Config.lb
===================================================================
--- targets/tyan/s2912_fam10/Config.lb	(revision 4704)
+++ targets/tyan/s2912_fam10/Config.lb	(working copy)
@@ -30,7 +30,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
@@ -40,7 +40,7 @@
 romimage "fallback" 
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
@@ -50,7 +50,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/pcengines/alix1c/Config.lb
===================================================================
--- targets/pcengines/alix1c/Config.lb	(revision 4704)
+++ targets/pcengines/alix1c/Config.lb	(working copy)
@@ -7,9 +7,9 @@
 ## (normal AND fallback images and payloads). Leave 36k for VSA.
 option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = (64 * 1024)
+option CONFIG_BOOTBLOCK_SIZE = (64 * 1024)
 
 option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
 
Index: targets/artecgroup/dbe61/Config.lb
===================================================================
--- targets/artecgroup/dbe61/Config.lb	(revision 4704)
+++ targets/artecgroup/dbe61/Config.lb	(working copy)
@@ -17,9 +17,9 @@
 #No VGA for now
 option CONFIG_ROM_SIZE = 1024*512 - 36*1024
 
-# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+# CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE=64*1024
+option CONFIG_BOOTBLOCK_SIZE=64*1024
 
 option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
Index: targets/asi/mb_5blmp/Config.lb
===================================================================
--- targets/asi/mb_5blmp/Config.lb	(revision 4704)
+++ targets/asi/mb_5blmp/Config.lb	(working copy)
@@ -26,14 +26,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Normal"
 	payload /tmp/filo.elf
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 	payload /tmp/filo.elf
 end
Index: targets/via/epia-m/Config.512kflash.lb
===================================================================
--- targets/via/epia-m/Config.512kflash.lb	(revision 4704)
+++ targets/via/epia-m/Config.512kflash.lb	(working copy)
@@ -36,7 +36,7 @@
 #
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -45,7 +45,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia-m/Config.lb
===================================================================
--- targets/via/epia-m/Config.lb	(revision 4704)
+++ targets/via/epia-m/Config.lb	(working copy)
@@ -31,16 +31,16 @@
 #
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#option CONFIG_ROM_IMAGE_SIZE=128*1024
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+#option CONFIG_BOOTBLOCK_SIZE=128*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0-Normal"
 	payload $(HOME)/svn/payload.elf
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	#option CONFIG_ROM_IMAGE_SIZE=128*1024
-	option CONFIG_ROM_IMAGE_SIZE=60*1024
+	#option CONFIG_BOOTBLOCK_SIZE=128*1024
+	option CONFIG_BOOTBLOCK_SIZE=60*1024
 	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload $(HOME)/svn/payload.elf
 end
Index: targets/via/epia-m/Config.filo.lb
===================================================================
--- targets/via/epia-m/Config.filo.lb	(revision 4704)
+++ targets/via/epia-m/Config.filo.lb	(working copy)
@@ -35,7 +35,7 @@
 #
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -45,7 +45,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia-m/Config.vga.filo
===================================================================
--- targets/via/epia-m/Config.vga.filo	(revision 4704)
+++ targets/via/epia-m/Config.vga.filo	(working copy)
@@ -33,7 +33,7 @@
 #
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0xc000
+	option CONFIG_BOOTBLOCK_SIZE=0xc000
 	option CONFIG_ROM_SECTION_OFFSET=0x10000
 	option CONFIG_ROM_SECTION_SIZE=0x18000
 	option COREBOOT_EXTRA_VERSION=".0-Normal"
@@ -42,7 +42,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0xc000
+	option CONFIG_BOOTBLOCK_SIZE=0xc000
 	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload $(HOME)/svn/filo.elf
 end
Index: targets/via/epia-m/Config.etherboot.lb
===================================================================
--- targets/via/epia-m/Config.etherboot.lb	(revision 4704)
+++ targets/via/epia-m/Config.etherboot.lb	(working copy)
@@ -35,7 +35,7 @@
 #
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -44,7 +44,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia-n/Config-abuild.lb
===================================================================
--- targets/via/epia-n/Config-abuild.lb	(revision 4704)
+++ targets/via/epia-n/Config-abuild.lb	(working copy)
@@ -14,7 +14,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/via/epia-cn/Config-abuild.lb
===================================================================
--- targets/via/epia-cn/Config-abuild.lb	(revision 4704)
+++ targets/via/epia-cn/Config-abuild.lb	(working copy)
@@ -14,7 +14,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/via/epia/Config.512kflash.lb
===================================================================
--- targets/via/epia/Config.512kflash.lb	(revision 4704)
+++ targets/via/epia/Config.512kflash.lb	(working copy)
@@ -10,7 +10,7 @@
 # Via Epia
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -19,7 +19,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia/Config.lb
===================================================================
--- targets/via/epia/Config.lb	(revision 4704)
+++ targets/via/epia/Config.lb	(working copy)
@@ -14,7 +14,7 @@
 # Via Epia
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -24,7 +24,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia/Config.512kflash.linuxtiny.lb
===================================================================
--- targets/via/epia/Config.512kflash.linuxtiny.lb	(revision 4704)
+++ targets/via/epia/Config.512kflash.linuxtiny.lb	(working copy)
@@ -11,7 +11,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=64*1024
+	option CONFIG_BOOTBLOCK_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia/Config.filo.lb
===================================================================
--- targets/via/epia/Config.filo.lb	(revision 4704)
+++ targets/via/epia/Config.filo.lb	(working copy)
@@ -8,7 +8,7 @@
 # Via Epia
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -18,7 +18,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/epia/Config.ituner.filo.lb
===================================================================
--- targets/via/epia/Config.ituner.filo.lb	(revision 4704)
+++ targets/via/epia/Config.ituner.filo.lb	(working copy)
@@ -10,7 +10,7 @@
 # Via Epia
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -20,7 +20,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/via/pc2500e/Config-abuild.lb
===================================================================
--- targets/via/pc2500e/Config-abuild.lb	(revision 4704)
+++ targets/via/pc2500e/Config-abuild.lb	(working copy)
@@ -32,7 +32,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 	payload __PAYLOAD__
 end
Index: targets/lippert/roadrunner-lx/Config.lb
===================================================================
--- targets/lippert/roadrunner-lx/Config.lb	(revision 4704)
+++ targets/lippert/roadrunner-lx/Config.lb	(working copy)
@@ -47,12 +47,12 @@
 #option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
 #option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
 
-# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
+# Saves space on CONFIG_BOOTBLOCK_SIZE, but decompression costs a second on boot.
 option CONFIG_COMPRESS = 1
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0"
 	payload ../payload.elf
 	# If getting payload from IDE
Index: targets/lippert/frontrunner/Config.lb
===================================================================
--- targets/lippert/frontrunner/Config.lb	(revision 4704)
+++ targets/lippert/frontrunner/Config.lb	(working copy)
@@ -8,7 +8,7 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x16000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -20,7 +20,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x16000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/lippert/spacerunner-lx/Config.lb
===================================================================
--- targets/lippert/spacerunner-lx/Config.lb	(revision 4704)
+++ targets/lippert/spacerunner-lx/Config.lb	(working copy)
@@ -47,12 +47,12 @@
 #option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
 #option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
 
-# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
+# Saves space on CONFIG_BOOTBLOCK_SIZE, but decompression costs a second on boot.
 option CONFIG_COMPRESS = 1
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 64 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0"
 	payload ../payload.elf
 	# If getting payload from IDE
Index: targets/dell/s1850/Config.lb
===================================================================
--- targets/dell/s1850/Config.lb	(revision 4704)
+++ targets/dell/s1850/Config.lb	(working copy)
@@ -7,7 +7,7 @@
 
 #romimage "normal"
 #	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x16000
+#	option CONFIG_BOOTBLOCK_SIZE=0x16000
 #	option COREBOOT_EXTRA_VERSION=".0Normal"
 ##	payload ../../../payloads/filo.elf
 #	payload /tmp/filo.elf
@@ -15,7 +15,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x16000
+	option CONFIG_BOOTBLOCK_SIZE=0x16000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload ../../../payloads/filo.elf
 	payload /tmp/filo.elf
Index: targets/msi/ms7135/Config-abuild.lb
===================================================================
--- targets/msi/ms7135/Config-abuild.lb	(revision 4704)
+++ targets/msi/ms7135/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/msi/ms7135/Config.lb
===================================================================
--- targets/msi/ms7135/Config.lb	(revision 4704)
+++ targets/msi/ms7135/Config.lb	(working copy)
@@ -34,7 +34,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="_Normal"
 	payload /tmp/payload.elf
@@ -43,7 +43,7 @@
 romimage "fallback" 
 	option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="_Fallback"
 	payload /tmp/payload.elf
@@ -52,7 +52,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="_Failover"
 end
Index: targets/msi/ms9282/Config-abuild.lb
===================================================================
--- targets/msi/ms9282/Config-abuild.lb	(revision 4704)
+++ targets/msi/ms9282/Config-abuild.lb	(working copy)
@@ -12,14 +12,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/msi/ms9282/Config.lb
===================================================================
--- targets/msi/ms9282/Config.lb	(revision 4704)
+++ targets/msi/ms9282/Config.lb	(working copy)
@@ -32,10 +32,10 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 458752
        option CONFIG_USE_FALLBACK_IMAGE=0
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x18800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
+#      option CONFIG_BOOTBLOCK_SIZE=0x13800
+#      option CONFIG_BOOTBLOCK_SIZE=0x18800
+       option CONFIG_BOOTBLOCK_SIZE=0x20000
+#      option CONFIG_BOOTBLOCK_SIZE=0x15800
        option CONFIG_XIP_ROM_SIZE=0x40000
        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -60,10 +60,10 @@
 
 romimage "fallback"
        option CONFIG_USE_FALLBACK_IMAGE=1
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x19800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
+#      option CONFIG_BOOTBLOCK_SIZE=0x13800
+#      option CONFIG_BOOTBLOCK_SIZE=0x19800
+       option CONFIG_BOOTBLOCK_SIZE=0x20000
+#      option CONFIG_BOOTBLOCK_SIZE=0x15800
        option CONFIG_XIP_ROM_SIZE=0x40000
        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/msi/ms9185/Config-abuild.lb
===================================================================
--- targets/msi/ms9185/Config-abuild.lb	(revision 4704)
+++ targets/msi/ms9185/Config-abuild.lb	(working copy)
@@ -12,14 +12,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/msi/ms9185/Config.lb
===================================================================
--- targets/msi/ms9185/Config.lb	(revision 4704)
+++ targets/msi/ms9185/Config.lb	(working copy)
@@ -35,10 +35,10 @@
 #       64K for Etherboot
 #        option CONFIG_ROM_SIZE = 458752
        option CONFIG_USE_FALLBACK_IMAGE=0
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x18800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
+#      option CONFIG_BOOTBLOCK_SIZE=0x13800
+#      option CONFIG_BOOTBLOCK_SIZE=0x18800
+       option CONFIG_BOOTBLOCK_SIZE=0x20000
+#      option CONFIG_BOOTBLOCK_SIZE=0x15800
        option CONFIG_XIP_ROM_SIZE=0x40000
        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -63,10 +63,10 @@
 
 romimage "fallback"
        option CONFIG_USE_FALLBACK_IMAGE=1
-#      option CONFIG_ROM_IMAGE_SIZE=0x13800
-#      option CONFIG_ROM_IMAGE_SIZE=0x19800
-       option CONFIG_ROM_IMAGE_SIZE=0x20000
-#      option CONFIG_ROM_IMAGE_SIZE=0x15800
+#      option CONFIG_BOOTBLOCK_SIZE=0x13800
+#      option CONFIG_BOOTBLOCK_SIZE=0x19800
+       option CONFIG_BOOTBLOCK_SIZE=0x20000
+#      option CONFIG_BOOTBLOCK_SIZE=0x15800
        option CONFIG_XIP_ROM_SIZE=0x40000
        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/msi/ms7260/Config-abuild.lb
===================================================================
--- targets/msi/ms7260/Config-abuild.lb	(revision 4704)
+++ targets/msi/ms7260/Config-abuild.lb	(working copy)
@@ -45,7 +45,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE = 1
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE = CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION = ".0Failover"
 end
Index: targets/msi/ms7260/Config.lb
===================================================================
--- targets/msi/ms7260/Config.lb	(revision 4704)
+++ targets/msi/ms7260/Config.lb	(working copy)
@@ -29,7 +29,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE = 0
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option CONFIG_XIP_ROM_SIZE = 256 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Normal"
 #	payload /tmp/filo.elf
@@ -39,7 +39,7 @@
 romimage "fallback"
 	option CONFIG_USE_FAILOVER_IMAGE = 0
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option CONFIG_XIP_ROM_SIZE = 256 * 1024
 	option COREBOOT_EXTRA_VERSION = ".0Fallback"
 #	payload /tmp/filo.elf
@@ -49,7 +49,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE = 1
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE = CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION = ".0Failover"
 end
Index: targets/arima/hdama/Config-abuild.lb
===================================================================
--- targets/arima/hdama/Config-abuild.lb	(revision 4704)
+++ targets/arima/hdama/Config-abuild.lb	(working copy)
@@ -14,14 +14,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/arima/hdama/Config.lb
===================================================================
--- targets/arima/hdama/Config.lb	(revision 4704)
+++ targets/arima/hdama/Config.lb	(working copy)
@@ -11,7 +11,7 @@
 # Arima hdama
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 	payload ../../../payloads/filo.elf
 #	payload /etc/hosts
@@ -19,7 +19,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../../../payloads/filo.elf
 #	payload /etc/hosts
Index: targets/arima/hdama/Config.kernelimage.lb
===================================================================
--- targets/arima/hdama/Config.kernelimage.lb	(revision 4704)
+++ targets/arima/hdama/Config.kernelimage.lb	(working copy)
@@ -32,7 +32,7 @@
 uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
-uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_BOOTBLOCK_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SIZE
@@ -83,7 +83,7 @@
 # Arima hdama
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 #	option CONFIG_ROM_SECTION_SIZE=0x100000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	mainboard arima/hdama
Index: targets/sunw/ultra40/Config.lb
===================================================================
--- targets/sunw/ultra40/Config.lb	(revision 4704)
+++ targets/sunw/ultra40/Config.lb	(working copy)
@@ -17,11 +17,11 @@
 #	64K for NIC option 48K for Raid option rom
 #	option CONFIG_ROM_SIZE = 512*1024-64*1024-48*1024
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -46,11 +46,11 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x11800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15000
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
+#	option CONFIG_BOOTBLOCK_SIZE=0x11800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x15000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x17800
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
Index: targets/eaglelion/5bcm/Config.lb
===================================================================
--- targets/eaglelion/5bcm/Config.lb	(revision 4704)
+++ targets/eaglelion/5bcm/Config.lb	(working copy)
@@ -8,7 +8,7 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -19,7 +19,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
Index: targets/newisys/khepri/Config.lb
===================================================================
--- targets/newisys/khepri/Config.lb	(revision 4704)
+++ targets/newisys/khepri/Config.lb	(working copy)
@@ -30,14 +30,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="-Khepri-Normal"
 	payload ../../../payloads/tg3--ide_disk.zelf
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="-Khepri-Fallback"
 	payload ../../../payloads/tg3--ide_disk.zelf
 end
Index: targets/jetway/j7f24/Config-abuild.lb
===================================================================
--- targets/jetway/j7f24/Config-abuild.lb	(revision 4704)
+++ targets/jetway/j7f24/Config-abuild.lb	(working copy)
@@ -14,7 +14,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/technexion/tim8690/Config-abuild.lb
===================================================================
--- targets/technexion/tim8690/Config-abuild.lb	(revision 4704)
+++ targets/technexion/tim8690/Config-abuild.lb	(working copy)
@@ -12,14 +12,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/technexion/tim8690/Config.lb
===================================================================
--- targets/technexion/tim8690/Config.lb	(revision 4704)
+++ targets/technexion/tim8690/Config.lb	(working copy)
@@ -7,7 +7,7 @@
 romimage "normal"
 	option CONFIG_ROM_SIZE = 1024*512 - 55808
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload /home/daniel/mypayloads/link
 end
@@ -15,7 +15,7 @@
 romimage "fallback" 
 	option CONFIG_FALLBACK_SIZE= 1024*512 - 55808
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload /home/daniel/mypayloads/link
 
Index: targets/ibm/e326/Config-abuild.lb
===================================================================
--- targets/ibm/e326/Config-abuild.lb	(revision 4704)
+++ targets/ibm/e326/Config-abuild.lb	(working copy)
@@ -14,14 +14,14 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
Index: targets/ibm/e326/Config.lb
===================================================================
--- targets/ibm/e326/Config.lb	(revision 4704)
+++ targets/ibm/e326/Config.lb	(working copy)
@@ -11,7 +11,7 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload ../../filo.elf
 	payload ../../../payloads/filo.elf
@@ -19,7 +19,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload ../../filo.elf
 	payload ../../../payloads/filo.elf
Index: targets/ibm/e325/Config.lb
===================================================================
--- targets/ibm/e325/Config.lb	(revision 4704)
+++ targets/ibm/e325/Config.lb	(working copy)
@@ -15,7 +15,7 @@
 # Arima hdama
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload ../../filo.elf
 	payload ../../../payloads/filo.elf
@@ -23,7 +23,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload ../../filo.elf
 	payload ../../../payloads/filo.elf
Index: targets/nvidia/l1_2pvv/Config-abuild.lb
===================================================================
--- targets/nvidia/l1_2pvv/Config-abuild.lb	(revision 4704)
+++ targets/nvidia/l1_2pvv/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/nvidia/l1_2pvv/Config.lb.kernel
===================================================================
--- targets/nvidia/l1_2pvv/Config.lb.kernel	(revision 4704)
+++ targets/nvidia/l1_2pvv/Config.lb.kernel	(working copy)
@@ -34,10 +34,10 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -69,7 +69,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/nvidia/l1_2pvv/Config.lb
===================================================================
--- targets/nvidia/l1_2pvv/Config.lb	(revision 4704)
+++ targets/nvidia/l1_2pvv/Config.lb	(working copy)
@@ -38,10 +38,10 @@
 #        option CONFIG_ROM_SIZE = 479232
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x18800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x18800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -66,10 +66,10 @@
 romimage "fallback" 
         option CONFIG_USE_FAILOVER_IMAGE=0
 	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x19800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+#	option CONFIG_BOOTBLOCK_SIZE=0x13800
+#	option CONFIG_BOOTBLOCK_SIZE=0x19800
+	option CONFIG_BOOTBLOCK_SIZE=0x20000
+#	option CONFIG_BOOTBLOCK_SIZE=0x15800
 	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
@@ -99,7 +99,7 @@
 romimage "failover"
         option CONFIG_USE_FAILOVER_IMAGE=1
         option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
         option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
Index: targets/intel/xe7501devkit/Config.lb
===================================================================
--- targets/intel/xe7501devkit/Config.lb	(revision 4704)
+++ targets/intel/xe7501devkit/Config.lb	(working copy)
@@ -5,9 +5,9 @@
 ## (normal AND fallback images and payloads).
 option CONFIG_ROM_SIZE = 192*1024
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 0x1B000
+option CONFIG_BOOTBLOCK_SIZE = 0x1B000
 
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image 
 ## (including payload) will use
Index: targets/intel/truxton/Config.lb
===================================================================
--- targets/intel/truxton/Config.lb	(revision 4704)
+++ targets/intel/truxton/Config.lb	(working copy)
@@ -24,13 +24,13 @@
 ## (normal AND fallback images and payloads).
 option CONFIG_ROM_SIZE = 2 * 1024 * 1024
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
 ## (including payload) will use
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
+option CONFIG_FALLBACK_SIZE = CONFIG_BOOTBLOCK_SIZE
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
Index: targets/intel/mtarvon/Config.lb
===================================================================
--- targets/intel/mtarvon/Config.lb	(revision 4704)
+++ targets/intel/mtarvon/Config.lb	(working copy)
@@ -24,9 +24,9 @@
 ## (normal AND fallback images and payloads).
 option CONFIG_ROM_SIZE = 2 * 1024 * 1024
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 
 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
 ## (including payload) will use
Index: targets/asus/a8v-e_se/Config.lb
===================================================================
--- targets/asus/a8v-e_se/Config.lb	(revision 4704)
+++ targets/asus/a8v-e_se/Config.lb	(working copy)
@@ -23,14 +23,14 @@
 romimage "normal"
 	option CONFIG_ROM_SIZE = 512 * 1024
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 	payload ../payload.elf
 end
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../payload.elf
 end
Index: targets/asus/mew-vm/Config.lb
===================================================================
--- targets/asus/mew-vm/Config.lb	(revision 4704)
+++ targets/asus/mew-vm/Config.lb	(working copy)
@@ -8,7 +8,7 @@
 
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /etc/hosts
 	payload /home/amp/filo-0.5/filo.elf
@@ -16,7 +16,7 @@
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_IMAGE_SIZE=0x10000
+	option CONFIG_BOOTBLOCK_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /etc/hosts
 	payload /home/amp/filo-0.5/filo.elf
Index: targets/asus/a8n_e/Config-abuild.lb
===================================================================
--- targets/asus/a8n_e/Config-abuild.lb	(revision 4704)
+++ targets/asus/a8n_e/Config-abuild.lb	(working copy)
@@ -27,7 +27,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE=1
 	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE=CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
Index: targets/asus/a8n_e/Config.lb
===================================================================
--- targets/asus/a8n_e/Config.lb	(revision 4704)
+++ targets/asus/a8n_e/Config.lb	(working copy)
@@ -25,7 +25,7 @@
 romimage "normal"
 	option CONFIG_USE_FAILOVER_IMAGE = 0
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option CONFIG_XIP_ROM_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION = "_Normal"
 	payload ../payload.elf
@@ -34,7 +34,7 @@
 romimage "fallback" 
 	option CONFIG_USE_FAILOVER_IMAGE = 0
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+	option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 	option CONFIG_XIP_ROM_SIZE = 128 * 1024
 	option COREBOOT_EXTRA_VERSION = "_Fallback"
 	payload ../payload.elf
@@ -43,7 +43,7 @@
 romimage "failover"
 	option CONFIG_USE_FAILOVER_IMAGE = 1
 	option CONFIG_USE_FALLBACK_IMAGE = 0
-	option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE
+	option CONFIG_BOOTBLOCK_SIZE = CONFIG_FAILOVER_SIZE
 	option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION = "_Failover"
 end
Index: targets/asus/m2v-mx_se/Config-abuild.lb
===================================================================
--- targets/asus/m2v-mx_se/Config-abuild.lb	(revision 4704)
+++ targets/asus/m2v-mx_se/Config-abuild.lb	(working copy)
@@ -32,7 +32,7 @@
 
 option CONFIG_ROM_SIZE = 512 * 1024
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
 
 romimage "fallback"
Index: targets/asus/m2v-mx_se/Config.lb
===================================================================
--- targets/asus/m2v-mx_se/Config.lb	(revision 4704)
+++ targets/asus/m2v-mx_se/Config.lb	(working copy)
@@ -34,12 +34,12 @@
 
 #option CONFIG_ROM_SIZE = (512 * 1024) - (64 * 1024)
 
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
+## CONFIG_BOOTBLOCK_SIZE is the maximum number of bytes allowed for a coreboot image,
 ## not including any payload.
 
 # Please note that 128KB is cached for (XIP) too
 
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+option CONFIG_BOOTBLOCK_SIZE = 128 * 1024
 
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE=1
Index: util/newconfig/config.g
===================================================================
--- util/newconfig/config.g	(revision 4704)
+++ util/newconfig/config.g	(working copy)
@@ -1386,7 +1386,7 @@
 	global curimage
 	global bootblocksize
 	mainboard()
-	imagesize = getoption("CONFIG_ROM_IMAGE_SIZE", curimage)
+	imagesize = getoption("CONFIG_BOOTBLOCK_SIZE", curimage)
 	bootblocksize += imagesize
 	print "End ROMIMAGE"
 	curimage = 0
Index: util/abuild/abuild
===================================================================
--- util/abuild/abuild	(revision 4704)
+++ util/abuild/abuild	(working copy)
@@ -178,7 +178,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=0
 if CONFIG_CBFS
 else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 end
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
@@ -188,7 +188,7 @@
 	option CONFIG_USE_FALLBACK_IMAGE=1
 if CONFIG_CBFS
 else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
+	option CONFIG_BOOTBLOCK_SIZE=0x17000
 end
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__

From mylesgw at gmail.com  Fri Oct  2 00:43:31 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 16:43:31 -0600
Subject: [coreboot] Rename ROM_IMAGE_SIZE to BOOTBLOCK_SIZE?
In-Reply-To: <20091001223739.17912.qmail@stuge.se>
References: <20091001223739.17912.qmail@stuge.se>
Message-ID: <2831fecf0910011543p195a3f59j5dcb79e4c854897a@mail.gmail.com>

On Thu, Oct 1, 2009 at 4:37 PM, Peter Stuge <peter at stuge.se> wrote:
> Myles Watson wrote:
>> 1. shrink your bootblock (CONFIG_ROM_IMAGE_SIZE)
>
> Is this variable still around with Kconfig?
That suggestion was for if he wanted to use newconfig still.

> How about the attached
> patch? It has not been tested yet.

I think it will be hard to test since the CBFS bootblock has normal
and fallback ram init concatenated together.  Kconfig doesn't support
normal yet.

As always I could be wrong :)

Thanks,
Myles



From joe at settoplinux.org  Fri Oct  2 00:54:45 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 18:54:45 -0400
Subject: [coreboot] XMM stack
In-Reply-To: <4AC52ED6.3060003@assembler.cz>
References: <4AC52ED6.3060003@assembler.cz>
Message-ID: <febdfd29e36ecee84d160c420b093c4c@imap.1and1.com>




On Fri, 02 Oct 2009 00:36:06 +0200, Rudolf Marek <r.marek at assembler.cz>
wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> Hello,
> 
> I made some fix for xmmstack.c found in SerialICE.
> 
> leal (%esp), %ecx
> 
> 
> Its simple:
> 
> - --- old.c	2009-05-14 15:43:45.000000000 +0200
> +++ xmmstack.c	2009-10-02 00:19:52.755673296 +0200
> @@ -547,9 +547,23 @@ getxmml:\n\
>              continue;
>          }
>  #endif
> +
> +   fprintf(w,"#%s #ORIG\n", buf);
> +
> +	/* leal is tricky */
> +        if
> (regexp("^leal\\s+(\\d*)\\(\\%esp\\)\\s*,\\s*(.*)$",buf,len,find))
> +        {
> +            fprintf(w,"movl %%dr2,%%esp #NOSTACK\n");
> +            fprintf(w,"%s\n",buf);
> +            fprintf(w,"movl %%esp,%%dr2 #NOSTACK\n");
> +            continue;
> +        }
> +
> 
> It makes things compile. Maybe there are other issues don't know.
> 
Cool, thanks Rudolf.
Stefan, do you plan a svn repo for SerialICE?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From peter at stuge.se  Fri Oct  2 00:56:32 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 00:56:32 +0200
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <4AC4F2AE.5080704@assembler.cz>
	<2831fecf0910011117v12a28258o5b5f1dadf26a0fcf@mail.gmail.com>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
	<4AC4F2AE.5080704@assembler.cz> <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
	<2831fecf0910011117v12a28258o5b5f1dadf26a0fcf@mail.gmail.com>
Message-ID: <20091001225632.21062.qmail@stuge.se>

Myles Watson wrote:
> It looks like a dependency problem somewhere.  I replicated it.
> 
> Try
> rm -rf build
> make oldconfig
> make
> 
> (make clean didn't do it for me)

Rudolf Marek wrote:
> Well I did just make clean which was not enough.

What do you think this dependency problem is?


//Peter



From info at coresystems.de  Fri Oct  2 00:58:29 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 02 Oct 2009 00:58:29 +0200
Subject: [coreboot] build service results for r4705
Message-ID: <E1MtUbV-0005aD-5E@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stuge" checked in revision 4705 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts

Sorry, but I've forgotten where I found them. :\

Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Peter Stuge <peter at stuge.se>


Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4705&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4705&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2


If something broke during this checkin please be a pain 
in stuge's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From peter at stuge.se  Fri Oct  2 01:01:18 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 01:01:18 +0200
Subject: [coreboot] [v2] r4701
	-	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <13426df10910011203v14ba4746k710ad205c879ae80@mail.gmail.com>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
	<20091001182908.GF15511@greenwood>
	<13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>
	<20091001185932.GE5738@greenwood>
	<13426df10910011203v14ba4746k710ad205c879ae80@mail.gmail.com>
Message-ID: <20091001230118.21817.qmail@stuge.se>

ron minnich wrote:
> > In the GX1 case we need to include cpu_setup.inc, then gx_setup.inc,
> > then auto.inc. However, enable_mmx.inc and disable_mmx.inc must _not_
> > be included in the GX1 case. Hence the ifeq/else construct.
> 
> I understand your point. You are correct about the mmx stuff. So what
> must happen is that the mmx stuff must ALSO be conditional. Hence my
> point, that to make this Makefile completely general, we need to
> make ALL of the crt0-y entries conditional.

Agree. So CONFIG_CPU_MMX or some such should then be select:ed by
many CPUs, but not by GX1, right?


//Peter



From mylesgw at gmail.com  Fri Oct  2 01:05:48 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 17:05:48 -0600
Subject: [coreboot] ROMSIP missing for kbuild based build
In-Reply-To: <20091001225632.21062.qmail@stuge.se>
References: <4AC4EC08.8080507@assembler.cz>
	<2831fecf0910011102v79a51d4cq43ddf50481908720@mail.gmail.com>
	<4AC4EFB7.6070101@assembler.cz>
	<2831fecf0910011113x6ce0058fr12a85e2baf0614bf@mail.gmail.com>
	<4AC4F2AE.5080704@assembler.cz>
	<2831fecf0910011117v12a28258o5b5f1dadf26a0fcf@mail.gmail.com>
	<20091001225632.21062.qmail@stuge.se>
Message-ID: <2831fecf0910011605r7e6e1c38lb80f1ceaf16de39e@mail.gmail.com>

On Thu, Oct 1, 2009 at 4:56 PM, Peter Stuge <peter at stuge.se> wrote:
> Myles Watson wrote:
>> It looks like a dependency problem somewhere. ?I replicated it.
>>
>> Try
>> rm -rf build
>> make oldconfig
>> make
>>
>> (make clean didn't do it for me)
>
> Rudolf Marek wrote:
>> Well I did just make clean which was not enough.
>
> What do you think this dependency problem is?
I think make clean doesn't remove the load script.  Most of the time
this isn't a problem, but it should probably be fixed.

Thanks,
Myles



From peter at stuge.se  Fri Oct  2 01:06:04 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 01:06:04 +0200
Subject: [coreboot] [PATCH] update from revision guide for fam 0fh
In-Reply-To: <4AC514A2.6050108@assembler.cz>
References: <4AC514A2.6050108@assembler.cz>
Message-ID: <20091001230604.22546.qmail@stuge.se>

Rudolf Marek wrote:
> Lets add some more CPUs.
> 
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Peter Stuge <peter at stuge.se>



From rminnich at gmail.com  Fri Oct  2 01:08:10 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 16:08:10 -0700
Subject: [coreboot] [v2] r4701 -
	trunk/coreboot-v2/src/mainboard/dell/s1850
In-Reply-To: <20091001230118.21817.qmail@stuge.se>
References: <20091001160112.3309420009842@t-stueck.streichelzoo.local>
	<1254417855.533.1.camel@tetris>
	<13426df10910011115l6e1c0c5fv14b12024f2e3ec29@mail.gmail.com>
	<20091001182908.GF15511@greenwood>
	<13426df10910011140j69cb8e59x4f6dbe58186612be@mail.gmail.com>
	<20091001185932.GE5738@greenwood>
	<13426df10910011203v14ba4746k710ad205c879ae80@mail.gmail.com>
	<20091001230118.21817.qmail@stuge.se>
Message-ID: <13426df10910011608k3245098ax7ba966c2b3642f29@mail.gmail.com>

On Thu, Oct 1, 2009 at 4:01 PM, Peter Stuge <peter at stuge.se> wrote:

> Agree. So CONFIG_CPU_MMX or some such should then be select:ed by
> many CPUs, but not by GX1, right?

Yes, same for SSE. That way the generic makefile should be fine.

I just called it MMX, you all want CPU_MMX? that if fine too.

thanks

ron



From peter at stuge.se  Fri Oct  2 01:08:45 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 01:08:45 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <4AC4B767.2060406@settoplinux.org>
References: <4AC4B767.2060406@settoplinux.org>
Message-ID: <20091001230845.23180.qmail@stuge.se>

Joseph Smith wrote:
> how hard would it be to get serialice to do the same with the bios?

I think it already does. PCI is just IO, so it gets handled.


//Peter



From peter at stuge.se  Fri Oct  2 01:09:49 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 01:09:49 +0200
Subject: [coreboot] patch: add config for MMX and SSE
In-Reply-To: <13426df10910011512h4234d07fna29d0a59914eeca9@mail.gmail.com>
References: <13426df10910011512h4234d07fna29d0a59914eeca9@mail.gmail.com>
Message-ID: <20091001230949.23492.qmail@stuge.se>

ron minnich wrote:
> Add these two booleans. Sockets or CPUs (NOT MAINBOARDS!) should set
> them if they are available. 

Maybe put this note in the help text for the options? Not neccessary,
just an idea.


> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Yeah!

Acked-by: Peter Stuge <peter at stuge.se>



From joe at settoplinux.org  Fri Oct  2 01:18:27 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 19:18:27 -0400
Subject: [coreboot] serialice PCI capture
In-Reply-To: <20091001230845.23180.qmail@stuge.se>
References: <4AC4B767.2060406@settoplinux.org>
	<20091001230845.23180.qmail@stuge.se>
Message-ID: <6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>




On Fri, 2 Oct 2009 01:08:45 +0200, Peter Stuge <peter at stuge.se> wrote:
> Joseph Smith wrote:
>> how hard would it be to get serialice to do the same with the bios?
> 
> I think it already does. PCI is just IO, so it gets handled.
> 
Huh? PCI has IO space allocated, but I am talking about actual PCI config
registers... 

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Fri Oct  2 01:20:09 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Oct 2009 01:20:09 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
References: <4AC4B767.2060406@settoplinux.org>	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
Message-ID: <4AC53929.7090704@coresystems.de>

Joseph Smith wrote:
>
> On Fri, 2 Oct 2009 01:08:45 +0200, Peter Stuge <peter at stuge.se> wrote:
>   
>> Joseph Smith wrote:
>>     
>>> how hard would it be to get serialice to do the same with the bios?
>>>       
>> I think it already does. PCI is just IO, so it gets handled.
>>
>>     
> Huh? PCI has IO space allocated, but I am talking about actual PCI config
> registers... 
>
>   
Just try it :-)

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From peter at stuge.se  Fri Oct  2 01:20:12 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 01:20:12 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
References: <4AC4B767.2060406@settoplinux.org>
	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
Message-ID: <20091001232012.25975.qmail@stuge.se>

Joseph Smith wrote:
> > I think it already does. PCI is just IO, so it gets handled.
> 
> Huh? PCI has IO space allocated, but I am talking about actual PCI
> config registers... 

You get reads and writes, because they go over IO cf8/cfc.


//Peter



From joe at settoplinux.org  Fri Oct  2 01:22:17 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 19:22:17 -0400
Subject: [coreboot] serialice PCI capture
In-Reply-To: <20091001232012.25975.qmail@stuge.se>
References: <4AC4B767.2060406@settoplinux.org>
	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
	<20091001232012.25975.qmail@stuge.se>
Message-ID: <aac121930fa180055838e8452348177c@imap.1and1.com>




On Fri, 2 Oct 2009 01:20:12 +0200, Peter Stuge <peter at stuge.se> wrote:
> Joseph Smith wrote:
>> > I think it already does. PCI is just IO, so it gets handled.
>>
>> Huh? PCI has IO space allocated, but I am talking about actual PCI
>> config registers...
> 
> You get reads and writes, because they go over IO cf8/cfc.
> 
> 
> //Peter
> 
Oh, ok, gotcha :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From svn at coreboot.org  Fri Oct  2 01:22:50 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 01:22:50 +0200
Subject: [coreboot] [v2] r4706 - trunk/coreboot-v2/src/cpu
Message-ID: <mailman.3777.1355071626.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-02 01:22:50 +0200 (Fri, 02 Oct 2009)
New Revision: 4706

Modified:
   trunk/coreboot-v2/src/cpu/Kconfig
Log:
Support variables for MMX and SSE. These would be used in
e.g. Makefile.romcc.inc to enable certain features.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>




Modified: trunk/coreboot-v2/src/cpu/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/Kconfig	2009-10-01 22:34:18 UTC (rev 4705)
+++ trunk/coreboot-v2/src/cpu/Kconfig	2009-10-01 23:22:50 UTC (rev 4706)
@@ -25,3 +25,17 @@
 	bool
 	default y if MAX_CPUS != 1
 	default n
+
+config	MMX
+	bool
+	default n
+	help
+		Set this in socket or model if the CPU has MMX. 
+		If the CPUs for the socket always have MMX, set it there. 
+
+config SSE
+	bool
+	default n
+	help
+		Set this in socket or model if the CPU has SSE. 
+		If the CPUs for the socket always have MX, set it there. 




From hng at lanl.gov  Fri Oct  2 01:23:40 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Thu, 01 Oct 2009 17:23:40 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
Message-ID: <4AC539FC.7070908@lanl.gov>

Thanks.  I took option number 2.  It flashed successfully, however, gpxe 
does not seem to be starting.  Here is the output from the coreboot/seabios:

coreboot-2.0.0-r_s2881_Fallback Thu Oct  1 17:07:49 MDT 2009 starting...
(0,1) link=00
(1,0) link=00
02 nodes initialized.
core0 started:  01
started ap apicid:
SBLink=02
NC node|link=02
ht reset -


coreboot-2.0.0-r_s2881_Fallback Thu Oct  1 17:07:49 MDT 2009 starting...
(0,1) link=00
(1,0) link=00
02 nodes initialized.
core0 started:  01
started ap apicid:
SBLink=02
NC node|link=02
Ram1.00
Ram1.01
Ram2.00
RAM end at 0x00100000 kB
Ram2.01
RAM end at 0x00200000 kB
Ram3
Initializing memory:  done
Initializing memory:  done
Ram4
v_esp=000cfe38
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Jumping to image.
Check fallback/payload
Check fallback/coreboot_ram
Stage: load fallback/coreboot_ram @ 16384/245760 bytes, enter @ 4000
Stage: done loading.
Jumping to image.
coreboot-2.0.0-r_s2881_Fallback Thu Oct  1 17:07:49 MDT 2009 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:18.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:09.0: enabled 1, 0 resources
PCI: 00:09.1: enabled 1, 0 resources
PCI: 00:0a.0: enabled 1, 0 resources
PCI: 00:0a.1: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:00.2: enabled 0, 0 resources
PCI: 00:01.0: enabled 0, 0 resources
PCI: 00:05.0: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PNP: 002e.0: enabled 1, 3 resources
PNP: 002e.1: enabled 0, 2 resources
PNP: 002e.2: enabled 1, 2 resources
PNP: 002e.3: enabled 0, 2 resources
PNP: 002e.5: enabled 1, 4 resources
PNP: 002e.6: enabled 0, 1 resources
PNP: 002e.7: enabled 0, 3 resources
PNP: 002e.8: enabled 0, 0 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 0, 0 resources
PNP: 002e.b: enabled 1, 2 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:01.2: enabled 1, 0 resources
PCI: 00:01.3: enabled 1, 0 resources
I2C: 00:50: enabled 1, 0 resources
I2C: 00:51: enabled 1, 0 resources
I2C: 00:52: enabled 1, 0 resources
I2C: 00:53: enabled 1, 0 resources
I2C: 00:54: enabled 1, 0 resources
I2C: 00:55: enabled 1, 0 resources
I2C: 00:56: enabled 1, 0 resources
I2C: 00:57: enabled 1, 0 resources
I2C: 00:2d: enabled 1, 0 resources
I2C: 00:2a: enabled 1, 0 resources
I2C: 00:49: enabled 1, 0 resources
I2C: 00:4a: enabled 1, 0 resources
PCI: 00:01.5: enabled 0, 0 resources
PCI: 00:01.6: enabled 0, 0 resources
PCI: 00:18.1: enabled 1, 0 resources
PCI: 00:18.2: enabled 1, 0 resources
PCI: 00:18.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:18.0: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:09.0: enabled 1, 0 resources
    PCI: 00:09.1: enabled 1, 0 resources
    PCI: 00:0a.0: enabled 1, 0 resources
    PCI: 00:0a.1: enabled 1, 0 resources
   PCI: 00:00.1: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.0: enabled 1, 0 resources
    PCI: 00:00.1: enabled 1, 0 resources
    PCI: 00:00.2: enabled 0, 0 resources
    PCI: 00:01.0: enabled 0, 0 resources
    PCI: 00:05.0: enabled 1, 0 resources
    PCI: 00:06.0: enabled 1, 0 resources
   PCI: 00:01.0: enabled 1, 0 resources
    PNP: 002e.0: enabled 1, 3 resources
    PNP: 002e.1: enabled 0, 2 resources
    PNP: 002e.2: enabled 1, 2 resources
    PNP: 002e.3: enabled 0, 2 resources
    PNP: 002e.5: enabled 1, 4 resources
    PNP: 002e.6: enabled 0, 1 resources
    PNP: 002e.7: enabled 0, 3 resources
    PNP: 002e.8: enabled 0, 0 resources
    PNP: 002e.9: enabled 0, 0 resources
    PNP: 002e.a: enabled 0, 0 resources
    PNP: 002e.b: enabled 1, 2 resources
   PCI: 00:01.1: enabled 1, 0 resources
   PCI: 00:01.2: enabled 1, 0 resources
   PCI: 00:01.3: enabled 1, 0 resources
    I2C: 00:50: enabled 1, 0 resources
    I2C: 00:51: enabled 1, 0 resources
    I2C: 00:52: enabled 1, 0 resources
    I2C: 00:53: enabled 1, 0 resources
    I2C: 00:54: enabled 1, 0 resources
    I2C: 00:55: enabled 1, 0 resources
    I2C: 00:56: enabled 1, 0 resources
    I2C: 00:57: enabled 1, 0 resources
    I2C: 00:2d: enabled 1, 0 resources
    I2C: 00:2a: enabled 1, 0 resources
    I2C: 00:49: enabled 1, 0 resources
    I2C: 00:4a: enabled 1, 0 resources
   PCI: 00:01.5: enabled 0, 0 resources
   PCI: 00:01.6: enabled 0, 0 resources
  PCI: 00:18.1: enabled 1, 0 resources
  PCI: 00:18.2: enabled 1, 0 resources
  PCI: 00:18.3: enabled 1, 0 resources
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
  PCI: 00:18.3 siblings=0
CPU: APIC: 00 enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] enabled
  PCI: 00:19.3 siblings=0
CPU: APIC: 01 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:19.0 [1022/1100] enabled
PCI: 00:19.1 [1022/1101] enabled
PCI: 00:19.2 [1022/1102] enabled
PCI: 00:19.3 [1022/1103] enabled

I don't see 14e4/1648 above.  Is that the problem?  Any suggestions?  
Thanks.

-- 
Hugh Greenberg
Los Alamos National Laboratory, CCS-1
Email: hng at lanl.gov
Phone: (505) 665-6471



Myles Watson wrote:
> On Thu, Oct 1, 2009 at 8:54 AM, Hugh Greenberg <hng at lanl.gov> wrote:
>   
>> I am trying to put coreboot v2 on a tyan s2881 and I would like to use
>> seabios and gpxe for the payload .  I successfully created the coreboot.rom
>> by following the s2881 build tutorial and seabios tutorial.  I then tried to
>> add gpxe to the coreboot rom and I received this output from cbfstool:
>>
>> $./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add
>> ../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99
>> Could not add the file to CBFS, it's probably too big.
>>
>> $ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print
>> ../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 262144,
>> romsize 524288, offset 0x0
>> Alignment: 64 bytes
>>     
>
>   
>> Name                           Offset     Type         Size
>> normal/payload                 0x0        payload      65592
>> normal/coreboot_ram            0x10080    stage        56173
>> fallback/payload               0x1dc40    payload      65592
>> fallback/coreboot_ram          0x2dcc0    stage        55651
>>                              0x3b680    null         18744
>>     
> I didn't see how big the gpxe ROM is.  That might influence which of
> these choices you make.
>
> You could:
> 1. shrink your bootblock (CONFIG_ROM_IMAGE_SIZE)
> 2. do fallback-only (Remove anything that says normal in
> targets/tyan/s2881/s2881/Config.lb)
>
>   
>> I taked to Ron about this and he suggested to try the Kconfig build system
>> as that would create a smaller rom.   That failed and I received this
>> output:
>>     
>
> 3. Apply the attached patch (updated version of one that is waiting to
> be reviewed.)
>
> Thanks,
> Myles
>   



From joe at settoplinux.org  Fri Oct  2 01:24:13 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 19:24:13 -0400
Subject: [coreboot] serialice PCI capture
In-Reply-To: <4AC53929.7090704@coresystems.de>
References: <4AC4B767.2060406@settoplinux.org>	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
	<4AC53929.7090704@coresystems.de>
Message-ID: <f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>




On Fri, 02 Oct 2009 01:20:09 +0200, Stefan Reinauer <stepan at coresystems.de>
wrote:
> Joseph Smith wrote:
>>
>> On Fri, 2 Oct 2009 01:08:45 +0200, Peter Stuge <peter at stuge.se> wrote:
>>   
>>> Joseph Smith wrote:
>>>     
>>>> how hard would it be to get serialice to do the same with the bios?
>>>>       
>>> I think it already does. PCI is just IO, so it gets handled.
>>>
>>>     
>> Huh? PCI has IO space allocated, but I am talking about actual PCI
config
>> registers... 
>>
>>   
> Just try it :-)
> 
Ok, will do, how long does it take to get through a 512k bios image?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Fri Oct  2 01:39:57 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Oct 2009 01:39:57 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>
References: <4AC4B767.2060406@settoplinux.org>	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
	<4AC53929.7090704@coresystems.de>
	<f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>
Message-ID: <4AC53DCD.8090902@coresystems.de>

Joseph Smith wrote:
> Ok, will do, how long does it take to get through a 512k bios image?
>
>   

Running a complete image will require several days...


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From mylesgw at gmail.com  Fri Oct  2 01:41:07 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 17:41:07 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <4AC539FC.7070908@lanl.gov>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<4AC539FC.7070908@lanl.gov>
Message-ID: <8EFC08F8964C431D9737758FAFAE183A@chimp>

> Thanks.  I took option number 2.  It flashed successfully, however, gpxe
> does not seem to be starting.  Here is the output from the
> coreboot/seabios:

>    PCI: 00:01.5: enabled 0, 0 resources
>    PCI: 00:01.6: enabled 0, 0 resources
>   PCI: 00:18.1: enabled 1, 0 resources
>   PCI: 00:18.2: enabled 1, 0 resources
>   PCI: 00:18.3: enabled 1, 0 resources
> APIC_CLUSTER: 0 enabled
> PCI_DOMAIN: 0000 enabled
>   PCI: 00:18.3 siblings=0
> CPU: APIC: 00 enabled
> PCI: 00:19.0 [1022/1100] enabled
> PCI: 00:19.1 [1022/1101] enabled
> PCI: 00:19.2 [1022/1102] enabled
> PCI: 00:19.3 [1022/1103] enabled
>   PCI: 00:19.3 siblings=0
> CPU: APIC: 01 enabled
> PCI: pci_scan_bus for bus 00
> PCI: 00:18.0 [1022/1100] enabled
> PCI: 00:18.1 [1022/1101] enabled
> PCI: 00:18.2 [1022/1102] enabled
> PCI: 00:18.3 [1022/1103] enabled
> PCI: 00:19.0 [1022/1100] enabled
> PCI: 00:19.1 [1022/1101] enabled
> PCI: 00:19.2 [1022/1102] enabled
> PCI: 00:19.3 [1022/1103] enabled
> 
> I don't see 14e4/1648 above.  Is that the problem?
It should come after this.  The full log would be helpful.  Do you see the
device's PCI device number that you see in lspci?  eg. PCI: 00:01.5

Thanks,
Myles




From kevin at koconnor.net  Fri Oct  2 01:42:15 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 1 Oct 2009 19:42:15 -0400
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC45990.4090409@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
	<20090930235721.GA1833@morn.localdomain> <4AC45990.4090409@gmx.net>
Message-ID: <20091001234215.GA4423@morn.localdomain>

On Thu, Oct 01, 2009 at 09:26:08AM +0200, Carl-Daniel Hailfinger wrote:
> > In particular, I'd like to be able to go into my "normal" directory
> > and run "svn up", "make", and then "flashrom" - and be fairly
> > confident that I didn't just blow up my image.
[...]
> Two problem areas need to be looked at:
> 1. Can the new build reuse the old bootblock? Does the new build have to
> know the old bootblock?
> 2. How do you merge old and new images?
[...]
> 2. is a bit more problematic regardless of whether you have v2 or v3. If
> you don't want to reflash the old parts of the image, you can't rename
> them either. If the old part was called "fallback", it will still be
> called "fallback" after flashing some new parts into the ROM. That means
> each time you reflash, the new part's name will be the opposite of the
> old part's name. Of course, with such a system, calling these things
> "fallback" and "normal" makes no sense anymore. After all, we always
> want to boot the newly flashed image first and the name doesn't tell us
> which one is new.

I'd always want to flash and boot the image I put in the "normal"
directory.  I don't want to rename "fallback" - I don't want to change
it at all.

-Kevin



From hng at lanl.gov  Fri Oct  2 01:46:02 2009
From: hng at lanl.gov (Hugh Greenberg)
Date: Thu, 01 Oct 2009 17:46:02 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <8EFC08F8964C431D9737758FAFAE183A@chimp>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<4AC539FC.7070908@lanl.gov>
	<8EFC08F8964C431D9737758FAFAE183A@chimp>
Message-ID: <4AC53F3A.6050503@lanl.gov>

This is all the output I get on the serial port.  How can I get a full 
log?  I do not see the device number, its: 02:09.0 .

-- 
Hugh Greenberg
Los Alamos National Laboratory, CCS-1
Email: hng at lanl.gov
Phone: (505) 665-6471



Myles Watson wrote:
>> Thanks.  I took option number 2.  It flashed successfully, however, gpxe
>> does not seem to be starting.  Here is the output from the
>> coreboot/seabios:
>>     
>
>   
>>    PCI: 00:01.5: enabled 0, 0 resources
>>    PCI: 00:01.6: enabled 0, 0 resources
>>   PCI: 00:18.1: enabled 1, 0 resources
>>   PCI: 00:18.2: enabled 1, 0 resources
>>   PCI: 00:18.3: enabled 1, 0 resources
>> APIC_CLUSTER: 0 enabled
>> PCI_DOMAIN: 0000 enabled
>>   PCI: 00:18.3 siblings=0
>> CPU: APIC: 00 enabled
>> PCI: 00:19.0 [1022/1100] enabled
>> PCI: 00:19.1 [1022/1101] enabled
>> PCI: 00:19.2 [1022/1102] enabled
>> PCI: 00:19.3 [1022/1103] enabled
>>   PCI: 00:19.3 siblings=0
>> CPU: APIC: 01 enabled
>> PCI: pci_scan_bus for bus 00
>> PCI: 00:18.0 [1022/1100] enabled
>> PCI: 00:18.1 [1022/1101] enabled
>> PCI: 00:18.2 [1022/1102] enabled
>> PCI: 00:18.3 [1022/1103] enabled
>> PCI: 00:19.0 [1022/1100] enabled
>> PCI: 00:19.1 [1022/1101] enabled
>> PCI: 00:19.2 [1022/1102] enabled
>> PCI: 00:19.3 [1022/1103] enabled
>>
>> I don't see 14e4/1648 above.  Is that the problem?
>>     
> It should come after this.  The full log would be helpful.  Do you see the
> device's PCI device number that you see in lspci?  eg. PCI: 00:01.5
>
> Thanks,
> Myles
>
>   



From info at coresystems.de  Fri Oct  2 01:49:25 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 02 Oct 2009 01:49:25 +0200
Subject: [coreboot] build service results for r4706
Message-ID: <E1MtVOn-0007Ok-5g@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4706 to
the coreboot repository. This caused the following 
changes:

Change Log:
Support variables for MMX and SSE. These would be used in
e.g. Makefile.romcc.inc to enable certain features.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>




Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4706&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4706&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Fri Oct  2 01:49:48 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 16:49:48 -0700
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <4AC539FC.7070908@lanl.gov>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<4AC539FC.7070908@lanl.gov>
Message-ID: <13426df10910011649p6c98e6f0l3c3626f5392696a8@mail.gmail.com>

looking better.

Did I miss something? I don't see seabios in there.

ron



From rminnich at gmail.com  Fri Oct  2 01:50:29 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 16:50:29 -0700
Subject: [coreboot] serialice PCI capture
In-Reply-To: <4AC53DCD.8090902@coresystems.de>
References: <4AC4B767.2060406@settoplinux.org>
	<20091001230845.23180.qmail@stuge.se>
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>
	<4AC53929.7090704@coresystems.de>
	<f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>
	<4AC53DCD.8090902@coresystems.de>
Message-ID: <13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>

not a couple days! Why, I'm up to SPD dump in  a few hours!

ron



From kevin at koconnor.net  Fri Oct  2 01:58:25 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Thu, 1 Oct 2009 19:58:25 -0400
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <1254380991.21870.21.camel@tetris>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
Message-ID: <20091001235825.GA29687@morn.localdomain>

On Thu, Oct 01, 2009 at 09:09:50AM +0200, Patrick Georgi wrote:
> My plan for it, pending any better solution:
> - unify the decision stuff into a single place
> - move everything but the decision stuff out of the bootblock (so it
>   essentially becomes immutable across updates)
> - extend kconfig so it knows how to update existing images (by adding
>   new files)
> - somehow make flashrom smart enough to safely update the flash

Thanks - that sounds like a big improvement.

> Open issues are:
> We need early rom mapping and CMOS access for all boards. So far, only
> the boards with failover layout are somewhat guaranteed to have code for
> that.

Proprietary BIOS have a cmos variable for a similar purpose - 0x0f
(RESET CODE).  Coreboot could probably use the same variable -
defining one variable for all boards is probably simpler than having
to define it on every board.

-Kevin



From rminnich at gmail.com  Fri Oct  2 02:04:39 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 17:04:39 -0700
Subject: [coreboot] SPD sanity check
Message-ID: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>

This looks to me like I'm mostly reading garbage from SPD -- comments anyone?

dimm 50
00: bad device: 01


dimm 51
00: bad device: 01


dimm 52
00: bad device: 01


dimm 53
00: bad device: 01


dimm 54
00: ad db de c0 01 00 00 00 01 f0 fa fa 00 00 00 d9
10: 00 00 00 00 00 00 6c 01 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

dimm 55
00: bad device: 01


dimm 56
00: bad device: 01


dimm 57
00: 80 08 08 0d 0a 60 48 00 05 50 60 02 02 08 08 00
10: 0c 04 38 00 01 00 01 50 60 50 60 3c 1e 3c 28 40
20: 35 47 15 27 3c 28 1e 00 00 37 4b 80 23 2d 0f 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 6b
40: ce 00 00 00 00 00 00 00 01 4d 33 20 39 33 54 33
50: 32 35 33 46 5a 30 2d 43 43 43 20 30 46 05 17 46
60: 04 cb 50 00 59 42 43 35 36 30 50 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 49 d6 06 71 16 23 33 80 30 45 52 00 07 05 ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: 01 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff



From rminnich at gmail.com  Fri Oct  2 02:07:33 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 17:07:33 -0700
Subject: [coreboot] proposal: remove Config.lb from dell s1850
Message-ID: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>

Nobody but me cares about the board. I am wondering about making the
Dell the pioneer here: remove Options.lb and Config.lb so that it can
no longer
be built the old way.

Comments?

ron



From svn at coreboot.org  Fri Oct  2 02:08:01 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 02:08:01 +0200
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
Message-ID: <mailman.3778.1355071627.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-10-02 02:08:00 +0200 (Fri, 02 Oct 2009)
New Revision: 4707

Removed:
   trunk/coreboot-v2/targets/totalimpact/
Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
Log:
Drop remainders of the removed Totalimpact board. Fix typos.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-01 23:22:50 UTC (rev 4706)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-02 00:08:00 UTC (rev 4707)
@@ -1,5 +1,5 @@
 config BOARD_DELL_S1850
-	bool "Dell S1850"
+	bool "S1850"
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_MPGA604
 	select NORTHBRIDGE_INTEL_E7520
@@ -8,7 +8,7 @@
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
 	help
-	  Dell S1850mainboard.
+	  Dell S1850 mainboard.
 
 config MAINBOARD_DIR
 	string




From peter at stuge.se  Fri Oct  2 02:09:07 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 02:09:07 +0200
Subject: [coreboot] proposal: remove Config.lb from dell s1850
In-Reply-To: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
References: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
Message-ID: <20091002000908.1958.qmail@stuge.se>

ron minnich wrote:
> Nobody but me cares about the board.

I built an image for someone, maybe a year ago. :)


> I am wondering about making the Dell the pioneer here: remove
> Options.lb and Config.lb so that it can no longer be built the old
> way.
> 
> Comments?

I think that's fine.


//Peter



From peter at stuge.se  Fri Oct  2 02:11:57 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 02:11:57 +0200
Subject: [coreboot] [v2] r4707 - in
	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
Message-ID: <20091002001157.2403.qmail@stuge.se>

svn at coreboot.org wrote:
> +	bool "S1850"

Is this a PowerEdge S1850 ?


//Peter



From stepan at coresystems.de  Fri Oct  2 02:18:38 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Oct 2009 02:18:38 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>
References: <4AC4B767.2060406@settoplinux.org>	
	<20091001230845.23180.qmail@stuge.se>	
	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>	
	<4AC53929.7090704@coresystems.de>	
	<f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>	
	<4AC53DCD.8090902@coresystems.de>
	<13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>
Message-ID: <4AC546DE.2010306@coresystems.de>

ron minnich wrote:
> not a couple days! Why, I'm up to SPD dump in  a few hours!
>   
Some BIOSes do an extensive RAM check, and the protocol limits checking
RAM (or copying) to something around 16MB/h

The checks can easily be circumvented with gdb, but stuff like
optimizing memory copy is tricky..

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From info at coresystems.de  Fri Oct  2 02:33:12 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 02 Oct 2009 02:33:12 +0200
Subject: [coreboot] build service results for r4707
Message-ID: <E1MtW5A-0001vh-5d@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4707 to
the coreboot repository. This caused the following 
changes:

Change Log:
Drop remainders of the removed Totalimpact board. Fix typos.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4707&device=ep405pc&vendor=embeddedplanet&num=2
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4707&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From joe at settoplinux.org  Fri Oct  2 03:21:39 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 21:21:39 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
Message-ID: <4AC555A3.1000700@settoplinux.org>

On 10/01/2009 08:04 PM, ron minnich wrote:
> This looks to me like I'm mostly reading garbage from SPD -- comments anyone?
>
> dimm 50
> 00: bad device: 01
>
>
> dimm 51
> 00: bad device: 01
>
>
> dimm 52
> 00: bad device: 01
>
>
> dimm 53
> 00: bad device: 01
>
>
> dimm 54
> 00: ad db de c0 01 00 00 00 01 f0 fa fa 00 00 00 d9
> 10: 00 00 00 00 00 00 6c 01 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> dimm 55
> 00: bad device: 01
>
>
> dimm 56
> 00: bad device: 01
>
>
> dimm 57
> 00: 80 08 08 0d 0a 60 48 00 05 50 60 02 02 08 08 00
> 10: 0c 04 38 00 01 00 01 50 60 50 60 3c 1e 3c 28 40
> 20: 35 47 15 27 3c 28 1e 00 00 37 4b 80 23 2d 0f 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 6b
> 40: ce 00 00 00 00 00 00 00 01 4d 33 20 39 33 54 33
> 50: 32 35 33 46 5a 30 2d 43 43 43 20 30 46 05 17 46
> 60: 04 cb 50 00 59 42 43 35 36 30 50 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 49 d6 06 71 16 23 33 80 30 45 52 00 07 05 ff
> 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f0: 01 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>
That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 
and 0x51? What SuperIO is this?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Fri Oct  2 03:24:25 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 21:24:25 -0400
Subject: [coreboot] serialice PCI capture
In-Reply-To: <13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>
References: <4AC4B767.2060406@settoplinux.org>	<20091001230845.23180.qmail@stuge.se>	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>	<4AC53929.7090704@coresystems.de>	<f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>	<4AC53DCD.8090902@coresystems.de>
	<13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>
Message-ID: <4AC55649.20006@settoplinux.org>

On 10/01/2009 07:50 PM, ron minnich wrote:
> not a couple days! Why, I'm up to SPD dump in  a few hours!
>
> ron
>
SerialICE does SPD Dumps too?
Capturing SPD reads as well would make writing raminit a snap :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Fri Oct  2 04:11:54 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 01 Oct 2009 22:11:54 -0400
Subject: [coreboot] SerialICE Build Error
Message-ID: <4AC5616A.7010803@settoplinux.org>

[root at smitty5m SerialICE-1.0]# make
gcc -O2 -Wall -o romcc util/romcc.c
util/romcc.c: In function ?simplify_load?:
util/romcc.c:9925: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c:9926: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c:9927: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c: In function ?get_const_pool_ref?:
util/romcc.c:23846: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
util/romcc.c:23851: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
util/romcc.c: In function ?print_sdecl?:
util/romcc.c:24660: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
./romcc -mcpu=i386 -I. -Imainboard -o serialice.S serialice.c
i386-elf-as -o serialice.o serialice.S
make: i386-elf-as: Command not found
make: *** [serialice.o] Error 127

Any ideas?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From mylesgw at gmail.com  Fri Oct  2 04:33:02 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 1 Oct 2009 20:33:02 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <4AC53F3A.6050503@lanl.gov>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<4AC539FC.7070908@lanl.gov>
	<8EFC08F8964C431D9737758FAFAE183A@chimp>
	<4AC53F3A.6050503@lanl.gov>
Message-ID: <DCAA3EBF7104406586ED792B4ABD41AA@chimp>



> -----Original Message-----
> From: Hugh Greenberg [mailto:hng at lanl.gov]
> Sent: Thursday, October 01, 2009 5:46 PM
> To: Myles Watson
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] tyan s2881 with seabios and gpxe
> 
> This is all the output I get on the serial port.  How can I get a full
> log?  I do not see the device number, its: 02:09.0 .
I thought you'd truncated it.  It's hanging for some reason.  I've never
seen Coreboot hang there.

> 
> --
> Hugh Greenberg
> Los Alamos National Laboratory, CCS-1
> Email: hng at lanl.gov
> Phone: (505) 665-6471
> 
> 
> 
> Myles Watson wrote:
> >> Thanks.  I took option number 2.  It flashed successfully, however,
> gpxe
> >> does not seem to be starting.  Here is the output from the
> >> coreboot/seabios:
> >>
> >
> >
> >>    PCI: 00:01.5: enabled 0, 0 resources
> >>    PCI: 00:01.6: enabled 0, 0 resources
> >>   PCI: 00:18.1: enabled 1, 0 resources
> >>   PCI: 00:18.2: enabled 1, 0 resources
> >>   PCI: 00:18.3: enabled 1, 0 resources
> >> APIC_CLUSTER: 0 enabled
> >> PCI_DOMAIN: 0000 enabled
> >>   PCI: 00:18.3 siblings=0
> >> CPU: APIC: 00 enabled
> >> PCI: 00:19.0 [1022/1100] enabled
> >> PCI: 00:19.1 [1022/1101] enabled
> >> PCI: 00:19.2 [1022/1102] enabled
> >> PCI: 00:19.3 [1022/1103] enabled
> >>   PCI: 00:19.3 siblings=0
> >> CPU: APIC: 01 enabled
> >> PCI: pci_scan_bus for bus 00
> >> PCI: 00:18.0 [1022/1100] enabled
> >> PCI: 00:18.1 [1022/1101] enabled
> >> PCI: 00:18.2 [1022/1102] enabled
> >> PCI: 00:18.3 [1022/1103] enabled
> >> PCI: 00:19.0 [1022/1100] enabled
> >> PCI: 00:19.1 [1022/1101] enabled
> >> PCI: 00:19.2 [1022/1102] enabled
> >> PCI: 00:19.3 [1022/1103] enabled
> >>
> >> I don't see 14e4/1648 above.  Is that the problem?
> >>
> > It should come after this.  The full log would be helpful.  Do you see
> the
> > device's PCI device number that you see in lspci?  eg. PCI: 00:01.5

The next thing in my log is:

PCI: Using configuration type 1

Do you want to try Rev 4645?  4646 was the last one that touched that code.

Sorry I'm not more help.

Thanks,
Myles




From svn at coreboot.org  Fri Oct  2 05:36:31 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 05:36:31 +0200
Subject: [coreboot] [v2] r4708 - in trunk/coreboot-v2/src: config mainboard
Message-ID: <mailman.3779.1355071627.16123.coreboot@coreboot.org>

Author: rminnich
Date: 2009-10-02 05:36:30 +0200 (Fri, 02 Oct 2009)
New Revision: 4708

Removed:
   trunk/coreboot-v2/src/mainboard/motorola/
Modified:
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/mainboard/Kconfig
Log:
Remove motorola PPC boards. These have lain untouched and unused by anyone
for years. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-10-02 00:08:00 UTC (rev 4707)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-10-02 03:36:30 UTC (rev 4708)
@@ -1225,49 +1225,3 @@
 	comment "Leave a hole for PCIe config space in the device allocator"
 end
 
-###############################################
-# Board specific options
-###############################################
-
-###############################################
-# Options for motorola/sandpoint
-###############################################
-define CONFIG_SANDPOINT_ALTIMUS
-	default 0
-	export never
-	comment "Configure Sandpoint with Altimus PMC"
-end
-define CONFIG_SANDPOINT_TALUS
-	default 0
-	export never
-	comment "Configure Sandpoint with Talus PMC"
-end
-define CONFIG_SANDPOINT_UNITY
-	default 0
-	export never
-	comment "Configure Sandpoint with Unity PMC"
-end
-define CONFIG_SANDPOINT_VALIS
-	default 0
-	export never
-	comment "Configure Sandpoint with Valis PMC"
-end
-define CONFIG_SANDPOINT_GYRUS
-	default 0
-	export never
-	comment "Configure Sandpoint with Gyrus PMC"
-end
-
-###############################################
-# Options for totalimpact/briq
-###############################################
-define CONFIG_BRIQ_750FX
-	default 0
-	export never
-	comment "Configure briQ with PowerPC 750FX"
-end
-define CONFIG_BRIQ_7400
-	default 0
-	export never
-	comment "Configure briQ with PowerPC G4"
-end

Modified: trunk/coreboot-v2/src/mainboard/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-02 00:08:00 UTC (rev 4707)
+++ trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-02 03:36:30 UTC (rev 4708)
@@ -62,8 +62,6 @@
 	bool "Lippert"
 config VENDOR_MITAC
 	bool "Mitac"
-config VENDOR_MOTOROLA
-	bool "Motorola"
 config VENDOR_MSI
 	bool "MSI"
 config VENDOR_NEC
@@ -246,11 +244,6 @@
 
 config MAINBOARD_VENDOR
 	string
-	default "Motorola"
-	depends on VENDOR_MOTOROLA
-
-config MAINBOARD_VENDOR
-	string
 	default "MSI"
 	depends on VENDOR_MSI
 




From rminnich at gmail.com  Fri Oct  2 05:37:22 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 20:37:22 -0700
Subject: [coreboot] remove motorola PPC boards
In-Reply-To: <2831fecf0910011016q2444f381ic5d92dbcc94d8e89@mail.gmail.com>
References: <13426df10910010959i784bab8bwc107cc0264d1c56c@mail.gmail.com>
	<2831fecf0910011016q2444f381ic5d92dbcc94d8e89@mail.gmail.com>
Message-ID: <13426df10910012037t4ce0e234rba8b3ced01e67a0f@mail.gmail.com>

Committed revision 4708.

Just one left. The embeddedplanet. I think we can leave the arch/ppc
stuff in there, because it shows people how we can do heterogeneity if
we ever want to.

ron



From rminnich at gmail.com  Fri Oct  2 05:39:40 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 20:39:40 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <4AC555A3.1000700@settoplinux.org>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
Message-ID: <13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>

On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith <joe at settoplinux.org> wrote:

> That doesn't look right at all! Shouldn't your dimms be at smbus 0x50 and
> 0x51? What SuperIO is this?

not at all, DIMMS can run from 50-57.

I think one of those SPD dumps is good, one bad, but I want to see
what anyone else thinks.

ron



From rminnich at gmail.com  Fri Oct  2 05:41:01 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 20:41:01 -0700
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
In-Reply-To: <20091002001157.2403.qmail@stuge.se>
References: <20091002001157.2403.qmail@stuge.se>
Message-ID: <13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>

On Thu, Oct 1, 2009 at 5:11 PM, Peter Stuge <peter at stuge.se> wrote:
> svn at coreboot.org wrote:
>> + ? ? bool "S1850"
>
> Is this a PowerEdge S1850 ?

yes.

ron



From rminnich at gmail.com  Fri Oct  2 05:43:43 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 20:43:43 -0700
Subject: [coreboot] patch: remove embeddedplanet
Message-ID: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>

attached.
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From Cristi.Magherusan at net.utcluj.ro  Fri Oct  2 05:49:30 2009
From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 02 Oct 2009 06:49:30 +0300
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <4AC5616A.7010803@settoplinux.org>
References: <4AC5616A.7010803@settoplinux.org>
Message-ID: <1254455370.28556.31.camel@ufo>

On Thu, 2009-10-01 at 22:11 -0400, Joseph Smith wrote:
> [root at smitty5m SerialICE-1.0]# make
> gcc -O2 -Wall -o romcc util/romcc.c
> util/romcc.c: In function ?simplify_load?:
> util/romcc.c:9925: warning: dereferencing type-punned pointer will break 
> strict-aliasing rules
> util/romcc.c:9926: warning: dereferencing type-punned pointer will break 
> strict-aliasing rules
> util/romcc.c:9927: warning: dereferencing type-punned pointer will break 
> strict-aliasing rules
> util/romcc.c: In function ?get_const_pool_ref?:
> util/romcc.c:23846: warning: format ?%ld? expects type ?long int?, but 
> argument 3 has type ?size_t?
> util/romcc.c:23851: warning: format ?%ld? expects type ?long int?, but 
> argument 3 has type ?size_t?
> util/romcc.c: In function ?print_sdecl?:
> util/romcc.c:24660: warning: format ?%ld? expects type ?long int?, but 
> argument 3 has type ?size_t?
> ./romcc -mcpu=i386 -I. -Imainboard -o serialice.S serialice.c
> i386-elf-as -o serialice.o serialice.S
> make: i386-elf-as: Command not found
> make: *** [serialice.o] Error 127
> 
> Any ideas?
Try the attached patch

Signed-off-by: Cristi M?gheru?an <cristi.magherusan at net.utcluj.ro>

Regards,
Cristi

-- 
Ing. Cristi M?gheru?an, System/Network Engineer
Technical University of Cluj-Napoca, Romania
http://cc.utcluj.ro  +40264 401247
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From info at coresystems.de  Fri Oct  2 06:01:16 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 02 Oct 2009 06:01:16 +0200
Subject: [coreboot] build service results for r4708
Message-ID: <E1MtZKW-00025O-9U@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "rminnich" checked in revision 4708 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove motorola PPC boards. These have lain untouched and unused by anyone
for years.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>


Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4708&device=ep405pc&vendor=embeddedplanet&num=2


If something broke during this checkin please be a pain 
in rminnich's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From rminnich at gmail.com  Fri Oct  2 06:03:46 2009
From: rminnich at gmail.com (ron minnich)
Date: Thu, 1 Oct 2009 21:03:46 -0700
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <1254455370.28556.31.camel@ufo>
References: <4AC5616A.7010803@settoplinux.org> <1254455370.28556.31.camel@ufo>
Message-ID: <13426df10910012103i24d63909s52d22294f8bc216b@mail.gmail.com>

This might work but you're probably better off building with the cross
tools I expect.

ron



From Cristi.Magherusan at net.utcluj.ro  Fri Oct  2 06:40:24 2009
From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 02 Oct 2009 07:40:24 +0300
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <13426df10910012103i24d63909s52d22294f8bc216b@mail.gmail.com>
References: <4AC5616A.7010803@settoplinux.org> <1254455370.28556.31.camel@ufo>
	<13426df10910012103i24d63909s52d22294f8bc216b@mail.gmail.com>
Message-ID: <1254458424.28556.38.camel@ufo>

On Thu, 2009-10-01 at 21:03 -0700, ron minnich wrote:
> This might work but you're probably better off building with the cross
> tools I expect.
> 
> ron
Yes, maybe those work better, but the problem with them is that there's
no uniform name across distributions.

My approach needs the 32bit toolchain to be installed on x86-64, with no
assumption on the cross-prefix of the binaries, but the toolchain must
support multilib in order for it to work.

Cristi

-- 
Ing. Cristi M?gheru?an, System/Network Engineer
Technical University of Cluj-Napoca, Romania
http://cc.utcluj.ro  +40264 401247
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From sander at humilis.net  Fri Oct  2 10:22:00 2009
From: sander at humilis.net (Sander)
Date: Fri, 2 Oct 2009 10:22:00 +0200
Subject: [coreboot] Supermicro X7SLA-H supported? (Intel 945GC + ICH7R)
In-Reply-To: <4AC1FDA8.10001@gmx.net>
References: <20090916113434.GA6160@cumulus> <4ABE6F2D.80104@gmx.net>
	<20090928135300.GA16473@cumulus> <4AC1FDA8.10001@gmx.net>
Message-ID: <20091002082159.GA6386@cumulus>

Hello Carl-Daniel,

Carl-Daniel Hailfinger wrote (ao):
> On 28.09.2009 15:53, Sander wrote:
> > Carl-Daniel Hailfinger wrote (ao):
> >> On 16.09.2009 13:34, Sander wrote:
> >>     
> >>> Supermicro X7SLA-H motherboard[2].
> >>>       
> >> [...] Of course, to
> >> recover the flash chip on your board, that flash chip should be in a
> >> socket (or have a SPI recovery header).
> >
> > I've just received the motherboard and it has a SPI BIOS with no header
> > whatsoever. So, sadly, no coreboot on this one.
> 
> Look for the flash chip(s). Probably near the ATX power connector, 8-pin
> chips, usually with a small colored dot and/or a sticker on top of them.
> If you peel off the sticker (if any), you should see the manufacturer
> and model number (probably 25...). Maybe you can find someone to solder
> a socket in place.

Hehe, I like that, but that is a bit too much for me I'm affraid ;-)

Thanks for the tip though.

	Sander

-- 
Humilis IT Services and Solutions
http://www.humilis.net



From patrick at georgi-clan.de  Fri Oct  2 11:54:19 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 02 Oct 2009 11:54:19 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <20091001235825.GA29687@morn.localdomain>
References: <1254343315.9254.20.camel@tetris>
	<20090930205626.25395.qmail@stuge.se>
	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
	<20091001235825.GA29687@morn.localdomain>
Message-ID: <4AC5CDCB.7080901@georgi-clan.de>

Am 02.10.2009 01:58, schrieb Kevin O'Connor:
> Proprietary BIOS have a cmos variable for a similar purpose - 0x0f
> (RESET CODE).  Coreboot could probably use the same variable -
> defining one variable for all boards is probably simpler than having
> to define it on every board.
That's not the issue, and our cmos.layout handling already takes care of 
writing to the "right" location without more effort.
We need to have access to CMOS before CAR or raminit, or anything 
interesting happens, really. And I'm not sure if our code supports this 
everywhere already.


Patrick



From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  2 12:04:31 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Oct 2009 12:04:31 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC5CDCB.7080901@georgi-clan.de>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>	<20091001235825.GA29687@morn.localdomain>
	<4AC5CDCB.7080901@georgi-clan.de>
Message-ID: <4AC5D02F.4040305@gmx.net>

On 02.10.2009 11:54, Patrick Georgi wrote:
> We need to have access to CMOS before CAR or raminit, or anything
> interesting happens, really. And I'm not sure if our code supports
> this everywhere already.

IMHO access to CMOS before CAR is unnecessarily painful and I'd like to
keep that out of the targets which don't need it (VIA/AMD).

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Fri Oct  2 12:19:29 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 06:19:29 -0400
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <1254458424.28556.38.camel@ufo>
References: <4AC5616A.7010803@settoplinux.org>	
	<1254455370.28556.31.camel@ufo>	
	<13426df10910012103i24d63909s52d22294f8bc216b@mail.gmail.com>
	<1254458424.28556.38.camel@ufo>
Message-ID: <4AC5D3B1.2090808@settoplinux.org>

On 10/02/2009 12:40 AM, Cristi Magherusan wrote:
> On Thu, 2009-10-01 at 21:03 -0700, ron minnich wrote:
>> This might work but you're probably better off building with the cross
>> tools I expect.
>>
>> ron
> Yes, maybe those work better, but the problem with them is that there's
> no uniform name across distributions.
>
> My approach needs the 32bit toolchain to be installed on x86-64, with no
> assumption on the cross-prefix of the binaries, but the toolchain must
> support multilib in order for it to work.
>
Thanks Cristi I will try your patch. I don't know if it makes a 
difference but I am running Fedora Core 11, and I already have the 
libelf and binutils packages installed, that is why I am a bit 
surprised. Did Fedora put the elf cross building tools in a different 
package on fc11?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From Cristi.Magherusan at net.utcluj.ro  Fri Oct  2 12:38:02 2009
From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 02 Oct 2009 13:38:02 +0300
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <4AC5D3B1.2090808@settoplinux.org>
References: <4AC5616A.7010803@settoplinux.org> <1254455370.28556.31.camel@ufo>
	<13426df10910012103i24d63909s52d22294f8bc216b@mail.gmail.com>
	<1254458424.28556.38.camel@ufo>  <4AC5D3B1.2090808@settoplinux.org>
Message-ID: <1254479882.28556.47.camel@ufo>

On Fri, 2009-10-02 at 06:19 -0400, Joseph Smith wrote:
> On 10/02/2009 12:40 AM, Cristi Magherusan wrote:
> > On Thu, 2009-10-01 at 21:03 -0700, ron minnich wrote:
> >> This might work but you're probably better off building with the cross
> >> tools I expect.
> >>
> >> ron
> > Yes, maybe those work better, but the problem with them is that there's
> > no uniform name across distributions.
> >
> > My approach needs the 32bit toolchain to be installed on x86-64, with no
> > assumption on the cross-prefix of the binaries, but the toolchain must
> > support multilib in order for it to work.
> >
> Thanks Cristi I will try your patch. I don't know if it makes a 
> difference but I am running Fedora Core 11, and I already have the 
> libelf and binutils packages installed, that is why I am a bit 
> surprised. Did Fedora put the elf cross building tools in a different 
> package on fc11?
> 
No idea, but my Ubuntu also had issues with the tools. I guess the
makefile was first written on Suse so there it may be work out of the
box.

Cristi

-- 
Ing. Cristi M?gheru?an, System/Network Engineer
Technical University of Cluj-Napoca, Romania
http://cc.utcluj.ro  +40264 401247
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From knuku at gap.upv.es  Fri Oct  2 12:51:55 2009
From: knuku at gap.upv.es (Knut Kujat)
Date: Fri, 02 Oct 2009 12:51:55 +0200
Subject: [coreboot] Not supported mobo, compile for a similar one?
Message-ID: <4AC5DB4B.8050403@gap.upv.es>

Hi,

first of all I'm new to the coreboot project and just wanted to say
Hello! :)

Now here my question: I have the supermicro mobo *H8QME-2+
http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2+.cfm
*that is not supported by coreboot but there is a similar one at the
coreboot v2 list: H8dmr
http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm.
What would happen if i compile a coreboot.rom for the H8dmr and flash
into the H8QME-2+? What kind of changes do i have to do?

THX and ciao.



From joe at settoplinux.org  Fri Oct  2 13:29:05 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 07:29:05 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
Message-ID: <b6a7d40b945a54c71bc4aa2e2e4f275c@imap.1and1.com>




On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith <joe at settoplinux.org> wrote:
> 
>> That doesn't look right at all! Shouldn't your dimms be at smbus 0x50
and
>> 0x51? What SuperIO is this?
> 
> not at all, DIMMS can run from 50-57.
> 
> I think one of those SPD dumps is good, one bad, but I want to see
> what anyone else thinks.
> 
Ok but I have never seen one that didn't start at 0x50. Unless you have
dimms in sockets 5(0x54) and 8(0x57)???

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  2 13:39:00 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Oct 2009 13:39:00 +0200
Subject: [coreboot] SPD sanity check
In-Reply-To: <b6a7d40b945a54c71bc4aa2e2e4f275c@imap.1and1.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>	<4AC555A3.1000700@settoplinux.org>	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<b6a7d40b945a54c71bc4aa2e2e4f275c@imap.1and1.com>
Message-ID: <4AC5E654.7060705@gmx.net>

On 02.10.2009 13:29, Joseph Smith wrote:
>
> On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich <rminnich at gmail.com> wrote:
>   
>> On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith <joe at settoplinux.org> wrote:
>>
>>     
>>> That doesn't look right at all! Shouldn't your dimms be at smbus 0x50
>>> and 0x51? What SuperIO is this?
>>>       
>> not at all, DIMMS can run from 50-57
>
> Ok but I have never seen one that didn't start at 0x50. Unless you have
> dimms in sockets 5(0x54) and 8(0x57)???
>   

I think I once saw DIMMS at 0x50-0x53 and 0x58-0x5b on a dualprocessor
board with 8 DIMM slots per processor (4 of them populated per
processor), but I could be mistaken.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Fri Oct  2 13:46:37 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 07:46:37 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
Message-ID: <522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>




On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich <rminnich at gmail.com> wrote:
> On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith <joe at settoplinux.org> wrote:
> 
>> That doesn't look right at all! Shouldn't your dimms be at smbus 0x50
and
>> 0x51? What SuperIO is this?
> 
> not at all, DIMMS can run from 50-57.
> 
> I think one of those SPD dumps is good, one bad, but I want to see
> what anyone else thinks.
> 
You know Ron you could always compare the JEDEC registers with the dimms
manufacturers specifications to find out if the register values are good or
not.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  2 13:53:43 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Oct 2009 13:53:43 +0200
Subject: [coreboot] SPD sanity check
In-Reply-To: <522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>	<4AC555A3.1000700@settoplinux.org>	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
Message-ID: <4AC5E9C7.90304@gmx.net>

On 02.10.2009 13:46, Joseph Smith wrote:
> On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich <rminnich at gmail.com> wrote:
>   
>> I think one of those SPD dumps is good, one bad, but I want to see
>> what anyone else thinks.
>>     
> You know Ron you could always compare the JEDEC registers with the dimms
> manufacturers specifications to find out if the register values are good or
> not.
>   

decode-dimms (or decode-dimms.pl) from lm-sensors is extremely useful
for this. Run it on a working system and it will dump the content of all
SPDs and show the meaning of the values stored there.

If you want, you can compare these results with the output of the
coreboot SPD dump.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From joe at settoplinux.org  Fri Oct  2 13:56:00 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 07:56:00 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <4AC5E9C7.90304@gmx.net>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>	<4AC555A3.1000700@settoplinux.org>	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
Message-ID: <e097a2ba4a092632a9f06631efb70f85@imap.1and1.com>




On Fri, 02 Oct 2009 13:53:43 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 02.10.2009 13:46, Joseph Smith wrote:
>> On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich <rminnich at gmail.com>
> wrote:
>>
>>> I think one of those SPD dumps is good, one bad, but I want to see
>>> what anyone else thinks.
>>>
>> You know Ron you could always compare the JEDEC registers with the dimms
>> manufacturers specifications to find out if the register values are good
> or
>> not.
>>
> 
> decode-dimms (or decode-dimms.pl) from lm-sensors is extremely useful
> for this. Run it on a working system and it will dump the content of all
> SPDs and show the meaning of the values stored there.
> 
> If you want, you can compare these results with the output of the
> coreboot SPD dump.
> 
Good idea C-D :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From stepan at coresystems.de  Fri Oct  2 14:29:24 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Oct 2009 14:29:24 +0200
Subject: [coreboot] proposal: remove Config.lb from dell s1850
In-Reply-To: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
References: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
Message-ID: <7CBBC6E4-AD82-4199-84F2-7C6D7A9951B0@coresystems.de>



On Oct 2, 2009, at 2:07, ron minnich <rminnich at gmail.com> wrote:

> Nobody but me cares about the board. I am wondering about making the
> Dell the pioneer here: remove Options.lb and Config.lb so that it can
> no longer
> be built the old way.
>

We will remove all Config.lb files once we have moved over to  
Kconfig.. It's not to be expected that anyone is relying on Config.lb  
for the Dell since it's broken anyways... So if you promise to fix all  
Kconfig builds please go ahead and drop Config.lb ... We should  
refrain from creating a situation where we have to maintain lists for  
which config method to use... There should be one supported way of  
doing things for boards at all times...

Stefan


> Comments?
>
> ron
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From stepan at coresystems.de  Fri Oct  2 14:30:47 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Oct 2009 14:30:47 +0200
Subject: [coreboot] proposal: remove Config.lb from dell s1850
In-Reply-To: <20091002000908.1958.qmail@stuge.se>
References: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
	<20091002000908.1958.qmail@stuge.se>
Message-ID: <39D2A2A2-B57A-4AE1-9116-C36CCF343273@coresystems.de>



On Oct 2, 2009, at 2:09, Peter Stuge <peter at stuge.se> wrote:

> ron minnich wrote:
>> Nobody but me cares about the board.
>
> I built an image for someone, maybe a year ago. :)
>

Did it work?


>
>> I am wondering about making the Dell the pioneer here: remove
>> Options.lb and Config.lb so that it can no longer be built the old
>> way.
>>
>> Comments?
>
> I think that's fine.
>
>
> //Peter
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From stepan at coresystems.de  Fri Oct  2 14:35:02 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Oct 2009 14:35:02 +0200
Subject: [coreboot] serialice PCI capture
In-Reply-To: <4AC55649.20006@settoplinux.org>
References: <4AC4B767.2060406@settoplinux.org>	<20091001230845.23180.qmail@stuge.se>	<6a7f9866bd1977f77d284355cdee180a@imap.1and1.com>	<4AC53929.7090704@coresystems.de>	<f67b113da7cdc42a1f0e903a15474037@imap.1and1.com>	<4AC53DCD.8090902@coresystems.de>
	<13426df10910011650o2db9b4fcg587fab2b9f4d0e19@mail.gmail.com>
	<4AC55649.20006@settoplinux.org>
Message-ID: <E571015D-9CC2-4934-8653-C5134765BFC7@coresystems.de>



On Oct 2, 2009, at 3:24, Joseph Smith <joe at settoplinux.org> wrote:

> On 10/01/2009 07:50 PM, ron minnich wrote:
>> not a couple days! Why, I'm up to SPD dump in  a few hours!
>>
>> ron
>>
> SerialICE does SPD Dumps too?
> Capturing SPD reads as well would make writing raminit a snap :-)
>

It captures _everything_ ... :-)

In theory we could do ram init using a "replay attack" mechanism...

In practice it's more complicated than that as the log shows you init  
for your very configuration only... Modulo you don't easily recognize  
loops and their exit conditions...

Stefan



> -- 
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From stepan at coresystems.de  Fri Oct  2 14:37:03 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 2 Oct 2009 14:37:03 +0200
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <4AC5616A.7010803@settoplinux.org>
References: <4AC5616A.7010803@settoplinux.org>
Message-ID: <FA08DC72-329F-4A9C-82D3-7B0B06354489@coresystems.de>


On Oct 2, 2009, at 4:11, Joseph Smith <joe at settoplinux.org> wrote:

> [root at smitty5m SerialICE-1.0]# make

Install a cross compiler from util/crossgcc or drop the cross  
definitions from the Makefile

> gcc -O2 -Wall -o romcc util/romcc.c
> util/romcc.c: In function ?simplify_load?:
> util/romcc.c:9925: warning: dereferencing type-punned pointer will  
> break strict-aliasing rules
> util/romcc.c:9926: warning: dereferencing type-punned pointer will  
> break strict-aliasing rules
> util/romcc.c:9927: warning: dereferencing type-punned pointer will  
> break strict-aliasing rules
> util/romcc.c: In function ?get_const_pool_ref?:
> util/romcc.c:23846: warning: format ?%ld? expects type ?long  
> int?, but argument 3 has type ?size_t?
> util/romcc.c:23851: warning: format ?%ld? expects type ?long  
> int?, but argument 3 has type ?size_t?
> util/romcc.c: In function ?print_sdecl?:
> util/romcc.c:24660: warning: format ?%ld? expects type ?long  
> int?, but argument 3 has type ?size_t?
> ./romcc -mcpu=i386 -I. -Imainboard -o serialice.S serialice.c
> i386-elf-as -o serialice.o serialice.S
> make: i386-elf-as: Command not found
> make: *** [serialice.o] Error 127
>
> Any ideas?
>
> -- 
> Thanks,
> Joseph Smith
> Set-Top-Linux
> www.settoplinux.org
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>



From svn at coreboot.org  Fri Oct  2 14:45:18 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 14:45:18 +0200
Subject: [coreboot] [v2] r4709 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
Message-ID: <mailman.3780.1355071627.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-10-02 14:45:18 +0200 (Fri, 02 Oct 2009)
New Revision: 4709

Removed:
   trunk/coreboot-v2/targets/motorola/
Modified:
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
Log:
Remove left-over targets/motorola/*, fix Dell PowerEdge 1850 name.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-02 03:36:30 UTC (rev 4708)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-02 12:45:18 UTC (rev 4709)
@@ -1,5 +1,5 @@
 config BOARD_DELL_S1850
-	bool "S1850"
+	bool "PowerEdge 1850"
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_MPGA604
 	select NORTHBRIDGE_INTEL_E7520
@@ -8,7 +8,7 @@
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
 	help
-	  Dell S1850 mainboard.
+	  Dell PowerEdge 1850 mainboard.
 
 config MAINBOARD_DIR
 	string




From uwe at hermann-uwe.de  Fri Oct  2 14:50:35 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Oct 2009 14:50:35 +0200
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
 src/mainboard/dell/s1850 targets
In-Reply-To: <13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
Message-ID: <20091002125035.GG15511@greenwood>

On Thu, Oct 01, 2009 at 08:41:01PM -0700, ron minnich wrote:
> On Thu, Oct 1, 2009 at 5:11 PM, Peter Stuge <peter at stuge.se> wrote:
> > svn at coreboot.org wrote:
> >> + ? ? bool "S1850"
> >
> > Is this a PowerEdge S1850 ?
> 
> yes.

OK, changed to "Dell PowerEdge 1850" (without "S") in the code and in
the wiki, according to this:

http://support.dell.com/support/edocs/systems/pe1850/en/index.htm

Why is the port/directory named S1850 instead of 1850 though? Just to
have a letter as first character, or is the board _actually_ called
"S1850"? If so, do you have a more correct vendor website we can link to?

Also, please check
http://www.coreboot.org/Supported_Motherboards#Motherboards_supported_in_coreboot_v2

Are the entries there correct? I.e. Intel Xeon CPUs, Socket 604? Do you
know what kind of chips they use (PLCC or DIP32 or ...) and if it's
Parallel/LPC/FWH/SPI?


Thanks, Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Oct  2 14:53:25 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 2 Oct 2009 14:53:25 +0200
Subject: [coreboot] patch: remove embeddedplanet
In-Reply-To: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>
References: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>
Message-ID: <20091002125325.GH15511@greenwood>


> Remove the embedded planet. It is causing build errors and has had no maintainer
> for over four years now. It has not run in over 5 years. 

A more correct commit message would be
"We drop all PowerPC boards as u-boot is much better-suited for them,
and coreboot concentrates on x86 support", IMHO.


> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Please remove targets/embeddedplanet also, thanks!


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From info at coresystems.de  Fri Oct  2 15:09:55 2009
From: info at coresystems.de (coreboot information)
Date: Fri, 02 Oct 2009 15:09:55 +0200
Subject: [coreboot] build service results for r4709
Message-ID: <E1MthtT-0001yB-B2@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "uwe" checked in revision 4709 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove left-over targets/motorola/*, fix Dell PowerEdge 1850 name.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Build Log:
Compilation of embeddedplanet:ep405pc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4709&device=ep405pc&vendor=embeddedplanet&num=2


If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From mylesgw at gmail.com  Fri Oct  2 15:20:06 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Oct 2009 07:20:06 -0600
Subject: [coreboot] Not supported mobo, compile for a similar one?
In-Reply-To: <4AC5DB4B.8050403@gap.upv.es>
References: <4AC5DB4B.8050403@gap.upv.es>
Message-ID: <B2F47A631B26458E92F9E8BAB2259CE3@chimp>



> Now here my question: I have the supermicro mobo *H8QME-2+
> http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2+.cfm
> *that is not supported by coreboot but there is a similar one at the
> coreboot v2 list: H8dmr
> http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-
> i2.cfm.
> What would happen if i compile a coreboot.rom for the H8dmr and flash
> into the H8QME-2+? What kind of changes do i have to do?

1. Read wiki pages about getting started
2. Choose a recovery method (extra flash chips, BIOS savior, etc)
3. Compare lspci for the two boards and update the device tree in Config.lb:

One of the most important differences is probably the 8132, and where it is
connected.  From the H8DMR devicetree.cb:

		chip northbridge/amd/amdk8 #mc0
			device pci 18.0 on end 
			device pci 18.0 on end
			device pci 18.0 on 
				#  devices on link 0, link 0 == LDT 0 
			        chip southbridge/nvidia/mcp55 
					device pci 0.0 on end   # HT
                			device pci 1.0 on # LPC
						chip
superio/winbond/w83627hf
							device pnp 2e.0 off
#  Floppy
                	                 			io 0x60 =
0x3f0
                	                			irq 0x70 = 6
                	                			drq 0x74 = 2
							end

Each Opteron (amdk8) has three links: 0,1,&2.  On this board the mcp55 is on
link 2.  For your board you at least need to know if the 8132 is on the same
link as the mcp55, or a different one.  After you get that right it
shouldn't be too hard to fix up the rest since the boards are so similar.

4. Send serial output to the list for help

Good luck,
Myles




From paulepanter at users.sourceforge.net  Fri Oct  2 16:10:03 2009
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 02 Oct 2009 16:10:03 +0200
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
 src/mainboard/dell/s1850 targets
In-Reply-To: <20091002125035.GG15511@greenwood>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
Message-ID: <1254492603.8986.18.camel@mattotaupa.wohnung.familie-menzel.net>

Dear list,


Am Freitag, den 02.10.2009, 14:50 +0200 schrieb Uwe Hermann:

[?]

> OK, changed to "Dell PowerEdge 1850" (without "S") in the code

This was r4709.

[?]


Thanks,

Paul
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From peter at stuge.se  Fri Oct  2 16:25:35 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 16:25:35 +0200
Subject: [coreboot] proposal: remove Config.lb from dell s1850
In-Reply-To: <39D2A2A2-B57A-4AE1-9116-C36CCF343273@coresystems.de>
References: <13426df10910011707t5eae22dbj72383d247471fc29@mail.gmail.com>
	<20091002000908.1958.qmail@stuge.se>
	<39D2A2A2-B57A-4AE1-9116-C36CCF343273@coresystems.de>
Message-ID: <20091002142535.30129.qmail@stuge.se>

Stefan Reinauer wrote:
>>> Nobody but me cares about the board.
>>
>> I built an image for someone, maybe a year ago. :)
>
> Did it work?

I never got feedback.


//Peter



From peter at stuge.se  Fri Oct  2 16:31:32 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 16:31:32 +0200
Subject: [coreboot] [v2] r4707 - in
	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
In-Reply-To: <20091002125035.GG15511@greenwood>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
Message-ID: <20091002143132.31870.qmail@stuge.se>

Uwe Hermann wrote:
> Do you know what kind of chips they use (PLCC or DIP32 or ...) and
> if it's Parallel/LPC/FWH/SPI?

Most if not all Dell servers have TSOP flash, I bet it's an Intel FWH
part.


//Peter



From mylesgw at gmail.com  Fri Oct  2 16:31:53 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Oct 2009 08:31:53 -0600
Subject: [coreboot] Not supported mobo, compile for a similar one?
In-Reply-To: <4AC602CC.904@gap.upv.es>
References: <4AC5DB4B.8050403@gap.upv.es>
	<B2F47A631B26458E92F9E8BAB2259CE3@chimp> <4AC602CC.904@gap.upv.es>
Message-ID: <2831fecf0910020731y11f5cd7fke162ae7e03a18d0a@mail.gmail.com>

On Fri, Oct 2, 2009 at 7:40 AM, Knut Kujat <knuku at gap.upv.es> wrote:
>> Each Opteron (amdk8) has three links: 0,1,&2. ?On this board the mcp55 is on
>> link 2. ?For your board you at least need to know if the 8132 is on the same
>> link as the mcp55, or a different one. ?After you get that right it
>> shouldn't be too hard to fix up the rest since the boards are so similar.
>>
> THX, for ur reply!
No problem.  According to the manual, the 8132 is on a link attached
to a different processor, so you probably would get debug output from
the board with an unmodified h8dmr image.

Myles



From mylesgw at gmail.com  Fri Oct  2 17:00:51 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Oct 2009 09:00:51 -0600
Subject: [coreboot] tyan s2881 with seabios and gpxe
In-Reply-To: <4AC53F3A.6050503@lanl.gov>
References: <4AC4C296.1050103@lanl.gov>
	<2831fecf0910010904t7b609492t7e77b5fa0d5cca21@mail.gmail.com>
	<4AC539FC.7070908@lanl.gov>
	<8EFC08F8964C431D9737758FAFAE183A@chimp>
	<4AC53F3A.6050503@lanl.gov>
Message-ID: <D81F71514503443484609744D6006AD1@chimp>



> This is all the output I get on the serial port.  How can I get a full
> log?
If you set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9

You may get some more useful information.

Thanks,
Myles





From svn at coreboot.org  Fri Oct  2 17:46:11 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Fri,  2 Oct 2009 17:46:11 +0200
Subject: [coreboot] [v2] r4710 - in trunk/coreboot-v2: src/mainboard targets
Message-ID: <mailman.3781.1355071627.16123.coreboot@coreboot.org>

Author: myles
Date: 2009-10-02 17:46:10 +0200 (Fri, 02 Oct 2009)
New Revision: 4710

Removed:
   trunk/coreboot-v2/src/mainboard/embeddedplanet/
   trunk/coreboot-v2/targets/embeddedplanet/
Modified:
   trunk/coreboot-v2/src/mainboard/Kconfig
Log:
Remove the Embedded Planet board.

Signed-off-by: Ronald G. Minnich <rminich at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Myles Watson <mylesgw at gmail.com>


Modified: trunk/coreboot-v2/src/mainboard/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-02 12:45:18 UTC (rev 4709)
+++ trunk/coreboot-v2/src/mainboard/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
@@ -38,8 +38,6 @@
 	bool "DIGITAL-LOGIC"
 config VENDOR_EAGLELION
 	bool "EagleLion"
-config VENDOR_EMBEDDED_PLANET
-	bool "Embedded Planet"
 config VENDOR_EMULATION
 	bool "Emulation"
 config VENDOR_GIGABYTE
@@ -184,11 +182,6 @@
 
 config MAINBOARD_VENDOR
 	string
-	default "Embedded Planet"
-	depends on VENDOR_EMBEDDED_PLANET
-
-config MAINBOARD_VENDOR
-	string
 	default "Emulation"
 	depends on VENDOR_EMULATION
 
@@ -349,7 +342,6 @@
 source "src/mainboard/dell/Kconfig"
 source "src/mainboard/digitallogic/Kconfig"
 source "src/mainboard/eaglelion/Kconfig"
-source "src/mainboard/embeddedplanet/Kconfig"
 source "src/mainboard/emulation/Kconfig"
 source "src/mainboard/gigabyte/Kconfig"
 source "src/mainboard/hp/Kconfig"
@@ -361,7 +353,6 @@
 source "src/mainboard/kontron/Kconfig"
 source "src/mainboard/lippert/Kconfig"
 source "src/mainboard/mitac/Kconfig"
-source "src/mainboard/motorola/Kconfig"
 source "src/mainboard/msi/Kconfig"
 source "src/mainboard/nec/Kconfig"
 source "src/mainboard/newisys/Kconfig"




From mylesgw at gmail.com  Fri Oct  2 17:48:10 2009
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Oct 2009 09:48:10 -0600
Subject: [coreboot] patch: remove embeddedplanet
In-Reply-To: <20091002125325.GH15511@greenwood>
References: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>
	<20091002125325.GH15511@greenwood>
Message-ID: <2831fecf0910020848k142cb527rb2abc048c4b22478@mail.gmail.com>

>> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
>
> Please remove targets/embeddedplanet also, thanks!
Done.  Rev 4710.

Thanks,
Myles



From peter at stuge.se  Fri Oct  2 18:04:38 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 18:04:38 +0200
Subject: [coreboot] patch: remove embeddedplanet
In-Reply-To: <20091002125325.GH15511@greenwood>
References: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>
	<20091002125325.GH15511@greenwood>
Message-ID: <20091002160438.17929.qmail@stuge.se>

Uwe Hermann wrote:
> "We drop all PowerPC boards as u-boot is much better-suited for
> them, and coreboot concentrates on x86 support", IMHO.

I don't know about that.. It sounds like we're doing so on purpose,
or in an excluding fashion, but really PC is just what we happen to
be working on. coreboot could definately work also on other machines
with dynamic busses, but there is less motivation since they don't
have the same firmware situation.


//Peter



From rminnich at gmail.com  Fri Oct  2 18:04:48 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 09:04:48 -0700
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
In-Reply-To: <20091002125035.GG15511@greenwood>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
Message-ID: <13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>

On Fri, Oct 2, 2009 at 5:50 AM, Uwe Hermann <uwe at hermann-uwe.de> wrote:

> Why is the port/directory named S1850 instead of 1850 though? Just to
> have a letter as first character, or is the board _actually_ called
> "S1850"? If so, do you have a more correct vendor website we can link to?

It say s1850 on the front I think.

I'll try to find the other info.

ron



From peter at stuge.se  Fri Oct  2 18:12:06 2009
From: peter at stuge.se (Peter Stuge)
Date: Fri, 2 Oct 2009 18:12:06 +0200
Subject: [coreboot] [v2] r4707 - in
	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
In-Reply-To: <13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
Message-ID: <20091002161206.19314.qmail@stuge.se>

ron minnich wrote:
> > Why is the port/directory named S1850 instead of 1850 though? Just to
> > have a letter as first character, or is the board _actually_ called
> > "S1850"? If so, do you have a more correct vendor website we can link to?
> 
> It say s1850 on the front I think.

This one?

http://gtk.no/images/bim/server/bim2.jpg

It could simply be that the board name can't be all numbers. I don't
know if we actually have that restriction?


//Peter



From rminnich at gmail.com  Fri Oct  2 18:21:21 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 09:21:21 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
Message-ID: <13426df10910020921j20480b1fm6a7401bfd51d6237@mail.gmail.com>

OK, well, I did not quite get the answers I hoped for. So here go my comments:

On Thu, Oct 1, 2009 at 5:04 PM, ron minnich <rminnich at gmail.com> wrote:

> dimm 50
> 00: bad device: 01
>
>
> dimm 51
> 00: bad device: 01
>
>
> dimm 52
> 00: bad device: 01
>
>
> dimm 53
> 00: bad device: 01
>
>

obviously bad.

> dimm 54
> 00: ad db de c0 01 00 00 00 01 f0 fa fa 00 00 00 d9

Bogus, because the first byte is "how many bytes written". I went to
http://en.wikipedia.org/wiki/Serial_presence_detect#On_older_equipment
and is is clear that 0xad doesn't match what's written:

> 10: 00 00 00 00 00 00 6c 01 00 00 00 00 00 00 00 00
> etc.
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

So this is bogus.
>
> dimm 55
> 00: bad device: 01
>
>
> dimm 56
> 00: bad device: 01
>
>

bad.

> dimm 57
> 00: 80 08 08 0d 0a 60 48 00 05 50 60 02 02 08 08 00
> 10: 0c 04 38 00 01 00 01 50 60 50 60 3c 1e 3c 28 40
> 20: 35 47 15 27 3c 28 1e 00 00 37 4b 80 23 2d 0f 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 6b
> 40: ce 00 00 00 00 00 00 00 01 4d 33 20 39 33 54 33
> 50: 32 35 33 46 5a 30 2d 43 43 43 20 30 46 05 17 46
> 60: 04 cb 50 00 59 42 43 35 36 30 50 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 49 d6 06 71 16 23 33 80 30 45 52 00 07 05 ff
> 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f0: 01 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
>

This looks closer to real. 0x80 is a common first byte. It also
matches (almost) the # bytes written since the last 112
bytes of this one are pretty clearly unwritten. Let's dig deeper.

Byte ordering for the first several bytes:

Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM...) from appendix A
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this Assembly
Data Width of this assembly...
...Data Width continuation
Voltage interface standard of this assembly


next bytes are 08 and 08. Oops. Byte 2 is the type and 8 doesn't match
any type. Disappointing as some of the other
bytes almost look plausible, but 0x60 module banks? Doubtful ...

Time to break out the lm sensors tools ... and do the gpio dance again.

thanks

ron



From rminnich at gmail.com  Fri Oct  2 18:23:33 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 09:23:33 -0700
Subject: [coreboot] patch: remove embeddedplanet
In-Reply-To: <20091002160438.17929.qmail@stuge.se>
References: <13426df10910012043x1acd1db8h2964d967ee6c9a40@mail.gmail.com>
	<20091002125325.GH15511@greenwood>
	<20091002160438.17929.qmail@stuge.se>
Message-ID: <13426df10910020923y9a6047aiec122fdacdaaeedf@mail.gmail.com>

On Fri, Oct 2, 2009 at 9:04 AM, Peter Stuge <peter at stuge.se> wrote:
> Uwe Hermann wrote:
>> "We drop all PowerPC boards as u-boot is much better-suited for
>> them, and coreboot concentrates on x86 support", IMHO.
>
> I don't know about that.. It sounds like we're doing so on purpose,
> or in an excluding fashion, but really PC is just what we happen to
> be working on. coreboot could definately work also on other machines
> with dynamic busses, but there is less motivation since they don't
> have the same firmware situation.

I think the statement is a bit strong as well. The person who did the
coreboot port did so because he felt coreboot+openbios was a better
setup. He even demo'ed the whole thing at usenix one year, booting to
linux.

But PPC has been ignored since that person left, so it seems not worth
the effort.

ron



From rminnich at gmail.com  Fri Oct  2 18:26:07 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 09:26:07 -0700
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
In-Reply-To: <20091002161206.19314.qmail@stuge.se>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
Message-ID: <13426df10910020926s63eb7646ybd92c54c5a4e99cf@mail.gmail.com>

On Fri, Oct 2, 2009 at 9:12 AM, Peter Stuge <peter at stuge.se> wrote:

> This one?
>
> http://gtk.no/images/bim/server/bim2.jpg

not that one. Interesting.

>
> It could simply be that the board name can't be all numbers. I don't
> know if we actually have that restriction?

since we generate identifiers from the names, it's always a danger,
and might have been an issue in v1. In any case I've gotten into the
habit.

ron



From rminnich at gmail.com  Fri Oct  2 18:53:44 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 09:53:44 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <4AC5E9C7.90304@gmx.net>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
Message-ID: <13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>

On Fri, Oct 2, 2009 at 4:53 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> decode-dimms (or decode-dimms.pl) from lm-sensors is extremely useful
> for this. Run it on a working system and it will dump the content of all
> SPDs and show the meaning of the values stored there.
>

The lm_sensors tools are handy when everything is working fine.
They're not when things are not. In my case, things are not and,
sadly, the tools are largely useless -- I'm going to have to write my
own.

I can run this on the dell, and the decode-dimms will gladly tell me
there is no memory. Bummer! :-)

A further problem is the lm_sensors guys don't always understand Unix
(a common problem nowadays :-) or decode-dimms would be two tools:
1. get_spd
2. decode_spd

which would make part 2 independent of part 1. Then, I could easily
feed my output from serialice into decode_spd and have it say "WOW!
That's bogus!".

Maybe as part of this I can bust decode-dimms into two pieces as well ...

thanks, though, my goal is to have decode-dimms work well on the dell.
Hopefully won't take too long ...

ron



From tsylla at gmail.com  Fri Oct  2 20:41:44 2009
From: tsylla at gmail.com (Tom Sylla)
Date: Fri, 2 Oct 2009 14:41:44 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
Message-ID: <57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>

On Fri, Oct 2, 2009 at 12:53 PM, ron minnich <rminnich at gmail.com> wrote:
> On Fri, Oct 2, 2009 at 4:53 AM, Carl-Daniel Hailfinger
> The lm_sensors tools are handy when everything is working fine.
> They're not when things are not. In my case, things are not and,
> sadly, the tools are largely useless -- I'm going to have to write my
> own.

I have a collection of DIMMs I use for testing platforms, and I keep
SPD dumps for each DIMM handy. Then I can look in my list of eeprom
dumps to find the aprticualr specs I need to test easily. I don't
really use any tools, Appendix A and hexdump are all you need.

> A further problem is the lm_sensors guys don't always understand Unix
> (a common problem nowadays :-) or decode-dimms would be two tools:
> 1. get_spd
> 2. decode_spd

"get_spd" is 'modprobe eeprom; cp /sys/bus/i2c/devices/0-0054/eeprom ./eeprom'


Regarding your other mail, I think you did not decode it carefully
enough. It looks ok to me, I even see this string:

4D 33 20 39 33 54 33 32 35 33 46 5A 30 2D 43 43  M3 93T3253FZ0-CC

and google says 93T3253FZ0 is a Samsung DDR2, registered, ECC DIMM

You said offset 2 is fundamental memory type, which is true. '08' is
certainly valid though, I see 08 as "DDR II SDRAM" in appendix A (is
yours the latest?)

Here are the first lines of the dumps of some of the DIMMs in my collection:

[tsylla at x DDR2]$ for i in `ls`; do hexdump -C $i/eeprom|grep 00000000; done
00000000  80 08 08 0e 0a 60 48 00  05 25 40 06 82 08 08 00  |.....`H..%@.....|
00000000  80 08 08 0d 0b 60 48 00  05 3d 50 02 82 04 04 00  |.....`H..=P.....|
00000000  80 08 08 0e 0a 61 48 00  05 25 40 06 82 08 08 00  |.....aH..%@.....|


They are pretty consistent with yours.

Please get the latest JEDEC specs and decode your dump more carefully;
I think you will find it makes sense. (I checked for you that the
checksum at 3f is correct)



As a side rant, why does do Linux and coreboot insist on referring to
SMBus addresses shifted right byte one bit? They are 7 bits long, and
should be *left* justified in the byte. Take a look at every SMBus
controller, and you will see that is how the register is laid out,
address is the top 7 bits, and the bottom bit is read/write. Take a
look at the SMBus drivers in coreboot, and you will see the access
function doing something like: dimm_address << 1 | READ_WRITE. It just
seems silly to me :)

Tom



From rminnich at gmail.com  Fri Oct  2 22:07:56 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 13:07:56 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
Message-ID: <13426df10910021307i2178e69apa57bbc1e55ae130d@mail.gmail.com>

On Fri, Oct 2, 2009 at 11:41 AM, Tom Sylla <tsylla at gmail.com> wrote:

> As a side rant, why does do Linux and coreboot insist on referring to
> SMBus addresses shifted right byte one bit? They are 7 bits long, and
> should be *left* justified in the byte. Take a look at every SMBus
> controller, and you will see that is how the register is laid out,
> address is the top 7 bits, and the bottom bit is read/write. Take a
> look at the SMBus drivers in coreboot, and you will see the access
> function doing something like: dimm_address << 1 | READ_WRITE. It just
> seems silly to me :)


Maybe it is a difference in view. The address is 7 bits in all the
docs. How it is laid out in the register and on the bits on the wire
is really a different concern.

I can see an argument for either side ...

ron



From rminnich at gmail.com  Fri Oct  2 22:09:37 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 13:09:37 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
Message-ID: <13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>

BTW, THANKS for the note. I was hoping for a note from an expert :-)

That leading bytes sure looked like SPD but my obsolete JDEC docs threw me off.

Now I wonder why I only see one SPD ... but that's grist for another
note in little bit.

Thanks

ron



From c-d.hailfinger.devel.2006 at gmx.net  Fri Oct  2 23:39:50 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Fri, 02 Oct 2009 23:39:50 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC64C32.4020509@codemonkey.ws>
References: <4AC29E4D.80707@us.ibm.com>	<D0452B81-706B-4154-92E1-6E253A305053@claunia.com>	<4AC4A487.1050003@us.ibm.com>	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>	<4AC51DBA.7020609@codemonkey.ws>	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>	<4AC60037.6000001@codemonkey.ws>	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>	<4AC64A5C.6010003@gmx.net>
	<4AC64C32.4020509@codemonkey.ws>
Message-ID: <4AC67326.6080603@gmx.net>

[Adding the coreboot list to CC. Please ignore the moderation messages,
your addresses will be whitelisted ASAP.]

On 02.10.2009 20:53, Anthony Liguori wrote:
> Carl-Daniel Hailfinger wrote:
>> Given that you can easily pack coreboot+SeaBIOS+UEFI into one ROM and
>> have coreboot boot either SeaBIOS (BIOS interface) or UEFI (EFI
>> interface), wouldn't that solve all problems in one go? You get an
>> unified stack and don't have to mess around with different firmware
>> files because coreboot can read in a Qemu machine config option (or
>> NVRAM/CMOS) and select the interface based on that.
>>   
>
> If you want to to work seamlessly, you need to check for the EFI
> system partition to see whether it's an EFI capable OS and then
> fallback gracefully to SeaBIOS boot.

Hm. Wouldn't that be a layering violation (hw init != reading the disk)
and also cause problems if you want to boot an EFI capable OS from
SeaBIOS? I can think of someone having an EFI bootable disk image who
wants to boot that disk image with EFI and BIOS without having to
repartition.


>> The hardware init part would be identical for all variants, only the
>> interface would differ. coreboot works now and has the benefit of
>> supporting real hardware as well, so the difference between a setup
>> inside Qemu and a setup on real hardware is minimal.   
>
> Tianocore's OVMF project should provide all the required
> initialization for EFI on QEMU.

Yes, but then we'd have two sets of hardware init: OVMF for EFI, SeaBIOS
for SeaBIOS. That also means each hw init codebase has to support the
new Q35 chipset proposed for Qemu.

It's not any better if SeaBIOS gets changed into a CSM for EFI. Then you
have SeaBIOS on top of EFI on top of OVMF. As I understand it, OVMF had
less testing than the Bochs BIOS or SeaBIOS on Qemu.

Jordan, I have to admit that I'm surprised OVMF was apparently created
from scratch although quite a few (established) hardware init solutions
already exist for Qemu: SeaBIOS, Bochs BIOS, coreboot, and some old
hobbyist projects. I'd like to understand the reasons for that and fix
them in coreboot (Kevin O'Connor will probably fix them in SeaBIOS). If
you ported/modified existing code, I'd be interested in the original
codebase to learn from it (especially what you had to change).


>> The coreboot solution would also avoid converting SeaBIOS because
>> SeaBIOS already works as coreboot payload (that's how coreboot
>> developers call the CSM).
>>   
>
> I'll bite, what's the advantage of doing coreboot + SeaBIOS vs.
> SeaBIOS alone?  Forget about EFI for the moment, should be considering
> switching to coreboot + SeaBIOS for 0.12?

Advantages:
- Code coverage increase: SeaBIOS is used with coreboot on real
hardware, so the BIOS interface part of SeaBIOS gets a lot more testing
than the Qemu hardware init part of SeaBIOS.

- coreboot supports real 440BX hardware besides Qemu, so the coreboot
init code is exercised more (and there is still a sizable number of such
machines around (clusters), many of them running coreboot).

- Only one ROM image needed. A coreboot ROM can pack the VGA BIOS into
the ROM image and SeaBIOS will automatically load it from there. Same
for network card ROMs (with gPXE etc.).

- coreboot ROMs (including those with SeaBIOS and/or EFI and/or VGABIOS)
are archives and can be listed/edited with cbfstool if you want to know
what's in there.

- coreboot ROMs use compression, so you can stuff more code (and PCI
option ROMs) into smaller ROMs.

- coreboot has pretty verbose hardware init messages (if you want that)
and can be totally silent as well. The messages end up in a log buffer
which can be read by the OS (experimental feature, not available by
default).

There are a lot more advantages, but I want to give other coreboot
developers a chance to chime in. If you add EFI to the mix, the
synergies increase.


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 00:19:01 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 00:19:01 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910021357i2b441f5flb98b1fa41c5f2150@mail.gmail.com>
References: <4AC29E4D.80707@us.ibm.com>	<D0452B81-706B-4154-92E1-6E253A305053@claunia.com>	<4AC4A487.1050003@us.ibm.com>	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>	<4AC51DBA.7020609@codemonkey.ws>	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>	<4AC60037.6000001@codemonkey.ws>	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>	<4AC64A5C.6010003@gmx.net>
	<2a50f7880910021357i2b441f5flb98b1fa41c5f2150@mail.gmail.com>
Message-ID: <4AC67C55.4040800@gmx.net>

Hi Jordan,

I have to admit that I'm not the expert for coreboot+EFI solutions. I
know they exist and work, but I'll defer to other developers on the
coreboot list to give you detailed answers. Please see below for what I
think I know (but I'll gladly accept any corrections).


On 02.10.2009 22:57, Jordan Justen wrote:
> Carl-Daniel,
>
> Interesting.  So, where can I download a QEMU bios rom to boot a UEFI
> OS with this solution?
>
> Can you explain what coreboot+tianocore means?  Which parts of
> tianocore do you use in this situation?
>   

This mail is CC: to the coreboot list and I'm sure someone who knows
more than I can respond.

The documentation about Tianocore/UEFI/EFI is not entirely clear about
the names of each part of the stack, but if I understand correctly,
there is a hardware init part (OVMF for Qemu) and parts which boot EFI
enabled operating systems, provide EFI services to the operating system,
or give users a shell to work from.

coreboot is pure hardware init (CPU, RAM, chipset, PCI), it has no
drivers whatsoever. It does provide ACPI tables for the hardware and a
memory map. Once coreboot finishes hardware initialization, it passes
control to a payload (which has drivers, boots the OS, provides
services). That payload is hardware-independent unless it explicitly
wants to contain non-generic drivers. It is possible to use the exact
same SeaBIOS binary as coreboot payload on Qemu, Pentium III systems
with i440BX chipset, AMD Phenom systems with 690G chipset, Via Nano
systems with VX800 chipset, and Intel Core 2 Duo systems with i945 chipset.
Unless I'm mistaken, OVMF and coreboot have pretty much the same purpose.


> If your solution can accomplish all of what you say, I'm not sure how
> OVMF would be able to compete against in terms of being included with
> QEMU.  Part of the reason for starting OVMF was to help enable UEFI
> support within VM's such as QEMU.  If OVMF was utilized by QEMU it
> definitely would have been a bit of a boost for our efforts, but if
> QEMU accomplishes UEFI support via another path, then overall we will
> still be happy.
>   

Please don't get me wrong. The number of developers in the open source
firmware space is small and I'm happy that you're such a developer. My
main worry is splitting one task among too many projects, with the
danger of frustation if only one project is accepted into Qemu. I don't
have an axe to grind against EFI (which is desired by many people) or
OVMF (which is purpose-built for UEFI in Qemu).
That's why I want to understand your goals and hope to find a way to
accomplish your goals, coreboot goals and at the same time have Qemu get
the best firmware possible.


> Thanks,
>
> -Jordan
>   

Regards,
Carl-Daniel

> On Fri, Oct 2, 2009 at 11:45, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> On 02.10.2009 18:58, Jordan Justen wrote:
>>     
>>> On Fri, Oct 2, 2009 at 06:29, Anthony Liguori <anthony at codemonkey.ws> wrote:
>>>
>>>       
>>>> So I think the best way forward is to hold off on UEFI in mainline until we
>>>> can provide a single unified stack.
>>>>
>>>>         
>>> While it is true that a separate machine type could potentially be
>>> viewed as increasing the testing requirements, I am not so sure.  If
>>> QEMU has a UEFI+CSM solution, wouldn't we still have to test both UEFI
>>> based OS boot and the CSM based legacy OS boot?
>>>
>>>       
>> Given that you can easily pack coreboot+SeaBIOS+UEFI into one ROM and
>> have coreboot boot either SeaBIOS (BIOS interface) or UEFI (EFI
>> interface), wouldn't that solve all problems in one go? You get an
>>     




From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 00:31:38 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 00:31:38 +0200
Subject: [coreboot] [Fwd: Re: [Qemu-devel] Release plan for 0.12.0]
Message-ID: <4AC67F4A.6010701@gmx.net>

Comments? Please try to add the original recipients to CC if you answer.

-------- Original Message --------
Subject: 	Re: [Qemu-devel] Release plan for 0.12.0
Date: 	Fri, 02 Oct 2009 16:37:49 -0500
From: 	Anthony Liguori <aliguori at us.ibm.com>
To: 	Jordan Justen <jljusten at gmail.com>
CC: 	Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>,
qemu-devel at nongnu.org
References: 	<4AC29E4D.80707 at us.ibm.com>
<D0452B81-706B-4154-92E1-6E253A305053 at claunia.com>
<4AC4A487.1050003 at us.ibm.com>
<2a50f7880910011410u6afbb658hf99839fdb3e7bab1 at mail.gmail.com>
<4AC51DBA.7020609 at codemonkey.ws>
<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9 at mail.gmail.com>
<4AC60037.6000001 at codemonkey.ws>
<2a50f7880910020958g3fe5eadehe5e5094c05b218d9 at mail.gmail.com>
<4AC64A5C.6010003 at gmx.net>
<2a50f7880910021357i2b441f5flb98b1fa41c5f2150 at mail.gmail.com>



Jordan Justen wrote:
> Carl-Daniel,
>
> Interesting.  So, where can I download a QEMU bios rom to boot a UEFI
> OS with this solution?
>
> Can you explain what coreboot+tianocore means?  Which parts of
> tianocore do you use in this situation?
>
> If your solution can accomplish all of what you say, I'm not sure how
> OVMF would be able to compete against in terms of being included with
> QEMU.  Part of the reason for starting OVMF was to help enable UEFI
> support within VM's such as QEMU.  If OVMF was utilized by QEMU it
> definitely would have been a bit of a boost for our efforts, but if
> QEMU accomplishes UEFI support via another path, then overall we will
> still be happy.
>   

FWIW, I looked more closely at Coreboot + SeaBIOS today.  It's much less 
functional than just SeaBIOS alone.  There really is no additional 
functionality because all payloads that Coreboot can run already run 
directly under QEMU (or under SeaBIOS).

With respect to Coreboot + SeaBIOS + UEFI, AFAIK, you cannot have 
multiple payloads without using essentially a payload switcher (like 
Bayou).  The problem with this though is your just deferring the 
EFI/BIOS choice to the user in a different place.  What we need is a 
mechanism to transparently choose UEFI or SeaBIOS depending on whether 
the guest is EFI aware.

I think option roms further complicate the matter because we would need 
a gPXE EFI module to support network boot.  That makes the switch logic 
even more complicated.  For PCI passthrough, I assume that the legacy 
option ROMs have to be loaded through a CSM so if we want to enable PCI 
passthrough, we really need a proper CSM.

-- 
Regards,

Anthony Liguori





-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 00:33:01 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 00:33:01 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910012237g3667a5b2sc08193829adc3f73@mail.gmail.com>
References: <4AC29E4D.80707@us.ibm.com>	<D0452B81-706B-4154-92E1-6E253A305053@claunia.com>	<4AC46327.4030004@gmx.net>	<1CD2353A-CCE0-4E2C-B3A7-9E6D2E9D34C7@claunia.com>
	<2a50f7880910012237g3667a5b2sc08193829adc3f73@mail.gmail.com>
Message-ID: <4AC67F9D.1020806@gmx.net>

Hi Jordan,

thanks for the detailed explanation. It certainly helped me understand
some parts of the tianocore umbrealla better.

On 02.10.2009 07:37, Jordan Justen wrote:
> I work for Intel on the edk2.tianocore.org project.  (Compared to the
> original edk) edk2 may be of interest to those on this list since it
> supports building on several OS's with several different toolchains.
> In other words, it also supports building under Linux and OS X with
> the GNU compiler and binutils.
>   

Neat. I remember the toolchain issues Linux-based developers had in the
past, so I think this is a good thing.


> Within our edk2 tree, we have two projects that relate to QEMU.
>
> The DUET platform is a UEFI emulator that boots like a legacy OS on
> top of a legacy BIOS.  It contains various hardware initialization
> drivers for several legacy hardware devices, but it also will call
> into the legacy BIOS and make use of certain items from the legacy
> BIOS.  DUET can boot from the QEMU legacy BIOS, but it does require a
> disk to be setup to have the DUET image on it.  I am not sure if all
> of DUET's code is currently safe for a UEFI OS to be able to access
> UEFI runtime services.
>   

By the way, SeaBIOS can boot virtual floppy images stored in the ROM (at
least when SeaBIOS runs as coreboot payload), so if you can fit DUET
into a floppy image (or if Kevin adds support for virtual harddisk
images), you can have a coreboot+SeaBIOS+DUET ROM right now.


> The OVMF platform is a project to build a (mostly) UEFI compatible
> firmware for virtual machines.  QEMU support is one of the main goals
> for OVMF.  The OVMF rom image completely replaces QEMU's standard
> bios.bin, and therefore we must have hardware drivers for any hardware
> within the QEMU VM that we want to make use of.  The project also has
> the goal to support UEFI OS's at runtime.
>   

So OVMF is not just hardware init, but a complete package of hardware
init and UEFI interface?


Regards,
Carl-Daniel



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 01:05:18 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 01:05:18 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
References: <4AC29E4D.80707@us.ibm.com>
	<4AC4A487.1050003@us.ibm.com>	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>	<4AC51DBA.7020609@codemonkey.ws>	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>	<4AC60037.6000001@codemonkey.ws>	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>	<4AC64A5C.6010003@gmx.net>
	<4AC64C32.4020509@codemonkey.ws>	<4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
Message-ID: <4AC6872E.6060103@gmx.net>

On 03.10.2009 00:28, Jordan Justen wrote:
> On Fri, Oct 2, 2009 at 14:39, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>   
>> Jordan, I have to admit that I'm surprised OVMF was apparently created
>> from scratch although quite a few (established) hardware init solutions
>> already exist for Qemu: SeaBIOS, Bochs BIOS, coreboot, and some old
>> hobbyist projects.
>>     
>
> The edk2 project provides an infrastructure for building complete UEFI
> firmware solutions.  OVMF is a sample platform which demonstrates how
> edk2 can be used to build firmware to boot a UEFI platform.
>   

I wish to apologize for the misunderstanding. I thought OVMF was only
hardware init. Thanks for correcting me.


> Aside from just this, OVMF is an effort to support VMs on edk2.  (Ie,
> more than just QEMU.)  Ideally the project, and code of OVMF could be
> used by any VM vendor as a sample for building UEFI compatible
> firmware.
>   

How does it relate to real hardware? You mention OVMF as an effort to
support VMs on edk2. Does this mean that VMs need special support or
that real hardware has different needs?


> Most of the code required to support QEMU was already open sourced on
> edk2 before OVMF was launched.  At the time that we started OVMF, it
> did not seem like any project was targeting UEFI support on QEMU.
> Tristan Gingold had done a port for UEFI QEMU support, but at that
> time it did not seem to be functional with the current QEMU, nor
> actively developed.
>   

I see.


>> I'd like to understand the reasons for that and fix
>> them in coreboot (Kevin O'Connor will probably fix them in SeaBIOS).
>>     
>
> If you want to remove any need for OVMF on QEMU, then I think all that
> is needed is to support booting UEFI OS's for both i386 and x86-64.
> Of course, we may still have some use for the OVMF project on edk2 as
> a sample platform.
>   

Given that my original statement incorrectly assumed OVMF was only about
hardware init, please let me try to express what I originally meant (and
which came across with unintended meaning).
I hope to use all EFI support code from OVMF, keep SeaBIOS, and have
coreboot as common hardware init base.


>> If
>> you ported/modified existing code, I'd be interested in the original
>> codebase to learn from it (especially what you had to change).
>>     
>
> As I mentioned above, a good portion of the code was already available
> in edk2.tianocore.org.

Thanks for the pointer.


> Edk2 is BSD licensed, and therefore from a
> licensing perspective should be easy for your project to utilize.
>   

(Speaking with my coreboot hat on.)
The goal of coreboot is not to assimilate and change other projects, but
to provide hardware init for any code which needs it.

After hardware init, it passes control to a payload (SeaBIOS, UEFI,
GRUB2, FILO, Linux, Plan9...). There are no callbacks to coreboot, each
payload is expected to talk to the hardware on its own. Except for ACPI
tables (and a memory map), nothing of coreboot stays in memory after
passing control to that payload. If you want some basic hardware drivers
for your favourite payload, you can use the BSD-licensed libpayload
library in your code, but most payloads (SeaBIOS, GRUB2, ...) have their
own drivers anyway.
Operating systems like Linux and Plan9 which do not need any BIOS/EFI
interface can be stored in the ROM and will be booted directly by
coreboot (if in ROM). Boot loaders like GRUB2 or FILO don't need
BIOS/EFI either, can be stored in ROM and will then be booted directly.
BIOS and EFI code can be used as a coreboot payload in ROM as well. Some
people are even working on making U-Boot available as coreboot payload.

The idea is to have coreboot handle all the hardware-specific
initialization and allow all other code to be mostly hardware-agnostic
(unless said code wants to implement drivers). The clean interface
(well, no interface, coreboot just passes control to the payload) allows
payloads to do whatever they want as long as they provide a single
32-bit entry point coreboot can jump to.


Regards,
Carl-Daniel



From joe at settoplinux.org  Sat Oct  3 03:31:06 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 21:31:06 -0400
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>	
	<4AC555A3.1000700@settoplinux.org>	
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>	
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>	
	<4AC5E9C7.90304@gmx.net>	
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>	
	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
	<13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
Message-ID: <4AC6A95A.8050002@settoplinux.org>

On 10/02/2009 04:09 PM, ron minnich wrote:
> BTW, THANKS for the note. I was hoping for a note from an expert :-)

:-(


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Sat Oct  3 04:12:44 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Oct 2009 22:12:44 -0400
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <1254455370.28556.31.camel@ufo>
References: <4AC5616A.7010803@settoplinux.org> <1254455370.28556.31.camel@ufo>
Message-ID: <4AC6B31C.7010307@settoplinux.org>

On 10/01/2009 11:49 PM, Cristi Magherusan wrote:
> On Thu, 2009-10-01 at 22:11 -0400, Joseph Smith wrote:
>> [root at smitty5m SerialICE-1.0]# make
>> gcc -O2 -Wall -o romcc util/romcc.c
>> util/romcc.c: In function ?simplify_load?:
>> util/romcc.c:9925: warning: dereferencing type-punned pointer will break
>> strict-aliasing rules
>> util/romcc.c:9926: warning: dereferencing type-punned pointer will break
>> strict-aliasing rules
>> util/romcc.c:9927: warning: dereferencing type-punned pointer will break
>> strict-aliasing rules
>> util/romcc.c: In function ?get_const_pool_ref?:
>> util/romcc.c:23846: warning: format ?%ld? expects type ?long int?, but
>> argument 3 has type ?size_t?
>> util/romcc.c:23851: warning: format ?%ld? expects type ?long int?, but
>> argument 3 has type ?size_t?
>> util/romcc.c: In function ?print_sdecl?:
>> util/romcc.c:24660: warning: format ?%ld? expects type ?long int?, but
>> argument 3 has type ?size_t?
>> ./romcc -mcpu=i386 -I. -Imainboard -o serialice.S serialice.c
>> i386-elf-as -o serialice.o serialice.S
>> make: i386-elf-as: Command not found
>> make: *** [serialice.o] Error 127
>>
>> Any ideas?
> Try the attached patch
>
> Signed-off-by: Cristi M?gheru?an<cristi.magherusan at net.utcluj.ro>
>
> Regards,
> Cristi
>
>
Hmm Cristi, now with your patch I'm getting:

[joe at smitty5m SerialICE-1.0]$ make
gcc -O2 -Wall -o romcc util/romcc.c
util/romcc.c: In function ?simplify_load?:
util/romcc.c:9925: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c:9926: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c:9927: warning: dereferencing type-punned pointer will break 
strict-aliasing rules
util/romcc.c: In function ?get_const_pool_ref?:
util/romcc.c:23846: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
util/romcc.c:23851: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
util/romcc.c: In function ?print_sdecl?:
util/romcc.c:24660: warning: format ?%ld? expects type ?long int?, but 
argument 3 has type ?size_t?
./romcc -mcpu=i386 -I. -Imainboard -o serialice.S serialice.c
as --32 -o serialice.o serialice.o.s
Assembler messages:
Error: can't open serialice.o.s for reading: No such file or directory
make: *** [serialice.o] Error 1


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From joe at settoplinux.org  Sat Oct  3 06:30:05 2009
From: joe at settoplinux.org (Joseph Smith)
Date: Sat, 03 Oct 2009 00:30:05 -0400
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <FA08DC72-329F-4A9C-82D3-7B0B06354489@coresystems.de>
References: <4AC5616A.7010803@settoplinux.org>
	<FA08DC72-329F-4A9C-82D3-7B0B06354489@coresystems.de>
Message-ID: <4AC6D34D.9090200@settoplinux.org>

On 10/02/2009 08:37 AM, Stefan Reinauer wrote:
>
> On Oct 2, 2009, at 4:11, Joseph Smith <joe at settoplinux.org> wrote:
>
>> [root at smitty5m SerialICE-1.0]# make
>
> Install a cross compiler from util/crossgcc or drop the cross
> definitions from the Makefile
>
Ok after playing with the Makefile I am able to get SerialICE to build. 
I am left with a 4.3GB serialice.rom. The README says to make sure the 
shell works before moving on to QEMU, how do I test the shell is working 
before moving on?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From rminnich at gmail.com  Sat Oct  3 07:41:22 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 22:41:22 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <4AC6A95A.8050002@settoplinux.org>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
	<13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
	<4AC6A95A.8050002@settoplinux.org>
Message-ID: <13426df10910022241i6b2fd382g3d1730e5f4f27473@mail.gmail.com>

On Fri, Oct 2, 2009 at 6:31 PM, Joseph Smith <joe at settoplinux.org> wrote:
> On 10/02/2009 04:09 PM, ron minnich wrote:
>>
>> BTW, THANKS for the note. I was hoping for a note from an expert :-)

Joseph, don't feel bad; I clearly don't know much about this stuff either :-)

That's why I'm glad we have such a broad range of experts here.
Everyone knows a lot about something :-)

ron



From rminnich at gmail.com  Sat Oct  3 07:54:10 2009
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Oct 2009 22:54:10 -0700
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <4AC6D34D.9090200@settoplinux.org>
References: <4AC5616A.7010803@settoplinux.org>
	<FA08DC72-329F-4A9C-82D3-7B0B06354489@coresystems.de>
	<4AC6D34D.9090200@settoplinux.org>
Message-ID: <13426df10910022254n7269f25bob6b9f27c8ad52a62@mail.gmail.com>

On Fri, Oct 2, 2009 at 9:30 PM, Joseph Smith <joe at settoplinux.org> wrote:

> Ok after playing with the Makefile I am able to get SerialICE to build. I am
> left with a 4.3GB serialice.rom. The README says to make sure the shell
> works before moving on to QEMU, how do I test the shell is working before
> moving on?

Something's very wrong. It should be 64K.

I can not remember -- did you first try to use the utils/crossgcc
stuff in coreboot -- that's how I built it and it worked flawlessly.

Good luck.

ron



From kevin at koconnor.net  Sat Oct  3 09:22:50 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 3 Oct 2009 03:22:50 -0400
Subject: [coreboot] XMM stack
In-Reply-To: <4AC52ED6.3060003@assembler.cz>
References: <4AC52ED6.3060003@assembler.cz>
Message-ID: <20091003072250.GA14986@morn.localdomain>

On Fri, Oct 02, 2009 at 12:36:06AM +0200, Rudolf Marek wrote:
> Hello,
> 
> I made some fix for xmmstack.c found in SerialICE.
> 
> leal (%esp), %ecx
> 

I was looking at xmmstack - it's a neat hack!  However, as near as I
can tell, it only fixes up %esp references.  If gcc were to copy %esp
to %ecx and then issue a memory access to %ecx then xmmstack isn't
going to fixup that memory access.  So, unless I missed something, the
leal change is likely to just mask the problem.

-Kevin



From stepan at coresystems.de  Sat Oct  3 14:25:50 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Oct 2009 14:25:50 +0200
Subject: [coreboot] SerialICE Build Error
In-Reply-To: <4AC6D34D.9090200@settoplinux.org>
References: <4AC5616A.7010803@settoplinux.org>
	<FA08DC72-329F-4A9C-82D3-7B0B06354489@coresystems.de>
	<4AC6D34D.9090200@settoplinux.org>
Message-ID: <4AC742CE.5050301@coresystems.de>

Joseph Smith wrote:
> On 10/02/2009 08:37 AM, Stefan Reinauer wrote:
>>
>> On Oct 2, 2009, at 4:11, Joseph Smith <joe at settoplinux.org> wrote:
>>
>>> [root at smitty5m SerialICE-1.0]# make
>>
>> Install a cross compiler from util/crossgcc or drop the cross
>> definitions from the Makefile
>>
> Ok after playing with the Makefile I am able to get SerialICE to
> build. I am left with a 4.3GB serialice.rom. The README says to make
> sure the shell works before moving on to QEMU, how do I test the shell
> is working before moving on?
>
Can you try http://www.coresystems.de/download/SerialICE-1.2.tar.bz2 ?

Some section is not included in the .rom and thus ends up at 0x0 instead
of 0xffff0000, hence the size..

You should probably install the cross compiler from
coreboot-v2/util/crossgcc

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From jljusten at gmail.com  Sat Oct  3 00:28:22 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Fri, 2 Oct 2009 15:28:22 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC67326.6080603@gmx.net>
References: <4AC29E4D.80707@us.ibm.com> <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>
	<4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
Message-ID: <2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>

On Fri, Oct 2, 2009 at 14:39, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> [Adding the coreboot list to CC. Please ignore the moderation messages,
> your addresses will be whitelisted ASAP.]
>
> On 02.10.2009 20:53, Anthony Liguori wrote:
>> Carl-Daniel Hailfinger wrote:
>>> Given that you can easily pack coreboot+SeaBIOS+UEFI into one ROM and
>>> have coreboot boot either SeaBIOS (BIOS interface) or UEFI (EFI
>>> interface), wouldn't that solve all problems in one go? You get an
>>> unified stack and don't have to mess around with different firmware
>>> files because coreboot can read in a Qemu machine config option (or
>>> NVRAM/CMOS) and select the interface based on that.
>>>
>>
>> If you want to to work seamlessly, you need to check for the EFI
>> system partition to see whether it's an EFI capable OS and then
>> fallback gracefully to SeaBIOS boot.
>
> Hm. Wouldn't that be a layering violation (hw init != reading the disk)
> and also cause problems if you want to boot an EFI capable OS from
> SeaBIOS? I can think of someone having an EFI bootable disk image who
> wants to boot that disk image with EFI and BIOS without having to
> repartition.
>
>
>>> The hardware init part would be identical for all variants, only the
>>> interface would differ. coreboot works now and has the benefit of
>>> supporting real hardware as well, so the difference between a setup
>>> inside Qemu and a setup on real hardware is minimal.
>>
>> Tianocore's OVMF project should provide all the required
>> initialization for EFI on QEMU.
>
> Yes, but then we'd have two sets of hardware init: OVMF for EFI, SeaBIOS
> for SeaBIOS. That also means each hw init codebase has to support the
> new Q35 chipset proposed for Qemu.
>
> It's not any better if SeaBIOS gets changed into a CSM for EFI. Then you
> have SeaBIOS on top of EFI on top of OVMF. As I understand it, OVMF had
> less testing than the Bochs BIOS or SeaBIOS on Qemu.
>
> Jordan, I have to admit that I'm surprised OVMF was apparently created
> from scratch although quite a few (established) hardware init solutions
> already exist for Qemu: SeaBIOS, Bochs BIOS, coreboot, and some old
> hobbyist projects.

The edk2 project provides an infrastructure for building complete UEFI
firmware solutions.  OVMF is a sample platform which demonstrates how
edk2 can be used to build firmware to boot a UEFI platform.

Aside from just this, OVMF is an effort to support VMs on edk2.  (Ie,
more than just QEMU.)  Ideally the project, and code of OVMF could be
used by any VM vendor as a sample for building UEFI compatible
firmware.

Most of the code required to support QEMU was already open sourced on
edk2 before OVMF was launched.  At the time that we started OVMF, it
did not seem like any project was targeting UEFI support on QEMU.
Tristan Gingold had done a port for UEFI QEMU support, but at that
time it did not seem to be functional with the current QEMU, nor
actively developed.

> I'd like to understand the reasons for that and fix
> them in coreboot (Kevin O'Connor will probably fix them in SeaBIOS).

If you want to remove any need for OVMF on QEMU, then I think all that
is needed is to support booting UEFI OS's for both i386 and x86-64.
Of course, we may still have some use for the OVMF project on edk2 as
a sample platform.

> If
> you ported/modified existing code, I'd be interested in the original
> codebase to learn from it (especially what you had to change).

As I mentioned above, a good portion of the code was already available
in edk2.tianocore.org.  Edk2 is BSD licensed, and therefore from a
licensing perspective should be easy for your project to utilize.

>
>>> The coreboot solution would also avoid converting SeaBIOS because
>>> SeaBIOS already works as coreboot payload (that's how coreboot
>>> developers call the CSM).
>>>
>>
>> I'll bite, what's the advantage of doing coreboot + SeaBIOS vs.
>> SeaBIOS alone? ?Forget about EFI for the moment, should be considering
>> switching to coreboot + SeaBIOS for 0.12?
>
> Advantages:
> - Code coverage increase: SeaBIOS is used with coreboot on real
> hardware, so the BIOS interface part of SeaBIOS gets a lot more testing
> than the Qemu hardware init part of SeaBIOS.
>
> - coreboot supports real 440BX hardware besides Qemu, so the coreboot
> init code is exercised more (and there is still a sizable number of such
> machines around (clusters), many of them running coreboot).
>
> - Only one ROM image needed. A coreboot ROM can pack the VGA BIOS into
> the ROM image and SeaBIOS will automatically load it from there. Same
> for network card ROMs (with gPXE etc.).
>
> - coreboot ROMs (including those with SeaBIOS and/or EFI and/or VGABIOS)
> are archives and can be listed/edited with cbfstool if you want to know
> what's in there.
>
> - coreboot ROMs use compression, so you can stuff more code (and PCI
> option ROMs) into smaller ROMs.
>
> - coreboot has pretty verbose hardware init messages (if you want that)
> and can be totally silent as well. The messages end up in a log buffer
> which can be read by the OS (experimental feature, not available by
> default).
>
> There are a lot more advantages, but I want to give other coreboot
> developers a chance to chime in. If you add EFI to the mix, the
> synergies increase.
>
>
> Regards,
> Carl-Daniel
>



From jljusten at gmail.com  Sat Oct  3 02:32:32 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Fri, 2 Oct 2009 17:32:32 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC6872E.6060103@gmx.net>
References: <4AC29E4D.80707@us.ibm.com> <4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
Message-ID: <2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>

Carl-Daniel,

It sounds like there is a whole lot of overlap in what coreboot and
tianocore are trying to enable.

The key difference is that tianocore is focused on enabling the UEFI
interfaces within platforms.

OS loaders in UEFI are UEFI applications, and therefore just like in
the case of the UEFI shell (which is a UEFI application), they could
be embedded in the ROM.  So, this is similar to the coreboot payloads
concept.  But, it is not quite as central of a design goal for UEFI
systems as it appears to be within coreboot.

UEFI does provide runtime services that an OS can make use of, so that
sounds a bit different that coreboot.  (Linux does have support for
these interfaces.)  Essentially you can think of UEFI as a better
spec'd version of what the legacy BIOS was, but with more
extensibility designed into the interfaces.

Anyway, it sounds like a useful project might be to develop a UEFI
coreboot payload based on the tianocore.org code.  Our DUET platform
would only work on top of seabios, and OVMF has some overlap in
hardware initialization along with being a VM/QEMU specific solution.
Of course, we are always glad to hear if people are able to make use
of our code, and we like to encourage any UEFI or tianocore related
contributions to tianocore.org.

Thanks,

-Jordan

On Fri, Oct 2, 2009 at 16:05, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 03.10.2009 00:28, Jordan Justen wrote:
>> On Fri, Oct 2, 2009 at 14:39, Carl-Daniel Hailfinger
>> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>>
>>> Jordan, I have to admit that I'm surprised OVMF was apparently created
>>> from scratch although quite a few (established) hardware init solutions
>>> already exist for Qemu: SeaBIOS, Bochs BIOS, coreboot, and some old
>>> hobbyist projects.
>>>
>>
>> The edk2 project provides an infrastructure for building complete UEFI
>> firmware solutions. ?OVMF is a sample platform which demonstrates how
>> edk2 can be used to build firmware to boot a UEFI platform.
>>
>
> I wish to apologize for the misunderstanding. I thought OVMF was only
> hardware init. Thanks for correcting me.
>
>
>> Aside from just this, OVMF is an effort to support VMs on edk2. ?(Ie,
>> more than just QEMU.) ?Ideally the project, and code of OVMF could be
>> used by any VM vendor as a sample for building UEFI compatible
>> firmware.
>>
>
> How does it relate to real hardware? You mention OVMF as an effort to
> support VMs on edk2. Does this mean that VMs need special support or
> that real hardware has different needs?
>
>
>> Most of the code required to support QEMU was already open sourced on
>> edk2 before OVMF was launched. ?At the time that we started OVMF, it
>> did not seem like any project was targeting UEFI support on QEMU.
>> Tristan Gingold had done a port for UEFI QEMU support, but at that
>> time it did not seem to be functional with the current QEMU, nor
>> actively developed.
>>
>
> I see.
>
>
>>> I'd like to understand the reasons for that and fix
>>> them in coreboot (Kevin O'Connor will probably fix them in SeaBIOS).
>>>
>>
>> If you want to remove any need for OVMF on QEMU, then I think all that
>> is needed is to support booting UEFI OS's for both i386 and x86-64.
>> Of course, we may still have some use for the OVMF project on edk2 as
>> a sample platform.
>>
>
> Given that my original statement incorrectly assumed OVMF was only about
> hardware init, please let me try to express what I originally meant (and
> which came across with unintended meaning).
> I hope to use all EFI support code from OVMF, keep SeaBIOS, and have
> coreboot as common hardware init base.
>
>
>>> If
>>> you ported/modified existing code, I'd be interested in the original
>>> codebase to learn from it (especially what you had to change).
>>>
>>
>> As I mentioned above, a good portion of the code was already available
>> in edk2.tianocore.org.
>
> Thanks for the pointer.
>
>
>> Edk2 is BSD licensed, and therefore from a
>> licensing perspective should be easy for your project to utilize.
>>
>
> (Speaking with my coreboot hat on.)
> The goal of coreboot is not to assimilate and change other projects, but
> to provide hardware init for any code which needs it.
>
> After hardware init, it passes control to a payload (SeaBIOS, UEFI,
> GRUB2, FILO, Linux, Plan9...). There are no callbacks to coreboot, each
> payload is expected to talk to the hardware on its own. Except for ACPI
> tables (and a memory map), nothing of coreboot stays in memory after
> passing control to that payload. If you want some basic hardware drivers
> for your favourite payload, you can use the BSD-licensed libpayload
> library in your code, but most payloads (SeaBIOS, GRUB2, ...) have their
> own drivers anyway.
> Operating systems like Linux and Plan9 which do not need any BIOS/EFI
> interface can be stored in the ROM and will be booted directly by
> coreboot (if in ROM). Boot loaders like GRUB2 or FILO don't need
> BIOS/EFI either, can be stored in ROM and will then be booted directly.
> BIOS and EFI code can be used as a coreboot payload in ROM as well. Some
> people are even working on making U-Boot available as coreboot payload.
>
> The idea is to have coreboot handle all the hardware-specific
> initialization and allow all other code to be mostly hardware-agnostic
> (unless said code wants to implement drivers). The clean interface
> (well, no interface, coreboot just passes control to the payload) allows
> payloads to do whatever they want as long as they provide a single
> 32-bit entry point coreboot can jump to.
>
>
> Regards,
> Carl-Daniel
>



From patrick at georgi-clan.de  Sat Oct  3 16:48:32 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 03 Oct 2009 16:48:32 +0200
Subject: [coreboot] [PATCH]fix various vgabios.c copies in light of CBFS
Message-ID: <1254581312.3224.18.camel@tetris>

Hi,

there were a couple of copies of vgabios.c that looked for the option
rom image at fixed addresses (usually begin of flash), which is not the
supported way of doing things anymore.

As this patch removes the non-CBFS capability, I'd commit it right after
the removal of non-CBFS support this evening (in ~3 hours), as non-CBFS
support isn't necessary anymore at that point.

Of course, the duplication should be eliminated, as well as (some of)
the rom_address entries in Config.lb and devicetree.cb for the boards.

It might also be worthwhile to investigate if src/devices/pci_rom.c
couldn't be used for the option rom loading. Just using dev->rom_address
didn't work on my board, but this fix was good enough for me for now.

The change is the same in all vgabios.c files, it's boot tested on cx700
(via/vt8454c), via/epia-m and artecgroup/dbe61 are build tested.
Furthermore,
for cn400, via/epia-n built,
for cn700, via/epia-cn built,
for vx800, via/epia-m700 built

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
-------------- next part --------------
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From gleb at redhat.com  Sat Oct  3 17:08:03 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Sat, 3 Oct 2009 17:08:03 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC67326.6080603@gmx.net>
References: <D0452B81-706B-4154-92E1-6E253A305053@claunia.com>
	<4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>
	<4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
Message-ID: <20091003150803.GF17326@redhat.com>

On Fri, Oct 02, 2009 at 11:39:50PM +0200, Carl-Daniel Hailfinger wrote:
> > I'll bite, what's the advantage of doing coreboot + SeaBIOS vs.
> > SeaBIOS alone?  Forget about EFI for the moment, should be considering
> > switching to coreboot + SeaBIOS for 0.12?
> 
> Advantages:
> - Code coverage increase: SeaBIOS is used with coreboot on real
> hardware, so the BIOS interface part of SeaBIOS gets a lot more testing
> than the Qemu hardware init part of SeaBIOS.
> 
> - coreboot supports real 440BX hardware besides Qemu, so the coreboot
> init code is exercised more (and there is still a sizable number of such
> machines around (clusters), many of them running coreboot).
> 
QEMU goal is to run popular OSes and OS usually don't care about low level
chipset details. That's way QEMU's chipset emulation implements only
bare minimum that is needed for OS to run: no need to initialize memory
controller for instance. Coreboot goal, on the other hand, is to talk to
real HW, so to use it on QEMU will require implementing chipset features
that are not needed to accomplish QEMU goal. So for me real 440BX
hardware support of coreboot is actually disadvantage. QEMU don't
have real 440BX hardware and there is not point in having one. It is
possible to implement 440BX-qemu support in coreboot of course if there
are other advantages worth having.

> - Only one ROM image needed. A coreboot ROM can pack the VGA BIOS into
> the ROM image and SeaBIOS will automatically load it from there. Same
> for network card ROMs (with gPXE etc.).
> 
> - coreboot ROMs (including those with SeaBIOS and/or EFI and/or VGABIOS)
> are archives and can be listed/edited with cbfstool if you want to know
> what's in there.
> 
> - coreboot ROMs use compression, so you can stuff more code (and PCI
> option ROMs) into smaller ROMs.
> 
> - coreboot has pretty verbose hardware init messages (if you want that)
> and can be totally silent as well. The messages end up in a log buffer
> which can be read by the OS (experimental feature, not available by
> default).
> 
> There are a lot more advantages, but I want to give other coreboot
> developers a chance to chime in. If you add EFI to the mix, the
> synergies increase.
> 
> 
> Regards,
> Carl-Daniel
> 

--
			Gleb.



From stepan at coresystems.de  Sat Oct  3 17:29:42 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Oct 2009 17:29:42 +0200
Subject: [coreboot] [PATCH]fix various vgabios.c copies in light of CBFS
In-Reply-To: <1254581312.3224.18.camel@tetris>
References: <1254581312.3224.18.camel@tetris>
Message-ID: <4AC76DE6.5060606@coresystems.de>

Patrick Georgi wrote:
> Hi,
>
> there were a couple of copies of vgabios.c that looked for the option
> rom image at fixed addresses (usually begin of flash), which is not the
> supported way of doing things anymore.
>
> As this patch removes the non-CBFS capability, I'd commit it right after
> the removal of non-CBFS support this evening (in ~3 hours), as non-CBFS
> support isn't necessary anymore at that point.
>
> Of course, the duplication should be eliminated, as well as (some of)
> the rom_address entries in Config.lb and devicetree.cb for the boards.
>
> It might also be worthwhile to investigate if src/devices/pci_rom.c
> couldn't be used for the option rom loading. Just using dev->rom_address
> didn't work on my board, but this fix was good enough for me for now.
>
> The change is the same in all vgabios.c files, it's boot tested on cx700
> (via/vt8454c), via/epia-m and artecgroup/dbe61 are build tested.
> Furthermore,
> for cn400, via/epia-n built,
> for cn700, via/epia-cn built,
> for vx800, via/epia-m700 built
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From svn at coreboot.org  Sat Oct  3 17:34:08 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 17:34:08 +0200
Subject: [coreboot] [v2] r4711 - in trunk/coreboot-v2/src/mainboard:
	a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 amd/rumba
	amd/serengeti_cheetah asus/m2v-mx_se asus/mew-am asus/mew-vm
	asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p3b-f
	azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600
	dell/s1850 emulation/qemu-x86 gigabyte/ga-6bxc
	intel/eagleheights intel/jarrell intel/mtarvon intel/truxton
	intel/xe7501devkit kontron/986lcd-m mitac/6513wu msi/ms6119
	msi/ms6147 msi/ms6178 nec/powermate2000 soyo/sy-6ba-plus-iii
	sunw/ultra40 supermicro/h8dme tyan/s1846 tyan/s2850
	tyan/s2875 tyan/s2881 tyan/s2891 tyan/s2892 tyan/s2895
	via/epia via/epia-cn via/epia-m via/epia-m700 via/epia-n
	via/pc2500e via/vt8454c
Message-ID: <mailman.3782.1355071627.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-10-03 17:34:08 +0200 (Sat, 03 Oct 2009)
New Revision: 4711

Modified:
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig
   trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Kconfig
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig
   trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig
   trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig
   trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia/Kconfig
   trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig
   trunk/coreboot-v2/src/mainboard/via/vt8454c/Kconfig
Log:
Remove duplicate and not too useful Kconfig board comments as
per discussion on the mailing list.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>



Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  A-Trend ATC-6220 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  A-Trend ATC-6240 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  Abit BE6-II V2.0 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -27,8 +27,6 @@
 	select UDELAY_TSC
 	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 	select HAVE_PIRQ_TABLE
-	help
-	  AMD Rumba mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -11,8 +11,6 @@
 	select HAVE_PIRQ_TABLE
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
-	help
-	 AMD Serengeti Cheetah mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -34,8 +34,6 @@
 	select IOAPIC
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
-	help
-	  Asus M2V-MX SE mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS MEW-AM mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS MEW-VM mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS P2B mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -32,8 +32,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS P2B-D mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -32,8 +32,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS P2B-DS mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS P2B-F mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  ASUS P3B-F mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  AZZA PT-6IBD mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  Biostar M6TBA mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -30,8 +30,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  Compaq Deskpro EN SFF P600 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -7,8 +7,6 @@
 	select SOUTHBRIDGE_INTEL_PXHD
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
-	help
-	  Dell PowerEdge 1850 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -5,8 +5,6 @@
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select CPU_EMULATION_QEMU_X86
 	select CONSOLE_SERIAL8250
-	help
-	  x86 QEMU variant.
 
 config MAINBOARD_DIR
 	string
@@ -15,5 +13,5 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "QEMU-86"
+	default "QEMU-x86"
 	depends on BOARD_EMULATION_QEMU_X86

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  GIGABYTE GA-6BXC mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -12,8 +12,6 @@
 	select UDELAY_TSC
 	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 	select AP_IN_SIPI_WAIT
-	help
-          Intel EagleHeights mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -8,8 +8,6 @@
 	select SUPERIO_NSC_PC87427
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
-	help
-          Intel Jarrell (SE7520JR2) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -7,8 +7,6 @@
 	select SUPERIO_INTEL_I3100
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
-	help
-          Intel 3100 devkit (Mt. Arvon) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -8,8 +8,6 @@
 	select SUPERIO_SMSC_SMSCSUPERIO
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
-	help
-          Intel EP80579 devkit (Truxton) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -8,8 +8,6 @@
 	select SUPERIO_SMSC_LPC47B272
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
-	help
-          Intel XE7501devkit mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -10,8 +10,6 @@
 	select MMCONF_SUPPORT
 	select USE_PRINTK_IN_CAR
 	select AP_IN_SIPI_WAIT
-	help
-          Kontron 986LCD-M/mITX mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  Mitac 6513WU mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  MSI MS-6119 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  MSI MS-6147 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  MSI MS-6178 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  NEC PowerMate 2000 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -29,8 +29,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  SOYO SY-6BA+ III mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -10,8 +10,6 @@
 	select HAVE_PIRQ_TABLE
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
-	help
-	 Sun Ultra 40 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -10,8 +10,6 @@
 	select HAVE_PIRQ_TABLE
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
-	help
-	  Supermicro H8DME mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -28,8 +28,6 @@
 	select UDELAY_IO
 	select PCI_ROM_RUN
 	select CONSOLE_VGA
-	help
-	  Tyan Tsunami ATX (S1846) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -8,8 +8,6 @@
 	select SOUTHBRIDGE_AMD_AMD8111
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
-	help
-	  Tyan Tomcat K8S (S2850) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -9,8 +9,6 @@
 	select SOUTHBRIDGE_AMD_AMD8111
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
-	help
-	  Tyan Tiger K8W (S2875) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -9,8 +9,6 @@
 	select SOUTHBRIDGE_AMD_AMD8111
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
-	help
-	  Tyan Thunder K8SR (S2881) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -9,8 +9,6 @@
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
-	help
-	  Tyan Thunder K8SRE (S2891) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -9,8 +9,6 @@
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_WINBOND_W83627HF
 	select PIRQ_TABLE
-	help
-	  Tyan Thunder K8SE (S2892) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -9,8 +9,6 @@
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_SMSC_LPC47B397
 	select PIRQ_TABLE
-	help
-	  Tyan Thunder K8WE (S2895) mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/epia/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/epia/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -6,8 +6,6 @@
 	select SOUTHBRIDGE_VIA_VT8231
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA EPIA mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -6,8 +6,6 @@
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SUPERIO_VIA_VT1211
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA EPIA-CN mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -7,8 +7,6 @@
 	select SOUTHBRIDGE_RICOH_RL5C476
 	select SUPERIO_VIA_VT1211
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA EPIA-M mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -5,8 +5,6 @@
 	select NORTHBRIDGE_VIA_VX800
 	select SUPERIO_WINBOND_W83697HF
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA EPIA-M700 mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -6,8 +6,6 @@
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SUPERIO_WINBOND_W83697HF
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA EPIA-N mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -6,8 +6,6 @@
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SUPERIO_ITE_IT8716F
 	select HAVE_PIRQ_TABLE
-	help
-	  VIA pc2500e mainboard.
 
 config MAINBOARD_DIR
 	string

Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/vt8454c/Kconfig	2009-10-02 15:46:10 UTC (rev 4710)
+++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
@@ -8,8 +8,6 @@
 	select HAVE_PIRQ_TABLE
 #	select MMCONF_SUPPORT
 	select USE_PRINTK_IN_CAR
-	help
-	  VIA VT8454C mainboard.
 
 config MAINBOARD_DIR
 	string




From stepan at coresystems.de  Sat Oct  3 17:50:22 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Oct 2009 17:50:22 +0200
Subject: [coreboot] [v2] r4707 -
 in	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
In-Reply-To: <20091002161206.19314.qmail@stuge.se>
References: <20091002001157.2403.qmail@stuge.se>	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>	<20091002125035.GG15511@greenwood>	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
Message-ID: <4AC772BE.4010403@coresystems.de>

Peter Stuge wrote:
> ron minnich wrote:
>   
>>> Why is the port/directory named S1850 instead of 1850 though? Just to
>>> have a letter as first character, or is the board _actually_ called
>>> "S1850"? If so, do you have a more correct vendor website we can link to?
>>>       
>> It say s1850 on the front I think.
>>     
>
> This one?
>
> http://gtk.no/images/bim/server/bim2.jpg
>
> It could simply be that the board name can't be all numbers. I don't
> know if we actually have that restriction?
>   

what about renaming it to pe1850?




From stepan at coresystems.de  Sat Oct  3 17:56:08 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Oct 2009 17:56:08 +0200
Subject: [coreboot] SPD sanity check
In-Reply-To: <13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>	<4AC555A3.1000700@settoplinux.org>	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>	<4AC5E9C7.90304@gmx.net>	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
	<13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
Message-ID: <4AC77418.303@coresystems.de>

ron minnich wrote:
> BTW, THANKS for the note. I was hoping for a note from an expert :-)
>
> That leading bytes sure looked like SPD but my obsolete JDEC docs threw me off.
>
> Now I wonder why I only see one SPD ... but that's grist for another
> note in little bit.
>
> Thanks
>
> ron
>
>   
What other devices do you see on that smbus? Some systems have smbus
switches, and you won't see the SPD devices unless you configure the
switch to the correct position.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
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Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From stepan at coresystems.de  Sat Oct  3 18:08:02 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Oct 2009 18:08:02 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC5D02F.4040305@gmx.net>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>	<20091001235825.GA29687@morn.localdomain>	<4AC5CDCB.7080901@georgi-clan.de>
	<4AC5D02F.4040305@gmx.net>
Message-ID: <4AC776E2.4040908@coresystems.de>

Carl-Daniel Hailfinger wrote:
> On 02.10.2009 11:54, Patrick Georgi wrote:
>   
>> We need to have access to CMOS before CAR or raminit, or anything
>> interesting happens, really. And I'm not sure if our code supports
>> this everywhere already.
>>     
>
> IMHO access to CMOS before CAR is unnecessarily painful and I'd like to
> keep that out of the targets which don't need it (VIA/AMD).
>   


Then how are we going to update CAR code in case a new CPU revision
needs an update while still keeping normal/fallback alive?


Stefan



From uwe at hermann-uwe.de  Sat Oct  3 18:08:07 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 3 Oct 2009 18:08:07 +0200
Subject: [coreboot] [v2] r4707 - in	trunk/coreboot-v2:
 src/mainboard/dell/s1850 targets
In-Reply-To: <4AC772BE.4010403@coresystems.de>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
	<4AC772BE.4010403@coresystems.de>
Message-ID: <20091003160807.GI15511@greenwood>

On Sat, Oct 03, 2009 at 05:50:22PM +0200, Stefan Reinauer wrote:
> > This one?
> >
> > http://gtk.no/images/bim/server/bim2.jpg
> >
> > It could simply be that the board name can't be all numbers. I don't
> > know if we actually have that restriction?
> >   
> 
> what about renaming it to pe1850?

Or poweredge_1850 if we're going to rename, so dirnames match the actual
board name.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From svn at coreboot.org  Sat Oct  3 18:24:58 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 18:24:58 +0200
Subject: [coreboot] [v2] r4712 - in trunk/coreboot-v2: src src/arch/i386
	src/arch/i386/init src/arch/i386/lib src/arch/ppc src/boot
	src/config src/cpu/amd/car src/cpu/amd/model_lx
	src/cpu/x86/car src/devices src/lib
	src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240
	src/mainboard/abit/be6-ii_v2_0
	src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800
	src/mainboard/amd/dbm690t src/mainboard/amd/norwich
	src/mainboard/amd/pistachio src/mainboard/amd/rumba
	src/mainboard/amd/serengeti_cheetah
	src/mainboard/amd/serengeti_cheetah_fam10
	src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61
	src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp
	src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se
	src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am
	src/mainboard/asus/mew-vm src/mainboard/asus/p2b
	src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds
	src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f
	src/mainboard/axus/tc320 src/mainboard/azza/pt-6ibd
	src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680
	src/mainboard/biostar/m6tba src/mainboard/broadcom/blast
	src/mainboard/compaq/deskpro_en_sff_p600
	src/mainboard/dell/s1850 src/mainboard/digitallogic/adl855pc
	src/mainboard/digitallogic/msm586seg
	src/mainboard/digitallogic/msm800sev
	src/mainboard/eaglelion/5bcm src/mainboard/emulation/qemu-x86
	src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk
	src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3
	src/mainboard/ibm/e325 src/mainboard/ibm/e326
	src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r
	src/mainboard/iei/pcisa-lx-800-r10
	src/mainboard/intel/eagleheights src/mainboard/intel/jarrell
	src/mainboard/intel/mtarvon src/mainboard/intel/truxton
	src/mainboard/intel/xe7501devkit src/mainboard/iwill/dk8_htx
	src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x
	src/mainboard/jetway/j7f24 src/mainboard/kontron/986lcd-m
	src/mainboard/lippert/frontrunner
	src/mainboard/lippert/roadrunner-lx
	src/mainboard/lippert/spacerunner-lx
	src/mainboard/mitac/6513wu src/mainboard/msi/ms6119
	src/mainboard/msi/ms6147 src/mainboard/msi/ms6178
	src/mainboard/msi/ms7135 src/mainboard/msi/ms7260
	src/mainboard/msi/ms9185 src/mainboard/msi/ms9282
	src/mainboard/nec/powermate2000 src/mainboard/newisys/khepri
	src/mainboard/nvidia/l1_2pvv src/mainboard/olpc/btest
	src/mainboard/olpc/rev_a src/mainboard/pcengines/alix1c
	src/mainboard/rca/rm4100 src/mainboard/soyo/sy-6ba-plus-iii
	src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme
	src/mainboard/supermicro/h8dmr src/mainboard/supermicro/h8dmr_fam10
	src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g
	src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig
	src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690
	src/mainboard/technologic/ts5300
	src/mainboard/televideo/tc7020 src/mainboard/thomson/ip1000
	src/mainboard/tyan/s1846 src/mainboard/tyan/s2735
	src/mainboard/tyan/s2850 src/mainboard/tyan/s2875
	src/mainboard/tyan/s2880 src/mainboard/tyan/s2881
	src/mainboard/tyan/s2882 src/mainboard/tyan/s2885
	src/mainboard/tyan/s2891 src/mainboard/tyan/s2892
	src/mainboard/tyan/s2895 src/mainboard/tyan/s2912
	src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880
	src/mainboard/tyan/s4882 src/mainboard/via/epia
	src/mainboard/via/epia-cn src/mainboard/via/epia-m
	src/mainboard/via/epia-m700 src/mainboard/via/epia-n
	src/mainboard/via/pc2500e src/mainboard/via/vt8454c
	targets/kontron/986lcd-m targets/lippert/roadrunner-lx
	targets/lippert/spacerunner-lx util/abuild util/newconfig
Message-ID: <mailman.3783.1355071627.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-03 18:24:58 +0200 (Sat, 03 Oct 2009)
New Revision: 4712

Removed:
   trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
   trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
   trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c
   trunk/coreboot-v2/src/boot/elfboot.c
   trunk/coreboot-v2/src/boot/filo.c
   trunk/coreboot-v2/src/stream/
Modified:
   trunk/coreboot-v2/src/Kconfig
   trunk/coreboot-v2/src/arch/i386/Config.lb
   trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
   trunk/coreboot-v2/src/arch/i386/lib/Config.lb
   trunk/coreboot-v2/src/arch/ppc/Config.lb
   trunk/coreboot-v2/src/boot/Config.lb
   trunk/coreboot-v2/src/boot/hardwaremain.c
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/config/failovercalculation.lb
   trunk/coreboot-v2/src/config/nofailovercalculation.lb
   trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
   trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
   trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
   trunk/coreboot-v2/src/devices/pci_rom.c
   trunk/coreboot-v2/src/lib/Config.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
   trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
   trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c
   trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
   trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
   trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
   trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb
   trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
   trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
   trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia/Options.lb
   trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb
   trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb
   trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb
   trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb
   trunk/coreboot-v2/targets/lippert/spacerunner-lx/Config.lb
   trunk/coreboot-v2/util/abuild/abuild
   trunk/coreboot-v2/util/newconfig/config.g
Log:
Remove:
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)

After this commit, there is no way to build an image that is not using
CBFS anymore.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/Kconfig
===================================================================
--- trunk/coreboot-v2/src/Kconfig	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/Kconfig	2009-10-03 16:24:58 UTC (rev 4712)
@@ -36,10 +36,6 @@
 source src/superio/Kconfig
 source src/cpu/Kconfig
 
-config CBFS
-	bool
-	default y
-
 config PCI_BUS_SEGN_BITS
 	int
 	default 0

Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,45 +1,29 @@
-uses CONFIG_CBFS
 uses CONFIG_SMP
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_USE_INIT
 uses CONFIG_HAVE_FAILOVER_BOOT
 uses CONFIG_USE_FAILOVER_IMAGE
 uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_CBFS
 
 init init/crt0.S.lb
 
-if CONFIG_CBFS
-	if CONFIG_USE_FAILOVER_IMAGE
-	else
-		initobject /src/lib/cbfs.o
-		initobject /src/lib/lzma.o
-	end
+if CONFIG_USE_FAILOVER_IMAGE
+else
+	initobject /src/lib/cbfs.o
+	initobject /src/lib/lzma.o
 end
 
 if CONFIG_HAVE_FAILOVER_BOOT
 	if CONFIG_USE_FAILOVER_IMAGE
 		ldscript init/ldscript_failover.lb
 	else
-		if CONFIG_CBFS
 			ldscript init/ldscript_cbfs.lb
-		else
-			ldscript init/ldscript.lb
-		end
 	end
 else
-	if CONFIG_CBFS
-		if CONFIG_USE_FALLBACK_IMAGE
-			ldscript init/ldscript_fallback_cbfs.lb
-		else
-			ldscript init/ldscript_cbfs.lb
-		end
+	if CONFIG_USE_FALLBACK_IMAGE
+		ldscript init/ldscript_fallback_cbfs.lb
 	else
-		if CONFIG_USE_FALLBACK_IMAGE
-			ldscript init/ldscript_fallback.lb
-		else
-			ldscript init/ldscript.lb
-		end
+		ldscript init/ldscript_cbfs.lb
 	end
 end
 
@@ -82,13 +66,6 @@
 # catch the case where there is no compression
 makedefine PAYLOAD-1:=payload
 
-if CONFIG_CBFS
-else
-# match the case where a compression type is specified.
-makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_NRV2B):=payload.nrv2b
-makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_LZMA):=payload.lzma
-end
-
 # catch the case where there is precompression. Yes, this bites. 
 if CONFIG_PRECOMPRESSED_PAYLOAD 
 	makedefine PAYLOAD-1:=payload
@@ -105,8 +82,8 @@
 else
 	makerule coreboot.rom 
 		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
-		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi"
+		action "touch cbfs-support; ./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
+		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 ]; then echo l > cbfs-support; fi"
 	end
 end
 

Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -74,19 +74,8 @@
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl %esi
-#if CONFIG_CBFS == 1
 	pushl $str_coreboot_ram_name
 	call cbfs_and_run_core
-#else
-	movl	$_liseg, %esi
-	movl	$_iseg,  %edi
-	movl	$_eiseg, %ecx
-	subl	%edi, %ecx
-	pushl %ecx
-	pushl %edi
-	pushl %esi
-	call copy_and_run_core
-#endif
 
 .Lhlt:	
 	intel_chip_post_macro(0xee)	/* post fe */
@@ -148,12 +137,10 @@
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
 
-#if CONFIG_CBFS == 1
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
-# else
+#else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
-# endif
 #endif
 
 #endif /* CONFIG_USE_DCACHE_RAM */

Deleted: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,70 +0,0 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		
- *				: data segment
- *				: bss segment
- *				: heap
- *				: stack
- *	CONFIG_ROMBASE
- *				: coreboot text 
- *				: readonly text
- */
-/*
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- *
- */
-
-/*
- *	Written by Johan Rydberg, based on work by Daniel Kahlin.
- *      Rewritten by Eric Biederman
- */
-/*
- *	We use ELF as output format. So that we can
- *	debug the code in some form. 
- */
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
-OUTPUT_ARCH(i386)
-
-/*
-ENTRY(_start)
-*/
-
-TARGET(binary)
-INPUT(coreboot_ram.rom)
-SECTIONS
-{
-	. = CONFIG_ROMBASE;
-
-	.ram . : {
-		_ram = . ;
-		coreboot_ram.rom(*)
-		_eram = . ;
-	}
-
-	/* This section might be better named .setup */
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.rodata.*);
-		*(.rom.data.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	_lrom = LOADADDR(.rom);
-	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = CONFIG_RAMBASE;
-	_eiseg = _iseg + SIZEOF(.ram);
-	_liseg = _ram;
-	_eliseg = _eram;
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.comment.*)
-		*(.note)
-		*(.note.*)
-	}
-}

Deleted: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,75 +0,0 @@
-/*
- *	Memory map:
- *
- *	CONFIG_RAMBASE		
- *				: data segment
- *				: bss segment
- *				: heap
- *				: stack
- *	CONFIG_ROMBASE
- *				: coreboot text 
- *				: readonly text
- */
-/*
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- *
- */
-
-/*
- *	Written by Johan Rydberg, based on work by Daniel Kahlin.
- *      Rewritten by Eric Biederman
- */
-/*
- *	We use ELF as output format. So that we can
- *	debug the code in some form. 
- */
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
-OUTPUT_ARCH(i386)
-
-/*
-ENTRY(_start)
-*/
-
-TARGET(binary)
-INPUT(coreboot_ram.rom)
-SECTIONS
-{
-	. = CONFIG_ROMBASE;
-
-	.ram . : {
-		_ram = . ;
-		coreboot_ram.rom(*)
-		_eram = . ;
-	}
-
-	/* cut _start into last 64k*/
-	_x = .;
-	. = (_x < (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 +  CONFIG_ROM_IMAGE_SIZE) : _x;
-
-	/* This section might be better named .setup */
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.init.rodata.*);
-		*(.rodata.*);
-		*(.rom.data.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	_lrom = LOADADDR(.rom);
-	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	_iseg = CONFIG_RAMBASE;
-	_eiseg = _iseg + SIZEOF(.ram);
-	_liseg = _ram;
-	_eliseg = _eram;
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-	}
-}

Modified: trunk/coreboot-v2/src/arch/i386/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/lib/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,7 +1,6 @@
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_CBFS
 
 object c_start.S
 object cpu.c
@@ -15,9 +14,5 @@
 
 if CONFIG_USE_FAILOVER_IMAGE
 else
-	if CONFIG_CBFS
-		initobject cbfs_and_run.o
-	else
-		initobject copy_and_run.o
-	end
+	initobject cbfs_and_run.o
 end

Deleted: trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,53 +0,0 @@
-/* by yhlu 6.2005
-	moved from nrv2v.c and some lines from crt0.S
-   2006/05/02 - stepan: move nrv2b to an extra file.
-*/
-
-#include <console/console.h>
-#include <stdint.h>
-#include <string.h>
-
-#if CONFIG_COMPRESS
-#define ENDIAN   0
-#define BITSIZE 32
-#include "../lib/nrv2b.c"
-#endif
-
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp)
-{
-        unsigned long olen;
-
-#if CONFIG_USE_INIT
-	printk_spew("src=%08x\r\n",src);
-	printk_spew("dst=%08x\r\n",dst);
-#else
-        print_spew("src="); print_spew_hex32((uint32_t)src); print_spew("\r\n");
-        print_spew("dst="); print_spew_hex32((uint32_t)dst); print_spew("\r\n");
-#endif
-
-#if !CONFIG_COMPRESS
-	print_debug("Copying image to RAM.\r\n");
-	memcpy(src, dst, ilen);
-	olen = ilen;
-#else
-	print_debug("Uncompressing image to RAM.\r\n");
-//	dump_mem(src, src+0x100);
-	olen = unrv2b(src, dst, &ilen);
-#endif
-
-//	dump_mem(dst, dst+0x100);
-#if CONFIG_USE_INIT
-	printk_spew("image length = %08x\r\n", olen);
-#else
-	print_spew("image length = "); print_spew_hex32(olen); print_spew("\r\n");
-#endif
-	print_debug("Jumping to image.\r\n");
-
-	__asm__ volatile (
-		"movl %%eax, %%ebp\n\t"
-		"cli\n\t"
-		"jmp     *%%edi\n\t"
-		:: "a"(ebp), "D"(dst)
-	);
-
-}

Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,4 +1,3 @@
-uses CONFIG_CBFS
 ldscript init/ldscript.lb
 
 makerule coreboot.strip 
@@ -11,10 +10,8 @@
 	action "cp $< $@"
 end
 
-if CONFIG_CBFS
-	initobject /src/lib/cbfs.o
-	initobject /src/lib/lzma.o
-end
+initobject /src/lib/cbfs.o
+initobject /src/lib/lzma.o
 
 dir init
 dir lib

Modified: trunk/coreboot-v2/src/boot/Config.lb
===================================================================
--- trunk/coreboot-v2/src/boot/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/boot/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,9 +1,2 @@
 object hardwaremain.o
-if CONFIG_CBFS
-	object selfboot.o
-else
-	object elfboot.o
-end
-if CONFIG_FS_PAYLOAD
-	object filo.o
-end
+object selfboot.o

Deleted: trunk/coreboot-v2/src/boot/elfboot.c
===================================================================
--- trunk/coreboot-v2/src/boot/elfboot.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/boot/elfboot.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,687 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Eric W. Biederman <ebiederm at xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <part/fallback_boot.h>
-#include <boot/elf.h>
-#include <boot/elf_boot.h>
-#include <boot/coreboot_tables.h>
-#include <ip_checksum.h>
-#include <stream/read_bytes.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Maximum physical address we can use for the coreboot bounce buffer.
- */
-#ifndef MAX_ADDR
-#define MAX_ADDR -1UL
-#endif
-
-extern unsigned char _ram_seg;
-extern unsigned char _eram_seg;
-
-struct segment {
-	struct segment *next;
-	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
-	unsigned long s_addr;
-	unsigned long s_memsz;
-	unsigned long s_offset;
-	unsigned long s_filesz;
-};
-
-struct verify_callback {
-	struct verify_callback *next;
-	int (*callback)(struct verify_callback *vcb, 
-		Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head);
-	unsigned long desc_offset;
-	unsigned long desc_addr;
-};
-
-struct ip_checksum_vcb {
-	struct verify_callback data;
-	unsigned short ip_checksum;
-};
-
-int verify_ip_checksum(
-	struct verify_callback *vcb, 
-	Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head)
-{
-	struct ip_checksum_vcb *cb;
-	struct segment *ptr;
-	unsigned long bytes;
-	unsigned long checksum;
-	unsigned char buff[2], *n_desc;
-	cb = (struct ip_checksum_vcb *)vcb;
-	/* zero the checksum so it's value won't
-	 * get in the way of verifying the checksum.
-	 */
-	n_desc = 0;
-	if (vcb->desc_addr) {
-		n_desc = (unsigned char *)(vcb->desc_addr);
-		memcpy(buff, n_desc, 2);
-		memset(n_desc, 0, 2);
-	}
-	bytes = 0;
-	checksum = compute_ip_checksum(ehdr, sizeof(*ehdr));
-	bytes += sizeof(*ehdr);
-	checksum = add_ip_checksums(bytes, checksum, 
-		compute_ip_checksum(phdr, ehdr->e_phnum*sizeof(*phdr)));
-	bytes += ehdr->e_phnum*sizeof(*phdr);
-	for(ptr = head->phdr_next; ptr != head; ptr = ptr->phdr_next) {
-		checksum = add_ip_checksums(bytes, checksum,
-			compute_ip_checksum((void *)ptr->s_addr, ptr->s_memsz));
-		bytes += ptr->s_memsz;
-	}
-	if (n_desc != 0) {
-		memcpy(n_desc, buff, 2);
-	}
-	if (checksum != cb->ip_checksum) {
-		printk_err("Image checksum: %04x != computed checksum: %04lx\n",
-			cb->ip_checksum, checksum);
-	}
-	return checksum == cb->ip_checksum;
-}
-
-/* The problem:  
- * Static executables all want to share the same addresses
- * in memory because only a few addresses are reliably present on
- * a machine, and implementing general relocation is hard.
- *
- * The solution:
- * - Allocate a buffer the size of the coreboot image plus additional
- *   required space.
- * - Anything that would overwrite coreboot copy into the lower part of
- *   the buffer. 
- * - After loading an ELF image copy coreboot to the top of the buffer.
- * - Then jump to the loaded image.
- * 
- * Benefits:
- * - Nearly arbitrary standalone executables can be loaded.
- * - Coreboot is preserved, so it can be returned to.
- * - The implementation is still relatively simple,
- *   and much simpler then the general case implemented in kexec.
- * 
- */
-
-static unsigned long bounce_size;
-
-static unsigned long get_bounce_buffer(struct lb_memory *mem)
-{
-	unsigned long lb_size;
-	unsigned long mem_entries;
-	unsigned long buffer;
-	int i;
-	lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
-	/* Double coreboot size so I have somewhere to place a copy to return to */
-	bounce_size = lb_size;
-	lb_size = bounce_size + lb_size;
-	mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
-	buffer = 0;
-	for(i = 0; i < mem_entries; i++) {
-		unsigned long mstart, mend;
-		unsigned long msize;
-		unsigned long tbuffer;
-		if (mem->map[i].type != LB_MEM_RAM)
-			continue;
-		if (unpack_lb64(mem->map[i].start) > MAX_ADDR)
-			continue;
-		if (unpack_lb64(mem->map[i].size) < lb_size)
-			continue;
-		mstart = unpack_lb64(mem->map[i].start);
-		msize = MAX_ADDR - mstart +1;
-		if (msize > unpack_lb64(mem->map[i].size))
-			msize = unpack_lb64(mem->map[i].size);
-		mend = mstart + msize;
-		tbuffer = mend - lb_size;
-		if (tbuffer < buffer) 
-			continue;
-		buffer = tbuffer;
-	}
-	return buffer;
-}
-
-
-static struct verify_callback *process_elf_notes(
-	unsigned char *header, 
-	unsigned long offset, unsigned long length)
-{
-	struct verify_callback *cb_chain;
-	unsigned char *note, *end;
-	unsigned char *program, *version;
-
-	cb_chain = 0;
-	note = header + offset;
-	end = note + length;
-	program = version = 0;
-	while(note < end) {
-		Elf_Nhdr *hdr;
-		unsigned char *n_name, *n_desc, *next;
-		hdr = (Elf_Nhdr *)note;
-		n_name = note + sizeof(*hdr);
-		n_desc = n_name + ((hdr->n_namesz + 3) & ~3);
-		next = n_desc + ((hdr->n_descsz + 3) & ~3);
-		if (next > end) {
-			break;
-		}
-		if ((hdr->n_namesz == sizeof(ELF_NOTE_BOOT)) && 
-			(memcmp(n_name, ELF_NOTE_BOOT, sizeof(ELF_NOTE_BOOT)) == 0)) {
-			switch(hdr->n_type) {
-			case EIN_PROGRAM_NAME:
-				if (n_desc[hdr->n_descsz -1] == 0) {
-					program = n_desc;
-				}
-				break;
-			case EIN_PROGRAM_VERSION:
-				if (n_desc[hdr->n_descsz -1] == 0) {
-					version = n_desc;
-				}
-				break;
-			case EIN_PROGRAM_CHECKSUM:
-			{
-				struct ip_checksum_vcb *cb;
-				cb = malloc(sizeof(*cb));
-				cb->ip_checksum = *((uint16_t *)n_desc);
-				cb->data.callback = verify_ip_checksum;
-				cb->data.next = cb_chain;
-				cb->data.desc_offset = n_desc - header;
-				cb_chain = &cb->data;
-				break;
-			}
-			}
-		}
-		printk_spew("n_type: %08x n_name(%d): %-*.*s n_desc(%d): %-*.*s\n", 
-			hdr->n_type,
-			hdr->n_namesz, hdr->n_namesz, hdr->n_namesz, n_name,
-			hdr->n_descsz,hdr->n_descsz, hdr->n_descsz, n_desc);
-		note = next;
-	}
-	if (program && version) {
-		printk_info("Loading %s version: %s\n",
-			program, version);
-	}
-	return cb_chain;
-}
-
-static int valid_area(struct lb_memory *mem, unsigned long buffer,
-	unsigned long start, unsigned long len)
-{
-	/* Check through all of the memory segments and ensure
-	 * the segment that was passed in is completely contained
-	 * in RAM.
-	 */
-	int i;
-	unsigned long end = start + len;
-	unsigned long mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
-
-	/* See if I conflict with the bounce buffer */
-	if (end >= buffer) {
-		return 0;
-	}
-
-	/* Walk through the table of valid memory ranges and see if I
-	 * have a match.
-	 */
-	for(i = 0; i < mem_entries; i++) {
-		uint64_t mstart, mend;
-		uint32_t mtype;
-		mtype = mem->map[i].type;
-		mstart = unpack_lb64(mem->map[i].start);
-		mend = mstart + unpack_lb64(mem->map[i].size);
-		if ((mtype == LB_MEM_RAM) && (start < mend) && (end > mstart)) {
-			break;
-		}
-		if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) {
-			printk_err("Payload is overwriting Coreboot tables.\n");
-			break;
-		}
-	}
-	if (i == mem_entries) {
-		printk_err("No matching ram area found for range:\n");
-		printk_err("  [0x%016lx, 0x%016lx)\n", start, end);
-		printk_err("Ram areas\n");
-		for(i = 0; i < mem_entries; i++) {
-			uint64_t mstart, mend;
-			uint32_t mtype;
-			mtype = mem->map[i].type;
-			mstart = unpack_lb64(mem->map[i].start);
-			mend = mstart + unpack_lb64(mem->map[i].size);
-			printk_err("  [0x%016lx, 0x%016lx) %s\n",
-				(unsigned long)mstart, 
-				(unsigned long)mend, 
-				(mtype == LB_MEM_RAM)?"RAM":"Reserved");
-			
-		}
-		return 0;
-	}
-	return 1;
-}
-
-static void relocate_segment(unsigned long buffer, struct segment *seg)
-{
-	/* Modify all segments that want to load onto coreboot
-	 * to load onto the bounce buffer instead.
-	 */
-	unsigned long lb_start = (unsigned long)&_ram_seg;
-	unsigned long lb_end = (unsigned long)&_eram_seg;
-	unsigned long start, middle, end;
-
-	printk_spew("lb: [0x%016lx, 0x%016lx)\n", 
-		lb_start, lb_end);
-
-	start = seg->s_addr;
-	middle = start + seg->s_filesz;
-	end = start + seg->s_memsz;
-	/* I don't conflict with coreboot so get out of here */
-	if ((end <= lb_start) || (start >= lb_end))
-		return;
-
-	printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-		start, middle, end);
-
-	/* Slice off a piece at the beginning
-	 * that doesn't conflict with coreboot.
-	 */
-	if (start < lb_start) {
-		struct segment *new;
-		unsigned long len = lb_start - start;
-		new = malloc(sizeof(*new));
-		*new = *seg;
-		new->s_memsz = len;
-		seg->s_memsz -= len;
-		seg->s_addr += len;
-		seg->s_offset += len;
-		if (seg->s_filesz > len) {
-			new->s_filesz = len;
-			seg->s_filesz -= len;
-		} else {
-			seg->s_filesz = 0;
-		}
-
-		/* Order by stream offset */
-		new->next = seg;
-		new->prev = seg->prev;
-		seg->prev->next = new;
-		seg->prev = new;
-		/* Order by original program header order */
-		new->phdr_next = seg;
-		new->phdr_prev = seg->phdr_prev;
-		seg->phdr_prev->phdr_next = new;
-		seg->phdr_prev = new;
-
-		/* compute the new value of start */
-		start = seg->s_addr;
-		
-		printk_spew("   early: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-			new->s_addr, 
-			new->s_addr + new->s_filesz,
-			new->s_addr + new->s_memsz);
-	}
-	
-	/* Slice off a piece at the end 
-	 * that doesn't conflict with coreboot 
-	 */
-	if (end > lb_end) {
-		unsigned long len = lb_end - start;
-		struct segment *new;
-		new = malloc(sizeof(*new));
-		*new = *seg;
-		seg->s_memsz = len;
-		new->s_memsz -= len;
-		new->s_addr += len;
-		new->s_offset += len;
-		if (seg->s_filesz > len) {
-			seg->s_filesz = len;
-			new->s_filesz -= len;
-		} else {
-			new->s_filesz = 0;
-		}
-		/* Order by stream offset */
-		new->next = seg->next;
-		new->prev = seg;
-		seg->next->prev = new;
-		seg->next = new;
-		/* Order by original program header order */
-		new->phdr_next = seg->phdr_next;
-		new->phdr_prev = seg;
-		seg->phdr_next->phdr_prev = new;
-		seg->phdr_next = new;
-
-		printk_spew("   late: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-			new->s_addr, 
-			new->s_addr + new->s_filesz,
-			new->s_addr + new->s_memsz);
-		
-	}
-	/* Now retarget this segment onto the bounce buffer */
-	seg->s_addr = buffer + (seg->s_addr - lb_start);
-
-	printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", 
-		seg->s_addr, 
-		seg->s_addr + seg->s_filesz, 
-		seg->s_addr + seg->s_memsz);
-}
-
-
-static int build_elf_segment_list(
-	struct segment *head, 
-	unsigned long bounce_buffer, struct lb_memory *mem,
-	Elf_phdr *phdr, int headers)
-{
-	struct segment *ptr;
-	int i;
-	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
-	head->next = head->prev = head;
-	for(i = 0; i < headers; i++) {
-		struct segment *new;
-		/* Ignore data that I don't need to handle */
-		if (phdr[i].p_type != PT_LOAD) {
-			printk_debug("Dropping non PT_LOAD segment\n");
-			continue;
-		}
-		if (phdr[i].p_memsz == 0) {
-			printk_debug("Dropping empty segment\n");
-			continue;
-		}
-		new = malloc(sizeof(*new));
-		new->s_addr = phdr[i].p_paddr;
-		new->s_memsz = phdr[i].p_memsz;
-		new->s_offset = phdr[i].p_offset;
-		new->s_filesz = phdr[i].p_filesz;
-		printk_debug("New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
-			new->s_addr, new->s_memsz, new->s_offset, new->s_filesz);
-		/* Clean up the values */
-		if (new->s_filesz > new->s_memsz)  {
-			new->s_filesz = new->s_memsz;
-		}
-		printk_debug("(cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n",
-			new->s_addr, new->s_memsz, new->s_offset, new->s_filesz);
-		for(ptr = head->next; ptr != head; ptr = ptr->next) {
-			if (new->s_offset < ptr->s_offset)
-				break;
-		}
-		/* Order by stream offset */
-		new->next = ptr;
-		new->prev = ptr->prev;
-		ptr->prev->next = new;
-		ptr->prev = new;
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
-
-		/* Verify the memory addresses in the segment are valid */
-		if (!valid_area(mem, bounce_buffer, new->s_addr, new->s_memsz)) 
-			goto out;
-
-		/* Modify the segment to load onto the bounce_buffer if necessary.
-		 */
-		relocate_segment(bounce_buffer, new);
-	}
-	return 1;
- out:
-	return 0;
-}
-
-static int load_elf_segments(
-	struct segment *head, unsigned char *header, unsigned long header_size)
-{
-	unsigned long offset;
-	struct segment *ptr;
-	
-	offset = 0;
-	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		unsigned long start_offset;
-		unsigned long skip_bytes, read_bytes;
-		unsigned char *dest, *middle, *end;
-		byte_offset_t result;
-		printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n",
-			ptr->s_addr, ptr->s_memsz, ptr->s_filesz);
-		
-		/* Compute the boundaries of the segment */
-		dest = (unsigned char *)(ptr->s_addr);
-		end = dest + ptr->s_memsz;
-		middle = dest + ptr->s_filesz;
-		start_offset = ptr->s_offset;
-		/* Ignore s_offset if I have a pure bss segment */
-		if (ptr->s_filesz == 0) {
-			start_offset = offset;
-		}
-		
-		printk_spew("[ 0x%016lx, %016lx, 0x%016lx) <- %016lx\n",
-			(unsigned long)dest,
-			(unsigned long)middle,
-			(unsigned long)end,
-			(unsigned long)start_offset);
-		
-		/* Skip intial buffer unused bytes */
-		if (offset < header_size) {
-			if (start_offset < header_size) {
-				offset = start_offset;
-			} else {
-				offset = header_size;
-			}
-		}
-		
-		/* Skip the unused bytes */
-		skip_bytes = start_offset - offset;
-		if (skip_bytes && 
-			((result = stream_skip(skip_bytes)) != skip_bytes)) {
-			printk_err("ERROR: Skip of %ld bytes skipped %ld bytes\n",
-				skip_bytes, result);
-			goto out;
-		}
-		offset = start_offset;
-		
-		/* Copy data from the initial buffer */
-		if (offset < header_size) {
-			size_t len;
-			if ((ptr->s_filesz + start_offset) > header_size) {
-				len = header_size - start_offset;
-			}
-			else {
-				len = ptr->s_filesz;
-			}
-			memcpy(dest, &header[start_offset], len);
-			dest += len;
-		}
-		
-		/* Read the segment into memory */
-		read_bytes = middle - dest;
-		if (read_bytes && 
-			((result = stream_read(dest, read_bytes)) != read_bytes)) {
-			printk_err("ERROR: Read of %ld bytes read %ld bytes...\n",
-				read_bytes, result);
-			goto out;
-		}
-		offset += ptr->s_filesz;
-		
-		/* Zero the extra bytes between middle & end */
-		if (middle < end) {
-			printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n",
-				(unsigned long)middle, (unsigned long)(end - middle));
-			
-			/* Zero the extra bytes */
-			memset(middle, 0, end - middle);
-		}
-	}
-	return 1;
- out:
-	return 0;
-}
-
-static int verify_loaded_image(
-	struct verify_callback *vcb,
-	Elf_ehdr *ehdr, Elf_phdr *phdr,
-	struct segment *head
-	)
-{
-	struct segment *ptr;
-	int ok;
-	ok = 1;
-	for(; ok && vcb ; vcb = vcb->next) {
-		/* Find where the note is loaded */
-		/* The whole note must be loaded intact
-		 * so an address of 0 for the descriptor is impossible
-		 */
-		vcb->desc_addr = 0; 
-		for(ptr = head->next; ptr != head; ptr = ptr->next) {
-			unsigned long desc_addr;
-			desc_addr = ptr->s_addr + vcb->desc_offset - ptr->s_offset;
-			if ((desc_addr >= ptr->s_addr) &&
-				(desc_addr < (ptr->s_addr + ptr->s_filesz))) {
-				vcb->desc_addr = desc_addr;
-			}
-		}
-		ok = vcb->callback(vcb, ehdr, phdr, head);
-	}
-	return ok;
-}
-
-int elfload(struct lb_memory *mem,
-	unsigned char *header, unsigned long header_size)
-{
-	Elf_ehdr *ehdr;
-	Elf_phdr *phdr;
-	void *entry;
-	struct segment head;
-	struct verify_callback *cb_chain;
-	unsigned long bounce_buffer;
-
-	/* Find a bounce buffer so I can load to coreboot's current location */
-	bounce_buffer = get_bounce_buffer(mem);
-	if (!bounce_buffer) {
-		printk_err("Could not find a bounce buffer...\n");
-		goto out;
-	}
-
-	ehdr = (Elf_ehdr *)header;
-	entry = (void *)(ehdr->e_entry);
-	phdr = (Elf_phdr *)(&header[ehdr->e_phoff]);
-
-	/* Digest elf note information... */
-	cb_chain = 0;
-	if ((phdr[0].p_type == PT_NOTE) && 
-		((phdr[0].p_offset + phdr[0].p_filesz) < header_size)) {
-		cb_chain = process_elf_notes(header,
-			phdr[0].p_offset, phdr[0].p_filesz);
-	}
-
-	/* Preprocess the elf segments */
-	if (!build_elf_segment_list(&head, 
-		bounce_buffer, mem, phdr, ehdr->e_phnum))
-		goto out;
-
-	/* Load the segments */
-	if (!load_elf_segments(&head, header, header_size))
-		goto out;
-
-	printk_spew("Loaded segments\n");
-	/* Verify the loaded image */
-	if (!verify_loaded_image(cb_chain, ehdr, phdr, &head)) 
-		goto out;
-
-	printk_spew("verified segments\n");
-	/* Shutdown the stream device */
-	stream_fini();
-	
-	printk_spew("closed down stream\n");
-	/* Reset to booting from this image as late as possible */
-	boot_successful();
-
-	printk_debug("Jumping to boot code at %p\n", entry);
-	post_code(0xfe);
-
-	/* Jump to kernel */
-	jmp_to_elf_entry(entry, bounce_buffer, bounce_size);
-	return 1;
-
- out:
-	return 0;
-}
-
-int elfboot(struct lb_memory *mem)
-{
-	Elf_ehdr *ehdr;
-	static unsigned char header[ELF_HEAD_SIZE];
-	int header_offset;
-	int i, result;
-
-	result = 0;
-	printk_debug("\nelfboot: Attempting to load payload.\n");
-	post_code(0xf8);
-
-	if (stream_init() < 0) {
-		printk_err("Could not initialize driver...\n");
-		goto out;
-	}
-
-	/* Read in the initial ELF_HEAD_SIZE bytes */
-	if (stream_read(header, ELF_HEAD_SIZE) != ELF_HEAD_SIZE) {
-		printk_err("Read failed...\n");
-		goto out;
-	}
-	/* Scan for an elf header */
-	header_offset = -1;
-	for(i = 0; i < ELF_HEAD_SIZE - (sizeof(Elf_ehdr) + sizeof(Elf_phdr)); i+=16) {
-		ehdr = (Elf_ehdr *)(&header[i]);
-		if (memcmp(ehdr->e_ident, ELFMAG, 4) != 0) {
-			printk_debug("No header at %d\n", i);
-			continue;
-		}
-		printk_debug("Found ELF candidate at offset %d\n", i);
-		/* Sanity check the elf header */
-		if ((ehdr->e_type == ET_EXEC) &&
-			elf_check_arch(ehdr) &&
-			(ehdr->e_ident[EI_VERSION] == EV_CURRENT) &&
-			(ehdr->e_version == EV_CURRENT) &&
-			(ehdr->e_ehsize == sizeof(Elf_ehdr)) &&
-			(ehdr->e_phentsize = sizeof(Elf_phdr)) &&
-			(ehdr->e_phoff < (ELF_HEAD_SIZE - i)) &&
-			((ehdr->e_phoff + (ehdr->e_phentsize * ehdr->e_phnum)) <= 
-				(ELF_HEAD_SIZE - i))) {
-			header_offset = i;
-			break;
-		}
-		ehdr = 0;
-	}
-	printk_debug("header_offset is %d\n", header_offset);
-	if (header_offset == -1) {
-		goto out;
-	}
-
-	printk_debug("Try to load at offset 0x%x\n", header_offset);
-	result = elfload(mem, 
-		header + header_offset , ELF_HEAD_SIZE - header_offset);
- out:
-	if (!result) {
-		/* Shutdown the stream device */
-		stream_fini();
-
-		printk_err("Can not load ELF Image.\n");
-
-		post_code(0xff);
-	}
-	return 0;
-
-}

Deleted: trunk/coreboot-v2/src/boot/filo.c
===================================================================
--- trunk/coreboot-v2/src/boot/filo.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/boot/filo.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,194 +0,0 @@
-/*
- * Copyright (C) 2003 by SONE Takeshi <ts1 at tsn.or.jp> and others.
- * This program is licensed under the terms of GNU General Public License.
- *
- * Modified for coreboot by Greg Watson <gwatson at lanl.gov>
- */
-
-#include <console/console.h>
-#include <delay.h>
-#include <string.h>
-#include <boot/tables.h>
-#include <boot/elf.h>
-
-#define ENTER '\r'
-#define ESCAPE '\x1b'
-
-#ifndef CONFIG_AUTOBOOT_CMDLINE
-#define autoboot(mem)
-#endif
-
-#if !CONFIG_AUTOBOOT_DELAY
-#define autoboot_delay() 0 /* success */
-#endif
-
-#define havechar() console_tst_byte()
-#define putchar(c) console_tx_byte(c)
-#define getchar(c) console_rx_byte(c)
-
-extern char *boot_file;
-
-int getline(char *buf, int max)
-{
-    int cur, ch, nonspace_seen;
-
-    cur = 0;
-    while (buf[cur]) {
-	putchar(buf[cur]);
-	cur++;
-    }
-    for (;;) {
-	ch = getchar();
-	switch (ch) {
-	/* end of line */
-	case '\r':
-	case '\n':
-	    putchar('\n');
-	    goto out;
-	/* backspace */
-	case '\b':
-	case '\x7f':
-	    if (cur > 0) {
-		cur--;
-		putchar('\b');
-		putchar(' ');
-		putchar('\b');
-	    }
-	    break;
-	/* word erase */
-	case 'W' & 0x1f: /* ^W */
-	    nonspace_seen = 0;
-	    while (cur) {
-		if (buf[cur-1] != ' ')
-		    nonspace_seen = 1;
-		putchar('\b');
-		putchar(' ');
-		putchar('\b');
-		cur--;
-		if (nonspace_seen && cur < max-1 && cur > 0 && buf[cur-1]==' ')
-		    break;
-	    }
-	    break;
-	/* line erase */
-	case 'U' & 0x1f: /* ^U */
-	    while (cur) {
-		putchar('\b');
-		putchar(' ');
-		putchar('\b');
-		cur--;
-	    }
-	    cur = 0;
-	    break;
-	default:
-	    if (ch < 0x20)
-		break; /* ignore control char */
-	    if (ch >= 0x7f)
-		break;
-	    if (cur + 1 < max) {
-		putchar(ch); /* echo back */
-		buf[cur] = ch;
-		cur++;
-	    }
-	}
-    }
-out:
-    if (cur >= max)
-	cur = max - 1;
-    buf[cur] = '\0';
-    return cur;
-}
-
-static void boot(struct lb_memory *mem, const char *line)
-{
-    char *param;
-
-    /* Split filename and parameter */
-    boot_file = strdup(line);
-    param = strchr(boot_file, ' ');
-    if (param) {
-	*param = '\0';
-	param++;
-    }
-
-    if (!elfboot(mem))
-	printk_info("Unsupported image format\n");
-    free(boot_file);
-}
-
-#ifdef CONFIG_AUTOBOOT_CMDLINE
-#if CONFIG_AUTOBOOT_DELAY
-static inline int autoboot_delay(void)
-{
-    unsigned int timeout;
-    int sec, tmp;
-    char key;
-    
-    key = 0;
-
-    printk_info("Press <Enter> for default boot, or <Esc> for boot prompt... ");
-    for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) {
-	printk_info("%d", sec);
-	timeout = 10;
-	while (timeout-- > 0) {
-	    if (havechar()) {
-		key = getchar();
-		if (key==ENTER || key==ESCAPE)
-		    break;
-	    }
-	    mdelay(100);
-	}
-	for (tmp = sec; tmp; tmp /= 10)
-	    printk_info("\b \b");
-    }
-    if (key == 0) {
-	printk_info("timed out\n");
-	return 0; /* success */
-    } else {
-	putchar('\n');
-	if (key == ESCAPE)
-	    return -1; /* canceled */
-	else
-	    return 0; /* default accepted */
-    }
-}
-#endif /* CONFIG_AUTOBOOT_DELAY */
-
-static void autoboot(struct lb_memory *mem)
-{
-    /* If Escape key is pressed already, skip autoboot */
-    if (havechar() && getchar()==ESCAPE)
-	return;
-
-    if (autoboot_delay()==0) {
-	printk_info("boot: %s\n", CONFIG_AUTOBOOT_CMDLINE);
-	boot(mem, CONFIG_AUTOBOOT_CMDLINE);
-    }
-}
-#endif /* CONFIG_AUTOBOOT_CMDLINE */
-
-/* The main routine */
-int filo(struct lb_memory *mem)
-{
-    char line[256];
-
-    printk_info("FILO version 0.4.1\n");
-
-    /* Try default image */
-    autoboot(mem);
-
-    /* The above didn't work, ask user */
-    while (havechar())
-	getchar();
-#ifdef CONFIG_AUTOBOOT_CMDLINE
-    strncpy(line, CONFIG_AUTOBOOT_CMDLINE, sizeof(line)-1);
-    line[sizeof(line)-1] = '\0';
-#else
-    line[0] = '\0';
-#endif
-    for (;;) {
-	printk_info("boot: ");
-	getline(line, sizeof line);
-	if (line[0])
-	    boot(mem, line);
-    }
-}

Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -96,22 +96,11 @@
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
-#if CONFIG_CBFS == 1
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_load_payload(lb_mem, "fallback/payload");
-# else
-	cbfs_load_payload(lb_mem, "normal/payload");
-# endif
 #else
-
-#if CONFIG_FS_PAYLOAD == 1
-#warning "CONFIG_FS_PAYLOAD is deprecated."
-	filo(lb_mem);
-#else
-#warning "elfboot will soon be deprecated."
-	elfboot(lb_mem);
+	cbfs_load_payload(lb_mem, "normal/payload");
 #endif
-#endif
 	printk(BIOS_ERR, "Boot failed.\n");
 }
 

Modified: trunk/coreboot-v2/src/config/Config.lb
===================================================================
--- trunk/coreboot-v2/src/config/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/config/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -215,7 +215,6 @@
 # for now, this is just 'lib', but it may be more later. 
 dir /lib
 dir /console
-dir /stream
 dir /devices
 dir /pc80
 dir /boot

Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -641,11 +641,6 @@
 	export always
 	comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
 end
-define CONFIG_IDE_PAYLOAD
-	default 0
-	export always
-	comment "Boot from IDE device"
-end
 define CONFIG_ROM_PAYLOAD
 	default 0
 	export always
@@ -672,47 +667,6 @@
 	export always
 	comment "boot image is already compressed" 
 end
-define CONFIG_SERIAL_PAYLOAD
-	default 0
-	export always
-	comment "Download boot image from serial port"
-end
-define CONFIG_FS_PAYLOAD
-	default 0
-	export always
-	comment "Boot from a filesystem"
-end
-define CONFIG_FS_EXT2
-	default 0
-	export always
-	comment "Enable ext2 filesystem support"
-end
-define CONFIG_FS_ISO9660
-	default 0
-	export always
-	comment "Enable ISO9660 filesystem support"
-end
-define CONFIG_FS_FAT
-	default 0
-	export always
-	comment "Enable FAT filesystem support"
-end
-define CONFIG_CBFS
-	default 1
-	export always
-	comment "The new CBFS file system"
-end
-define CONFIG_AUTOBOOT_DELAY
-	default 2
-	export always
-	comment "Delay (in seconds) before autobooting"
-end
-define CONFIG_AUTOBOOT_CMDLINE
-	default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
-	export always
-	format "\"%s\""
-	comment "Default command line when autobooting"
-end
 
 define CONFIG_USE_WATCHDOG_ON_BOOT
 	default 0

Modified: trunk/coreboot-v2/src/config/failovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/failovercalculation.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/config/failovercalculation.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -10,13 +10,8 @@
 	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
 	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
     else
-	if CONFIG_CBFS
-		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
-		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
-	else
-		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
-		default CONFIG_ROM_SECTION_OFFSET = 0
-	end
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE )
     end
 end
 

Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -6,13 +6,8 @@
 	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
 	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
 else
-	if CONFIG_CBFS
-		default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
-		default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
-	else
-		default CONFIG_ROM_SECTION_SIZE   = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE )
-		default CONFIG_ROM_SECTION_OFFSET = 0
-	end
+	default CONFIG_ROM_SECTION_SIZE   = CONFIG_FALLBACK_SIZE
+	default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE )
 end
 
 ##

Modified: trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -3,16 +3,15 @@
    2006/05/02 - stepan: move nrv2b to an extra file.
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(const char*, unsigned ebp);
 
 static void copy_and_run(void)
 {
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", 0);
-# else
+#else
       	cbfs_and_run_core("normal/coreboot_ram", 0);
-# endif
+#endif
 }
 
 #if CONFIG_AP_CODE_IN_CAR == 1
@@ -26,38 +25,3 @@
 # endif
 }
 #endif
-
-#else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(void)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	copy_and_run_core(src, dst, ilen, 0);
-}
-
-#if CONFIG_AP_CODE_IN_CAR == 1
-
-extern u8 _liseg_apc, _iseg_apc, _eiseg_apc;
-
-static void copy_and_run_ap_code_in_car(unsigned ret_addr)
-{
-        uint8_t *src, *dst;
-        unsigned long ilen;
-
-	src = &_liseg_apc;
-	dst = &_iseg_apc;
-	ilen = &_eiseg_apc - dst;
-
-	copy_and_run_core(src, dst, ilen, ret_addr);
-}
-#endif
-#endif

Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc	2009-10-03 16:24:58 UTC (rev 4712)
@@ -222,19 +222,8 @@
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl	%esi
-#if CONFIG_CBFS == 1
 	pushl $str_coreboot_ram_name
 	call cbfs_and_run_core
-#else
-	movl	$_liseg, %esi
-	movl	$_iseg,  %edi
-	movl	$_eiseg, %ecx
-	subl	%edi, %ecx
-	pushl	%ecx
-	pushl	%edi
-	pushl	%esi
-	call copy_and_run_core
-#endif
 
 .Lhlt:
 	intel_chip_post_macro(0xee)	/* post fail ee */
@@ -295,10 +284,8 @@
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-#if CONFIG_CBFS == 1
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 str_coreboot_ram_name:	.string "fallback/coreboot_ram"
-# else
+#else
 str_coreboot_ram_name:	.string "normal/coreboot_ram"
-# endif
 #endif

Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -2,7 +2,6 @@
    (Written by Patrick Georgi <patrick.georgi at coresystems.de> for coresystems GmbH
 */
 
-#if CONFIG_CBFS == 1
 void cbfs_and_run_core(char*, unsigned ebp);
 
 static void copy_and_run(unsigned cpu_reset)
@@ -10,32 +9,9 @@
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;
 
-# if CONFIG_USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 	cbfs_and_run_core("fallback/coreboot_ram", cpu_reset);
-# else
-	cbfs_and_run_core("normal/coreboot_ram", cpu_reset);
-# endif
-}
-
 #else
-void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
-
-extern u8 _liseg, _iseg, _eiseg;
-
-static void copy_and_run(unsigned cpu_reset)
-{
-	uint8_t *src, *dst; 
-        unsigned long ilen;
-
-
-	src = &_liseg;
-	dst = &_iseg;
-	ilen = &_eiseg - dst;
-
-	if (cpu_reset == 1) cpu_reset = -1;
-	else cpu_reset = 0;
-
-	copy_and_run_core(src, dst, ilen, cpu_reset);
-}
+	cbfs_and_run_core("normal/coreboot_ram", cpu_reset);
 #endif
-
+}

Modified: trunk/coreboot-v2/src/devices/pci_rom.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_rom.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/devices/pci_rom.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -35,22 +35,17 @@
 	struct rom_header *rom_header;
 	struct pci_data *rom_data;
 
-	if (CONFIG_CBFS) {
-		void *v;
-		/* if it's in FLASH, then it's as if dev->on_mainboard was true */
-		v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
-		printk_debug("In cbfs, rom address for %s = %p\n", 
-				dev_path(dev), v);
-		if (v) {
-			dev->rom_address = (u32)v;
-			dev->on_mainboard = 1;
-		}
-	} 
+	void *v;
+	/* if it's in FLASH, then it's as if dev->on_mainboard was true */
+	v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
+	printk_debug("In cbfs, rom address for %s = %p\n", 
+			dev_path(dev), v);
+	if (v) {
+		dev->rom_address = (u32)v;
+		dev->on_mainboard = 1;
+	}
 
 	if (dev->on_mainboard) {
-		/* this is here as a legacy path. We hope it goes away soon. Users should not have to 
-		 * compute the ROM address at build time!
-		 */
                 // in case some device PCI_ROM_ADDRESS can not be set or readonly 
 		rom_address = dev->rom_address;
 		printk_debug("On mainboard, rom address for %s = %lx\n", 

Modified: trunk/coreboot-v2/src/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/lib/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/lib/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -27,11 +27,5 @@
 initobject memcpy.o
 initobject memcmp.o
 
-if CONFIG_CBFS
-	object cbfs.o
-	object lzma.o
-end
-
-if CONFIG_COMPRESSED_PAYLOAD_LZMA
-	object lzma.o
-end
+object cbfs.o
+object lzma.o

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -98,9 +97,4 @@
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -301,9 +300,4 @@
 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -299,9 +298,4 @@
 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,10 +158,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -325,9 +324,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -18,7 +18,6 @@
 #
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -362,9 +361,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -242,9 +241,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_PIRQ_TABLE
-uses CONFIG_CBFS
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
 uses CONFIG_HAVE_HARD_RESET
@@ -161,10 +160,4 @@
 # default CONFIG_PCI_ROM_RUN=1
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -167,9 +166,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -18,7 +18,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -167,9 +166,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -18,7 +18,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -176,9 +175,4 @@
 
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
 default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -158,9 +157,4 @@
 
 default CONFIG_UDELAY_TSC=1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -98,9 +97,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,5 +102,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,9 +103,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,9 +102,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,10 +102,4 @@
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -260,9 +259,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -113,11 +112,4 @@
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -121,11 +120,4 @@
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -35,9 +35,6 @@
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
 static void enable_dev(struct device *dev) {
-#if !CONFIG_CBFS
-	extern unsigned char *rom_start, *rom_end;
-#endif
 	volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
@@ -135,15 +132,6 @@
 	 */
 	/* follow fuctory here */
 	mmcr->dmacontrol.extchanmapa = 0x3210;
-
-#if !CONFIG_CBFS
-	/* hack for IDIOTIC need to fix rom_start */
-	printk_err("Patching rom_start due to sc520 limits\n");
-	rom_start = 0x2000000 + 0x40000;
-	rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1;
-#endif
-
-	
 }
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -180,10 +179,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -164,10 +163,4 @@
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -48,13 +48,11 @@
 
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CBFS
 
 
 default CONFIG_CONSOLE_SERIAL8250=1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-default CONFIG_CBFS=1
 
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 default CONFIG_ROM_SIZE  = 256*1024

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -22,7 +22,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -359,10 +358,5 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -84,7 +84,6 @@
 uses CONFIG_HW_MEM_HOLE_SIZEK
 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_CBFS
 
 uses CONFIG_HT_CHAIN_UNITID_BASE
 uses CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -327,9 +326,5 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-##
-## CBFS
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -221,9 +220,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -227,9 +226,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -145,10 +144,4 @@
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -172,10 +171,4 @@
 
 default CONFIG_VIDEO_MB = 0
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -106,10 +105,4 @@
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -70,7 +70,6 @@
 uses CONFIG_PCIE_CONFIGSPACE_HOLE
 uses CONFIG_MMCONF_SUPPORT
 uses CONFIG_MMCONF_BASE_ADDRESS
-uses CONFIG_CBFS
 #
 uses CONFIG_MAINBOARD
 uses CONFIG_MAINBOARD_PART_NUMBER
@@ -322,10 +321,5 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -242,9 +241,4 @@
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -18,7 +18,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -225,9 +224,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -18,7 +18,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -236,10 +235,4 @@
 
 ### End Options.lb
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_HAVE_PIRQ_TABLE
@@ -240,9 +239,4 @@
 # default CONFIG_CPU_OPT="-g"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -326,9 +325,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -227,9 +226,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -104,10 +103,4 @@
 ##
 default CONFIG_MAX_PCI_BUSES = 3
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -71,7 +71,6 @@
 uses CONFIG_MMCONF_SUPPORT
 uses CONFIG_MMCONF_BASE_ADDRESS
 uses CONFIG_GFXUMA
-uses CONFIG_CBFS
 
 #
 uses CONFIG_MAINBOARD
@@ -327,10 +326,5 @@
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
-#
-# CBFS
-# 
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -159,10 +158,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -21,7 +21,6 @@
 ## Based on Options.lb from AMD's DB800 mainboard.
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -29,11 +28,6 @@
 uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IDE
-uses CONFIG_FS_PAYLOAD
-uses CONFIG_FS_EXT2
-uses CONFIG_AUTOBOOT_DELAY
-uses CONFIG_AUTOBOOT_CMDLINE
 uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_MAINBOARD
 uses CONFIG_MAINBOARD_VENDOR
@@ -211,9 +205,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -21,7 +21,6 @@
 ## Based on Options.lb from AMD's DB800 mainboard.
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -29,11 +28,6 @@
 uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IDE
-uses CONFIG_FS_PAYLOAD
-uses CONFIG_FS_EXT2
-uses CONFIG_AUTOBOOT_DELAY
-uses CONFIG_AUTOBOOT_CMDLINE
 uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_MAINBOARD
 uses CONFIG_MAINBOARD_VENDOR
@@ -211,9 +205,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
@@ -78,7 +77,6 @@
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_HAVE_FALLBACK_BOOT = 1
 default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CBFS=1
 
 # RAM layout
 default CONFIG_RAMBASE = 0x00004000

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,9 +96,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,7 +96,6 @@
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS = 1
 default CONFIG_HAVE_HIGH_TABLES = 1
 default CONFIG_VIDEO_MB = 1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -21,7 +21,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -320,9 +319,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -186,9 +185,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -23,7 +23,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -327,9 +326,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -23,7 +23,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -307,9 +306,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -96,9 +95,4 @@
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -243,9 +242,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -349,9 +348,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -160,10 +159,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -160,10 +159,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -198,10 +197,4 @@
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
@@ -96,9 +95,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_VENDOR = "RCA"
 default CONFIG_MAINBOARD_PART_NUMBER = "RM4100"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -96,5 +95,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -276,9 +275,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -348,11 +347,5 @@
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ## 
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -360,12 +359,5 @@
 default CONFIG_USE_FAILOVER_IMAGE=0
 default CONFIG_USE_FALLBACK_IMAGE=0
 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-
 ### End Options.lb
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,10 +227,4 @@
 
 
 ### End Options.lb
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -228,9 +227,4 @@
 
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME

Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -135,10 +134,4 @@
 ##
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c	2009-10-03 16:24:58 UTC (rev 4712)
@@ -35,9 +35,6 @@
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
 static void enable_dev(struct device *dev) {
-#if !CONFIG_CBFS
-	extern unsigned char *rom_start, *rom_end;
-#endif
 	volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
@@ -141,15 +138,7 @@
 	mmcr->dmacontrol.extchanmapa = 0xf210;
 	mmcr->dmacontrol.extchanmapb = 0xffff;
 
-#if !CONFIG_CBFS
-	/* hack for IDIOTIC need to fix rom_start */
-	printk_err("Patching rom_start due to sc520 limits\n");
-	rom_start = 0x09400000 + 0xe0000;
-	rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1;
-#endif
-
 	printk_err("TS5300 EXIT %s\n", __func__);
-	
 }
 
 struct chip_operations mainboard_ops = {

Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,10 +102,4 @@
 default CONFIG_TTYS0_LCS = 0x3		# 8n1
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CC
-uses CONFIG_CBFS
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
@@ -96,9 +95,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAINBOARD_VENDOR = "THOMSON"
 default CONFIG_MAINBOARD_PART_NUMBER = "IP1000"
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -97,10 +96,4 @@
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_CONSOLE_VGA = 1
 default CONFIG_PCI_ROM_RUN = 1
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -256,9 +255,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -245,9 +244,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -261,9 +260,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -244,9 +243,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -271,9 +270,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -300,9 +299,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -288,9 +287,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -307,9 +306,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -351,9 +350,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
@@ -360,9 +359,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -253,9 +252,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -252,9 +251,4 @@
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CBFS
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_TTYS0_BAUD
@@ -139,12 +138,4 @@
 default CONFIG_CROSS_COMPILE=""
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
-
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -20,7 +20,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -103,11 +102,4 @@
 ## time when it can't find a device.
 ##
 default CONFIG_MAX_PCI_BUSES = 3
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -1,5 +1,4 @@
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -142,11 +141,4 @@
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 default  CONFIG_CONSOLE_SERIAL8250=1
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_HAVE_MP_TABLE
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
@@ -137,7 +136,6 @@
 default HOSTCC = "gcc"
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CBFS=1
 
 ##
 ## Set this to the max PCI bus number you would ever use for PCI config I/O.

Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses CONFIG_CBFS
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_HAVE_FAILOVER_BOOT
 uses CONFIG_USE_FAILOVER_IMAGE
@@ -120,11 +119,4 @@
 ## time when it can't find a device.
 ##
 default CONFIG_MAX_PCI_BUSES = 3
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -19,7 +19,6 @@
 ##
 
 uses CONFIG_SMP
-uses CONFIG_CBFS
 uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_USE_FALLBACK_IMAGE
@@ -111,11 +110,4 @@
 default CONFIG_TTYS0_LCS = 0x3
 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
 end

Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -55,7 +55,6 @@
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CBFS
 
 # compiler specifics
 uses CONFIG_CROSS_COMPILE
@@ -242,11 +241,5 @@
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-
-#
-# CBFS
-# 
-default CONFIG_CBFS=1
-
 end
 

Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -5,7 +5,6 @@
 ## (normal AND fallback images and payloads).
 option CONFIG_ROM_SIZE = 1024 * 1024
 
-option CONFIG_CBFS=1
 option HAVE_HIGH_TABLES=1
 option MAXIMUM_CONSOLE_LOGLEVEL=9
 option DEFAULT_CONSOLE_LOGLEVEL=9

Modified: trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -30,14 +30,6 @@
 option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
 option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
 
-## Load payload (e.g. Linux) from IDE.
-#option CONFIG_ROM_PAYLOAD = 0
-#option CONFIG_IDE = 1
-#option CONFIG_FS_PAYLOAD = 1
-#option CONFIG_FS_EXT2 = 1
-#option CONFIG_AUTOBOOT_DELAY = 0
-#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf"
-
 # Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
 # however it can be replaced with a 1 MB chip.
 option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)

Modified: trunk/coreboot-v2/targets/lippert/spacerunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/lippert/spacerunner-lx/Config.lb	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/targets/lippert/spacerunner-lx/Config.lb	2009-10-03 16:24:58 UTC (rev 4712)
@@ -31,14 +31,6 @@
 option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
 option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
 
-## Load payload (e.g. Linux) from IDE.
-#option CONFIG_ROM_PAYLOAD = 0
-#option CONFIG_IDE = 1
-#option CONFIG_FS_PAYLOAD = 1
-#option CONFIG_FS_EXT2 = 1
-#option CONFIG_AUTOBOOT_DELAY = 0
-#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf"
-
 # Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to
 # limitations of the IT8712F Super I/O, only the top 512 KB are directly mapped.
 option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)

Modified: trunk/coreboot-v2/util/abuild/abuild
===================================================================
--- trunk/coreboot-v2/util/abuild/abuild	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/util/abuild/abuild	2009-10-03 16:24:58 UTC (rev 4712)
@@ -176,20 +176,12 @@
 			cat <<EOF
 romimage "normal"
 	option CONFIG_USE_FALLBACK_IMAGE=0
-if CONFIG_CBFS
-else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-end
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
 	option CONFIG_USE_FALLBACK_IMAGE=1
-if CONFIG_CBFS
-else
-	option CONFIG_ROM_IMAGE_SIZE=0x17000
-end
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end

Modified: trunk/coreboot-v2/util/newconfig/config.g
===================================================================
--- trunk/coreboot-v2/util/newconfig/config.g	2009-10-03 15:34:08 UTC (rev 4711)
+++ trunk/coreboot-v2/util/newconfig/config.g	2009-10-03 16:24:58 UTC (rev 4712)
@@ -2247,7 +2247,7 @@
 	file = safe_open(makefilepath, 'w+')
 	writemakefileheader(file, makefilepath)
 
-	# Hack to get the necessary settings (CONFIG_CBFS):
+	# Hack to get the necessary settings (CONFIG_COMPRESSED_PAYLOAD_LZMA):
 	file.write("include %s/Makefile.settings\n\n" % romimages.keys()[0])
 
 	# main rule
@@ -2275,7 +2275,6 @@
 	file.write("base-clean:\n")
 	file.write("\trm -f romcc*\n\n")
 
-	file.write("ifeq \"$(CONFIG_CBFS)\" \"1\"\n\n")
 	file.write("CBFS_COMPRESS_FLAG:=\n")
 	file.write("CBFS_STAGE_COMPRESS_FLAG:=\n")
 	file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\nendif\n\n")
@@ -2309,20 +2308,7 @@
 			file.write("\tif [ -f %s/coreboot_apc ]; then ./cbfs/cbfstool %s add-stage %s/coreboot_apc %s/coreboot_apc $(CBFS_COMPRESS_FLAG); fi\n" % (j, i.name, j, j,))
 		file.write("\t./cbfs/cbfstool %s print\n" % i.name)
 		file.write("\n")
-	file.write("else\n\n")
 
-	for i in buildroms:
-		file.write("%s:" % i.name)
-		for j in i.roms:
-			file.write(" %s/coreboot.rom " % j)
-		file.write("\n")
-		file.write("\t cat ")
-		for j in i.roms:
-			file.write(" %s/coreboot.rom " % j)
-		file.write("> %s\n\n" %i.name)
-
-	file.write("endif\n\n")
-
 	file.write(".PHONY: all clean cbfstool")
 	for i in romimages.keys():
 		file.write(" %s-clean" % i)




From svn at coreboot.org  Sat Oct  3 18:27:48 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 18:27:48 +0200
Subject: [coreboot] [v2] r4713 - in trunk/coreboot-v2/src:
	mainboard/artecgroup/dbe61/realmode mainboard/via/epia-m
	northbridge/via/cn400 northbridge/via/cn700
	northbridge/via/cx700 northbridge/via/vx800
Message-ID: <mailman.3784.1355071627.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-03 18:27:48 +0200 (Sat, 03 Oct 2009)
New Revision: 4713

Modified:
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
   trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c
Log:
Tell vgabios code in a couple of boards/chipsets about CBFS

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>


Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -7,6 +7,7 @@
 #include <arch/io.h>
 #include <string.h>
 #include "chip.h"
+#include <cbfs.h>
 
 /* vgabios.c. Derived from: */
 
@@ -266,7 +267,7 @@
 {
 	
 	unsigned long busdevfn;
-	unsigned int rom = dev->rom_address;
+	unsigned int rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	unsigned char *buf;
 	unsigned int size = 64*1024;
 	int i;

Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -7,6 +7,7 @@
 //#include <printk.h>
 #include <string.h>
 #include "vgachip.h"
+#include <cbfs.h>
 
 /* vgabios.c. Derived from: */
 
@@ -356,7 +357,7 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xfffc0000;
+	rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
 	printk_debug("rom base, size: %x\n", rom);
 

Modified: trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -7,6 +7,7 @@
 //#include <printk.h>
 #include <string.h>
 #include "vgachip.h"
+#include <cbfs.h>
 
 /* vgabios.c. Derived from: */
 
@@ -356,7 +357,7 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xfff80000;
+        rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
 	printk_debug("VGA BIOS ROM base address: %x\n", rom);
 

Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -7,6 +7,7 @@
 //#include <printk.h>
 #include <string.h>
 #include "vgachip.h"
+#include <cbfs.h>
 
 /* vgabios.c. Derived from: */
 
@@ -356,7 +357,7 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xfff80000;
+	rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
 	printk_debug("rom base, size: %x\n", rom);
 

Modified: trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -28,6 +28,7 @@
 #undef __KERNEL__
 #include <arch/io.h>
 #include <string.h>
+#include <cbfs.h>
 
 void write_protect_vgabios(void);
 
@@ -323,7 +324,7 @@
 	 * of core LXB stuff */
 
 #warning ROM address hardcoded to 512K
-	rom = 0xfff80000;
+	rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); 
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
 	printk_debug("rom base, size: %x\n", rom);
 

Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c	2009-10-03 16:24:58 UTC (rev 4712)
+++ trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c	2009-10-03 16:27:48 UTC (rev 4713)
@@ -6,6 +6,7 @@
 #include <arch/io.h>
 #include <string.h>
 #include "vgachip.h"
+#include <cbfs.h>
 
 /* vgabios.c. Derived from: */
 
@@ -319,7 +320,7 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xffffffff - CONFIG_ROM_SIZE + 1;
+        rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
 	printk_debug("rom base: %x\n", rom);
 	buf = (unsigned char *)rom;




From peter at stuge.se  Sat Oct  3 18:34:17 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 18:34:17 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC5D02F.4040305@gmx.net>
References: <C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>
	<4AC3D6CD.7000403@gmx.net>
	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
	<20091001235825.GA29687@morn.localdomain>
	<4AC5CDCB.7080901@georgi-clan.de> <4AC5D02F.4040305@gmx.net>
Message-ID: <20091003163417.23369.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> IMHO access to CMOS before CAR is unnecessarily painful

Why?


//Peter



From peter at stuge.se  Sat Oct  3 18:40:27 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 18:40:27 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <4AC45990.4090409@gmx.net>
References: <1254343315.9254.20.camel@tetris>
	<46F32041A2CB4C16A76C44EF06B9052E@chimp>
	<4AC3E0E5.6090005@coresystems.de>
	<20090930232308.GA1720@morn.localdomain>
	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>
	<20090930235721.GA1833@morn.localdomain> <4AC45990.4090409@gmx.net>
Message-ID: <20091003164027.24419.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> Given that flashrom already has a generic image layout feature, I
> propose to have cbfstool spit out an image layout file which is
> then read by flashrom. This makes flashrom independent of CBFS and
> that's a good thing (think upgrade).

This is trivial to implement and might be a good first step, but it's
absolutely horrible from a usability perspective;

The user would need to keep track of and understand no less than two
tools, AND an intermediary layout file, in order to perform the
single task of partial firmware update.

I think it is quite neccessary for flashrom to understand CBFS (and
LAR, for v3 users).


//Peter



From peter at stuge.se  Sat Oct  3 18:44:43 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 18:44:43 +0200
Subject: [coreboot] [v2] r4707 - in
	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
In-Reply-To: <20091003160807.GI15511@greenwood>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
	<4AC772BE.4010403@coresystems.de>
	<20091003160807.GI15511@greenwood>
Message-ID: <20091003164443.25272.qmail@stuge.se>

Uwe Hermann wrote:
> > what about renaming it to pe1850?
> 
> Or poweredge_1850 if we're going to rename, so dirnames match the
> actual board name.

pe is a quite familiar abbreviation for Dell servers, I'd prefer
that. But Ron said it's not the same machine as on the picture -
we should find out what's going on there before changing the name..

And maybe the mainboard actually does have a name/code, PE is the
server product, I don't know if Dell usually name their boards
independently. I don't think so.


//Peter



From uwe at hermann-uwe.de  Sat Oct  3 19:15:19 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 3 Oct 2009 19:15:19 +0200
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
In-Reply-To: <4AC48F68.9000801@coresystems.de>
References: <20091001013040.GC15511@greenwood>
	<0245AF4550D4474DBCCE0C2083A3F306@chimp>
	<4AC48F68.9000801@coresystems.de>
Message-ID: <20091003171519.GJ15511@greenwood>

On Thu, Oct 01, 2009 at 01:15:52PM +0200, Stefan Reinauer wrote:
> Myles Watson wrote:
> >> High Tables Base is 1fff0000.
> >> Copying Interrupt Routing Table to 0x000f0000... done.
> >> Copying Interrupt Routing Table to 0x1fff0000... done.
> >> Wrote the mp table end at: 000f0410 - 000f0568
> >> Wrote the mp table end at: 1fff0410 - 2001040e
> >>     
> > Writing high tables above RAM!  Why is the high MP table so much larger than
> > the low one?
> >  
> >   
> 
> Right! Good spotting... something is reaaaally fishy here... Almost 64k
> mp table vs 300 bytes.
> 
> 
> >> Moving GDT to 0x20010800...ok
> >>     
> And, this alone is good for quite a crash.

I bisected this, the commit that broke the board was r4238, where high
tables support was added. Disabling it in
src/northbridge/cn700/Config.lb results in a successful boot into FILO.

Not sure what the correct fix for working high tables support for this
board/chipset is.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From rminnich at gmail.com  Sat Oct  3 19:20:13 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 3 Oct 2009 10:20:13 -0700
Subject: [coreboot] [v2] r4707 - in trunk/coreboot-v2:
	src/mainboard/dell/s1850 targets
In-Reply-To: <20091003164443.25272.qmail@stuge.se>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
	<4AC772BE.4010403@coresystems.de> <20091003160807.GI15511@greenwood>
	<20091003164443.25272.qmail@stuge.se>
Message-ID: <13426df10910031020s41164e7fs42e791af5ab3594d@mail.gmail.com>

actually it's all meaningless in a sense. We have ten 1850s that have
utterly different motherboards than the other 128. They can't even
properly netboot as the other 128 do. They all look the same outside.

Vendor names on the outside tell you nothing about the inside.

ron



From rminnich at gmail.com  Sat Oct  3 19:21:33 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 3 Oct 2009 10:21:33 -0700
Subject: [coreboot] SPD sanity check
In-Reply-To: <4AC77418.303@coresystems.de>
References: <13426df10910011704r6526dfe0sf9dd203b51db82fd@mail.gmail.com>
	<4AC555A3.1000700@settoplinux.org>
	<13426df10910012039l3a5ea1d5tf5d0d626ecef6495@mail.gmail.com>
	<522b905bb9329446dee9dc9b63ede57b@imap.1and1.com>
	<4AC5E9C7.90304@gmx.net>
	<13426df10910020953j38cc2f1eu1ccf7b50d589547e@mail.gmail.com>
	<57947bf80910021141t3e70e2f1u7f7d9ca1fd9193fe@mail.gmail.com>
	<13426df10910021309s46c1a16doc5e4275564059dd4@mail.gmail.com>
	<4AC77418.303@coresystems.de>
Message-ID: <13426df10910031021s76df6fbbo3dcce986585984a9@mail.gmail.com>

I'll poll the whole smbus monday. One problem is it doesn't seem to
work at all under factory bios -- Linux can't get to it. I expect the
BMC is, once again, getting in the way.

ron



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 19:27:06 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 19:27:06 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC776E2.4040908@coresystems.de>
References: <1254343315.9254.20.camel@tetris>	<20090930205626.25395.qmail@stuge.se>	<C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>	<20091001235825.GA29687@morn.localdomain>	<4AC5CDCB.7080901@georgi-clan.de>	<4AC5D02F.4040305@gmx.net>
	<4AC776E2.4040908@coresystems.de>
Message-ID: <4AC7896A.8050808@gmx.net>

On 03.10.2009 18:08, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> On 02.10.2009 11:54, Patrick Georgi wrote:
>>   
>>     
>>> We need to have access to CMOS before CAR or raminit, or anything
>>> interesting happens, really. And I'm not sure if our code supports
>>> this everywhere already.
>>>     
>>>       
>> IMHO access to CMOS before CAR is unnecessarily painful and I'd like to
>> keep that out of the targets which don't need it (VIA/AMD).  
>>     
>
>
> Then how are we going to update CAR code in case a new CPU revision
> needs an update while still keeping normal/fallback alive?
>   

This has never happened with any AMD or VIA CPU. And I highly doubt it
happened with Intel CPUs.
So why should we design for such an event?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Sat Oct  3 19:30:06 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 19:30:06 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
References: <4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
Message-ID: <20091003173006.595.qmail@stuge.se>

Jordan Justen wrote:
> Anyway, it sounds like a useful project might be to develop a UEFI
> coreboot payload based on the tianocore.org code.

I believe it might have been done already.

http://www.coreboot.org/File:Tianocoreboot.png


//Peter



From peter at stuge.se  Sat Oct  3 19:32:52 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 19:32:52 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003150803.GF17326@redhat.com>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011410u6afbb658hf99839fdb3e7bab1@mail.gmail.com>
	<4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
Message-ID: <20091003173252.1061.qmail@stuge.se>

Hi Gleb,

Gleb Natapov wrote:
> So for me real 440BX hardware support of coreboot is actually
> disadvantage. QEMU don't have real 440BX hardware and there is not
> point in having one. It is possible to implement 440BX-qemu support
> in coreboot of course if there are other advantages worth having.

coreboot supports both Intel 440BX and QEMU 440BX since many years.
The QEMU support in particular is used intensively by many coreboot
developers.


//Peter



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 19:35:18 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 19:35:18 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <20091003163417.23369.qmail@stuge.se>
References: <C9FA7E9B-518E-4875-AFFF-A77B14610B65@coresystems.de>	<4AC3D6CD.7000403@gmx.net>	<13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>	<20090930224333.14184.qmail@stuge.se>	<4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>	<20091001235825.GA29687@morn.localdomain>	<4AC5CDCB.7080901@georgi-clan.de>
	<4AC5D02F.4040305@gmx.net> <20091003163417.23369.qmail@stuge.se>
Message-ID: <4AC78B56.2040304@gmx.net>

On 03.10.2009 18:34, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> IMHO access to CMOS before CAR is unnecessarily painful
>>     
>
> Why?
>   

Because you either introduce a dependency on ROMCC or you need
additional assembler code. mmxstack/xmmstack+GCC is not an option here
because a microcode update may be required before using floating point
stuff.

If I had stood up a year ago and said "Let's introduce a ROMCC
dependency for all CAR boards", we would have seen a major flamewar. If
I had proposed to rewrite our CMOS code in assembler, the response would
not have been enthusiastic either.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From rminnich at gmail.com  Sat Oct  3 19:40:35 2009
From: rminnich at gmail.com (ron minnich)
Date: Sat, 3 Oct 2009 10:40:35 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003173252.1061.qmail@stuge.se>
References: <4AC4A487.1050003@us.ibm.com> <4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
Message-ID: <13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>

I use qemu for a lot of coreboot work. I really depend on qemu for
many things I do, not just coreboot related. The qemu target in
coreboot has been very heavily used by us to test out new ideas.

That said, I don't see a compelling need to augment seabios with
coreboot on qemu *in the standard distribution*. If seabios gets the
job done, and gets OSes booted, I think that's sufficient. I don't see
a need to complicate anyone's life with something that is, after all,
a sideshow for qemu users.

Conversely, I don't see the need to add the huge pile of stuff that
comes with UEFI/OVMF/whatever to qemu either. One might argue that
having any BIOS callbacks in the OS is a huge mistake, and certainly
I've learned in practice that this argument is true.

thanks

ron



From peter at stuge.se  Sat Oct  3 20:03:25 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 20:03:25 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <4AC78B56.2040304@gmx.net>
References: <13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se>
	<4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
	<20091001235825.GA29687@morn.localdomain>
	<4AC5CDCB.7080901@georgi-clan.de> <4AC5D02F.4040305@gmx.net>
	<20091003163417.23369.qmail@stuge.se> <4AC78B56.2040304@gmx.net>
Message-ID: <20091003180325.6108.qmail@stuge.se>

Carl-Daniel Hailfinger wrote:
> >> IMHO access to CMOS before CAR is unnecessarily painful
> >
> > Why?
> 
> Because you either introduce a dependency on ROMCC or you need
> additional assembler code.

I love Patrick's idea about generating macros from cmos.layout. With
that, the additional assembler code would amount to maybe 15
instructions. Far from painful to me.


//Peter



From gleb at redhat.com  Sat Oct  3 20:16:31 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Sat, 3 Oct 2009 20:16:31 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
References: <4AC51DBA.7020609@codemonkey.ws>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
Message-ID: <20091003181631.GG17326@redhat.com>

On Sat, Oct 03, 2009 at 10:40:35AM -0700, ron minnich wrote:
> I use qemu for a lot of coreboot work. I really depend on qemu for
> many things I do, not just coreboot related. The qemu target in
> coreboot has been very heavily used by us to test out new ideas.
> 
> That said, I don't see a compelling need to augment seabios with
> coreboot on qemu *in the standard distribution*. If seabios gets the
> job done, and gets OSes booted, I think that's sufficient. I don't see
> a need to complicate anyone's life with something that is, after all,
> a sideshow for qemu users.
> 
Exactly. I am glad to hear that coreboot has support for QEMU,
but seabios does the job already, so why add more layers?

> Conversely, I don't see the need to add the huge pile of stuff that
> comes with UEFI/OVMF/whatever to qemu either. One might argue that
> having any BIOS callbacks in the OS is a huge mistake, and certainly
> I've learned in practice that this argument is true.
> 
> thanks
> 
> ron

--
			Gleb.



From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 20:20:33 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 20:20:33 +0200
Subject: [coreboot] [PATCH]Remove non-CBFS
In-Reply-To: <20091003164027.24419.qmail@stuge.se>
References: <1254343315.9254.20.camel@tetris>	<46F32041A2CB4C16A76C44EF06B9052E@chimp>	<4AC3E0E5.6090005@coresystems.de>	<20090930232308.GA1720@morn.localdomain>	<13426df10909301626l34b9b185s17eea9944e82ebe2@mail.gmail.com>	<20090930235721.GA1833@morn.localdomain>
	<4AC45990.4090409@gmx.net> <20091003164027.24419.qmail@stuge.se>
Message-ID: <4AC795F1.5020008@gmx.net>

[adding flashrom at flashrom.org to CC]

On 03.10.2009 18:40, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>   
>> Given that flashrom already has a generic image layout feature, I
>> propose to have cbfstool spit out an image layout file which is
>> then read by flashrom. This makes flashrom independent of CBFS and
>> that's a good thing (think upgrade).
>>     
>
> This is trivial to implement and might be a good first step, but it's
> absolutely horrible from a usability perspective;
>
> The user would need to keep track of and understand no less than two
> tools, AND an intermediary layout file, in order to perform the
> single task of partial firmware update.
>   

The user has to understand cbfstool and lar anyway right now if he/she
wants to do anything useful with fallback/normal. The user also has to
understand flashrom to flash the resulting image. The user will not
directly inspect the ROM image, nor will he/she directly inspect the
layout file.


> I think it is quite neccessary for flashrom to understand CBFS (and
> LAR, for v3 users).
>   

What about WPH and other formats from proprietary BIOS vendors? Flashrom
has more users who deal with WPH and related formats than it has users
who deal with CBFS or LAR.

IIRC the Unix philosophy is roughly "Create programs that do one thing
and do it well. Use simple programs together." I like that philosophy.
One option would be to have cbfstool and lar execute the flashrom binary.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From c-d.hailfinger.devel.2006 at gmx.net  Sat Oct  3 20:22:01 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sat, 03 Oct 2009 20:22:01 +0200
Subject: [coreboot] Boot issues (CBFS?) on VIA pc2500e
In-Reply-To: <20091003171519.GJ15511@greenwood>
References: <20091001013040.GC15511@greenwood>	<0245AF4550D4474DBCCE0C2083A3F306@chimp>	<4AC48F68.9000801@coresystems.de>
	<20091003171519.GJ15511@greenwood>
Message-ID: <4AC79649.6050906@gmx.net>

On 03.10.2009 19:15, Uwe Hermann wrote:
> On Thu, Oct 01, 2009 at 01:15:52PM +0200, Stefan Reinauer wrote:
>   
>> Myles Watson wrote:
>>     
>>>> High Tables Base is 1fff0000.
>>>> Copying Interrupt Routing Table to 0x000f0000... done.
>>>> Copying Interrupt Routing Table to 0x1fff0000... done.
>>>> Wrote the mp table end at: 000f0410 - 000f0568
>>>> Wrote the mp table end at: 1fff0410 - 2001040e
>>>>     
>>>>         
>>> Writing high tables above RAM!  Why is the high MP table so much larger than
>>> the low one?
>>>  
>>>   
>>>       
>> Right! Good spotting... something is reaaaally fishy here... Almost 64k
>> mp table vs 300 bytes.
>>
>>
>>     
>>>> Moving GDT to 0x20010800...ok
>>>>     
>>>>         
>> And, this alone is good for quite a crash.
>>     
>
> I bisected this, the commit that broke the board was r4238, where high
> tables support was added. Disabling it in
> src/northbridge/cn700/Config.lb results in a successful boot into FILO.
>
> Not sure what the correct fix for working high tables support for this
> board/chipset is.
>   

High tables are also broken on 690G. I sent a hacky patch for this
(which is unmerged), but we need a real solution.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From peter at stuge.se  Sat Oct  3 20:26:55 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 20:26:55 +0200
Subject: [coreboot] [v2] r4707 - in
	trunk/coreboot-v2:	src/mainboard/dell/s1850 targets
In-Reply-To: <13426df10910031020s41164e7fs42e791af5ab3594d@mail.gmail.com>
References: <20091002001157.2403.qmail@stuge.se>
	<13426df10910012041m16ddb588xc5d191fe6407dbe4@mail.gmail.com>
	<20091002125035.GG15511@greenwood>
	<13426df10910020904j72672ce8o3fdcfb07776a521a@mail.gmail.com>
	<20091002161206.19314.qmail@stuge.se>
	<4AC772BE.4010403@coresystems.de>
	<20091003160807.GI15511@greenwood>
	<20091003164443.25272.qmail@stuge.se>
	<13426df10910031020s41164e7fs42e791af5ab3594d@mail.gmail.com>
Message-ID: <20091003182656.9963.qmail@stuge.se>

ron minnich wrote:
> actually it's all meaningless in a sense. We have ten 1850s that
> have utterly different motherboards than the other 128. They can't
> even properly netboot as the other 128 do. They all look the same
> outside.

Ok, then it would be nice to find out more about the actual boards
inside. Thinking of this I remember one customer getting some systems
with different onboard NICs, although it was the very same server
model.


> Vendor names on the outside tell you nothing about the inside.

As always, very true.


//Peter



From peter at stuge.se  Sat Oct  3 20:30:30 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 20:30:30 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003181631.GG17326@redhat.com>
References: <2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<20091003181631.GG17326@redhat.com>
Message-ID: <20091003183030.10662.qmail@stuge.se>

Gleb Natapov wrote:
> Exactly. I am glad to hear that coreboot has support for QEMU,
> but seabios does the job already, so why add more layers?

If SeaBIOS does not need any code at all for QEMU machine init I
agree there's no point in considering coreboot.

If QEMU machine specific init is in fact needed in that SeaBIOS, then
the answer isn't as obvious..


//Peter



From patrick at georgi-clan.de  Sat Oct  3 20:51:12 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 03 Oct 2009 20:51:12 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <20091003180325.6108.qmail@stuge.se>
References: <13426df10909301532s1d0806f0x62b02567e4c7040a@mail.gmail.com>
	<20090930224333.14184.qmail@stuge.se> <4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
	<20091001235825.GA29687@morn.localdomain>
	<4AC5CDCB.7080901@georgi-clan.de>
	<4AC5D02F.4040305@gmx.net> <20091003163417.23369.qmail@stuge.se>
	<4AC78B56.2040304@gmx.net>  <20091003180325.6108.qmail@stuge.se>
Message-ID: <1254595872.3224.30.camel@tetris>

Am Samstag, den 03.10.2009, 20:03 +0200 schrieb Peter Stuge:
> > Because you either introduce a dependency on ROMCC or you need
> > additional assembler code.
> 
> I love Patrick's idea about generating macros from cmos.layout. With
> that, the additional assembler code would amount to maybe 15
> instructions. Far from painful to me.
The thing is, there's code that isn't that pretty in assembly. K8 HT
init comes to mind (necessary for rom mapping), so there is a use case
for romcc in that model anyway.


But that isn't all that bad in my opinion:
1. we had much more trouble with gcc than with romcc.. If anything, gcc
has to go ;-)
2. We're talking about a tiny piece of code here. The smaller, the
better, so that even good, slow, unscalable romcc won't be too much of a
burden.
3. We'll be using romcc for various projects anyway (eg. serialICE) -
it's far from that, so we can use it where appropriate.

We have issues with romcc currently because we use it on a large set of
files from many separate parts of the tree (the various bridges etc),
and suffer from its constraints.

What I don't know is, do we require any chipset setup to _reach_ CMOS?
Accessing it will be trivial, no matter if assembly or romcc.


Patrick




From peter at stuge.se  Sat Oct  3 21:05:38 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 21:05:38 +0200
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <1254595872.3224.30.camel@tetris>
References: <4AC3E2F3.6060509@coresystems.de>
	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>
	<1254380991.21870.21.camel@tetris>
	<20091001235825.GA29687@morn.localdomain>
	<4AC5CDCB.7080901@georgi-clan.de> <4AC5D02F.4040305@gmx.net>
	<20091003163417.23369.qmail@stuge.se>
	<4AC78B56.2040304@gmx.net> <20091003180325.6108.qmail@stuge.se>
	<1254595872.3224.30.camel@tetris>
Message-ID: <20091003190538.16733.qmail@stuge.se>

Patrick Georgi wrote:
> What I don't know is, do we require any chipset setup to _reach_
> CMOS?

It's not generally in the CPU, so some setup may be needed. On the
other hand, maybe 70/71 are decoded correctly on power up, just like
flash access?


//Peter



From kevin at koconnor.net  Sat Oct  3 21:09:20 2009
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 3 Oct 2009 15:09:20 -0400
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003183030.10662.qmail@stuge.se>
References: <4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<20091003181631.GG17326@redhat.com>
	<20091003183030.10662.qmail@stuge.se>
Message-ID: <20091003190920.GA16294@morn.localdomain>

On Sat, Oct 03, 2009 at 08:30:30PM +0200, Peter Stuge wrote:
> Gleb Natapov wrote:
> > Exactly. I am glad to hear that coreboot has support for QEMU,
> > but seabios does the job already, so why add more layers?
> 
> If SeaBIOS does not need any code at all for QEMU machine init I
> agree there's no point in considering coreboot.

SeaBIOS contains the code necessary to initialize the qemu hardware.

For the details see src/mtrr.c, src/pciinit.c, src/shadow.c, and
src/smm.c.  These codepaths are disabled when SeaBIOS is compiled for
coreboot.

-Kevin



From gleb at redhat.com  Sat Oct  3 21:09:54 2009
From: gleb at redhat.com (Gleb Natapov)
Date: Sat, 3 Oct 2009 21:09:54 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003183030.10662.qmail@stuge.se>
References: <4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<20091003181631.GG17326@redhat.com>
	<20091003183030.10662.qmail@stuge.se>
Message-ID: <20091003190954.GH17326@redhat.com>

On Sat, Oct 03, 2009 at 08:30:30PM +0200, Peter Stuge wrote:
> Gleb Natapov wrote:
> > Exactly. I am glad to hear that coreboot has support for QEMU,
> > but seabios does the job already, so why add more layers?
> 
> If SeaBIOS does not need any code at all for QEMU machine init I
> agree there's no point in considering coreboot.
> 
The code is there already.

> If QEMU machine specific init is in fact needed in that SeaBIOS, then
> the answer isn't as obvious..
> 
May be it is possible to drop seabios init code and use coreboot, but I
prefer to dial with one codebase for all BIOS needs. By moving to seabios
we try to improve situation not make it worse.

--
			Gleb.



From patrick at georgi-clan.de  Sat Oct  3 22:11:08 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 03 Oct 2009 22:11:08 +0200
Subject: [coreboot] [PATCH]kconfig cleanup (failover config flags)
Message-ID: <1254600668.12717.1.camel@tetris>

Hi,

attached patch moves the failover configuration symbols to a global
file, defined as bool, defaulting to false.
Given that Kconfig doesn't support failover, there hardly will be a
reason to enable it, and if there is, they can still be enabled as
needed.


Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From harald.gutmann at gmx.net  Sat Oct  3 22:29:32 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sat, 3 Oct 2009 22:29:32 +0200
Subject: [coreboot] Gigabyte M57SLI Kconfig support
Message-ID: <200910032229.32190.harald.gutmann@gmx.net>

Hello,

here is my new patch which adds the Kconfig support for m57sli from gigabyte.

There is one Problem with the patch, but I'm not able to track that down.
I've really no idea what causes Kconfig to put all those warnings out with my 
patch. As this patch causes quite a massive amount of warnings, and I wasn't 
able to fix that it is not signed off.

The warnings which are given by make menuconfig are attached in warnings.txt 
and the patch itself is also attached.
Hopefully someone can help me to track this down.


Kind regards,
Harald

-------------- next part --------------
src/mainboard/gigabyte/m57sli/Kconfig:66:warning: choice value must have a prompt
src/mainboard/gigabyte/m57sli/Kconfig:68:warning: defaults for choice values not supported
src/mainboard/intel/xe7501devkit/Kconfig:21:warning: defaults for choice values not supported
src/Kconfig:69:warning: defaults for choice values not supported                             
src/mainboard/gigabyte/m57sli/Kconfig:70:warning: choice value must have a prompt            
src/mainboard/amd/serengeti_cheetah/Kconfig:54:warning: defaults for choice values not supported
src/mainboard/asus/m2v-mx_se/Kconfig:92:warning: defaults for choice values not supported       
src/mainboard/dell/s1850/Kconfig:20:warning: defaults for choice values not supported           
src/mainboard/gigabyte/m57sli/Kconfig:72:warning: defaults for choice values not supported      
src/mainboard/intel/eagleheights/Kconfig:40:warning: defaults for choice values not supported   
src/mainboard/intel/jarrell/Kconfig:21:warning: defaults for choice values not supported        
src/mainboard/intel/mtarvon/Kconfig:20:warning: defaults for choice values not supported        
src/mainboard/intel/truxton/Kconfig:21:warning: defaults for choice values not supported        
src/mainboard/intel/xe7501devkit/Kconfig:26:warning: defaults for choice values not supported   
src/mainboard/kontron/986lcd-m/Kconfig:33:warning: defaults for choice values not supported     
src/mainboard/sunw/ultra40/Kconfig:63:warning: defaults for choice values not supported         
src/mainboard/supermicro/h8dme/Kconfig:63:warning: defaults for choice values not supported     
src/mainboard/tyan/s2881/Kconfig:32:warning: defaults for choice values not supported           
src/mainboard/tyan/s2891/Kconfig:32:warning: defaults for choice values not supported           
src/mainboard/tyan/s2892/Kconfig:32:warning: defaults for choice values not supported           
src/mainboard/tyan/s2895/Kconfig:32:warning: defaults for choice values not supported           
src/Kconfig:73:warning: defaults for choice values not supported                                
src/mainboard/gigabyte/m57sli/Kconfig:75:warning: choice value must have a prompt               
src/mainboard/amd/serengeti_cheetah/Kconfig:59:warning: defaults for choice values not supported
src/mainboard/asus/m2v-mx_se/Kconfig:97:warning: defaults for choice values not supported       
src/mainboard/dell/s1850/Kconfig:25:warning: defaults for choice values not supported           
src/mainboard/gigabyte/m57sli/Kconfig:77:warning: defaults for choice values not supported      
src/mainboard/intel/eagleheights/Kconfig:45:warning: defaults for choice values not supported   
src/mainboard/intel/jarrell/Kconfig:26:warning: defaults for choice values not supported        
src/mainboard/intel/mtarvon/Kconfig:25:warning: defaults for choice values not supported        
src/mainboard/intel/truxton/Kconfig:26:warning: defaults for choice values not supported        
src/mainboard/intel/xe7501devkit/Kconfig:31:warning: defaults for choice values not supported   
src/mainboard/kontron/986lcd-m/Kconfig:38:warning: defaults for choice values not supported     
src/mainboard/sunw/ultra40/Kconfig:68:warning: defaults for choice values not supported         
src/mainboard/supermicro/h8dme/Kconfig:68:warning: defaults for choice values not supported     
src/mainboard/tyan/s2881/Kconfig:37:warning: defaults for choice values not supported           
src/mainboard/tyan/s2891/Kconfig:37:warning: defaults for choice values not supported           
src/mainboard/tyan/s2892/Kconfig:37:warning: defaults for choice values not supported           
src/mainboard/tyan/s2895/Kconfig:37:warning: defaults for choice values not supported           
src/Kconfig:77:warning: defaults for choice values not supported                                
src/mainboard/gigabyte/m57sli/Kconfig:80:warning: choice value must have a prompt               
src/mainboard/a-trend/atc-6220/Kconfig:42:warning: defaults for choice values not supported     
src/mainboard/a-trend/atc-6240/Kconfig:42:warning: defaults for choice values not supported     
src/mainboard/abit/be6-ii_v2_0/Kconfig:42:warning: defaults for choice values not supported     
src/mainboard/amd/serengeti_cheetah/Kconfig:64:warning: defaults for choice values not supported
src/mainboard/amd/rumba/Kconfig:40:warning: defaults for choice values not supported            
src/mainboard/asus/p2b/Kconfig:42:warning: defaults for choice values not supported             
src/mainboard/asus/p2b-d/Kconfig:45:warning: defaults for choice values not supported           
src/mainboard/asus/p2b-f/Kconfig:42:warning: defaults for choice values not supported           
src/mainboard/asus/p3b-f/Kconfig:42:warning: defaults for choice values not supported           
src/mainboard/asus/m2v-mx_se/Kconfig:67:warning: defaults for choice values not supported       
src/mainboard/asus/mew-am/Kconfig:42:warning: defaults for choice values not supported          
src/mainboard/asus/mew-vm/Kconfig:42:warning: defaults for choice values not supported          
src/mainboard/azza/pt-6ibd/Kconfig:42:warning: defaults for choice values not supported         
src/mainboard/biostar/m6tba/Kconfig:42:warning: defaults for choice values not supported        
src/mainboard/compaq/deskpro_en_sff_p600/Kconfig:43:warning: defaults for choice values not supported
src/mainboard/dell/s1850/Kconfig:30:warning: defaults for choice values not supported                
src/mainboard/emulation/qemu-x86/Kconfig:18:warning: defaults for choice values not supported        
src/mainboard/gigabyte/ga-6bxc/Kconfig:42:warning: defaults for choice values not supported          
src/mainboard/gigabyte/m57sli/Kconfig:82:warning: defaults for choice values not supported           
src/mainboard/intel/eagleheights/Kconfig:50:warning: defaults for choice values not supported        
src/mainboard/intel/jarrell/Kconfig:31:warning: defaults for choice values not supported             
src/mainboard/intel/mtarvon/Kconfig:30:warning: defaults for choice values not supported             
src/mainboard/intel/truxton/Kconfig:31:warning: defaults for choice values not supported             
src/mainboard/intel/xe7501devkit/Kconfig:36:warning: defaults for choice values not supported        
src/mainboard/kontron/986lcd-m/Kconfig:43:warning: defaults for choice values not supported          
src/mainboard/mitac/6513wu/Kconfig:42:warning: defaults for choice values not supported              
src/mainboard/msi/ms6119/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/msi/ms6147/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/msi/ms6178/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/nec/powermate2000/Kconfig:42:warning: defaults for choice values not supported         
src/mainboard/soyo/sy-6ba-plus-iii/Kconfig:42:warning: defaults for choice values not supported      
src/mainboard/sunw/ultra40/Kconfig:73:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:73:warning: defaults for choice values not supported          
src/mainboard/tyan/s1846/Kconfig:41:warning: defaults for choice values not supported                
src/mainboard/tyan/s2881/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:42:warning: defaults for choice values not supported                
src/mainboard/via/epia/Kconfig:29:warning: defaults for choice values not supported                  
src/mainboard/via/epia-cn/Kconfig:29:warning: defaults for choice values not supported               
src/mainboard/via/epia-m/Kconfig:30:warning: defaults for choice values not supported                
src/mainboard/via/epia-m700/Kconfig:28:warning: defaults for choice values not supported             
src/mainboard/via/epia-n/Kconfig:29:warning: defaults for choice values not supported                
src/mainboard/via/pc2500e/Kconfig:29:warning: defaults for choice values not supported               
src/mainboard/via/vt8454c/Kconfig:31:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:85:warning: choice value must have a prompt                    
src/mainboard/gigabyte/m57sli/Kconfig:87:warning: defaults for choice values not supported           
src/devices/Kconfig:78:warning: defaults for choice values not supported                             
src/mainboard/gigabyte/m57sli/Kconfig:90:warning: choice value must have a prompt                    
src/mainboard/gigabyte/m57sli/Kconfig:92:warning: defaults for choice values not supported           
src/Kconfig:147:warning: defaults for choice values not supported                                    
src/mainboard/gigabyte/m57sli/Kconfig:95:warning: choice value must have a prompt                    
src/mainboard/gigabyte/m57sli/Kconfig:97:warning: defaults for choice values not supported           
src/Kconfig:151:warning: defaults for choice values not supported                                    
src/mainboard/gigabyte/m57sli/Kconfig:100:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:69:warning: defaults for choice values not supported     
src/mainboard/gigabyte/m57sli/Kconfig:102:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:78:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:78:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:57:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:57:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:57:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:57:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:105:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:74:warning: defaults for choice values not supported     
src/mainboard/amd/serengeti_cheetah/Kconfig:99:warning: defaults for choice values not supported     
src/mainboard/gigabyte/m57sli/Kconfig:107:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:62:warning: defaults for choice values not supported                
src/mainboard/tyan/s2881/Kconfig:87:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:62:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:87:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:62:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:87:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:62:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:87:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:110:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:79:warning: defaults for choice values not supported     
src/mainboard/dell/s1850/Kconfig:45:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:112:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:83:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:83:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:67:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:67:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:67:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:67:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:115:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:84:warning: defaults for choice values not supported     
src/mainboard/dell/s1850/Kconfig:40:warning: defaults for choice values not supported                
src/mainboard/dell/s1850/Kconfig:50:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:117:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:88:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:88:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:52:warning: defaults for choice values not supported                
src/mainboard/tyan/s2881/Kconfig:72:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:52:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:72:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:52:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:72:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:52:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:72:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:120:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:89:warning: defaults for choice values not supported     
src/mainboard/asus/p2b-d/Kconfig:60:warning: defaults for choice values not supported                
src/mainboard/asus/m2v-mx_se/Kconfig:72:warning: defaults for choice values not supported            
src/mainboard/dell/s1850/Kconfig:55:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:122:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:93:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:93:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:77:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:77:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:77:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:77:warning: defaults for choice values not supported                
src/Kconfig:113:warning: defaults for choice values not supported                                    
src/mainboard/gigabyte/m57sli/Kconfig:125:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:94:warning: defaults for choice values not supported     
src/mainboard/asus/m2v-mx_se/Kconfig:77:warning: defaults for choice values not supported            
src/mainboard/dell/s1850/Kconfig:60:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:127:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:98:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:98:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:82:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:82:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:82:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:82:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:130:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:104:warning: defaults for choice values not supported    
src/mainboard/amd/serengeti_cheetah/Kconfig:144:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:132:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:92:warning: defaults for choice values not supported                
src/mainboard/tyan/s2881/Kconfig:122:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:92:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:122:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:92:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:122:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:92:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:122:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:135:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:109:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:137:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:97:warning: defaults for choice values not supported                
src/mainboard/tyan/s2891/Kconfig:97:warning: defaults for choice values not supported                
src/mainboard/tyan/s2892/Kconfig:97:warning: defaults for choice values not supported                
src/mainboard/tyan/s2895/Kconfig:97:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:140:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:129:warning: defaults for choice values not supported    
src/mainboard/asus/m2v-mx_se/Kconfig:102:warning: defaults for choice values not supported           
src/mainboard/gigabyte/m57sli/Kconfig:142:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:108:warning: defaults for choice values not supported             
src/mainboard/supermicro/h8dme/Kconfig:108:warning: defaults for choice values not supported         
src/mainboard/tyan/s2881/Kconfig:102:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:102:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:102:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:102:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:145:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:114:warning: defaults for choice values not supported    
src/mainboard/asus/m2v-mx_se/Kconfig:107:warning: defaults for choice values not supported           
src/mainboard/gigabyte/m57sli/Kconfig:147:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:58:warning: defaults for choice values not supported              
src/mainboard/supermicro/h8dme/Kconfig:58:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:137:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:137:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:137:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:137:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:150:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:124:warning: defaults for choice values not supported    
src/mainboard/asus/m2v-mx_se/Kconfig:117:warning: defaults for choice values not supported           
src/mainboard/gigabyte/m57sli/Kconfig:152:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:103:warning: defaults for choice values not supported             
src/mainboard/supermicro/h8dme/Kconfig:103:warning: defaults for choice values not supported         
src/mainboard/tyan/s2881/Kconfig:107:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:107:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:107:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:107:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:155:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:134:warning: defaults for choice values not supported    
src/mainboard/amd/rumba/Kconfig:55:warning: defaults for choice values not supported                 
src/mainboard/dell/s1850/Kconfig:65:warning: defaults for choice values not supported                
src/mainboard/gigabyte/m57sli/Kconfig:157:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:113:warning: defaults for choice values not supported             
src/mainboard/supermicro/h8dme/Kconfig:113:warning: defaults for choice values not supported         
src/mainboard/tyan/s2881/Kconfig:112:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:112:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:112:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:112:warning: defaults for choice values not supported               
src/mainboard/gigabyte/m57sli/Kconfig:160:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:139:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:162:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:117:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:117:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:117:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:117:warning: defaults for choice values not supported               
src/cpu/x86/Kconfig:3:warning: defaults for choice values not supported                              
src/mainboard/gigabyte/m57sli/Kconfig:165:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:149:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:167:warning: defaults for choice values not supported          
src/mainboard/tyan/s2881/Kconfig:127:warning: defaults for choice values not supported               
src/mainboard/tyan/s2891/Kconfig:127:warning: defaults for choice values not supported               
src/mainboard/tyan/s2892/Kconfig:127:warning: defaults for choice values not supported               
src/mainboard/tyan/s2895/Kconfig:127:warning: defaults for choice values not supported               
src/cpu/x86/Kconfig:7:warning: defaults for choice values not supported                              
src/mainboard/gigabyte/m57sli/Kconfig:170:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:154:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:172:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:123:warning: defaults for choice values not supported             
src/mainboard/supermicro/h8dme/Kconfig:123:warning: defaults for choice values not supported         
src/console/Kconfig:33:warning: choice values currently only support a single prompt                 
src/console/Kconfig:34:warning: defaults for choice values not supported                             
src/mainboard/gigabyte/m57sli/Kconfig:175:warning: choice value must have a prompt                   
src/mainboard/amd/serengeti_cheetah/Kconfig:159:warning: defaults for choice values not supported    
src/mainboard/gigabyte/m57sli/Kconfig:177:warning: defaults for choice values not supported          
src/mainboard/sunw/ultra40/Kconfig:128:warning: defaults for choice values not supported             
src/mainboard/supermicro/h8dme/Kconfig:128:warning: defaults for choice values not supported
src/devices/Kconfig:37:warning: choice values currently only support a single prompt
src/Kconfig:85:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:180:warning: choice value must have a prompt
src/mainboard/gigabyte/m57sli/Kconfig:182:warning: defaults for choice values not supported
src/mainboard/sunw/ultra40/Kconfig:48:warning: defaults for choice values not supported
src/cpu/amd/Kconfig:3:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:185:warning: choice value must have a prompt
src/mainboard/gigabyte/m57sli/Kconfig:187:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:190:warning: choice value must have a prompt
src/mainboard/Kconfig:315:warning: defaults for choice values not supported
src/mainboard/Kconfig:325:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:192:warning: defaults for choice values not supported
src/Kconfig:49:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:195:warning: choice value must have a prompt
src/mainboard/dell/s1850/Kconfig:35:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:197:warning: defaults for choice values not supported
src/mainboard/tyan/s2881/Kconfig:47:warning: defaults for choice values not supported
src/mainboard/tyan/s2891/Kconfig:47:warning: defaults for choice values not supported
src/mainboard/tyan/s2892/Kconfig:47:warning: defaults for choice values not supported
src/mainboard/tyan/s2895/Kconfig:47:warning: defaults for choice values not supported
src/Kconfig:53:warning: defaults for choice values not supported
src/mainboard/gigabyte/m57sli/Kconfig:200:warning: choice value must have a prompt
src/mainboard/gigabyte/m57sli/Kconfig:202:warning: defaults for choice values not supported
src/mainboard/tyan/s2881/Kconfig:141:warning: choice values currently only support a single prompt
src/mainboard/tyan/s2881/Kconfig:142:warning: defaults for choice values not supported
src/mainboard/tyan/s2891/Kconfig:141:warning: choice values currently only support a single prompt
src/mainboard/tyan/s2891/Kconfig:142:warning: defaults for choice values not supported
src/mainboard/tyan/s2892/Kconfig:141:warning: choice values currently only support a single prompt
src/mainboard/tyan/s2892/Kconfig:142:warning: defaults for choice values not supported
src/mainboard/tyan/s2895/Kconfig:141:warning: choice values currently only support a single prompt
src/mainboard/tyan/s2895/Kconfig:142:warning: defaults for choice values not supported
src/Kconfig:225:warning: choice values currently only support a single prompt
src/Kconfig:226:warning: defaults for choice values not supported
.config:75:warning: override: SB_HT_CHAIN_UNITID_OFFSET_ONLY changes choice state
.config:88:warning: override: BOARD_GIGABYTE_M57SLI changes choice state
.config:95:warning: override: K8_REV_F_SUPPORT changes choice state
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From harald.gutmann at gmx.net  Sat Oct  3 22:48:42 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sat, 3 Oct 2009 22:48:42 +0200
Subject: [coreboot] Gigabyte M57SLI Kconfig support
In-Reply-To: <200910032229.32190.harald.gutmann@gmx.net>
References: <200910032229.32190.harald.gutmann@gmx.net>
Message-ID: <200910032248.42658.harald.gutmann@gmx.net>

On Saturday 03 October 2009 22:29:32 Harald Gutmann wrote:
> There is one Problem with the patch, but I'm not able to track that down.
> I've really no idea what causes Kconfig to put all those warnings out with
>  my patch. As this patch causes quite a massive amount of warnings, and I
>  wasn't able to fix that it is not signed off.
There was a "depends on" missing in my Kconfig for m57sli.
Thanks a lot to Patrick Georgi for finding that one!

Some more modifications to the first patch sent have been done.

Now the patch builds a image without errors for that board, but it's right now 
untested as SPI chips >512kb can not be accessed correctly on m57sli after the 
"remove non-CBFS" patch.

Maybe someone who has a <=512kb chip can test this.


Attached is the new version of the patch which is

Signed-off-by: Harald Gutmann

Kind regards,
Harald
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From harald.gutmann at gmx.net  Sat Oct  3 22:52:42 2009
From: harald.gutmann at gmx.net (Harald Gutmann)
Date: Sat, 3 Oct 2009 22:52:42 +0200
Subject: [coreboot] Gigabyte M57SLI Kconfig support
In-Reply-To: <200910032229.32190.harald.gutmann@gmx.net>
References: <200910032229.32190.harald.gutmann@gmx.net>
Message-ID: <200910032252.42240.harald.gutmann@gmx.net>

On Saturday 03 October 2009 22:29:32 Harald Gutmann wrote:
> Hello,
> 
> here is my new patch which adds the Kconfig support for m57sli from
>  gigabyte.
The changes in devicetree.cb are just whitespace fixes and I removed some parts 



Kind regards,
Harald




From peter at stuge.se  Sat Oct  3 22:55:41 2009
From: peter at stuge.se (Peter Stuge)
Date: Sat, 3 Oct 2009 22:55:41 +0200
Subject: [coreboot] [PATCH]kconfig cleanup (failover config flags)
In-Reply-To: <1254600668.12717.1.camel@tetris>
References: <1254600668.12717.1.camel@tetris>
Message-ID: <20091003205541.1067.qmail@stuge.se>

Patrick Georgi wrote:
> attached patch moves the failover configuration symbols to a global
> file, defined as bool, defaulting to false.
> Given that Kconfig doesn't support failover, there hardly will be a
> reason to enable it, and if there is, they can still be enabled as
> needed.
> 
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>


> +config HAVE_FAILOVER_BOOT
> +config USE_FAILOVER_IMAGE

Could we simplify to config FAILOVER or even further? Maybe something
to look into when implementing it for CBFS.


//Peter



From svn at coreboot.org  Sat Oct  3 23:04:14 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 23:04:14 +0200
Subject: [coreboot] [v2] r4714 - in trunk/coreboot-v2/src: .
	mainboard/amd/serengeti_cheetah mainboard/dell/s1850
	mainboard/sunw/ultra40 mainboard/supermicro/h8dme
	mainboard/tyan/s2850 mainboard/tyan/s2875
	mainboard/tyan/s2881 mainboard/tyan/s2891
	mainboard/tyan/s2892 mainboard/tyan/s2895
Message-ID: <mailman.3785.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-03 23:04:13 +0200 (Sat, 03 Oct 2009)
New Revision: 4714

Modified:
   trunk/coreboot-v2/src/Kconfig
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig
Log:
Move HAVE_FAILOVER_BOOT and USE_FAILOVER_IMAGE from
boards to global. It's not a per-board value, but
compatibility stuff.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/Kconfig
===================================================================
--- trunk/coreboot-v2/src/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -146,6 +146,14 @@
 	bool
 	default y
 
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+
 config HAVE_HARD_RESET
 	bool
 	default 0

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -72,16 +72,6 @@
 	default y
 	depends on BOARD_AMD_SERENGETI_CHEETAH
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_AMD_SERENGETI_CHEETAH
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_AMD_SERENGETI_CHEETAH
-
 config MAX_CPUS
 	int
 	default 8

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -33,21 +33,6 @@
 	default 0x016c
 	depends on BOARD_DELL_S1850
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_DELL_S1850
-
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_DELL_S1850
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_DELL_S1850
-
 config MAX_CPUS
 	int
 	default 2

Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -76,16 +76,6 @@
 	default 0x100000
 	depends on BOARD_SUNW_ULTRA40
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_SUNW_ULTRA40
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_SUNW_ULTRA40
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -76,16 +76,6 @@
 	default 0x100000
 	depends on BOARD_SUPERMICRO_H8DME
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8DME
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8DME
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -39,16 +39,6 @@
 	default 0x100000
 	depends on BOARD_TYAN_S2850
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2850
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2850
-
 config MAX_CPUS
 	int
 	default 2

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -40,16 +40,6 @@
 	default 0x100000
 	depends on BOARD_TYAN_S2875
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2875
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2875
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -45,11 +45,6 @@
 	default 0x2881
 	depends on BOARD_TYAN_S2881
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2881
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
@@ -60,16 +55,6 @@
 	default n
 	depends on BOARD_TYAN_S2881
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2881
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2881
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -45,11 +45,6 @@
 	default 0x2891
 	depends on BOARD_TYAN_S2891
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2891
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
@@ -60,16 +55,6 @@
 	default n
 	depends on BOARD_TYAN_S2891
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2891
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2891
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -45,11 +45,6 @@
 	default 0x2892
 	depends on BOARD_TYAN_S2892
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2892
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
@@ -60,16 +55,6 @@
 	default n
 	depends on BOARD_TYAN_S2892
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2892
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2892
-
 config MAX_CPUS
 	int
 	default 4

Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig	2009-10-03 16:27:48 UTC (rev 4713)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
@@ -45,11 +45,6 @@
 	default 0x2895
 	depends on BOARD_TYAN_S2895
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2895
-
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
@@ -60,16 +55,6 @@
 	default n
 	depends on BOARD_TYAN_S2895
 
-config HAVE_FAILOVER_BOOT
-	bool
-	default n
-	depends on BOARD_TYAN_S2895
-
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_TYAN_S2895
-
 config MAX_CPUS
 	int
 	default 4




From patrick at georgi-clan.de  Sat Oct  3 23:05:03 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 03 Oct 2009 23:05:03 +0200
Subject: [coreboot] [PATCH]kconfig cleanup (failover config flags)
In-Reply-To: <20091003205541.1067.qmail@stuge.se>
References: <1254600668.12717.1.camel@tetris>
	<20091003205541.1067.qmail@stuge.se>
Message-ID: <1254603903.12717.4.camel@tetris>

Am Samstag, den 03.10.2009, 22:55 +0200 schrieb Peter Stuge:
> Acked-by: Peter Stuge <peter at stuge.se>
Thanks, r4714

> > +config HAVE_FAILOVER_BOOT
> > +config USE_FAILOVER_IMAGE
> 
> Could we simplify to config FAILOVER or even further? Maybe something
> to look into when implementing it for CBFS.
They are still in use by newconfig, and are both required - They're only
here so the code makes the right decisions. Nothing to simplify at this
point.


Patrick




From svn at coreboot.org  Sat Oct  3 23:06:53 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 23:06:53 +0200
Subject: [coreboot] [v2] r4715 - in
	trunk/coreboot-v2/src/mainboard/gigabyte: . m57sli
Message-ID: <mailman.3786.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-03 23:06:53 +0200 (Sat, 03 Oct 2009)
New Revision: 4715

Added:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc
Modified:
   trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb
Log:
Add gigabyte/m57sli support to Kconfig.
Whitespace fixes to devicetree.cb

Signed-off-by: Harald Gutmann <harald.gutmann at gmx.net>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig	2009-10-03 21:04:13 UTC (rev 4714)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig	2009-10-03 21:06:53 UTC (rev 4715)
@@ -21,8 +21,9 @@
 choice
 	prompt "Mainboard model"
 	depends on VENDOR_GIGABYTE
-	
+        
 source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
+source "src/mainboard/gigabyte/m57sli/Kconfig"
 
 endchoice
 

Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig	2009-10-03 21:06:53 UTC (rev 4715)
@@ -0,0 +1,153 @@
+
+config BOARD_GIGABYTE_M57SLI
+	bool "M57SLI"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_AM2
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_ITE_IT8716F
+	select PIRQ_TABLE
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	select HAVE_HARD_RESET
+	select HAVE_HIGH_TABLES
+	select IOAPIC
+	select MEM_TRAIN_SEQ
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select HAVE_ACPI_TABLES
+	select K8_REV_F_SUPPORT
+	select PCI_ROM_RUN
+	select CONSOLE_VGA
+	select HAVE_FANCTL
+ 
+config MAINBOARD_DIR
+	string
+	default gigabyte/m57sli 
+	depends on BOARD_GIGABYTE_M57SLI
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_GIGABYTE_M57SLI
+	
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config APIC_ID_OFFSET
+	hex	
+	default 16
+	depends on BOARD_GIGABYTE_M57SLI
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_GIGABYTE_M57SLI
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+	depends on BOARD_GIGABYTE_M57SLI
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_GIGABYTE_M57SLI
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "m57sli"
+	depends on BOARD_GIGABYTE_M57SLI
+
+config PCI_64BIT_PREF_MEM
+	bool
+        default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_FALLBACK_IMAGE
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+
+config AP_CODE_IN_CAR
+	bool	
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool	
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HT_CHAIN_END_UNITID_BASE
+	hex	
+	default 0x0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config SERIAL_CPU_INIT
+	bool	
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config WAIT_BEFORE_CPUS_INIT
+	bool	
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2b80
+	depends on BOARD_GIGABYTE_M57SLI

Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc	2009-10-03 21:06:53 UTC (rev 4715)
@@ -0,0 +1,67 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
+obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
+
+# This is part of the conversion to init-obj and away from included code. 
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv $(obj)/dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb	2009-10-03 21:04:13 UTC (rev 4714)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb	2009-10-03 21:06:53 UTC (rev 4715)
@@ -1,202 +1,175 @@
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_AM2
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/ite/it8716f
-							# Floppy and any LDN
-							device pnp 2e.0 off
-                	               			# Watchdog from CLKIN, CLKIN = 24 MHz
-                	                 			irq 0x23 = 0x11 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+			device apic 0 on end
+		end
+end
+device pci_domain 0 on
+	chip northbridge/amd/amdk8
+		device pci 18.0 on 
+			chip southbridge/nvidia/mcp55 
+				device pci 0.0 on end
+				device pci 1.0 on
+					chip superio/ite/it8716f
+						# Floppy and any LDN
+						device pnp 2e.0 on
+							# Watchdog from CLKIN, CLKIN = 24 MHz
+							irq 0x23 = 0x11
 							# Serial Flash (SPI only)
-								#0x24 = 0x1a
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.2 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.3 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.4 on #  EC
-                	                 			io 0x60 = 0x290
-                	                 			io 0x62 = 0x230
-                	                			irq 0x70 = 9
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-							end
-                	        			device pnp 2e.6 on #  Mouse
-                	                			irq 0x70 = 12
-							end
-	              	        			device pnp 2e.7 on #  GPIO, SPI flash
-								# pin 84 is not GP10
-								irq 0x25 = 0x0
-				# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
-								irq 0x26 = 0x43
-								# pin 13 is GP35
-								irq 0x27 = 0x20 
-								# pin 70 is not GP46
-								#irq 0x28 = 0x0
-				# pin 6,3,128,127,126 is GP63,64,65,66,67
-								irq 0x29 = 0x81
-				# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
-								#irq 0x2c = 0x1f
-				# Simple I/O base
-								io 0x62 = 0x800
-				# Serial Flash I/O (SPI only)
-								io 0x64 = 0x820
-				# watch dog force timeout (parallel flash only)
-								#irq 0x71 = 0x1
-								# No WDT interrupt
-								irq 0x72 = 0x0 
-					# GPIO pin set 1 disable internal pullup
-								irq 0xb8 = 0x0
-					# GPIO pin set 5 enable internal pullup
-								irq 0xbc = 0x01
-					# SIO pin set 1 alternate function
-								#irq 0xc0 = 0x0
-					# SIO pin set 2 mixed function
-								irq 0xc1 = 0x43
-					# SIO pin set 3 mixed function
-								irq 0xc2 = 0x20
-					# SIO pin set 4 alternate function
-								#irq 0xc3 = 0x0
-					# SIO pin set 1 input mode
-								#irq 0xc8 = 0x0
-					# SIO pin set 2 input mode
-								irq 0xc9 = 0x0
-					# SIO pin set 4 input mode
-								#irq 0xcb = 0x0
-					# Generate SMI# on EC IRQ
-								#irq 0xf0 = 0x10
-					# SMI# level trigger
-								#irq 0xf1 = 0x40
-					# HWMON alert beep pin location
-								irq 0xf6 = 0x28
-							end
-                	        			device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 10
-							end
-                	        			device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-                	        			device pnp 2e.a off end #  CIR
+							#0x24 = 0x1a
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
 						end
+						device pnp 2e.1 on # Com1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off # Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 on #  Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp 2e.4 on #  EC
+							io 0x60 = 0x290
+							io 0x62 = 0x230
+							irq 0x70 = 9
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 on #  Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on #  GPIO, SPI flash
+						# pin 84 is not GP10
+							irq 0x25 = 0x0
+						# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+							irq 0x26 = 0x43
+						# pin 13 is GP35
+							irq 0x27 = 0x20 
+						# pin 70 is not GP46
+							#irq 0x28 = 0x0
+						# pin 6,3,128,127,126 is GP63,64,65,66,67
+							irq 0x29 = 0x81
+						# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+							#irq 0x2c = 0x1f
+						# Simple I/O base
+							io 0x62 = 0x800
+						# Serial Flash I/O (SPI only)
+							io 0x64 = 0x820
+						# watch dog force timeout (parallel flash only)
+							#irq 0x71 = 0x1
+						# No WDT interrupt
+							irq 0x72 = 0x0 
+						# GPIO pin set 1 disable internal pullup
+							irq 0xb8 = 0x0
+						# GPIO pin set 5 enable internal pullup
+							irq 0xbc = 0x01
+						# SIO pin set 1 alternate function
+							#irq 0xc0 = 0x0
+						# SIO pin set 2 mixed function
+							irq 0xc1 = 0x43
+						# SIO pin set 3 mixed function
+							irq 0xc2 = 0x20
+						# SIO pin set 4 alternate function
+							#irq 0xc3 = 0x0
+						# SIO pin set 1 input mode
+							#irq 0xc8 = 0x0
+						# SIO pin set 2 input mode
+							irq 0xc9 = 0x0
+						# SIO pin set 4 input mode
+							#irq 0xcb = 0x0
+						# Generate SMI# on EC IRQ
+							#irq 0xf0 = 0x10
+						# SMI# level trigger
+							#irq 0xf1 = 0x40
+						# HWMON alert beep pin location
+							irq 0xf6 = 0x28
+						end
+						device pnp 2e.8 off #  MIDI
+							io 0x60 = 0x300
+							irq 0x70 = 10
+						end
+						device pnp 2e.9 off #  GAME
+							io 0x60 = 0x220
+						end
+						device pnp 2e.a off #  CIR
+						end
 					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
-#WTF?!? We already have device pci 1.1 in the section above
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on end # PCI
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 off end # NIC
-        	       			device pci a.0 on end # PCI E 5
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
+				end
+				device pci 1.1 on
+					chip drivers/generic/generic #dimm 0-0-0
+						device i2c 50 on end
+					end
+					chip drivers/generic/generic #dimm 0-0-1
+						device i2c 51 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-0
+						device i2c 52 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-1
+						device i2c 53 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-0
+						device i2c 54 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-1
+						device i2c 55 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-0
+						device i2c 56 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-1
+						device i2c 57 on end
+					end
+				end # SM
+	                	device pci 2.0 on end # USB 1.1
+        	        	device pci 2.1 on end # USB 2
+                		device pci 4.0 on end # IDE
+	                	device pci 5.0 on end # SATA 0
+	                	device pci 5.1 on end # SATA 1
+	                	device pci 5.2 on end # SATA 2
+                		device pci 6.0 on end # PCI
+        	        	device pci 6.1 on end # AUDIO
+	                	device pci 8.0 on end # NIC
+	                	device pci 9.0 off end # N/A
+        	       		device pci a.0 on end # PCI E 5
+        	       		device pci b.0 on end # PCI E 4
+                		device pci c.0 on end # PCI E 3
+                		device pci d.0 on end # PCI E 2
+                		device pci e.0 on end # PCI E 1
+        	       		device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #device pci 18.0
 			device pci 18.0 on end # Link 1
-			device pci 18.0 on end
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
-#       end  
+
+#	 chip drivers/generic/debug 
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	 end  
+
 end #root_complex




From svn at coreboot.org  Sat Oct  3 23:13:36 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sat,  3 Oct 2009 23:13:36 +0200
Subject: [coreboot] [v2] r4716 -
	trunk/coreboot-v2/src/mainboard/gigabyte/m57sli
Message-ID: <mailman.3787.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-03 23:13:36 +0200 (Sat, 03 Oct 2009)
New Revision: 4716

Modified:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig
Log:
Remove another FAILOVER variable. (trivial)

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig	2009-10-03 21:06:53 UTC (rev 4715)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig	2009-10-03 21:13:36 UTC (rev 4716)
@@ -92,11 +92,6 @@
 	default 0x100000
 	depends on BOARD_GIGABYTE_M57SLI
 
-config USE_FAILOVER_IMAGE
-	bool
-	default n
-	depends on BOARD_GIGABYTE_M57SLI
-
 config MAX_CPUS
 	int
 	default 2




From jljusten at gmail.com  Sat Oct  3 23:49:42 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Sat, 3 Oct 2009 14:49:42 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <20091003173006.595.qmail@stuge.se>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
	<20091003173006.595.qmail@stuge.se>
Message-ID: <2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>

On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
> Jordan Justen wrote:
>> Anyway, it sounds like a useful project might be to develop a UEFI
>> coreboot payload based on the tianocore.org code.
>
> I believe it might have been done already.
>
> http://www.coreboot.org/File:Tianocoreboot.png

That screenshot mentions DUET which is the tianocore.org UEFI emulator
that boots on top of a legacy BIOS.  But, it's unclear if it was just
DUET, or something based modified specifically for coreboot based on
DUET.

I will not dispute that DUET might be a potential solution to achieve
UEFI compatibility for QEMU.  (I'm not sure, but I think DUET may not
be able to boot UEFI OS's at this time.)  However, we thought a
project such as OVMF was a more direct approach to achieve UEFI
compatibility for QEMU.

I see that there was a gnufi project that is mentioned on
http://www.coreboot.org/Payloads, but it looks like this
project may be stalled.  ??

-Jordan



From patrick at georgi-clan.de  Sat Oct  3 23:58:15 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 03 Oct 2009 23:58:15 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
	<20091003173006.595.qmail@stuge.se>
	<2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
Message-ID: <1254607096.12717.10.camel@tetris>

Am Samstag, den 03.10.2009, 14:49 -0700 schrieb Jordan Justen:
> On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
> > Jordan Justen wrote:
> >> Anyway, it sounds like a useful project might be to develop a UEFI
> >> coreboot payload based on the tianocore.org code.
> >
> > I believe it might have been done already.
> >
> > http://www.coreboot.org/File:Tianocoreboot.png
> 
> That screenshot mentions DUET which is the tianocore.org UEFI emulator
> that boots on top of a legacy BIOS.  But, it's unclear if it was just
> DUET, or something based modified specifically for coreboot based on
> DUET.
Modified: The 16bit loader stub was dropped and replaced by 32bit C code
that did mostly the same (pushing code to the right address, jump to the
real entry point, as determined by some PE data structures).
With some minor modification to Duet it's even possible to remove the
470k limit Duet suffers from, by moving the data chunk to >1MB.

Interaction with BIOS seems to be restricted to expecting the right
tables (ACPI, MP table, SMBIOS stuff), which coreboot can provide.

> be able to boot UEFI OS's at this time.)  However, we thought a
> project such as OVMF was a more direct approach to achieve UEFI
> compatibility for QEMU.
With coreboot, seabios and Duet, it should be reasonably simple to
provide a single BIOS image that selects (based on nvram - ie.
configuration) which interface to provide: PCBIOS or UEFI.

If that is just as simple with OVMF, and easier to maintain, then it's
hard to argue with that.


Patrick




From stepan at coresystems.de  Sun Oct  4 00:02:59 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 04 Oct 2009 00:02:59 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC60037.6000001@codemonkey.ws>	
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>	
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>	
	<4AC67326.6080603@gmx.net>	
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>	
	<4AC6872E.6060103@gmx.net>	
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>	
	<20091003173006.595.qmail@stuge.se>
	<2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
Message-ID: <4AC7CA13.1090007@coresystems.de>

Jordan Justen wrote:
> On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
>   
>> Jordan Justen wrote:
>>     
>>> Anyway, it sounds like a useful project might be to develop a UEFI
>>> coreboot payload based on the tianocore.org code.
>>>       
>> I believe it might have been done already.
>>
>> http://www.coreboot.org/File:Tianocoreboot.png
>>     
>
> That screenshot mentions DUET which is the tianocore.org UEFI emulator
> that boots on top of a legacy BIOS.  But, it's unclear if it was just
> DUET, or something based modified specifically for coreboot based on
> DUET.
>
> I will not dispute that DUET might be a potential solution to achieve
> UEFI compatibility for QEMU.  (I'm not sure, but I think DUET may not
> be able to boot UEFI OS's at this time.)  However, we thought a
> project such as OVMF was a more direct approach to achieve UEFI
> compatibility for QEMU.
>   

We have DUET running as a coreboot payload with a small coreboot
specific PE payload loader.

DUET is, however, not an emulator, it is executing much of the same code
as all other TianoCore based UEFI implementations.

It is possible to boot an OS just fine with DUET.

Can you explain what you think would be more direct about OVMF than
about DUET? As far as I understand it's another build target of EDK2 but
besides that shares exactly the same design and even 99% of the code.

Stefan


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From jljusten at gmail.com  Sun Oct  4 00:13:08 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Sat, 3 Oct 2009 15:13:08 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
Message-ID: <2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>

On Sat, Oct 3, 2009 at 10:40, ron minnich <rminnich at gmail.com> wrote:
> I use qemu for a lot of coreboot work. I really depend on qemu for
> many things I do, not just coreboot related. The qemu target in
> coreboot has been very heavily used by us to test out new ideas.
>
> That said, I don't see a compelling need to augment seabios with
> coreboot on qemu *in the standard distribution*. If seabios gets the
> job done, and gets OSes booted, I think that's sufficient. I don't see
> a need to complicate anyone's life with something that is, after all,
> a sideshow for qemu users.
>
> Conversely, I don't see the need to add the huge pile of stuff that
> comes with UEFI/OVMF/whatever to qemu either. One might argue that

This is a valid argument right now.  OS X is the only OS today that
targets UEFI, and specifically not legacy BIOS.  But, in 5 ~ 10 years
that might not be the case.

I'll admit that this is a fairly dumb argument to make while we are
talking about a QEMU release only a few months from now.  But, as UEFI
seems to be gaining ground in the industry, I think the sooner QEMU
can get this support, the better.

We're specifically trying to help out with this with OVMF.  But if a
better solution is developed, then so be it.

> having any BIOS callbacks in the OS is a huge mistake, and certainly
> I've learned in practice that this argument is true.

I'm not going to take a side on this matter.  But, I think what will
be more important is what is used in the majority of OS's and systems.
 This is why we still put the 16-bit legacy BIOS as the #1 priority
after ~30 years.  But, like I mention, I think there are signs that
this may shift towards UEFI at some point.

-Jordan



From patrick at georgi-clan.de  Sun Oct  4 00:19:07 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 00:19:07 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
Message-ID: <1254608347.12717.12.camel@tetris>

Am Samstag, den 03.10.2009, 15:13 -0700 schrieb Jordan Justen:
> I'll admit that this is a fairly dumb argument to make while we are
> talking about a QEMU release only a few months from now.  But, as UEFI
> seems to be gaining ground in the industry, I think the sooner QEMU
> can get this support, the better.
This smells like self-fulfulling prophecy: Let QEmu support EFI in the
hope that EFI actually gains ground (for example by better testability
due to available emulation environments)

So you want QEmu as a marketing device - nothing wrong with saying that,
right?


Regards,
Patrick




From jljusten at gmail.com  Sun Oct  4 00:40:38 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Sat, 3 Oct 2009 15:40:38 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC7CA13.1090007@coresystems.de>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC64A5C.6010003@gmx.net>
	<4AC64C32.4020509@codemonkey.ws> <4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
	<20091003173006.595.qmail@stuge.se>
	<2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
	<4AC7CA13.1090007@coresystems.de>
Message-ID: <2a50f7880910031540p12bcacbajc53fe2831ec6f929@mail.gmail.com>

On Sat, Oct 3, 2009 at 15:02, Stefan Reinauer <stepan at coresystems.de> wrote:
> Jordan Justen wrote:
>> On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
>>
>>> Jordan Justen wrote:
>>>
>>>> Anyway, it sounds like a useful project might be to develop a UEFI
>>>> coreboot payload based on the tianocore.org code.
>>>>
>>> I believe it might have been done already.
>>>
>>> http://www.coreboot.org/File:Tianocoreboot.png
>>>
>>
>> That screenshot mentions DUET which is the tianocore.org UEFI emulator
>> that boots on top of a legacy BIOS. ?But, it's unclear if it was just
>> DUET, or something based modified specifically for coreboot based on
>> DUET.
>>
>> I will not dispute that DUET might be a potential solution to achieve
>> UEFI compatibility for QEMU. ?(I'm not sure, but I think DUET may not
>> be able to boot UEFI OS's at this time.) ?However, we thought a
>> project such as OVMF was a more direct approach to achieve UEFI
>> compatibility for QEMU.
>>
>
> We have DUET running as a coreboot payload with a small coreboot
> specific PE payload loader.

Meaning you bring up a legacy BIOS compatible interface before
starting DUET?  DUET depends on a legacy BIOS.  My point is that a
tianocore.org based coreboot payload ought be able to do away with
this legacy BIOS dependency.

> DUET is, however, not an emulator, it is executing much of the same code
> as all other TianoCore based UEFI implementations.

According to the ReadMe.txt for our edk2 DuetPkg, DUET stands for
Developer's UEFI Emulation.  (Seems a bit of a stretch as an acronym.
:)  But, 'emulation' is a very squishy word at times, and this doesn't
imply that it can't accomplish a lot in terms of UEFI compatibility.

> It is possible to boot an OS just fine with DUET.
>
> Can you explain what you think would be more direct about OVMF than
> about DUET? As far as I understand it's another build target of EDK2 but
> besides that shares exactly the same design and even 99% of the code.

DUET expects that you boot a legacy BIOS, and then you load DUET off
the disk.  Once DUET is loaded, there is a (mostly) UEFI compatible
environment.

OVMF initializes the VM hardware and at the same time brings up the
(mostly) UEFI compatible environment.  This is basically the same
thing that would normally be done in most UEFI compatible systems.  To
me, this is a more direct approach to UEFI compatibility for QEMU.

Both DUET and OVMF have some slight issues with providing a fully
compatible UEFI variable interface.  But I know OVMF can still boot a
UEFI OS, and I thought DUET might have a problem in this area.  But, I
was fairly sure this could have been fixed in DUET, and it appears
that perhaps it has been.

Yes, DUET and OVMF likely share 90+% of the same code.

-Jordan



From stepan at coresystems.de  Sun Oct  4 00:46:28 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 04 Oct 2009 00:46:28 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
References: <4AC4A487.1050003@us.ibm.com>	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>	<4AC60037.6000001@codemonkey.ws>	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>	<4AC64A5C.6010003@gmx.net>
	<4AC64C32.4020509@codemonkey.ws>	<4AC67326.6080603@gmx.net>
	<20091003150803.GF17326@redhat.com>	<20091003173252.1061.qmail@stuge.se>	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
Message-ID: <4AC7D444.9050007@coresystems.de>

Jordan Justen wrote:
> I'm not going to take a side on this matter.  But, I think what will
> be more important is what is used in the majority of OS's and systems.
>  This is why we still put the 16-bit legacy BIOS as the #1 priority
> after ~30 years.  But, like I mention, I think there are signs that
> this may shift towards UEFI at some point.
>   
Looking at today's OSes, the BIOS "interface" is basically completely
unused except for loading the OS kernel.
For future generations of firmware and computers and virtual machines it
might make sense to optimize with that situation in mind.

The industry we're working in does not see UEFI can cope with the
problems firmware has today, unfortunately. After seeing EFI fail so
badly with the Itanium it would certainly be nice to see if something
can evolve from it in a decade, or two. We're watching excitedly.

All the best,
Stefan




From tsylla at gmail.com  Sun Oct  4 01:01:19 2009
From: tsylla at gmail.com (Tom Sylla)
Date: Sat, 03 Oct 2009 19:01:19 -0400
Subject: [coreboot] fallback/normal support [PATCH]Remove non-CBFS
In-Reply-To: <20091003190538.16733.qmail@stuge.se>
References: <4AC3E2F3.6060509@coresystems.de>	<13426df10909301607v23a25dadsfa51001cdb729229@mail.gmail.com>	<1254380991.21870.21.camel@tetris>	<20091001235825.GA29687@morn.localdomain>	<4AC5CDCB.7080901@georgi-clan.de>
	<4AC5D02F.4040305@gmx.net>	<20091003163417.23369.qmail@stuge.se>	<4AC78B56.2040304@gmx.net>
	<20091003180325.6108.qmail@stuge.se>	<1254595872.3224.30.camel@tetris>
	<20091003190538.16733.qmail@stuge.se>
Message-ID: <4AC7D7BF.5040402@gmail.com>

Peter Stuge wrote:
> Patrick Georgi wrote:
>> What I don't know is, do we require any chipset setup to _reach_
>> CMOS?
> 
> It's not generally in the CPU, so some setup may be needed. On the
> other hand, maybe 70/71 are decoded correctly on power up, just like
> flash access?

It's not like there is a spec or anything, but most of the PC AT junk in 
IO space will be accessible from first fetch. Disassemble the early 
portions of some AMI or Phoenix BIOSes, and you'll see accesses to 
things like CMOS in the first few instructions. Legacy accesses have to 
die somewhere subtractively, and the RTC usually is in that path.


Tom



From stepan at coresystems.de  Sun Oct  4 01:03:07 2009
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sun, 04 Oct 2009 01:03:07 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <2a50f7880910031540p12bcacbajc53fe2831ec6f929@mail.gmail.com>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC64A5C.6010003@gmx.net>	
	<4AC64C32.4020509@codemonkey.ws> <4AC67326.6080603@gmx.net>	
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>	
	<4AC6872E.6060103@gmx.net>	
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>	
	<20091003173006.595.qmail@stuge.se>	
	<2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>	
	<4AC7CA13.1090007@coresystems.de>
	<2a50f7880910031540p12bcacbajc53fe2831ec6f929@mail.gmail.com>
Message-ID: <4AC7D82B.9030405@coresystems.de>

Jordan Justen wrote:
> On Sat, Oct 3, 2009 at 15:02, Stefan Reinauer <stepan at coresystems.de> wrote:
>   
>> Jordan Justen wrote:
>>     
>>> On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
>>>
>>>       
>>>> Jordan Justen wrote:
>>>>
>>>>         
>>>>> Anyway, it sounds like a useful project might be to develop a UEFI
>>>>> coreboot payload based on the tianocore.org code.
>>>>>
>>>>>           
>>>> I believe it might have been done already.
>>>>
>>>> http://www.coreboot.org/File:Tianocoreboot.png
>>>>
>>>>         
>>> That screenshot mentions DUET which is the tianocore.org UEFI emulator
>>> that boots on top of a legacy BIOS.  But, it's unclear if it was just
>>> DUET, or something based modified specifically for coreboot based on
>>> DUET.
>>>
>>> I will not dispute that DUET might be a potential solution to achieve
>>> UEFI compatibility for QEMU.  (I'm not sure, but I think DUET may not
>>> be able to boot UEFI OS's at this time.)  However, we thought a
>>> project such as OVMF was a more direct approach to achieve UEFI
>>> compatibility for QEMU.
>>>
>>>       
>> We have DUET running as a coreboot payload with a small coreboot
>> specific PE payload loader.
>>     
>
> Meaning you bring up a legacy BIOS compatible interface before
> starting DUET? 
No.
>  DUET depends on a legacy BIOS.  
It did not for us, except for the loader which was replaced. We might
have been lucky though...

> My point is that a tianocore.org based coreboot payload ought be able to do away with
> this legacy BIOS dependency.
>   
Absolutely agreed.


At some point it might make sense to have a coreboot specific target
next to OVMF and DUET, some corebootPkg with specific adaptions and the
loader integrated.

The requirements for a coreboot target are very similar to those of OVMF
and/or Duet, I guess. No hardware specific code is required, but in
addition to what OVMF provides, we feature an in-flash filesystem and we
export a coreboot table which contains memory information, cmos layout
among other things...

What are the chances to get something like this integrated upstream
TianoCore.org?

>> Can you explain what you think would be more direct about OVMF than
>> about DUET? As far as I understand it's another build target of EDK2 but
>> besides that shares exactly the same design and even 99% of the code.
>>     
>
> DUET expects that you boot a legacy BIOS, and then you load DUET off
> the disk. 
It does expect a few tables, but does not seem to make any 16bit calls
once loaded.
>  Once DUET is loaded, there is a (mostly) UEFI compatible
> environment.
>   
I'm curious on the "mostly" here... what's missing? We certainly want to
make sure what we do is fully UEFI compatible.
> Both DUET and OVMF have some slight issues with providing a fully
> compatible UEFI variable interface. 
Is that about saving settings in an NVRAM/flash memory?



Stefan




From jljusten at gmail.com  Sun Oct  4 01:04:47 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Sat, 3 Oct 2009 16:04:47 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <1254608347.12717.12.camel@tetris>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
	<1254608347.12717.12.camel@tetris>
Message-ID: <2a50f7880910031604y14c9dde1mc350d42d93ff1c9d@mail.gmail.com>

On Sat, Oct 3, 2009 at 15:19, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am Samstag, den 03.10.2009, 15:13 -0700 schrieb Jordan Justen:
>> I'll admit that this is a fairly dumb argument to make while we are
>> talking about a QEMU release only a few months from now. ?But, as UEFI
>> seems to be gaining ground in the industry, I think the sooner QEMU
>> can get this support, the better.
> This smells like self-fulfulling prophecy: Let QEmu support EFI in the
> hope that EFI actually gains ground (for example by better testability
> due to available emulation environments)
>
> So you want QEmu as a marketing device - nothing wrong with saying that,
> right?

I'm not in marketing. :)  But, I do work for Intel, on tianocore.org
and thus UEFI.  I've been working with Tiano/EFI since ~2003, when
Intel started converting its desktop motherboards over to a Tiano code
base.  So yes, I have a bias.

I think (but no, I cannot back this up) that tens of millions of UEFI
compatible motherboards are shipping out each year now.  Microsoft has
implemented UEFI support in Vista and Win7.  Several Linux vendor have
or are enabling UEFI support now.  Mac OS X implements UEFI.

My point?  Well, while I think QEMU support for UEFI is still valuable
to help support UEFI adoption, I think it could have done a lot more
for UEFI if it was done several years ago. :)

On the flip side, I also think it could have done a lot more to assist
Linux to have first rate UEFI support now if it was done several years
ago. :(

-Jordan



From jljusten at gmail.com  Sun Oct  4 01:52:11 2009
From: jljusten at gmail.com (Jordan Justen)
Date: Sat, 3 Oct 2009 16:52:11 -0700
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <4AC7D82B.9030405@coresystems.de>
References: <4AC51DBA.7020609@codemonkey.ws> <4AC67326.6080603@gmx.net>
	<2a50f7880910021528v742c39e8sd334b318c577fb71@mail.gmail.com>
	<4AC6872E.6060103@gmx.net>
	<2a50f7880910021732k68ae1a97qc7307ac52a225371@mail.gmail.com>
	<20091003173006.595.qmail@stuge.se>
	<2a50f7880910031449k13090dcdr8440d89ccb7fcfe9@mail.gmail.com>
	<4AC7CA13.1090007@coresystems.de>
	<2a50f7880910031540p12bcacbajc53fe2831ec6f929@mail.gmail.com>
	<4AC7D82B.9030405@coresystems.de>
Message-ID: <2a50f7880910031652u5837f7cdx85686eddd2050f8@mail.gmail.com>

On Sat, Oct 3, 2009 at 16:03, Stefan Reinauer <stepan at coresystems.de> wrote:
> Jordan Justen wrote:
>> On Sat, Oct 3, 2009 at 15:02, Stefan Reinauer <stepan at coresystems.de> wrote:
>>
>>> Jordan Justen wrote:
>>>
>>>> On Sat, Oct 3, 2009 at 10:30, Peter Stuge <peter at stuge.se> wrote:
>>>>
>>>>
>>>>> Jordan Justen wrote:
>>>>>
>>>>>
>>>>>> Anyway, it sounds like a useful project might be to develop a UEFI
>>>>>> coreboot payload based on the tianocore.org code.
>>>>>>
>>>>>>
>>>>> I believe it might have been done already.
>>>>>
>>>>> http://www.coreboot.org/File:Tianocoreboot.png
>>>>>
>>>>>
>>>> That screenshot mentions DUET which is the tianocore.org UEFI emulator
>>>> that boots on top of a legacy BIOS. ?But, it's unclear if it was just
>>>> DUET, or something based modified specifically for coreboot based on
>>>> DUET.
>>>>
>>>> I will not dispute that DUET might be a potential solution to achieve
>>>> UEFI compatibility for QEMU. ?(I'm not sure, but I think DUET may not
>>>> be able to boot UEFI OS's at this time.) ?However, we thought a
>>>> project such as OVMF was a more direct approach to achieve UEFI
>>>> compatibility for QEMU.
>>>>
>>>>
>>> We have DUET running as a coreboot payload with a small coreboot
>>> specific PE payload loader.
>>>
>>
>> Meaning you bring up a legacy BIOS compatible interface before
>> starting DUET?
> No.
>> ?DUET depends on a legacy BIOS.
> It did not for us, except for the loader which was replaced. We might
> have been lucky though...
>
>> My point is that a tianocore.org based coreboot payload ought be able to do away with
>> this legacy BIOS dependency.
>>
> Absolutely agreed.
>
>
> At some point it might make sense to have a coreboot specific target
> next to OVMF and DUET, some corebootPkg with specific adaptions and the
> loader integrated.
>LegacyBiosInt86
> The requirements for a coreboot target are very similar to those of OVMF
> and/or Duet, I guess. No hardware specific code is required, but in
> addition to what OVMF provides, we feature an in-flash filesystem and we
> export a coreboot table which contains memory information, cmos layout
> among other things...
>
> What are the chances to get something like this integrated upstream
> TianoCore.org?

I'll refrain from making a prediction on this.  But, by my view,
tianocore.org is supposed to be an open source community that
encourages UEFI related contributions.

However, (at this time) it is going to tougher to get it included at
tianocore.org if it is not BSD licensed.  I would also suggest
discussing the situation on the tianocore.org email lists beforehand
to get somewhat of a confirmation before investing a lot into it.

>>> Can you explain what you think would be more direct about OVMF than
>>> about DUET? As far as I understand it's another build target of EDK2 but
>>> besides that shares exactly the same design and even 99% of the code.
>>>
>>
>> DUET expects that you boot a legacy BIOS, and then you load DUET off
>> the disk.
> It does expect a few tables, but does not seem to make any 16bit calls
> once loaded.
>> ?Once DUET is loaded, there is a (mostly) UEFI compatible
>> environment.
>>
> I'm curious on the "mostly" here... what's missing? We certainly want to
> make sure what we do is fully UEFI compatible.

I think tianocore.org will not call these fully UEFI compatible
projects, since that implies a lot.  Normally these platforms are not
run through the UEFI Self-Certification Tests, for example.
(Although, this is something I plan to try on OVMF at some point.)

Also, there is the variable situation.  (see below)

>> Both DUET and OVMF have some slight issues with providing a fully
>> compatible UEFI variable interface.
> Is that about saving settings in an NVRAM/flash memory?

Yes.  Neither platform provides proper UEFI NV variables support.  The
NV variables can be lost depending on when the platform is shut off,
and when the variable has been written to.

But in addition, for DUET, I thought that accessing the NV variable
services at OS runtime might not work correctly.  (Perhaps cause an
exception.  Perhaps just always return an error.)

-Jordan



From patrick at georgi-clan.de  Sun Oct  4 13:12:58 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 13:12:58 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 1
Message-ID: <1254654778.4077.13.camel@tetris>

Hi,

attached patch removes a bit of pre-cbfs build system infrastructure.
Payloads are compressed by cbfstool itself, no need for external tools.


Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From c-d.hailfinger.devel.2006 at gmx.net  Sun Oct  4 13:16:04 2009
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 04 Oct 2009 13:16:04 +0200
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <BEEB3748-A576-4369-BFFE-312AAC38F80F@claunia.com>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
	<1254608347.12717.12.camel@tetris>
	<BEEB3748-A576-4369-BFFE-312AAC38F80F@claunia.com>
Message-ID: <4AC883F4.6050607@gmx.net>

Hi Natalia,

I tried to understand your points. Please correct me where I'm wrong.

On 04.10.2009 06:10, Natalia Portillo wrote:
> EFI actually DOES HAVE ground.
>
> Itanium machines are still worldwide used, manufactured and sold.

Unless I'm mistaken, Itanium is not x86. Now if we consider EFI for x86
because it has solid standing on Itanium, shouldn't we also consider
U-Boot and OpenFirmware for x86 because they have solid standing on
ARM/PowerPC?


> Intel-based Macintoshes used them and ALL of their facilities.

True.


> The disadvantages can be a lot.
> The advantages that I see, are the following (implemented by Apple's
> EFI):
> Hardware drivers, so the OS loader can use ANY hardware present.

Same for BIOS.


> Hardware testing easily programable, as you can use the EFI to call
> the hardware (unlike PC diagnostics that makes direct and real mode
> calls to the hardware, making them imposible to test different
> hardware without implementing all variations -SCSI cards, wifi cards,
> so on-)

Same for BIOS (the only difference is that the interface to the BIOS
provides a 16bit interface and EFI provides a 32bit interface).


> Filesystem independent bootloader (it just expects the EFI to have the
> filesystem and disk driver, then searches the disk for the OS loader)

Burn a BIOS together with DOS in the ROM and you get the same
functionality. I have seen youtube videos of such systems.


> Upgradable drivers without firmware patching (so if I add a wifi card,
> I can put a driver for netbooting it)

Install DOS with a boot agent on the disk and you get exactly the same
feature.


> Extensive input devices support (USB keyb and mice, bluetooth keyb and
> mice and infrared remote)

AFAIK USB keyboard+mouse is supported in pretty much every BIOS out
there. Not sure about bluetooth keyboard and infrared remote, but the
boards with builtin bluetooth support probably also have a bluetooth
keyboard driver in the BIOS.


> I think that this is impossible (if not nearly to) make using BIOS. I
> think it is only possible with OpenFirmware or EFI. 

Except for bluetooth keyboard and infrared remote which I'm not sure
about, everything you listed above is the same for BIOS and EFI.

> And I prefer EFI for the matters of being programable in C (personal
> distaste for Forth)

Now the Forth argument is something I can agree with. ;-)


> and the EFI System Partition usability.

I don't understand what an EFI System Partition is used for. The
wikipedia entry suggests that it is essentially a special partition
where bootloaders live (instead of using a normal partition for that)
and where EFI loads drivers and DOS/Windows PE commandline executables
from. That sounds suspiciously like a DOS partition with NTLDR and loadlin.


> A bootloader can fuckinly easy put a good splash without limiting to
> 12 colors or making calls to the VGA system (for example). What will
> happen with the GRUB if tomorrow VGA disappears? What a mess...

I've seen quite a few GRUB installations with 24-bit color splash
screens in high resolutions. Graphics hardware won't disappear from
computers any time soon, only the interfaces may change.


> And I don't work for Intel, IBM, HP, Apple, etc.
>
> In QEMU' side I see that maybe not for 0.12.0 but anyway, EFI is a
> MUST have if we want to emulate, support, test, patch, anything that
> uses it, starting with Itanium, continuing with Intel Macintosh, and
> finishing with all the thousands of PCs (not only from Intel, as I've
> seen a bunch from Asus and Asrock) that instead of using a BIOS are
> using a hidden EFI with a boot-by-default CSM.

Interesting. Do these boards still have a 20-30 second wait time from
poweron to bootloader? I've seen coreboot+SeaBIOS achieve 1 second from
poweron to bootloader on real x86 hardware, so I always wonder what the
commercial BIOSes do during the time we wait for them.


> I'm sure, EFI will prevail over BIOS and sooner or later, also over
> OpenFirmware.

I'm not so sure about that. EFI is "cool", but so were Linux netbooks
and nowadays people buy mostly Windows netbooks.


> And we need to move with the world, not against it.

Fully agreed.


Many years ago, some EFI proponent told me: "EFI is great. It is a
32-bit BIOS with builtin 32-bit DOS. Now every operating system can use
EFI drivers in compatibility mode like Windows 95 used DOS drivers in
compatibility mode."
That statement had a lasting impression on me and I've yet to see any
explanation why that statement would be incorrect. I'm very willing to
learn, so if I got something wrong, please educate me.


Regards,
Carl-Daniel



From claunia at claunia.com  Sun Oct  4 06:10:00 2009
From: claunia at claunia.com (Natalia Portillo)
Date: Sun, 4 Oct 2009 05:10:00 +0100
Subject: [coreboot] [Qemu-devel] Release plan for 0.12.0
In-Reply-To: <1254608347.12717.12.camel@tetris>
References: <4AC4A487.1050003@us.ibm.com>
	<2a50f7880910011741k65ac8dfbq2fc8c9f58f5fa8d9@mail.gmail.com>
	<4AC60037.6000001@codemonkey.ws>
	<2a50f7880910020958g3fe5eadehe5e5094c05b218d9@mail.gmail.com>
	<4AC64A5C.6010003@gmx.net> <4AC64C32.4020509@codemonkey.ws>
	<4AC67326.6080603@gmx.net> <20091003150803.GF17326@redhat.com>
	<20091003173252.1061.qmail@stuge.se>
	<13426df10910031040y5029dc31m8c6ca4a4bac098a6@mail.gmail.com>
	<2a50f7880910031513u713f7d52xc95847e9b248964b@mail.gmail.com>
	<1254608347.12717.12.camel@tetris>
Message-ID: <BEEB3748-A576-4369-BFFE-312AAC38F80F@claunia.com>

I don't think that's the case.

EFI actually DOES HAVE ground.

Itanium machines are still worldwide used, manufactured and sold.
Intel-based Macintoshes used them and ALL of their facilities.

The disadvantages can be a lot.
The advantages that I see, are the following (implemented by Apple's  
EFI):
Hardware drivers, so the OS loader can use ANY hardware present.
Hardware testing easily programable, as you can use the EFI to call  
the hardware (unlike PC diagnostics that makes direct and real mode  
calls to the hardware, making them imposible to test different  
hardware without implementing all variations -SCSI cards, wifi cards,  
so on-)
Filesystem independent bootloader (it just expects the EFI to have the  
filesystem and disk driver, then searches the disk for the OS loader)
Upgradable drivers without firmware patching (so if I add a wifi card,  
I can put a driver for netbooting it)
Extensive input devices support (USB keyb and mice, bluetooth keyb and  
mice and infrared remote)

I think that this is impossible (if not nearly to) make using BIOS.
I think it is only possible with OpenFirmware or EFI.

And I prefer EFI for the matters of being programable in C (personal  
distaste for Forth) and the EFI System Partition usability.

A bootloader can fuckinly easy put a good splash without limiting to  
12 colors or making calls to the VGA system (for example). What will  
happen with the GRUB if tomorrow VGA disappears? What a mess...

And I don't work for Intel, IBM, HP, Apple, etc.

In QEMU' side I see that maybe not for 0.12.0 but anyway, EFI is a  
MUST have if we want to emulate, support, test, patch, anything that  
uses it, starting with Itanium, continuing with Intel Macintosh, and  
finishing with all the thousands of PCs (not only from Intel, as I've  
seen a bunch from Asus and Asrock) that instead of using a BIOS are  
using a hidden EFI with a boot-by-default CSM.

I'm sure, EFI will prevail over BIOS and sooner or later, also over  
OpenFirmware.
And we need to move with the world, not against it.

Regards,
Natalia Portillo

El 03/10/2009, a las 23:19, Patrick Georgi escribi?:

> Am Samstag, den 03.10.2009, 15:13 -0700 schrieb Jordan Justen:
>> I'll admit that this is a fairly dumb argument to make while we are
>> talking about a QEMU release only a few months from now.  But, as  
>> UEFI
>> seems to be gaining ground in the industry, I think the sooner QEMU
>> can get this support, the better.
> This smells like self-fulfulling prophecy: Let QEmu support EFI in the
> hope that EFI actually gains ground (for example by better testability
> due to available emulation environments)
>
> So you want QEmu as a marketing device - nothing wrong with saying  
> that,
> right?
>
>
> Regards,
> Patrick
>
>
>
>




From patrick at georgi-clan.de  Sun Oct  4 14:18:01 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 14:18:01 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 2
Message-ID: <1254658681.4077.15.camel@tetris>

Hi,

This removes the uses of the buildrom utility and the coreboot.strip
intermediate file.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From peter at stuge.se  Sun Oct  4 14:21:10 2009
From: peter at stuge.se (Peter Stuge)
Date: Sun, 4 Oct 2009 14:21:10 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 1
In-Reply-To: <1254654778.4077.13.camel@tetris>
References: <1254654778.4077.13.camel@tetris>
Message-ID: <20091004122110.5029.qmail@stuge.se>

Patrick Georgi wrote:
> attached patch removes a bit of pre-cbfs build system infrastructure.
> Payloads are compressed by cbfstool itself, no need for external tools.
> 
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From peter at stuge.se  Sun Oct  4 14:23:24 2009
From: peter at stuge.se (Peter Stuge)
Date: Sun, 4 Oct 2009 14:23:24 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 2
In-Reply-To: <1254658681.4077.15.camel@tetris>
References: <1254658681.4077.15.camel@tetris>
Message-ID: <20091004122324.5378.qmail@stuge.se>

Patrick Georgi wrote:
> This removes the uses of the buildrom utility and the coreboot.strip
> intermediate file.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Sun Oct  4 14:27:48 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  4 Oct 2009 14:27:48 +0200
Subject: [coreboot] [v2] r4717 - trunk/coreboot-v2/src/arch/i386
Message-ID: <mailman.3788.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-04 14:27:48 +0200 (Sun, 04 Oct 2009)
New Revision: 4717

Modified:
   trunk/coreboot-v2/src/arch/i386/Config.lb
Log:
Remove a bit of pre-cbfs build system infrastructure.
Payloads are compressed by cbfstool itself, no need for external tools.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-03 21:13:36 UTC (rev 4716)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-04 12:27:48 UTC (rev 4717)
@@ -41,36 +41,6 @@
 	action	"$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
 end
 
-makerule payload
-	depends "$(PAYLOAD)"
-	action  "cp $< $@"
-end
-
-makerule payload.nrv2b
-	depends "$(PAYLOAD) nrv2b"
-	action  "./nrv2b e $(PAYLOAD) $@"
-end
-
-# unlike nrv2b, lzma is a huge build mess. If they want lzma, they have to have built it
-makerule payload.lzma
-	depends "$(PAYLOAD) "
-	action  "lzma -zc $(PAYLOAD) > $@ || lzma e $(PAYLOAD) $@"
-end
-
-
-# this one example shows the mess that has occurred. People are now mixing
-# conditional if in the make style with if in the config language style. 
-# The -1 is linux standard. 
-# I don't much like it but it is the mode nowadays. So coreboot will change
-# what a mess. -- RGM
-# catch the case where there is no compression
-makedefine PAYLOAD-1:=payload
-
-# catch the case where there is precompression. Yes, this bites. 
-if CONFIG_PRECOMPRESSED_PAYLOAD 
-	makedefine PAYLOAD-1:=payload
-end
-
 if CONFIG_USE_FAILOVER_IMAGE
 	makedefine COREBOOT_APC:=
 	makedefine COREBOOT_RAM_ROM:=
@@ -81,9 +51,8 @@
 	end
 else
 	makerule coreboot.rom 
-		depends	"coreboot.strip buildrom $(PAYLOAD-1)"
-		action "touch cbfs-support; ./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
-		action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 ]; then echo l > cbfs-support; fi"
+		depends	"coreboot.strip buildrom"
+		action "./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
 	end
 end
 




From svn at coreboot.org  Sun Oct  4 14:30:45 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  4 Oct 2009 14:30:45 +0200
Subject: [coreboot] [v2] r4718 - in trunk/coreboot-v2: src/arch/i386
	src/arch/ppc src/config util
Message-ID: <mailman.3789.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-04 14:30:44 +0200 (Sun, 04 Oct 2009)
New Revision: 4718

Removed:
   trunk/coreboot-v2/util/buildrom/
Modified:
   trunk/coreboot-v2/src/arch/i386/Config.lb
   trunk/coreboot-v2/src/arch/ppc/Config.lb
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/src/config/coreboot_ram.ld
Log:
This removes the uses of the buildrom utility and the coreboot.strip
intermediate file.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-04 12:27:48 UTC (rev 4717)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb	2009-10-04 12:30:44 UTC (rev 4718)
@@ -44,16 +44,6 @@
 if CONFIG_USE_FAILOVER_IMAGE
 	makedefine COREBOOT_APC:=
 	makedefine COREBOOT_RAM_ROM:=
-
-	makerule coreboot.rom 
-		depends	"coreboot.strip" 
-		action "cp $< $@"
-	end
-else
-	makerule coreboot.rom 
-		depends	"coreboot.strip buildrom"
-		action "./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)"
-	end
 end
 
 makerule crt0.S

Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-10-04 12:27:48 UTC (rev 4717)
+++ trunk/coreboot-v2/src/arch/ppc/Config.lb	2009-10-04 12:30:44 UTC (rev 4718)
@@ -1,12 +1,7 @@
 ldscript init/ldscript.lb
 
-makerule coreboot.strip 
-	depends	"coreboot" 
-	action	"cp $< $@"
-end
-
 makerule coreboot.rom 
-	depends	"coreboot.strip" 
+	depends	"coreboot"
 	action "cp $< $@"
 end
 

Modified: trunk/coreboot-v2/src/config/Config.lb
===================================================================
--- trunk/coreboot-v2/src/config/Config.lb	2009-10-04 12:27:48 UTC (rev 4717)
+++ trunk/coreboot-v2/src/config/Config.lb	2009-10-04 12:30:44 UTC (rev 4718)
@@ -33,9 +33,9 @@
 #	action	"perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
 #end
 
-makerule coreboot.strip  
+makerule coreboot.rom
 	depends	"coreboot" 
-	action	"$(CONFIG_OBJCOPY) -O binary coreboot coreboot.strip"
+	action	"$(CONFIG_OBJCOPY) -O binary coreboot coreboot.rom"
 end
 
 makerule coreboot.a
@@ -133,12 +133,6 @@
 	action 	"$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"	
 end
 
-# the buildrom tool
-makerule buildrom 
-	depends	"$(TOP)/util/buildrom/buildrom.c" 
-	action	"$(HOSTCC) -o $@ $<"
-end
-
 # Force crt0.s (which has build time version code in it to rebuild every time)
 makedefine .PHONY : crt0.s
 makerule crt0.s   
@@ -204,7 +198,7 @@
 	action	"rm -f ldscript.ld"
 	action	"rm -f a.out *.s *.l *.o *.E *.inc"
 	action	"rm -f TAGS tags romcc*"
-	action	"rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
+	action	"rm -f docipl chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
 	action	"rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm"
 	action	"rm -f smm smm.elf smm.map smm_bin.c"
 	action	"rm -f dsdt.aml dsdt.c"

Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld
===================================================================
--- trunk/coreboot-v2/src/config/coreboot_ram.ld	2009-10-04 12:27:48 UTC (rev 4717)
+++ trunk/coreboot-v2/src/config/coreboot_ram.ld	2009-10-04 12:30:44 UTC (rev 4718)
@@ -57,7 +57,7 @@
 		/*
 		 * kevinh/Ispiri - Added an align, because the objcopy tool
 		 * incorrectly converts sections that are not long word aligned.
-		 * This breaks the coreboot.strip target.
+		 * This breaks the coreboot.rom target.
 		 */
 		 . = ALIGN(4);
 




From patrick at georgi-clan.de  Sun Oct  4 15:45:12 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 15:45:12 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 3
Message-ID: <1254663912.4077.20.camel@tetris>

Hi,

this patch does away with CONFIG_ROM_PAYLOAD_START and
CONFIG_PAYLOAD_SIZE. Both were only really used in pre-cbfs, as the
payload's size isn't relevant for the build process anymore.

abuild is happily chugging along, but it isn't runtime tested. esp.
failover boards are affected by this, so if someone with a board
configured for failover could test this, and report back (basically: do
both fallback and normal still work?), I'd be grateful.

Various calculations in {no,}failovercalculation.lb are adapted
accordingly.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From peter at stuge.se  Sun Oct  4 16:24:29 2009
From: peter at stuge.se (Peter Stuge)
Date: Sun, 4 Oct 2009 16:24:29 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 3
In-Reply-To: <1254663912.4077.20.camel@tetris>
References: <1254663912.4077.20.camel@tetris>
Message-ID: <20091004142429.29875.qmail@stuge.se>

Patrick Georgi wrote:
> this patch does away with CONFIG_ROM_PAYLOAD_START and
> CONFIG_PAYLOAD_SIZE. Both were only really used in pre-cbfs, as the
> payload's size isn't relevant for the build process anymore.
> 
> abuild is happily chugging along, but it isn't runtime tested. esp.
> failover boards are affected by this, so if someone with a board
> configured for failover could test this, and report back (basically: do
> both fallback and normal still work?), I'd be grateful.
> 
> Various calculations in {no,}failovercalculation.lb are adapted
> accordingly.
> 
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>

Might be wise to wait for some testing, but I really like this!


>  uses CONFIG_ROM_IMAGE_SIZE
>  uses CONFIG_ROM_SECTION_SIZE
>  uses CONFIG_ROM_SECTION_OFFSET

What about these ones? They are also affected by cbfs, right?


> +++ src/mainboard/intel/xe7501devkit/Options.lb	(Arbeitskopie)
> @@ -47,8 +47,6 @@
>  uses CONFIG_IDE
>  
>  ## The default definitions are used for these
> -uses CONFIG_ROM_PAYLOAD_START
> -uses CONFIG_PAYLOAD_SIZE
>  
>  ## These are defined in target Config.lb, don't add here
>  uses CONFIG_USE_FALLBACK_IMAGE

Please delete the comment and a blank line too.


> Index: src/arch/i386/lib/failover_failover.lds
> ===================================================================
> --- src/arch/i386/lib/failover_failover.lds	(Revision 4716)
> +++ src/arch/i386/lib/failover_failover.lds	(Arbeitskopie)
> @@ -1,2 +1,2 @@
> -	__fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
> -	__normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;
> +	__fallback_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;
> +	__normal_image = ((CONFIG_ROMBASE - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;
> Index: src/arch/i386/lib/failover.lds
> ===================================================================
> --- src/arch/i386/lib/failover.lds	(Revision 4716)
> +++ src/arch/i386/lib/failover.lds	(Arbeitskopie)
> @@ -1 +1 @@
> -	__normal_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
> +	__normal_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;

What do these files do, exactly? What is the -8 about?


//Peter



From patrick at georgi-clan.de  Sun Oct  4 16:34:59 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 16:34:59 +0200
Subject: [coreboot] [PATCH]remove pre-cbfs build system, pt. 3
In-Reply-To: <20091004142429.29875.qmail@stuge.se>
References: <1254663912.4077.20.camel@tetris>
	<20091004142429.29875.qmail@stuge.se>
Message-ID: <1254666899.4077.23.camel@tetris>

Am Sonntag, den 04.10.2009, 16:24 +0200 schrieb Peter Stuge:
> Might be wise to wait for some testing, but I really like this!
I'll wait a bit more.

> >  uses CONFIG_ROM_IMAGE_SIZE
> >  uses CONFIG_ROM_SECTION_SIZE
> >  uses CONFIG_ROM_SECTION_OFFSET
> 
> What about these ones? They are also affected by cbfs, right?
I'm not done yet :-)

> Please delete the comment and a blank line too.
Right, thanks

> > --- src/arch/i386/lib/failover.lds	(Revision 4716)
> > +++ src/arch/i386/lib/failover.lds	(Arbeitskopie)
> > @@ -1 +1 @@
> > -	__normal_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
> > +	__normal_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;
> 
> What do these files do, exactly? What is the -8 about?
They define the symbols used in linking: failover does a
jmp __normal_image
to get to normal, this one calculates the address: 8 bytes before the
start of the current image in this case, similar for the others.
reset32.{inc,lds} creates a jump instruction there, jumping to the real
start address.


Patrick




From uwe at hermann-uwe.de  Sun Oct  4 17:45:34 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Oct 2009 17:45:34 +0200
Subject: [coreboot] [PATCH] kconfig support for all GX1 boards
Message-ID: <20091004154534.GM15511@greenwood>

See patch.

Build-tested, but not yet run-time-tested on any board.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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From rminnich at gmail.com  Sun Oct  4 18:26:47 2009
From: rminnich at gmail.com (ron minnich)
Date: Sun, 4 Oct 2009 09:26:47 -0700
Subject: [coreboot] [PATCH] kconfig support for all GX1 boards
In-Reply-To: <20091004154534.GM15511@greenwood>
References: <20091004154534.GM15511@greenwood>
Message-ID: <13426df10910040926ye896544vf08872fc8bbb31de@mail.gmail.com>

===================================================================
--- src/mainboard/Makefile.romccboard.inc	(Revision 4718)
+++ src/mainboard/Makefile.romccboard.inc	(Arbeitskopie)
@@ -26,9 +26,16 @@
 crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += failover.inc
 crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+
+ifeq ($(CONFIG_CPU_AMD_GX1),y)
+crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
+crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
+crt0-y += auto.inc
+else
 crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
 crt0-y += auto.inc
 crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+endif

As you know I'd rather see this done differently but I need to put the
select MMX
in all those CPUs that support it. So I will change this later when I
can, or someone else can. Here's what it ought to look like:

+crt0-$(CONFIG_CPU_AMD_GX1) += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
+crt0-$(CONFIG_CPU_AMD_GX1) += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
 crt0-$(CONFIG_MMX) += ../../../../src/cpu/x86/mmx/enable_mmx.inc
 crt0-$(CONFIG_SSE) += ../../../../src/cpu/x86/sse/enable_sse.inc
 crt0-y += auto.inc
 crt0-$(CONFIG_SSE) += ../../../../src/cpu/x86/sse/enable_sse.inc
 crt0-$(CONFIG_MMX) += ../../../../src/cpu/x86/mmx/disable_mmx.inc

But, as said,for each CPU that supports SSE and MMX, we have to add
the right select statements.

But this is such fine work that it is:

Acked-by: Ronald G. Minnich <rminnich at gmail.com>


thanks, really nice job

ron



From svn at coreboot.org  Sun Oct  4 19:15:39 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  4 Oct 2009 19:15:39 +0200
Subject: [coreboot] [v2] r4719 - in trunk/coreboot-v2/src: . cpu/amd
	cpu/amd/model_gx1 mainboard mainboard/advantech
	mainboard/advantech/pcm-5820 mainboard/asi
	mainboard/asi/mb_5blgp mainboard/asi/mb_5blmp mainboard/axus
	mainboard/axus/tc320 mainboard/bcom mainboard/bcom/winnet100
	mainboard/eaglelion mainboard/eaglelion/5bcm mainboard/iei
	mainboard/iei/juki-511p mainboard/iei/nova4899r
	mainboard/televideo mainboard/televideo/tc7020
	northbridge/amd northbridge/amd/gx1 southbridge/amd/cs5530
Message-ID: <mailman.3790.1355071628.16123.coreboot@coreboot.org>

Author: uwe
Date: 2009-10-04 19:15:39 +0200 (Sun, 04 Oct 2009)
New Revision: 4719

Added:
   trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig
   trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc
   trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig
   trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc
   trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig
   trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc
Modified:
   trunk/coreboot-v2/src/Kconfig
   trunk/coreboot-v2/src/cpu/amd/Kconfig
   trunk/coreboot-v2/src/cpu/amd/Makefile.inc
   trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc
   trunk/coreboot-v2/src/mainboard/advantech/Kconfig
   trunk/coreboot-v2/src/mainboard/asi/Kconfig
   trunk/coreboot-v2/src/mainboard/axus/Kconfig
   trunk/coreboot-v2/src/mainboard/bcom/Kconfig
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c
   trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig
   trunk/coreboot-v2/src/mainboard/iei/Kconfig
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
   trunk/coreboot-v2/src/mainboard/televideo/Kconfig
   trunk/coreboot-v2/src/northbridge/amd/Kconfig
   trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig
Log:
Add initial kconfig support for all AMD GX1 boards.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: trunk/coreboot-v2/src/Kconfig
===================================================================
--- trunk/coreboot-v2/src/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -190,6 +190,10 @@
 	bool
 	default n
 
+config VIDEO_MB
+	int
+	default 0
+
 config USE_WATCHDOG_ON_BOOT
 	bool
 	default n

Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/cpu/amd/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -12,4 +12,5 @@
 source src/cpu/amd/socket_S1G1/Kconfig
 
 source src/cpu/amd/model_fxx/Kconfig
+source src/cpu/amd/model_gx1/Kconfig
 source src/cpu/amd/model_gx2/Kconfig

Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/Makefile.inc	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1,5 +1,6 @@
 subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
 subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2
+subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1

Added: trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_AMD_GX1
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+driver-y += model_gx1_init.o

Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -26,9 +26,16 @@
 crt0-y += ../../../../src/arch/i386/lib/id.inc
 crt0-y += failover.inc
 crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+
+ifeq ($(CONFIG_CPU_AMD_GX1),y)
+crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc
+crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc
+crt0-y += auto.inc
+else
 crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
 crt0-y += auto.inc
 crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+endif
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
 ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds

Modified: trunk/coreboot-v2/src/mainboard/advantech/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/advantech/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,28 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_ADVANTECH
+
+source "src/mainboard/advantech/pcm-5820/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_ADVANTECH_PCM_5820
+	bool "PCM-5820"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_WINBOND_W83977F
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default advantech/pcm-5820
+	depends on BOARD_ADVANTECH_PCM_5820
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "PCM-5820"
+	depends on BOARD_ADVANTECH_PCM_5820
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_ADVANTECH_PCM_5820
+
+config IRQ_SLOT_COUNT
+	int
+	default 2
+	depends on BOARD_ADVANTECH_PCM_5820
+

Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/asi/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/asi/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,29 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_ASI
+
+source "src/mainboard/asi/mb_5blgp/Kconfig"
+source "src/mainboard/asi/mb_5blmp/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_ASI_MB_5BLGP
+	bool "MB-5BLGP"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC87351
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default asi/mb_5blgp
+	depends on BOARD_ASI_MB_5BLGP
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MB-5BLGP"
+	depends on BOARD_ASI_MB_5BLGP
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_ASI_MB_5BLGP
+
+config IRQ_SLOT_COUNT
+	int
+	default 3
+	depends on BOARD_ASI_MB_5BLGP
+

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_ASI_MB_5BLMP
+	bool "MB-5BLMP"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC87351
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default asi/mb_5blmp
+	depends on BOARD_ASI_MB_5BLMP
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MB-5BLMP"
+	depends on BOARD_ASI_MB_5BLMP
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_ASI_MB_5BLMP
+
+config IRQ_SLOT_COUNT
+	int
+	default 5
+	depends on BOARD_ASI_MB_5BLMP
+

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/axus/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/axus/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,28 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_AXUS
+
+source "src/mainboard/axus/tc320/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_AXUS_TC320
+	bool "TC320"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC97317
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default axus/tc320
+	depends on BOARD_AXUS_TC320
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "TC320"
+	depends on BOARD_AXUS_TC320
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_AXUS_TC320
+
+# Soldered NIC, internal USB, no real PCI slots.
+config IRQ_SLOT_COUNT
+	int
+	default 2
+	depends on BOARD_AXUS_TC320
+

Added: trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/bcom/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/bcom/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,29 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_BCOM
+
+source "src/mainboard/bcom/winnet100/Kconfig"
+# source "src/mainboard/bcom/winnetp680/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_BCOM_WINNET100
+	bool "WinNET100"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC97317
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default bcom/winnet100
+	depends on BOARD_BCOM_WINNET100
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "WinNET100"
+	depends on BOARD_BCOM_WINNET100
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_BCOM_WINNET100
+
+# Soldered NIC, internal USB, no real PCI slots.
+config IRQ_SLOT_COUNT
+	int
+	default 2
+	depends on BOARD_BCOM_WINNET100
+

Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_EAGLELION_5BCM
+	bool "5BCM"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC97317
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default eaglelion/5bcm
+	depends on BOARD_EAGLELION_5BCM
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "5BCM"
+	depends on BOARD_EAGLELION_5BCM
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_EAGLELION_5BCM
+
+config IRQ_SLOT_COUNT
+	int
+	default 2
+	depends on BOARD_EAGLELION_5BCM
+

Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c	2009-10-04 17:15:39 UTC (rev 4719)
@@ -10,7 +10,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
-	32+16*2,	 /* there can be total 2 devices on the bus */
+	32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 2 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
 	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
 	0x800,		 /* IRQs devoted exclusively to PCI usage */

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,28 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_EAGLELION
+
+source "src/mainboard/eaglelion/5bcm/Kconfig"
+
+endchoice
+

Modified: trunk/coreboot-v2/src/mainboard/iei/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/iei/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,29 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_IEI
+
+source "src/mainboard/iei/juki-511p/Kconfig"
+source "src/mainboard/iei/nova4899r/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,48 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_IEI_JUKI_511P
+	bool "JUKI-511P"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_WINBOND_W83977F
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select HAVE_OPTION_TABLE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default iei/juki-511p
+	depends on BOARD_IEI_JUKI_511P
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "JUKI-511P"
+	depends on BOARD_IEI_JUKI_511P
+
+config IRQ_SLOT_COUNT
+	int
+	default 2
+	depends on BOARD_IEI_JUKI_511P
+

Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,48 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_IEI_NOVA_4899R
+	bool "NOVA-4899R"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_WINBOND_W83977TF
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select HAVE_OPTION_TABLE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default iei/nova4899r
+	depends on BOARD_IEI_NOVA_4899R
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "NOVA-4899R"
+	depends on BOARD_IEI_NOVA_4899R
+
+config IRQ_SLOT_COUNT
+	int
+	default 5
+	depends on BOARD_IEI_NOVA_4899R
+

Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
@@ -82,7 +82,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default CONFIG_HAVE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=7
+default CONFIG_IRQ_SLOT_COUNT=5
 default CONFIG_PIRQ_ROUTE=1
 #object irq_tables.o
 

Modified: trunk/coreboot-v2/src/mainboard/televideo/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/mainboard/televideo/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1 +1,28 @@
-#
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_TELEVIDEO
+
+source "src/mainboard/televideo/tc7020/Kconfig"
+
+endchoice
+

Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_TELEVIDEO_TC7020
+	bool "TC7020"
+	select ARCH_X86
+	select CPU_AMD_GX1
+	select NORTHBRIDGE_AMD_GX1
+	select SOUTHBRIDGE_AMD_CS5530
+	select SUPERIO_NSC_PC97317
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config MAINBOARD_DIR
+	string
+	default televideo/tc7020
+	depends on BOARD_TELEVIDEO_TC7020
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "TC7020"
+	depends on BOARD_TELEVIDEO_TC7020
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_TELEVIDEO_TC7020
+
+config IRQ_SLOT_COUNT
+	int
+	default 3
+	depends on BOARD_TELEVIDEO_TC7020
+

Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ROMCCFLAGS := -mcpu=i386
+include $(src)/mainboard/Makefile.romccboard.inc
+

Modified: trunk/coreboot-v2/src/northbridge/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/northbridge/amd/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1,5 +1,5 @@
 source src/northbridge/amd/amdk8/Kconfig
+source src/northbridge/amd/gx1/Kconfig
 source src/northbridge/amd/gx2/Kconfig
 source src/northbridge/amd/amdfam10/Kconfig
-#source src/northbridge/amd/gx1/Kconfig
 #source src/northbridge/amd/lx/Kconfig

Added: trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_AMD_GX1
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc	2009-10-04 17:15:39 UTC (rev 4719)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-y += northbridge.o
+

Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig	2009-10-04 12:30:44 UTC (rev 4718)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig	2009-10-04 17:15:39 UTC (rev 4719)
@@ -1,3 +1,76 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
 config SOUTHBRIDGE_AMD_CS5530
 	bool
 	default n
+
+menu "AMD Geode GX1 video support"
+	depends on SOUTHBRIDGE_AMD_CS5530
+
+config GX1_VIDEO
+	bool "AMD Geode GX1 video mode support"
+	default y
+	depends on SOUTHBRIDGE_AMD_CS5530
+
+choice
+	prompt "AMD Geode GX1 video mode"
+	default GX1_VIDEOMODE_0
+	depends on GX1_VIDEO
+
+config GX1_VIDEOMODE_0
+	bool "640x480"
+config GX1_VIDEOMODE_1
+	bool "800x600"
+config GX1_VIDEOMODE_2
+	bool "1024x768"
+config GX1_VIDEOMODE_3
+	bool "1280x960"
+config GX1_VIDEOMODE_4
+	bool "1280x1024"
+
+endchoice
+
+config GX1_VIDEOMODE
+	int
+	default 0 if GX1_VIDEOMODE_0
+	default 1 if GX1_VIDEOMODE_1
+	default 2 if GX1_VIDEOMODE_2
+	default 3 if GX1_VIDEOMODE_3
+	default 4 if GX1_VIDEOMODE_4
+	depends on GX1_VIDEO
+
+# TODO: Check how much RAM each of the modes actually needs.
+config VIDEO_MB
+	int
+	default 2 if GX1_VIDEOMODE_0
+	default 2 if GX1_VIDEOMODE_1
+	default 2 if GX1_VIDEOMODE_2
+	default 2 if GX1_VIDEOMODE_3
+	default 2 if GX1_VIDEOMODE_4
+	depends on GX1_VIDEO
+
+config SPLASH_GRAPHIC
+	bool "Enable splash screen on AMD Geode GX1 boards"
+	default y
+	depends on GX1_VIDEO
+
+endmenu
+




From uwe at hermann-uwe.de  Sun Oct  4 19:16:41 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Oct 2009 19:16:41 +0200
Subject: [coreboot] [PATCH] kconfig support for all GX1 boards
In-Reply-To: <13426df10910040926ye896544vf08872fc8bbb31de@mail.gmail.com>
References: <20091004154534.GM15511@greenwood>
	<13426df10910040926ye896544vf08872fc8bbb31de@mail.gmail.com>
Message-ID: <20091004171640.GA14135@greenwood>

On Sun, Oct 04, 2009 at 09:26:47AM -0700, ron minnich wrote:
> But, as said,for each CPU that supports SSE and MMX, we have to add
> the right select statements.

Sure, we'll change that as soon as the SSE/MMX infrastructure is in
place.


> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Thanks, r4719.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From uwe at hermann-uwe.de  Sun Oct  4 20:08:04 2009
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 4 Oct 2009 20:08:04 +0200
Subject: [coreboot] CBFS issues on 440BX boards
Message-ID: <20091004180804.GN15511@greenwood>

Uncompressing coreboot to RAM.                                                  
Jumping to image.                                                               
Check CBFS header at fffedfe0                                                   
magic is ffffffff                                                               
ERROR: No valid CBFS header found!                                              
CBFS:  Could not find file fallback/coreboot_ram                                
Jumping to image.                                                               


I can reproduce this on hardware on ASUS P2B-F and Biostar M6TBA, but I
guess it happens on all 440BX boards, maybe also for other chipsets,
didn't check yet.

RAM init works ok (tested with ram_check()) so I think bad RAM init can
be ruled out. Also, disabling HIGH TABLES didn't seem to improve
anything here.

Here's a sample CBFS output:

./coreboot.rom: 256 kB, bootblocksize 73728, romsize 262144, offset 0x0
Alignment: 64 bytes

Name                           Offset     Type         Size
normal/payload                 0x0        payload      28850
normal/coreboot_ram            0x7100     stage        46897
fallback/payload               0x12880    payload      28850
fallback/coreboot_ram          0x19980    stage        46893
                               0x25100    null         36536

Not sure why it says "Check CBFS header at fffedfe0" as
CBFS_HEADPTR_ADDR is defined as 0xFFFFFFFc...

I'm thankful for any hints.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org



From patrick at georgi-clan.de  Sun Oct  4 20:26:17 2009
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 04 Oct 2009 20:26:17 +0200
Subject: [coreboot] CBFS issues on 440BX boards
In-Reply-To: <20091004180804.GN15511@greenwood>
References: <20091004180804.GN15511@greenwood>
Message-ID: <1254680777.4077.96.camel@tetris>

Am Sonntag, den 04.10.2009, 20:08 +0200 schrieb Uwe Hermann:
> Uncompressing coreboot to RAM.                                                  
> Jumping to image.                                                               
> Check CBFS header at fffedfe0                                                   
> magic is ffffffff                                                               
> ERROR: No valid CBFS header found!                                              
> CBFS:  Could not find file fallback/coreboot_ram                                
> Jumping to image.                                                               
> 
> 
> I can reproduce this on hardware on ASUS P2B-F and Biostar M6TBA, but I
> guess it happens on all 440BX boards, maybe also for other chipsets,
> didn't check yet.
> 
> RAM init works ok (tested with ram_check()) so I think bad RAM init can
> be ruled out. Also, disabling HIGH TABLES didn't seem to improve
> anything here.
> 
> Here's a sample CBFS output:
> 
> ./coreboot.rom: 256 kB, bootblocksize 73728, romsize 262144, offset 0x0
> Alignment: 64 bytes
> 
> Name                           Offset     Type         Size
> normal/payload                 0x0        payload      28850
> normal/coreboot_ram            0x7100     stage        46897
> fallback/payload               0x12880    payload      28850
> fallback/coreboot_ram          0x19980    stage        46893
>                                0x25100    null         36536
> 
> Not sure why it says "Check CBFS header at fffedfe0" as
> CBFS_HEADPTR_ADDR is defined as 0xFFFFFFFc...
That I can answer:
fffffffc contains the address that points to the CBFS header (so it
likely contains fffedfe0)

A magic of 0xffffffff is suspicious, are you sure the ROM is entirely
mapped before coreboot_ram is loaded?


Patrick




From ziltro at ziltro.com  Sun Oct  4 20:49:18 2009
From: ziltro at ziltro.com (Andrew Morgan)
Date: Sun, 04 Oct 2009 19:49:18 +0100
Subject: [coreboot] CBFS issues on 440BX boards
In-Reply-To: <20091004180804.GN15511@greenwood>
References: <20091004180804.GN15511@greenwood>
Message-ID: <4AC8EE2E.6030003@ziltro.com>

Uwe Hermann wrote:
> Uncompressing coreboot to RAM.                                                  
> Jumping to image.                                                               
> Check CBFS header at fffedfe0                                                   
> magic is ffffffff                                                               
> ERROR: No valid CBFS header found!                                              
> CBFS:  Could not find file fallback/coreboot_ram                                
> Jumping to image.                                                               
>
>
> I can reproduce this on hardware on ASUS P2B-F and Biostar M6TBA, but I
> guess it happens on all 440BX boards, maybe also for other chipsets,
> didn't check yet.
>   

I get something similar on the Soyo SY-6BA+ III board, only the address 
is different:

Copying coreboot to RAM.
Jumping to image.
Check CBFS header at fffeffe0
magic is ffffffff
ERROR: No valid CBFS header found!
CBFS:  Could not find file fallback/coreboot_ram
Jumping to image.

Booting from the vendor BIOS into Linux then swapping to the Coreboot 
ROM and typing 'reboot' made it get further, if that helps.

-- 

Andrew.




From svn at coreboot.org  Sun Oct  4 20:55:40 2009
From: svn at coreboot.org (svn at coreboot.org)
Date: Sun,  4 Oct 2009 20:55:40 +0200
Subject: [coreboot] [v2] r4720 - in trunk/coreboot-v2: src/arch/i386/lib
	src/config src/mainboard/a-trend/atc-6220
	src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0
	src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800
	src/mainboard/amd/dbm690t src/mainboard/amd/norwich
	src/mainboard/amd/pistachio src/mainboard/amd/rumba
	src/mainboard/amd/serengeti_cheetah
	src/mainboard/amd/serengeti_cheetah_fam10
	src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61
	src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp
	src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se
	src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am
	src/mainboard/asus/mew-vm src/mainboard/asus/p2b
	src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds
	src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f
	src/mainboard/axus/tc320 src/mainboard/azza/pt-6ibd
	src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680
	src/mainboard/biostar/m6tba src/mainboard/broadcom/blast
	src/mainboard/compaq/deskpro_en_sff_p600
	src/mainboard/dell/s1850 src/mainboard/digitallogic/adl855pc
	src/mainboard/digitallogic/msm586seg
	src/mainboard/digitallogic/msm800sev
	src/mainboard/eaglelion/5bcm src/mainboard/emulation/qemu-x86
	src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk
	src/mainboard/gigabyte/m57sli src/mainboard/hp/dl145_g3
	src/mainboard/ibm/e325 src/mainboard/ibm/e326
	src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r
	src/mainboard/iei/pcisa-lx-800-r10
	src/mainboard/intel/eagleheights src/mainboard/intel/jarrell
	src/mainboard/intel/mtarvon src/mainboard/intel/truxton
	src/mainboard/intel/xe7501devkit src/mainboard/iwill/dk8_htx
	src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x
	src/mainboard/jetway/j7f24 src/mainboard/kontron/986lcd-m
	src/mainboard/lippert/frontrunner
	src/mainboard/lippert/roadrunner-lx
	src/mainboard/lippert/spacerunner-lx
	src/mainboard/mitac/6513wu src/mainboard/msi/ms6119
	src/mainboard/msi/ms6147 src/mainboard/msi/ms6178
	src/mainboard/msi/ms7135 src/mainboard/msi/ms7260
	src/mainboard/msi/ms9185 src/mainboard/msi/ms9282
	src/mainboard/nec/powermate2000 src/mainboard/newisys/khepri
	src/mainboard/nvidia/l1_2pvv src/mainboard/olpc/btest
	src/mainboard/olpc/rev_a src/mainboard/pcengines/alix1c
	src/mainboard/rca/rm4100 src/mainboard/soyo/sy-6ba-plus-iii
	src/mainboard/sunw/ultra40 src/mainboard/supermicro/h8dme
	src/mainboard/supermicro/h8dmr src/mainboard/supermicro/h8dmr_fam10
	src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g
	src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig
	src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion/tim8690
	src/mainboard/technologic/ts5300
	src/mainboard/televideo/tc7020 src/mainboard/thomson/ip1000
	src/mainboard/tyan/s1846 src/mainboard/tyan/s2735
	src/mainboard/tyan/s2850 src/mainboard/tyan/s2875
	src/mainboard/tyan/s2880 src/mainboard/tyan/s2881
	src/mainboard/tyan/s2882 src/mainboard/tyan/s2885
	src/mainboard/tyan/s2891 src/mainboard/tyan/s2892
	src/mainboard/tyan/s2895 src/mainboard/tyan/s2912
	src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880
	src/mainboard/tyan/s4882 src/mainboard/via/epia
	src/mainboard/via/epia-cn src/mainboard/via/epia-m
	src/mainboard/via/epia-m700 src/mainboard/via/epia-n
	src/mainboard/via/pc2500e src/mainboard/via/vt8454c
	src/southbridge/nvidia/ck804 src/southbridge/nvidia/mcp55
	src/southbridge/sis/sis966 targets/arima/hdama
	targets/iwill/dk8s2 targets/iwill/dk8x
Message-ID: <mailman.3791.1355071628.16123.coreboot@coreboot.org>

Author: oxygene
Date: 2009-10-04 20:55:40 +0200 (Sun, 04 Oct 2009)
New Revision: 4720

Modified:
   trunk/coreboot-v2/src/arch/i386/lib/failover.lds
   trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds
   trunk/coreboot-v2/src/arch/i386/lib/id.inc
   trunk/coreboot-v2/src/config/Options.lb
   trunk/coreboot-v2/src/config/failovercalculation.lb
   trunk/coreboot-v2/src/config/nofailovercalculation.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
   trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
   trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
   trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
   trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
   trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
   trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
   trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
   trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb
   trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
   trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
   trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia/Options.lb
   trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb
   trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/id.inc
   trunk/coreboot-v2/src/southbridge/sis/sis966/id.inc
   trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb
   trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/targets/iwill/dk8x/Config.lb
Log:
This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.

Various calculations in {no,}failovercalculation.lb are adapted
accordingly.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/arch/i386/lib/failover.lds
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/failover.lds	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/arch/i386/lib/failover.lds	2009-10-04 18:55:40 UTC (rev 4720)
@@ -1 +1 @@
-	__normal_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
+	__normal_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;

Modified: trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds	2009-10-04 18:55:40 UTC (rev 4720)
@@ -1,2 +1,2 @@
-	__fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8;
-	__normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;
+	__fallback_image = (CONFIG_ROMBASE & 0xfffffff0) - 8;
+	__normal_image = ((CONFIG_ROMBASE - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8;

Modified: trunk/coreboot-v2/src/arch/i386/lib/id.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/id.inc	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/arch/i386/lib/id.inc	2009-10-04 18:55:40 UTC (rev 4720)
@@ -8,7 +8,7 @@
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 .long __id_end + 0x10 - vendor  /* Reverse offset to the vendor id */
 .long __id_end + 0x10 - part    /* Reverse offset to the part number */
-.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE  /* Size of this romimage */
+.long CONFIG_ROM_SIZE           /* Size of this romimage */
 	.globl __id_end
 
 __id_end:

Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/config/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -246,14 +246,8 @@
 	export used
 	comment "Default rom section offset"
 end
-define CONFIG_PAYLOAD_SIZE
-	default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE}
-	format "0x%x"
-	export always
-	comment "Default payload size"
-end
 define CONFIG_ROMBASE
-	default {CONFIG_PAYLOAD_SIZE}
+	default {0xffffffff - CONFIG_ROM_SIZE + 1}
 	format "0x%x"
 	export always
 	comment "Base address of coreboot in ROM"
@@ -646,12 +640,6 @@
 	export always
 	comment "Boot image is located in ROM" 
 end
-define CONFIG_ROM_PAYLOAD_START
-	default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1}
-	format "0x%x"
-	export always
-	comment "ROM stream start location"
-end
 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
 	default 0
 	export always

Modified: trunk/coreboot-v2/src/config/failovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/failovercalculation.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/config/failovercalculation.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,16 +16,9 @@
 end
 
 ##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,

Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -11,16 +11,9 @@
 end
 
 ##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,8 +40,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,10 +20,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -23,10 +23,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -42,10 +42,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,8 +40,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -17,12 +17,10 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -41,10 +41,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -36,8 +36,6 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -36,8 +36,6 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,10 +20,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,8 +40,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,8 +40,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -41,10 +41,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -19,10 +19,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -21,10 +21,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -22,10 +22,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,10 +20,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -6,19 +6,12 @@
 ##
 default CONFIG_ROM_SIZE = 256 * 1024 
 default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_SECTION_OFFSET = 0
+default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
 
 ##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,

Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -24,8 +24,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -46,11 +46,9 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -44,11 +44,9 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -45,10 +45,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -5,16 +5,9 @@
 default CONFIG_ROM_SIZE = 256 * 1024 
 
 ##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )
+default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute a range of ROM that can cached to speed up coreboot,

Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -25,8 +25,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,8 +20,6 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,12 +40,10 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -48,11 +48,9 @@
 uses CONFIG_ROM_SECTION_OFFSET
 # Payload
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 # Build Internals
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE

Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -34,9 +34,7 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -34,10 +34,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_LB_MEM_TOPK
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -46,10 +46,6 @@
 #uses CONFIG_CPU_OPT
 uses CONFIG_IDE
 
-## The default definitions are used for these
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
-
 ## These are defined in target Config.lb, don't add here
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -23,10 +23,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -16,10 +16,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -41,10 +41,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -49,10 +49,8 @@
 uses CONFIG_ROM_SECTION_OFFSET
 # Payload
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 # Build Internals
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE

Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,10 +20,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -42,12 +42,10 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -42,12 +42,10 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESS
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -37,13 +37,11 @@
 uses CONFIG_MAINBOARD_VENDOR
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_OBJCOPY
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,9 +40,7 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -42,9 +42,7 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,11 +40,9 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -44,10 +44,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -41,8 +41,6 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,10 +40,8 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -17,10 +17,8 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -44,11 +44,9 @@
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_XIP_ROM_BASE

Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -20,11 +20,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -40,11 +40,9 @@
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_PAYLOAD_SIZE
 uses CONFIG_ROMBASE
 uses CONFIG_RAMBASE
 uses CONFIG_XIP_ROM_SIZE

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-10-04 17:15:39 UTC (rev 4719)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb	2009-10-04 18:55:40 UTC (rev 4720)
@@ -26,7 +26,6 @@
 uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 uses CONFIG_PCI_ROM_RUN