[coreboot] [v2] r4745 - in trunk/coreboot-v2/src/cpu/intel: socket_PGA370 socket_mPGA479M socket_mPGA604
mylesgw at gmail.com
Fri Oct 9 17:47:32 CEST 2009
On Thu, Oct 8, 2009 at 9:44 PM, ron minnich <rminnich at gmail.com> wrote:
> to generate romcc code that
> will work on the least-capable CPU for that socket.
> the socket has to determine
> whether MMX and SSE are set.
Maybe since these options are romcc-specific they should be ROMCC_MMX
& ROMCC_SSE. I just noticed that on my K8 boards SSE=0, which is
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