[coreboot] build service results for r4796
joe at settoplinux.org
Sat Oct 17 01:41:38 CEST 2009
On 10/16/2009 06:30 PM, coreboot information wrote:
> Dear coreboot readers!
> This is the automatic build system of coreboot.
> The developer "rminnich" checked in revision 4796 to
> the coreboot repository. This caused the following
> Change Log:
> This is a snapshot as the availability of the systems for this
> project is now uncertain, and I can't invest the remaining time
> needed to get it done.
> Status is that memory is still not quite configured correctly. It is close
> but here are DRAM Row Boundary registers.
> Here is coreboot
> 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
> This is close. But:
> 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
> is the real hardware. So we are somehow missing those last slots. I think it's
> because the SPD connections and the chip connections differ, some dumping
> of RAM registers differ. But it's very close.
Hmm, why not try SPD byte 31 to calculate DRB, I use this on the i830
and it has yet to fail. DRB is not hard to calculate it is just the
memory size of each row (side) in ticks of 64 in your case. The i830 is
similar (except ticks of 32), take a look it may help.
> I want to commit this because even if I get no further, someone else might.
> Note that for serialice you need the following temporary patch as well:
> Index: src/superio/nsc/pc8374/pc8374_early_init.c
> --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791)
> +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy)
> @@ -29,7 +29,8 @@
> static void pc8374_enable_dev(device_t dev, unsigned iobase)
> - pnp_set_enable(dev, 0);
> +/* don't disable for now, it kills serialice */
> + pnp_set_enable(dev, 1);
You didn't commit this to real coreboot did you?
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