From svn at coreboot.org  Thu Apr  1 11:50:32 2010
From: svn at coreboot.org (repository service)
Date: Thu, 01 Apr 2010 11:50:32 +0200
Subject: [coreboot] [commit] r5344 - in trunk/src: arch/i386/include/arch
	arch/i386/init arch/i386/lib arch/i386/llshell console
	cpu/amd/model_lx cpu/intel/model_106cx cpu/intel/model_6ex
	cpu/intel/model_6fx cpu/x86/3...
Message-ID: <E1NxH2m-0005d0-Rj@ra.coresystems.de>

Author: stepan
Date: Thu Apr  1 11:50:32 2010
New Revision: 5344
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5344

Log:
-??get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()"

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/arch/i386/include/arch/intel.h
   trunk/src/arch/i386/init/bootblock_prologue.c
   trunk/src/arch/i386/init/car.S
   trunk/src/arch/i386/init/crt0.S.lb
   trunk/src/arch/i386/lib/c_start.S
   trunk/src/arch/i386/lib/printk_init.c
   trunk/src/arch/i386/llshell/console.inc
   trunk/src/arch/i386/llshell/ramtest.inc
   trunk/src/arch/i386/llshell/readme.coreboot
   trunk/src/console/console.c
   trunk/src/cpu/amd/model_lx/cache_as_ram.inc
   trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
   trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
   trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
   trunk/src/cpu/x86/32bit/entry32.inc
   trunk/src/include/console/console.h
   trunk/src/include/console/loglevel.h
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/norwich/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/artecgroup/dbe61/romstage.c
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/digitallogic/adl855pc/romstage.c
   trunk/src/mainboard/digitallogic/msm586seg/romstage.c
   trunk/src/mainboard/digitallogic/msm800sev/romstage.c
   trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
   trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/pcengines/alix1c/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/technologic/ts5300/romstage.c
   trunk/src/mainboard/tyan/s2850/romstage.c
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/winent/pl6064/romstage.c
   trunk/src/northbridge/amd/gx2/pll_reset.c
   trunk/src/northbridge/amd/lx/pll_reset.c
   trunk/src/northbridge/amd/lx/raminit.c

Modified: trunk/src/arch/i386/include/arch/intel.h
==============================================================================
--- trunk/src/arch/i386/include/arch/intel.h	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/include/arch/intel.h	Thu Apr  1 11:50:32 2010	(r5344)
@@ -45,10 +45,8 @@
 	jmp *%esp
 
 
-/* originally this macro was from STPC BIOS */
-#define	intel_chip_post_macro(value)			 \
-	movb	$value, %al				; \
+#define	post_code(value)	\
+	movb	$value, %al;	\
 	outb	%al, $0x80
 
-
 #endif /* ROM_INTEL_H */

Modified: trunk/src/arch/i386/init/bootblock_prologue.c
==============================================================================
--- trunk/src/arch/i386/init/bootblock_prologue.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/init/bootblock_prologue.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -33,5 +33,5 @@
 .section ".rom.data", "a", @progbits
 .section ".rom.text", "ax", @progbits
 
-	intel_chip_post_macro(0x01)             /* delay for chipsets */
+	post_code(0x01)             /* delay for chipsets */
 

Modified: trunk/src/arch/i386/init/car.S
==============================================================================
--- trunk/src/arch/i386/init/car.S	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/init/car.S	Thu Apr  1 11:50:32 2010	(r5344)
@@ -54,7 +54,7 @@
 	/* Save the BIST result. */
 	movl	%eax, %ebp
 
-	intel_chip_post_macro(0x01)
+	post_code(0x01)
 
 	movw	$ROM_DATA_SEG, %ax
 	movw	%ax, %ds

Modified: trunk/src/arch/i386/init/crt0.S.lb
==============================================================================
--- trunk/src/arch/i386/init/crt0.S.lb	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/init/crt0.S.lb	Thu Apr  1 11:50:32 2010	(r5344)
@@ -25,6 +25,10 @@
 #include <arch/intel.h>
 #include <console/loglevel.h>	
 
+#ifndef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#endif
+
 /*
  * This is the entry code the code in .reset section
  * jumps to this address.
@@ -33,7 +37,7 @@
 .section ".rom.data", "a", @progbits
 .section ".rom.text", "ax", @progbits
 
-	intel_chip_post_macro(0x01)             /* delay for chipsets */
+	post_code(0x01)             /* delay for chipsets */
 
 #include "crt0_includes.h"
 
@@ -61,7 +65,7 @@
 	 *	isn\'t really that big we just copy/clear using bytes, not
 	 *	double words.
 	 */
-	intel_chip_post_macro(0x11)		/* post 11 */
+	post_code(0x11)		/* post 11 */
 
 	cld				/* clear direction flag */
 	
@@ -78,7 +82,7 @@
 	call cbfs_and_run_core
 
 .Lhlt:	
-	intel_chip_post_macro(0xee)	/* post fe */
+	post_code(0xee)	/* post fe */
 	hlt
 	jmp	.Lhlt
 

Modified: trunk/src/arch/i386/lib/c_start.S
==============================================================================
--- trunk/src/arch/i386/lib/c_start.S	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/lib/c_start.S	Thu Apr  1 11:50:32 2010	(r5344)
@@ -15,7 +15,7 @@
 	movl	%eax, %fs
 	movl	%eax, %gs
 
-	intel_chip_post_macro(0x13)		/* post 13 */
+	post_code(0x13)		/* post 13 */
 
 	/** clear stack */
 	cld
@@ -74,7 +74,7 @@
 	 *	bss is cleared.   Now we call the main routine and
 	 *	let it do the rest.
 	 */ 
-	intel_chip_post_macro(0xfe)	/* post fe */
+	post_code(0xfe)	/* post fe */
 
 	/* Restore the stack location */
 	movl	%ebp, %esp
@@ -83,7 +83,7 @@
 	call	hardwaremain
 	/*NOTREACHED*/
 .Lhlt:
-	intel_chip_post_macro(0xee)	/* post ee */
+	post_code(0xee)	/* post ee */
 	hlt
 	jmp	.Lhlt
 	

Modified: trunk/src/arch/i386/lib/printk_init.c
==============================================================================
--- trunk/src/arch/i386/lib/printk_init.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/lib/printk_init.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -19,19 +19,8 @@
 
 #include <console/console.h>
 #include <console/vtxprintf.h>
-#include <console/loglevel.h>
 #include <uart8250.h>
 
-/* Using a global varible can cause problems when we reset the stack 
- * from cache as ram to ram. If we make this a define USE_SHARED_STACK
- * we could use the same code on all architectures.
- */
-#if 0
-int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
-#else
-#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#endif
-
 static void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')

Modified: trunk/src/arch/i386/llshell/console.inc
==============================================================================
--- trunk/src/arch/i386/llshell/console.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/llshell/console.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -234,180 +234,6 @@
 #define CONSOLE_SPEW_TX_STRING(string)        __CONSOLE_TX_STRING(string)
 #define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
 
-#if 0
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_EMERG
-#undef  CONSOLE_EMERG_TX_CHAR
-#undef  CONSOLE_EMERG_INLINE_TX_CHAR
-#undef  CONSOLE_EMERG_TX_HEX8
-#undef  CONSOLE_EMERG_INLINE_TX_HEX8
-#undef  CONSOLE_EMERG_TX_HEX32
-#undef  CONSOLE_EMERG_INLINE_TX_HEX32
-#undef  CONSOLE_EMERG_TX_STRING
-#undef  CONSOLE_EMERG_INLINE_TX_STRING
-#define CONSOLE_EMERG_TX_CHAR(byte)            
-#define CONSOLE_EMERG_INLINE_TX_CHAR(byte)     
-#define CONSOLE_EMERG_TX_HEX8(byte)            
-#define CONSOLE_EMERG_INLINE_TX_HEX8(byte)     
-#define CONSOLE_EMERG_TX_HEX32(lword)          
-#define CONSOLE_EMERG_INLINE_TX_HEX32(lword)   
-#define CONSOLE_EMERG_TX_STRING(string)        
-#define CONSOLE_EMERG_INLINE_TX_STRING(string) 
-#endif
-
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_ALERT
-#undef  CONSOLE_ALERT_TX_CHAR
-#undef  CONSOLE_ALERT_INLINE_TX_CHAR
-#undef  CONSOLE_ALERT_TX_HEX8
-#undef  CONSOLE_ALERT_INLINE_TX_HEX8
-#undef  CONSOLE_ALERT_TX_HEX32
-#undef  CONSOLE_ALERT_INLINE_TX_HEX32
-#undef  CONSOLE_ALERT_TX_STRING
-#undef  CONSOLE_ALERT_INLINE_TX_STRING
-#define CONSOLE_ALERT_TX_CHAR(byte)            
-#define CONSOLE_ALERT_INLINE_TX_CHAR(byte)     
-#define CONSOLE_ALERT_TX_HEX8(byte)            
-#define CONSOLE_ALERT_INLINE_TX_HEX8(byte)     
-#define CONSOLE_ALERT_TX_HEX32(lword)          
-#define CONSOLE_ALERT_INLINE_TX_HEX32(lword)   
-#define CONSOLE_ALERT_TX_STRING(string)        
-#define CONSOLE_ALERT_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_CRIT
-#undef  CONSOLE_CRIT_TX_CHAR
-#undef  CONSOLE_CRIT_INLINE_TX_CHAR
-#undef  CONSOLE_CRIT_TX_HEX8
-#undef  CONSOLE_CRIT_INLINE_TX_HEX8
-#undef  CONSOLE_CRIT_TX_HEX32
-#undef  CONSOLE_CRIT_INLINE_TX_HEX32
-#undef  CONSOLE_CRIT_TX_STRING
-#undef  CONSOLE_CRIT_INLINE_TX_STRING
-#define CONSOLE_CRIT_TX_CHAR(byte)            
-#define CONSOLE_CRIT_INLINE_TX_CHAR(byte)     
-#define CONSOLE_CRIT_TX_HEX8(byte)            
-#define CONSOLE_CRIT_INLINE_TX_HEX8(byte)     
-#define CONSOLE_CRIT_TX_HEX32(lword)          
-#define CONSOLE_CRIT_INLINE_TX_HEX32(lword)   
-#define CONSOLE_CRIT_TX_STRING(string)        
-#define CONSOLE_CRIT_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_ERR
-#undef  CONSOLE_ERR_TX_CHAR
-#undef  CONSOLE_ERR_INLINE_TX_CHAR
-#undef  CONSOLE_ERR_TX_HEX8
-#undef  CONSOLE_ERR_INLINE_TX_HEX8
-#undef  CONSOLE_ERR_TX_HEX32
-#undef  CONSOLE_ERR_INLINE_TX_HEX32
-#undef  CONSOLE_ERR_TX_STRING
-#undef  CONSOLE_ERR_INLINE_TX_STRING
-#define CONSOLE_ERR_TX_CHAR(byte)            
-#define CONSOLE_ERR_INLINE_TX_CHAR(byte)     
-#define CONSOLE_ERR_TX_HEX8(byte)            
-#define CONSOLE_ERR_INLINE_TX_HEX8(byte)     
-#define CONSOLE_ERR_TX_HEX32(lword)          
-#define CONSOLE_ERR_INLINE_TX_HEX32(lword)   
-#define CONSOLE_ERR_TX_STRING(string)        
-#define CONSOLE_ERR_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_WARNING
-#undef  CONSOLE_WARNING_TX_CHAR
-#undef  CONSOLE_WARNING_INLINE_TX_CHAR
-#undef  CONSOLE_WARNING_TX_HEX8
-#undef  CONSOLE_WARNING_INLINE_TX_HEX8
-#undef  CONSOLE_WARNING_TX_HEX32
-#undef  CONSOLE_WARNING_INLINE_TX_HEX32
-#undef  CONSOLE_WARNING_TX_STRING
-#undef  CONSOLE_WARNING_INLINE_TX_STRING
-#define CONSOLE_WARNING_TX_CHAR(byte)            
-#define CONSOLE_WARNING_INLINE_TX_CHAR(byte)     
-#define CONSOLE_WARNING_TX_HEX8(byte)            
-#define CONSOLE_WARNING_INLINE_TX_HEX8(byte)     
-#define CONSOLE_WARNING_TX_HEX32(lword)          
-#define CONSOLE_WARNING_INLINE_TX_HEX32(lword)   
-#define CONSOLE_WARNING_TX_STRING(string)        
-#define CONSOLE_WARNING_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
-#undef  CONSOLE_NOTICE_TX_CHAR
-#undef  CONSOLE_NOTICE_INLINE_TX_CHAR
-#undef  CONSOLE_NOTICE_TX_HEX8
-#undef  CONSOLE_NOTICE_INLINE_TX_HEX8
-#undef  CONSOLE_NOTICE_TX_HEX32
-#undef  CONSOLE_NOTICE_INLINE_TX_HEX32
-#undef  CONSOLE_NOTICE_TX_STRING
-#undef  CONSOLE_NOTICE_INLINE_TX_STRING
-#define CONSOLE_NOTICE_TX_CHAR(byte)            
-#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte)     
-#define CONSOLE_NOTICE_TX_HEX8(byte)            
-#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte)     
-#define CONSOLE_NOTICE_TX_HEX32(lword)          
-#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword)   
-#define CONSOLE_NOTICE_TX_STRING(string)        
-#define CONSOLE_NOTICE_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_INFO
-#undef  CONSOLE_INFO_TX_CHAR
-#undef  CONSOLE_INFO_INLINE_TX_CHAR
-#undef  CONSOLE_INFO_TX_HEX8
-#undef  CONSOLE_INFO_INLINE_TX_HEX8
-#undef  CONSOLE_INFO_TX_HEX32
-#undef  CONSOLE_INFO_INLINE_TX_HEX32
-#undef  CONSOLE_INFO_TX_STRING
-#undef  CONSOLE_INFO_INLINE_TX_STRING
-#define CONSOLE_INFO_TX_CHAR(byte)            
-#define CONSOLE_INFO_INLINE_TX_CHAR(byte)     
-#define CONSOLE_INFO_TX_HEX8(byte)            
-#define CONSOLE_INFO_INLINE_TX_HEX8(byte)     
-#define CONSOLE_INFO_TX_HEX32(lword)          
-#define CONSOLE_INFO_INLINE_TX_HEX32(lword)   
-#define CONSOLE_INFO_TX_STRING(string)        
-#define CONSOLE_INFO_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
-#undef  CONSOLE_DEBUG_TX_CHAR
-#undef  CONSOLE_DEBUG_INLINE_TX_CHAR
-#undef  CONSOLE_DEBUG_TX_HEX8
-#undef  CONSOLE_DEBUG_INLINE_TX_HEX8
-#undef  CONSOLE_DEBUG_TX_HEX32
-#undef  CONSOLE_DEBUG_INLINE_TX_HEX32
-#undef  CONSOLE_DEBUG_TX_STRING
-#undef  CONSOLE_DEBUG_INLINE_TX_STRING
-#define CONSOLE_DEBUG_TX_CHAR(byte)            
-#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte)     
-#define CONSOLE_DEBUG_TX_HEX8(byte)            
-#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte)     
-#define CONSOLE_DEBUG_TX_HEX32(lword)          
-#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword)   
-#define CONSOLE_DEBUG_TX_STRING(string)        
-#define CONSOLE_DEBUG_INLINE_TX_STRING(string) 
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW
-#undef  CONSOLE_SPEW_TX_CHAR
-#undef  CONSOLE_SPEW_INLINE_TX_CHAR
-#undef  CONSOLE_SPEW_TX_HEX8
-#undef  CONSOLE_SPEW_INLINE_TX_HEX8
-#undef  CONSOLE_SPEW_TX_HEX32
-#undef  CONSOLE_SPEW_INLINE_TX_HEX32
-#undef  CONSOLE_SPEW_TX_STRING
-#undef  CONSOLE_SPEW_INLINE_TX_STRING
-#define CONSOLE_SPEW_TX_CHAR(byte)            
-#define CONSOLE_SPEW_INLINE_TX_CHAR(byte)     
-#define CONSOLE_SPEW_TX_HEX8(byte)            
-#define CONSOLE_SPEW_INLINE_TX_HEX8(byte)     
-#define CONSOLE_SPEW_TX_HEX32(lword)          
-#define CONSOLE_SPEW_INLINE_TX_HEX32(lword)   
-#define CONSOLE_SPEW_TX_STRING(string)        
-#define CONSOLE_SPEW_INLINE_TX_STRING(string) 
-#endif
-#endif
-
 	/* uses:	esp, ax, dx */
 console_tx_al:	
 	__CONSOLE_INLINE_TX_AL

Modified: trunk/src/arch/i386/llshell/ramtest.inc
==============================================================================
--- trunk/src/arch/i386/llshell/ramtest.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/llshell/ramtest.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -112,7 +112,7 @@
 	jmp 3b
 5:	
 	CONSOLE_INFO_TX_STRING($rt_toomany)
-	intel_chip_post_macro(0xf1)
+	post_code(0xf1)
 	jmp	.Lhlt
 
 6:

Modified: trunk/src/arch/i386/llshell/readme.coreboot
==============================================================================
--- trunk/src/arch/i386/llshell/readme.coreboot	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/arch/i386/llshell/readme.coreboot	Thu Apr  1 11:50:32 2010	(r5344)
@@ -16,7 +16,7 @@
 3) Optionally, comment out two lines in ramtest.inc:
 5:
         CONSOLE_INFO_TX_STRING($rt_toomany)
-        // intel_chip_post_macro(0xf1)
+        // post_code(0xf1)
         // jmp  .Lhlt
 otherwise, a ramtest failure will hang
 

Modified: trunk/src/console/console.c
==============================================================================
--- trunk/src/console/console.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/console/console.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -76,7 +76,7 @@
 /*
  *    Write POST information
  */
-void post_code(uint8_t value)
+void post_code(u8 value)
 {
 #if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
 #if CONFIG_SERIAL_POST==1

Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/model_lx/cache_as_ram.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -17,6 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#endif
+
 #define	LX_STACK_BASE		CONFIG_DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
 #define	LX_STACK_END		LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
 
@@ -206,7 +210,7 @@
 	 *	isn\'t really that big we just copy/clear using bytes, not
 	 *	double words.
 	 */
-	intel_chip_post_macro(0x11)		/* post 11 */
+	post_code(0x11)		/* post 11 */
 
 	cld				/* clear direction flag */
 
@@ -220,7 +224,7 @@
 	call cbfs_and_run_core
 
 .Lhlt:
-	intel_chip_post_macro(0xee)	/* post fail ee */
+	post_code(0xee)	/* post fail ee */
 	hlt
 	jmp	.Lhlt
 

Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -20,7 +20,6 @@
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -20,7 +20,6 @@
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -20,7 +20,6 @@
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>

Modified: trunk/src/cpu/x86/32bit/entry32.inc
==============================================================================
--- trunk/src/cpu/x86/32bit/entry32.inc	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/cpu/x86/32bit/entry32.inc	Thu Apr  1 11:50:32 2010	(r5344)
@@ -50,7 +50,7 @@
 	/* Save the BIST value */
 	movl	%eax, %ebp
 
-	intel_chip_post_macro(0x10)	/* post 10 */
+	post_code(0x10)	/* post 10 */
 
 	movw	$ROM_DATA_SEG, %ax
 	movw	%ax, %ds

Modified: trunk/src/include/console/console.h
==============================================================================
--- trunk/src/include/console/console.h	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/include/console/console.h	Thu Apr  1 11:50:32 2010	(r5344)
@@ -10,7 +10,7 @@
 void console_tx_flush(void);
 unsigned char console_rx_byte(void);
 int console_tst_byte(void);
-void post_code(uint8_t value);
+void post_code(u8 value);
 void __attribute__ ((noreturn)) die(const char *msg);
 #if CONFIG_CONSOLE_VGA == 1
 void vga_console_init(void);
@@ -31,7 +31,14 @@
 extern struct console_driver econsole_drivers[];
 
 extern int console_loglevel;
-#endif /* !__PRE_RAM__ */
+#else
+/* __PRE_RAM__ */
+/* Using a global varible can cause problems when we reset the stack 
+ * from cache as ram to ram. If we make this a define USE_SHARED_STACK
+ * we could use the same code on all architectures.
+ */
+#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+#endif
 
 #ifndef __ROMCC__
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
@@ -121,6 +128,8 @@
 #define print_debug_hex32(HEX)   printk(BIOS_DEBUG,  "%08x", (HEX))
 #define print_spew_hex32(HEX)    printk(BIOS_SPEW,   "%08x", (HEX))
 #else
+
+
 /* __ROMCC__ */
 static void __console_tx_byte(unsigned char byte)
 {
@@ -139,14 +148,14 @@
 
 static void __console_tx_char(int loglevel, unsigned char byte)
 {
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+	if (console_loglevel >= loglevel) {
 		uart_tx_byte(byte);
 	}
 }
 
 static void __console_tx_hex8(int loglevel, unsigned char value)
 {
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+	if (console_loglevel >= loglevel) {
 		__console_tx_nibble((value >>  4U) & 0x0fU);
 		__console_tx_nibble(value & 0x0fU);
 	}
@@ -154,7 +163,7 @@
 
 static void __console_tx_hex16(int loglevel, unsigned short value)
 {
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+	if (console_loglevel >= loglevel) {
 		__console_tx_nibble((value >> 12U) & 0x0fU);
 		__console_tx_nibble((value >>  8U) & 0x0fU);
 		__console_tx_nibble((value >>  4U) & 0x0fU);
@@ -164,7 +173,7 @@
 
 static void __console_tx_hex32(int loglevel, unsigned int value)
 {
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+	if (console_loglevel >= loglevel) {
 		__console_tx_nibble((value >> 28U) & 0x0fU);
 		__console_tx_nibble((value >> 24U) & 0x0fU);
 		__console_tx_nibble((value >> 20U) & 0x0fU);
@@ -178,7 +187,7 @@
 
 static void __console_tx_string(int loglevel, const char *str)
 {
-	if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+	if (console_loglevel >= loglevel) {
 		unsigned char ch;
 		while((ch = *str++) != '\0') {
 			if (ch == '\n')

Modified: trunk/src/include/console/loglevel.h
==============================================================================
--- trunk/src/include/console/loglevel.h	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/include/console/loglevel.h	Thu Apr  1 11:50:32 2010	(r5344)
@@ -2,11 +2,6 @@
 #define LOGLEVEL_H
 
 /* Safe for inclusion in assembly */
-
-#ifndef ASM_CONSOLE_LOGLEVEL
-#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-#endif
-
 #define BIOS_EMERG      0   /* system is unusable                   */
 #define BIOS_ALERT      1   /* action must be taken immediately     */
 #define BIOS_CRIT       2   /* critical conditions                  */

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/amd/db800/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -33,7 +33,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -98,7 +97,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/amd/norwich/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -32,8 +32,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -95,7 +93,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -39,8 +39,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -35,8 +35,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -112,7 +110,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -17,17 +17,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 0
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"

Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -1,4 +1,3 @@
-#define ASM_CONSOLE_LOGLEVEL 8
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -1,4 +1,3 @@
-#define ASM_CONSOLE_LOGLEVEL 8
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -13,7 +13,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -63,7 +62,7 @@
 void cache_as_ram_main(void)
 {
 	extern void RestartCAR();
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl [] = {
 		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
@@ -105,7 +104,7 @@
 
 	 We use method 1 on Norwich.
 	*/
-	POST_CODE(0x02);
+	post_code(0x02);
 	print_err("POST 02\n");
 	__asm__("wbinvd\n");
 	print_err("Past wbinvd\n");

Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -32,7 +32,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -102,7 +101,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -46,8 +46,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -36,8 +36,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
@@ -132,7 +130,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -37,8 +37,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
@@ -194,7 +192,7 @@
 void cache_as_ram_main(void)
 {
 	int err;
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -52,17 +52,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -18,17 +18,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -33,7 +33,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
@@ -148,7 +147,7 @@
 
 	extern void RestartCAR();
 
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	SystemPreInit();
 	msr_init();
@@ -195,7 +194,7 @@
 	 *
 	 * We use method 1 on Norwich and on this board too.
 	 */
-	POST_CODE(0x02);
+	post_code(0x02);
 	print_err("POST 02\n");
 	__asm__("wbinvd\n");
 	print_err("Past wbinvd\n");

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -45,8 +45,6 @@
 #include "pc80/serial.c"
 #include "console/console.c"
 
-#define post_code(x) outb(x, 0x80)
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

Modified: trunk/src/mainboard/technologic/ts5300/romstage.c
==============================================================================
--- trunk/src/mainboard/technologic/ts5300/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/technologic/ts5300/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -4,7 +4,6 @@
  *   (c) 2006 coresystems GmbH
  */
 
-#define ASM_CONSOLE_LOGLEVEL 6
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>

Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/tyan/s2850/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -13,17 +13,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -17,17 +17,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -12,17 +12,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
-
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"

Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/mainboard/winent/pl6064/romstage.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -34,7 +34,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define POST_CODE(x) outb(x, 0x80)
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -99,7 +98,7 @@
 
 void cache_as_ram_main(void)
 {
-	POST_CODE(0x01);
+	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}

Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/pll_reset.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -115,7 +115,6 @@
 #if USE_GOODRICH_VERSION
 ///////////////////////////////////////////////////////////////////////////////
 // Goodrich Version of pll_reset
-#define POST_CODE(x) outb(x, 0x80)
 
 // PLLCHECK_COMPLETED is the "we've already done this" flag
 #define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
@@ -149,7 +148,7 @@
 	
 		// Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
 		// correct Strap Table.
-		POST_CODE(POST_PLL_INIT);
+		post_code(POST_PLL_INIT);
 		
 		// configure for DDR
 		msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
@@ -157,7 +156,7 @@
 		
 		// Use Manual settings
 		//	UseManual:
-		POST_CODE(POST_PLL_MANUAL);
+		post_code(POST_PLL_MANUAL);
 
 		// DIV settings manually entered.
 		// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
@@ -237,7 +236,7 @@
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 		
 		// You should never get here..... The chip has reset.
-		POST_CODE(POST_PLL_RESET_FAIL);
+		post_code(POST_PLL_RESET_FAIL);
 		while (1);
 
 	} // we haven't configured the PLL; do it now

Modified: trunk/src/northbridge/amd/lx/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/lx/pll_reset.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/northbridge/amd/lx/pll_reset.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -31,12 +31,12 @@
 	print_debug(":");
 	print_debug_hex32(msrGlcpSysRstpll.lo);
 	print_debug("\n");
-	POST_CODE(POST_PLL_INIT);
+	post_code(POST_PLL_INIT);
 
 	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
 		print_debug("Configuring PLL\n");
 		if (manualconf) {
-			POST_CODE(POST_PLL_MANUAL);
+			post_code(POST_PLL_MANUAL);
 			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
 			msrGlcpSysRstpll.hi = PLLMSRhi;
 
@@ -44,7 +44,7 @@
 			msrGlcpSysRstpll.lo = PLLMSRlo;
 		} else {
 			/*automatic configuration (straps) */
-			POST_CODE(POST_PLL_STRAP);
+			post_code(POST_PLL_STRAP);
 			msrGlcpSysRstpll.lo &=
 			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
 			msrGlcpSysRstpll.lo |=
@@ -64,7 +64,7 @@
 
 		/*      You should never get here..... The chip has reset. */
 		print_debug("CONFIGURING PLL FAILURE\n");
-		POST_CODE(POST_PLL_RESET_FAIL);
+		post_code(POST_PLL_RESET_FAIL);
 		__asm__ __volatile__("hlt\n");
 
 	}

Modified: trunk/src/northbridge/amd/lx/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.c	Wed Mar 31 16:57:55 2010	(r5343)
+++ trunk/src/northbridge/amd/lx/raminit.c	Thu Apr  1 11:50:32 2010	(r5344)
@@ -67,7 +67,7 @@
 	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
 	if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
 		print_emerg("Number of module banks not compatible\n");
-		POST_CODE(ERROR_BANK_SET);
+		post_code(ERROR_BANK_SET);
 		hcf();
 	}
 	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
@@ -78,7 +78,7 @@
 	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 	if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
 		print_emerg("Number of device banks not compatible\n");
-		POST_CODE(ERROR_BANK_SET);
+		post_code(ERROR_BANK_SET);
 		hcf();
 	}
 	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
@@ -94,7 +94,7 @@
 	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
 	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
 		print_emerg("Assymetirc DIMM not compatible\n");
-		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
 	banner("SPDBANKDENSITY");
@@ -111,7 +111,7 @@
 	banner("TEST DIMM SIZE>8");
 	if (dimm_size > 8) {	/* 8 is 1GB only support 1GB per DIMM */
 		print_emerg("Only support up to 1 GB per DIMM\n");
-		POST_CODE(ERROR_DENSITY_DIMM);
+		post_code(ERROR_DENSITY_DIMM);
 		hcf();
 	}
 	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
@@ -144,7 +144,7 @@
 	banner("MAXCOLADDR");
 	if (spd_byte > MAX_COL_ADDR) {
 		print_emerg("DIMM page size not compatible\n");
-		POST_CODE(ERROR_SET_PAGE);
+		post_code(ERROR_SET_PAGE);
 		hcf();
 	}
 	banner(">12address test");
@@ -186,7 +186,7 @@
 	/* I don't think you need this check.
 	   if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
 	   print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
-	   POST_CODE(POST_PLL_MEM_FAIL);
+	   post_code(POST_PLL_MEM_FAIL);
 	   hcf();
 	   } */
 
@@ -201,7 +201,7 @@
 	/* current speed > max speed? */
 	if (GeodeLinkSpeed() > speed) {
 		print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
-		POST_CODE(POST_PLL_MEM_FAIL);
+		post_code(POST_PLL_MEM_FAIL);
 		hcf();
 	}
 }
@@ -341,7 +341,7 @@
 		spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
 	} else {
 		print_emerg("DIMM CAS Latencies not compatible\n");
-		POST_CODE(ERROR_DIFF_DIMMS);
+		post_code(ERROR_DIFF_DIMMS);
 		hcf();
 	}
 
@@ -570,41 +570,41 @@
 	uint8_t spd_byte;
 
 	banner("sdram_set_spd_register\n");
-	POST_CODE(POST_MEM_SETUP);	// post_70h
+	post_code(POST_MEM_SETUP);	// post_70h
 
 	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
 	banner("Check DIMM 0");
 	/* Check DIMM is not Register and not Buffered DIMMs. */
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
 		print_emerg("DIMM0 NOT COMPATIBLE\n");
-		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
 	banner("Check DIMM 1");
 	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
 		print_emerg("DIMM1 NOT COMPATIBLE\n");
-		POST_CODE(ERROR_UNSUPPORTED_DIMM);
+		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
 
-	POST_CODE(POST_MEM_SETUP2);	// post_72h
+	post_code(POST_MEM_SETUP2);	// post_72h
 	banner("Check DDR MAX");
 
 	/* Check that the memory is not overclocked. */
 	checkDDRMax();
 
 	/* Size the DIMMS */
-	POST_CODE(POST_MEM_SETUP3);	// post_73h
+	post_code(POST_MEM_SETUP3);	// post_73h
 	banner("AUTOSIZE DIMM 0");
 	auto_size_dimm(DIMM0);
-	POST_CODE(POST_MEM_SETUP4);	// post_74h
+	post_code(POST_MEM_SETUP4);	// post_74h
 	banner("AUTOSIZE DIMM 1");
 	auto_size_dimm(DIMM1);
 
 	/* Set CAS latency */
 	banner("set cas latency");
-	POST_CODE(POST_MEM_SETUP5);	// post_75h
+	post_code(POST_MEM_SETUP5);	// post_75h
 	setCAS();
 
 	/* Set all the other latencies here (tRAS, tRP....) */
@@ -640,7 +640,7 @@
 ;* 9) MRS w/ memory config & reset DLL clear
 ;* 8) DDR SDRAM ready for normal operation
 ;********************************************************************/
-	POST_CODE(POST_MEM_ENABLE);	// post_76h
+	post_code(POST_MEM_ENABLE);	// post_76h
 
 	/* Only enable MTest for TLA memory debug */
 	/*EnableMTest(); */
@@ -650,7 +650,7 @@
 	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == 
 			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
 		print_emerg("No memory in the system\n");
-		POST_CODE(ERROR_NO_DIMMS);
+		post_code(ERROR_NO_DIMMS);
 		hcf();
 	}
 
@@ -760,7 +760,7 @@
 	wrmsr(msrnum, msr);
 
 	print_emerg("DRAM controller init done.\n");
-	POST_CODE(POST_MEM_SETUP_GOOD);	//0x7E
+	post_code(POST_MEM_SETUP_GOOD);	//0x7E
 
 	/* make sure there is nothing stale in the cache */
 	/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */



From stepan at coresystems.de  Fri Apr  2 18:04:02 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Apr 2010 18:04:02 +0200
Subject: [coreboot] [PATCH] remove annoying noisy message
Message-ID: <4BB61572.4060908@coresystems.de>

See patch

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From rminnich at gmail.com  Fri Apr  2 18:09:04 2010
From: rminnich at gmail.com (ron minnich)
Date: Fri, 2 Apr 2010 09:09:04 -0700
Subject: [coreboot] [PATCH] remove annoying noisy message
In-Reply-To: <4BB61572.4060908@coresystems.de>
References: <4BB61572.4060908@coresystems.de>
Message-ID: <p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>

On Fri, Apr 2, 2010 at 9:04 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
> See patch

I'm mixed on this one, but at the same time, I bet there are few
broken devices that return 0 as there were in the old days.

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



From stepan at coresystems.de  Fri Apr  2 18:16:37 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Apr 2010 18:16:37 +0200
Subject: [coreboot] [PATCH] remove annoying noisy message
In-Reply-To: <p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>
References: <4BB61572.4060908@coresystems.de>
	<p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>
Message-ID: <4BB61865.9030604@coresystems.de>

On 4/2/10 6:09 PM, ron minnich wrote:
> On Fri, Apr 2, 2010 at 9:04 AM, Stefan Reinauer <stepan at coresystems.de> wrote:
>   
>> See patch
>>     
> I'm mixed on this one, but at the same time, I bet there are few
> broken devices that return 0 as there were in the old days.
I wonder, what would we do with them if we knew..

Maybe we should only print the message if something else than 0xffffffff
is read? Would that be more appropriate?
0xffffffff is the expected read-back if there is no device, and I think
that case should not be reported as "bad id"

Like the attached one

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From svn at coreboot.org  Fri Apr  2 18:19:00 2010
From: svn at coreboot.org (repository service)
Date: Fri, 02 Apr 2010 18:19:00 +0200
Subject: [coreboot] [FILO] r122 - trunk/filo
Message-ID: <E1NxjaG-0007Qn-03@ra.coresystems.de>

Author: stepan
Date: Fri Apr  2 18:18:59 2010
New Revision: 122
URL: http://tracker.coreboot.org/trac/filo/changeset/122

Log:
As suggested by Wang Qing Pei: Fix FILO compilation without extra parameters on AMD64

Signed-off-by: Wang Qing Pei <wangqingpei at gmail.com>
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/filo/Makefile

Modified: trunk/filo/Makefile
==============================================================================
--- trunk/filo/Makefile	Fri Mar 26 15:32:47 2010	(r121)
+++ trunk/filo/Makefile	Fri Apr  2 18:18:59 2010	(r122)
@@ -41,15 +41,17 @@
 Q := @
 endif
 
-CC = gcc
+CROSS_PREFIX =
+CC = $(CROSS_PREFIX)gcc -m32
+AS = $(CROSS_PREFIX)as --32
+LD = $(CROSS_PREFIX)ld -belf32-i386
+STRIP = $(CROSS_PREFIX)strip
+NM = $(CROSS_PREFIX)nm
 HOSTCC = gcc
 HOSTCXX = g++
 HOSTCFLAGS := -I$(srck) -I$(objk) -pipe
 HOSTCXXFLAGS := -I$(srck) -I$(objk) -pipe
 
-STRIP ?= strip
-NM ?= nm
-
 ifeq ($(strip $(HAVE_DOTCONFIG)),)
 
 all: config



From stepan at coresystems.de  Fri Apr  2 18:19:28 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Fri, 02 Apr 2010 18:19:28 +0200
Subject: [coreboot] patch for avoding amd64 compiling error
In-Reply-To: <m2idf1430311003311032u763e164eh44db55b818edd66c@mail.gmail.com>
References: <m2idf1430311003311032u763e164eh44db55b818edd66c@mail.gmail.com>
Message-ID: <4BB61910.4080603@coresystems.de>

On 3/31/10 7:32 PM, Qing Pei Wang wrote:
> Signed-off-by: Wang Qing Pei <wangqingpei at gmal.com
> <mailto:wangqingpei at gmal.com>>
slightly modified and checked in as r122

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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From mylesgw at gmail.com  Fri Apr  2 18:19:24 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 10:19:24 -0600
Subject: [coreboot] [PATCH] remove annoying noisy message
In-Reply-To: <p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>
References: <4BB61572.4060908@coresystems.de>
	<p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>
Message-ID: <05F8F3D9FC084667B9B303C7F2657FA2@chimp>

> I'm mixed on this one, but at the same time, I bet there are few
> broken devices that return 0 as there were in the old days.

In that case the check could be split, so that the message is only printed
in the cases where it isn't 0xffffffff.  Then only the broken boards would
print the message.

		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 		/* Have we found something?
		 * Some broken boards return 0 if a slot is empty, but
		 * the expected answer is 0xffffffff
 		 */
		if (id == 0xffffffff) {
 			return NULL;
 		}
		if ((id == 0x00000000) || (id == 0x0000ffff) ||
		    (id == 0xffff0000)) {
			printk(BIOS_SPEW, "%s, bad id 0x%x\n",
dev_path(&dummy), id);
 			return NULL;
 		}
 		dev = alloc_dev(bus, &dummy.path);

Thanks,
Myles




From mylesgw at gmail.com  Fri Apr  2 18:21:03 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 10:21:03 -0600
Subject: [coreboot] [PATCH] remove annoying noisy message
In-Reply-To: <4BB61865.9030604@coresystems.de>
References: <4BB61572.4060908@coresystems.de><p2o13426df11004020909r79bf7d4s2aed5bc38e052972@mail.gmail.com>
	<4BB61865.9030604@coresystems.de>
Message-ID: <7C7E00E7D3DB43C7920FA4301CA6A3CA@chimp>

> Maybe we should only print the message if something else than 0xffffffff
> is read? Would that be more appropriate?
> 0xffffffff is the expected read-back if there is no device, and I think
> that case should not be reported as "bad id"
> 
> Like the attached one

Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles




From svn at coreboot.org  Fri Apr  2 18:30:26 2010
From: svn at coreboot.org (repository service)
Date: Fri, 02 Apr 2010 18:30:26 +0200
Subject: [coreboot] [commit] r5345 - trunk/src/devices
Message-ID: <E1NxjlK-0000iK-Ae@ra.coresystems.de>

Author: stepan
Date: Fri Apr  2 18:30:25 2010
New Revision: 5345
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5345

Log:
The error message is misleading, even for a SPEW, because
the slot is empty, it's NOT a bad ID (and the message is
more confusing than helpful even in SPEW)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/devices/pci_device.c

Modified: trunk/src/devices/pci_device.c
==============================================================================
--- trunk/src/devices/pci_device.c	Thu Apr  1 11:50:32 2010	(r5344)
+++ trunk/src/devices/pci_device.c	Fri Apr  2 18:30:25 2010	(r5345)
@@ -910,10 +910,14 @@
 		dummy.path.pci.devfn = devfn;
 		id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 		/* Have we found something?
-		 * Some broken boards return 0 if a slot is empty.
+		 * Some broken boards return 0 if a slot is empty, but
+		 * the expected answer is 0xffffffff
 		 */
-		if ((id == 0xffffffff) || (id == 0x00000000) ||
-		    (id == 0x0000ffff) || (id == 0xffff0000)) {
+		if (id == 0xffffffff) {
+			return NULL;
+		}
+		if ((id == 0x00000000) || (id == 0x0000ffff) ||
+		    (id == 0xffff0000)) {
 			printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id);
 			return NULL;
 		}



From mylesgw at gmail.com  Fri Apr  2 19:55:44 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 11:55:44 -0600
Subject: [coreboot] [PATCH] continue cleaning up log levels
Message-ID: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>

x86_emu_debug.diff:
Change DEBUG for the emulator to DEBUG_EMU to avoid conflicts with DEBUG for
log levels.

loglevel.diff:
Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER
I didn't change their numerical values.  They were rarely used.
BIOS_EMERG, BIOS_ALERT, BIOS_CRIT -> BIOS_ERR
BIOS_NOTICE -> BIOS_INFO
BIOS_NEVER -> BIOS_SPEW+1

loglevel2.diff:
BIOS_ERR -> ERROR
BIOS_WARNING -> WARNING
BIOS_INFO -> INFO
BIOS_DEBUG -> DEBUG
BIOS_SPEW -> SPEW
For 80 character line aficionados, this puts most of the lines back, since
printk_debug(...) is about the same length as printk(DEBUG, ...)

I didn't change llshell in any of these patches.  It would be easy to add.

Abuild tested.
Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From svn at coreboot.org  Fri Apr  2 22:14:21 2010
From: svn at coreboot.org (repository service)
Date: Fri, 02 Apr 2010 22:14:21 +0200
Subject: [coreboot] [commit] r5346 - trunk/src/northbridge/amd/amdk8
Message-ID: <E1NxnG1-0008RW-Ig@ra.coresystems.de>

Author: myles
Date: Fri Apr  2 22:14:21 2010
New Revision: 5346
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5346

Log:
Fix includes for showallroutes.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/northbridge/amd/amdk8/amdk8.h
   trunk/src/northbridge/amd/amdk8/util.c

Modified: trunk/src/northbridge/amd/amdk8/amdk8.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8.h	Fri Apr  2 18:30:25 2010	(r5345)
+++ trunk/src/northbridge/amd/amdk8/amdk8.h	Fri Apr  2 22:14:21 2010	(r5346)
@@ -8,7 +8,7 @@
         #include "amdk8_pre_f.h"
 #endif
 
-#ifndef __PRE_RAM__
+#ifndef __ROMCC__
 void showallroutes(int level, device_t dev);
 #endif
 

Modified: trunk/src/northbridge/amd/amdk8/util.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/util.c	Fri Apr  2 18:30:25 2010	(r5345)
+++ trunk/src/northbridge/amd/amdk8/util.c	Fri Apr  2 22:14:21 2010	(r5346)
@@ -27,12 +27,10 @@
  */
 #ifndef __PRE_RAM__
 #include <console/console.h>
-#include <string.h>
 #include <device/pci.h>
-#include <cpu/amd/amdk8_sysconf.h>
 #include <device/pci_ops.h>
-#include "amdk8.h"
 #endif
+#include "amdk8.h"
 
 /* Function 1 */
 /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at



From svn at coreboot.org  Fri Apr  2 23:39:13 2010
From: svn at coreboot.org (repository service)
Date: Fri, 02 Apr 2010 23:39:13 +0200
Subject: [coreboot] [commit] r5347 - in trunk/src/include: . console
Message-ID: <E1Nxoa9-0001lh-08@ra.coresystems.de>

Author: myles
Date: Fri Apr  2 23:39:12 2010
New Revision: 5347
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5347

Log:
Fix console prototypes for non-romcc boards.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/include/console/console.h
   trunk/src/include/lib.h

Modified: trunk/src/include/console/console.h
==============================================================================
--- trunk/src/include/console/console.h	Fri Apr  2 22:14:21 2010	(r5346)
+++ trunk/src/include/console/console.h	Fri Apr  2 23:39:12 2010	(r5347)
@@ -4,14 +4,17 @@
 #include <stdint.h>
 #include <console/loglevel.h>
 
-#ifndef __PRE_RAM__
+#ifndef __ROMCC__
 void console_init(void);
+void post_code(u8 value);
+void __attribute__ ((noreturn)) die(const char *msg);
+#endif
+
+#ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);
 unsigned char console_rx_byte(void);
 int console_tst_byte(void);
-void post_code(u8 value);
-void __attribute__ ((noreturn)) die(const char *msg);
 #if CONFIG_CONSOLE_VGA == 1
 void vga_console_init(void);
 #endif

Modified: trunk/src/include/lib.h
==============================================================================
--- trunk/src/include/lib.h	Fri Apr  2 22:14:21 2010	(r5346)
+++ trunk/src/include/lib.h	Fri Apr  2 23:39:12 2010	(r5347)
@@ -37,6 +37,7 @@
 
 /* Defined in src/lib/ramtest.c */
 void ram_check(unsigned long start, unsigned long stop);
+void quick_ram_check(void);
 
 /* Defined in src/pc80/serial.c */
 void uart_init(void);



From svn at coreboot.org  Sat Apr  3 00:11:21 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 00:11:21 +0200
Subject: [coreboot] [commit] r5348 - in trunk/src: cpu/amd/model_gx2
	include/console mainboard/advantech/pcm-5820
	mainboard/amd/db800 northbridge/amd/lx southbridge/amd/cs5536
Message-ID: <E1Nxp5F-0000eU-6H@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 00:11:20 2010
New Revision: 5348
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5348

Log:
remove some more warnings

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/amd/model_gx2/vsmsetup.c
   trunk/src/include/console/console.h
   trunk/src/mainboard/advantech/pcm-5820/irq_tables.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/northbridge/amd/lx/pll_reset.c
   trunk/src/northbridge/amd/lx/raminit.c
   trunk/src/southbridge/amd/cs5536/cs5536.c
   trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c

Modified: trunk/src/cpu/amd/model_gx2/vsmsetup.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/vsmsetup.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/cpu/amd/model_gx2/vsmsetup.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -35,7 +35,6 @@
 #include <arch/io.h>
 #include <cbfs.h>
 
-u32 VSA_vrRead(u16 classIndex);
 void do_vsmbios(void);
 
 #define VSA2_BUFFER		0x60000
@@ -150,7 +149,7 @@
 
 /* andrei: Some VSA virtual register helpers: raw read and MSR read. */
 
-u32 VSA_vrRead(u16 classIndex)
+static u32 VSA_vrRead(u16 classIndex)
 {
 	unsigned eax, ebx, ecx, edx;
 	asm volatile (
@@ -166,7 +165,7 @@
 	return eax;
 }
 
-u32 VSA_msrRead(u32 msrAddr)
+static u32 VSA_msrRead(u32 msrAddr)
 {
 	unsigned eax, ebx, ecx, edx;
 	asm volatile (

Modified: trunk/src/include/console/console.h
==============================================================================
--- trunk/src/include/console/console.h	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/include/console/console.h	Sat Apr  3 00:11:20 2010	(r5348)
@@ -44,6 +44,9 @@
 #endif
 
 #ifndef __ROMCC__
+void console_init(void);
+void post_code(u8 value);
+void __attribute__ ((noreturn)) die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
 
 #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS

Modified: trunk/src/mainboard/advantech/pcm-5820/irq_tables.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/irq_tables.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/mainboard/advantech/pcm-5820/irq_tables.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -30,7 +30,7 @@
 	0x1078,			/* Vendor */
 	0x2,			/* Device */
 	0,			/* Crap (miniport) */
-	// { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0xde,			/* Checksum */
 	{
 		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/mainboard/amd/db800/romstage.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -24,6 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
+#include <console/console.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/northbridge/amd/lx/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/lx/pll_reset.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/northbridge/amd/lx/pll_reset.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -72,6 +72,7 @@
 	return;
 }
 
+#if 0 // Unused
 static unsigned int CPUSpeed(void)
 {
 	unsigned int speed;
@@ -84,6 +85,8 @@
 	}
 	return (speed);
 }
+#endif
+
 static unsigned int GeodeLinkSpeed(void)
 {
 	unsigned int speed;
@@ -96,6 +99,8 @@
 	}
 	return (speed);
 }
+
+#if 0 // Unused
 static unsigned int PCISpeed(void)
 {
 	msr_t msr;
@@ -107,3 +112,4 @@
 		return (33);
 	}
 }
+#endif

Modified: trunk/src/northbridge/amd/lx/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/northbridge/amd/lx/raminit.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -514,6 +514,8 @@
 	wrmsr(MC_CF07_DATA, msr);
 }
 
+#undef TLA_MEMORY_DEBUG
+#ifdef TLA_MEMORY_DEBUG
 static void EnableMTest(void)
 {
 	msr_t msr;
@@ -534,6 +536,7 @@
 
 	print_info("Enabled MTest for TLA debug\n");
 }
+#endif
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
@@ -642,8 +645,10 @@
 ;********************************************************************/
 	post_code(POST_MEM_ENABLE);	// post_76h
 
+#ifdef TLA_MEMORY_DEBUG
 	/* Only enable MTest for TLA memory debug */
-	/*EnableMTest(); */
+	EnableMTest();
+#endif
 
 	/* If both Page Size = "Not Installed" we have a problems and should halt. */
 	msr = rdmsr(MC_CF07_DATA);

Modified: trunk/src/southbridge/amd/cs5536/cs5536.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/southbridge/amd/cs5536/cs5536.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -77,7 +77,7 @@
 	{PMS_IO_BASE + PM_SIDD, 0x000008C02},
 	{PMS_IO_BASE + PM_WKD, 0x0000000A0},
 	{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
-	{0, 0, 0}
+	{0, 0}
 };
 
 struct FLASH_DEVICE {
@@ -197,7 +197,7 @@
 /*		Run after VSA init to enable the flash PCI device header */
 /* **/
 /* ***************************************************************************/
-static void enable_ide_nand_flash_header()
+static void enable_ide_nand_flash_header(void)
 {
 	/* Tell VSA to use FLASH PCI header. Not IDE header. */
 	outl(0x80007A40, 0xCF8);

Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -156,7 +156,7 @@
  *
  * See page 412 of the AMD Geode CS5536 Companion Device data book.
  */
-void cs5536_setup_onchipuart1(void)
+static void cs5536_setup_onchipuart1(void)
 {
 	msr_t msr;
 
@@ -196,7 +196,7 @@
 	wrmsr(MDD_UART1_CONF, msr);
 }
 
-void cs5536_setup_onchipuart2(void)
+static void cs5536_setup_onchipuart2(void)
 {
 	msr_t msr;
 



From svn at coreboot.org  Sat Apr  3 00:13:28 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 00:13:28 +0200
Subject: [coreboot] [commit] r5349 - trunk/src/include/console
Message-ID: <E1Nxp7I-0001HJ-A1@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 00:13:27 2010
New Revision: 5349
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5349

Log:
oops, sorry, overlapping work
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/include/console/console.h

Modified: trunk/src/include/console/console.h
==============================================================================
--- trunk/src/include/console/console.h	Sat Apr  3 00:11:20 2010	(r5348)
+++ trunk/src/include/console/console.h	Sat Apr  3 00:13:27 2010	(r5349)
@@ -4,12 +4,6 @@
 #include <stdint.h>
 #include <console/loglevel.h>
 
-#ifndef __ROMCC__
-void console_init(void);
-void post_code(u8 value);
-void __attribute__ ((noreturn)) die(const char *msg);
-#endif
-
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);



From stepan at coresystems.de  Sat Apr  3 00:19:48 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Sat, 03 Apr 2010 00:19:48 +0200
Subject: [coreboot] [PATCH] continue cleaning up log levels
In-Reply-To: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>
References: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>
Message-ID: <4BB66D84.9080908@coresystems.de>

On 4/2/10 7:55 PM, Myles Watson wrote:
> loglevel.diff:
> Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER
I am not convinced that's a good idea. But let's hear what other people
say...
> I didn't change their numerical values.  They were rarely used. 
> BIOS_EMERG, BIOS_ALERT, BIOS_CRIT -> BIOS_ERR
> BIOS_NOTICE -> BIOS_INFO
I don't think we want to just remove log levels like that. Let's rather
fix the messages and choose the right log levels for them.

> BIOS_NEVER -> BIOS_SPEW+1
The whole intent was to make clear to the reader that this is something
that's never seen. ;-)
That doesn't become clear from BIOS_SPEW+1 in my opinion.


> loglevel2.diff:
> BIOS_ERR -> ERROR
> BIOS_WARNING -> WARNING
> BIOS_INFO -> INFO
> BIOS_DEBUG -> DEBUG
> BIOS_SPEW -> SPEW
> For 80 character line aficionados, this puts most of the lines back,
> since printk_debug(...) is about the same length as printk(DEBUG, ...)
I kind of like the fact that they are prefixed, while I see the point
that BIOS_ is a bad prefix. What about LOG_? Because, that's what it is,
log levels.
I like the idea of not abbreviating ERROR to ERR as the only exception
to the rule.

Stefan
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From svn at coreboot.org  Sat Apr  3 00:31:35 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 00:31:35 +0200
Subject: [coreboot] [commit] r5350 - in trunk/src: cpu/amd/model_gx2
	northbridge/amd/amdht northbridge/amd/gx2 southbridge/amd/rs780
Message-ID: <E1NxpOp-0002iE-M6@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 00:31:35 2010
New Revision: 5350
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5350

Log:
remove more warnings.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/amd/model_gx2/cpubug.c
   trunk/src/northbridge/amd/amdht/h3finit.h
   trunk/src/northbridge/amd/amdht/h3ncmn.c
   trunk/src/northbridge/amd/gx2/northbridgeinit.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c

Modified: trunk/src/cpu/amd/model_gx2/cpubug.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/cpubug.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/cpu/amd/model_gx2/cpubug.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -92,7 +92,7 @@
  *
  ****************************************************************************/
 
-void bug784(void)
+static void bug784(void)
 {
 	msr_t msr;
 	//static char *name = "Geode by NSC";
@@ -133,7 +133,7 @@
  *	Modified:
  *
  **************************************************************************/
-void eng1398(void)
+static void eng1398(void)
 {
 	msr_t msr;
 
@@ -164,7 +164,7 @@
  *	Modified:
  *
  **************************************************************************/
-void
+static void
 eng2900(void)
 {
 	msr_t msr;
@@ -248,7 +248,7 @@
 	}
 }
 
-void bug118253(void)
+static void bug118253(void)
 {
 	/* GLPCI PIO Post Control shouldn't be enabled */
 	msr_t msr;
@@ -258,7 +258,7 @@
 	wrmsr(GLPCI_SPARE, msr);
 }
 
-void bug118339(void)
+static void bug118339(void)
 {
 	/* per AMD, do this always */
 	msr_t msr = {0,0};
@@ -337,7 +337,7 @@
 /**	Modified:*/
 /***/
 /****************************************************************************/
-void disablememoryreadorder(void)
+static void disablememoryreadorder(void)
 {	
 	msr_t msr;
 	msr = rdmsr(MC_CF8F_DATA);

Modified: trunk/src/northbridge/amd/amdht/h3finit.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/h3finit.h	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/amdht/h3finit.h	Sat Apr  3 00:31:35 2010	(r5350)
@@ -353,7 +353,7 @@
 	 *
 	 * ---------------------------------------------------------------------------------------
 	 */
-	BOOL (*AMD_CB_CustomizeTrafficDistribution)();
+	BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
 
 
 	/**----------------------------------------------------------------------------------------

Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c
==============================================================================
--- trunk/src/northbridge/amd/amdht/h3ncmn.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/amdht/h3ncmn.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -1041,7 +1041,7 @@
 
 /**----------------------------------------------------------------------------------------
  *
- * void
+ * static void
  * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
  *
  *  Description:
@@ -1058,7 +1058,7 @@
  *
  * ---------------------------------------------------------------------------------------
  */
-void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
+static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
 {
 	u8 curNode;
 	SBDFO linkBase;

Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/northbridgeinit.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/gx2/northbridgeinit.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -704,7 +704,6 @@
 	int i;
 	msr_t msr;
 	uint8_t SysMemCacheProp;
-	uint8_t RegionProp;
 
 	/* Locate SYSMEM entry in GLIU0table */
 	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {

Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -17,6 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
+#endif
+
 #include "rs780_rev.h"
 
 #define NBHTIU_INDEX		0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
@@ -142,7 +146,7 @@
 	}
 }
 
-static void get_cpu_rev()
+static void get_cpu_rev(void)
 {
 	u32 eax;
 
@@ -168,17 +172,17 @@
 		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
 }
 
-static u8 is_famly10()
+static u8 is_famly10(void)
 {
 	return (cpuid_eax(1) & 0xff00000) != 0;
 }
 
-static u8 l3_cache()
+static u8 l3_cache(void)
 {
 	return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
 }
 
-static u8 cpu_core_number()
+static u8 cpu_core_number(void)
 {
 	return (cpuid_ecx(0x80000008) & 0xFF) + 1;
 }
@@ -226,7 +230,7 @@
 	[0xe] = 0xC6,		/* 2.6Ghz HyperTransport 3 only */
 };
 
-static void rs780_htinit()
+static void rs780_htinit(void)
 {
 	/*
 	 * About HT, it has been done in enumerate_ht_chain().
@@ -325,7 +329,7 @@
 *	Function2: DRAM and HT technology Trace mode configuration
 *	Function3: Miscellaneous configuration
 *******************************************************/
-static void k8_optimization()
+static void k8_optimization(void)
 {
 	device_t k8_f0, k8_f2, k8_f3;
 	msr_t msr;
@@ -367,7 +371,7 @@
 #endif	/* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
-void fam10_optimization()
+void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
 	msr_t msr;



From mylesgw at gmail.com  Sat Apr  3 00:27:10 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 16:27:10 -0600
Subject: [coreboot] [PATCH] continue cleaning up log levels
In-Reply-To: <4BB66D84.9080908@coresystems.de>
References: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>
	<4BB66D84.9080908@coresystems.de>
Message-ID: <w2r2831fecf1004021527t6529b9b6pb6d9fa6da8a01562@mail.gmail.com>

On Fri, Apr 2, 2010 at 4:19 PM, Stefan Reinauer <stepan at coresystems.de>wrote:

>  On 4/2/10 7:55 PM, Myles Watson wrote:
>
> loglevel.diff:
> Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER
>
> I am not convinced that's a good idea. But let's hear what other people
> say...
>
They were used so infrequently that they were just noise to me.


>
> I didn't change their numerical values.  They were rarely used.
> BIOS_EMERG, BIOS_ALERT, BIOS_CRIT -> BIOS_ERR
> BIOS_NOTICE -> BIOS_INFO
>
> I don't think we want to just remove log levels like that. Let's rather fix
> the messages and choose the right log levels for them.
>
I think it preserves the meaning.  Emergency, alert, and critical all seem
like errors.  The difference between notice and info seems like splitting
hairs.


>
> BIOS_NEVER -> BIOS_SPEW+1
>
> The whole intent was to make clear to the reader that this is something
> that's never seen. ;-)
> That doesn't become clear from BIOS_SPEW+1 in my opinion.
>
NEVER was only used once or twice in the code.  If it's something that will
be used more often, then I can see your point.  Why don't we just comment
out messages that will never be seen?


>
> loglevel2.diff:
> BIOS_ERR -> ERROR
> BIOS_WARNING -> WARNING
> BIOS_INFO -> INFO
> BIOS_DEBUG -> DEBUG
> BIOS_SPEW -> SPEW
> For 80 character line aficionados, this puts most of the lines back, since
> printk_debug(...) is about the same length as printk(DEBUG, ...)
>
> I kind of like the fact that they are prefixed, while I see the point that
> BIOS_ is a bad prefix. What about LOG_? Because, that's what it is, log
> levels.
>
I think printk works well for the prefix, and I like brevity when it doesn't
interfere with the meaning.  I think we talked about other prefixes some
time in the past and couldn't get agreement.


> I like the idea of not abbreviating ERROR to ERR as the only exception to
> the rule.
>
Good.  I've mis-typed that a lot of times.  I like uniformity.

Thanks,
Myles
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From mylesgw at gmail.com  Sat Apr  3 00:44:42 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 16:44:42 -0600
Subject: [coreboot] [PATCH] continue cleaning up log levels
In-Reply-To: <w2r2831fecf1004021527t6529b9b6pb6d9fa6da8a01562@mail.gmail.com>
References: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>
	<4BB66D84.9080908@coresystems.de>
	<w2r2831fecf1004021527t6529b9b6pb6d9fa6da8a01562@mail.gmail.com>
Message-ID: <n2z2831fecf1004021544p175bc997ue48d4f7ccb78e4d3@mail.gmail.com>

>
>> BIOS_NEVER -> BIOS_SPEW+1
>>
>> The whole intent was to make clear to the reader that this is something
>> that's never seen. ;-)
>> That doesn't become clear from BIOS_SPEW+1 in my opinion.
>>
> NEVER was only used once or twice in the code.  If it's something that will
> be used more often, then I can see your point.  Why don't we just comment
> out messages that will never be seen?
>

I just looked again, and it was only used once.  It makes sense where it was
used, but I don't think it makes sense to use it other places, and I think
naming it with the same prefix and including it in the same list makes that
likely in the future.

I think a comment explaining BIOS_SPEW+1 would work just as well, or this:
BIOS_NEVER -> CONFIG_MAXIMUM_CONSOLE_LOGLEVEL+1

Thanks,
Myles
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From mylesgw at gmail.com  Sat Apr  3 00:20:11 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Fri, 2 Apr 2010 16:20:11 -0600
Subject: [coreboot] [commit] r5348 - in trunk/src: cpu/amd/model_gx2
	include/console mainboard/advantech/pcm-5820
	mainboard/amd/db800 northbridge/amd/lx southbridge/amd/cs5536
In-Reply-To: <E1Nxp5F-0000eU-6H@ra.coresystems.de>
References: <E1Nxp5F-0000eU-6H@ra.coresystems.de>
Message-ID: <y2m2831fecf1004021520s9dce2dfdica15aeea940e6bf@mail.gmail.com>

>
> Modified: trunk/src/include/console/console.h
>
> ==============================================================================
> --- trunk/src/include/console/console.h Fri Apr  2 23:39:12 2010
>  (r5347)
> +++ trunk/src/include/console/console.h Sat Apr  3 00:11:20 2010
>  (r5348)
> @@ -44,6 +44,9 @@
>  #endif
>
>  #ifndef __ROMCC__
> +void console_init(void);
> +void post_code(u8 value);
> +void __attribute__ ((noreturn)) die(const char *msg);
>  int do_printk(int msg_level, const char *fmt, ...)
> __attribute__((format(printf, 2, 3)));
>
This looks redundant as of 5347.


>
> Modified: trunk/src/mainboard/amd/db800/romstage.c
>
> ==============================================================================
> --- trunk/src/mainboard/amd/db800/romstage.c    Fri Apr  2 23:39:12 2010
>      (r5347)
> +++ trunk/src/mainboard/amd/db800/romstage.c    Sat Apr  3 00:11:20 2010
>      (r5348)
> @@ -24,6 +24,7 @@
>  #include <device/pnp_def.h>
>  #include <arch/hlt.h>
>  #include "pc80/serial.c"
> +#include <console/console.h>
>  #include "console/console.c"
>

This shouldn't be necessary, since console.c includes console.h

Thanks,
Myles
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From joe at settoplinux.org  Sat Apr  3 01:19:26 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 02 Apr 2010 19:19:26 -0400
Subject: [coreboot] [PATCH] continue cleaning up log levels
In-Reply-To: <4BB66D84.9080908@coresystems.de>
References: <w2z2831fecf1004021055r600ac38av504270fa3fa4a481@mail.gmail.com>
	<4BB66D84.9080908@coresystems.de>
Message-ID: <4BB67B7E.8010501@settoplinux.org>

On 04/02/2010 06:19 PM, Stefan Reinauer wrote:
> On 4/2/10 7:55 PM, Myles Watson wrote:
>> loglevel.diff:
>> Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER
> I am not convinced that's a good idea. But let's hear what other people
> say...
>> I didn't change their numerical values. They were rarely used.
>> BIOS_EMERG, BIOS_ALERT, BIOS_CRIT -> BIOS_ERR
>> BIOS_NOTICE -> BIOS_INFO
> I don't think we want to just remove log levels like that. Let's rather
> fix the messages and choose the right log levels for them.
>
>> BIOS_NEVER -> BIOS_SPEW+1
> The whole intent was to make clear to the reader that this is something
> that's never seen. ;-)
> That doesn't become clear from BIOS_SPEW+1 in my opinion.
>
>
>> loglevel2.diff:
>> BIOS_ERR -> ERROR
>> BIOS_WARNING -> WARNING
>> BIOS_INFO -> INFO
>> BIOS_DEBUG -> DEBUG
>> BIOS_SPEW -> SPEW
>> For 80 character line aficionados, this puts most of the lines back,
>> since printk_debug(...) is about the same length as printk(DEBUG, ...)
> I kind of like the fact that they are prefixed, while I see the point
> that BIOS_ is a bad prefix. What about LOG_? Because, that's what it is,
> log levels.
> I like the idea of not abbreviating ERROR to ERR as the only exception
> to the rule.
>
> Stefan
>
Yes I agree Stefan, lets get that _BIOS_ out of coreboot.

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From svn at coreboot.org  Sat Apr  3 02:03:12 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 02:03:12 +0200
Subject: [coreboot] [commit] r5351 - trunk/util/romcc
Message-ID: <E1NxqpU-00052k-Op@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 02:03:07 2010
New Revision: 5351
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5351

Log:
Add noreturn attribute to die() in romcc.
This makes life a lot easier for static analyzers such as scan-build.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/util/romcc/romcc.c

Modified: trunk/util/romcc/romcc.c
==============================================================================
--- trunk/util/romcc/romcc.c	Sat Apr  3 00:31:35 2010	(r5350)
+++ trunk/util/romcc/romcc.c	Sat Apr  3 02:03:07 2010	(r5351)
@@ -135,7 +135,7 @@
 
 struct filelist *include_filelist = NULL;
 
-static void die(char *fmt, ...)
+static void __attribute__((noreturn)) die(char *fmt, ...)
 {
 	va_list args;
 



From info at coresystems.de  Sat Apr  3 02:35:33 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 02:35:33 +0200
Subject: [coreboot] build service results for r5348
Message-ID: <E1NxrKn-00079G-7T@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5348 to
the coreboot repository. This caused the following 
changes:

Change Log:
remove some more warnings

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of emulation:qemu-x86 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5348&device=qemu-x86&vendor=emulation&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Apr  3 12:47:55 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 12:47:55 +0200
Subject: [coreboot] build service results for r5349
Message-ID: <E1Ny0tP-0005PJ-Ke@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5349 to
the coreboot repository. This caused the following 
changes:

Change Log:
oops, sorry, overlapping work
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of emulation:qemu-x86 has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Apr  3 14:41:41 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 14:41:41 +0200
Subject: [coreboot] [commit] r5352 - in trunk/src: cpu/via/car cpu/x86/car
	lib mainboard/tyan/s2735 mainboard/via/epia-m700
	mainboard/via/vt8454c northbridge/via/cx700
	northbridge/via/vx800/examples superio/via/vt1211
Message-ID: <E1Ny2fV-0004P9-T8@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 14:41:41 2010
New Revision: 5352
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5352

Log:
remove more warnings
rename amd64_main to stage1_main.. 
copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Deleted:
   trunk/src/mainboard/via/vt8454c/debug.c
Modified:
   trunk/src/cpu/via/car/cache_as_ram.inc
   trunk/src/cpu/x86/car/cache_as_ram.inc
   trunk/src/lib/debug.c
   trunk/src/mainboard/tyan/s2735/romstage.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/mainboard/via/vt8454c/acpi_tables.c
   trunk/src/mainboard/via/vt8454c/romstage.c
   trunk/src/northbridge/via/cx700/cx700_early_smbus.c
   trunk/src/northbridge/via/cx700/cx700_lpc.c
   trunk/src/northbridge/via/cx700/cx700_reset.c
   trunk/src/northbridge/via/cx700/raminit.c
   trunk/src/northbridge/via/vx800/examples/romstage.c
   trunk/src/superio/via/vt1211/vt1211.c

Modified: trunk/src/cpu/via/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.inc	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/cpu/via/car/cache_as_ram.inc	Sat Apr  3 14:41:41 2010	(r5352)
@@ -163,7 +163,7 @@
 	/* We need to set ebp ? No need */
 	movl	%esp, %ebp
 	pushl	%eax  /* bist */
-	call	amd64_main
+	call	stage1_main
 	/* We will not go back */
 
 fixed_mtrr_msr:

Modified: trunk/src/cpu/x86/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/x86/car/cache_as_ram.inc	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/cpu/x86/car/cache_as_ram.inc	Sat Apr  3 14:41:41 2010	(r5352)
@@ -289,7 +289,7 @@
 	/* We need to set ebp ? No need */
 	movl	%esp, %ebp
 	pushl	%eax  /* bist */
-	call	amd64_main
+	call	stage1_main
 	/* We will not go back */
 
 fixed_mtrr_msr:

Modified: trunk/src/lib/debug.c
==============================================================================
--- trunk/src/lib/debug.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/lib/debug.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
 
 static void print_debug_pci_dev(unsigned dev)
 {
@@ -9,17 +29,16 @@
 	print_debug_hex8((dev >> 8) & 7);
 }
 
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
+	for (dev = PCI_DEV(0, 0, 0);
+	     dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+		u32 id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+		    || (((id >> 16) & 0xffff) == 0xffff)
+		    || (((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
 		print_debug_pci_dev(dev);
@@ -32,8 +51,8 @@
 	int i;
 	print_debug_pci_dev(dev);
 	print_debug("\n");
-	
-	for(i = 0; i <= 255; i++) {
+
+	for (i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 			print_debug_hex8(i);
@@ -48,19 +67,42 @@
 	}
 }
 
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
+	for (dev = PCI_DEV(0, 0, 0);
+	     dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+		u32 id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+		    || (((id >> 16) & 0xffff) == 0xffff)
+		    || (((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
 		dump_pci_device(dev);
 	}
 }
+
+
+static inline void dump_io_resources(unsigned port)
+{
+
+	int i;
+	udelay(2000);
+	print_debug_hex16(port);
+	print_debug(":\n");
+	for (i = 0; i < 256; i++) {
+		u8 val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = inb(port);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\n");
+		}
+		port++;
+	}
+}

Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/mainboard/tyan/s2735/romstage.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -65,7 +65,7 @@
 
 #include "cpu/x86/car/copy_and_run.c"
 
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
                 {

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -394,7 +394,7 @@
 }
 
 /* cache_as_ram.inc jumps to here. */
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
 {
 	unsigned cpu_reset = 0;
 	u16 boot_mode;

Modified: trunk/src/mainboard/via/vt8454c/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/via/vt8454c/acpi_tables.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/mainboard/via/vt8454c/acpi_tables.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -52,7 +52,7 @@
 }
 
 
-void acpi_create_via_hpet(acpi_hpet_t * hpet)
+static void acpi_create_via_hpet(acpi_hpet_t * hpet)
 {
 #define HPET_ADDR  0xfe800000ULL
 	acpi_header_t *header = &(hpet->header);
@@ -182,7 +182,7 @@
 	dsdt = (acpi_header_t *) current;
 	current += AmlCode.length;
 	memcpy((void *) dsdt, &AmlCode,AmlCode.length);
-#if DONT_TRUST_IASL
+#ifdef DONT_TRUST_IASL
 	dsdt->checksum = 0;	// don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
 #endif

Modified: trunk/src/mainboard/via/vt8454c/romstage.c
==============================================================================
--- trunk/src/mainboard/via/vt8454c/romstage.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/mainboard/via/vt8454c/romstage.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -30,7 +30,6 @@
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/cx700/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #define DEACTIVATE_CAR 1
@@ -38,9 +37,8 @@
 #include "cpu/x86/car/copy_and_run.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/via/cx700/cx700_early_smbus.c"
-#include "debug.c"
+#include "lib/debug.c"
 
 #include "northbridge/via/cx700/cx700_early_serial.c"
 #include "northbridge/via/cx700/raminit.c"
@@ -126,7 +124,8 @@
 	copy_and_run(0);
 }
 
-void amd64_main(unsigned long bist) {
+void stage1_main(unsigned long bist)
+{
 	main(bist);
 }
 

Modified: trunk/src/northbridge/via/cx700/cx700_early_smbus.c
==============================================================================
--- trunk/src/northbridge/via/cx700/cx700_early_smbus.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/northbridge/via/cx700/cx700_early_smbus.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -57,6 +57,7 @@
 #endif
 
 /* Internal functions */
+#if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register, int loops)
 {
 	/* Check if there actually was an error */
@@ -87,6 +88,7 @@
 		print_err("Host Busy\n");
 	}
 }
+#endif
 
 static void smbus_wait_until_ready(void)
 {
@@ -127,7 +129,7 @@
 	inb(SMBHSTCTL);
 
 	/* fill blocktransfer array */
-	if (dev = 0xd2) {
+	if (dev == 0xd2) {
 		//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
 		outb(0x0d, SMBBLKDAT);
 		outb(0x00, SMBBLKDAT);
@@ -231,7 +233,7 @@
 }
 
 /* Debugging Function */
-#ifdef CONFIG_DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 static void dump_spd_data(const struct mem_controller *ctrl)
 {
 	int dimm, offset, regs;

Modified: trunk/src/northbridge/via/cx700/cx700_lpc.c
==============================================================================
--- trunk/src/northbridge/via/cx700/cx700_lpc.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/northbridge/via/cx700/cx700_lpc.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -84,7 +84,7 @@
  * can't figure out how to do !!!!
  */
 
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
 {
 	/* Debounce LID and PWRBTN# Inputs for 16ms. */
 	pci_write_config8(dev, 0x80, 0x20);
@@ -236,7 +236,7 @@
 
 }
 
-void cx700_read_resources(device_t dev)
+static void cx700_read_resources(device_t dev)
 {
 	struct resource *res;
 
@@ -258,7 +258,7 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-void cx700_set_resources(device_t dev)
+static void cx700_set_resources(device_t dev)
 {
 	struct resource *resource;
 	resource = find_resource(dev, 1);
@@ -266,7 +266,7 @@
 	pci_dev_set_resources(dev);
 }
 
-void cx700_enable_resources(device_t dev)
+static void cx700_enable_resources(device_t dev)
 {
 	/* Enable SuperIO decoding */
 	pci_dev_enable_resources(dev);

Modified: trunk/src/northbridge/via/cx700/cx700_reset.c
==============================================================================
--- trunk/src/northbridge/via/cx700/cx700_reset.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/northbridge/via/cx700/cx700_reset.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -18,6 +18,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 void hard_reset(void)
 {

Modified: trunk/src/northbridge/via/cx700/raminit.c
==============================================================================
--- trunk/src/northbridge/via/cx700/raminit.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/northbridge/via/cx700/raminit.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -103,15 +103,15 @@
 	} while ( 0 )
 
 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
-	{ u8 i, reg; \
-		for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
+	{ u8 j, reg; \
+		for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \
 			printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
-			printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
+			printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \
 			printk(BIOS_DEBUG, "\n"); \
-			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
-			reg &= (bdfspec)[i].mask; \
-			reg |= (bdfspec)[i].val; \
-			pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \
+			reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg); \
+			reg &= (bdfspec)[j].mask; \
+			reg |= (bdfspec)[j].val; \
+			pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg, reg); \
 		} \
 	}
 
@@ -1436,23 +1436,23 @@
 		{ 0x67, ~0x03, 0x01},
 		{ 0x5b, ~0x01, 0x00},
 		{ 0x8d, ~0x02, 0x02},
-		{ 0x97, ~0x80, 0x00},
+		{ 0x97, 0x7f, 0x00},
 		{ 0xd2, ~0x18, 0x00},
 		{ 0xe2, ~0x36, 0x06},
-		{ 0xe4, ~0x80, 0x00},
+		{ 0xe4, 0x7f, 0x00},
 		{ 0xe5, 0x00, 0x40},
 		{ 0xe6, 0x00, 0x20},
-		{ 0xe7, ~0xd0, 0xc0},
+		{ 0xe7, 0x2f, 0xc0},
 		{ 0xec, ~0x08, 0x00}
 	}, b0d17f7[] = {
-		{ 0x4e, ~0x80, 0x80},
+		{ 0x4e, 0x7f, 0x80},
 		{ 0x4f, ~(1 << 6), 1 << 6 },	/* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */
 		{ 0x74, ~0x00, 0x04},		/* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */
 		{ 0x7c, ~0x00, 0x02},		/* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */
 		{ 0xe6, 0x0, 0x04}		// MSI post
 	}, b0d19f0[] = {	/* P2PE */
 		{ 0x42, ~0x08, 0x08},		// Disable HD Audio,
-		{ 0x40, ~0xc0, 0x80}		// 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
+		{ 0x40, 0x3f, 0x80}		// 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
 	}, b0d0f2[] = {
 		{ 0x50, ~0x40, 0x88},
 		{ 0x51, 0x80, 0x7b},

Modified: trunk/src/northbridge/via/vx800/examples/romstage.c
==============================================================================
--- trunk/src/northbridge/via/vx800/examples/romstage.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/northbridge/via/vx800/examples/romstage.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -300,7 +300,7 @@
 
 /* cache_as_ram.inc jump to here
 */
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
 {
 	unsigned cpu_reset = 0;
 	u16 boot_mode;

Modified: trunk/src/superio/via/vt1211/vt1211.c
==============================================================================
--- trunk/src/superio/via/vt1211/vt1211.c	Sat Apr  3 02:03:07 2010	(r5351)
+++ trunk/src/superio/via/vt1211/vt1211.c	Sat Apr  3 14:41:41 2010	(r5352)
@@ -117,7 +117,7 @@
 	}
 }
 
-void vt1211_pnp_enable_resources(device_t dev)
+static void vt1211_pnp_enable_resources(device_t dev)
 {
 	printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev));
 	pnp_enter_ext_func_mode(dev);
@@ -125,7 +125,7 @@
 	pnp_exit_ext_func_mode(dev);
 }
 
-void vt1211_pnp_set_resources(struct device *dev)
+static void vt1211_pnp_set_resources(struct device *dev)
 {
 	int i;
 	struct resource *resource;
@@ -178,7 +178,7 @@
 	pnp_exit_ext_func_mode(dev);
 }
 
-void vt1211_pnp_enable(device_t dev)
+static void vt1211_pnp_enable(device_t dev)
 {
 	if (!dev->enabled) {
 		pnp_enter_ext_func_mode(dev);



From svn at coreboot.org  Sat Apr  3 15:33:02 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 15:33:02 +0200
Subject: [coreboot] [commit] r5353 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr
	mainboard/asus/m2v-mx_se mainboard/via/pc2500e
	northbridge/amd/amdk8 northbridge/via/cn700
	southbridge/via/k8t890 southbridge/via/vt8237r
Message-ID: <E1Ny3TC-0000y3-Co@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 15:33:01 2010
New Revision: 5353
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5353

Log:
remove more warnings.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/amd/mtrr/amd_earlymtrr.c
   trunk/src/cpu/x86/mtrr/earlymtrr.c
   trunk/src/mainboard/asus/m2v-mx_se/Kconfig
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/via/pc2500e/mptable.c
   trunk/src/northbridge/amd/amdk8/debug.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c
   trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
   trunk/src/northbridge/via/cn700/cn700.h
   trunk/src/northbridge/via/cn700/northbridge.c
   trunk/src/northbridge/via/cn700/vga.c
   trunk/src/northbridge/via/cn700/vgabios.c
   trunk/src/southbridge/via/k8t890/k8t890.h
   trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/vt8237r.c
   trunk/src/southbridge/via/vt8237r/vt8237r.h
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c

Modified: trunk/src/cpu/amd/mtrr/amd_earlymtrr.c
==============================================================================
--- trunk/src/cpu/amd/mtrr/amd_earlymtrr.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/cpu/amd/mtrr/amd_earlymtrr.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -42,12 +42,6 @@
         wrmsr(TOP_MEM, msr);
 
 #if defined(CONFIG_XIP_ROM_SIZE)
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-extern unsigned long AUTO_XIP_ROM_BASE;
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
         /* enable write through caching so we can do execute in place
          * on the flash rom.
          */

Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==============================================================================
--- trunk/src/cpu/x86/mtrr/earlymtrr.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -26,6 +26,15 @@
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
+#if defined(CONFIG_XIP_ROM_SIZE)
+# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+   extern unsigned long AUTO_XIP_ROM_BASE;
+#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+# else
+#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+# endif
+#endif
+
 static void disable_var_mtrr(unsigned reg)
 {
 	/* The invalid bit is kept in the mask so we simply
@@ -100,12 +109,6 @@
 	}
 
 #if defined(CONFIG_XIP_ROM_SIZE)
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-extern unsigned long AUTO_XIP_ROM_BASE;
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
 	/* enable write through caching so we can do execute in place
 	 * on the flash rom.
 	 */

Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Sat Apr  3 15:33:01 2010	(r5353)
@@ -29,7 +29,6 @@
 	select SUPERIO_ITE_IT8712F
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
-	select HAVE_HARD_RESET
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -116,12 +116,6 @@
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-#warning No hard_reset implemented for this board!
-void hard_reset(void)
-{
-	print_info("NO HARD RESET. FIX ME!\n");
-}
-
 void soft_reset(void)
 {
 	uint8_t tmp;
@@ -164,7 +158,6 @@
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	msr_t msr;
 	static const uint16_t spd_addr[] = {
 		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
 		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
@@ -176,9 +169,7 @@
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
-	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-	char *p;
-	u8 reg;
+	    (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	sio_init();
 	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/via/pc2500e/mptable.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/mptable.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/mainboard/via/pc2500e/mptable.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -40,7 +40,6 @@
 	struct mp_config_table *mc;
 
 	int bus_num;
-	int i;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));

Modified: trunk/src/northbridge/amd/amdk8/debug.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/debug.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/amd/amdk8/debug.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -20,7 +20,7 @@
 	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0);
@@ -63,7 +63,7 @@
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
-static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
+static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 {
 	int i;
 	print_debug_pci_dev(dev);
@@ -109,7 +109,7 @@
 	}
 }
 
-static void dump_pci_devices_on_bus(unsigned busn)
+static inline void dump_pci_devices_on_bus(unsigned busn)
 {
 	device_t dev;
 	for(dev = PCI_DEV(busn, 0, 0);
@@ -208,7 +208,7 @@
 }
 #endif
 
-static void dump_io_resources(unsigned port)
+static inline void dump_io_resources(unsigned port)
 {
 
 	int i;
@@ -228,7 +228,7 @@
 	}
 }
 
-static void dump_mem(unsigned start, unsigned end)
+static inline void dump_mem(unsigned start, unsigned end)
 {
 	unsigned i;
 	print_debug("dump_mem:");

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -1690,7 +1690,7 @@
 
 static const uint8_t latency_indicies[] = { 25, 23, 9 };
 
-int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
+static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
 {
 	int new_cycle_time, new_latency;
 	int index;
@@ -1938,7 +1938,7 @@
 	return valuex;
 }
 
-int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
+static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
 {
 	int value;
 	int value2;

Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -125,7 +125,7 @@
 }
 
 
-static inline void enable_sse2()
+static inline void enable_sse2(void)
 {
 	unsigned long cr4;
 	cr4 = read_cr4();
@@ -133,7 +133,7 @@
 	write_cr4(cr4);
 }
 
-static inline void disable_sse2()
+static inline void disable_sse2(void)
 {
 	unsigned long cr4;
 	cr4 = read_cr4();

Modified: trunk/src/northbridge/via/cn700/cn700.h
==============================================================================
--- trunk/src/northbridge/via/cn700/cn700.h	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/via/cn700/cn700.h	Sat Apr  3 15:33:01 2010	(r5353)
@@ -19,7 +19,8 @@
  */
 
 #if !defined (__PRE_RAM__)
-static void cn700_noop()
+// HACK
+static inline void cn700_noop(device_t dev)
 {
 }
 #endif

Modified: trunk/src/northbridge/via/cn700/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/cn700/northbridge.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/via/cn700/northbridge.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -202,7 +202,7 @@
 	assign_resources(&dev->link[0]);
 }
 
-static const struct device_operations pci_domain_ops = {
+static struct device_operations pci_domain_ops = {
 	.read_resources   = pci_domain_read_resources,
 	.set_resources    = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
@@ -219,7 +219,7 @@
 {
 }
 
-static const struct device_operations cpu_bus_ops = {
+static struct device_operations cpu_bus_ops = {
 	.read_resources   = cpu_bus_noop,
 	.set_resources    = cpu_bus_noop,
 	.enable_resources = cpu_bus_noop,

Modified: trunk/src/northbridge/via/cn700/vga.c
==============================================================================
--- trunk/src/northbridge/via/cn700/vga.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/via/cn700/vga.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -52,7 +52,7 @@
 	 * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
 	 * This is for compatibility with the VGA ROM's BIOS callbacks.
 	 */
-	memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
+	memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
 
 	printk(BIOS_DEBUG, "Initializing VGA\n");
 
@@ -98,7 +98,7 @@
 	outb(reg8, SR_DATA);
 
 	/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
-	memset(0xf0000, 0, 0x10000);
+	memset((void *)0xf0000, 0, 0x10000);
 }
 
 static const struct device_operations vga_operations = {

Modified: trunk/src/northbridge/via/cn700/vgabios.c
==============================================================================
--- trunk/src/northbridge/via/cn700/vgabios.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/northbridge/via/cn700/vgabios.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -4,7 +4,7 @@
 #include <device/pci_ops.h>
 #undef __KERNEL__
 #include <arch/io.h>
-//#include <printk.h>
+#include <stddef.h>
 #include <string.h>
 #include "vgachip.h"
 #include <cbfs.h>
@@ -176,6 +176,7 @@
 		/* put the stack at the end of page zero. 
 		 * that way we can easily share it between real and protected, 
 		 * since the 16-bit ESP at segment 0 will work for any case. 
+		 */
 		/* Setup a stack */
 		"	mov	$0x0, %ax	\n"
 		"	mov	%ax, %ss	\n"
@@ -271,6 +272,7 @@
 		/* put the stack at the end of page zero. 
 		 * that way we can easily share it between real and protected, 
 		 * since the 16-bit ESP at segment 0 will work for any case. 
+		 */
 		/* Setup a stack */
 		"	mov	$0x0, %ax	\n"
 		"	mov	%ax, %ss	\n"
@@ -336,7 +338,7 @@
 {
 	device_t dev;
 	unsigned long busdevfn;
-	unsigned int rom = 0;
+	unsigned char *rom;
 	unsigned char *buf;
 	unsigned int size = 64*1024;
 	int i;
@@ -357,9 +359,9 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
-	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
-	printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
+	rom = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
+	pci_write_config32(dev, PCI_ROM_ADDRESS, (u32)rom | 1);
+	printk(BIOS_DEBUG, "rom base: %p\n", rom);
 
 	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -635,7 +637,7 @@
 	// and get it that way. But that's really disgusting.
 	for (i = 0; i < 256; i++) {
 		idts[i].cs = 0;
-		codeptr = (char*) 4096 + i * codesize;
+		codeptr = (unsigned char*) 4096 + i * codesize;
 		idts[i].offset = (unsigned) codeptr;
 		memcpy(codeptr, &idthandle, codesize);
 		intbyte = codeptr + 3;
@@ -648,7 +650,7 @@
 	// int10. 
 	// calling convention here is the same as INTs, we can reuse
 	// the int entry code.
-	codeptr = (char*) 0xff065;
+	codeptr = (unsigned char*) 0xff065;
 	memcpy(codeptr, &idthandle, codesize);
 	intbyte = codeptr + 3;
 	*intbyte = 0x42; /* int42 is the relocated int10 */
@@ -657,7 +659,7 @@
 	   TF bit is set upon call to real mode */
 	idts[1].cs = 0;
 	idts[1].offset = 16384;
-	memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+	memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle);
 
 	
 }
@@ -687,16 +689,7 @@
 	unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, 
 	unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
 {
-	unsigned long edi = *pedi;
-	unsigned long esi = *pesi;
-	unsigned long ebp = *pebp;
-	unsigned long esp = *pesp;
-	unsigned long ebx = *pebx;
-	unsigned long edx = *pedx;
-	unsigned long ecx = *pecx;
-	unsigned long eax = *peax;
-	unsigned long flags = *pflags;
-	unsigned short func = (unsigned short) eax;
+	unsigned short func = (unsigned short) (*peax);
 	int retval = 0;
 	unsigned short devid, vendorid, devfn;
 	short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */

Modified: trunk/src/southbridge/via/k8t890/k8t890.h
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890.h	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/k8t890/k8t890.h	Sat Apr  3 15:33:01 2010	(r5353)
@@ -40,8 +40,12 @@
 
 #include <device/device.h>
 
+#if 0
 extern void writeback(struct device *dev, u16 where, u8 what);
 extern void dump_south(device_t dev);
+#endif
+#include <southbridge/via/vt8237r/vt8237r.h>
+
 
 int k8m890_host_fb_size_get(void);
 //void k8m890_host_fb_direct_set(uint32_t fb_address);

Modified: trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_ctrl.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/k8t890/k8t890_ctrl.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -29,7 +29,7 @@
 
 static void vt8237r_cfg(struct device *dev, struct device *devsb)
 {
-	u8 regm, regm2, regm3;
+	u8 regm, regm3;
 
 	device_t devfun3;
 

Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_early_car.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -59,6 +59,7 @@
 	pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
 
 	/* check if connected non coherent, initcomplete (find the SB on K8 side) */
+	ldtnr = 0;
 	if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
 		ldtnr = 0;
 	} else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {

Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -22,12 +22,13 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include "vt8237r.h"
 
 /* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */
 
 static void vt8237_cfg(struct device *dev)
 {
-	u8 regm, regm2, regm3;
+	u8 regm, regm3;
 	device_t devfun3;
 
 	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -69,6 +70,7 @@
 	regm = pci_read_config8(devfun3, 0x83);
 	pci_write_config8(dev, 0x63, regm);
 
+	// FIXME is this really supposed to be regm3?
 	regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
 	pci_write_config8(dev, 0x64, regm);
 
@@ -167,8 +169,6 @@
 	pci_write_config8(dev, 0x4f, 0x43);
 }
 
-extern void dump_south(device_t dev);
-
 static void ctrl_init(struct device *dev)
 {
 	/*

Modified: trunk/src/southbridge/via/vt8237r/vt8237r.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237r.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -21,6 +21,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include "vt8237r.h"
 #include "chip.h"
 
 /*
@@ -28,11 +29,6 @@
  *		VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
  */
 
-void hard_reset(void)
-{
-	printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n");
-}
-
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7
 void writeback(struct device *dev, u16 where, u8 what)
 {

Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r.h	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237r.h	Sat Apr  3 15:33:01 2010	(r5353)
@@ -103,4 +103,9 @@
 #endif
 ;
 
+#ifndef __PRE_RAM__
+void writeback(struct device *dev, u16 where, u8 what);
+void dump_south(device_t dev);
+#endif
+
 #endif

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -61,8 +61,9 @@
 
 	PRINT_DEBUG("Waiting until SMBus ready\n");
 
-	loops = 0;
 	/* Yes, this is a mess, but it's the easiest way to do it. */
+	/* XXX not so messy, but an explanation of the hack would have been better */
+	loops = 0;
 	while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
 		++loops;
 
@@ -464,6 +465,8 @@
 	pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */
 
 	/* Yes, this is a mess, but it's the easiest way to do it. */
+	/* XXX not so messy, but an explanation of the hack would have been better */
+	loops = 0;
 	while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0)
 	       && (loops < LAN_TIMEOUT)) {
 		++loops;

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_ide.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_ide.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -35,10 +35,8 @@
 	struct southbridge_via_vt8237r_config *sb =
 	    (struct southbridge_via_vt8237r_config *)dev->chip_info;
 
-	u8 enables, reg8;
+	u8 enables;
 	u32 cablesel;
-	device_t lpc_dev;
-	int i, j;
 
 	printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
 		    sb->ide0_enable ? "enabled" : "disabled");
@@ -98,6 +96,8 @@
 	pci_write_config32(dev, IDE_UDMA, cablesel);
 
 #if CONFIG_EPIA_VT8237R_INIT
+	device_t lpc_dev;
+
 	/* Set PATA Output Drive Strength */
 	lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 				    PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sat Apr  3 14:41:41 2010	(r5352)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Sat Apr  3 15:33:01 2010	(r5353)
@@ -34,7 +34,6 @@
 #include "vt8237r.h"
 #include "chip.h"
 
-extern void dump_south(device_t dev);
 static void southbridge_init_common(struct device *dev);
 
 #if CONFIG_EPIA_VT8237R_INIT
@@ -248,7 +247,7 @@
 
 static void vt8237r_init(struct device *dev)
 {
-	u8 enables, reg8;
+	u8 enables;
 	
 #if CONFIG_EPIA_VT8237R_INIT
 	printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");



From info at coresystems.de  Sat Apr  3 15:47:45 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 15:47:45 +0200
Subject: [coreboot] build service results for r5352
Message-ID: <E1Ny3hR-0004JN-MW@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5352 to
the coreboot repository. This caused the following 
changes:

Change Log:
remove more warnings
rename amd64_main to stage1_main..
copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of asus:mew-am has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-d has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-d&vendor=asus&num=2
Compilation of asus:p2b-ds has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-f&vendor=asus&num=2
Compilation of asus:p2b-ls has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-ls&vendor=asus&num=2
Compilation of asus:p3b-f has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p3b-f&vendor=asus&num=2
Compilation of azza:pt-6ibd has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=pt-6ibd&vendor=azza&num=2
Compilation of biostar:m6tba has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of gigabyte:ga-6bxc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of mitac:6513wu has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=6513wu&vendor=mitac&num=2
Compilation of msi:ms6119 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6156 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6156&vendor=msi&num=2
Compilation of soyo:sy-6ba-plus-iii has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=sy-6ba-plus-iii&vendor=soyo&num=2
Compilation of tyan:s1846 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=s1846&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Sat Apr  3 16:02:48 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 16:02:48 +0200
Subject: [coreboot] build service results for r5353
Message-ID: <E1Ny3w0-0006zB-Pr@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5353 to
the coreboot repository. This caused the following 
changes:

Change Log:
remove more warnings.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=atc-6220&vendor=a-trend&num=2
Compilation of a-trend:atc-6240 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=atc-6240&vendor=a-trend&num=2
Compilation of abit:be6-ii_v2_0 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=be6-ii_v2_0&vendor=abit&num=2
Compilation of asus:mew-am is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=mew-am&vendor=asus&num=2
Compilation of asus:mew-vm is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=mew-vm&vendor=asus&num=2
Compilation of asus:p2b is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b&vendor=asus&num=2
Compilation of asus:p2b-d is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-d&vendor=asus&num=2
Compilation of asus:p2b-ds is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-ds&vendor=asus&num=2
Compilation of asus:p2b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-f&vendor=asus&num=2
Compilation of asus:p2b-ls is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-ls&vendor=asus&num=2
Compilation of asus:p3b-f is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p3b-f&vendor=asus&num=2
Compilation of azza:pt-6ibd is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=pt-6ibd&vendor=azza&num=2
Compilation of biostar:m6tba is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=m6tba&vendor=biostar&num=2
Compilation of compaq:deskpro_en_sff_p600 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=deskpro_en_sff_p600&vendor=compaq&num=2
Compilation of gigabyte:ga-6bxc is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ga-6bxc&vendor=gigabyte&num=2
Compilation of mitac:6513wu is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=6513wu&vendor=mitac&num=2
Compilation of msi:ms6119 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6119&vendor=msi&num=2
Compilation of msi:ms6147 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6147&vendor=msi&num=2
Compilation of msi:ms6156 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6156&vendor=msi&num=2
Compilation of soyo:sy-6ba-plus-iii is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=sy-6ba-plus-iii&vendor=soyo&num=2
Compilation of tyan:s1846 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=s1846&vendor=tyan&num=2
Compilation of via:epia-n has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=epia-n&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Apr  3 16:19:22 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 16:19:22 +0200
Subject: [coreboot] [commit] r5354 - trunk/src/lib
Message-ID: <E1Ny4C2-00008A-H1@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 16:19:22 2010
New Revision: 5354
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5354

Log:
no need to udelay()

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/lib/debug.c

Modified: trunk/src/lib/debug.c
==============================================================================
--- trunk/src/lib/debug.c	Sat Apr  3 15:33:01 2010	(r5353)
+++ trunk/src/lib/debug.c	Sat Apr  3 16:19:22 2010	(r5354)
@@ -88,7 +88,6 @@
 {
 
 	int i;
-	udelay(2000);
 	print_debug_hex16(port);
 	print_debug(":\n");
 	for (i = 0; i < 256; i++) {



From info at coresystems.de  Sat Apr  3 16:34:47 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 16:34:47 +0200
Subject: [coreboot] build service results for r5354
Message-ID: <E1Ny4Qx-0002WR-0Z@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5354 to
the coreboot repository. This caused the following 
changes:

Change Log:
no need to udelay()

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of a-trend:atc-6220 has been fixed
Compilation of a-trend:atc-6240 has been fixed
Compilation of abit:be6-ii_v2_0 has been fixed
Compilation of asus:mew-am has been fixed
Compilation of asus:mew-vm has been fixed
Compilation of asus:p2b has been fixed
Compilation of asus:p2b-d has been fixed
Compilation of asus:p2b-ds has been fixed
Compilation of asus:p2b-f has been fixed
Compilation of asus:p2b-ls has been fixed
Compilation of asus:p3b-f has been fixed
Compilation of azza:pt-6ibd has been fixed
Compilation of biostar:m6tba has been fixed
Compilation of compaq:deskpro_en_sff_p600 has been fixed
Compilation of gigabyte:ga-6bxc has been fixed
Compilation of mitac:6513wu has been fixed
Compilation of msi:ms6119 has been fixed
Compilation of msi:ms6147 has been fixed
Compilation of msi:ms6156 has been fixed
Compilation of soyo:sy-6ba-plus-iii has been fixed
Compilation of tyan:s1846 has been fixed
Compilation of via:epia-n is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5354&device=epia-n&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Sat Apr  3 17:41:27 2010
From: svn at coreboot.org (repository service)
Date: Sat, 03 Apr 2010 17:41:27 +0200
Subject: [coreboot] [commit] r5355 - trunk/src/southbridge/via/vt8237r
Message-ID: <E1Ny5TT-0001id-IA@ra.coresystems.de>

Author: stepan
Date: Sat Apr  3 17:41:27 2010
New Revision: 5355
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5355

Log:
device_t wants device/device.h
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/southbridge/via/vt8237r/vt8237r.h

Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r.h	Sat Apr  3 16:19:22 2010	(r5354)
+++ trunk/src/southbridge/via/vt8237r/vt8237r.h	Sat Apr  3 17:41:27 2010	(r5355)
@@ -104,6 +104,7 @@
 ;
 
 #ifndef __PRE_RAM__
+#include <device/device.h>
 void writeback(struct device *dev, u16 where, u8 what);
 void dump_south(device_t dev);
 #endif



From info at coresystems.de  Sat Apr  3 17:56:50 2010
From: info at coresystems.de (coreboot information)
Date: Sat, 03 Apr 2010 17:56:50 +0200
Subject: [coreboot] build service results for r5355
Message-ID: <E1Ny5iM-0004KK-Sx@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5355 to
the coreboot repository. This caused the following 
changes:

Change Log:
device_t wants device/device.h
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia-n has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From adi_sav at yahoo.com  Sun Apr  4 20:47:00 2010
From: adi_sav at yahoo.com (Adrian George Sav)
Date: Sun, 4 Apr 2010 11:47:00 -0700 (PDT)
Subject: [coreboot] Do you recommend flashing coreboot on ASUS P5PD2 deluxe?
Message-ID: <651225.3122.qm@web55304.mail.re4.yahoo.com>



 
  
  
  
  
  
  
   
  
 
  
   Step 1
   
   Board vendor: ASUS
   Board name: P5LD2 Deluxe
   CPU: Intel Pentium D830, 3.0 GHz
   North Bridge: ?Intel 945 chipset
   South bridge:  ?ICH7R
   
   Step 2 "lspci -tvnn"
   
   -[0000:00]-+-00.0 ?Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
    ??????????+-01.0-[04]----00.0 ?nVidia Corporation G92 [GeForce 9800 GT] [10de:0614]
    ??????????+-1b.0 ?Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8]
    ??????????+-1c.0-[03]--
    ??????????+-1c.4-[02]----00.0 ?Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller [11ab:4362]
    ??????????+-1d.0 ?Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
    ??????????+-1d.1 ?Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9]
    ??????????+-1d.2 ?Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca]
    ??????????+-1d.3 ?Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb]
    ??????????+-1d.7 ?Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc]
    ??????????+-1e.0-[01]--
    ??????????+-1f.0 ?Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
    ??????????+-1f.1 ?Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
    ??????????+-1f.2 ?Intel Corporation N10/ICH7 Family SATA IDE Controller [8086:27c0]
    ??????????\-1f.3 ?Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da]
   
   Step?3
   Winbond W83627EHG-A
   
   Step 4 flashrom -V
   
   flashrom v0.9.1-r946
   No coreboot table found.
   DMI string system-manufacturer: "System manufacturer"
   DMI string system-product-name: "System Product Name"
   DMI string system-version: "System Version"
   DMI string baseboard-manufacturer: "ASUSTeK Computer INC."
   DMI string baseboard-product-name: "P5LD2-Deluxe"
   DMI string baseboard-version: "Rev 1.xx"
   DMI string chassis-type: "<OUT OF SPEC>"
   Found chipset "Intel ICH7/ICH7R", enabling flash write... 
   0xfff80000/0xffb80000 FWH IDSEL: 0x0
   0xfff00000/0xffb00000 FWH IDSEL: 0x0
   0xffe80000/0xffa80000 FWH IDSEL: 0x1
   0xffe00000/0xffa00000 FWH IDSEL: 0x1
   0xffd80000/0xff980000 FWH IDSEL: 0x2
   0xffd00000/0xff900000 FWH IDSEL: 0x2
   0xffc80000/0xff880000 FWH IDSEL: 0x3
   0xffc00000/0xff800000 FWH IDSEL: 0x3
   0xff700000/0xff300000 FWH IDSEL: 0x4
   0xff600000/0xff200000 FWH IDSEL: 0x5
   0xff500000/0xff100000 FWH IDSEL: 0x6
   0xff400000/0xff000000 FWH IDSEL: 0x7
   0xfff80000/0xffb80000 FWH decode enabled
   0xfff00000/0xffb00000 FWH decode enabled
   0xffe80000/0xffa80000 FWH decode disabled
   0xffe00000/0xffa00000 FWH decode disabled
   0xffd80000/0xff980000 FWH decode disabled
   0xffd00000/0xff900000 FWH decode disabled
   0xffc80000/0xff880000 FWH decode disabled
   0xffc00000/0xff800000 FWH decode disabled
   0xff700000/0xff300000 FWH decode disabled
   0xff600000/0xff200000 FWH decode disabled
   0xff500000/0xff100000 FWH decode disabled
   0xff400000/0xff000000 FWH decode disabled
   Maximum FWH chip size: 0x100000 bytes
   BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
   
   Root Complex Register Block address = 0xfed1c000
   GCS = 0x200c64: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC)
   Top Swap : not enabled
   OK.
   This chipset supports the following protocols: FWH.
   Calibrating delay loop... 799M loops per second, 100 myus = 200 us. OK.
   Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ASD AE49F2008, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT26F004, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT29C512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT29C020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for AMIC A29002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMIC A29002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMIC A29040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for EMST F49B002UA, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Eon EN25B05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B05T, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B10T, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B20T, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B40T, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25D16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN25F32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Eon EN29F010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Intel 28F004S5, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x43, id2 0x5d
   Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for Macronix MX25L512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF040B, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST SST28SF040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST29EE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST29LE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST29EE020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST29LE020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39SF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39SF010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39SF020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39SF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39VF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39VF010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39VF020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39VF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST39VF080, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x43, id2 0x5d
   Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address 0xfff00000.
   Lock status for 0x000000 (size 0x010000) is 00, full access
   Lock status for 0x010000 (size 0x010000) is 00, full access
   Lock status for 0x020000 (size 0x010000) is 00, full access
   Lock status for 0x030000 (size 0x010000) is 00, full access
   Lock status for 0x040000 (size 0x010000) is 00, full access
   Lock status for 0x050000 (size 0x010000) is 00, full access
   Lock status for 0x060000 (size 0x010000) is 00, full access
   Lock status for 0x070000 (size 0x010000) is 00, full access
   Lock status for 0x080000 (size 0x010000) is 00, full access
   Lock status for 0x090000 (size 0x010000) is 00, full access
   Lock status for 0x0a0000 (size 0x010000) is 00, full access
   Lock status for 0x0b0000 (size 0x010000) is 00, full access
   Lock status for 0x0c0000 (size 0x010000) is 00, full access
   Lock status for 0x0d0000 (size 0x010000) is 00, full access
   Lock status for 0x0e0000 (size 0x010000) is 00, full access
   Lock status for 0x0f0000 (size 0x010000) is 00, full access
   Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff
   Probing for SST SST49LF020, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SST SST49LF020A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SST SST49LF040, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SST SST49LF040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for ST M25P05-A, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P05.RES, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P10-A, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P10.RES, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P40-old, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M25P128, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST M29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29F400BT, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29W010B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29W040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M29W512B, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x43, id2 0x5d
   Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x43, id2 0x5d
   Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x24, id2 0xfc
   Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff
   Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x43, id2 0x5d
   Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
   Probing for ST M50LPW116, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W25x10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W25x64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Winbond W29C011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W29C020C, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W29C040P, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W29EE011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W39V040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for Winbond W39V040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for Winbond W39V040C, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for Winbond W49F002U, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible.
   Probing for Winbond W49V002A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible.
   Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a
   Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible.
   ===
   This flash part has status UNTESTED for operations: ERASE
   Please email a report to flashrom at flashrom.org if any of the above operations
   work correctly for you with this flash part. Please include the flashrom
   output with the additional -V option for all operations you tested (-V, -rV,
   -wV, -EV), and mention which mainboard or programmer you tested.
   Thanks for your help!
   ===
   No operations were specified.
   
   
   
   Step 5
   
   http://www.asus.com/Product.aspx?P_ID=qFHXXacaSsviIIxI
  
 


      
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From ataya65 at googlemail.com  Sun Apr  4 21:31:14 2010
From: ataya65 at googlemail.com (ataya65 at googlemail.com)
Date: Sun, 04 Apr 2010 21:31:14 +0200
Subject: [coreboot] Asrock Mainboard Support
Message-ID: <4BB8E902.4010808@googlemail.com>

As suggested in your homepage i would like to send  you the outputs of 
lspci; lspci -tvnn; superiotool -dV; flashrom -V,  further i attached 
the BIOS-Information,  output of dmesg and specificationd i got from the 
(Hardware lister).

The URL to my Mainboard manf. is: 
http://www.asrock.com/mb/overview.asp?Model=K10N78


*_BIOS:_*
vendor: American Megatrends Inc.
version: P1.90 (12/30/2009)
size: 64KiB
capacity: 960KiB
capabilities:
     PCI bus,
     BIOS EEPROM can be upgraded,
     BIOS shadowing,
     Booting from CD-ROM/DVD,
     Selectable boot path,
     BIOS ROM is socketed,
     Enhanced Disk Drive extensions,
     5.25" 1.2MB floppy,
     3.5" 720KB floppy,
     3.5" 2.88MB floppy,
     Print Screen key,
     i8042 keyboard controller,
     INT14 serial line control,
     INT17 printer control,
     INT10 CGA/Mono video,
     ACPI,
     USB legacy emulation,
     Booting from LS-120,
     Booting from ATAPI ZIP,
     BIOS boot specification,
     Function-key initiated network service boot






*_lspci -tvnn_*
-[0000:00]-+-00.0  nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller [10de:0754]
            +-01.0  nVidia Corporation MCP78S [GeForce 8200] LPC Bridge 
[10de:075c]
            +-01.1  nVidia Corporation MCP78S [GeForce 8200] SMBus 
[10de:0752]
            +-01.2  nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller [10de:0751]
            +-01.3  nVidia Corporation MCP78S [GeForce 8200] 
Co-Processor [10de:0753]
            +-01.4  nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller [10de:0568]
            +-02.0  nVidia Corporation MCP78S [GeForce 8200] OHCI USB 
1.1 Controller [10de:077b]
            +-02.1  nVidia Corporation MCP78S [GeForce 8200] EHCI USB 
2.0 Controller [10de:077c]
            +-04.0  nVidia Corporation MCP78S [GeForce 8200] OHCI USB 
1.1 Controller [10de:077d]
            +-04.1  nVidia Corporation MCP78S [GeForce 8200] EHCI USB 
2.0 Controller [10de:077e]
            +-06.0  nVidia Corporation MCP78S [GeForce 8200] IDE [10de:0759]
            +-07.0  nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S High 
Definition Audio [10de:0774]
            +-08.0-[01]--
            +-09.0  nVidia Corporation MCP78S [GeForce 8200] AHCI 
Controller [10de:0ad4]
            +-0a.0  nVidia Corporation MCP77 Ethernet [10de:0760]
            +-0b.0-[02]----00.0  nVidia Corporation GeForce 8200 [10de:0849]
            +-10.0-[03]----00.0  nVidia Corporation GeForce 8400 GS 
[10de:0422]
            +-12.0-[04]--
            +-13.0-[05]--
            +-14.0-[06]--
            +-18.0  Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] HyperTransport Configuration [1022:1200]
            +-18.1  Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Address Map [1022:1201]
            +-18.2  Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] DRAM Controller [1022:1202]
            +-18.3  Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Miscellaneous Control [1022:1203]
            \-18.4  Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Link Control [1022:1204]





*_lspci_*
00:00.0 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller (rev a2)
00:01.0 ISA bridge: nVidia Corporation MCP78S [GeForce 8200] LPC Bridge 
(rev a2)
00:01.1 SMBus: nVidia Corporation MCP78S [GeForce 8200] SMBus (rev a1)
00:01.2 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller (rev a1)
00:01.3 Co-processor: nVidia Corporation MCP78S [GeForce 8200] 
Co-Processor (rev a2)
00:01.4 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory 
Controller (rev a1)
00:02.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI 
USB 1.1 Controller (rev a1)
00:02.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI 
USB 2.0 Controller (rev a1)
00:04.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI 
USB 1.1 Controller (rev a1)
00:04.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI 
USB 2.0 Controller (rev a1)
00:06.0 IDE interface: nVidia Corporation MCP78S [GeForce 8200] IDE (rev a1)
00:07.0 Audio device: nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S 
High Definition Audio (rev a1)
00:08.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge 
(rev a1)
00:09.0 SATA controller: nVidia Corporation MCP78S [GeForce 8200] AHCI 
Controller (rev a2)
00:0a.0 Ethernet controller: nVidia Corporation MCP77 Ethernet (rev a2)
00:0b.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express 
Bridge (rev a1)
00:10.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express 
Bridge (rev a1)
00:12.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express 
Bridge (rev a1)
00:13.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge 
(rev a1)
00:14.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge 
(rev a1)
00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] HyperTransport Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Miscellaneous Control
00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, 
Athlon64, Sempron] Link Control
02:00.0 VGA compatible controller: nVidia Corporation GeForce 8200 (rev a2)
03:00.0 VGA compatible controller: nVidia Corporation GeForce 8400 GS 
(rev a1)



_*superiotool -dV*_
superiotool r4931
Probing for ALi Super I/O at 0x3f0...
   Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
   Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
   Failed. Returned data: vid=0x0400, id=0x6388
Probing for Fintek Super I/O at 0x4e...
   Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
   Failed. Returned data: id=0x8863, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
   Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
   Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
   Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
   Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
   Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
   Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e
Register dump:
idx 20 21 22 23 24 25 26 27  28 29 2a 2b 2c 2d 2e 2f
val 88 63 ff 00 04 00 00 ff  70 03 00 00 02 40 00 ff
def 88 MM ff 00 MM 00 MM RR  50 04 00 RR 00 21 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 00 00 00 02 0e 00 ff  00 00
def 01 03 f0 06 02 8e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 00 03 78 07 04 3f
def 01 03 78 07 04 3f
LDN 0x02 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (COM2)
idx 30 60 61 70 f0 f1
val 00 00 00 00 00 00
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 0c 82
def 01 00 60 00 64 01 0c 83
LDN 0x06 (Serial flash interface)
idx 30 62 63
val 00 ff ff
def 00 00 00
LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f7
val 01 02 01 03 30 00 e1 04  00 00 ff ff ff 00
def 00 02 01 03 30 09 ff 00  00 00 ff 00 00 00
LDN 0x08 (WDTO#, PLED)
idx 30 f5 f6 f7
val 01 00 00 00
def 00 00 00 00
LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
idx 30 e0 e1 e2 e3 e4 e5 f0  f1 f2 f3 f4 f5 f6 f7
val 05 ff ff ff ff 09 00 ff  ff ff 40 4f cc 00 00
def 00 ff 00 00 ff 00 00 ff  00 00 00 ff 00 00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 f2 f3 f4 f6 f7
val 00 00 01 00 00 03 00 00  0c 00 09 7c 00 00 00 00
def 00 00 01 00 ff 08 00 RR  00 00 RR 7c 00 00 00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0 f1
val 01 02 90 00 c1 3f
def 00 00 00 00 c1 00
Probing for Winbond Super I/O (init=0x88) at 0x4e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
   Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff





_*flashrom -V*_
flashrom v0.9.1-r931
No coreboot table found.
DMI string system-manufacturer: "To Be Filled By O.E.M."
DMI string system-product-name: "To Be Filled By O.E.M."
DMI string system-version: "To Be Filled By O.E.M."
DMI string baseboard-manufacturer: "ASRock"
DMI string baseboard-product-name: "K10N78"
DMI string baseboard-version: "                      "
DMI string chassis-type: "Desktop"
Found chipset "NVIDIA MCP78S", enabling flash write... This chipset is 
not really supported yet. Guesswork...
ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0
Guessed flash bus type is SPI
Found SMBus device 10de:0752 at 00:01:1
SPI BAR is at 0xf8e80000, after clearing low bits BAR is at 0xf8e80000
Mapping MCP67 SPI at 0xf8e80000, unaligned size 0x544.
SPI control is 0xc04a, enable=0, idle=0
Please send the output of "flashrom -V" to flashrom at flashrom.org to help 
us finish support for your chipset. Thanks.
SPI on this chipset is not supported yet.
OK.
This chipset supports the following protocols: None.
Calibrating delay loop... 702M loops per second, 100 myus = 199 us. OK.
Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip 
bus type LPC are incompatible.
Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip 
bus type LPC are incompatible.
Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip 
bus type LPC are incompatible.
Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus 
type SPI are incompatible.
Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus 
type Parallel are incompatible.
Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip 
bus type LPC,FWH are incompatible.
Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip 
bus type FWH are incompatible.
Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip 
bus type LPC are incompatible.
Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip 
bus type Parallel are incompatible.
Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip 
bus type SPI are incompatible.
Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and 
chip bus type SPI are incompatible.
Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and 
chip bus type Parallel are incompatible.
Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and 
chip bus type LPC are incompatible.
Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and 
chip bus type FWH are incompatible.
Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus 
type None and chip bus type FWH are incompatible.
Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type 
None and chip bus type SPI are incompatible.
Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus 
type None and chip bus type SPI are incompatible.
Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None 
and chip bus type SPI are incompatible.
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type 
None and chip bus type SPI are incompatible.
Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus 
type None and chip bus type SPI are incompatible.
Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus 
type None and chip bus type SPI are incompatible.
No EEPROM/flash device found.
If you know which flash chip you have, and if this version of flashrom
supports a similar flash chip, you can try to force read your chip. Run:
flashrom -f -r -c similar_supported_flash_chip filename

Note: flashrom can never write when the flash chip isn't found 
automatically.





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From buurin at gmail.com  Mon Apr  5 05:06:45 2010
From: buurin at gmail.com (Keith Hui)
Date: Sun, 4 Apr 2010 23:06:45 -0400
Subject: [coreboot] PATCH: Add code to initialize PIIX4 ACPI/PM/SMBus
	device
In-Reply-To: <b72cdb061003281943o3d7265bbi59857425926ce0df@mail.gmail.com>
References: <b72cdb061003281943o3d7265bbi59857425926ce0df@mail.gmail.com>
Message-ID: <x2mb72cdb061004042006t646192f1nb6a74877b9a3fe40@mail.gmail.com>

ping...

On Sun, Mar 28, 2010 at 10:43 PM, Keith Hui <buurin at gmail.com> wrote:
> The attached patch adds code required for initializing the ACPI/power
> management/SMBus subdevice of PIIX4.
>
> This is required for properly placing the I/O ports for power
> management functionalities, which in turn will be required for future
> ACPI work. Speaking of which, I based these ports at 0xe400, after my
> P2B-LS board. This support is far from complete, but one step at a
> time.
>
> I was thinking to ask if someone know where to set this I/O base
> address, and turns out no initialization whatsoever was being done.
> :-O
>
> Enjoy.
>
> Signed-off-by: Keith Hui <buurin at gmail.com>
>



From c-d.hailfinger.devel.2006 at gmx.net  Mon Apr  5 00:19:23 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Mon, 05 Apr 2010 00:19:23 +0200
Subject: [coreboot] Asrock Mainboard Support
In-Reply-To: <4BB8E902.4010808@googlemail.com>
References: <4BB8E902.4010808@googlemail.com>
Message-ID: <4BB9106B.6040901@gmx.net>

Hi,

On 04.04.2010 21:31, ataya65 at googlemail.com wrote:
> As suggested in your homepage i would like to send  you the outputs of
> lspci; lspci -tvnn; superiotool -dV; flashrom -V,  further i attached
> the BIOS-Information,  output of dmesg and specificationd i got from
> the (Hardware lister).
>
> The URL to my Mainboard manf. is:
> http://www.asrock.com/mb/overview.asp?Model=K10N78
>
> *_lspci_*
> 00:00.0 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory
> Controller (rev a2)
> 00:01.0 ISA bridge: nVidia Corporation MCP78S [GeForce 8200] LPC
> Bridge (rev a2)
> 00:01.1 SMBus: nVidia Corporation MCP78S [GeForce 8200] SMBus (rev a1)
> 00:01.2 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory
> Controller (rev a1)
> 00:01.3 Co-processor: nVidia Corporation MCP78S [GeForce 8200]
> Co-Processor (rev a2)
> 00:01.4 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory
> Controller (rev a1)
> 00:02.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI
> USB 1.1 Controller (rev a1)
> 00:02.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI
> USB 2.0 Controller (rev a1)
> 00:04.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI
> USB 1.1 Controller (rev a1)
> 00:04.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI
> USB 2.0 Controller (rev a1)
> 00:06.0 IDE interface: nVidia Corporation MCP78S [GeForce 8200] IDE
> (rev a1)
> 00:07.0 Audio device: nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S
> High Definition Audio (rev a1)
> 00:08.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Bridge (rev a1)
> 00:09.0 SATA controller: nVidia Corporation MCP78S [GeForce 8200] AHCI
> Controller (rev a2)
> 00:0a.0 Ethernet controller: nVidia Corporation MCP77 Ethernet (rev a2)
> 00:0b.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Express Bridge (rev a1)
> 00:10.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Express Bridge (rev a1)
> 00:12.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Express Bridge (rev a1)
> 00:13.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Bridge (rev a1)
> 00:14.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI
> Bridge (rev a1)
> 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron,
> Athlon64, Sempron] HyperTransport Configuration
> 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron,
> Athlon64, Sempron] Address Map
> 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron,
> Athlon64, Sempron] DRAM Controller
> 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron,
> Athlon64, Sempron] Miscellaneous Control
> 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron,
> Athlon64, Sempron] Link Control
> 02:00.0 VGA compatible controller: nVidia Corporation GeForce 8200
> (rev a2)
> 03:00.0 VGA compatible controller: nVidia Corporation GeForce 8400 GS
> (rev a1)

Unfortunately we do not have docs for the Nvidia MCP78S chipset and that
makes it impossible to support your board in coreboot.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From stepan at coresystems.de  Mon Apr  5 12:38:13 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Mon, 05 Apr 2010 12:38:13 +0200
Subject: [coreboot] PATCH: Add code to initialize PIIX4 ACPI/PM/SMBus
 device
In-Reply-To: <b72cdb061003281943o3d7265bbi59857425926ce0df@mail.gmail.com>
References: <b72cdb061003281943o3d7265bbi59857425926ce0df@mail.gmail.com>
Message-ID: <4BB9BD95.5010006@coresystems.de>

On 3/29/10 4:43 AM, Keith Hui wrote:
> This is required for properly placing the I/O ports for power
> management functionalities, which in turn will be required for future
> ACPI work. Speaking of which, I based these ports at 0xe400, after my
> P2B-LS board.
>   
That is problematic. Can you put it below 0x1000? IO ports 0x1000 and
above are maintained by the register allocator and thus there may be
conflicts, depending on what PCI cards you plug into that system.

> One other change I should propose (but is not in this patch) is that
> the definition for SMBUS_IO_BASE be moved to i82371eb.h from
> i82371eb_early_smbus.c.
>  Makes more sense for a definition that may be
> referenced from some other places.
>   
Yes, absolutely.

Stefan

-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From mylesgw at gmail.com  Mon Apr  5 17:21:37 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 5 Apr 2010 09:21:37 -0600
Subject: [coreboot] PATCH: Add code to initialize PIIX4 ACPI/PM/SMBus
	device
In-Reply-To: <4BB9BD95.5010006@coresystems.de>
References: <b72cdb061003281943o3d7265bbi59857425926ce0df@mail.gmail.com>
	<4BB9BD95.5010006@coresystems.de>
Message-ID: <94FCC29F4689486FB356F210937E41E8@chimp>



> On 3/29/10 4:43 AM, Keith Hui wrote:
> > This is required for properly placing the I/O ports for power
> > management functionalities, which in turn will be required for future
> > ACPI work. Speaking of which, I based these ports at 0xe400, after my
> > P2B-LS board.
> >
> That is problematic. Can you put it below 0x1000? IO ports 0x1000 and
> above are maintained by the register allocator and thus there may be
> conflicts, depending on what PCI cards you plug into that system.

As long as they are fixed resources, it should just work, but nothing above
0xe400 will be available for the allocator.  It doesn't seem like too much
address space lost, though.

Thanks,
Myles




From michael.rodin at arcor.de  Mon Apr  5 17:02:08 2010
From: michael.rodin at arcor.de (Michael Rodin)
Date: Mon, 5 Apr 2010 17:02:08 +0200 (CEST)
Subject: [coreboot] Support of the MS-7091 mainboard
Message-ID: <23443361.1270479728106.JavaMail.ngmail@webmail13.arcor-online.net>

Hello,
I would like to now whether my motherboard is (could be) supported by coreboot. As suggested in the FAQ, i send the following informations:

Step 1:
Motherboard is a MS-7091 (OEM-Board by MEDION) with a P4 processor.

==================================================================================

Step 2:
"lspci -tvnn" output:

-[0000:00]-+-00.0  Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller Hub [8086:2580]
           +-01.0-[0000:01]--+-00.0  ATI Technologies Inc RV410 [Radeon X700 Pro (PCIE)] [1002:5e4b]
           |                 \-00.1  ATI Technologies Inc RV410 [Radeon X700 Pro (PCIE)] (Secondary) [1002:5e6b]
           +-1b.0  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller [8086:2668]
           +-1c.0-[0000:02]--
           +-1d.0  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658]
           +-1d.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659]
           +-1d.2  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a]
           +-1d.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b]
           +-1d.7  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c]
           +-1e.0-[0000:03]--+-01.0  Philips Semiconductors SAA7134/SAA7135HL Video Broadcast Decoder [1131:7134]
           |                 +-03.0  VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044]
           |                 +-04.0  Philips Semiconductors SAA7134/SAA7135HL Video Broadcast Decoder [1131:7134]
           |                 +-05.0  Agere Systems V.92 56K WinModem [11c1:048c]
           |                 \-06.0  VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] [1106:3106]
           +-1f.0  Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640]
           +-1f.1  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller [8086:266f]
           +-1f.2  Intel Corporation 82801FR/FRW (ICH6R/ICH6RW) SATA Controller [8086:2652]
           \-1f.3  Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller [8086:266a]

==================================================================================

Step 3:
"superiotool -dV" output:

superiotool r3844
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xc4f8, id=0xa170
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0x70a1, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0x70/0x0f, rev=0xa1
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
No Super I/O found

==================================================================================

Step 4:
"flashrom -V" output:

flashrom v0.9.1-r706
No coreboot table found.
Found chipset "Intel ICH6/ICH6R", enabling flash write... 
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode disabled
0xffe00000/0xffa00000 FWH decode disabled
0xffd80000/0xff980000 FWH decode disabled
0xffd00000/0xff900000 FWH decode disabled
0xffc80000/0xff880000 FWH decode disabled
0xffc00000/0xff800000 FWH decode disabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
OK.
This chipset supports the following protocols: Non-SPI.
Calibrating delay loop... 775M loops per second, 100 myus = 175 us. OK.
Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x00, id2 0x18
Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xda, id2 0x34
Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xda, id2 0x34
Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0xda, id2 0x34
Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0xda, id2 0x34
Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xda, id2 0x34
Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xda, id2 0x34
Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0xda, id2 0x34
Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x99, id2 0x47
Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x99, id2 0x47
Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x49, id2 0x4d
Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d
Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d
Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x49, id2 0x4d
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34
Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x99, id2 0x47
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip.
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xda, id2 0x34
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xda, id2 0x34
Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000.
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xda, id2 0x34
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xda, id2 0x34
Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible.
No operations were specified.

==================================================================================

Step 5:
I could not find the mainboard at the MSI or MEDION homepage :-(

Regards,
Michael

Internet-Tipps f?r jedermann und jedefrau - jetzt aktuell und kostenfrei auf arcor.de: http://www.arcor.de/rd/footer.inettipps



From r.marek at assembler.cz  Mon Apr  5 18:59:24 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 05 Apr 2010 18:59:24 +0200
Subject: [coreboot] [PATCH] Quick and dirty Asrock 939A785GMH support
In-Reply-To: <4BA01074.6000702@coresystems.de>
References: <4BA005D1.5020803@assembler.cz> <4BA01074.6000702@coresystems.de>
Message-ID: <4BBA16EC.8090404@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

What about this? Looks like there will be some GSOC for ACPI cleanup/porting?
Maybe I can check it in and make it usable?

Ideas?

Rudolf
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Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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=wEOC
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From svn at coreboot.org  Mon Apr  5 21:21:18 2010
From: svn at coreboot.org (repository service)
Date: Mon, 05 Apr 2010 21:21:18 +0200
Subject: [coreboot] [commit] r5356 - in trunk/src: include/device
	southbridge/amd/rs780
Message-ID: <E1NyrrK-0004zj-Lm@ra.coresystems.de>

Author: ruik
Date: Mon Apr  5 21:21:18 2010
New Revision: 5356
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5356

Log:
Add RS785G, looks like it works although it is RV620.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/include/device/pci_ids.h
   trunk/src/southbridge/amd/rs780/rs780_gfx.c

Modified: trunk/src/include/device/pci_ids.h
==============================================================================
--- trunk/src/include/device/pci_ids.h	Sat Apr  3 17:41:27 2010	(r5355)
+++ trunk/src/include/device/pci_ids.h	Mon Apr  5 21:21:18 2010	(r5356)
@@ -340,6 +340,7 @@
 #define PCI_DEVICE_ID_ATI_RS780M_INT_GFX	0x9612
 #define PCI_DEVICE_ID_ATI_RS780MC_INT_GFX	0x9613
 #define PCI_DEVICE_ID_ATI_RS780E_INT_GFX	0x9615
+#define PCI_DEVICE_ID_ATI_RS785G_INT_GFX	0x9710
 
 #define PCI_VENDOR_ID_VLSI		0x1004
 #define PCI_DEVICE_ID_VLSI_82C592	0x0005

Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c	Sat Apr  3 17:41:27 2010	(r5355)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c	Mon Apr  5 21:21:18 2010	(r5356)
@@ -25,6 +25,7 @@
  *	RS780M:	0x9612
  *	RS780MC:0x9613
  *	RS780E: 0x9615
+ *	RS785G: 0x9710 - just works, not much tested
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -815,6 +816,11 @@
 	.vendor = PCI_VENDOR_ID_ATI,
 	.device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
 };
+static const struct pci_driver pcie_driver_785g __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
+};
 
 /* step 12 ~ step 14 from rpr */
 static void single_port_configuration(device_t nb_dev, device_t dev)



From r.marek at assembler.cz  Mon Apr  5 21:21:49 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 05 Apr 2010 21:21:49 +0200
Subject: [coreboot] [PATCH] Quick and dirty Asrock 939A785GMH support
In-Reply-To: <4BA01A35.9020602@assembler.cz>
References: <4BA005D1.5020803@assembler.cz>
	<4BA0137C.3060106@assembler.cz>	<4BA015AD.4060708@coresystems.de>
	<4BA01A35.9020602@assembler.cz>
Message-ID: <4BBA384D.4090102@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Ok it is in as Committed revision 5356.

Now the motherboard stuff.

Rudolf
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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From svn at coreboot.org  Mon Apr  5 21:47:35 2010
From: svn at coreboot.org (repository service)
Date: Mon, 05 Apr 2010 21:47:35 +0200
Subject: [coreboot] [commit] r5357 - in trunk/src/mainboard: . asrock
	asrock/939a785gmh asrock/939a785gmh/acpi
Message-ID: <E1NysGl-0006yN-Cr@ra.coresystems.de>

Author: ruik
Date: Mon Apr  5 21:47:34 2010
New Revision: 5357
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5357

Log:
Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Add Asrock 939a785gmh motherboard. The ACPI needs more cleanup, could be done when cleaning
the Mahagony board. The SidePort mode does not work because AMD hardcoded memory type in rs780_gfx.c
The UMA is enabled instead. The board boots, network and int VGA works, IDE too.

Added:
   trunk/src/mainboard/asrock/
   trunk/src/mainboard/asrock/939a785gmh/
   trunk/src/mainboard/asrock/939a785gmh/Kconfig
   trunk/src/mainboard/asrock/939a785gmh/acpi/
   trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c
   trunk/src/mainboard/asrock/939a785gmh/chip.h
   trunk/src/mainboard/asrock/939a785gmh/cmos.layout
   trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
   trunk/src/mainboard/asrock/939a785gmh/dsdt.asl
   trunk/src/mainboard/asrock/939a785gmh/fadt.c
   trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
   trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
   trunk/src/mainboard/asrock/939a785gmh/mainboard.c
   trunk/src/mainboard/asrock/939a785gmh/mptable.c
   trunk/src/mainboard/asrock/939a785gmh/resourcemap.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asrock/Kconfig
Modified:
   trunk/src/mainboard/Kconfig

Modified: trunk/src/mainboard/Kconfig
==============================================================================
--- trunk/src/mainboard/Kconfig	Mon Apr  5 21:21:18 2010	(r5356)
+++ trunk/src/mainboard/Kconfig	Mon Apr  5 21:47:34 2010	(r5357)
@@ -16,6 +16,8 @@
 	bool "Artec Group"
 config VENDOR_ASI
 	bool "ASI"
+config VENDOR_ASROCK
+	bool "ASROCK"
 config VENDOR_ASUS
 	bool "ASUS"
 config VENDOR_A_TREND
@@ -131,6 +133,11 @@
 
 config MAINBOARD_VENDOR
 	string
+	default "ASROCK"
+	depends on VENDOR_ASROCK
+
+config MAINBOARD_VENDOR
+	string
 	default "ASUS"
 	depends on VENDOR_ASUS
 
@@ -366,6 +373,7 @@
 source "src/mainboard/arima/Kconfig"
 source "src/mainboard/artecgroup/Kconfig"
 source "src/mainboard/asi/Kconfig"
+source "src/mainboard/asrock/Kconfig"
 source "src/mainboard/asus/Kconfig"
 source "src/mainboard/axus/Kconfig"
 source "src/mainboard/azza/Kconfig"

Added: trunk/src/mainboard/asrock/939a785gmh/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/Kconfig	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,123 @@
+config BOARD_ASROCK_939A785GMH
+	bool "939A785GMH/128M"
+	select ARCH_X86
+	select CPU_AMD_SOCKET_939
+	select K8_HT_FREQ_1G_SUPPORT
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_SB700
+	select SUPERIO_WINBOND_W83627DHG
+	select BOARD_HAS_FADT
+	select GENERATE_ACPI_TABLES
+	select GENERATE_MP_TABLE
+	select GENERATE_PIRQ_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_BUS_CONFIG
+	select LIFT_BSP_APIC_ID
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select BOARD_ROMSIZE_KB_1024
+	select GFXUMA
+
+config MAINBOARD_DIR
+	string
+	default asrock/939a785gmh
+	depends on BOARD_ASROCK_939A785GMH
+
+config HAVE_HIGH_TABLES
+	bool
+	default n
+	depends on BOARD_ASROCK_939A785GMH
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_ASROCK_939A785GMH
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+	depends on BOARD_ASROCK_939A785GMH
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_ASROCK_939A785GMH
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+	depends on BOARD_ASROCK_939A785GMH
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_ASROCK_939A785GMH
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_ASROCK_939A785GMH
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "939A785GMH"
+	depends on BOARD_ASROCK_939A785GMH
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_ASROCK_939A785GMH
+
+config MAX_CPUS
+	int
+	default 8
+	depends on BOARD_ASROCK_939A785GMH
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_ASROCK_939A785GMH
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+	depends on BOARD_ASROCK_939A785GMH
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+	depends on BOARD_ASROCK_939A785GMH
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+	depends on BOARD_ASROCK_939A785GMH
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_ASROCK_939A785GMH
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_ASROCK_939A785GMH
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+	depends on BOARD_ASROCK_939A785GMH
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_ASROCK_939A785GMH
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x3060
+	depends on BOARD_ASROCK_939A785GMH

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+	DefinitionBlock (
+		"DSDT.AML",
+		"DSDT",
+		0x01,
+		"XXXXXX",
+		"XXXXXXXX",
+		0x00010001
+		)
+	{
+		#include "debug.asl"
+	}
+*/
+
+/*
+* 0x80: POST_BASE
+* 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
+*
+* CREG: DEBCOM_REGION
+* CUAR: DEBCOM_UART
+* CDAT: DEBCOM_DATA
+* CDLM: DEBCOM_DLM
+* DLCR: DEBCOM_LCR
+* CMCR: DEBCOM_MCR
+* CLSR: DEBCOM_LSR
+*
+* DEBUG_INIT	DINI
+*/
+
+OperationRegion(X80, SystemIO, 0x80, 1)
+	Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+	Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
+}
+
+/*
+* DINI
+* Initialize the COM port to 115,200 8-N-1
+*/
+Method(DINI)
+{
+	store(0x83, DLCR)
+	store(0x01, CDAT)	/* 115200 baud (low) */
+	store(0x00, CDLM)	/* 115200 baud (high) */
+	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
+	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
+	store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/*
+* THRE
+* Wait for COM port transmitter holding register to go empty
+*/
+Method(THRE)
+{
+	and(CLSR, 0x20, local0)
+	while (Lequal(local0, Zero)) {
+		and(CLSR, 0x20, local0)
+	}
+}
+
+/*
+* OUTX
+* Send a single raw character
+*/
+Method(OUTX, 1)
+{
+	THRE()
+	store(Arg0, CDAT)
+}
+
+/*
+* OUTC
+* Send a single character, expanding LF into CR/LF
+*/
+Method(OUTC, 1)
+{
+	if (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/*
+* DBGN
+* Send a single hex nibble
+*/
+Method(DBGN, 1)
+{
+	and(Arg0, 0x0f, Local0)
+	if (LLess(Local0, 10)) {
+		add(Local0, 0x30, Local0)
+	} else {
+		add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/*
+* DBGB
+* Send a hex byte
+*/
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/*
+* DBGW
+* Send a hex word
+*/
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/*
+* DBGD
+* Send a hex Dword
+*/
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/*
+* DBGO
+* Send either a string or an integer
+*/
+Method(DBGO, 1)
+{
+	/* DINI() */
+	if (LEqual(ObjectType(Arg0), 1)) {
+		if (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} else {
+			if (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} else {
+				DBGB(Arg0)
+			}
+		}
+	} else {
+		Name(BDBG, Buffer(80) {})
+		store(Arg0, BDBG)
+		store(0, Local1)
+		while (One) {
+			store(GETC(BDBG, Local1), Local0)
+			if (LEqual(Local0, 0)) {
+				return (0)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+	return (0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	return (DBGC)
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope(\_SB) {
+	#include "globutil.asl"
+}
+*/
+
+/* string compare functions */
+Method(MIN, 2)
+{
+	if (LLess(Arg0, Arg1)) {
+		Return(Arg0)
+	} else {
+		Return(Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return(Sizeof(Local0))
+}
+
+Method(S2BF, 1)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return(BUFF)
+}
+
+/* Strong string compare.  Checks both length and content */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While(LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		if (LGreater(Local2, Local3)) {
+			Return(One)
+		} else {
+			if (LLess(Local2, Local3)) {
+				Return(Ones)
+			}
+		}
+		Increment(Local4)
+	}
+	if (LLess(Local4, Local5)) {
+		Return(One)
+	} else {
+		if (LLess(Local4, Local6)) {
+			Return(Ones)
+		} else {
+			Return(Zero)
+		}
+	}
+}
+
+/* Weak string compare.  Checks to find Arg1 at beginning of Arg0.
+* Fails if length(Arg0) < length(Arg1).  Returns 0 on Fail, 1 on
+* Pass.
+*/
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return(0)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While(LLess(Local2, Local3)) {
+		if (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return(0)
+		}
+		Increment(Local2)
+	}
+	Return(One)
+}
+
+/* ARG0 = IRQ Number(0-15)
+* Returns Bit Map
+*/
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	if (LNotEqual(ARG0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, ARG0, Local0)
+	}
+	Return(Local0)
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTA, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTA, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		Package(){0x0012FFFF, 2, INTC, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTD, 0 },
+		Package(){0x0013FFFF, 2, INTA, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Package(){0x0001FFFF, 0, 0, 18 }, */
+		/* package(){0x0001FFFF, 1, 0, 19 }, */
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 22 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 16 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		Package(){0x0012FFFF, 2, 0, 18 },
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 19 },
+		Package(){0x0013FFFF, 2, 0, 16 },
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		/* Package(){0x00130004, 2, 0, 18 }, */
+		/* Package(){0x00130005, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+	})
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00120000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/* Status and notification definitions */
+
+#define STA_MISSING			    0x00
+#define STA_PRESENT			    0x01
+#define	STA_ENABLED			    0x03
+#define STA_DISABLED		    0x09
+#define	STA_INVISIBLE		    0x0B
+#define	STA_UNAVAILABLE		    0x0D
+#define	STA_VISIBLE			    0x0F
+
+/* SMBus status codes */
+#define SMB_OK                  0x00
+#define SMB_UnknownFail         0x07
+#define SMB_DevAddrNAK          0x10
+#define SMB_DeviceError         0x11
+#define SMB_DevCmdDenied        0x12
+#define SMB_UnknownErr          0x13
+#define SMB_DevAccDenied        0x17
+#define SMB_Timeout             0x18
+#define SMB_HstUnsuppProtocol   0x19
+#define SMB_Busy                0x1A
+#define SMB_PktChkError         0x1F
+
+/* Device Object Notification Values */
+#define	NOTIFY_BUS_CHECK		0x00
+#define	NOTIFY_DEVICE_CHECK		0x01
+#define	NOTIFY_DEVICE_WAKE		0x02
+#define	NOTIFY_EJECT_REQUEST	0x03
+#define	NOTIFY_DEVICE_CHECK_JR	0x04
+#define	NOTIFY_FREQUENCY_ERROR	0x05
+#define	NOTIFY_BUS_MODE			0x06
+#define	NOTIFY_POWER_FAULT		0x07
+#define	NOTIFY_CAPABILITIES		0x08
+#define	NOTIFY_PLD_CHECK		0x09
+#define	NOTIFY_SLIT_UPDATE		0x0B
+
+/* Battery Device Notification Values */
+#define	NOTIFY_BAT_STATUSCHG	0x80
+#define	NOTIFY_BAT_INFOCHG  	0x81
+#define	NOTIFY_BAT_MAINTDATA    0x82
+
+/* Power Source Object Notification Values */
+#define	NOTIFY_PWR_STATUSCHG	0x80
+
+/* Thermal Zone Object Notification Values */
+#define	NOTIFY_TZ_STATUSCHG	    0x80
+#define	NOTIFY_TZ_TRIPPTCHG	    0x81
+#define	NOTIFY_TZ_DEVLISTCHG	0x82
+#define	NOTIFY_TZ_RELTBLCHG 	0x83
+
+/* Power Button Notification Values */
+#define	NOTIFY_POWER_BUTTON		0x80
+
+/* Sleep Button Notification Values */
+#define	NOTIFY_SLEEP_BUTTON		0x80
+
+/* Lid Notification Values */
+#define	NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define	NOTIFY_CPU_PPCCHG   	0x80
+#define	NOTIFY_CPU_CSTATECHG  	0x81
+#define	NOTIFY_CPU_THROTLCHG    0x82
+
+/* User Presence Device Notification Values */
+#define	NOTIFY_USR_PRESNCECHG	0x80
+
+/* Battery Device Notification Values */
+#define	NOTIFY_ALS_ILLUMCHG 	0x80
+#define	NOTIFY_ALS_COLORTMPCHG 	0x81
+#define	NOTIFY_ALS_RESPCHG      0x82
+
+

Added: trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}

Added: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
+#include <arch/cpu.h>
+#include <cpu/amd/model_fxx_powernow.h>
+
+extern u16 pm_base;
+
+#define DUMP_ACPI_TABLES 0
+
+/*
+* Assume the max pstate number is 8
+* 0x21(33 bytes) is one package length of _PSS package
+*/
+
+#define Maxpstate 8
+#define Defpkglength 0x21
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const acpi_header_t AmlCode;
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const acpi_header_t AmlCode_ssdt2;
+extern const acpi_header_t AmlCode_ssdt3;
+extern const acpi_header_t AmlCode_ssdt4;
+extern const acpi_header_t AmlCode_ssdt5;
+#endif
+
+#define IO_APIC_ADDR	0xfec00000UL
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB700 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+extern void get_bus_conf(void);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+static void update_ssdtx(void *ssdtx, int i)
+{
+	u8 *PCI;
+	u8 *HCIN;
+	u8 *UID;
+
+	PCI = ssdtx + 0x32;
+	HCIN = ssdtx + 0x39;
+	UID = ssdtx + 0x40;
+
+	if (i < 7) {
+		*PCI = (u8) ('4' + i - 1);
+	} else {
+		*PCI = (u8) ('A' + i - 1 - 6);
+	}
+	*HCIN = (u8) i;
+	*UID = (u8) (i + 3);
+
+	/* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+#endif
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
+	k8acpi_write_vars();
+	amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	acpi_header_t const *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SSDT */
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
+
+	for (i = 1; i < sysconf.hc_possible_num; i++) {	/* 0: is hc sblink */
+		if ((sysconf.pci1234[i] & 1) != 1)
+			continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);	/* pci0 and pci1 are in dsdt */
+		current = (current + 0x07) & -0x08;
+		ssdtx = (acpi_header_t *) current;
+		switch (sysconf.hcid[i]) {
+		case 1:	/* 8132 */
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:	/* 8151 */
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		current += p->length;
+		memcpy((void *)ssdtx, p, p->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* FACS */
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* DSDT */
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy((void *)dsdt, &AmlCode, AmlCode.length);
+	current += dsdt->length;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	/* FADT */
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}

Added: trunk/src/mainboard/asrock/939a785gmh/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/chip.h	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config
+{
+	u32 uma_size;			/* How many UMA should be used in memory for TOP. */
+};
+

Added: trunk/src/mainboard/asrock/939a785gmh/cmos.layout
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,119 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+##
+##
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399	     1	     e	     2	      dual_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

Added: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,133 @@
+#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
+#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
+#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
+#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
+#Define gfx_dual_slot, 0: single slot, 1: dual slot
+#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
+#Define gfx_tmds, 0: didn't support TMDS, 1: support
+#Define gfx_compliance, 0: didn't support compliance, 1: support
+#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
+#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_939
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT  	0x9600
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 on end # PCIE P2P bridge	0x960b
+					device pci 4.0 on end # PCIE P2P bridge 0x9604
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 on end #
+					device pci a.0 on end #
+					register "gppsb_configuration" = "1"   # Configuration B
+					register "gpp_configuration" = "3"   # Configuration D default
+					register "port_enable" = "0x6fc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "1"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.1 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.1 on end # USB
+					device pci 13.2 on end # USB
+	 				device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x439d
+
+						chip superio/winbond/w83627dhg
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							#device pnp 2e.6 off #  SPI
+							#end
+							device pnp 2e.307 off #  GPIO6
+							end
+							device pnp 2e.8 on #  WDTO#, PLED
+							end
+							device pnp 2e.009 on #  GPIO2
+							end
+							device pnp 2e.109 on #  GPIO3
+							end
+							device pnp 2e.209 on #  GPIO4
+							end
+							device pnp 2e.309 off #  GPIO5
+							end
+							device pnp 2e.a off #  ACPI
+							end
+							device pnp 2e.b on # HWM
+								io 0x60 = 0x290
+							end
+							device pnp 2e.c off # PECI, SST
+							end
+						end	#superio/winbond/w8362
+
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # USB 2
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb700
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,1807 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"ASROCK",               /* OEMID */
+	"939A785GM",     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/* PIC IRQ mapping registers, C00h-C01h */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PINA, 0x00000008,	/* Index 0  */
+		PINB, 0x00000008,	/* Index 1 */
+		PINC, 0x00000008,	/* Index 2 */
+		PIND, 0x00000008,	/* Index 3 */
+		AINT, 0x00000008,	/* Index 4 */
+		SINT, 0x00000008,	/*  Index 5 */
+		, 0x00000008,	             /* Index 6 */
+		AAUD, 0x00000008,	/* Index 7 */
+		AMOD, 0x00000008,	/* Index 8 */
+		PINE, 0x00000008,	/* Index 9 */
+		PINF, 0x00000008,	/* Index A */
+		PING, 0x00000008,	/* Index B */
+		PINH, 0x00000008,	/* Index C */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PINA)
+			Store(0, PINB)
+			Store(0, PINC)
+			Store(0, PIND)
+			Store(0, PINE)
+			Store(0, PINF)
+			Store(0, PING)
+			Store(0, PINH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PINA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PINA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PINB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PINB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PINC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PINC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIND) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIND)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIND, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIND)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PINE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PINE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PINF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PINF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PING) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PING)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PING, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PING)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PINH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PINH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+		\_SB.PCI0.SIOS (Arg0)
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		\_SB.PCI0.SIOW (Arg0)
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			Notify (\_TZ.TZ00, 0x80)
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00130001)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130003)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00130004)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00130005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			/* ITE8718 Support */
+			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
+				Field (IOID, ByteAcc, NoLock, Preserve)
+				{
+					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
+				}
+
+			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+			{
+					Offset (0x07),
+				LDN,	8,	/* Logical Device Number */
+					Offset (0x20),
+				CID1,	8,	/* Chip ID Byte 1, 0x87 */
+				CID2,	8,	/* Chip ID Byte 2, 0x12 */
+					Offset (0x30),
+				ACTR,	8,	/* Function activate */
+					Offset (0xF0),
+				APC0,	8,	/* APC/PME Event Enable Register */
+				APC1,	8,	/* APC/PME Status Register */
+				APC2,	8,	/* APC/PME Control Register 1 */
+				APC3,	8,	/* Environment Controller Special Configuration Register */
+				APC4,	8	/* APC/PME Control Register 2 */
+			}
+
+			/* Enter the 8718 MB PnP Mode */
+			Method (EPNP)
+			{
+				Store(0x87, SIOI)
+				Store(0x01, SIOI)
+				Store(0x55, SIOI)
+				Store(0x55, SIOI) /* 8718 magic number */
+			}
+			/* Exit the 8718 MB PnP Mode */
+			Method (XPNP)
+			{
+				Store (0x02, SIOI)
+				Store (0x02, SIOD)
+			}
+			/*
+			 * Keyboard PME is routed to SB600 Gevent3. We can wake
+			 * up the system by pressing the key.
+			 */
+			Method (SIOS, 1)
+			{
+				/* We only enable KBD PME for S5. */
+				If (LLess (Arg0, 0x05))
+				{
+					EPNP()
+					/* DBGO("8718F\n") */
+
+					Store (0x4, LDN)
+					Store (One, ACTR)  /* Enable EC */
+					/*
+					Store (0x4, LDN)
+					Store (0x04, APC4)
+					*/  /* falling edge. which mode? Not sure. */
+
+					Store (0x4, LDN)
+					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+					Store (0x4, LDN)
+					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+					XPNP()
+				}
+			}
+			Method (SIOW, 1)
+			{
+				EPNP()
+				Store (0x4, LDN)
+				Store (Zero, APC0) /* disable keyboard PME */
+				Store (0x4, LDN)
+				Store (0xFF, APC1) /* clear keyboard PME status */
+				XPNP()
+			}
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/*  Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0xFFFFFFFF,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/*  Max */
+					0x00000000,		/* Translation */
+					0x00000000,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+}
+/* End of ASL file */

Added: trunk/src/mainboard/asrock/939a785gmh/fadt.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/fadt.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <../southbridge/amd/sb700/sb700.h>
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of rs780. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x2A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x2B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 20-2B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}

Added: trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_isa;
+u8 bus_rs780[11];
+u8 bus_sb700[2];
+u32 apicid_sb700;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_rs780;
+u32 sbdn_sb700;
+
+extern void get_sblk_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void);
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_sblk_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb700 = 0;
+
+	for (i = 0; i < 2; i++) {
+		bus_sb700[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb700[0] = bus_rs780[0];
+
+	bus_type[bus_rs780[0]] = 1;
+
+	/* sb700 */
+	dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
+	if (dev) {
+		bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb700[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rs780[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rs780[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb700 = apicid_base + 0;
+}

Added: trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/irq_tables.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify!
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern void get_bus_conf(void);
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_rs780[8];
+extern u8 bus_sb700[2];
+extern unsigned long sbdn_sb700;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb700[0];
+	pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}

Added: trunk/src/mainboard/asrock/939a785gmh/mainboard.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <arch/coreboot_tables.h>
+#include <../southbridge/amd/sb700/sb700.h>
+#include "chip.h"
+
+#define SMBUS_IO_BASE 0x6000
+
+extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
+				uint64_t start, uint64_t size);
+
+uint64_t uma_memory_base, uma_memory_size;
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
+/*
+ * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+	u16 word;
+	device_t sm_dev;
+	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	word = pci_read_config16(sm_dev, 0xA8);
+	word |= (1 << 0) | (1 << 2);	/* Set Gpio6,4 as output */
+	word &= ~((1 << 8) | (1 << 10));
+	pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+	u16 word;
+	device_t sm_dev;
+	/* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	word = pci_read_config16(sm_dev, 0xA8);
+	word &= ~((1 << 0) | (1 << 2));	/* Set Gpio6,4 as output */
+	word &= ~((1 << 8) | (1 << 10));
+	pci_write_config16(sm_dev, 0xA8, word);
+}
+
+#if 0	     /* not tested yet */
+/********************************************************
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+	u8 byte;
+	/*u32 sm_dev, ide_dev; */
+	device_t sm_dev, ide_dev;
+
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	byte = pci_read_config8(sm_dev, 0xA9);
+	byte |= (1 << 5);	/* Set Gpio9 as input */
+	pci_write_config8(sm_dev, 0xA9, byte);
+
+	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+	byte = pci_read_config8(ide_dev, 0x56);
+	byte &= ~(7 << 0);
+	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+		byte |= 2 << 0;	/* mode 2 */
+	else
+		byte |= 5 << 0;	/* mode 5 */
+	pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif	/* get_ide_dma66 */
+
+/*************************************************
+* enable the dedicated function in mahogany board.
+* This function called early than rs780_enable.
+*************************************************/
+static void mahogany_enable(device_t dev)
+{
+	/* Leave it for future. */
+	/* struct mainboard_config *mainboard =
+	   (struct mainboard_config *)dev->chip_info;*/
+
+	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in 780 BDG. */
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	/* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("AMD MAHOGANY   Mainboard")
+	.enable_dev = mahogany_enable,
+};

Added: trunk/src/mainboard/asrock/939a785gmh/mptable.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/mptable.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern u8 bus_isa;
+extern u8 bus_rs780[11];
+extern u8 bus_sb700[2];
+
+extern u32 apicid_sb700;
+
+extern u32 bus_type[256];
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb700;
+
+extern void get_bus_conf(void);
+
+static void *smp_write_config_table(void *v)
+{
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "AMD     ";
+	static const char productid[12] = "MAHOGANY    ";
+	struct mp_config_table *mc;
+	int j;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
+
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc);	/* initially just the header */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0;	/* not yet computed */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0;	/* No entries yet... */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	/* Bus:         Bus ID  Type */
+	/* define bus and isa numbers */
+	for (j = 0; j < bus_isa; j++) {
+		smp_write_bus(mc, j, (char *)"PCI   ");
+	}
+	smp_write_bus(mc, bus_isa, (char *)"ISA   ");
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	{
+		device_t dev;
+		u32 dword;
+		u8 byte;
+
+		dev =
+		    dev_find_slot(bus_sb700[0],
+				  PCI_DEVFN(sbdn_sb700 + 0x14, 0));
+		if (dev) {
+			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+
+			/* Initialize interrupt mapping */
+			/* aza */
+			byte = pci_read_config8(dev, 0x63);
+			byte &= 0xf8;
+			byte |= 0;	/* 0: INTA, ...., 7: INTH */
+			pci_write_config8(dev, 0x63, byte);
+
+			/* SATA */
+			dword = pci_read_config32(dev, 0xac);
+			dword &= ~(7 << 26);
+			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
+			/* dword |= 1<<22; PIC and APIC co exists */
+			pci_write_config32(dev, 0xac, dword);
+
+			/*
+			 * 00:12.0: PROG SATA : INT F
+			 * 00:13.0: INTA USB_0
+			 * 00:13.1: INTB USB_1
+			 * 00:13.2: INTC USB_2
+			 * 00:13.3: INTD USB_3
+			 * 00:13.4: INTC USB_4
+			 * 00:13.5: INTD USB2
+			 * 00:14.1: INTA IDE
+			 * 00:14.2: Prog HDA : INT E
+			 * 00:14.5: INTB ACI
+			 * 00:14.6: INTB MCI
+			 */
+		}
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb700, 0x0);
+
+	/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+	 * or its remainings.
+	 */
+#define ISA_INT(intr, pin) \
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, (intr), apicid_sb700, (pin))
+
+	ISA_INT(0x1, 0x1);
+	ISA_INT(0x0, 0x2);
+	ISA_INT(0x3, 0x3);
+	ISA_INT(0x4, 0x4);
+	ISA_INT(0x6, 0x6);
+	ISA_INT(0x7, 0x7);
+	ISA_INT(0xc, 0xc);
+	ISA_INT(0xd, 0xd);
+	ISA_INT(0xe, 0xe);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	/* usb */
+	PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, 0x11);
+	PCI_INT(0x0, 0x13, 0x0, 0x12);
+	PCI_INT(0x0, 0x13, 0x1, 0x13);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, 0x16);
+
+	/* HD Audio: b0:d20:f1:reg63 should be 0. */
+	/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum =
+	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+		     mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}

Added: trunk/src/mainboard/asrock/939a785gmh/resourcemap.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/resourcemap.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_939a785gmh_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		* F1:0x44 i = 0
+		* F1:0x4C i = 1
+		* F1:0x54 i = 2
+		* F1:0x5C i = 3
+		* F1:0x64 i = 4
+		* F1:0x6C i = 5
+		* F1:0x74 i = 6
+		* F1:0x7C i = 7
+		* [ 2: 0] Destination Node ID
+		*	000 = Node 0
+		*	001 = Node 1
+		*	010 = Node 2
+		*	011 = Node 3
+		*	100 = Node 4
+		*	101 = Node 5
+		*	110 = Node 6
+		*	111 = Node 7
+		* [ 7: 3] Reserved
+		* [10: 8] Interleave select
+		*	specifies the values of A[14:12] to use with interleave enable.
+		* [15:11] Reserved
+		* [31:16] DRAM Limit Address i Bits 39-24
+		*	This field defines the upper address bits of a 40 bit  address
+		*	that define the end of the DRAM region.
+		*/
+		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		* F1:0x40 i = 0
+		* F1:0x48 i = 1
+		* F1:0x50 i = 2
+		* F1:0x58 i = 3
+		* F1:0x60 i = 4
+		* F1:0x68 i = 5
+		* F1:0x70 i = 6
+		* F1:0x78 i = 7
+		* [ 0: 0] Read Enable
+		*	0 = Reads Disabled
+		*	1 = Reads Enabled
+		* [ 1: 1] Write Enable
+		*	0 = Writes Disabled
+		*	1 = Writes Enabled
+		* [ 7: 2] Reserved
+		* [10: 8] Interleave Enable
+		*	000 = No interleave
+		*	001 = Interleave on A[12] (2 nodes)
+		*	010 = reserved
+		*	011 = Interleave on A[12] and A[14] (4 nodes)
+		*	100 = reserved
+		*	101 = reserved
+		*	110 = reserved
+		*	111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		* [15:11] Reserved
+		* [13:16] DRAM Base Address i Bits 39-24
+		*	This field defines the upper address bits of a 40-bit address
+		*	that define the start of the DRAM region.
+		*/
+		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	000 = Node 0
+		 *	001 = Node 1
+		 *	010 = Node 2
+		 *	011 = Node 3
+		 *	100 = Node 4
+		 *	101 = Node 5
+		 *	110 = Node 6
+		 *	111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	00 = Link 0
+		 *	01 = Link 1
+		 *	10 = Link 2
+		 *	11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	0 = CPU writes may be posted
+		 *	1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	This field defines the upp adddress bits of a 40-bit address that
+		 *	defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		* F1:0x80 i = 0
+		* F1:0x88 i = 1
+		* F1:0x90 i = 2
+		* F1:0x98 i = 3
+		* F1:0xA0 i = 4
+		* F1:0xA8 i = 5
+		* F1:0xB0 i = 6
+		* F1:0xB8 i = 7
+		* [ 0: 0] Read Enable
+		*	0 = Reads disabled
+		*	1 = Reads Enabled
+		* [ 1: 1] Write Enable
+		*	0 = Writes disabled
+		*	1 = Writes Enabled
+		* [ 2: 2] Cpu Disable
+		*	0 = Cpu can use this I/O range
+		*	1 = Cpu requests do not use this I/O range
+		* [ 3: 3] Lock
+		*	0 = base/limit registers i are read/write
+		*	1 = base/limit registers i are read-only
+		* [ 7: 4] Reserved
+		* [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		*	This field defines the upper address bits of a 40bit address
+		*	that defines the start of memory-mapped I/O region i
+		*/
+		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		* F1:0xC4 i = 0
+		* F1:0xCC i = 1
+		* F1:0xD4 i = 2
+		* F1:0xDC i = 3
+		* [ 2: 0] Destination Node ID
+		*	000 = Node 0
+		*	001 = Node 1
+		*	010 = Node 2
+		*	011 = Node 3
+		*	100 = Node 4
+		*	101 = Node 5
+		*	110 = Node 6
+		*	111 = Node 7
+		* [ 3: 3] Reserved
+		* [ 5: 4] Destination Link ID
+		*	00 = Link 0
+		*	01 = Link 1
+		*	10 = Link 2
+		*	11 = reserved
+		* [11: 6] Reserved
+		* [24:12] PCI I/O Limit Address i
+		*	This field defines the end of PCI I/O region n
+		* [31:25] Reserved
+		*/
+		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	0 = Reads Disabled
+		 *	1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	0 = Writes Disabled
+		 *	1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	0 = VGA matches Disabled
+		 *	1 = matches all address < 64K and where A[9:0] is in the
+		 *	range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	0 = ISA matches Disabled
+		 *	1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	0 = Reads Disabled
+		 *	1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	0 = Writes Disabled
+		 *	1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	0 = The ranges are based on bus number
+		 *	1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	000 = Node 0
+		 *	001 = Node 1
+		 *	010 = Node 2
+		 *	011 = Node 3
+		 *	100 = Node 4
+		 *	101 = Node 5
+		 *	110 = Node 6
+		 *	111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	00 = Link 0
+		 *	01 = Link 1
+		 *	10 = Link 2
+		 *	11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	This field defines the highest bus number in configuration regin i
+		 */
+		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}

Added: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,248 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define RAMINIT_SYSINFO 1
+#define K8_SET_FIDVID 1
+#define QRANK_DIMM_SUPPORT 1
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#define RC0 (6<<8)
+#define RC1 (7<<8)
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+
+#define ICS951462_ADDRESS	0x69
+#define SMBUS_HUB 0x71
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "console/console.c"
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#include "southbridge/amd/rs780/rs780_early_setup.c"
+#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
+#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
+
+/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+/* called in raminit_f.c */
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+/*called in raminit_f.c */
+static inline int spd_read_byte(u32 device, u32 address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "lib/generic_sdram.c"
+#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void sio_init(void)
+{
+	u8 reg;
+
+	pnp_enter_ext_func_mode(GPIO2345_DEV);
+	pnp_set_logical_device(GPIO2345_DEV);
+
+	/* Pin 119 ~ 120 GP21, GP20  */
+	reg = pnp_read_config(GPIO2345_DEV, 0x29);
+	pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
+
+	/* todo document this */
+	pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
+	pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
+
+
+//idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
+//val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
+
+//GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
+//mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
+//DDR voltage 44 45 46
+
+	/* GPO20 - sideport voltage GPO23 - mgpuV */
+	pnp_write_config(GPIO2345_DEV, 0x30, 0x07);	/* Enable GPIO 2,3,4. */
+	pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);	/* dir of GPIO2 11110110*/
+	pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);	/* data */
+	pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);	/* No inversion */
+
+	/* GPO30 GPO33 GPO35 */
+	//GPO35 - loadline control 0 - enabled
+	//GPIO30 - unknown
+	//GPIO33 - unknown
+	pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);	/* dir of GPIO3 11010110*/
+	pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);	/* data */
+	pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);	/* No inversion */
+
+	/* GPO40 GPO41 GPO42 GPO43 PO45 */
+	pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);	/* dir of GPIO4 11010000 */
+	pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);	/* data */
+	pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);	/* No inversion */
+
+	pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);	/* MFC */
+	pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);	/* MFC */
+	pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);	/* trig type */
+	pnp_exit_ext_func_mode(GPIO2345_DEV);
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+	int needs_reset = 0;
+	u32 bsp_apicid = 0;
+	msr_t msr;
+	struct cpuid_result cpuid1;
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		enumerate_ht_chain();
+
+		/* sb700_lpc_port80(); */
+		sb700_pci_port80();
+	}
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+	}
+
+	enable_rs780_dev8();
+	sb700_lpc_init();
+
+	sio_init();
+	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
+
+	setup_939a785gmh_resource_map();
+
+	setup_coherent_ht_domain();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* It is said that we should start core1 after all core0 launched */
+	wait_all_core0_started();
+	start_other_cores();
+#endif
+	wait_all_aps_started(bsp_apicid);
+
+	ht_setup_chains_x(sysinfo);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+	sb700_early_setup();
+
+	/* Check to see if processor is capable of changing FIDVID  */
+	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
+	cpuid1 = cpuid(0x80000007);
+	if( (cpuid1.edx & 0x6) == 0x6 ) {
+
+		/* Read FIDVID_STATUS */
+		msr=rdmsr(0xc0010042);
+		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+		enable_fid_change();
+		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+		init_fidvid_bsp(bsp_apicid);
+
+		/* show final fid and vid */
+		msr=rdmsr(0xc0010042);
+		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+	} else {
+		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
+	}
+
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	rs780_htinit();
+	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
+
+	if (needs_reset) {
+		print_info("ht reset -\n");
+		soft_reset();
+	}
+
+	allow_all_aps_stop(bsp_apicid);
+
+	/* It's the time to set ctrl now; */
+	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
+		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+	rs780_before_pci_init();
+	sb700_before_pci_init();
+
+	post_cache_as_ram();
+}
+

Added: trunk/src/mainboard/asrock/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/asrock/Kconfig	Mon Apr  5 21:47:34 2010	(r5357)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_ASROCK
+
+source "src/mainboard/asrock/939a785gmh/Kconfig"
+
+endchoice
+



From r.marek at assembler.cz  Mon Apr  5 21:54:37 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Mon, 05 Apr 2010 21:54:37 +0200
Subject: [coreboot] [PATCH] Quick and dirty Asrock 939A785GMH support
In-Reply-To: <4BA01074.6000702@coresystems.de>
References: <4BA005D1.5020803@assembler.cz> <4BA01074.6000702@coresystems.de>
Message-ID: <4BBA3FFD.1030900@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Ok I checked that in as 5357. The cleanup of console etc stuff included.

Add Asrock 939a785gmh motherboard. The ACPI needs more cleanup, could be done
when cleaningthe Mahagony board. The SidePort mode does not work because AMD
hardcoded memory type in rs780_gfx.c The UMA is enabled instead. The board
boots, network and int VGA works, IDE too.

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAku6P/0ACgkQ3J9wPJqZRNX+nQCgly3INNmynQi+WAbTqfQo1wTi
eTMAoN1jkhEnHF9bCc9sMuyGwRjaWsss
=DUk8
-----END PGP SIGNATURE-----



From austinro at msu.edu  Tue Apr  6 20:56:43 2010
From: austinro at msu.edu (austinro at msu.edu)
Date: Tue, 06 Apr 2010 14:56:43 -0400
Subject: [coreboot] GSOC: thoughts on projects
Message-ID: <20100406145643.12073rxk92o6xiwb@mail.msu.edu>

Hi.  My name's Rob Austin, I'm a computer engineering major at  
Michigan State University.  I got on IRC for a bit a week or so ago  
and chatted with a few people about some of the proposed ideas.  I've  
had some time to think and read more about what I could do for  
coreboot, and I'd like to get a little more feedback.

- First, the "tianocore" idea.  What do you see as the end result of  
getting tianocore working well as a payload?  I've been reading about  
it and it sounds interesting, but I need to say something more on the  
application as to "why" this is a worthwhile project.  What can we  
boot with EFI that we can't boot with a traditional bios, besides  
maybe OSX?

- Second, just how difficult would the port to the Marvell chipset be?  
  I'm familiar with the ARM architecture and assembly, more so than  
x86, and realistically in my future I'll probably be working more with  
embedded devices than PCs, so this might be the more valuable  
experience to put on a resume.

Also, I was planning on applying both to coreboot and beagleboard (my  
fallback), doing largely the same thing.  For beagleboard's GSOC  
project page, they have "Improve bootloader support"  
http://elinux.org/BeagleBoard/GSoC/Ideas#Improve_bootloader_support
listed as an idea.  If someone could port coreboot to one ARM device,  
it would probably be considerably easier to then port it to other ARM  
devices.

I want to be up front about my ignorance here:  I don't know much  
about BIOSes.  There seems to be a hole in my computer engineering  
curriculum.  With all the required classes, I've started understanding  
computers from the bottom (transistor physics and digital logic), and  
built up from that (combinational logic, VLSI design, computer  
architecture) --the hardware--, and at the same time I've been  
learning about them from the top down --high level languages, then  
assembler and operating systems, the software side.  Ideally they  
would meet in the middle and teach about the bios, but they don't.   
I've asked.  I don't feel that my education would be complete without  
this knowledge.  I don't like the idea that there's hardware,  
software, and some magical binary blob in the middle that connects  
them.  I want to understand it, and I want it to be open.  You can't  
trust a blob.

So that's why I want to work at the  
bios/hardware-initialization/bootloader level.  There are only two  
projects for GSOC that focus on the hardware-software interface, and  
I'd be happy to work on either one.  There are other reasons: I want  
to become a good programmer, and reading and writing code every day  
for a whole summer will do that;  I want to do something meaningful  
that people will actually use, to give back to the open-source  
community after benefitting from it for so many years.

So having said all that, I would appreciate any feedback as far as  
what the devs think is more doable/would be more useful.  I'm  
interested in both projects, but if following one path will lead to a  
summer of banging my head against the wall and failure, I'd rather  
choose the other.  Writing "I spent 3 months participating in GSOC and  
accomplished nothing" doesn't look so hot.

Thanks.

Rob Austin






From joe at settoplinux.org  Tue Apr  6 22:51:23 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Tue, 06 Apr 2010 16:51:23 -0400
Subject: [coreboot] GSOC: thoughts on projects
In-Reply-To: <20100406145643.12073rxk92o6xiwb@mail.msu.edu>
References: <20100406145643.12073rxk92o6xiwb@mail.msu.edu>
Message-ID: <4BBB9ECB.6050204@settoplinux.org>

On 04/06/2010 02:56 PM, austinro at msu.edu wrote:
> Hi.  My name's Rob Austin, I'm a computer engineering major at Michigan
> State University. I got on IRC for a bit a week or so ago and chatted
> with a few people about some of the proposed ideas. I've had some time
> to think and read more about what I could do for coreboot, and I'd like
> to get a little more feedback.
>
> - First, the "tianocore" idea. What do you see as the end result of
> getting tianocore working well as a payload? I've been reading about it
> and it sounds interesting, but I need to say something more on the
> application as to "why" this is a worthwhile project. What can we boot
> with EFI that we can't boot with a traditional bios, besides maybe OSX?
>
> - Second, just how difficult would the port to the Marvell chipset be?
> I'm familiar with the ARM architecture and assembly, more so than x86,
> and realistically in my future I'll probably be working more with
> embedded devices than PCs, so this might be the more valuable experience
> to put on a resume.
>
> Also, I was planning on applying both to coreboot and beagleboard (my
> fallback), doing largely the same thing. For beagleboard's GSOC project
> page, they have "Improve bootloader support"
> http://elinux.org/BeagleBoard/GSoC/Ideas#Improve_bootloader_support
> listed as an idea. If someone could port coreboot to one ARM device, it
> would probably be considerably easier to then port it to other ARM devices.
>
> I want to be up front about my ignorance here: I don't know much about
> BIOSes. There seems to be a hole in my computer engineering curriculum.
> With all the required classes, I've started understanding computers from
> the bottom (transistor physics and digital logic), and built up from
> that (combinational logic, VLSI design, computer architecture) --the
> hardware--, and at the same time I've been learning about them from the
> top down --high level languages, then assembler and operating systems,
> the software side. Ideally they would meet in the middle and teach about
> the bios, but they don't. I've asked. I don't feel that my education
> would be complete without this knowledge. I don't like the idea that
> there's hardware, software, and some magical binary blob in the middle
> that connects them. I want to understand it, and I want it to be open.
> You can't trust a blob.
>
> So that's why I want to work at the
> bios/hardware-initialization/bootloader level. There are only two
> projects for GSOC that focus on the hardware-software interface, and I'd
> be happy to work on either one. There are other reasons: I want to
> become a good programmer, and reading and writing code every day for a
> whole summer will do that; I want to do something meaningful that people
> will actually use, to give back to the open-source community after
> benefitting from it for so many years.
>
> So having said all that, I would appreciate any feedback as far as what
> the devs think is more doable/would be more useful. I'm interested in
> both projects, but if following one path will lead to a summer of
> banging my head against the wall and failure, I'd rather choose the
> other. Writing "I spent 3 months participating in GSOC and accomplished
> nothing" doesn't look so hot.
>
Hello and Welcome Rob!
I think the tianocore payload is the most realistic. And I believe it 
was partially started already, so it may easier to get familiar with. 
This would be great to see running along side coreboot.

Don't get me wrong I think the ARM project would be cool too, but it 
will take alot of work to port coreboot to ARM, then again it would open 
coreboot to a whole new audiance.

Either way you will have full support of the coreboot team.
Great to have you aboard :-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From rminnich at gmail.com  Tue Apr  6 21:59:44 2010
From: rminnich at gmail.com (ron minnich)
Date: Tue, 6 Apr 2010 12:59:44 -0700
Subject: [coreboot] GSOC: thoughts on projects
In-Reply-To: <20100406145643.12073rxk92o6xiwb@mail.msu.edu>
References: <20100406145643.12073rxk92o6xiwb@mail.msu.edu>
Message-ID: <q2u13426df11004061259je913a32ft8f2070eb366b3ab0@mail.gmail.com>

If you have never done a bios before I would take a more limited scope
project, maybe getting v4 working on geode, which we really need.

I would think twice about the marvell, that may be too much for the summer.

ron



From svn at coreboot.org  Tue Apr  6 23:49:31 2010
From: svn at coreboot.org (repository service)
Date: Tue, 06 Apr 2010 21:49:31 +0000
Subject: [coreboot] [commit] r5358 - trunk/src/northbridge/amd/amdfam10
Message-ID: <E1NzGeJ-0002zY-Kq@ra.coresystems.de>

Author: stepan
Date: Tue Apr  6 21:49:31 2010
New Revision: 5358
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5358

Log:
fam10 acpi fix 

Signed-off-by: Stefan Reinauer<stepan at coresystems.de> 
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c

Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c	Mon Apr  5 19:47:34 2010	(r5357)
+++ trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c	Tue Apr  6 21:49:31 2010	(r5358)
@@ -296,10 +296,10 @@
 
 	for(i=0;i<sysconf.p_state_num;i++) {
 		struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i];
-		intx_to_stream(COREFREQ + i*offset, 2, p_state->corefreq);
-		intx_to_stream(POWER + i*offset, 3, p_state->power);
-		intx_to_stream(TRANSITION_LAT + i*offset, 2, p_state->transition_lat);
-		intx_to_stream(BUSMASTER_LAT + i*offset, 2, p_state->busmaster_lat);
+		intx_to_stream(p_state->corefreq, 2, COREFREQ + i*offset);
+		intx_to_stream(p_state->power, 3, POWER + i*offset);
+		intx_to_stream(p_state->transition_lat, 2, TRANSITION_LAT + i*offset);
+		intx_to_stream(p_state->busmaster_lat, 2, BUSMASTER_LAT + i*offset);
 		*((u8 *)(CONTROL + i*offset)) =(u8) p_state->control;
 		*((u8 *)(STATUS + i*offset)) =(u8) p_state->status;
 	}



From svn at coreboot.org  Tue Apr  6 23:50:22 2010
From: svn at coreboot.org (repository service)
Date: Tue, 06 Apr 2010 21:50:22 +0000
Subject: [coreboot] [commit] r5359 - in trunk/src: . cpu/amd/model_10xxx
	cpu/amd/model_fxx cpu/amd/model_lx cpu/x86/mtrr
	include/cpu/x86 mainboard/amd/mahogany_fam10
	mainboard/amd/serengeti_cheetah mainboard/asus/a8n_...
Message-ID: <E1NzGf8-0004Ae-8Y@ra.coresystems.de>

Author: stepan
Date: Tue Apr  6 21:50:21 2010
New Revision: 5359
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359

Log:
No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/Kconfig
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c
   trunk/src/cpu/amd/model_lx/cpureginit.c
   trunk/src/cpu/x86/mtrr/earlymtrr.c
   trunk/src/include/cpu/x86/cache.h
   trunk/src/include/cpu/x86/mtrr.h
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/asus/a8n_e/mptable.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/intel/d945gclf/Makefile.inc
   trunk/src/mainboard/kontron/986lcd-m/Makefile.inc
   trunk/src/mainboard/roda/rk886ex/Makefile.inc
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/northbridge/amd/amdk8/amdk8_f.h
   trunk/src/northbridge/amd/amdk8/misc_control.c
   trunk/src/northbridge/amd/amdk8/raminit.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c
   trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
   trunk/src/northbridge/amd/lx/raminit.c
   trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
   trunk/src/southbridge/amd/cs5536/cs5536_ide.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.h
   trunk/src/southbridge/via/vt8237r/vt8237_fadt.c

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/Kconfig	Tue Apr  6 21:50:21 2010	(r5359)
@@ -621,7 +621,8 @@
 	depends on (SOUTHBRIDGE_VIA_VT8237R \
 		 || NORTHBRIDGE_VIA_VX800 \
 		 || NORTHBRIDGE_VIA_CX700 \
-		 || NORTHBRIDGE_AMD_AMDK8)
+		 || NORTHBRIDGE_AMD_AMDK8 \
+		 || NORTHBRIDGE_AMD_AMDFAM10)
 	help
 	  This option enables additional SMBus (and SPD) debug messages.
 

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -91,7 +91,7 @@
 	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
 
 	//mtrr for that range?
-//	set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
+	// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
 
 	set_wrap32dis();
 
@@ -293,7 +293,7 @@
 }
 
 
-static void STOP_CAR_AND_CPU()
+static void STOP_CAR_AND_CPU(void)
 {
 	msr_t msr;
 
@@ -529,7 +529,7 @@
 }
 #endif	/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-void AMD_Errata281(u8 node, u32 revision, u32 platform)
+static void AMD_Errata281(u8 node, u32 revision, u32 platform)
 {
 	/* Workaround for Transaction Scheduling Conflict in
 	 * Northbridge Cross Bar.  Implement XCS Token adjustment
@@ -591,7 +591,7 @@
 }
 
 
-void AMD_Errata298(void)
+static void AMD_Errata298(void)
 {
 	/* Workaround for L2 Eviction May Occur during operation to
 	 * set Accessed or dirty bit.

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -244,7 +244,6 @@
 static void init_ecc_memory(unsigned node_id)
 {
 	unsigned long startk, begink, endk;
-	unsigned long hole_startk = 0;
 	unsigned long basek;
 	struct mtrr_state mtrr_state;
 
@@ -291,6 +290,8 @@
 	endk   = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	unsigned long hole_startk = 0;
+
 	#if CONFIG_K8_REV_F_SUPPORT == 0
         if (!is_cpu_pre_e0())
 	{

Modified: trunk/src/cpu/amd/model_lx/cpureginit.c
==============================================================================
--- trunk/src/cpu/amd/model_lx/cpureginit.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/cpu/amd/model_lx/cpureginit.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -25,7 +25,7 @@
 ;*	SetDelayControl
 ;*
 ;*************************************************************************/
-void SetDelayControl(void)
+static void SetDelayControl(void)
 {
 	unsigned int msrnum, glspeed;
 	unsigned char spdbyte0, spdbyte1;

Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==============================================================================
--- trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -4,37 +4,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
-# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
-#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
-
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE)
-# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-   extern unsigned long AUTO_XIP_ROM_BASE;
-#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-# else
-#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-# endif
-#endif
-
+#if 0
 static void disable_var_mtrr(unsigned reg)
 {
 	/* The invalid bit is kept in the mask so we simply
@@ -45,6 +15,7 @@
 	zero.lo = zero.hi = 0;
 	wrmsr(MTRRphysMask_MSR(reg), zero);
 }
+#endif
 
 static void set_var_mtrr(
 	unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -61,6 +32,7 @@
 	wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+#if 0
 static void set_var_mtrr_x(
         unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
 
@@ -79,6 +51,7 @@
 	}
         wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
+#endif
 
 static void cache_lbmem(int type)
 {

Modified: trunk/src/include/cpu/x86/cache.h
==============================================================================
--- trunk/src/include/cpu/x86/cache.h	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/include/cpu/x86/cache.h	Tue Apr  6 21:50:21 2010	(r5359)
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2004 Eric W. Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #ifndef CPU_X86_CACHE
 #define CPU_X86_CACHE
 
@@ -17,6 +36,7 @@
 {
 	asm volatile("invd" ::: "memory");
 }
+
 static inline void wbinvd(void)
 {
 	asm volatile ("wbinvd");

Modified: trunk/src/include/cpu/x86/mtrr.h
==============================================================================
--- trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:50:21 2010	(r5359)
@@ -31,7 +31,6 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
-
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
@@ -42,5 +41,39 @@
 void x86_setup_fixed_mtrrs(void);
 #endif
 
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
+# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
+#endif
+#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
+# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
+#endif
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
+#endif
+
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
+# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
+#endif
+
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
+#endif
+
+
+#if !defined (ASSEMBLY)
+#if defined(CONFIG_XIP_ROM_SIZE)
+# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+   extern unsigned long AUTO_XIP_ROM_BASE;
+#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+# else
+#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+# endif
+#endif
+
+#endif
 
 #endif /* CPU_X86_MTRR_H */

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -58,18 +58,13 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 
 #include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#endif
-#define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #include "southbridge/amd/rs780/rs780_early_setup.c"

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -29,20 +29,11 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
 #include "pc80/serial.c"
 #include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
@@ -54,7 +45,8 @@
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

Modified: trunk/src/mainboard/asus/a8n_e/mptable.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/mptable.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/asus/a8n_e/mptable.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -41,7 +41,7 @@
 	static const char productid[12] = "A8N-E      ";
 	struct mp_config_table *mc;
 	unsigned sbdn;
-	int i, bus_num;
+	int bus_num;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -96,7 +96,6 @@
 
 static void sio_setup(void)
 {
-	unsigned value;
 	uint32_t dword;
 	uint8_t byte;
 

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -187,7 +187,6 @@
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
 	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-	char *p;
 
 	sio_init();
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/intel/d945gclf/Makefile.inc
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/Makefile.inc	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/intel/d945gclf/Makefile.inc	Tue Apr  6 21:50:21 2010	(r5359)
@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

Modified: trunk/src/mainboard/kontron/986lcd-m/Makefile.inc
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/Makefile.inc	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/kontron/986lcd-m/Makefile.inc	Tue Apr  6 21:50:21 2010	(r5359)
@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

Modified: trunk/src/mainboard/roda/rk886ex/Makefile.inc
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/Makefile.inc	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/roda/rk886ex/Makefile.inc	Tue Apr  6 21:50:21 2010	(r5359)
@@ -17,13 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += m3885.o
 obj-y += ec.o
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -56,7 +56,6 @@
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
-        int ret;
         unsigned device=(ctrl->channel0[0])>>8;
         smbus_write_byte(SMBUS_HUB, 0x01, device);
         smbus_write_byte(SMBUS_HUB, 0x03, 0);

Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8_f.h	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/amdk8/amdk8_f.h	Tue Apr  6 21:50:21 2010	(r5359)
@@ -520,6 +520,8 @@
 
 #include <reset.h>
 
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
+	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
@@ -585,5 +587,6 @@
 	}
 
 }
+#endif
 
 #endif /* AMDK8_F_H */

Modified: trunk/src/northbridge/amd/amdk8/misc_control.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/misc_control.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/amdk8/misc_control.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -110,7 +110,7 @@
 {
 	uint32_t cmd, cmd_ref;
 	int needs_reset;
-	struct device *f0_dev, *f2_dev;
+	struct device *f0_dev;
 	
 	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
@@ -161,6 +161,7 @@
 		}
 	}
 	else if(is_cpu_pre_d0()) {
+		struct device *f2_dev;
 		uint32_t dcl;
 		f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
 		/* Errata 98 

Modified: trunk/src/northbridge/amd/amdk8/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/amdk8/raminit.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -18,10 +18,6 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if defined (__GNUC__)
-static void hard_reset(void);
-#endif
-
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -707,12 +707,14 @@
 	printk(BIOS_SPEW, "done.\n");
 }
 
+#if 0
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return dcl & DCL_Width128;
 }
+#endif
 
 static int is_opteron(const struct mem_controller *ctrl)
 {
@@ -727,6 +729,7 @@
 	return !!(nbcap & NBCAP_128Bit);
 }
 
+#if 0
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -737,7 +740,7 @@
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return !(dcl & DCL_UnBuffDimm);
 }
-
+#endif
 
 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 {
@@ -2481,6 +2484,7 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 static void set_SlowAccessMode(const struct mem_controller *ctrl)
 {
 	uint32_t dch;
@@ -2491,6 +2495,7 @@
 
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
+#endif
 
 /*
 	DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20

Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -1872,6 +1872,7 @@
 	return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
 	/* 30 bytes per channel */
@@ -1902,6 +1903,7 @@
 	reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
 	pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {

Modified: trunk/src/northbridge/amd/lx/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/northbridge/amd/lx/raminit.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -35,7 +35,7 @@
 	print_debug("======================================\n");
 }
 
-void hcf(void)
+static void hcf(void)
 {
 	print_emerg("DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also 

Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
==============================================================================
--- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -35,7 +35,7 @@
 	enable_cf9_x(sbbusn, sbdn);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         set_bios_reset();
         /* reset */
@@ -68,7 +68,7 @@
 
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 
 	unsigned sblk = get_sblk();

Modified: trunk/src/southbridge/amd/cs5536/cs5536_ide.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536_ide.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/amd/cs5536/cs5536_ide.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -46,13 +46,6 @@
 	pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
-static void ide_enable(struct device *dev)
-{
-
-	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
-
-}
-
 static struct device_operations ide_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,

Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -371,10 +371,9 @@
 #endif	/* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
-void fam10_optimization(void)
+static void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
-	msr_t msr;
 	u32 val;
 
 	printk(BIOS_INFO, "fam10_optimization()\n");
@@ -634,16 +633,16 @@
 }
 
 /* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8()
+static void enable_rs780_dev8(void)
 {
 	set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
 }
 
-static void rs780_before_pci_init()
+static void rs780_before_pci_init(void)
 {
 }
 
-static void rs780_early_setup()
+static void rs780_early_setup(void)
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
 	printk(BIOS_INFO, "rs780_early_setup()\n");

Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/amd/sb700/sb700_smbus.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -205,7 +205,7 @@
 /* space = 0: AX_INDXC, AX_DATAC
  * space = 1: AX_INDXP, AX_DATAP
  */
-static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
 			  u32 mask, u32 val)
 {
 	u32 tmp;

Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.h	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/amd/sb700/sb700_smbus.h	Tue Apr  6 21:50:21 2010	(r5359)
@@ -20,8 +20,6 @@
 #ifndef SB700_SMBUS_H
 #define SB700_SMBUS_H
 
-//#include <stdint.h>
-
 #define SMBHSTSTAT 0x0
 #define SMBSLVSTAT 0x1
 #define SMBHSTCTRL 0x2

Modified: trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237_fadt.c	Tue Apr  6 21:49:31 2010	(r5358)
+++ trunk/src/southbridge/via/vt8237r/vt8237_fadt.c	Tue Apr  6 21:50:21 2010	(r5359)
@@ -51,8 +51,8 @@
 	memcpy(header->asl_compiler_id, "CORE", 4);
 	header->asl_compiler_revision = 42;
 
-	fadt->firmware_ctrl = facs;
-	fadt->dsdt = dsdt;
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
 	fadt->preferred_pm_profile = 0;
 	fadt->sci_int = 9;
 	fadt->smi_cmd = 0;
@@ -108,9 +108,9 @@
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;



From mylesgw at gmail.com  Wed Apr  7 00:06:06 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 6 Apr 2010 16:06:06 -0600
Subject: [coreboot] [commit] r5359 - in trunk/src: .
	cpu/amd/model_10xxxcpu/amd/model_fxx cpu/amd/model_lx
	cpu/x86/mtrrinclude/cpu/x86
	mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah
	mainboard/asus/a8n_...
In-Reply-To: <E1NzGf8-0004Ae-8Y@ra.coresystems.de>
References: <E1NzGf8-0004Ae-8Y@ra.coresystems.de>
Message-ID: <50E7FDA364984298AC5EDF0000E01285@chimp>



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of repository service
> Sent: Tuesday, April 06, 2010 3:50 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] [commit] r5359 - in trunk/src: .
> cpu/amd/model_10xxxcpu/amd/model_fxx cpu/amd/model_lx
> cpu/x86/mtrrinclude/cpu/x86
> mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah
> mainboard/asus/a8n_...
> 
> Author: stepan
> Date: Tue Apr  6 21:50:21 2010
> New Revision: 5359
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359
> 
> Log:
> No warnings day, next round.
Thanks.

>    trunk/src/cpu/x86/mtrr/earlymtrr.c

>    trunk/src/include/cpu/x86/mtrr.h

> Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
> ==========================================================================
> ====
> --- trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:49:31 2010
> 	(r5358)
> +++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:50:21 2010
> 	(r5359)
> @@ -4,37 +4,7 @@
>  #include <cpu/x86/mtrr.h>
>  #include <cpu/x86/msr.h>
> 
> -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
> -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
> -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
...
I'm surprised you wanted to move this.  It made sense to me to check it when
compiling CAR.

> Modified: trunk/src/include/cpu/x86/mtrr.h
> ==========================================================================
> ====
> --- trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:49:31 2010
> 	(r5358)
> +++ trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:50:21 2010
> 	(r5359)
...
> +#if !defined(CONFIG_RAMTOP)
> +# error "CONFIG_RAMTOP not defined"
> +#endif

Now that we have Kconfig, I think this check can disappear.  Is there a way
to un-define CONFIG_RAMTOP?

Thanks,
Myles




From mylesgw at gmail.com  Wed Apr  7 00:21:57 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 6 Apr 2010 16:21:57 -0600
Subject: [coreboot] memset called to somewhere high on the stack (uncached)
Message-ID: <9281742AE71C4F5C9017A52ABC2C857A@chimp>

I'm seeing code reads to memset() in coreboot_ram interleaved with byte
writes to somewhere high on the stack (_estack -0x1fC).  This is a k8.

I can't find the place during the RAM stage when we are calling memset with
caches disabled.  Does this ring a bell for anyone?

Thanks,
Myles




From stepan at coresystems.de  Wed Apr  7 00:25:27 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 07 Apr 2010 00:25:27 +0200
Subject: [coreboot] [commit] r5359 - in trunk/src:
 .	cpu/amd/model_10xxxcpu/amd/model_fxx
 cpu/amd/model_lx	cpu/x86/mtrrinclude/cpu/x86	mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah
 mainboard/asus/a8n_...
In-Reply-To: <4BBBB4A7.8010908@coresystems.de>
References: <E1NzGf8-0004Ae-8Y@ra.coresystems.de>
	<50E7FDA364984298AC5EDF0000E01285@chimp>
	<4BBBB4A7.8010908@coresystems.de>
Message-ID: <4BBBB4D7.2080302@coresystems.de>

wasn't meant to be private only.

On 4/7/10 12:24 AM, Stefan Reinauer wrote:
> On 4/7/10 12:06 AM, Myles Watson wrote:
>   
>>   
>>     
>>> -----Original Message-----
>>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>>> On Behalf Of repository service
>>> Sent: Tuesday, April 06, 2010 3:50 PM
>>> To: coreboot at coreboot.org
>>> Subject: [coreboot] [commit] r5359 - in trunk/src: .
>>> cpu/amd/model_10xxxcpu/amd/model_fxx cpu/amd/model_lx
>>> cpu/x86/mtrrinclude/cpu/x86
>>> mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah
>>> mainboard/asus/a8n_...
>>>
>>> Author: stepan
>>> Date: Tue Apr  6 21:50:21 2010
>>> New Revision: 5359
>>> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359
>>>
>>> Log:
>>> No warnings day, next round.
>>>     
>>>       
>> Thanks.
>>
>>   
>>     
>>>    trunk/src/cpu/x86/mtrr/earlymtrr.c
>>>     
>>>       
>>   
>>     
>>>    trunk/src/include/cpu/x86/mtrr.h
>>>     
>>>       
>>   
>>     
>>> Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
>>> ==========================================================================
>>> ====
>>> --- trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:49:31 2010
>>> 	(r5358)
>>> +++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Tue Apr  6 21:50:21 2010
>>> 	(r5359)
>>> @@ -4,37 +4,7 @@
>>>  #include <cpu/x86/mtrr.h>
>>>  #include <cpu/x86/msr.h>
>>>
>>> -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
>>> -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
>>> -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
>>>     
>>>       
>> ...
>> I'm surprised you wanted to move this.  It made sense to me to check it when
>> compiling CAR.
>>   
>>     
> The idea was to be able to have the check, no matter if only
> cpu/x86/earlymtrr.c or only cpu/amd/amd_earlymtrr.c is included.
>
> It seems that in the long term most of the earlymtrr code can completely
> go away though, so I was not sure where to put it.
>
>   
>>> Modified: trunk/src/include/cpu/x86/mtrr.h
>>> ==========================================================================
>>> ====
>>> --- trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:49:31 2010
>>> 	(r5358)
>>> +++ trunk/src/include/cpu/x86/mtrr.h	Tue Apr  6 21:50:21 2010
>>> 	(r5359)
>>>     
>>>       
>> ...
>>   
>>     
>>> +#if !defined(CONFIG_RAMTOP)
>>> +# error "CONFIG_RAMTOP not defined"
>>> +#endif
>>>     
>>>       
>> Now that we have Kconfig, I think this check can disappear.  Is there a way
>> to un-define CONFIG_RAMTOP?
>>     
> In theory, yes. If you say this in Kconfig:
>
> config FOO
> bool
> depends on SOME_FEATURE
>
> config BAR
> bool
> depends on FOO
>
> You might end up with BAR not being there even though we modified
> Kconfig to always set 0 bools to 0 instead of omitting them.
> That's because Kconfig completely skips BAR if FOO is not set.
>
> With RAMTOP being
>
> config RAMTOP
> hex
> default 0x200000
>
> it can't happen.
>
> But I didn't want to change the rough logical flow with self-acked code,
> so I thought I better leave an error check too many in there ;-)
>
> If you feel it should go, you have my Acked-by: Stefan Reinauer
> <stepan at coresystems.de>
>
>   


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866




From r.marek at assembler.cz  Wed Apr  7 00:26:20 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 07 Apr 2010 00:26:20 +0200
Subject: [coreboot] memset called to somewhere high on the stack
	(uncached)
In-Reply-To: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
References: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
Message-ID: <4BBBB50C.30003@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Maybe you can run under SimNow and use a memory access breakpoint?

Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAku7tQsACgkQ3J9wPJqZRNVLPQCeOgzlrj7Sj2n6mLBWLuTH0s4e
1RUAoNT+qYrw+z3LSuHDoxVYg6KYgl1F
=ngTh
-----END PGP SIGNATURE-----



From info at coresystems.de  Wed Apr  7 00:38:06 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 00:38:06 +0200
Subject: [coreboot] build service results for r5359
Message-ID: <E1NzHPK-00027E-HV@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5359 to
the coreboot repository. This caused the following 
changes:

Change Log:
No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of asus:a8n_e has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=a8n_e&vendor=asus&num=2
Compilation of msi:ms7135 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=ms7135&vendor=msi&num=2
Compilation of sunw:ultra40 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=ultra40&vendor=sunw&num=2
Compilation of tyan:s2891 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2891&vendor=tyan&num=2
Compilation of tyan:s2892 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2892&vendor=tyan&num=2
Compilation of tyan:s2895 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2895&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From r.marek at assembler.cz  Wed Apr  7 00:48:11 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 07 Apr 2010 00:48:11 +0200
Subject: [coreboot] memset called to somewhere high on the stack
	(uncached)
In-Reply-To: <B5283B68B13D4878A6ECF1EBB706D75A@chimp>
References: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
	<4BBBB50C.30003@assembler.cz>
	<B5283B68B13D4878A6ECF1EBB706D75A@chimp>
Message-ID: <4BBBBA2B.3050507@assembler.cz>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Myles Watson wrote:
>> Maybe you can run under SimNow and use a memory access breakpoint?
> Good idea.  How do you tell in SimNow if an access is cached or not?

Dont know maybe you can check CPU state after a breakpoint?

Rudolf

> 
> Thanks,
> Myles
> 
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAku7uisACgkQ3J9wPJqZRNWZKgCeOmk8RkQxx6arPtKfSQ0pk9KC
+qYAn3ucXF5SUBXJK8Z5cRq/6UN5ajQF
=1y0R
-----END PGP SIGNATURE-----



From mylesgw at gmail.com  Wed Apr  7 00:44:00 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 6 Apr 2010 16:44:00 -0600
Subject: [coreboot] memset called to somewhere high on the stack
	(uncached)
In-Reply-To: <4BBBB50C.30003@assembler.cz>
References: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
	<4BBBB50C.30003@assembler.cz>
Message-ID: <B5283B68B13D4878A6ECF1EBB706D75A@chimp>

> Maybe you can run under SimNow and use a memory access breakpoint?
Good idea.  How do you tell in SimNow if an access is cached or not?

Thanks,
Myles




From mylesgw at gmail.com  Wed Apr  7 00:47:42 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 6 Apr 2010 16:47:42 -0600
Subject: [coreboot] [commit] r5359 - in trunk/src:
	.	cpu/amd/model_10xxxcpu/amd/model_fxx
	cpu/amd/model_lx	cpu/x86/mtrrinclude/cpu/x86	mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah
	mainboard/asus/a8n_...
In-Reply-To: <4BBBB4D7.2080302@coresystems.de>
References: <E1NzGf8-0004Ae-8Y@ra.coresystems.de>
	<50E7FDA364984298AC5EDF0000E01285@chimp>
	<4BBBB4A7.8010908@coresystems.de> <4BBBB4D7.2080302@coresystems.de>
Message-ID: <105BC0675F664535BEFF44181AFB43FB@chimp>

> >> Now that we have Kconfig, I think this check can disappear.  Is there a
> way
> >> to un-define CONFIG_RAMTOP?

> > With RAMTOP being
> >
> > config RAMTOP
> > hex
> > default 0x200000
> >
> > it can't happen.
> >
> > But I didn't want to change the rough logical flow with self-acked code,
> > so I thought I better leave an error check too many in there ;-)

I agree that it's good to be careful.

I think it clutters this file to have so many checks.  I wonder if there
should be some central file for checking Kconfig variables.

Thanks,
Myles




From secretocean at gmx.de  Wed Apr  7 01:05:35 2010
From: secretocean at gmx.de (secretocean at gmx.de)
Date: Wed, 07 Apr 2010 01:05:35 +0200
Subject: [coreboot] Need confirmation if HP nx6310 will work with coreboot
Message-ID: <20100406230535.171610@gmx.net>

Hi,

I've got an HP nx6310 notebook with Linux as operating system and I'm thinking of trying coreboot to get rid of the non-free HP BIOS.
Though I'm quite confident that the chipset is supported, it'll be nice if someone would confirm that and perhaps give further instructions on how to use coreboot with my mainboard.

Notebook: HP nx6310 EY366EA#ABD
no extensions at all, except a PCMCIA WLAN card with Atheros chipset
BIOS version: F.0E
CPU: Intel Celeron M 1,46GHz
RAM: 1GB (512MB by default)
Graphics card: on board, Intel GMA 945
Sound card: on board, Intel HDA ... (don't know the exact model)

Outputs of lspci -tvnn, superiotool -dV and flashrom -V: see text files

Hopefully someone can help. I'd love to help making coreboot better but without shooting my mainboard.

Thanks!
-- 
GRATIS f?r alle GMX-Mitglieder: Die maxdome Movie-FLAT!
Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01
-------------- next part --------------
superiotool r3844
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0x26, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
No Super I/O found
-------------- next part --------------
-[0000:00]-+-00.0  Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0]
           +-02.0  Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2]
           +-02.1  Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6]
           +-1b.0  Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8]
           +-1c.0-[0000:08]--
           +-1d.0  Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
           +-1d.1  Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9]
           +-1d.2  Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca]
           +-1d.3  Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb]
           +-1d.7  Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc]
           +-1e.0-[0000:02-06]--+-[0000:03]---00.0  Atheros Communications Inc. AR2413 802.11bg NIC [168c:001a]
           |                    \-[0000:02]-+-06.0  Texas Instruments PCIxx12 Cardbus Controller [104c:8039]
           |                                \-0e.0  Broadcom Corporation BCM4401-B0 100Base-TX [14e4:170c]
           +-1f.0  Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9]
           +-1f.1  Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
           \-1f.2  Intel Corporation 82801GBM/GHM (ICH7 Family) SATA AHCI Controller [8086:27c5]
-------------- next part --------------
flashrom v0.9.1-r946
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "HP Compaq nx6310 (EY366EA#ABD)"
DMI string system-version: "F.0E"
DMI string baseboard-manufacturer: "Hewlett-Packard"
DMI string baseboard-product-name: "30AA"
DMI string baseboard-version: "KBC Version 58.13"
DMI string chassis-type: "Notebook"
Laptop detected via DMI
========================================================================
WARNING! You seem to be running flashrom on a laptop.
Laptops, notebooks and netbooks are difficult to support and we recommend
to use the vendor flashing utility. The embedded controller (EC) in these
machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.
========================================================================
Found chipset "Intel ICH7M", enabling flash write... 
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode disabled
0xffe00000/0xffa00000 FWH decode disabled
0xffd80000/0xff980000 FWH decode disabled
0xffd00000/0xff900000 FWH decode disabled
0xffc80000/0xff880000 FWH decode disabled
0xffc00000/0xff800000 FWH decode disabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
Maximum FWH chip size: 0x100000 bytes
BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0

Root Complex Register Block address = 0xfed90000
GCS = 0x4e0460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
Top Swap : not enabled
SPIBAR = 0xfed90000 + 0x3020
0x00: 0x8004     (SPIS)
0x02: 0x0030     (SPIC)
0x04: 0x00000000 (SPIA)
0x08: 0x00000000 (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0x00000000 (SPID2)
0x1c: 0x00000000 (SPID2+4)
0x20: 0x00000000 (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0x00000000 (SPID4)
0x2c: 0x00000000 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x00000000 (SPID6)
0x3c: 0x00000000 (SPID6+4)
0x40: 0x00000000 (SPID7)
0x44: 0x00000000 (SPID7+4)
0x50: 0x00000000 (BBAR)
0x54: 0x5006     (PREOP)
0x56: 0x7f48     (OPTYPE)
0x58: 0x0405039f (OPMENU)
0x5c: 0x0102d852 (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
0x6c: 0x00000000 (PBR3)

WARNING: SPI Configuration Lockdown activated.
Generating OPCODES... done
SPI Read Configuration: prefetching disabled, caching enabled, OK.
This chipset supports the following protocols: SPI.
Calibrating delay loop... 411M loops per second, 100 myus = 198 us. OK.
Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ASD AE49F2008, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT25DF021, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25F512B, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25FS010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT25FS040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT26DF041, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT26F004, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT29C512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT29C020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMIC A25L40PT, 512 KB: RDID returned 0xc2 0x20 0x14 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for AMIC A25L40PU, 512 KB: RDID returned 0xc2 0x20 0x14 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for AMIC A29002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMIC A29002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMIC A29040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for EMST F49B002UA, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Eon EN25B05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B05T, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B10T, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B20T, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B40T, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B80T, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B16T, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B32T, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25B64T, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25D16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F05, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN25F32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Eon EN29F010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Intel 28F004S5, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Intel 82802AB, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Intel 82802AC, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Macronix MX25L512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L1005, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L2005, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L4005, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Chip status register is 00
Chip status register: Status Register Write Disable (SRWD) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000.
Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Numonyx M25PE10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Numonyx M25PE20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Numonyx M25PE40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV010, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV020, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV040, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm25LV512, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for Sanyo LF25FW203A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Spansion S25FL008A, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for SST SST25VF016B, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for SST SST25VF032B, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for SST SST25VF040.REMS, 512 KB: Invalid OPCODE 0x90
Probing for SST SST25VF040B, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for SST SST25VF040B.REMS, 512 KB: Invalid OPCODE 0x90
Probing for SST SST25VF080B, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for SST SST28SF040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST29EE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST29LE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST29EE020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST29LE020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39SF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39SF010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39SF020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39SF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39VF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39VF010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39VF020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39VF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST39VF080, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF004C, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for SST SST49LF020, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SST SST49LF020A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SST SST49LF040, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SST SST49LF040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for ST M25P05-A, 64 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P05.RES, 64 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P10.RES, 128 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P40-old, 512 KB: RDID returned 0xc2 0x20 0x14. Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M25P128, 16384 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for ST M29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29F400BT, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29W010B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29W040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M29W512B, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for ST M50FLW040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for ST M50FLW040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible.
Probing for ST M50FW002, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for ST M50FW016, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for ST M50FW040, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for ST M50FW080, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for ST M50LPW116, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W25x10, 128 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x20, 256 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x40, 512 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x80, 1024 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x16, 2048 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x32, 4096 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W25x64, 8192 KB: RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Probing for Winbond W29C011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W29C020C, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W29C040P, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W29EE011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W39V040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for Winbond W39V040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for Winbond W39V040C, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for Winbond W49F002U, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible.
Probing for Winbond W49V002A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible.
Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible.
Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000.
RDID returned 0xc2 0x20 0x14. probe_spi_rdid_generic: id1 0xc2, id2 0x2014
Not unmapping zero size at (nil)
Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000.
Invalid OPCODE 0x90
Not unmapping zero size at (nil)
===
This flash part has status UNTESTED for operations: ERASE
Please email a report to flashrom at flashrom.org if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -rV,
-wV, -EV), and mention which mainboard or programmer you tested.
Thanks for your help!
===
No operations were specified.

From svn at coreboot.org  Wed Apr  7 01:55:17 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 01:55:17 +0200
Subject: [coreboot] [commit] r5360 - trunk/src/southbridge/nvidia/ck804
Message-ID: <E1NzIc1-0001kf-Gl@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 01:55:17 2010
New Revision: 5360
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5360

Log:
fix CK804 boards.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c

Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c	Tue Apr  6 23:50:21 2010	(r5359)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c	Wed Apr  7 01:55:17 2010	(r5360)
@@ -314,7 +314,7 @@
 	return set_ht_link_ck804(4);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
 	set_bios_reset();
 
@@ -323,7 +323,7 @@
 	outb(0x0e, 0x0cf9);
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 	set_bios_reset();
 

Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	Tue Apr  6 23:50:21 2010	(r5359)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	Wed Apr  7 01:55:17 2010	(r5360)
@@ -339,7 +339,7 @@
 	return set_ht_link_ck804(4);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
 	set_bios_reset();
 
@@ -348,7 +348,7 @@
 	outb(0x0e, 0x0cf9);
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 	set_bios_reset();
 



From info at coresystems.de  Wed Apr  7 02:11:25 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 02:11:25 +0200
Subject: [coreboot] build service results for r5360
Message-ID: <E1NzIrd-0006Nn-FA@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5360 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix CK804 boards.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of asus:a8n_e has been fixed
Compilation of msi:ms7135 has been fixed
Compilation of sunw:ultra40 has been fixed
Compilation of tyan:s2891 has been fixed
Compilation of tyan:s2892 has been fixed
Compilation of tyan:s2895 has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Apr  7 02:38:09 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 02:38:09 +0200
Subject: [coreboot] [commit] r5361 - in trunk/src: mainboard/asus/a8n_e
	mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se
	mainboard/hp/dl145_g3 mainboard/msi/ms7135
	mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainb...
Message-ID: <E1NzJHV-0001U5-Uv@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 02:38:09 2010
New Revision: 5361
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5361

Log:
- unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY
- cleanup reset
- some minor warning fixes.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/asus/a8n_e/Kconfig
   trunk/src/mainboard/asus/a8v-e_se/Kconfig
   trunk/src/mainboard/asus/m2v-mx_se/Kconfig
   trunk/src/mainboard/hp/dl145_g3/Kconfig
   trunk/src/mainboard/msi/ms7135/Kconfig
   trunk/src/mainboard/msi/ms9282/get_bus_conf.c
   trunk/src/mainboard/msi/ms9282/mptable.c
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/sunw/ultra40/Kconfig
   trunk/src/mainboard/supermicro/h8dme/Kconfig
   trunk/src/mainboard/supermicro/h8dmr/Kconfig
   trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
   trunk/src/mainboard/tyan/s2850/Kconfig
   trunk/src/mainboard/tyan/s2875/Kconfig
   trunk/src/mainboard/tyan/s2892/Kconfig
   trunk/src/mainboard/tyan/s2895/Kconfig
   trunk/src/northbridge/amd/amdfam10/Kconfig
   trunk/src/northbridge/amd/amdk8/Kconfig
   trunk/src/northbridge/amd/amdk8/reset_test.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h

Modified: trunk/src/mainboard/asus/a8n_e/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/asus/a8n_e/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -44,11 +44,6 @@
 	default 2
 	depends on BOARD_ASUS_A8N_E
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_ASUS_A8N_E
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "A8N-E"

Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/asus/a8v-e_se/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -44,11 +44,6 @@
 	default 1
 	depends on BOARD_ASUS_A8V_E_SE
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_ASUS_A8V_E_SE
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "A8V-E SE"

Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -86,11 +86,6 @@
 	default 0x0
 	depends on BOARD_ASUS_M2V_MX_SE
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_ASUS_M2V_MX_SE
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 1

Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/hp/dl145_g3/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -47,11 +47,6 @@
 	default 2
 	depends on BOARD_HP_DL145_G3
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_HP_DL145_G3
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "ProLiant DL145 G3"

Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/msi/ms7135/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -79,11 +79,6 @@
 	default 2
 	depends on BOARD_MSI_MS7135
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_MSI_MS7135
-
 config IRQ_SLOT_COUNT
 	int
 	default 13

Modified: trunk/src/mainboard/msi/ms9282/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/get_bus_conf.c	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/msi/ms9282/get_bus_conf.c	Wed Apr  7 02:38:09 2010	(r5361)
@@ -68,31 +68,6 @@
 
 static unsigned get_bus_conf_done = 0;
 
-static unsigned get_hcid(unsigned i)
-{
-        unsigned id = 0;
-
-        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
-        unsigned devn = sysconf.hcdn[i] & 0xff;
-
-        device_t dev;
-
-        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
-        switch (dev->device) {
-        case 0x0369: //IO55
-                id = 4;
-                break;
-        }
-
-        // we may need more way to find out hcid: subsystem id? GPIO read ?
-
-        // we need use id for 1. bus num, 2. mptable, 3. acpi table
-
-        return id;
-}
-
 void get_bus_conf(void)
 {
 

Modified: trunk/src/mainboard/msi/ms9282/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/mptable.c	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/msi/ms9282/mptable.c	Wed Apr  7 02:38:09 2010	(r5361)
@@ -38,12 +38,12 @@
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "MSI    ";
-        static const char productid[12] = "MS9282       ";
+        static const char productid[12] = "MS9282      ";
         struct mp_config_table *mc;
-       struct mb_sysconf_t *m;
-       unsigned sbdn;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
 
-       int i,j;
+	int i,j;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -16,6 +16,7 @@
 	select ENABLE_APIC_EXT_ID
 	select AMDMCT
 	select TINY_BOOTBLOCK
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 config MAINBOARD_DIR
 	string
@@ -189,11 +190,6 @@
 	default 1
 	depends on BOARD_MSI_MS9652_FAM10
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default y
-	depends on BOARD_MSI_MS9652_FAM10
-
 config VAR_MTRR_HOLE
 	bool
 	default n

Modified: trunk/src/mainboard/sunw/ultra40/Kconfig
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/sunw/ultra40/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -44,11 +44,6 @@
 	default 2
 	depends on BOARD_SUNW_ULTRA40
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_SUNW_ULTRA40
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "Ultra 40"

Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/supermicro/h8dme/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -51,11 +51,6 @@
 	default 2
 	depends on BOARD_SUPERMICRO_H8DME
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8DME
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "H8DME-2"

Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/supermicro/h8dmr/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -50,11 +50,6 @@
 	default 2
 	depends on BOARD_SUPERMICRO_H8DMR
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8DMR
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "H8DMR-i2"

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -68,11 +68,6 @@
 	default 2
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8DMR_FAM10
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "H8DMR-i2 (Fam10)"

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -69,11 +69,6 @@
 	default 2
 	depends on BOARD_SUPERMICRO_H8QME_FAM10
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_SUPERMICRO_H8QME_FAM10
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "H8QME-2+ (Fam10)"

Modified: trunk/src/mainboard/tyan/s2850/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2850/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/tyan/s2850/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -10,6 +10,7 @@
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 config MAINBOARD_DIR
 	string
@@ -56,11 +57,6 @@
 	default 0x20
 	depends on BOARD_TYAN_S2850
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default y
-	depends on BOARD_TYAN_S2850
-
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 0

Modified: trunk/src/mainboard/tyan/s2875/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2875/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/tyan/s2875/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -11,6 +11,7 @@
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 config MAINBOARD_DIR
 	string
@@ -62,11 +63,6 @@
         default 0x20
         depends on BOARD_TYAN_S2875
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        bool
-        default y
-        depends on BOARD_TYAN_S2875
-
 config SB_HT_CHAIN_ON_BUS0
         int
         default 0

Modified: trunk/src/mainboard/tyan/s2892/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2892/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/tyan/s2892/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -75,11 +75,6 @@
 	default 2
 	depends on BOARD_TYAN_S2892
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_TYAN_S2892
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/mainboard/tyan/s2895/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2895/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/mainboard/tyan/s2895/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -75,11 +75,6 @@
 	default 2
 	depends on BOARD_TYAN_S2895
 
-config SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	bool
-	default n
-	depends on BOARD_TYAN_S2895
-
 config IRQ_SLOT_COUNT
 	int
 	default 11

Modified: trunk/src/northbridge/amd/amdfam10/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/northbridge/amd/amdfam10/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -57,4 +57,9 @@
         default "northbridge/amd/amdfam10/bootblock.c"
 	depends on NORTHBRIDGE_AMD_AMDFAM10
 
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
 source src/northbridge/amd/amdfam10/root_complex/Kconfig

Modified: trunk/src/northbridge/amd/amdk8/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdk8/Kconfig	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/northbridge/amd/amdk8/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
@@ -47,4 +47,9 @@
 	default n
 	depends on NORTHBRIDGE_AMD_AMDK8
 
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AMDK8
+
 source src/northbridge/amd/amdk8/root_complex/Kconfig

Modified: trunk/src/northbridge/amd/amdk8/reset_test.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/reset_test.c	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/northbridge/amd/amdk8/reset_test.c	Wed Apr  7 02:38:09 2010	(r5361)
@@ -7,9 +7,9 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static int cpu_init_detected(unsigned nodeid)
+static inline int cpu_init_detected(unsigned nodeid)
 {
-	unsigned long htic;
+	u32 htic;
 	device_t dev;
 
 	dev = PCI_DEV(0, 0x18 + nodeid, 0);
@@ -18,25 +18,25 @@
 	return !!(htic & HTIC_INIT_Detect);
 }
 
-static int bios_reset_detected(void)
+static inline int bios_reset_detected(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 
 	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
 }
 
-static int cold_reset_detected(void)
+static inline int cold_reset_detected(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static void distinguish_cpu_resets(unsigned nodeid)
+static inline void distinguish_cpu_resets(unsigned nodeid)
 {
-	uint32_t htic;
+	u32 htic;
 	device_t device;
 	device = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(device, HT_INIT_CONTROL);
@@ -46,7 +46,7 @@
 
 static void set_bios_reset(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 	htic &= ~HTIC_BIOSR_Detect;
 	pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
@@ -54,10 +54,10 @@
 
 static unsigned node_link_to_bus(unsigned node, unsigned link)
 {
-	unsigned reg;
+	u8 reg;
 
 	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-		unsigned config_map;
+		u32 config_map;
 		config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
 		if ((config_map & 3) != 3) {
 			continue;
@@ -71,17 +71,16 @@
 	return 0;
 }
 
-static unsigned get_sblk(void)
+static inline unsigned get_sblk(void)
 {
-	uint32_t reg;
+	u32 reg;
 	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
 	reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
 	return ((reg>>8) & 3) ;
 }
 
-static unsigned get_sbbusn(unsigned sblk)
+static inline unsigned get_sbbusn(unsigned sblk)
 {
 	return node_link_to_bus(0, sblk);
 }
 
-

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c	Wed Apr  7 02:38:09 2010	(r5361)
@@ -22,6 +22,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
 	(((BUS) & 0xFFF) << 20) | \

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c	Wed Apr  7 02:38:09 2010	(r5361)
@@ -100,7 +100,6 @@
 
 static void mcp55_sm_read_resources(device_t dev)
 {
-	struct resource *res;
 	unsigned long index;
 
 	/* Get the normal pci resources of this device */
@@ -110,7 +109,6 @@
 		pci_get_resource(dev, index);
 	}
 	compact_resources(dev);
-
 }
 
 static void mcp55_sm_init(device_t dev)

Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h	Wed Apr  7 01:55:17 2010	(r5360)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h	Wed Apr  7 02:38:09 2010	(r5361)
@@ -40,23 +40,6 @@
 	outb(0x80, 0x80);
 }
 
-static int smbus_wait_until_ready(unsigned smbus_io_base)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) {
-			return 0;
-		}
-		outb(val,smbus_io_base + SMBHSTSTAT);
-	} while(--loops);
-	return -2;
-}
-
 static int smbus_wait_until_done(unsigned smbus_io_base)
 {
 	unsigned long loops;



From svn at coreboot.org  Wed Apr  7 03:41:01 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 03:41:01 +0200
Subject: [coreboot] [commit] r5362 - trunk/src/mainboard/via/epia-n
Message-ID: <E1NzKGL-0004yB-HE@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 03:41:01 2010
New Revision: 5362
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5362

Log:
oops... this is a critical issue. Some boards in the tree don't compile with
romcc even though they don't have CAR either. We need to check all boards and
fix those that are broken like this.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/via/epia-n/Kconfig

Modified: trunk/src/mainboard/via/epia-n/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia-n/Kconfig	Wed Apr  7 02:38:09 2010	(r5361)
+++ trunk/src/mainboard/via/epia-n/Kconfig	Wed Apr  7 03:41:01 2010	(r5362)
@@ -11,6 +11,7 @@
 	select EPIA_VT8237R_INIT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
+	select ROMCC
 
 config MAINBOARD_DIR
 	string



From svn at coreboot.org  Wed Apr  7 03:44:06 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 03:44:06 +0200
Subject: [coreboot] [commit] r5363 - in trunk/src: mainboard/msi/ms9185
	mainboard/via/epia-m mainboard/via/epia-n
	northbridge/amd/amdfam10 northbridge/amd/amdk8
	northbridge/via/cn400 northbridge/via/vt8623 northbridge...
Message-ID: <E1NzKJK-0001fk-9m@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 03:44:04 2010
New Revision: 5363
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5363

Log:
"no warnings day"
last round for today. still warnings - help appreciated.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/msi/ms9185/mptable.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/via/epia-m/fadt.c
   trunk/src/mainboard/via/epia-m/mainboard.c
   trunk/src/mainboard/via/epia-n/acpi_tables.c
   trunk/src/mainboard/via/epia-n/fadt.c
   trunk/src/northbridge/amd/amdfam10/setup_resource_map.c
   trunk/src/northbridge/amd/amdk8/incoherent_ht.c
   trunk/src/northbridge/amd/amdk8/raminit_f.c
   trunk/src/northbridge/amd/amdk8/setup_resource_map.c
   trunk/src/northbridge/via/cn400/cn400.h
   trunk/src/northbridge/via/cn400/northbridge.c
   trunk/src/northbridge/via/vt8623/northbridge.c
   trunk/src/northbridge/via/vt8623/raminit.c
   trunk/src/northbridge/via/vx800/vx800.h
   trunk/src/northbridge/via/vx800/vx800_ide.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/src/southbridge/ricoh/rl5c476/rl5c476.c
   trunk/src/southbridge/via/vt8235/vt8235.c
   trunk/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/src/southbridge/via/vt8235/vt8235_usb.c
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c

Modified: trunk/src/mainboard/msi/ms9185/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/mptable.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/msi/ms9185/mptable.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -43,8 +43,8 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[3] = "MSI";
-        static const char productid[6] = "MS9185       ";
+        static const char oem[8] = "MSI     ";
+        static const char productid[12] = "MS9185      ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;
@@ -82,8 +82,7 @@
 
 /*I/O APICs:   APIC ID Version State           Address*/
         {
-                device_t dev = 0;
-               int i;
+		device_t dev = 0;
                struct resource *res;
                for(i=0; i<3; i++) {
                        dev = dev_find_device(0x1166, 0x0235, dev);

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -57,6 +57,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <reset.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -151,7 +152,8 @@
 
        };
 
-       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset;
         unsigned bsp_apicid = 0;

Modified: trunk/src/mainboard/via/epia-m/fadt.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/fadt.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/via/epia-m/fadt.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -37,8 +37,8 @@
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
-	fadt->firmware_ctrl=facs;
-	fadt->dsdt= dsdt;
+	fadt->firmware_ctrl=(u32)facs;
+	fadt->dsdt=(u32)dsdt;
 	fadt->preferred_pm_profile=0;
 	fadt->sci_int=5;
 	fadt->smi_cmd = 0;
@@ -84,9 +84,9 @@
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;

Modified: trunk/src/mainboard/via/epia-m/mainboard.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/mainboard.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/via/epia-m/mainboard.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -7,9 +7,6 @@
 #include "chip.h"
 #include "vgachip.h"
 
-void vga_enable_console();
-
-
 static void vga_fixup(void) {
         // we do this right here because:
         // - all the hardware is working, and some VGA bioses seem to need
@@ -22,8 +19,6 @@
         do_vgabios();
         post_code(0x93);
 	vga_enable_console();
-
-
 }
  
 void write_protect_vgabios(void)

Modified: trunk/src/mainboard/via/epia-n/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/acpi_tables.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/via/epia-n/acpi_tables.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -126,7 +126,6 @@
 	unsigned long current;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
 	acpi_madt_t *madt;
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
@@ -163,8 +162,10 @@
 	dsdt = (acpi_header_t *)current;
 	current += AmlCode.length;
 	memcpy((void *)dsdt, &AmlCode, AmlCode.length);
+#if 0
 	dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
 	dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
+#endif
 	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
 

Modified: trunk/src/mainboard/via/epia-n/fadt.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/fadt.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/mainboard/via/epia-n/fadt.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -39,8 +39,8 @@
 	memcpy(header->asl_compiler_id,ASLC,4);
 	header->asl_compiler_revision=0;
 
-	fadt->firmware_ctrl=facs;
-	fadt->dsdt= dsdt;
+	fadt->firmware_ctrl=(u32)facs;
+	fadt->dsdt= (u32)dsdt;
 	fadt->preferred_pm_profile=0;
 	fadt->sci_int=VT8237R_ACPI_IRQ;
 	fadt->smi_cmd = 0;
@@ -86,9 +86,9 @@
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;

Modified: trunk/src/northbridge/amd/amdfam10/setup_resource_map.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/setup_resource_map.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/amd/amdfam10/setup_resource_map.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -195,6 +195,7 @@
 #endif
 }
 
+#if 0
 static void setup_iob_resource_map(const u32 *register_values, u32 max)
 {
 	u32 i;
@@ -227,5 +228,5 @@
 		outl(reg, where);
 	}
 }
-
+#endif
 

Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -444,7 +444,6 @@
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 	if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
 		uint16_t flags;
-		int i;
 		flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
 		flags &= ~0x1f;
 		flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
@@ -452,6 +451,7 @@
 
 		#if RAMINIT_SYSINFO == 1
 		// Here need to change the dev in the array
+		int i;
 		for(i=0;i<sysinfo->link_pair_num;i++)
 		{
 			struct link_pair_st *link_pair = &sysinfo->link_pair[i];

Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/amd/amdk8/raminit_f.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -33,7 +33,7 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if DEBUG_RAM_SETUP
+#if CONFIG_DEBUG_RAM_SETUP
 #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)

Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/setup_resource_map.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -192,6 +192,7 @@
 #endif
 }
 
+#if 0
 static void setup_iob_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
@@ -267,7 +268,6 @@
 	}
 }
 
-#if 0
 static void setup_mem_resource_map(const unsigned int *register_values, int max)
 {
 	int i;

Modified: trunk/src/northbridge/via/cn400/cn400.h
==============================================================================
--- trunk/src/northbridge/via/cn400/cn400.h	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/cn400/cn400.h	Wed Apr  7 03:44:04 2010	(r5363)
@@ -19,7 +19,8 @@
  */
 
 #ifndef __PRE_RAM__
-static void cn400_noop(void)
+// HACK
+static inline void cn400_noop(device_t dev)
 {
 }
 #endif

Modified: trunk/src/northbridge/via/cn400/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/cn400/northbridge.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/cn400/northbridge.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -238,7 +238,7 @@
 	if (mc_dev) {
 		unsigned long tomk, tolmk;
 		unsigned char rambits;
-		int i, idx;
+		int idx;
 
 		rambits = pci_read_config8(mc_dev, 0x47);
 		tomk = rambits * 32 * 1024;

Modified: trunk/src/northbridge/via/vt8623/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/vt8623/northbridge.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/vt8623/northbridge.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -105,7 +105,7 @@
 static void vga_init(device_t dev)
 {
 //	unsigned long fb;
-	msr_t clocks1,clocks2,instructions,setup;
+	//msr_t clocks1,clocks2,instructions,setup;
 
 	printk(BIOS_DEBUG, "VGA random fixup ...\n");
 	pci_write_config8(dev, 0x04, 0x07);

Modified: trunk/src/northbridge/via/vt8623/raminit.c
==============================================================================
--- trunk/src/northbridge/via/vt8623/raminit.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/vt8623/raminit.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -69,7 +69,7 @@
 {
 	device_t north = (device_t) 0;
 	uint8_t b, c, bank;
-	uint16_t i,j;
+	uint16_t i;
 	unsigned long bank_address;
 
 	print_debug("vt8623 init starting\n");

Modified: trunk/src/northbridge/via/vx800/vx800.h
==============================================================================
--- trunk/src/northbridge/via/vx800/vx800.h	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/vx800/vx800.h	Wed Apr  7 03:44:04 2010	(r5363)
@@ -21,7 +21,7 @@
 #define  VX800_H 1
 
 #ifndef __PRE_RAM__
-static void vx800_noop()
+static inline void vx800_noop(device_t dev)
 {
 }
 #endif

Modified: trunk/src/northbridge/via/vx800/vx800_ide.c
==============================================================================
--- trunk/src/northbridge/via/vx800/vx800_ide.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/northbridge/via/vx800/vx800_ide.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -166,13 +166,10 @@
 
 static void ide_init(struct device *dev)
 {
-	uint8_t enables, Rx89, RxC0;
 	u8 i, data;
-	struct ATA_REG_INIT_TABLE *pEntry;
 	printk(BIOS_INFO, "ide_init\n");
 
-#if 1
-	/*these 3 lines help to keep interl back door for DID VID SUBID untouched */
+	/* these 3 lines help to keep interl back door for DID VID SUBID untouched */
 	u16 data16_1, data16_2;
 	data16_1 = pci_read_config16(dev, 0xba);
 	data16_2 = pci_read_config16(dev, 0xbe);
@@ -189,7 +186,7 @@
 	//these 2 lines help to keep interl back door for DID VID SUBID untouched
 	pci_write_config16(dev, 0xba, data16_1);
 	pci_write_config16(dev, 0xbe, data16_2);
-#endif
+
 	/* Force interrupts to use compat mode. */
 	pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
 	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -12,8 +12,7 @@
 {
 	device_t sb_pci_main_dev;
 	device_t bus_dev;
-	unsigned index;
-	unsigned reg_old, reg;
+	// unsigned index;
 
 	/* See if we are on the behind the pcix bridge */
 	bus_dev = dev->bus->dev;
@@ -23,18 +22,17 @@
 		unsigned devfn;
 		devfn = bus_dev->path.pci.devfn + (1 << 3);
 		sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
-//		index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
+		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
 	} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
                 (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
         {
                 unsigned devfn;
                 devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
                 sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
-//                index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
+		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
         }
 	else { // same bus
 		unsigned devfn;
-		uint32_t id;
 		devfn = (dev->path.pci.devfn) & ~7;
 		if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { 
 			if(dev->device == 0x0036) //PCI-X Bridge
@@ -43,7 +41,7 @@
 			{ devfn -= (1<<3); }
 		}
 		sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn);
-//		index = dev->path.pci.devfn & 7;
+		// index = dev->path.pci.devfn & 7;
 	}
 	if (!sb_pci_main_dev) {
 		return;
@@ -51,6 +49,7 @@
 
 	// get index now
 #if 0
+	unsigned reg_old, reg;
 	if (index < 16) {
 		reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48);
 		reg &= ~(1 << index);

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -6,8 +6,6 @@
 static void bcm5785_enable_rom(void)
 {
         unsigned char byte;
-        uint32_t dword;
-        uint16_t word;
         device_t addr;
 
         /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
@@ -109,7 +107,7 @@
 }
 
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         bcm5785_enable_wdt_port_cf9();
 
@@ -120,7 +118,7 @@
         outb(0x0e, 0x0cf9);
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
         bcm5785_enable_wdt_port_cf9();
 
@@ -164,7 +162,6 @@
 static void bcm5785_early_setup(void)
 {
         uint8_t byte;
-        uint16_t word;
         uint32_t dword;
         device_t dev;
 
@@ -181,13 +178,12 @@
         byte |= (1<<0); // SATA enable
         pci_write_config8(dev, 0x84, byte);
 
-// wdt and cf9 for later in coreboot_ram to call hard_reset
+// WDT and cf9 for later in coreboot_ram to call hard_reset
         bcm5785_enable_wdt_port_cf9();
 
         bcm5785_enable_msg();
 
 
-#if 1
 // IDE related
 	//F0
         byte = pci_read_config8(dev, 0x4e);
@@ -207,9 +203,8 @@
         byte = pci_read_config8(dev, 0x49);
         byte |= 1; // enable second channel
         pci_write_config8(dev, 0x49, byte);
-#endif
 
-//F2
+	//F2
         dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
         byte = pci_read_config8(dev, 0x40);
@@ -218,7 +213,6 @@
 
         pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
 
-#if 1
 // USB related
         pci_write_config8(dev, 0x90, 0x40);
         pci_write_config8(dev, 0x92, 0x06);
@@ -227,5 +221,4 @@
         pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
         pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
         pci_write_config8(dev, 0xb4, 0x40);
-#endif
 }

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -12,9 +12,6 @@
 
 static void bcm5785_ide_read_resources(device_t dev)
 {
-        struct resource *res;
-        unsigned long index;
-
         /* Get the normal pci resources of this device */
         pci_dev_read_resources(dev);
 
@@ -26,9 +23,6 @@
 
 static void ide_init(struct device *dev)
 {
-	uint16_t word;
-
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -36,6 +30,7 @@
         pci_write_config32(dev, 0x40,
                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
+
 static struct pci_operations lops_pci = {
         .set_subsystem = lpci_set_subsystem,
 };

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -70,7 +70,6 @@
         unsigned link; 
 	uint32_t reg;
 	int i;
-	int var_num = 0;
 	
 	reg = pci_read_config8(dev, 0x44);
 

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -4,6 +4,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
         (((BUS) & 0xFFF) << 20) | \

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -12,17 +12,13 @@
 #include <arch/io.h>
 #include "bcm5785.h"
 
-
 static void sata_init(struct device *dev)
 {
-
 	uint8_t byte;
 
-        uint8_t *base;
-	uint8_t *mmio;
+	u32 mmio;
         struct resource *res;
-        unsigned int mmio_base;
-        volatile unsigned int *mmio_reg;
+        u32 mmio_base;
 	int i;
 
 	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
@@ -31,27 +27,24 @@
         	pci_write_config8(dev, 0x78, byte);
 
 	        res = find_resource(dev, 0x24);
-	        base = res->base;
-
-                mmio_base = base;
+                mmio_base = res->base;
                 mmio_base &= 0xfffffffc;
-                mmio_reg = (unsigned int *)( mmio_base + 0x10f0 );
-                * mmio_reg = 0x40000001;
-                mmio_reg = ( unsigned int *)( mmio_base + 0x8c );
-                * mmio_reg = 0x00ff2007;
+
+		write32(mmio_base + 0x10f0, 0x40000001);
+		write32(mmio_base + 0x8c, 0x00ff2007);
                 mdelay( 10 );
-                * mmio_reg = 0x78592009;
+		write32(mmio_base + 0x8c, 0x78592009);
                 mdelay( 10 );
-                * mmio_reg = 0x00082004;
+		write32(mmio_base + 0x8c, 0x00082004);
                 mdelay( 10 );
-                * mmio_reg = 0x00002004;
+		write32(mmio_base + 0x8c, 0x00002004);
                 mdelay( 10 );
 
 		//init PHY
 
 		printk(BIOS_DEBUG, "init PHY...\n");
 		for(i=0; i<4; i++) {
-			mmio = base + 0x100 * i; 
+			mmio = res->base + 0x100 * i; 
 			byte = read8(mmio + 0x40);
 			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
 			if(byte & 0x4) {// bit 2 is set
@@ -62,10 +55,7 @@
 	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
 			}
 		}
-		
 	}
-
-
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)

Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -25,8 +25,6 @@
 	uint8_t byte_old;
 	int nmi_option;
 
-	uint32_t dword;
-
 	/* Set up NMI on errors */
 	byte = inb(0x70); // RTC70
 	byte_old = byte;
@@ -47,7 +45,6 @@
 static void bcm5785_sb_read_resources(device_t dev)
 {
 	struct resource *res;
-	unsigned long index;
 
 	/* Get the normal pci resources of this device */
 	pci_dev_read_resources(dev); 		
@@ -64,6 +61,7 @@
         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 }
+
 static int lsmbus_recv_byte(device_t dev)
 {
         unsigned device;

Modified: trunk/src/southbridge/ricoh/rl5c476/rl5c476.c
==============================================================================
--- trunk/src/southbridge/ricoh/rl5c476/rl5c476.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/ricoh/rl5c476/rl5c476.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -162,7 +162,7 @@
 	*cptr = 0x41;
 }
 
-void rl5c476_read_resources(device_t dev)
+static void rl5c476_read_resources(device_t dev)
 {
 
 	struct resource *resource;
@@ -181,7 +181,7 @@
 	cardbus_read_resources(dev);
 }
 
-void rl5c476_set_resources(device_t dev)
+static void rl5c476_set_resources(device_t dev)
 {
 	struct resource *resource;
 	printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
@@ -212,12 +212,10 @@
 	.device = PCI_DEVICE_ID_RICOH_RL5C476,
 };
 
-void southbridge_init(device_t dev)
+static void southbridge_init(device_t dev)
 {
-
 	struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info;
 	enable_cf_boot = conf->enable_cf;
-
 }
 
 struct chip_operations southbridge_ricoh_rl5c476_ops = {

Modified: trunk/src/southbridge/via/vt8235/vt8235.c
==============================================================================
--- trunk/src/southbridge/via/vt8235/vt8235.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/via/vt8235/vt8235.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -10,7 +10,6 @@
 /*
  * Base VT8235.
  */
-static int enabled = 0;
 
 void hard_reset(void) 
 {
@@ -53,11 +52,9 @@
 
 static void vt8235_enable(struct device *dev)
 {
-	struct southbridge_via_vt8235_config *conf = dev->chip_info;
 	unsigned char regval;
 	unsigned short vendor,model;
 
-
 	vendor = pci_read_config16(dev,0);
 	model = pci_read_config16(dev,0x2);
 
@@ -72,7 +69,6 @@
 
 	printk(BIOS_DEBUG, "Initialising Devices\n");
 
-
 	setup_i8259();   // make sure interupt controller is configured before keyboard init 
 
 	/* enable RTC and ethernet */
@@ -87,8 +83,6 @@
    	regval = pci_read_config8(dev, 0x50);
 	regval &= ~(0x36);
 	pci_write_config8(dev, 0x50, regval);
-
-
 }
 
 struct chip_operations southbridge_via_vt8235_ops = {

Modified: trunk/src/southbridge/via/vt8235/vt8235_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8235/vt8235_lpc.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/via/vt8235/vt8235_lpc.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -105,9 +105,8 @@
  * can't figure out how to do !!!!
  */ 
 
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
 {
-
 	// Set gen config 0
 	pci_write_config8(dev, 0x80, 0x20);
 
@@ -216,7 +215,7 @@
 
 /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
    device has a resource to set - so set a dummy one */
-void vt8235_read_resources(device_t dev)
+static void vt8235_read_resources(device_t dev)
 {
 	struct resource *res;
 
@@ -234,21 +233,20 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-void vt8235_set_resources(device_t dev)
+static void vt8235_set_resources(device_t dev)
 {
-	struct resource *resource;
+	//struct resource *resource;
 	//resource = find_resource(dev,1);
 	//resource->flags |= IORESOURCE_STORED;
 	pci_dev_set_resources(dev);
 }
 
-void vt8235_enable_resources(device_t dev)
+static void vt8235_enable_resources(device_t dev)
 {
 	/* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
            however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
-
 }
 	
 static void southbridge_init(struct device *dev)

Modified: trunk/src/southbridge/via/vt8235/vt8235_usb.c
==============================================================================
--- trunk/src/southbridge/via/vt8235/vt8235_usb.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/via/vt8235/vt8235_usb.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -27,7 +27,6 @@
 	 */
 }
 
-/*
 static struct device_operations usb_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
@@ -42,4 +41,4 @@
 	.vendor = PCI_VENDOR_ID_VIA,
 	.device = PCI_DEVICE_ID_VIA_82C586_2,
 };
-*/
+

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Wed Apr  7 03:41:01 2010	(r5362)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c	Wed Apr  7 03:44:04 2010	(r5363)
@@ -65,7 +65,6 @@
 {
 #if CONFIG_EPIA_VT8237R_INIT
 	device_t pdev;
-	u8 reg;
 #endif
 
 	/* PCI PNP Interrupt Routing INTE/F - disable */



From kevin at koconnor.net  Wed Apr  7 03:01:08 2010
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 6 Apr 2010 21:01:08 -0400
Subject: [coreboot] memset called to somewhere high on the stack
 (uncached)
In-Reply-To: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
References: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
Message-ID: <20100407010108.GA6328@morn.localdomain>

On Tue, Apr 06, 2010 at 04:21:57PM -0600, Myles Watson wrote:
> I'm seeing code reads to memset() in coreboot_ram interleaved with byte
> writes to somewhere high on the stack (_estack -0x1fC).  This is a k8.
> 
> I can't find the place during the RAM stage when we are calling memset with
> caches disabled.  Does this ring a bell for anyone?

Probably not related, but I found the code at
src/arch/i386/init/crt0.S.lb:
        movl    %ebp, %esi
        /* FIXME: look for a proper place for the stack */
        movl    $0x4000000, %esp
        movl    %esp, %ebp
        pushl %esi
        pushl $str_coreboot_ram_name
        call cbfs_and_run_core

to be problematic on my epia-cn back when I was running timing tests.
The stack was set to 0x4000000, but that memory wasn't cached.  It
caused a really long delay - doubly so when lzma compression was used.

-Kevin



From svn at coreboot.org  Wed Apr  7 04:06:54 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 04:06:54 +0200
Subject: [coreboot] [commit] r5364 - in trunk/src: drivers/generic/debug
	mainboard/msi/ms7135 mainboard/tyan/s2735 mainboard/via/epia
	mainboard/via/epia-m mainboard/via/epia-m700
	mainboard/via/epia-n southbridge/intel...
Message-ID: <E1NzKfO-0003bI-9U@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 04:06:53 2010
New Revision: 5364
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5364

Log:
switch some ROMCC boards back to ROMCC.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/drivers/generic/debug/debug_dev.c
   trunk/src/mainboard/msi/ms7135/mptable.c
   trunk/src/mainboard/tyan/s2735/Kconfig
   trunk/src/mainboard/via/epia-m/Kconfig
   trunk/src/mainboard/via/epia-m700/Kconfig
   trunk/src/mainboard/via/epia-n/Kconfig
   trunk/src/mainboard/via/epia/Kconfig
   trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/src/southbridge/intel/esb6300/esb6300_ide.c
   trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
   trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
   trunk/src/superio/smsc/lpc47m10x/superio.c

Modified: trunk/src/drivers/generic/debug/debug_dev.c
==============================================================================
--- trunk/src/drivers/generic/debug/debug_dev.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/drivers/generic/debug/debug_dev.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -59,7 +59,7 @@
 	}
 }
 
-static void print_cpuid()
+static void print_cpuid(void)
 {
 	msr_t msr;
 	unsigned index;

Modified: trunk/src/mainboard/msi/ms7135/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/mptable.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/msi/ms7135/mptable.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -47,7 +47,6 @@
 	unsigned sbdn;
 
 	int bus_num;
-	int i;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));

Modified: trunk/src/mainboard/tyan/s2735/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2735/Kconfig	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/tyan/s2735/Kconfig	Wed Apr  7 04:06:53 2010	(r5364)
@@ -15,6 +15,7 @@
 	select USE_DCACHE_RAM
 	select USE_WATCHDOG_ON_BOOT
 	select BOARD_ROMSIZE_KB_512
+	select USE_PRINTK_IN_CAR
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/via/epia-m/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia-m/Kconfig	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/via/epia-m/Kconfig	Wed Apr  7 04:06:53 2010	(r5364)
@@ -10,22 +10,13 @@
 	select HAVE_PIRQ_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_256
+	select ROMCC
 
 config MAINBOARD_DIR
 	string
 	default via/epia-m
 	depends on BOARD_VIA_EPIA_M
 
-#config DCACHE_RAM_BASE
-#	hex
-#	default 0xffef0000
-#	depends on BOARD_VIA_EPIA_M
-
-#config DCACHE_RAM_SIZE
-#	hex
-#	default 0x8000
-#	depends on BOARD_VIA_EPIA_M
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "EPIA-M"

Modified: trunk/src/mainboard/via/epia-m700/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia-m700/Kconfig	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/via/epia-m700/Kconfig	Wed Apr  7 04:06:53 2010	(r5364)
@@ -7,6 +7,7 @@
 	select BOARD_HAS_FADT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
+	select USE_PRINTK_IN_CAR
 
 config MAINBOARD_DIR
 	string

Modified: trunk/src/mainboard/via/epia-n/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia-n/Kconfig	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/via/epia-n/Kconfig	Wed Apr  7 04:06:53 2010	(r5364)
@@ -18,16 +18,6 @@
 	default via/epia-n
 	depends on BOARD_VIA_EPIA_N
 
-#config DCACHE_RAM_BASE
-#	hex
-#	default 0xffef0000
-#	depends on BOARD_VIA_EPIA_N
-#
-#config DCACHE_RAM_SIZE
-#	hex
-#	default 0x8000
-#	depends on BOARD_VIA_EPIA_N
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "EPIA-N"

Modified: trunk/src/mainboard/via/epia/Kconfig
==============================================================================
--- trunk/src/mainboard/via/epia/Kconfig	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/mainboard/via/epia/Kconfig	Wed Apr  7 04:06:53 2010	(r5364)
@@ -7,22 +7,13 @@
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
+	select ROMCC
 
 config MAINBOARD_DIR
 	string
 	default via/epia
 	depends on BOARD_VIA_EPIA
 
-#config DCACHE_RAM_BASE
-#	hex
-#	default 0xffef0000
-#	depends on BOARD_VIA_EPIA
-#
-#config DCACHE_RAM_SIZE
-#	hex
-#	default 0x8000
-#	depends on BOARD_VIA_EPIA
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "EPIA"

Modified: trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -7,9 +7,6 @@
 
 static void bridge1c_init(struct device *dev)
 {
-
-	uint16_t word;
-
 	/* configuration */
 	pci_write_config8(dev, 0x1b, 0x30);
 //	pci_write_config8(dev, 0x3e, 0x07);
@@ -31,7 +28,6 @@
 
 	/* multi transaction timer */
 	pci_write_config8(dev, 0x42, 0x08);
-
 }
 
 static struct device_operations pci_ops  = {

Modified: trunk/src/southbridge/intel/esb6300/esb6300_ide.c
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_ide.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/intel/esb6300/esb6300_ide.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -9,7 +9,6 @@
 {
 
 	/* Enable ide devices so the linux ide driver will work */
-	uint16_t word;
 
 	/* Enable IDE devices */
         pci_write_config16(dev, 0x40, 0x0a307);
@@ -19,6 +18,7 @@
         pci_write_config16(dev, 0x54, 0x5055);
  
 #if 0
+	uint16_t word;
 	word = pci_read_config16(dev, 0x40);
 	word |= (1 << 15);
 	pci_write_config16(dev, 0x40, word);

Modified: trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_lpc.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/intel/esb6300/esb6300_lpc.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -51,13 +51,13 @@
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_use_sel, gpio_use_sel2;
-	int i;
 
 //	gpio_use_sel  = 0x1B003100;
 //	gpio_use_sel2 = 0x03000000;
 	gpio_use_sel  = 0x1BBC31C0;
 	gpio_use_sel2 = 0x03000FE1;
 #if 0
+	int i;
 	for(i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) {
@@ -84,13 +84,13 @@
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_io_sel, gpio_io_sel2;
-	int i;
 
 //	gpio_io_sel  = 0x0000ffff;
 //	gpio_io_sel2 = 0x00000000;
 	gpio_io_sel  = 0x1900ffff;
 	gpio_io_sel2 = 0x00000fe1;
 #if 0
+	int i;
 	for(i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
@@ -118,7 +118,6 @@
 {
 	uint32_t gpio_lvl, gpio_lvl2;
 	uint32_t gpio_blink;
-	int i;
 
 //	gpio_lvl   = 0x1b3f0000;
 //	gpio_blink = 0x00040000;
@@ -127,6 +126,7 @@
 	gpio_blink = 0x00000000;
 	gpio_lvl2  = 0x00000fff;
 #if 0
+	int i;
 	for(i = 0; i < 64; i++) {
 		int val, blink;
 		switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) {
@@ -157,10 +157,10 @@
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_inv;
-	int i;
 
 	gpio_inv   = 0x00003100;
 #if 0
+	int i;
 	for(i = 0; i < 32; i++) {
 		int val;
 		switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {

Modified: trunk/src/southbridge/intel/esb6300/esb6300_sata.c
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_sata.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/intel/esb6300/esb6300_sata.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -7,9 +7,7 @@
 
 static void sata_init(struct device *dev)
 {
-
 	/* Enable sata devices so the linux sata driver will work */
-	uint16_t word;
 
 	/* Enable SATA devices */
 

Modified: trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
==============================================================================
--- trunk/src/southbridge/via/vt8235/vt8235_early_serial.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/via/vt8235/vt8235_early_serial.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -38,9 +38,6 @@
 
 static void enable_vt8235_serial(void) 
 {
-	unsigned long x;
-	uint8_t c;
-	device_t dev;
 	// turn on pnp
 	vt8235_writepnpaddr(0x87);
 	vt8235_writepnpaddr(0x87);

Modified: trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -85,7 +85,6 @@
 	unsigned long loops;
 	loops = SMBUS_TIMEOUT;
 	do {
-		unsigned char val;
 		smbus_delay();
 		c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 		while((c & 1) == 1) {
@@ -121,7 +120,6 @@
 	unsigned char byte;
 	loops = SMBUS_TIMEOUT;
 	do {
-		unsigned char val;
 		smbus_delay();
 		
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);

Modified: trunk/src/superio/smsc/lpc47m10x/superio.c
==============================================================================
--- trunk/src/superio/smsc/lpc47m10x/superio.c	Wed Apr  7 03:44:04 2010	(r5363)
+++ trunk/src/superio/smsc/lpc47m10x/superio.c	Wed Apr  7 04:06:53 2010	(r5364)
@@ -44,7 +44,7 @@
 
 static void pnp_enter_conf_state(device_t dev);
 static void pnp_exit_conf_state(device_t dev);
-static void dump_pnp_device(device_t dev);
+//static void dump_pnp_device(device_t dev);
 
 struct chip_operations superio_smsc_lpc47m10x_ops = {
 	CHIP_NAME("SMSC LPC47M10x Super I/O")



From svn at coreboot.org  Wed Apr  7 04:09:54 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 04:09:54 +0200
Subject: [coreboot] [commit] r5365 - trunk/src/mainboard/asrock/939a785gmh
Message-ID: <E1NzKiI-0000KW-MT@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 04:09:54 2010
New Revision: 5365
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5365

Log:
no duplicate names in cmos.layout.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/asrock/939a785gmh/cmos.layout

Modified: trunk/src/mainboard/asrock/939a785gmh/cmos.layout
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/cmos.layout	Wed Apr  7 04:06:53 2010	(r5364)
+++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout	Wed Apr  7 04:09:54 2010	(r5365)
@@ -67,7 +67,7 @@
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
+1000        24       r       0        amd_reserved
 
 
 



From info at coresystems.de  Wed Apr  7 04:20:52 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 04:20:52 +0200
Subject: [coreboot] build service results for r5363
Message-ID: <E1NzKsu-00020b-TC@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5363 to
the coreboot repository. This caused the following 
changes:

Change Log:
"no warnings day"
last round for today. still warnings - help appreciated.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia-m700 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5363&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Apr  7 04:30:57 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 04:30:57 +0200
Subject: [coreboot] [commit] r5366 - in trunk/src:
	mainboard/artecgroup/dbe61 mainboard/intel/eagleheights
	mainboard/intel/xe7501devkit northbridge/via/vx800
	southbridge/intel/i82801cx superio/smsc/lpc47b272
Message-ID: <E1NzL2f-0001Lt-Vw@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 04:30:57 2010
New Revision: 5366
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5366

Log:
fix epia-m700 compilation, and remove more warnings.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/artecgroup/dbe61/mainboard.c
   trunk/src/mainboard/intel/eagleheights/acpi_tables.c
   trunk/src/mainboard/intel/eagleheights/fadt.c
   trunk/src/mainboard/intel/eagleheights/mainboard.c
   trunk/src/mainboard/intel/eagleheights/mptable.c
   trunk/src/mainboard/intel/xe7501devkit/mptable.c
   trunk/src/northbridge/via/vx800/vx800.h
   trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
   trunk/src/superio/smsc/lpc47b272/superio.c

Modified: trunk/src/mainboard/artecgroup/dbe61/mainboard.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/mainboard.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/artecgroup/dbe61/mainboard.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -28,7 +28,7 @@
 #include "../../../southbridge/amd/cs5536/cs5536.h"
 #include "chip.h"
 
-static void init_gpio()
+static void init_gpio(void)
 {
 	msr_t msr;
 	printk(BIOS_DEBUG, "Checking GPIO module...\n");

Modified: trunk/src/mainboard/intel/eagleheights/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/acpi_tables.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/intel/eagleheights/acpi_tables.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -91,7 +91,6 @@
 {
 	unsigned int irq_start = 0;
 	device_t dev = 0;
-	struct resource* res = NULL;
 	unsigned char bus_isa;
 
 	/* Local Apic */
@@ -141,7 +140,6 @@
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
-	int i;
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
 	acpi_hpet_t *hpet;

Modified: trunk/src/mainboard/intel/eagleheights/fadt.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/fadt.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/intel/eagleheights/fadt.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -115,9 +115,9 @@
 	fadt->res3 = 0;
 	fadt->res4 = 0;
 	fadt->res5 = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;

Modified: trunk/src/mainboard/intel/eagleheights/mainboard.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/mainboard.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/intel/eagleheights/mainboard.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -21,10 +21,13 @@
 
 
 #include <device/device.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
 #include "chip.h"
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
+	return 0;
 }
 
 struct chip_operations mainboard_ops = {

Modified: trunk/src/mainboard/intel/eagleheights/mptable.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/mptable.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/intel/eagleheights/mptable.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -75,7 +75,7 @@
 	dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
 	res = find_resource(dev, RCBA);
 	if (!res) {
-	  return;
+	  return NULL;
 	}
 	rcba = res->base;
 

Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/mptable.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/mainboard/intel/xe7501devkit/mptable.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -69,7 +69,7 @@
 	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
 }
 
-void xe7501devkit_register_interrupts(struct mp_config_table *mc)
+static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 {
 	// Chipset PCI bus
 	//					 Type		Trigger | Polarity							Bus ID				IRQ					APIC ID					PIN#

Modified: trunk/src/northbridge/via/vx800/vx800.h
==============================================================================
--- trunk/src/northbridge/via/vx800/vx800.h	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/northbridge/via/vx800/vx800.h	Wed Apr  7 04:30:57 2010	(r5366)
@@ -21,6 +21,7 @@
 #define  VX800_H 1
 
 #ifndef __PRE_RAM__
+#include <device/device.h>
 static inline void vx800_noop(device_t dev)
 {
 }

Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
==============================================================================
--- trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -23,7 +23,7 @@
 #define MAINBOARD_POWER_ON  1
 
 
-void i82801cx_enable_ioapic( struct device *dev) 
+static void i82801cx_enable_ioapic( struct device *dev) 
 {
 	uint32_t dword;
     volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
@@ -54,7 +54,7 @@
 }
 
 // This is how interrupts are received from the Super I/O chip
-void i82801cx_enable_serial_irqs( struct device *dev)
+static void i82801cx_enable_serial_irqs( struct device *dev)
 {
 	// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
@@ -69,7 +69,7 @@
 // Return Value:	None
 // Description: 	Route all DMA channels to either PCI or LPC.
 //
-void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) 
+static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) 
 {
     uint16_t dmaConfig;
     int channelIndex;
@@ -84,7 +84,7 @@
     pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
 }
 
-void i82801cx_rtc_init(struct device *dev)
+static void i82801cx_rtc_init(struct device *dev)
 {
     uint32_t dword;
     int rtc_failed;
@@ -116,7 +116,7 @@
 }
 
 
-void i82801cx_1f0_misc(struct device *dev)
+static void i82801cx_1f0_misc(struct device *dev)
 {
 	// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
     pci_write_config16(dev, PCI_COMMAND, 0x014f);

Modified: trunk/src/superio/smsc/lpc47b272/superio.c
==============================================================================
--- trunk/src/superio/smsc/lpc47b272/superio.c	Wed Apr  7 04:09:54 2010	(r5365)
+++ trunk/src/superio/smsc/lpc47b272/superio.c	Wed Apr  7 04:30:57 2010	(r5366)
@@ -45,7 +45,7 @@
 
 static void pnp_enter_conf_state(device_t dev);
 static void pnp_exit_conf_state(device_t dev);
-static void dump_pnp_device(device_t dev);
+//static void dump_pnp_device(device_t dev);
 
 struct chip_operations superio_smsc_lpc47b272_ops = {
 	CHIP_NAME("SMSC LPC47B272 Super I/O")



From stepan at coresystems.de  Wed Apr  7 04:38:10 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Wed, 07 Apr 2010 04:38:10 +0200
Subject: [coreboot] Need confirmation if HP nx6310 will work with
	coreboot
In-Reply-To: <20100406230535.171610@gmx.net>
References: <20100406230535.171610@gmx.net>
Message-ID: <4BBBF012.3010708@coresystems.de>

On 4/7/10 1:05 AM, secretocean at gmx.de wrote:
> Hi,
>
> I've got an HP nx6310 notebook with Linux as operating system and I'm thinking of trying coreboot to get rid of the non-free HP BIOS.
> Though I'm quite confident that the chipset is supported, it'll be nice if someone would confirm that and perhaps give further instructions on how to use coreboot with my mainboard.
>
> Notebook: HP nx6310 EY366EA#ABD
> no extensions at all, except a PCMCIA WLAN card with Atheros chipset
> BIOS version: F.0E
> CPU: Intel Celeron M 1,46GHz
> RAM: 1GB (512MB by default)
> Graphics card: on board, Intel GMA 945
> Sound card: on board, Intel HDA ... (don't know the exact model)
>
> Outputs of lspci -tvnn, superiotool -dV and flashrom -V: see text files
>
> Hopefully someone can help. I'd love to help making coreboot better but without shooting my mainboard.
Hi,

coreboot might work on this machine with reasonable effort. You will
however need to get some SPI flashing hardware, and you should be
familiar with a soldering iron in order to solder a SPI socket / header
to your board or some wires to your SPI flash.

An issue might be that there does not seem to be a serial console. You
might need a net20dc USB debug device.

Stefan




From info at coresystems.de  Wed Apr  7 04:44:22 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 04:44:22 +0200
Subject: [coreboot] build service results for r5364
Message-ID: <E1NzLFe-0006KZ-Lx@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5364 to
the coreboot repository. This caused the following 
changes:

Change Log:
switch some ROMCC boards back to ROMCC.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5364&device=epia&vendor=via&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5364&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Apr  7 05:06:53 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 05:06:53 +0200
Subject: [coreboot] build service results for r5365
Message-ID: <E1NzLbR-0002Do-Po@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5365 to
the coreboot repository. This caused the following 
changes:

Change Log:
no duplicate names in cmos.layout.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5365&device=epia&vendor=via&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5365&device=epia-m700&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Apr  7 05:11:29 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 05:11:29 +0200
Subject: [coreboot] [commit] r5367 -
	trunk/src/mainboard/digitallogic/msm586seg
Message-ID: <E1NzLft-0003aw-3Q@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 05:11:28 2010
New Revision: 5367
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5367

Log:
drop the use of function pointers from romcc code.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/digitallogic/msm586seg/romstage.c

Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Wed Apr  7 04:30:57 2010	(r5366)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Wed Apr  7 05:11:28 2010	(r5367)
@@ -40,8 +40,6 @@
 
 #include "cpu/amd/sc520/raminit.c"
 
-typedef void (*lj)(void);
-
 struct mem_controller {
 	int i;
 };



From info at coresystems.de  Wed Apr  7 05:28:36 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 05:28:36 +0200
Subject: [coreboot] build service results for r5366
Message-ID: <E1NzLwS-0008IT-8k@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5366 to
the coreboot repository. This caused the following 
changes:

Change Log:
fix epia-m700 compilation, and remove more warnings.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5366&device=epia&vendor=via&num=2
Compilation of via:epia-m700 has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Wed Apr  7 05:40:38 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 05:40:38 +0200
Subject: [coreboot] [commit] r5368 - in trunk/src: . cpu/x86/mtrr
	mainboard/via/epia mainboard/via/epia-m
	northbridge/via/vt8601 southbridge/via/vt8231
Message-ID: <E1NzM86-0008Mw-Rf@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 05:40:37 2010
New Revision: 5368
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5368

Log:
clean up age old via epia target.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/Kconfig
   trunk/src/cpu/x86/mtrr/earlymtrr.c
   trunk/src/mainboard/via/epia-m/romstage.c
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/northbridge/via/vt8601/raminit.c
   trunk/src/southbridge/via/vt8231/vt8231.c
   trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
   trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
   trunk/src/southbridge/via/vt8231/vt8231_lpc.c

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/Kconfig	Wed Apr  7 05:40:37 2010	(r5368)
@@ -622,7 +622,8 @@
 		 || NORTHBRIDGE_VIA_VX800 \
 		 || NORTHBRIDGE_VIA_CX700 \
 		 || NORTHBRIDGE_AMD_AMDK8 \
-		 || NORTHBRIDGE_AMD_AMDFAM10)
+		 || NORTHBRIDGE_AMD_AMDFAM10 \
+		 || SOUTHBRIDGE_VIA_VT8231)
 	help
 	  This option enables additional SMBus (and SPD) debug messages.
 

Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==============================================================================
--- trunk/src/cpu/x86/mtrr/earlymtrr.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -53,7 +53,7 @@
 }
 #endif
 
-static void cache_lbmem(int type)
+static inline void cache_lbmem(int type)
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
@@ -118,7 +118,7 @@
 	enable_cache();
 }
 
-static int early_mtrr_init_detected(void)
+static inline int early_mtrr_init_detected(void)
 {
 	msr_t msr;
 	/* See if MTRR's are enabled.

Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/mainboard/via/epia-m/romstage.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -78,7 +78,6 @@
 
 static void main(unsigned long bist)
 {
-	unsigned long x;
 	device_t dev;
 
 	/*

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/mainboard/via/epia/romstage.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -13,7 +13,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "lib/debug.c"
 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
 #include "southbridge/via/vt8231/vt8231_early_serial.c"
@@ -76,10 +75,8 @@
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	unsigned long x;
-	
 	if (bist == 0) {
 		early_mtrr_init();
 	}

Modified: trunk/src/northbridge/via/vt8601/raminit.c
==============================================================================
--- trunk/src/northbridge/via/vt8601/raminit.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/northbridge/via/vt8601/raminit.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -47,7 +47,7 @@
 #define DIMM_CL2 0
 #endif
 
-void dimms_read(unsigned long x)
+static void dimms_read(unsigned long x)
 {
 	uint8_t c;
 	unsigned long eax;
@@ -59,7 +59,7 @@
 	}
 }
 
-void dimms_write(int x)
+static void dimms_write(int x)
 {
 	uint8_t c;
 	unsigned long eax = x;
@@ -69,7 +69,8 @@
 	}
 }
 
-void dumpnorth(device_t north)
+#ifdef CONFIG_DEBUG_RAM_SETUP
+static void dumpnorth(device_t north)
 {
 	unsigned int r, c;
 	for (r = 0;; r += 16) {
@@ -84,11 +85,11 @@
 			break;
 	}
 }
+#endif
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	device_t north = (device_t) PCI_DEV(0, 0, 0);
-	uint8_t c, r;
 
 	print_err("vt8601 init starting\n");
 	print_debug_hex32(north);
@@ -175,7 +176,7 @@
 	 * module. This is just a very early first cut at sizing.
 	 */
 	/* we may run out of registers ... */
-	unsigned int banks, rows, cols, reg;
+	unsigned int banks, rows, cols;
 	unsigned int value = 0;
 	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
@@ -213,9 +214,9 @@
 	}
 	print_info("\n");
 	return value;
-
 }
 
+#if 0
 static int spd_num_chips(unsigned char slot)
 {
 	unsigned int module = 0x50 + slot;
@@ -226,6 +227,7 @@
 		width = 8;
 	return 64 / width;
 }
+#endif
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
@@ -275,7 +277,6 @@
 
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
-	unsigned char i;
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 	};

Modified: trunk/src/southbridge/via/vt8231/vt8231.c
==============================================================================
--- trunk/src/southbridge/via/vt8231/vt8231.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/southbridge/via/vt8231/vt8231.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -12,11 +12,6 @@
 /* Base 8231 controller */
 static device_t lpc_dev;
 
-void hard_reset(void)
-{
-        printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n");
-}
-
 static void keyboard_on(void)
 {
 	unsigned char regval;

Modified: trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
==============================================================================
--- trunk/src/southbridge/via/vt8231/vt8231_early_serial.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/southbridge/via/vt8231/vt8231_early_serial.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -31,7 +31,6 @@
 
 static void enable_vt8231_serial(void) 
 {
-	unsigned long x;
 	uint8_t c;
 	device_t dev;
 	outb(6, 0x80);

Modified: trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -107,6 +107,7 @@
 	return loops ? 0 : -3;
 }
 
+#if 0
 void smbus_reset(void)
 {
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
@@ -119,7 +120,9 @@
 	print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
 	print_debug("\n");
 }
+#endif
 
+#if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register)
 {
 
@@ -142,6 +145,7 @@
 		print_err("Host Busy\n");
 	}
 }
+#endif
 
 /*
  * Copied from intel/i82801dbm early smbus code - suggested by rgm.
@@ -150,7 +154,6 @@
  */
 static int smbus_read_byte(unsigned device, unsigned address)
 {
-	unsigned char global_control_register;
 	unsigned char global_status_register;
 	unsigned char byte;
 

Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c
==============================================================================
--- trunk/src/southbridge/via/vt8231/vt8231_lpc.c	Wed Apr  7 05:11:28 2010	(r5367)
+++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c	Wed Apr  7 05:40:37 2010	(r5368)
@@ -10,7 +10,6 @@
 
 /* PIRQ init
  */
-void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
@@ -55,7 +54,6 @@
 static void vt8231_init(struct device *dev)
 {
 	unsigned char enables;
-	struct southbridge_via_vt8231_config *conf = dev->chip_info;
 
 	printk(BIOS_DEBUG, "vt8231 init\n");
 
@@ -130,7 +128,7 @@
 	rtc_init(0);
 }
 
-void vt8231_read_resources(device_t dev)
+static void vt8231_read_resources(device_t dev)
 {
 	struct resource *res;
 



From svn at coreboot.org  Wed Apr  7 05:41:39 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 05:41:39 +0200
Subject: [coreboot] [commit] r5369 - trunk/src/northbridge/via/vt8601
Message-ID: <E1NzM95-0001V6-R8@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 05:41:39 2010
New Revision: 5369
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5369

Log:
it's a long term, give the compiler a chance to breathe .. ;-)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/northbridge/via/vt8601/raminit.c

Modified: trunk/src/northbridge/via/vt8601/raminit.c
==============================================================================
--- trunk/src/northbridge/via/vt8601/raminit.c	Wed Apr  7 05:40:37 2010	(r5368)
+++ trunk/src/northbridge/via/vt8601/raminit.c	Wed Apr  7 05:41:39 2010	(r5369)
@@ -201,7 +201,8 @@
 	/* grand total. You have rows+cols addressing, * times of banks, times
 	 * width of data in bytes */
 	/* Width is assumed to be 64 bits == 8 bytes */
-	value = (1 << (cols + rows)) * banks * 8;
+	value = (1 << (cols + rows));
+	value *= banks * 8;
 	print_info_hex32(value);
 	print_info(" bytes ");
 	/* Return in 8MB units */



From info at coresystems.de  Wed Apr  7 05:48:45 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 05:48:45 +0200
Subject: [coreboot] build service results for r5367
Message-ID: <E1NzMFx-00056e-IS@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5367 to
the coreboot repository. This caused the following 
changes:

Change Log:
drop the use of function pointers from romcc code.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5367&device=epia&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Apr  7 06:07:14 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 06:07:14 +0200
Subject: [coreboot] build service results for r5368
Message-ID: <E1NzMXq-0002Gy-Km@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5368 to
the coreboot repository. This caused the following 
changes:

Change Log:
clean up age old via epia target.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5368&device=epia&vendor=via&num=2


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Wed Apr  7 06:28:13 2010
From: info at coresystems.de (coreboot information)
Date: Wed, 07 Apr 2010 06:28:13 +0200
Subject: [coreboot] build service results for r5369
Message-ID: <E1NzMs9-0006hC-CZ@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5369 to
the coreboot repository. This caused the following 
changes:

Change Log:
it's a long term, give the compiler a chance to breathe .. ;-)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of via:epia has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From secretocean at gmx.de  Wed Apr  7 12:36:18 2010
From: secretocean at gmx.de (secretocean at gmx.de)
Date: Wed, 07 Apr 2010 12:36:18 +0200
Subject: [coreboot] Need confirmation if HP nx6310 will work with
 coreboot
Message-ID: <20100407103618.267860@gmx.net>

Hi,

oh shit, I thought it would be sufficient to rewrite the flash chip on the board by flashrom! Why this effort?
-- 
GRATIS f?r alle GMX-Mitglieder: Die maxdome Movie-FLAT!
Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01



From c-d.hailfinger.devel.2006 at gmx.net  Wed Apr  7 13:59:01 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Wed, 07 Apr 2010 13:59:01 +0200
Subject: [coreboot] Need confirmation if HP nx6310 will work with
	coreboot
In-Reply-To: <20100407103618.267860@gmx.net>
References: <20100407103618.267860@gmx.net>
Message-ID: <4BBC7385.2070608@gmx.net>

Hi,

On 07.04.2010 12:36, secretocean at gmx.de wrote:
> oh shit, I thought it would be sufficient to rewrite the flash chip on the board by flashrom! Why this effort?
>   

Stefan's description was about the easy and optimal way to get coreboot
running. Depending on the embedded controller (EC) on your board, it is
easily possible you will spend a few weeks or even months full-time to
have coreboot working completely on your laptop.

Why is it such a big effort to port coreboot to a new board, especially
a laptop?
- An OS can simply probe for hardware and load the correct driver.
coreboot can't do that because some of the hardware has to be
initialized blindly (probing is impossible).
- Many board specific settings are not stored in the hardware and there
is no way to determine them from software. The firmware (coreboot/BIOS)
has to know them, or RAM/interrupts/DMA/... will not work. An OS
retrieves these settings from the firmware.
- For some of the hardware on laptops (usually the EC) there is no
documentation at all, so you can either leave the EC (which has its own
firmware) alone and try to reverse engineer the communication protocol
between EC and main CPU which will take weeks or months, or you can
write your own EC firmware which will take months with docs or years
without docs.
- It is not unusual to need a few dozen tries before coreboot runs well
enough on a board that you can reflash in-system.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From mylesgw at gmail.com  Wed Apr  7 17:25:22 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Wed, 7 Apr 2010 09:25:22 -0600
Subject: [coreboot] memset called to somewhere high on the stack
	(uncached)
In-Reply-To: <20100407010108.GA6328@morn.localdomain>
References: <9281742AE71C4F5C9017A52ABC2C857A@chimp>
	<20100407010108.GA6328@morn.localdomain>
Message-ID: <9A1A864045ED4DD7B88C8F56EC8DF2A6@chimp>

> On Tue, Apr 06, 2010 at 04:21:57PM -0600, Myles Watson wrote:
> > I'm seeing code reads to memset() in coreboot_ram interleaved with byte
> > writes to somewhere high on the stack (_estack -0x1fC).  This is a k8.
> >
> > I can't find the place during the RAM stage when we are calling memset
> with
> > caches disabled.  Does this ring a bell for anyone?
> 
> Probably not related, but I found the code at
> src/arch/i386/init/crt0.S.lb:
>         movl    %ebp, %esi
>         /* FIXME: look for a proper place for the stack */
>         movl    $0x4000000, %esp
>         movl    %esp, %ebp
>         pushl %esi
>         pushl $str_coreboot_ram_name
>         call cbfs_and_run_core
> 
> to be problematic on my epia-cn back when I was running timing tests.
> The stack was set to 0x4000000, but that memory wasn't cached.  It
> caused a really long delay - doubly so when lzma compression was used.

It isn't the same address range, but thanks for reminding us.

All:

Does this interfere with suspend/resume?  Is there a ticket already created
for this?  It looks like something that would be hard to debug in system.

Thanks,
Myles




From svn at coreboot.org  Wed Apr  7 17:30:12 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 17:30:12 +0200
Subject: [coreboot] [commit] r5370 - in trunk/src: include/cpu/amd
	mainboard/amd/dbm690t mainboard/amd/mahogany
	mainboard/amd/mahogany_fam10 mainboard/amd/pistachio
	mainboard/amd/serengeti_cheetah mainboard/amd/sereng...
Message-ID: <E1NzXCm-0000qv-JP@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 17:30:11 2010
New Revision: 5370
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5370

Log:
move amd K8/Fam10 "bus detection" function prototypes to a common place.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/include/cpu/amd/amdfam10_sysconf.h
   trunk/src/include/cpu/amd/amdk8_sysconf.h
   trunk/src/mainboard/amd/dbm690t/acpi_tables.c
   trunk/src/mainboard/amd/dbm690t/get_bus_conf.c
   trunk/src/mainboard/amd/dbm690t/irq_tables.c
   trunk/src/mainboard/amd/dbm690t/mptable.c
   trunk/src/mainboard/amd/mahogany/acpi_tables.c
   trunk/src/mainboard/amd/mahogany/get_bus_conf.c
   trunk/src/mainboard/amd/mahogany/irq_tables.c
   trunk/src/mainboard/amd/mahogany/mptable.c
   trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
   trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c
   trunk/src/mainboard/amd/mahogany_fam10/mptable.c
   trunk/src/mainboard/amd/pistachio/acpi_tables.c
   trunk/src/mainboard/amd/pistachio/get_bus_conf.c
   trunk/src/mainboard/amd/pistachio/irq_tables.c
   trunk/src/mainboard/amd/pistachio/mptable.c
   trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
   trunk/src/mainboard/amd/serengeti_cheetah/irq_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah/mptable.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
   trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c
   trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
   trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
   trunk/src/mainboard/asrock/939a785gmh/mptable.c
   trunk/src/mainboard/asus/a8n_e/get_bus_conf.c
   trunk/src/mainboard/asus/a8n_e/irq_tables.c
   trunk/src/mainboard/asus/a8n_e/mptable.c
   trunk/src/mainboard/broadcom/blast/get_bus_conf.c
   trunk/src/mainboard/broadcom/blast/irq_tables.c
   trunk/src/mainboard/broadcom/blast/mptable.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
   trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c
   trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c
   trunk/src/mainboard/gigabyte/m57sli/irq_tables.c
   trunk/src/mainboard/gigabyte/m57sli/mptable.c
   trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c
   trunk/src/mainboard/hp/dl145_g3/mptable.c
   trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c
   trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c
   trunk/src/mainboard/iwill/dk8_htx/irq_tables.c
   trunk/src/mainboard/iwill/dk8_htx/mptable.c
   trunk/src/mainboard/kontron/kt690/acpi_tables.c
   trunk/src/mainboard/kontron/kt690/get_bus_conf.c
   trunk/src/mainboard/kontron/kt690/irq_tables.c
   trunk/src/mainboard/kontron/kt690/mptable.c
   trunk/src/mainboard/msi/ms7135/get_bus_conf.c
   trunk/src/mainboard/msi/ms7135/irq_tables.c
   trunk/src/mainboard/msi/ms7135/mptable.c
   trunk/src/mainboard/msi/ms7260/get_bus_conf.c
   trunk/src/mainboard/msi/ms7260/irq_tables.c
   trunk/src/mainboard/msi/ms7260/mptable.c
   trunk/src/mainboard/msi/ms9185/get_bus_conf.c
   trunk/src/mainboard/msi/ms9185/irq_tables.c
   trunk/src/mainboard/msi/ms9185/mptable.c
   trunk/src/mainboard/msi/ms9282/get_bus_conf.c
   trunk/src/mainboard/msi/ms9282/irq_tables.c
   trunk/src/mainboard/msi/ms9282/mptable.c
   trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c
   trunk/src/mainboard/msi/ms9652_fam10/irq_tables.c
   trunk/src/mainboard/msi/ms9652_fam10/mptable.c
   trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
   trunk/src/mainboard/nvidia/l1_2pvv/irq_tables.c
   trunk/src/mainboard/nvidia/l1_2pvv/mptable.c
   trunk/src/mainboard/sunw/ultra40/get_bus_conf.c
   trunk/src/mainboard/sunw/ultra40/irq_tables.c
   trunk/src/mainboard/sunw/ultra40/mptable.c
   trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c
   trunk/src/mainboard/supermicro/h8dme/irq_tables.c
   trunk/src/mainboard/supermicro/h8dme/mptable.c
   trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c
   trunk/src/mainboard/supermicro/h8dmr/irq_tables.c
   trunk/src/mainboard/supermicro/h8dmr/mptable.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c
   trunk/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
   trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c
   trunk/src/mainboard/technexion/tim5690/acpi_tables.c
   trunk/src/mainboard/technexion/tim5690/get_bus_conf.c
   trunk/src/mainboard/technexion/tim5690/irq_tables.c
   trunk/src/mainboard/technexion/tim5690/mptable.c
   trunk/src/mainboard/technexion/tim8690/acpi_tables.c
   trunk/src/mainboard/technexion/tim8690/get_bus_conf.c
   trunk/src/mainboard/technexion/tim8690/irq_tables.c
   trunk/src/mainboard/technexion/tim8690/mptable.c
   trunk/src/mainboard/tyan/s2881/get_bus_conf.c
   trunk/src/mainboard/tyan/s2881/irq_tables.c
   trunk/src/mainboard/tyan/s2881/mptable.c
   trunk/src/mainboard/tyan/s2885/get_bus_conf.c
   trunk/src/mainboard/tyan/s2885/irq_tables.c
   trunk/src/mainboard/tyan/s2885/mptable.c
   trunk/src/mainboard/tyan/s2891/get_bus_conf.c
   trunk/src/mainboard/tyan/s2891/irq_tables.c
   trunk/src/mainboard/tyan/s2891/mptable.c
   trunk/src/mainboard/tyan/s2892/get_bus_conf.c
   trunk/src/mainboard/tyan/s2892/irq_tables.c
   trunk/src/mainboard/tyan/s2892/mptable.c
   trunk/src/mainboard/tyan/s2895/get_bus_conf.c
   trunk/src/mainboard/tyan/s2895/irq_tables.c
   trunk/src/mainboard/tyan/s2895/mptable.c
   trunk/src/mainboard/tyan/s2912/get_bus_conf.c
   trunk/src/mainboard/tyan/s2912/irq_tables.c
   trunk/src/mainboard/tyan/s2912/mptable.c
   trunk/src/mainboard/tyan/s2912_fam10/irq_tables.c
   trunk/src/mainboard/tyan/s2912_fam10/mptable.c

Modified: trunk/src/include/cpu/amd/amdfam10_sysconf.h
==============================================================================
--- trunk/src/include/cpu/amd/amdfam10_sysconf.h	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/include/cpu/amd/amdfam10_sysconf.h	Wed Apr  7 17:30:11 2010	(r5370)
@@ -70,4 +70,6 @@
 
 extern struct amdfam10_sysconf_t sysconf;
 
+void get_sblk_pci1234(void);
+void get_bus_conf(void);
 #endif

Modified: trunk/src/include/cpu/amd/amdk8_sysconf.h
==============================================================================
--- trunk/src/include/cpu/amd/amdk8_sysconf.h	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/include/cpu/amd/amdk8_sysconf.h	Wed Apr  7 17:30:11 2010	(r5370)
@@ -25,4 +25,6 @@
 
 extern struct amdk8_sysconf_t sysconf;
 
+void get_sblk_pci1234(void);
+void get_bus_conf(void);
 #endif

Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -92,7 +92,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/amd/dbm690t/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/dbm690t/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/amd/dbm690t/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/dbm690t/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/amd/dbm690t/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/dbm690t/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -99,7 +99,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 #if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)

Modified: trunk/src/mainboard/amd/mahogany/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs780;
 u32 sbdn_sb700;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/amd/mahogany/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/amd/mahogany/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -37,7 +37,7 @@
 extern u32 sbdn_rs780;
 extern u32 sbdn_sb700;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -89,7 +89,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 extern void update_ssdt(void *ssdt);
 
 /* not tested yet. */

Modified: trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -25,7 +25,7 @@
 
 #include <cpu/amd/amdfam10_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/amd/mahogany_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/mahogany_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -37,7 +37,7 @@
 extern u32 sbdn_rs780;
 extern u32 sbdn_sb700;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/pistachio/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -92,7 +92,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/amd/pistachio/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/pistachio/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/amd/pistachio/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/pistachio/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/amd/pistachio/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/pistachio/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -150,7 +150,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -39,7 +39,7 @@
 //        0x20202020,
 };
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -34,7 +34,7 @@
 }
 
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/amd/serengeti_cheetah/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -10,7 +10,7 @@
 #include <cpu/amd/amdk8_sysconf.h>
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -160,7 +160,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 extern void update_ssdt(void *ssdt);
 
 static void update_ssdtx(void *ssdtx, int i)

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -46,7 +46,7 @@
 }
 
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 #include <cpu/amd/amdfam10_sysconf.h>
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -99,7 +99,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 #if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)

Modified: trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs780;
 u32 sbdn_sb700;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asrock/939a785gmh/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/asrock/939a785gmh/mptable.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asrock/939a785gmh/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -37,7 +37,7 @@
 extern u32 sbdn_rs780;
 extern u32 sbdn_sb700;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/asus/a8n_e/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asus/a8n_e/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -61,7 +61,7 @@
 
 unsigned bus_type[256];
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/asus/a8n_e/irq_tables.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asus/a8n_e/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -30,7 +30,7 @@
 
 extern unsigned char bus_isa;
 extern unsigned char bus_ck804[6];
-extern void get_bus_conf(void);
+
 
 /**
  * Add one line to IRQ table.

Modified: trunk/src/mainboard/asus/a8n_e/mptable.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/asus/a8n_e/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -32,7 +32,7 @@
 extern unsigned char bus_ck804[6];
 extern unsigned apicid_ck804;
 extern unsigned bus_type[256];
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/broadcom/blast/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/broadcom/blast/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -46,7 +46,7 @@
 };
 unsigned sbdn2;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/broadcom/blast/irq_tables.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/broadcom/blast/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -40,7 +40,7 @@
 
 extern  unsigned sbdn2;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/broadcom/blast/mptable.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/broadcom/blast/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -19,7 +19,7 @@
 
 extern  unsigned sbdn2;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -66,7 +66,7 @@
 };
 unsigned bus_type[256];
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -55,7 +55,7 @@
 extern unsigned char bus_isa;
 extern unsigned char bus_sis966[8]; //1
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
@@ -133,7 +133,6 @@
 			PINTH = IRQ7
 
                         */
-                int	i;
                 uint8_t	reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63};
 		uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
 

Modified: trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -47,7 +47,7 @@
 	unsigned int gsi_base = 0x18;
 	extern unsigned char bus_mcp55[8];
 	extern unsigned apicid_mcp55;
-	extern void get_bus_conf(void);
+	
 	unsigned sbdn;
 	struct resource *res;
 	device_t dev;

Modified: trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -64,7 +64,7 @@
 };
 unsigned bus_type[256]; 
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/gigabyte/m57sli/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/m57sli/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -53,7 +53,7 @@
 extern unsigned char bus_isa;
 extern unsigned char bus_mcp55[8]; //1
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/gigabyte/m57sli/mptable.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/gigabyte/m57sli/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -34,7 +34,7 @@
 
 extern unsigned bus_type[256]; 
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -61,7 +61,7 @@
 //	0x20202020,
 };
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/hp/dl145_g3/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -41,7 +41,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -157,7 +157,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -39,7 +39,7 @@
 //        0x20202020,
 };
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/iwill/dk8_htx/irq_tables.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/iwill/dk8_htx/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -34,7 +34,7 @@
 }
 
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/iwill/dk8_htx/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -10,7 +10,7 @@
 #include <cpu/amd/amdk8_sysconf.h>
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/kontron/kt690/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -92,7 +92,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/kontron/kt690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/kontron/kt690/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/kontron/kt690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/kontron/kt690/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/kontron/kt690/mptable.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/kontron/kt690/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/msi/ms7135/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7135/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -51,7 +51,7 @@
 };
 unsigned bus_type[256];
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/msi/ms7135/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7135/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -37,7 +37,7 @@
 
 extern unsigned char bus_isa;
 extern unsigned char bus_ck804[6];
-extern void get_bus_conf(void);
+
 
 /**
  * Add one line to IRQ table.

Modified: trunk/src/mainboard/msi/ms7135/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7135/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 
 extern unsigned bus_type[256];
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/msi/ms7260/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7260/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -67,7 +67,7 @@
 
 unsigned bus_type[256];
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/msi/ms7260/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7260/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -49,7 +49,7 @@
 extern unsigned char bus_isa;
 extern unsigned char bus_mcp55[8];	// 1
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/msi/ms7260/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms7260/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 extern unsigned apicid_mcp55;
 extern unsigned bus_type[256];
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/msi/ms9185/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9185/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -62,7 +62,7 @@
 //        0x20202020,
 };
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/msi/ms9185/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9185/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -58,7 +58,7 @@
        pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/msi/ms9185/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9185/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -38,7 +38,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/msi/ms9282/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9282/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -64,7 +64,7 @@
 };
 
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/msi/ms9282/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9282/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -55,7 +55,7 @@
         pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/msi/ms9282/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9282/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -32,7 +32,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -49,7 +49,7 @@
 	struct mb_sysconf_t *m;
 	//extern unsigned char bus_mcp55[8];
 	//extern unsigned apicid_mcp55;
-	extern void get_bus_conf(void);
+	
 	unsigned sbdn;
 	struct resource *res;
 	device_t dev;

Modified: trunk/src/mainboard/msi/ms9652_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9652_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/msi/ms9652_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/msi/ms9652_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -61,7 +61,7 @@
 };
 
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/irq_tables.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/nvidia/l1_2pvv/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/nvidia/l1_2pvv/mptable.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/nvidia/l1_2pvv/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/sunw/ultra40/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/sunw/ultra40/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -61,7 +61,7 @@
 unsigned sbdn3;
 unsigned sbdnb;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/sunw/ultra40/irq_tables.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/sunw/ultra40/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -51,7 +51,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdnb;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/sunw/ultra40/mptable.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/sunw/ultra40/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -32,7 +32,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdnb;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -65,7 +65,7 @@
 };
 unsigned sbdnb;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/supermicro/h8dme/irq_tables.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dme/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -53,7 +53,7 @@
 extern unsigned char bus_isa;
 extern unsigned char bus_mcp55[8]; //1
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/supermicro/h8dme/mptable.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dme/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -33,7 +33,7 @@
 
 extern unsigned char bus_pcix[3]; // under bus_mcp55_2
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -65,7 +65,7 @@
 };
 unsigned sbdnb;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/supermicro/h8dmr/irq_tables.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dmr/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -53,7 +53,7 @@
 extern unsigned char bus_isa;
 extern unsigned char bus_mcp55[8]; //1
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/supermicro/h8dmr/mptable.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dmr/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -33,7 +33,7 @@
 
 extern unsigned char bus_pcix[3]; // under bus_mcp55_2
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 extern unsigned sbdn3;
 
 static void *smp_write_config_table(void *v)

Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -92,7 +92,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/technexion/tim5690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim5690/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/technexion/tim5690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim5690/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/technexion/tim5690/mptable.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim5690/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/acpi_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -92,7 +92,7 @@
 	return current;
 }
 
-extern void get_bus_conf(void);
+
 
 static void update_ssdtx(void *ssdtx, int i)
 {

Modified: trunk/src/mainboard/technexion/tim8690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim8690/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -59,7 +59,7 @@
 u32 sbdn_rs690;
 u32 sbdn_sb600;
 
-extern void get_sblk_pci1234(void);
+
 
 static u32 get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/technexion/tim8690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim8690/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -31,7 +31,7 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-extern void get_bus_conf(void);
+
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,

Modified: trunk/src/mainboard/technexion/tim8690/mptable.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/technexion/tim8690/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -36,7 +36,7 @@
 extern u32 sbdn_rs690;
 extern u32 sbdn_sb600;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2881/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2881/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -48,7 +48,7 @@
 };
 unsigned sbdn3;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2881/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2881/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -38,7 +38,7 @@
 
 extern  unsigned sbdn3;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2881/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2881/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -18,7 +18,7 @@
 
 extern  unsigned sbdn3;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2885/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2885/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -50,7 +50,7 @@
 unsigned sbdn3;
 unsigned sbdn5;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2885/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2885/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -41,7 +41,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdn5;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2885/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2885/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -21,7 +21,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdn5;
 
-extern void get_bus_conf(void);
+
 
 
 static void *smp_write_config_table(void *v)

Modified: trunk/src/mainboard/tyan/s2891/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2891/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -55,7 +55,7 @@
 unsigned sbdn3;
 unsigned coprocdn;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2891/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2891/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -45,7 +45,7 @@
 extern  unsigned sbdn3;
 extern  unsigned coprocdn;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2891/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2891/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -22,7 +22,7 @@
 
 extern  unsigned sbdn3;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2892/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2892/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 
 unsigned sbdn3;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2892/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2892/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -43,7 +43,7 @@
 
 extern  unsigned sbdn3;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2892/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2892/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -22,7 +22,7 @@
 
 extern  unsigned sbdn3;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2895/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2895/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -60,7 +60,7 @@
 unsigned sbdn3;
 unsigned sbdnb;
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2895/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2895/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -50,7 +50,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdnb;
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2895/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2895/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -30,7 +30,7 @@
 extern  unsigned sbdn3;
 extern  unsigned sbdnb;
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2912/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/get_bus_conf.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2912/get_bus_conf.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -61,7 +61,7 @@
 };
 
 
-extern void get_sblk_pci1234(void);
+
 
 static unsigned get_bus_conf_done = 0;
 

Modified: trunk/src/mainboard/tyan/s2912/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2912/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2912/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2912/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {

Modified: trunk/src/mainboard/tyan/s2912_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/irq_tables.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2912_fam10/irq_tables.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -52,7 +52,7 @@
 	pirq_info->rfu = rfu;
 }
 
-extern void get_bus_conf(void);
+
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {

Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/mptable.c	Wed Apr  7 05:41:39 2010	(r5369)
+++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c	Wed Apr  7 17:30:11 2010	(r5370)
@@ -29,7 +29,7 @@
 
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {



From svn at coreboot.org  Wed Apr  7 17:32:55 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 17:32:55 +0200
Subject: [coreboot] [commit] r5371 - in trunk/src: northbridge/amd/amdk8
	southbridge/amd/amd8111 southbridge/amd/rs780
	southbridge/sis/sis966 southbridge/via/k8t890
	superio/winbond/w83627hf superio/winbond/w83697hf
Message-ID: <E1NzXFP-0004Yc-7c@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 17:32:52 2010
New Revision: 5371
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5371

Log:
no warnings day

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/northbridge/amd/amdk8/amdk8_f.h
   trunk/src/northbridge/amd/amdk8/coherent_ht.c
   trunk/src/northbridge/amd/amdk8/incoherent_ht.c
   trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
   trunk/src/southbridge/amd/amd8111/amd8111_reset.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/sis/sis966/sis966_aza.c
   trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/src/southbridge/sis/sis966/sis966_nic.c
   trunk/src/southbridge/sis/sis966/sis966_reset.c
   trunk/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c
   trunk/src/superio/winbond/w83697hf/superio.c

Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8_f.h	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/northbridge/amd/amdk8/amdk8_f.h	Wed Apr  7 17:32:52 2010	(r5371)
@@ -522,7 +522,7 @@
 
 #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
 	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
-static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
+static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
 	int i;

Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -153,6 +153,7 @@
 
 }
 
+#if 0
 static void enable_apic_ext_id(u8 node)
 {
 #if CONFIG_ENABLE_APIC_EXT_ID==1
@@ -165,6 +166,7 @@
 	pci_write_config32(NODE_HT(node), 0x68, val);
 #endif
 }
+#endif
 
 static void enable_routing(u8 node)
 {
@@ -378,6 +380,7 @@
 	return byte;
 }
 
+#if TRY_HIGH_FIRST == 1
 static uint8_t get_linkn_last(uint8_t byte)
 {
 	if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
@@ -385,7 +388,9 @@
 	if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
 	return byte>>4;
 }
+#endif
 
+#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
 static uint8_t get_linkn_last_count(uint8_t byte)
 {
 	byte &= 0x0f;
@@ -394,6 +399,7 @@
 	if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
 	return byte>>4;
 }
+#endif
 
 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
 {
@@ -484,10 +490,12 @@
 	fill_row(source,7,get_row(source,dest));
 }
 
+#if 0
 static void clear_temp_row(u8 source)
 {
 	fill_row(source, 7, DEFAULT);
 }
+#endif
 
 static void setup_remote_node(u8 node)
 {

Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -67,10 +67,12 @@
 	return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
 }
 
+#if 0
 static uint8_t ht_lookup_host_capability(device_t dev)
 {
 	return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
 }
+#endif
 
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
 {

Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -1824,12 +1824,12 @@
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
 
@@ -1837,12 +1837,14 @@
 }
 #endif
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
 	u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
 
 	return s3_save_nvram_early(dword, size, nvram_pos);
 }
+#endif
 
 static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {

Modified: trunk/src/southbridge/amd/amd8111/amd8111_reset.c
==============================================================================
--- trunk/src/southbridge/amd/amd8111/amd8111_reset.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/amd/amd8111/amd8111_reset.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -1,4 +1,5 @@
 #include <arch/io.h>
+#include <reset.h>
 #include <device/pci_ids.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \

Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -177,6 +177,7 @@
 	return (cpuid_eax(1) & 0xff00000) != 0;
 }
 
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
 static u8 l3_cache(void)
 {
 	return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@@ -186,6 +187,7 @@
 {
 	return (cpuid_ecx(0x80000008) & 0xFF) + 1;
 }
+#endif
 
 static u8 get_nb_rev(device_t nb_dev)
 {

Modified: trunk/src/southbridge/sis/sis966/sis966_aza.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_aza.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_aza.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -32,7 +32,7 @@
 #include <delay.h>
 #include "sis966.h"
 
-uint8_t	SiS_SiS7502_init[7][3]={
+u8	SiS_SiS7502_init[7][3]={
 {0x04, 0xFF, 0x07},
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -42,9 +42,9 @@
 {0x00, 0x00, 0x00}					//End of table
 };
 
-static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
+static int set_bits(u32 port, u32 mask, u32 val)
 {
-	uint32_t dword;
+	u32 dword;
 	int count;
 
 	val &= mask;
@@ -67,11 +67,9 @@
 
 }
 
- uint32_t send_verb(uint8_t *base, uint32_t verb)
+static u32 send_verb(u32 base, u32 verb)
 {
-
-
-     uint32_t dword;
+     u32 dword;
 
      dword = read32(base + 0x68);
      dword=dword|(unsigned long)0x0002;
@@ -91,13 +89,12 @@
 
      dword = read32(base + 0x64);
      return dword;
-
 }
 
 
-static int codec_detect(uint8_t *base)
+static int codec_detect(u32 base)
 {
-	uint32_t dword;
+	u32 dword;
 	int idx=0;
 
 	/* 1 */ // controller reset
@@ -125,7 +122,7 @@
 }
 
 
-static uint32_t verb_data[] = {
+static u32 verb_data[] = {
 
 //14
 	0x01471c10,
@@ -189,18 +186,18 @@
 	0x01f71f01,
 };
 
-static unsigned find_verb(uint32_t viddid, uint32_t **verb)
+static unsigned find_verb(u32 viddid, u32 **verb)
 {
         if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
-	*verb =  (uint32_t *)verb_data;
-	return sizeof(verb_data)/sizeof(uint32_t);
+	*verb =  (u32 *)verb_data;
+	return sizeof(verb_data)/sizeof(u32);
 }
 
 
-static void codec_init(uint8_t *base, int addr)
+static void codec_init(u32 base, int addr)
 {
-	uint32_t dword;
-	uint32_t *verb;
+	u32 dword;
+	u32 *verb;
 	unsigned verb_size;
 	int i;
 
@@ -235,7 +232,7 @@
 	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
-static void codecs_init(uint8_t *base, uint32_t codec_mask)
+static void codecs_init(u32 base, u32 codec_mask)
 {
 	codec_init(base, 0);
 	return;
@@ -243,15 +240,15 @@
 
 static void aza_init(struct device *dev)
 {
-        uint8_t *base;
+        u32 base;
         struct resource *res;
-        uint32_t codec_mask;
+        u32 codec_mask;
 
         print_debug("AZALIA_INIT:---------->\n");
 
 //-------------- enable AZA (SiS7502) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
         while(SiS_SiS7502_init[i][0] != 0)
         {
@@ -292,8 +289,8 @@
 	if(!res)
 		return;
 
-	base =(uint8_t *) res->base;
-	printk(BIOS_DEBUG, "base = %p\n", base);
+	base = res->base;
+	printk(BIOS_DEBUG, "base = 0x%08x\n", base);
 
 	codec_mask = codec_detect(base);
 

Modified: trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -19,6 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <reset.h>
+
 static unsigned get_sbdn(unsigned bus)
 {
 	device_t dev;
@@ -31,7 +33,7 @@
 	return (dev>>15) & 0x1f;
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
 	set_bios_reset();
 
@@ -42,12 +44,11 @@
 
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
-/* default value for sis966 is good */
+	/* default value for sis966 is good */
 	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 	set_bios_reset();
 

Modified: trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_early_smbus.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_early_smbus.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -344,7 +344,7 @@
                             => 04h :  128MBytes
                             => Others:  Reserved
 */
-void Init_Share_Memory(uint8_t ShareSize)
+static void Init_Share_Memory(uint8_t ShareSize)
 {
     device_t dev;
 
@@ -360,7 +360,7 @@
                => 04h :  512MBytes
                => Others:  Reserved
 */
-void Init_Aper_Size(uint8_t AperSize)
+static void Init_Aper_Size(uint8_t AperSize)
 {
         device_t dev;
         uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
@@ -372,7 +372,7 @@
         pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 }
 
-void sis_init_stage1(void)
+static void sis_init_stage1(void)
 {
         device_t dev;
         uint8_t temp8;
@@ -434,7 +434,7 @@
 
 
 
-void sis_init_stage2(void)
+static void sis_init_stage2(void)
 {
 	device_t dev;
 	msr_t	msr;

Modified: trunk/src/southbridge/sis/sis966/sis966_lpc.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_lpc.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_lpc.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -55,6 +55,8 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL	MAINBOARD_POWER_ON
 #endif
 
+#undef SLAVE_INIT
+
 static void lpc_common_init(device_t dev)
 {
 	uint8_t byte;
@@ -69,11 +71,12 @@
 	setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
 }
 
+#ifdef SLAVE_INIT
 static void lpc_slave_init(device_t dev)
 {
 	lpc_common_init(dev);
 }
-
+#endif
 
 static void lpc_usb_legacy_init(device_t dev)
 {
@@ -271,12 +274,14 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops	= &lpc_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC,
 };
 
+#ifdef SLAVE_INIT // No device? 
 static struct device_operations lpc_slave_ops  = {
 	.read_resources	= sis966_lpc_read_resources,
 	.set_resources	= pci_dev_set_resources,
@@ -285,3 +290,4 @@
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+#endif

Modified: trunk/src/southbridge/sis/sis966/sis966_nic.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_nic.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_nic.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -34,7 +34,7 @@
 #include "sis966.h"
 
 
-uint8_t	SiS_SiS191_init[6][3]={
+u8	SiS_SiS191_init[6][3]={
 {0x04, 0xFF, 0x07},
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -50,17 +50,18 @@
 #define TRUE            1
 #define FALSE           0
 
-uint16_t MacAddr[3];
+u16 MacAddr[3];
 
 
-void writeApcByte(int addr, uint8_t value)
+static void writeApcByte(int addr, u8 value)
 {
     outb(addr,0x78);
     outb(value,0x79);
 }
-uint8_t readApcByte(int addr)
+
+static u8 readApcByte(int addr)
 {
-    uint8_t value;
+    u8 value;
     outb(addr,0x78);
     value=inb(0x79);
     return(value);
@@ -68,7 +69,7 @@
 
 static void readApcMacAddr(void)
 {
-    uint8_t i;
+    u8 i;
 
 // enable APC in south bridge sis966 D2F0
 
@@ -93,9 +94,9 @@
 
 static void set_apc(struct device *dev)
 {
-    uint16_t addr;
-    uint16_t i;
-    uint8_t   bTmp;
+    u16 addr;
+    u16 i;
+    u8   bTmp;
 
     /* enable APC in south bridge sis966 D2F0 */
     outl(0x80001048,0xcf8);
@@ -104,8 +105,8 @@
     for(i = 0 ; i <3; i++)
     {
        addr=0x9+2*i;
-       writeApcByte(addr,(uint8_t)(MacAddr[i]&0xFF));
-	writeApcByte(addr+1L,(uint8_t)((MacAddr[i]>>8)&0xFF));
+       writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
+	writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
         // printf("%x - ",readMacAddrByte(0x59+i));
     }
 
@@ -135,11 +136,11 @@
 //      Contents of EEPROM word (Reg).
 //-----------------------------------------------------------------------------
 #define LoopNum 200
-static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t Reg)
+static  unsigned long ReadEEprom( struct device *dev,  u32 base,  u32 Reg)
 {
-    uint32_t 	data;
-    uint32_t 	i;
-    uint32_t 	ulValue;
+    u32 	data;
+    u32 	i;
+    u32 	ulValue;
 
 
     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
@@ -169,11 +170,11 @@
     return data;
 }
 
-static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u32  base, unsigned phy_addr, unsigned phy_reg)
 {
-    uint32_t   ulValue;
-    uint32_t   Read_Cmd;
-    uint16_t   usData;
+    u32   ulValue;
+    u32   Read_Cmd;
+    u16   usData;
 
 
 
@@ -203,10 +204,10 @@
 
 // Detect a valid PHY
 // If there exist a valid PHY then return TRUE, else return FALSE
-static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
+static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
 {
     int	              bFoundPhy = FALSE;
-    uint16_t		usData;
+    u16		usData;
     int		       PhyAddress = 0;
 
 
@@ -239,17 +240,15 @@
 static void nic_init(struct device *dev)
 {
         int val;
-        uint16_t  PhyAddr;
-        uint32_t base;
+        u16 PhyAddr;
+        u32 base;
         struct resource *res;
 
-
         print_debug("NIC_INIT:---------->\n");
 
-
 //-------------- enable NIC (SiS19x) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
         while(SiS_SiS191_init[i][0] != 0)
 	{

Modified: trunk/src/southbridge/sis/sis966/sis966_reset.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_reset.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_reset.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -22,6 +22,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
 	(((BUS) & 0xFFF) << 20) | \

Modified: trunk/src/southbridge/sis/sis966/sis966_usb2.c
==============================================================================
--- trunk/src/southbridge/sis/sis966/sis966_usb2.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/sis/sis966/sis966_usb2.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -36,7 +36,7 @@
 
 extern struct ehci_debug_info dbg_info;
 
-uint8_t	SiS_SiS7002_init[22][3]={
+u8	SiS_SiS7002_init[22][3]={
 {0x04, 0x00, 0x06},
 {0x0D, 0x00, 0x00},
 
@@ -70,14 +70,14 @@
 
 static void usb2_init(struct device *dev)
 {
-        uint8_t *base;
+        u32 base;
         struct resource *res;
 
         print_debug("USB 2.0 INIT:---------->\n");
 
 //-------------- enable USB2.0 (SiS7002) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
 
         while(SiS_SiS7002_init[i][0] != 0)
@@ -94,8 +94,8 @@
         if(!res)
                 return;
 
-        base =(uint8_t *) res->base;
-        printk(BIOS_DEBUG, "base = %p\n", base);
+        base = res->base;
+        printk(BIOS_DEBUG, "base = 0x%08x\n", base);
         write32(base+0x20, 0x2);
 //-----------------------------------------------------------
 

Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c
==============================================================================
--- trunk/src/southbridge/via/k8t890/k8t890_early_car.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -113,7 +113,8 @@
 	return 1;
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+{
 	
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
@@ -133,7 +134,8 @@
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
 	switch (size) {
 	case 1:
 		*old_dword &= ~0xff;

Modified: trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c
==============================================================================
--- trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -47,7 +47,7 @@
 	pnp_exit_ext_func_mode(dev);
 }
 
-static void w83627hf_set_clksel_48(device_t dev)
+static inline void w83627hf_set_clksel_48(device_t dev)
 {
 	unsigned port = dev >> 8;
 	pnp_enter_ext_func_mode(dev);

Modified: trunk/src/superio/winbond/w83697hf/superio.c
==============================================================================
--- trunk/src/superio/winbond/w83697hf/superio.c	Wed Apr  7 17:30:11 2010	(r5370)
+++ trunk/src/superio/winbond/w83697hf/superio.c	Wed Apr  7 17:32:52 2010	(r5371)
@@ -44,7 +44,7 @@
 static void w83697hf_init(device_t dev)
 {
 	struct superio_winbond_w83697hf_config *conf;
-	struct resource *res0, *res1;
+	struct resource *res0;
 
 	if (!dev->enabled)
 		return;



From svn at coreboot.org  Wed Apr  7 17:40:27 2010
From: svn at coreboot.org (repository service)
Date: Wed, 07 Apr 2010 17:40:27 +0200
Subject: [coreboot] [commit] r5372 - in trunk/src: cpu/amd/car cpu/via/car
	mainboard/asrock/939a785gmh mainboard/digitallogic/msm586seg
	mainboard/gigabyte/ga_2761gxdk mainboard/jetway/j7f24
	mainboard/via/epia mainboar...
Message-ID: <E1NzXMh-0007D9-Ga@ra.coresystems.de>

Author: stepan
Date: Wed Apr  7 17:40:26 2010
New Revision: 5372
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5372

Log:
- copy_and_run() gets the same calling convention on AMD and on all the others.
- some vx800 Kconfig fixes
- remove warnings...
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/amd/car/copy_and_run.c
   trunk/src/cpu/amd/car/post_cache_as_ram.c
   trunk/src/cpu/via/car/cache_as_ram.lds
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/digitallogic/msm586seg/mainboard.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/mainboard/via/epia-m700/fadt.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/mainboard/via/epia-m700/wakeup.c
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/northbridge/via/vx800/northbridge.c
   trunk/src/northbridge/via/vx800/pci_rawops.h
   trunk/src/northbridge/via/vx800/vx800_ide.c
   trunk/src/northbridge/via/vx800/vx800_lpc.c

Modified: trunk/src/cpu/amd/car/copy_and_run.c
==============================================================================
--- trunk/src/cpu/amd/car/copy_and_run.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/cpu/amd/car/copy_and_run.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -1,17 +1,30 @@
-/* by yhlu 6.2005 
-	moved from nrv2v.c and some lines from crt0.S
-   2006/05/02 - stepan: move nrv2b to an extra file.
-*/
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
 
 void cbfs_and_run_core(const char *filename, unsigned ebp);
 
-static void copy_and_run(void)
+static void copy_and_run(unsigned cpu_reset)
 {
-	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", 0);
+	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
 }
 
 #if CONFIG_AP_CODE_IN_CAR == 1
-
 static void copy_and_run_ap_code_in_car(unsigned ret_addr)
 {
 	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);

Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c
==============================================================================
--- trunk/src/cpu/amd/car/post_cache_as_ram.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/cpu/amd/car/post_cache_as_ram.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -112,7 +112,7 @@
 //	wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
 #endif
 	/*copy and execute coreboot_ram */
-	copy_and_run();
+	copy_and_run(0);
 	/* We will not return */
 
 	print_debug("should not be here -\n");

Modified: trunk/src/cpu/via/car/cache_as_ram.lds
==============================================================================
--- trunk/src/cpu/via/car/cache_as_ram.lds	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/cpu/via/car/cache_as_ram.lds	Wed Apr  7 17:40:26 2010	(r5372)
@@ -27,5 +27,4 @@
 		. = ALIGN(16);
 		_einit = .;
 	}
-
 }

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -102,7 +102,7 @@
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
-void sio_init(void)
+static void sio_init(void)
 {
 	u8 reg;
 

Modified: trunk/src/mainboard/digitallogic/msm586seg/mainboard.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/mainboard.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/digitallogic/msm586seg/mainboard.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -7,12 +7,10 @@
 #include "chip.h"
 
 
-static void irqdump()
+static void irqdump(void)
 {
   volatile unsigned char *irq;
   void *mmcr;
-
-
   int i;
   int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
 	        0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
@@ -34,8 +32,9 @@
 /* TODO: finish up mmcr struct in sc520.h, and;
    - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
 */
-static void enable_dev(struct device *dev) {
-	volatile struct mmcrpic *pic = MMCRPIC;
+static void enable_dev(struct device *dev)
+{
+	//volatile struct mmcrpic *pic = MMCRPIC;
 	volatile struct mmcr *mmcr = MMCRDEFAULT;
 
 	/* msm586seg has this register set to a weird value. 
@@ -72,15 +71,11 @@
 	mmcr->pic.gp10imap = 0x9;
 	mmcr->pic.gp9imap = 0x4;
 
-
-
-
-
 	irqdump();
 	printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
 
 	printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
-	printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b);
+	printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
 
 	/* The following block has NOT proven sufficient to get
 	 * the VGA hardware to talk to us 
@@ -124,7 +119,7 @@
 	/* still not interrupts. */
 	/* their IRQ table is wrong. Just hardwire it */
 	{
-	  char pciints[4] = {15, 15, 15, 15};
+	  unsigned char pciints[4] = {15, 15, 15, 15};
 	  pci_assign_irqs(0, 12, pciints);
 	}
 	/* the assigned failed but we just noticed -- there is no
@@ -133,6 +128,7 @@
 	/* follow fuctory here */
 	mmcr->dmacontrol.extchanmapa = 0x3210;
 }
+
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
 	.enable_dev = enable_dev

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -146,8 +146,6 @@
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
 
@@ -175,7 +173,8 @@
 #endif
 	};
 
-        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
+		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -44,10 +44,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
 #endif
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -93,9 +89,6 @@
 
 static void main(unsigned long bist)
 {
-	unsigned long x;
-	device_t dev;
-
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 

Modified: trunk/src/mainboard/via/epia-m700/fadt.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/fadt.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/via/epia-m700/fadt.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -36,8 +36,8 @@
 	memcpy(header->asl_compiler_id, "LXB", 8);
 	header->asl_compiler_revision = 0;
 
-	fadt->firmware_ctrl = facs;
-	fadt->dsdt = dsdt;
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
 	fadt->preferred_pm_profile = 0;
 	fadt->sci_int = 0x9;
 
@@ -105,9 +105,9 @@
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -41,7 +41,6 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <string.h>
-#include "cpu/x86/lapic/boot_cpu.c"
 
 /* This file contains the board-special SI value for raminit.c. */
 #include "driving_clk_phase_data.c"
@@ -59,18 +58,6 @@
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
  * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
  */
-void jason_tsc_count_car(void)
-{
-#if 0
-	unsigned long long start;
-	asm volatile ("rdtsc" : "=A" (start));
-	start >>= 20;
-	print_emerg("jason_tsc_count_car=  ");
-	print_emerg_hex32((unsigned long) start);
-	print_emerg("\n");
-#endif
-}
-
 int acpi_is_wakeup_early_via_vx800(void)
 {
 	device_t dev;
@@ -431,8 +418,6 @@
 	 * g) Rx73h = 32h
 	*/
 
-	jason_tsc_count_car();
-
 	pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
 			   PCI_DEVICE_ID_VIA_VX855_IDE);
 	pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
@@ -462,7 +447,6 @@
 	 * written, then this must be a CPU restart (result of OS reboot cmd),
 	 * so we need a real "cold boot".
 	 */
-	jason_tsc_count_car();
 	if ((boot_mode != 3)
 	    && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
 		outb(6, 0xcf9);
@@ -471,7 +455,6 @@
 	/* x86 cold boot I/O cmd. */
 	/* These 2 lines are the same with epia-cn port. */
 	enable_smbus();
-	jason_tsc_count_car();
 
 	/* This fix does help vx800!, but vx855 doesn't need this. */
 	/* smbus_fixup(&ctrl); */
@@ -564,8 +547,6 @@
 	/* This line is the same with cx700 port. */
 	enable_shadow_ram();
 
-	jason_tsc_count_car();
-
 	/*
 	 * For coreboot most time of S3 resume is the same as normal boot,
 	 * so some memory area under 1M become dirty, so before this happen,
@@ -801,7 +782,6 @@
 		print_debug("\n");
 #endif
 
-		jason_tsc_count_car();
 		/* Copy and execute coreboot_ram. */
 		copy_and_run(new_cpu_reset);
 		/* We will not return. */

Modified: trunk/src/mainboard/via/epia-m700/wakeup.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/wakeup.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/via/epia-m700/wakeup.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -111,9 +111,7 @@
 
 void acpi_jump_wake(u32 vector)
 {
-	u32 tmp, dwEip;
-	u16 tmpvector;
-	u8 Data;
+	u32 dwEip;
 	struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
 
 	printk(BIOS_DEBUG, "IN ACPI JUMP WAKE TO %x\n", vector);

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/mainboard/via/epia/romstage.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -75,7 +75,7 @@
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
-void main(unsigned long bist)
+static void main(unsigned long bist)
 {
 	if (bist == 0) {
 		early_mtrr_init();

Modified: trunk/src/northbridge/via/vx800/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/vx800/northbridge.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/northbridge/via/vx800/northbridge.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -142,7 +142,6 @@
 		 * this register's value multiply 64 * 1024 * 1024
 		 */
 		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
-			unsigned char reg;
 			rambits = pci_read_config8(mc_dev, ramregs[i]);
 			if (rambits != 0)
 				break;
@@ -179,7 +178,7 @@
 	assign_resources(&dev->link[0]);
 }
 
-static const struct device_operations pci_domain_ops = {
+static struct device_operations pci_domain_ops = {
 	.read_resources = pci_domain_read_resources,
 	.set_resources = pci_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
@@ -196,7 +195,7 @@
 {
 }
 
-static const struct device_operations cpu_bus_ops = {
+static struct device_operations cpu_bus_ops = {
 	.read_resources = cpu_bus_noop,
 	.set_resources = cpu_bus_noop,
 	.enable_resources = cpu_bus_noop,

Modified: trunk/src/northbridge/via/vx800/pci_rawops.h
==============================================================================
--- trunk/src/northbridge/via/vx800/pci_rawops.h	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/northbridge/via/vx800/pci_rawops.h	Wed Apr  7 17:40:26 2010	(r5372)
@@ -26,243 +26,260 @@
         (((SEGBUS) & 0xFFF) << 20) | \
         (((DEV) & 0x1F) << 15) | \
         (((FN)  & 0x07) << 12))
-struct  VIA_PCI_REG_INIT_TABLE {
+
+struct VIA_PCI_REG_INIT_TABLE {
 	u8 ChipRevisionStart;
 	u8 ChipRevisionEnd;
 	u8 Bus;
 	u8 Device;
 	u8 Function;
-        u32 Register;
+	u32 Register;
 	u8 Mask;
 	u8 Value;
 };
-typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
+typedef unsigned device_t_raw;	/* pci and pci_mmio need to have different ways to have dev */
 
 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
  * We don't need to set %fs, and %gs anymore
  * Before that We need to use %gs, and leave %fs to other RAM access
  */
- uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where)
+u8 pci_io_rawread_config8(device_t_raw dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-	addr = (dev>>4) | where;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-	addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);	//seg == 0
 #endif
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	return inb(0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
- uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
+#if CONFIG_MMCONF_SUPPORT
+u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
 {
-        unsigned addr;
-        addr = dev | where;
-        return read8x(addr);
+	unsigned addr;
+	addr = dev | where;
+	return read8x(addr);
 }
 #endif
- uint8_t pci_rawread_config8(device_t_raw dev, unsigned where)
+u8 pci_rawread_config8(device_t_raw dev, unsigned where)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	return pci_mmio_rawread_config8(dev, where);
 #else
 	return pci_io_rawread_config8(dev, where);
 #endif
 }
 
- uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where)
+u16 pci_io_rawread_config16(device_t_raw dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-        addr = (dev>>4) | where;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
 #endif
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	return inw(0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
- uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
+#if CONFIG_MMCONF_SUPPORT
+u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
 {
-        unsigned addr;
-        addr = dev | where;
-        return read16x(addr);
+	unsigned addr;
+	addr = dev | where;
+	return read16x(addr);
 }
 #endif
 
- uint16_t pci_rawread_config16(device_t_raw dev, unsigned where)
+u16 pci_rawread_config16(device_t_raw dev, unsigned where)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	return pci_mmio_rawread_config16(dev, where);
 #else
-        return pci_io_rawread_config16(dev, where);
+	return pci_io_rawread_config16(dev, where);
 #endif
 }
 
-
- uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where)
+u32 pci_io_rawread_config32(device_t_raw dev, unsigned where)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-        addr = (dev>>4) | where;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
 #endif
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	return inl(0xCFC);
 }
 
-#if MMCONF_SUPPORT
- uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
+#if CONFIG_MMCONF_SUPPORT
+u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
 {
-        unsigned addr;
-        addr = dev | where;
-        return read32x(addr);
+	unsigned addr;
+	addr = dev | where;
+	return read32x(addr);
 }
 #endif
 
- uint32_t pci_rawread_config32(device_t_raw dev, unsigned where)
+u32 pci_rawread_config32(device_t_raw dev, unsigned where)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	return pci_mmio_rawread_config32(dev, where);
 #else
-        return pci_io_rawread_config32(dev, where);
+	return pci_io_rawread_config32(dev, where);
 #endif
 }
 
- void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
+void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-        addr = (dev>>4) | where;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
 #endif
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	outb(value, 0xCFC + (addr & 3));
 }
 
-#if MMCONF_SUPPORT
- void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
+#if CONFIG_MMCONF_SUPPORT
+void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
 {
-        unsigned addr;
-        addr = dev | where;
-        write8x(addr, value);
+	unsigned addr;
+	addr = dev | where;
+	write8x(addr, value);
 }
 #endif
 
- void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
+void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	pci_mmio_rawwrite_config8(dev, where, value);
 #else
-        pci_io_rawwrite_config8(dev, where, value);
+	pci_io_rawwrite_config8(dev, where, value);
 #endif
 }
 
-
- void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
+void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
 {
-        unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-        addr = (dev>>4) | where;
+	unsigned addr;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
 #endif
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outw(value, 0xCFC + (addr & 2));
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outw(value, 0xCFC + (addr & 2));
 }
 
-#if MMCONF_SUPPORT
- void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
+#if CONFIG_MMCONF_SUPPORT
+void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where,
+				u16 value)
 {
-        unsigned addr;
-        addr = dev | where;
-        write16x(addr, value);
+	unsigned addr;
+	addr = dev | where;
+	write16x(addr, value);
 }
 #endif
 
- void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
+void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	pci_mmio_rawwrite_config16(dev, where, value);
 #else
 	pci_io_rawwrite_config16(dev, where, value);
 #endif
 }
 
-
- void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
+void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
 {
 	unsigned addr;
-#if PCI_IO_CFG_EXT == 0
-        addr = (dev>>4) | where;
+#if CONFIG_PCI_IO_CFG_EXT == 0
+	addr = (dev >> 4) | where;
 #else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+	addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
 #endif
 	outl(0x80000000 | (addr & ~3), 0xCF8);
 	outl(value, 0xCFC);
 }
 
-#if MMCONF_SUPPORT
- void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
+#if CONFIG_MMCONF_SUPPORT
+void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where,
+				u32 value)
 {
-        unsigned addr;
-        addr = dev | where;
-        write32x(addr, value);
+	unsigned addr;
+	addr = dev | where;
+	write32x(addr, value);
 }
 #endif
 
- void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
+void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
 {
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
 	pci_mmio_rawwrite_config32(dev, where, value);
 #else
-        pci_io_rawwrite_config32(dev, where, value);
+	pci_io_rawwrite_config32(dev, where, value);
 #endif
 }
 
-
-void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask)
-{     u8 data=pci_rawread_config8(dev,where);
-       data&=(~mask);
-       data|=orval;
-       pci_rawwrite_config8(dev,where,data);
+void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask)
+{
+	u8 data = pci_rawread_config8(dev, where);
+	data &= (~mask);
+	data |= orval;
+	pci_rawwrite_config8(dev, where, data);
 }
-void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask)
-{     uint16_t data=pci_rawread_config16(dev,where);
-       data&=(~mask);
-       data|=orval;
-       pci_rawwrite_config16(dev,where,data);
+
+void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask)
+{
+	u16 data = pci_rawread_config16(dev, where);
+	data &= (~mask);
+	data |= orval;
+	pci_rawwrite_config16(dev, where, data);
 }
-void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask)
-{     uint32_t data=pci_rawread_config32(dev,where);
-       data&=(~mask);
-       data|=orval;
-       pci_rawwrite_config32(dev,where,data);
+
+void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask)
+{
+	u32 data = pci_rawread_config32(dev, where);
+	data &= (~mask);
+	data |= orval;
+	pci_rawwrite_config32(dev, where, data);
 }
 
-void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask)
+void io_rawmodify_config8(u16 where, u8 orval, u8 mask)
 {
-	u8 data=inb(where);
-       data&=(~mask);
-       data|=orval;
-       outb(data,where);
+	u8 data = inb(where);
+	data &= (~mask);
+	data |= orval;
+	outb(data, where);
 }
 
-void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata)
+void via_pci_inittable(u8 chipversion,
+		       struct VIA_PCI_REG_INIT_TABLE *initdata)
 {
-        u8 i=0;
+	u8 i = 0;
 	device_t_raw devbxdxfx;
-	for(i=0;;i++)	{
-			if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0))
-				break;
-			if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){
-				devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function);
-				pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask);
-			}
+	for (i = 0;; i++) {
+		if ((initdata[i].Mask == 0) && (initdata[i].Value == 0)
+		    && (initdata[i].Bus == 0)
+		    && (initdata[i].ChipRevisionEnd == 0xff)
+		    && (initdata[i].ChipRevisionStart == 0)
+		    && (initdata[i].Device == 0)
+		    && (initdata[i].Function == 0)
+		    && (initdata[i].Register == 0))
+			break;
+		if ((chipversion >= initdata[i].ChipRevisionStart)
+		    && (chipversion <= initdata[i].ChipRevisionEnd)) {
+			devbxdxfx =
+			    PCI_RAWDEV(initdata[i].Bus, initdata[i].Device,
+				       initdata[i].Function);
+			pci_rawmodify_config8(devbxdxfx,
+					      initdata[i].Register,
+					      initdata[i].Value,
+					      initdata[i].Mask);
+		}
 	}
 }
 #endif

Modified: trunk/src/northbridge/via/vx800/vx800_ide.c
==============================================================================
--- trunk/src/northbridge/via/vx800/vx800_ide.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/northbridge/via/vx800/vx800_ide.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -26,7 +26,7 @@
 #include <arch/io.h>
 #include "vx800.h"
 
-static const idedevicepcitable[16 * 12] = {
+static const u8 idedevicepcitable[16 * 12] = {
 	/*
 	0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00,
 	0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6,

Modified: trunk/src/northbridge/via/vx800/vx800_lpc.c
==============================================================================
--- trunk/src/northbridge/via/vx800/vx800_lpc.c	Wed Apr  7 17:32:52 2010	(r5371)
+++ trunk/src/northbridge/via/vx800/vx800_lpc.c	Wed Apr  7 17:40:26 2010	(r5372)
@@ -104,7 +104,7 @@
 	printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
 }
 
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
 {
 	u16 tmp;
 	/* Debounce LID and PWRBTN# Inputs for 16ms. */
@@ -198,7 +198,7 @@
 */
 }
 
-void S3_ps2_kb_ms_wakeup(struct device *dev)
+static void S3_ps2_kb_ms_wakeup(struct device *dev)
 {
 	u8 enables;
 	enables = pci_read_config8(dev, 0x51);
@@ -222,12 +222,12 @@
 
 }
 
-void S3_usb_wakeup(struct device *dev)
+static void S3_usb_wakeup(struct device *dev)
 {
 	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22);	//SCI on USB PME
 }
 
-void S3_lid_wakeup(struct device *dev)
+static void S3_lid_wakeup(struct device *dev)
 {
 	outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22);	//SCI on LID PME
 }
@@ -301,7 +301,7 @@
 
 /* total kludge to get lxb to call our childrens set/enable functions - these are
    not called unless this device has a resource to set - so set a dummy one */
-void vx800_read_resources(device_t dev)
+static void vx800_read_resources(device_t dev)
 {
 
 	struct resource *resource;
@@ -312,10 +312,9 @@
 	    IORESOURCE_STORED;
 	resource->size = 2;
 	resource->base = 0x2e;
-
 }
 
-void vx800_set_resources(device_t dev)
+static void vx800_set_resources(device_t dev)
 {
 	struct resource *resource;
 	resource = find_resource(dev, 1);
@@ -323,7 +322,7 @@
 	pci_dev_set_resources(dev);
 }
 
-void vx800_enable_resources(device_t dev)
+static void vx800_enable_resources(device_t dev)
 {
 	/* vx800 is not a pci bridge and has no resources of its own (other than
 	   standard PC i/o addresses). however it does control the isa bus and so



From patrick at georgi-clan.de  Wed Apr  7 18:13:02 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 07 Apr 2010 18:13:02 +0200
Subject: [coreboot] [PREVIEW]sconfig in C
Message-ID: <4BBCAF0E.7010002@georgi-clan.de>

Hi,

attached you'll find a couple of files:
- sconfig.py.diff which is a patch against our current sconfig.
The patch makes sconfig's output more predictable, by
* reordering hard coded output so its elements match the order of the
generated output
* sorting registers alphanumerically by key
* sorting headers alphanumerically.
The third part contains a hack as I couldn't convince python that it
should sort src/northbridge/amd/amdk8/root_complex/chip.h _after_
src/northbridge/amd/amdk8/chip.h (and the same for fam10)

This patch makes the output of sconfig more regular, but should
otherwise not affect functionality.

The other files provide an implementation of sconfig in C. This has a
couple of advantages:
1. We do not rely on python any longer
2. We use a commonly used compiler compiler (instead of yapps2)
3. It's faster (by a factor of 20, not that this matters much in
absolute numbers)
4. It's smaller: 511LOC vs. 1035LOC (both excluding the compiler
compiler), with code to drop once the byte-for-byte compatibility with
python-sconfig can go.

sconfig.l and sconfig.y give you (with the help of bison and flex) an
implementation of sconfig in C. I wrote a script that mass generated
static.c files for all mainboards both with the python and the C version
and diffed the results.
With the patch to python-sconfig, these diffs are empty.


There are a couple of things left to do with the C version:
- Hook up to the build system (in a way that flex and bison are optional
dependencies, ie. deliver and by default use prebuilt results)

- Add static.dot generation code. This should be reasonably easy, now
that the parsing and rewiring between the components is done. The
emitter is a separate phase which doesn't change the internal device
tree model.

- Clean up:
-- There are various overly complicated things in the code to precisely
match python-sconfig output where it wouldn't matter except to aid with
the comparison (the order of the structs and includes)
-- It's not so nice to stuff all the C code in sconfig.y. Parser and
processing code should be split more sensibly.
-- Naming: A couple of variables changed meaning over their life time.
That's stable now, so they should be named intuitively.
-- Strict parsing: For example, only accept registers for chips
(python-sconfig doesn't do that properly, either)


Yet, I'd prefer to get the python-sconfig patch in, and the C code as
similar to the current state as possible - It's known to give useful
results. That way, further development provides history, so we can
triage bugs more easily.

For the python patch, I'd need some help by someone with python
knowledge about why it sorts the strings the way it does (the
root_complex hack isn't acceptable for upstream)


Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>



From patrick at georgi-clan.de  Wed Apr  7 18:14:22 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Wed, 07 Apr 2010 18:14:22 +0200
Subject: [coreboot] [PREVIEW]sconfig in C
In-Reply-To: <4BBCAF0E.7010002@georgi-clan.de>
References: <4BBCAF0E.7010002@georgi-clan.de>
Message-ID: <4BBCAF5E.6000406@georgi-clan.de>

Am 07.04.2010 18:13, schrieb Patrick Georgi:
> Hi,
> 
> attached you'll find a couple of files:
Well, now..

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
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From stepan at coresystems.de  Thu Apr  8 00:16:54 2010
From: stepan at coresystems.de (Stefan Reinauer)
Date: Thu, 08 Apr 2010 00:16:54 +0200
Subject: [coreboot] [PREVIEW]sconfig in C
In-Reply-To: <4BBCAF5E.6000406@georgi-clan.de>
References: <4BBCAF0E.7010002@georgi-clan.de> <4BBCAF5E.6000406@georgi-clan.de>
Message-ID: <4BBD0456.6030509@coresystems.de>

On 4/7/10 6:14 PM, Patrick Georgi wrote:
> Am 07.04.2010 18:13, schrieb Patrick Georgi:
>   
>> Hi,
>>
>> attached you'll find a couple of files:
>>     
> Well, now..
>
> Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
>   

Awesome work!

Since the C version creates 100% the same device trees as the Python
version, I think this should go in as is.

The .dot files were a nice feature, but so is getting rid of python from
our build tool chain, with all its weird side effects. So let's not wait
but rather implement .dot as we improve the C version of sconfig in the
tree.

Acked-by: Stefan Reinauer <stepan at coresystems.de>





From rminnich at gmail.com  Thu Apr  8 00:40:31 2010
From: rminnich at gmail.com (ron minnich)
Date: Wed, 7 Apr 2010 15:40:31 -0700
Subject: [coreboot] [PREVIEW]sconfig in C
In-Reply-To: <4BBD0456.6030509@coresystems.de>
References: <4BBCAF0E.7010002@georgi-clan.de> <4BBCAF5E.6000406@georgi-clan.de>
	<4BBD0456.6030509@coresystems.de>
Message-ID: <i2p13426df11004071540m595bd671hbde92f2731ed872d@mail.gmail.com>

Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Ah, finally, no more python!

ron



From joe at settoplinux.org  Thu Apr  8 08:09:09 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 08 Apr 2010 02:09:09 -0400
Subject: [coreboot] [PATCH] CAR on Intel P6 Series - Support for model_6bx
Message-ID: <4BBD7305.9060702@settoplinux.org>

Hello,
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000

Build and boot tested (bootlog attached).

Signed-off-by: Joseph Smith <joe at settoplinux.org>

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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From paulepanter at users.sourceforge.net  Thu Apr  8 08:36:56 2010
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 08 Apr 2010 08:36:56 +0200
Subject: [coreboot] [PATCH] CAR on Intel P6 Series - Support for
 model_6bx
In-Reply-To: <4BBD7305.9060702@settoplinux.org>
References: <4BBD7305.9060702@settoplinux.org>
Message-ID: <1270708617.3726.13.camel@mattotaupa>

Dear Joseph,


Am Donnerstag, den 08.04.2010, 02:09 -0400 schrieb Joseph Smith:
> 1. This patch adds CAR for Intel P6 series processors.
> 2. Add support for Micro-FCBGA 479 Celeron and PIII's
> 3. Add support for model_6bx and microcode updates
> 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000

sorry for my dump question. Does supporting CAR have any practical
improvements besides going with coreboot features(?). For example did
boot time improve?

> Build and boot tested (bootlog attached).

It says ?Boot failed.? at the end. But that is due to the payload, is
not it?

Anyway, I just spotted one indentation error. Someone knowledgeable has
to do the review. Sorry!

[?]

> Index: src/cpu/intel/model_6bx/cache_as_ram_disable.c
> ===================================================================
> --- src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
> +++ src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
> @@ -0,0 +1,89 @@
> +/*
> + * This file is part of the coreboot project.
> + * 
> + * Copyright (C) 2007-2009 coresystems GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; version 2 of
> + * the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include "cpu/x86/car/copy_and_run.c"
> +
> +/* called from assembler code */
> +void stage1_main(unsigned long bist);
> +
> +/* from romstage.c */
> +void real_main(unsigned long bist);
> +
> +void stage1_main(unsigned long bist)
> +{
> +       unsigned int cpu_reset = 0;
> +
> +       real_main(bist);
> +
> +       /* No servicable parts below this line .. */
> +#ifdef CAR_DEBUG
> +        /* Check value of esp to verify if we have enough rom for
> stack in Cache as RAM */
> +       unsigned v_esp;
> +       __asm__ volatile (
> +               "movl   %%esp, %0\n"
> +               : "=a" (v_esp)
> +       );
> +       printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
> +#endif
> +
> +        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
> +       printk(BIOS_SPEW, "No cache as ram now - ");

This indentation looks different. I do not know if it is just my MUA.

[?]


Thanks for your work,

Paul


[1] http://www.coreboot.org/images/6/6c/LBCar.pdf
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From svn at coreboot.org  Thu Apr  8 13:37:43 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 13:37:43 +0200
Subject: [coreboot] [commit] r5373 - in trunk: . util/abuild util/sconfig
Message-ID: <E1Nzq3L-0008GD-Pw@ra.coresystems.de>

Author: oxygene
Date: Thu Apr  8 13:37:43 2010
New Revision: 5373
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5373

Log:
Replace sconfig with a C implementation.
(smaller, faster, standard parser generator, no more python)

Provide precompiled parser, so bison and flex are optional dependencies.

Adapt Makefile and abuild (which uses some sconfig file as a
magic path) to match.

Drop python as dependency from README, and add bison and flex
as optional dependencies

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Added:
   trunk/util/sconfig/Makefile.inc
   trunk/util/sconfig/lex.yy.c_shipped
   trunk/util/sconfig/sconfig.l   (contents, props changed)
   trunk/util/sconfig/sconfig.tab.c_shipped
   trunk/util/sconfig/sconfig.tab.h_shipped
   trunk/util/sconfig/sconfig.y   (contents, props changed)
Deleted:
   trunk/util/sconfig/LICENSE
   trunk/util/sconfig/Makefile
   trunk/util/sconfig/NOTES
   trunk/util/sconfig/config.g
   trunk/util/sconfig/parsedesc.g
   trunk/util/sconfig/test.config
   trunk/util/sconfig/yapps2.py
   trunk/util/sconfig/yapps2.tex
   trunk/util/sconfig/yappsrt.py
Modified:
   trunk/Makefile
   trunk/README
   trunk/util/abuild/abuild

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Wed Apr  7 17:40:26 2010	(r5372)
+++ trunk/Makefile	Thu Apr  8 13:37:43 2010	(r5373)
@@ -37,9 +37,6 @@
 export srck := $(top)/util/kconfig
 export obj ?= build
 export objk := $(obj)/util/kconfig
-export sconfig := $(top)/util/sconfig
-export yapps2_py := $(sconfig)/yapps2.py
-export config_g := $(sconfig)/config.g
 
 
 export KERNELVERSION      := 4.0
@@ -109,7 +106,7 @@
 TARGETS-y :=
 
 BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers
-BUILD-y += util/cbfstool
+BUILD-y += util/cbfstool util/sconfig
 BUILD-$(CONFIG_ARCH_X86) += src/pc80
 
 ifneq ($(CONFIG_LOCALVERSION),"")
@@ -150,16 +147,11 @@
 
 CBFSTOOL:=$(obj)/util/cbfstool/cbfstool
 
-$(obj)/mainboard/$(MAINBOARDDIR)/config.py: $(yapps2_py) $(config_g) 
-	mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
-	python $(yapps2_py) $(config_g) $(obj)/mainboard/$(MAINBOARDDIR)/config.py
-
-
 # needed objects that every mainboard uses 
 # Creation of these is architecture and mainboard independent
-$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb  $(obj)/mainboard/$(MAINBOARDDIR)/config.py
+$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb  $(obj)/util/sconfig/sconfig
 	mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
-	(PYTHONPATH=$(top)/util/sconfig python $(obj)/mainboard/$(MAINBOARDDIR)/config.py  $(MAINBOARDDIR) $(top) $(obj)/mainboard/$(MAINBOARDDIR))
+	$(obj)/util/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR)
 
 objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o
 initobjs:=
@@ -334,7 +326,6 @@
 	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.*
 	rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm
 	rmdir -p $(alldirs) 2>/dev/null >/dev/null || true
-	$(MAKE) -C util/sconfig clean
 
 clean: clean-for-update
 	rm -f $(obj)/coreboot* .ccwrap

Modified: trunk/README
==============================================================================
--- trunk/README	Wed Apr  7 17:40:26 2010	(r5372)
+++ trunk/README	Thu Apr  8 13:37:43 2010	(r5373)
@@ -34,7 +34,6 @@
 
  * gcc / g++
  * make
- * python
 
 Optional:
 
@@ -42,6 +41,7 @@
  * iasl (for targets with ACPI support)
  * gdb (for better debugging facilities on some targets)
  * ncurses (for 'make menuconfig')
+ * flex and bison (for regenerating parsers)
 
 
 Building coreboot

Modified: trunk/util/abuild/abuild
==============================================================================
--- trunk/util/abuild/abuild	Wed Apr  7 17:40:26 2010	(r5372)
+++ trunk/util/abuild/abuild	Thu Apr  8 13:37:43 2010	(r5373)
@@ -558,8 +558,8 @@
 buildall=false
 verbose=false
 
-test -f util/sconfig/config.g && ROOT=$( pwd )
-test -f ../util/sconfig/config.g && ROOT=$( cd ..; pwd )
+test -f util/sconfig/sconfig.l && ROOT=$( pwd )
+test -f ../util/sconfig/sconfig.l && ROOT=$( cd ..; pwd )
 test "$ROOT" = "" && ROOT=$( cd ../..; pwd )
 
 # parse parameters.. try to find out whether we're running GNU getopt

Added: trunk/util/sconfig/Makefile.inc
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/Makefile.inc	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,30 @@
+sconfigobj :=
+sconfigobj += lex.yy.o
+sconfigobj += sconfig.tab.o
+
+$(obj)/util/sconfig:
+	mkdir -p $@
+
+$(obj)/util/sconfig/%.o: $(obj)/util/sconfig/%.c
+	printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
+	$(HOSTCC) $(SCONFIGFLAGS) $(HOSTCFLAGS) -c -o $@ $<
+
+ifdef SCONFIG_GENPARSER
+$(top)/util/sconfig/lex.yy.c_shipped: $(top)/util/sconfig/sconfig.l
+	flex -o $@ $<
+
+# the .c rule also creates .h
+$(top)/util/sconfig/sconfig.tab.h_shipped: $(top)/util/sconfig/sconfig.tab.c_shipped
+$(top)/util/sconfig/sconfig.tab.c_shipped: $(top)/util/sconfig/sconfig.y
+	bison --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $<
+
+endif
+
+$(obj)/util/sconfig/lex.yy.o: $(obj)/util/sconfig/sconfig.tab.h
+
+$(obj)/util/sconfig/%: $(top)/util/sconfig/%_shipped
+	cp $< $@
+
+$(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj))
+	printf "    HOSTCXX    $(subst $(obj)/,,$(@)) (link)\n"
+	$(HOSTCXX) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj))

Added: trunk/util/sconfig/lex.yy.c_shipped
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/lex.yy.c_shipped	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,1932 @@
+#line 2 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+
+#line 4 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif	/* defined (__STDC__) */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart(yyin  )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int yyleng;
+
+extern FILE *yyin, *yyout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+    #define YY_LESS_LINENO(n)
+    
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		*yy_cp = (yy_hold_char); \
+		YY_RESTORE_YY_MORE_OFFSET \
+		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr)  )
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via yyrestart()), so that the user can continue scanning by
+	 * just pointing yyin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+                          : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+int yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void yyrestart (FILE *input_file  );
+void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE yy_create_buffer (FILE *file,int size  );
+void yy_delete_buffer (YY_BUFFER_STATE b  );
+void yy_flush_buffer (YY_BUFFER_STATE b  );
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void yypop_buffer_state (void );
+
+static void yyensure_buffer_stack (void );
+static void yy_load_buffer_state (void );
+static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file  );
+
+#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len  );
+
+void *yyalloc (yy_size_t  );
+void *yyrealloc (void *,yy_size_t  );
+void yyfree (void *  );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){ \
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){\
+        yyensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            yy_create_buffer(yyin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+typedef unsigned char YY_CHAR;
+
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int yylineno;
+
+int yylineno = 1;
+
+extern char *yytext;
+#define yytext_ptr yytext
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[]  );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	(yytext_ptr) = yy_bp; \
+	yyleng = (size_t) (yy_cp - yy_bp); \
+	(yy_hold_char) = *yy_cp; \
+	*yy_cp = '\0'; \
+	(yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 25
+#define YY_END_OF_BUFFER 26
+/* This struct is not used in this scanner,
+   but its presence is necessary. */
+struct yy_trans_info
+	{
+	flex_int32_t yy_verify;
+	flex_int32_t yy_nxt;
+	};
+static yyconst flex_int16_t yy_accept[86] =
+    {   0,
+        0,    0,   26,   24,    1,    3,   24,   24,   24,   21,
+       21,   19,   22,   22,   22,   22,   22,   24,   24,   24,
+       24,   24,    1,    3,   24,    0,   24,    0,    2,   21,
+       22,   24,   24,   24,   22,   24,   24,   24,   17,   24,
+       24,    7,   24,   24,   24,   23,   23,   20,   24,   24,
+       24,   16,   18,   11,   15,    8,    9,   10,   24,   12,
+        4,   24,   24,   24,   24,   24,   24,   24,   24,    5,
+       24,   24,   24,   24,   24,   24,   24,    6,   24,   24,
+       24,   14,   24,   13,    0
+    } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        1,    1,    4,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    1,    5,    6,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    7,    1,    8,    7,    9,
+        7,    7,    7,    7,    7,    7,    7,    1,    1,    1,
+       10,    1,    1,    1,   11,   11,   11,   11,   11,   11,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,   12,    1,   13,   11,   14,   15,
+
+       16,   17,   18,   19,   20,    1,    1,   21,   22,   23,
+       24,   25,   26,   27,   28,   29,   30,   31,    1,   32,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+static yyconst flex_int32_t yy_meta[33] =
+    {   0,
+        1,    2,    2,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1
+    } ;
+
+static yyconst flex_int16_t yy_base[91] =
+    {   0,
+        0,    0,  146,    0,  143,  147,  141,   31,   35,   32,
+      111,    0,   43,   46,   49,   65,   52,   53,   46,   21,
+      126,    0,  139,  147,   62,  135,   76,  136,  147,    0,
+       75,   86,  118,  117,   78,  110,  120,  120,    0,  107,
+      115,    0,  111,  105,  111,    0,  147,    0,  114,  102,
+      106,    0,    0,    0,    0,    0,  113,    0,  104,  111,
+        0,  108,  106,   92,  105,  102,   84,   78,   85,    0,
+       83,   88,   68,   83,   64,   62,   69,    0,   59,   53,
+       54,    0,   39,    0,  147,   41,  109,  111,  113,  115
+    } ;
+
+static yyconst flex_int16_t yy_def[91] =
+    {   0,
+       85,    1,   85,   86,   85,   85,   86,   87,   88,   86,
+       10,   86,   10,   10,   10,   10,   10,   86,   86,   86,
+       86,   86,   85,   85,   87,   89,   88,   90,   85,   10,
+       10,   10,   86,   86,   10,   86,   86,   86,   86,   86,
+       86,   86,   86,   86,   86,   86,   85,   32,   86,   86,
+       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
+       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
+       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,
+       86,   86,   86,   86,    0,   85,   85,   85,   85,   85
+    } ;
+
+static yyconst flex_int16_t yy_nxt[180] =
+    {   0,
+        4,    5,    6,    7,    8,    9,   10,   11,   10,   12,
+       13,    4,   14,   15,   16,   17,   13,    4,    4,   18,
+        4,    4,    4,   19,   20,    4,   21,    4,    4,    4,
+        4,    4,   26,   26,   43,   22,   28,   29,   30,   30,
+       30,   22,   31,   44,   31,   31,   31,   31,   31,   31,
+       31,   31,   31,   31,   31,   31,   31,   31,   31,   31,
+       31,   38,   41,   26,   26,   84,   46,   34,   42,   83,
+       33,   31,   31,   31,   37,   82,   39,   28,   29,   40,
+       35,   31,   31,   31,   31,   31,   31,   81,   80,   79,
+       78,   36,   48,   48,   48,   77,   48,   76,   48,   48,
+
+       48,   48,   48,   75,   74,   73,   72,   71,   51,   25,
+       25,   27,   27,   26,   26,   28,   28,   70,   69,   68,
+       67,   66,   65,   64,   63,   62,   61,   60,   59,   58,
+       57,   56,   55,   54,   53,   52,   50,   49,   29,   47,
+       23,   45,   32,   24,   23,   85,    3,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85
+    } ;
+
+static yyconst flex_int16_t yy_chk[180] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    8,    8,   20,    8,    9,    9,   10,   10,
+       10,   86,   10,   20,   10,   10,   10,   10,   10,   13,
+       13,   13,   14,   14,   14,   15,   15,   15,   17,   17,
+       17,   18,   19,   25,   25,   83,   25,   15,   19,   81,
+       14,   16,   16,   16,   17,   80,   18,   27,   27,   18,
+       16,   31,   31,   31,   35,   35,   35,   79,   77,   76,
+       75,   16,   32,   32,   32,   74,   32,   73,   32,   32,
+
+       32,   32,   32,   72,   71,   69,   68,   67,   35,   87,
+       87,   88,   88,   89,   89,   90,   90,   66,   65,   64,
+       63,   62,   60,   59,   57,   51,   50,   49,   45,   44,
+       43,   41,   40,   38,   37,   36,   34,   33,   28,   26,
+       23,   21,   11,    7,    5,    3,   85,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85,   85,
+       85,   85,   85,   85,   85,   85,   85,   85,   85
+    } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int yy_flex_debug;
+int yy_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+#line 2 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+/*
+ * sconfig, coreboot device tree compiler
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *                 written by Patrick Georgi <patrick.georgi at coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include "sconfig.tab.h"
+
+int linenum = 0;
+#line 537 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+
+#define INITIAL 0
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Accessor methods to globals.
+   These are made visible to non-reentrant scanners for convenience. */
+
+int yylex_destroy (void );
+
+int yyget_debug (void );
+
+void yyset_debug (int debug_flag  );
+
+YY_EXTRA_TYPE yyget_extra (void );
+
+void yyset_extra (YY_EXTRA_TYPE user_defined  );
+
+FILE *yyget_in (void );
+
+void yyset_in  (FILE * in_str  );
+
+FILE *yyget_out (void );
+
+void yyset_out  (FILE * out_str  );
+
+int yyget_leng (void );
+
+char *yyget_text (void );
+
+int yyget_lineno (void );
+
+void yyset_lineno (int line_number  );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap (void );
+#else
+extern int yywrap (void );
+#endif
+#endif
+
+    static void yyunput (int c,char *buf_ptr  );
+    
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO fwrite( yytext, yyleng, 1, yyout )
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+		{ \
+		int c = '*'; \
+		int n; \
+		for ( n = 0; n < max_size && \
+			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+			buf[n] = (char) c; \
+		if ( c == '\n' ) \
+			buf[n++] = (char) c; \
+		if ( c == EOF && ferror( yyin ) ) \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+		result = n; \
+		} \
+	else \
+		{ \
+		errno=0; \
+		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+			{ \
+			if( errno != EINTR) \
+				{ \
+				YY_FATAL_ERROR( "input in flex scanner failed" ); \
+				break; \
+				} \
+			errno=0; \
+			clearerr(yyin); \
+			} \
+		}\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int yylex (void);
+
+#define YY_DECL int yylex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+	YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+    
+#line 27 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+
+#line 721 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+
+	if ( !(yy_init) )
+		{
+		(yy_init) = 1;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! (yy_start) )
+			(yy_start) = 1;	/* first start state */
+
+		if ( ! yyin )
+			yyin = stdin;
+
+		if ( ! yyout )
+			yyout = stdout;
+
+		if ( ! YY_CURRENT_BUFFER ) {
+			yyensure_buffer_stack ();
+			YY_CURRENT_BUFFER_LVALUE =
+				yy_create_buffer(yyin,YY_BUF_SIZE );
+		}
+
+		yy_load_buffer_state( );
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+		yy_cp = (yy_c_buf_p);
+
+		/* Support of yytext. */
+		*yy_cp = (yy_hold_char);
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+		yy_current_state = (yy_start);
+yy_match:
+		do
+			{
+			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+			if ( yy_accept[yy_current_state] )
+				{
+				(yy_last_accepting_state) = yy_current_state;
+				(yy_last_accepting_cpos) = yy_cp;
+				}
+			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+				{
+				yy_current_state = (int) yy_def[yy_current_state];
+				if ( yy_current_state >= 86 )
+					yy_c = yy_meta[(unsigned int) yy_c];
+				}
+			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+			++yy_cp;
+			}
+		while ( yy_base[yy_current_state] != 147 );
+
+yy_find_action:
+		yy_act = yy_accept[yy_current_state];
+		if ( yy_act == 0 )
+			{ /* have to back up */
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			yy_act = yy_accept[yy_current_state];
+			}
+
+		YY_DO_BEFORE_ACTION;
+
+do_action:	/* This label is used only to access EOF actions. */
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+			case 0: /* must back up */
+			/* undo the effects of YY_DO_BEFORE_ACTION */
+			*yy_cp = (yy_hold_char);
+			yy_cp = (yy_last_accepting_cpos);
+			yy_current_state = (yy_last_accepting_state);
+			goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 28 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{}
+	YY_BREAK
+case 2:
+/* rule 2 can match eol */
+YY_RULE_SETUP
+#line 29 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{linenum++;}
+	YY_BREAK
+case 3:
+/* rule 3 can match eol */
+YY_RULE_SETUP
+#line 30 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{linenum++;}
+	YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 31 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{return(CHIP);}
+	YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 32 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{return(DEVICE);}
+	YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 33 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{return(REGISTER);}
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 34 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=1; return(BOOL);}
+	YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 35 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=0; return(BOOL);}
+	YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 36 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=PCI; return(BUS);}
+	YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 37 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=PNP; return(BUS);}
+	YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 38 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=I2C; return(BUS);}
+	YY_BREAK
+case 12:
+YY_RULE_SETUP
+#line 39 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=APIC; return(BUS);}
+	YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 40 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=APIC_CLUSTER; return(BUS);}
+	YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 41 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=PCI_DOMAIN; return(BUS);}
+	YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 42 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=IRQ; return(RESOURCE);}
+	YY_BREAK
+case 16:
+YY_RULE_SETUP
+#line 43 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=DRQ; return(RESOURCE);}
+	YY_BREAK
+case 17:
+YY_RULE_SETUP
+#line 44 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.number=IO; return(RESOURCE);}
+	YY_BREAK
+case 18:
+YY_RULE_SETUP
+#line 45 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{return(END);}
+	YY_BREAK
+case 19:
+YY_RULE_SETUP
+#line 46 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{return(EQUALS);}
+	YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 47 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+	YY_BREAK
+case 21:
+YY_RULE_SETUP
+#line 48 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+	YY_BREAK
+case 22:
+YY_RULE_SETUP
+#line 49 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+	YY_BREAK
+case 23:
+/* rule 23 can match eol */
+YY_RULE_SETUP
+#line 50 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+	YY_BREAK
+case 24:
+YY_RULE_SETUP
+#line 51 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
+	YY_BREAK
+case 25:
+YY_RULE_SETUP
+#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+ECHO;
+	YY_BREAK
+#line 932 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+case YY_STATE_EOF(INITIAL):
+	yyterminate();
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = (yy_hold_char);
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed yyin at a new source and called
+			 * yylex().  If so, then we have to assure
+			 * consistency between YY_CURRENT_BUFFER and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+			YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state(  );
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++(yy_c_buf_p);
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+				yy_cp = (yy_c_buf_p);
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer(  ) )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				(yy_did_buffer_switch_on_eof) = 0;
+
+				if ( yywrap( ) )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * yytext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				(yy_c_buf_p) =
+					(yytext_ptr) + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				(yy_c_buf_p) =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+} /* end of yylex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+	register char *source = (yytext_ptr);
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+	else
+		{
+			int num_to_read =
+			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+			int yy_c_buf_p_offset =
+				(int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+						number_to_move - 1;
+
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+			(yy_n_chars), (size_t) num_to_read );
+
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	if ( (yy_n_chars) == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			yyrestart(yyin  );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+		/* Extend the array by 50%, plus the number we really need. */
+		yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+		YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size  );
+		if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+	}
+
+	(yy_n_chars) += number_to_move;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+	return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+    static yy_state_type yy_get_previous_state (void)
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+    
+	yy_current_state = (yy_start);
+
+	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+		{
+		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+		if ( yy_accept[yy_current_state] )
+			{
+			(yy_last_accepting_state) = yy_current_state;
+			(yy_last_accepting_cpos) = yy_cp;
+			}
+		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+			{
+			yy_current_state = (int) yy_def[yy_current_state];
+			if ( yy_current_state >= 86 )
+				yy_c = yy_meta[(unsigned int) yy_c];
+			}
+		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+		}
+
+	return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
+{
+	register int yy_is_jam;
+    	register char *yy_cp = (yy_c_buf_p);
+
+	register YY_CHAR yy_c = 1;
+	if ( yy_accept[yy_current_state] )
+		{
+		(yy_last_accepting_state) = yy_current_state;
+		(yy_last_accepting_cpos) = yy_cp;
+		}
+	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+		{
+		yy_current_state = (int) yy_def[yy_current_state];
+		if ( yy_current_state >= 86 )
+			yy_c = yy_meta[(unsigned int) yy_c];
+		}
+	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+	yy_is_jam = (yy_current_state == 85);
+
+	return yy_is_jam ? 0 : yy_current_state;
+}
+
+    static void yyunput (int c, register char * yy_bp )
+{
+	register char *yy_cp;
+    
+    yy_cp = (yy_c_buf_p);
+
+	/* undo effects of setting up yytext */
+	*yy_cp = (yy_hold_char);
+
+	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = (yy_n_chars) + 2;
+		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+		register char *source =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+	(yytext_ptr) = yy_bp;
+	(yy_hold_char) = *yy_cp;
+	(yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+    static int yyinput (void)
+#else
+    static int input  (void)
+#endif
+
+{
+	int c;
+    
+	*(yy_c_buf_p) = (yy_hold_char);
+
+	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			/* This was really a NUL. */
+			*(yy_c_buf_p) = '\0';
+
+		else
+			{ /* need more input */
+			int offset = (yy_c_buf_p) - (yytext_ptr);
+			++(yy_c_buf_p);
+
+			switch ( yy_get_next_buffer(  ) )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					yyrestart(yyin );
+
+					/*FALLTHROUGH*/
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( yywrap( ) )
+						return EOF;
+
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					(yy_c_buf_p) = (yytext_ptr) + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
+	*(yy_c_buf_p) = '\0';	/* preserve yytext */
+	(yy_hold_char) = *++(yy_c_buf_p);
+
+	return c;
+}
+#endif	/* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ * 
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+    void yyrestart  (FILE * input_file )
+{
+    
+	if ( ! YY_CURRENT_BUFFER ){
+        yyensure_buffer_stack ();
+		YY_CURRENT_BUFFER_LVALUE =
+            yy_create_buffer(yyin,YY_BUF_SIZE );
+	}
+
+	yy_init_buffer(YY_CURRENT_BUFFER,input_file );
+	yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ * 
+ */
+    void yy_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
+{
+    
+	/* TODO. We should be able to replace this entire function body
+	 * with
+	 *		yypop_buffer_state();
+	 *		yypush_buffer_state(new_buffer);
+     */
+	yyensure_buffer_stack ();
+	if ( YY_CURRENT_BUFFER == new_buffer )
+		return;
+
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+	yy_load_buffer_state( );
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (yywrap()) processing, but the only time this flag
+	 * is looked at is after yywrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void yy_load_buffer_state  (void)
+{
+    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+	yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+	(yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ * 
+ * @return the allocated buffer state.
+ */
+    YY_BUFFER_STATE yy_create_buffer  (FILE * file, int  size )
+{
+	YY_BUFFER_STATE b;
+    
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2  );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	yy_init_buffer(b,file );
+
+	return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ * 
+ */
+    void yy_delete_buffer (YY_BUFFER_STATE  b )
+{
+    
+	if ( ! b )
+		return;
+
+	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		yyfree((void *) b->yy_ch_buf  );
+
+	yyfree((void *) b  );
+}
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+    
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+    static void yy_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
+
+{
+	int oerrno = errno;
+    
+	yy_flush_buffer(b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+    /* If b is the current buffer, then yy_init_buffer was _probably_
+     * called from yyrestart() or through yy_get_next_buffer.
+     * In that case, we don't want to reset the lineno or column.
+     */
+    if (b != YY_CURRENT_BUFFER){
+        b->yy_bs_lineno = 1;
+        b->yy_bs_column = 0;
+    }
+
+        b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+    
+	errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ * 
+ */
+    void yy_flush_buffer (YY_BUFFER_STATE  b )
+{
+    	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == YY_CURRENT_BUFFER )
+		yy_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ *  the current state. This function will allocate the stack
+ *  if necessary.
+ *  @param new_buffer The new state.
+ *  
+ */
+void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+    	if (new_buffer == NULL)
+		return;
+
+	yyensure_buffer_stack();
+
+	/* This block is copied from yy_switch_to_buffer. */
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	/* Only push if top exists. Otherwise, replace top. */
+	if (YY_CURRENT_BUFFER)
+		(yy_buffer_stack_top)++;
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+	/* copied from yy_switch_to_buffer. */
+	yy_load_buffer_state( );
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ *  The next element becomes the new top.
+ *  
+ */
+void yypop_buffer_state (void)
+{
+    	if (!YY_CURRENT_BUFFER)
+		return;
+
+	yy_delete_buffer(YY_CURRENT_BUFFER );
+	YY_CURRENT_BUFFER_LVALUE = NULL;
+	if ((yy_buffer_stack_top) > 0)
+		--(yy_buffer_stack_top);
+
+	if (YY_CURRENT_BUFFER) {
+		yy_load_buffer_state( );
+		(yy_did_buffer_switch_on_eof) = 1;
+	}
+}
+
+/* Allocates the stack if it does not exist.
+ *  Guarantees space for at least one push.
+ */
+static void yyensure_buffer_stack (void)
+{
+	int num_to_alloc;
+    
+	if (!(yy_buffer_stack)) {
+
+		/* First allocation is just for 2 elements, since we don't know if this
+		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
+		 * immediate realloc on the next call.
+         */
+		num_to_alloc = 1;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+								(num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+								  
+		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+				
+		(yy_buffer_stack_max) = num_to_alloc;
+		(yy_buffer_stack_top) = 0;
+		return;
+	}
+
+	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+		/* Increase the buffer to prepare for a possible push. */
+		int grow_size = 8 /* arbitrary grow size */;
+
+		num_to_alloc = (yy_buffer_stack_max) + grow_size;
+		(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+								((yy_buffer_stack),
+								num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		if ( ! (yy_buffer_stack) )
+			YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+		/* zero only the new slots.*/
+		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+		(yy_buffer_stack_max) = num_to_alloc;
+	}
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ * 
+ * @return the newly allocated buffer state object. 
+ */
+YY_BUFFER_STATE yy_scan_buffer  (char * base, yy_size_t  size )
+{
+	YY_BUFFER_STATE b;
+    
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	yy_switch_to_buffer(b  );
+
+	return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to yylex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ * 
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ *       yy_scan_bytes() instead.
+ */
+YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+{
+    
+	return yy_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ * 
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE yy_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
+{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+    
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = _yybytes_len + 2;
+	buf = (char *) yyalloc(n  );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+	for ( i = 0; i < _yybytes_len; ++i )
+		buf[i] = yybytes[i];
+
+	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = yy_scan_buffer(buf,n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+    	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		yytext[yyleng] = (yy_hold_char); \
+		(yy_c_buf_p) = yytext + yyless_macro_arg; \
+		(yy_hold_char) = *(yy_c_buf_p); \
+		*(yy_c_buf_p) = '\0'; \
+		yyleng = yyless_macro_arg; \
+		} \
+	while ( 0 )
+
+/* Accessor  methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ * 
+ */
+int yyget_lineno  (void)
+{
+        
+    return yylineno;
+}
+
+/** Get the input stream.
+ * 
+ */
+FILE *yyget_in  (void)
+{
+        return yyin;
+}
+
+/** Get the output stream.
+ * 
+ */
+FILE *yyget_out  (void)
+{
+        return yyout;
+}
+
+/** Get the length of the current token.
+ * 
+ */
+int yyget_leng  (void)
+{
+        return yyleng;
+}
+
+/** Get the current token.
+ * 
+ */
+
+char *yyget_text  (void)
+{
+        return yytext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ * 
+ */
+void yyset_lineno (int  line_number )
+{
+    
+    yylineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ * 
+ * @see yy_switch_to_buffer
+ */
+void yyset_in (FILE *  in_str )
+{
+        yyin = in_str ;
+}
+
+void yyset_out (FILE *  out_str )
+{
+        yyout = out_str ;
+}
+
+int yyget_debug  (void)
+{
+        return yy_flex_debug;
+}
+
+void yyset_debug (int  bdebug )
+{
+        yy_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+        /* Initialization is the same as for the non-reentrant scanner.
+     * This function is called from yylex_destroy(), so don't allocate here.
+     */
+
+    (yy_buffer_stack) = 0;
+    (yy_buffer_stack_top) = 0;
+    (yy_buffer_stack_max) = 0;
+    (yy_c_buf_p) = (char *) 0;
+    (yy_init) = 0;
+    (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+    yyin = stdin;
+    yyout = stdout;
+#else
+    yyin = (FILE *) 0;
+    yyout = (FILE *) 0;
+#endif
+
+    /* For future reference: Set errno on error, since we are called by
+     * yylex_init()
+     */
+    return 0;
+}
+
+/* yylex_destroy is for both reentrant and non-reentrant scanners. */
+int yylex_destroy  (void)
+{
+    
+    /* Pop the buffer stack, destroying each element. */
+	while(YY_CURRENT_BUFFER){
+		yy_delete_buffer(YY_CURRENT_BUFFER  );
+		YY_CURRENT_BUFFER_LVALUE = NULL;
+		yypop_buffer_state();
+	}
+
+	/* Destroy the stack itself. */
+	yyfree((yy_buffer_stack) );
+	(yy_buffer_stack) = NULL;
+
+    /* Reset the globals. This is important in a non-reentrant scanner so the next time
+     * yylex() is called, initialization will occur. */
+    yy_init_globals( );
+
+    return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+}
+#endif
+
+void *yyalloc (yy_size_t  size )
+{
+	return (void *) malloc( size );
+}
+
+void *yyrealloc  (void * ptr, yy_size_t  size )
+{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+	free( (char *) ptr );	/* see yyrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
+
+
+

Added: trunk/util/sconfig/sconfig.l
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/sconfig.l	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,52 @@
+%{
+/*
+ * sconfig, coreboot device tree compiler
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *                 written by Patrick Georgi <patrick.georgi at coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include "sconfig.tab.h"
+
+int linenum = 0;
+%}
+%option nodebug
+%%
+[ \t]+		{}
+#.*\n		{linenum++;}
+\r?\n		{linenum++;}
+chip		{return(CHIP);}
+device		{return(DEVICE);}
+register	{return(REGISTER);}
+on		{yylval.number=1; return(BOOL);}
+off		{yylval.number=0; return(BOOL);}
+pci		{yylval.number=PCI; return(BUS);}
+pnp		{yylval.number=PNP; return(BUS);}
+i2c		{yylval.number=I2C; return(BUS);}
+apic		{yylval.number=APIC; return(BUS);}
+apic_cluster	{yylval.number=APIC_CLUSTER; return(BUS);}
+pci_domain	{yylval.number=PCI_DOMAIN; return(BUS);}
+irq		{yylval.number=IRQ; return(RESOURCE);}
+drq		{yylval.number=DRQ; return(RESOURCE);}
+io		{yylval.number=IO; return(RESOURCE);}
+end		{return(END);}
+=		{return(EQUALS);}
+0x[0-9a-fA-F.]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+[0-9.]+		{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+[0-9a-fA-F.]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+\"[^\"]+\"	{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+[^ \n\t]+	{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
+%%

Added: trunk/util/sconfig/sconfig.tab.c_shipped
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/sconfig.tab.c_shipped	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,2088 @@
+
+/* A Bison parser, made by GNU Bison 2.4.1.  */
+
+/* Skeleton implementation for Bison's Yacc-like parsers in C
+   
+      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+   
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation, either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+   
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+   simplifying the original so-called "semantic" parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.4.1"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Push parsers.  */
+#define YYPUSH 0
+
+/* Pull parsers.  */
+#define YYPULL 1
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+
+
+/* Copy the first part of user declarations.  */
+
+/* Line 189 of yacc.c  */
+#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+
+/*
+ * sconfig, coreboot device tree compiler
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *                 written by Patrick Georgi <patrick.georgi at coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <errno.h>
+
+enum devtype { chip, device };
+
+struct resource;
+struct resource {
+	int type;
+	int index;
+	int base;
+	struct resource *next;
+};
+
+struct reg;
+struct reg {
+	char *key;
+	char *value;
+	struct reg *next;
+};
+
+struct device;
+struct device {
+	int id;
+	int enabled;
+	int used;
+	int multidev;
+	int link;
+	int rescnt;
+	int chiph_exists;
+	char *ops;
+	char *name;
+	char *aliased_name;
+	char *name_underscore;
+	char *path;
+	int path_a;
+	int path_b;
+	int bustype;
+	enum devtype type;
+	struct device *parent;
+	struct device *bus;
+	struct device *next;
+	struct device *nextdev;
+	struct device *children;
+	struct device *latestchild;
+	struct device *next_sibling;
+	struct device *sibling;
+	struct device *chip;
+	struct resource *res;
+	struct reg *reg;
+} *head, *lastdev, *cur_parent, *cur_bus, root;
+
+struct header;
+struct header {
+	char *name;
+	struct header *next;
+} headers;
+
+int devcount = 0;
+
+struct device *new_dev() {
+	struct device *dev = malloc(sizeof(struct device));
+	memset(dev, 0, sizeof(struct device));
+	dev->id = ++devcount;
+	dev->parent = cur_parent;
+	dev->bus = cur_bus;
+	head->next = dev;
+	head = dev;
+	return dev;
+}
+
+int device_match(struct device *a, struct device *b) {
+	if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b))
+		return 1;
+	return 0;
+}
+
+void fold_in(struct device *parent) {
+	struct device *child = parent->children;
+	struct device *latest = 0;
+	while (child != latest) {
+		if (child->children) {
+			if (!latest) latest = child->children;
+			parent->latestchild->next_sibling = child->children;
+			parent->latestchild = child->latestchild;
+		}
+		child = child->next_sibling;
+	}
+}
+
+int yywrap(void) {
+	return 1;
+}
+
+void yyerror (char const *str)
+{
+	fprintf (stderr, "%s\n", str);
+}
+
+
+/* Line 189 of yacc.c  */
+#line 199 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
+
+/* Enabling traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     CHIP = 258,
+     DEVICE = 259,
+     REGISTER = 260,
+     BOOL = 261,
+     BUS = 262,
+     RESOURCE = 263,
+     END = 264,
+     EQUALS = 265,
+     HEX = 266,
+     STRING = 267,
+     PCI = 268,
+     PNP = 269,
+     I2C = 270,
+     APIC = 271,
+     APIC_CLUSTER = 272,
+     PCI_DOMAIN = 273,
+     IRQ = 274,
+     DRQ = 275,
+     IO = 276,
+     NUMBER = 277
+   };
+#endif
+
+
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE
+{
+
+/* Line 214 of yacc.c  */
+#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+
+	struct device *device;
+	char *string;
+	int number;
+
+
+
+/* Line 214 of yacc.c  */
+#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
+} YYSTYPE;
+# define YYSTYPE_IS_TRIVIAL 1
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+
+/* Copy the second part of user declarations.  */
+
+
+/* Line 264 of yacc.c  */
+#line 277 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#elif (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+typedef signed char yytype_int8;
+#else
+typedef short int yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+#  define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+#  define YYSIZE_T size_t
+# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYSIZE_T size_t
+# else
+#  define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E.  */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(e) ((void) (e))
+#else
+# define YYUSE(e) /* empty */
+#endif
+
+/* Identity function, used to suppress warnings about constant conditions.  */
+#ifndef lint
+# define YYID(n) (n)
+#else
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static int
+YYID (int yyi)
+#else
+static int
+YYID (yyi)
+    int yyi;
+#endif
+{
+  return yyi;
+}
+#endif
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols.  */
+
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
+#   elif defined __BUILTIN_VA_ARG_INCR
+#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+#   elif defined _AIX
+#    define YYSTACK_ALLOC __alloca
+#   elif defined _MSC_VER
+#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+#    define alloca _alloca
+#   else
+#    define YYSTACK_ALLOC alloca
+#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     ifndef _STDLIB_H
+#      define _STDLIB_H 1
+#     endif
+#    endif
+#   endif
+#  endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+   /* Pacify GCC's `empty if-body' warning.  */
+#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+#  endif
+# else
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+#  endif
+#  if (defined __cplusplus && ! defined _STDLIB_H \
+       && ! ((defined YYMALLOC || defined malloc) \
+	     && (defined YYFREE || defined free)))
+#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#   ifndef _STDLIB_H
+#    define _STDLIB_H 1
+#   endif
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+     && (! defined __cplusplus \
+	 || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member.  */
+union yyalloc
+{
+  yytype_int16 yyss_alloc;
+  YYSTYPE yyvs_alloc;
+};
+
+/* The size of the maximum gap between one aligned stack and the next.  */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+   N elements.  */
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+      + YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)		\
+      do					\
+	{					\
+	  YYSIZE_T yyi;				\
+	  for (yyi = 0; yyi < (Count); yyi++)	\
+	    (To)[yyi] = (From)[yyi];		\
+	}					\
+      while (YYID (0))
+#  endif
+# endif
+
+/* Relocate STACK from its old location to the new one.  The
+   local variables YYSIZE and YYSTACKSIZE give the old and new number of
+   elements in the stack, and YYPTR gives the new location of the
+   stack.  Advance YYPTR to a properly aligned location for the next
+   stack.  */
+# define YYSTACK_RELOCATE(Stack_alloc, Stack)				\
+    do									\
+      {									\
+	YYSIZE_T yynewbytes;						\
+	YYCOPY (&yyptr->Stack_alloc, Stack, yysize);			\
+	Stack = &yyptr->Stack_alloc;					\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+	yyptr += yynewbytes / sizeof (*yyptr);				\
+      }									\
+    while (YYID (0))
+
+#endif
+
+/* YYFINAL -- State number of the termination state.  */
+#define YYFINAL  9
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   23
+
+/* YYNTOKENS -- Number of terminals.  */
+#define YYNTOKENS  23
+/* YYNNTS -- Number of nonterminals.  */
+#define YYNNTS  11
+/* YYNRULES -- Number of rules.  */
+#define YYNRULES  16
+/* YYNRULES -- Number of states.  */
+#define YYNSTATES  30
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   277
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const yytype_uint8 yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const yytype_uint8 yyprhs[] =
+{
+       0,     0,     3,     5,     7,     9,    12,    15,    16,    19,
+      22,    23,    24,    30,    31,    39,    44
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS.  */
+static const yytype_int8 yyrhs[] =
+{
+      24,     0,    -1,    25,    -1,    28,    -1,    30,    -1,    26,
+      25,    -1,    26,    33,    -1,    -1,    27,    25,    -1,    27,
+      32,    -1,    -1,    -1,     3,    12,    29,    26,     9,    -1,
+      -1,     4,     7,    22,     6,    31,    27,     9,    -1,     8,
+      22,    10,    22,    -1,     5,    12,    10,    12,    -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const yytype_uint16 yyrline[] =
+{
+       0,   132,   132,   152,   152,   154,   154,   154,   156,   156,
+     156,   158,   158,   214,   214,   293,   311
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL",
+  "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C",
+  "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER",
+  "$accept", "devtree", "devchip", "devices", "devicesorresources", "chip",
+  "@1", "device", "@2", "resource", "registers", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const yytype_uint16 yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
+     275,   276,   277
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const yytype_uint8 yyr1[] =
+{
+       0,    23,    24,    25,    25,    26,    26,    26,    27,    27,
+      27,    29,    28,    31,    30,    32,    33
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const yytype_uint8 yyr2[] =
+{
+       0,     2,     1,     1,     1,     2,     2,     0,     2,     2,
+       0,     0,     5,     0,     7,     4,     4
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const yytype_uint8 yydefact[] =
+{
+       0,     0,     0,     0,     2,     3,     4,    11,     0,     1,
+       7,     0,     0,    13,     0,    12,     5,     6,    10,     0,
+       0,     0,     0,    14,     8,     9,    16,     0,     0,    15
+};
+
+/* YYDEFGOTO[NTERM-NUM].  */
+static const yytype_int8 yydefgoto[] =
+{
+      -1,     3,     4,    12,    20,     5,    10,     6,    18,    25,
+      17
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -13
+static const yytype_int8 yypact[] =
+{
+       8,    -6,     6,    14,   -13,   -13,   -13,   -13,    -7,   -13,
+     -13,    10,    -2,   -13,     5,   -13,   -13,   -13,   -13,     9,
+       1,    11,    -4,   -13,   -13,   -13,   -13,    12,    -1,   -13
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const yytype_int8 yypgoto[] =
+{
+     -13,   -13,   -12,   -13,   -13,   -13,   -13,   -13,   -13,   -13,
+     -13
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -1
+static const yytype_uint8 yytable[] =
+{
+      16,     1,     2,    14,     1,     2,     7,    15,    24,    22,
+      23,     1,     2,     8,     9,    11,    13,    19,    27,    21,
+       0,    29,    28,    26
+};
+
+static const yytype_int8 yycheck[] =
+{
+      12,     3,     4,     5,     3,     4,    12,     9,    20,     8,
+       9,     3,     4,     7,     0,    22,     6,    12,    22,    10,
+      -1,    22,    10,    12
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const yytype_uint8 yystos[] =
+{
+       0,     3,     4,    24,    25,    28,    30,    12,     7,     0,
+      29,    22,    26,     6,     5,     9,    25,    33,    31,    12,
+      27,    10,     8,     9,    25,    32,    12,    22,    10,    22
+};
+
+#define yyerrok		(yyerrstatus = 0)
+#define yyclearin	(yychar = YYEMPTY)
+#define YYEMPTY		(-2)
+#define YYEOF		0
+
+#define YYACCEPT	goto yyacceptlab
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror.  This remains here temporarily
+   to ease the transition to the new meaning of YYERROR, for GCC.
+   Once GCC version 2 has supplanted version 1, this can go.  */
+
+#define YYFAIL		goto yyerrlab
+
+#define YYRECOVERING()  (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value)					\
+do								\
+  if (yychar == YYEMPTY && yylen == 1)				\
+    {								\
+      yychar = (Token);						\
+      yylval = (Value);						\
+      yytoken = YYTRANSLATE (yychar);				\
+      YYPOPSTACK (1);						\
+      goto yybackup;						\
+    }								\
+  else								\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
+      YYERROR;							\
+    }								\
+while (YYID (0))
+
+
+#define YYTERROR	1
+#define YYERRCODE	256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (YYID (N))                                                    \
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (YYID (0))
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+	      (Loc).first_line, (Loc).first_column,	\
+	      (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
+/* Enable debugging if requested.  */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args)			\
+do {						\
+  if (yydebug)					\
+    YYFPRINTF Args;				\
+} while (YYID (0))
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)			  \
+do {									  \
+  if (yydebug)								  \
+    {									  \
+      YYFPRINTF (stderr, "%s ", Title);					  \
+      yy_symbol_print (stderr,						  \
+		  Type, Value); \
+      YYFPRINTF (stderr, "\n");						  \
+    }									  \
+} while (YYID (0))
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_value_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (!yyvaluep)
+    return;
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# else
+  YYUSE (yyoutput);
+# endif
+  switch (yytype)
+    {
+      default:
+	break;
+    }
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_print (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE const * const yyvaluep;
+#endif
+{
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+  yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+  YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
+#else
+static void
+yy_stack_print (yybottom, yytop)
+    yytype_int16 *yybottom;
+    yytype_int16 *yytop;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (; yybottom <= yytop; yybottom++)
+    {
+      int yybot = *yybottom;
+      YYFPRINTF (stderr, " %d", yybot);
+    }
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (YYID (0))
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
+#else
+static void
+yy_reduce_print (yyvsp, yyrule)
+    YYSTYPE *yyvsp;
+    int yyrule;
+#endif
+{
+  int yynrhs = yyr2[yyrule];
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+	     yyrule - 1, yylno);
+  /* The symbols being reduced.  */
+  for (yyi = 0; yyi < yynrhs; yyi++)
+    {
+      YYFPRINTF (stderr, "   $%d = ", yyi + 1);
+      yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
+		       &(yyvsp[(yyi + 1) - (yynrhs)])
+		       		       );
+      YYFPRINTF (stderr, "\n");
+    }
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (yyvsp, Rule); \
+} while (YYID (0))
+
+/* Nonzero means print parse trace.  It is left uninitialized so that
+   multiple parsers can coexist.  */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks.  */
+#ifndef	YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+   if the built-in stack extension method is used).
+
+   Do not make this value too large; the results are undefined if
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+   evaluated with infinite-precision integer arithmetic.  */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+

+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+#  if defined __GLIBC__ && defined _STRING_H
+#   define yystrlen strlen
+#  else
+/* Return the length of YYSTR.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static YYSIZE_T
+yystrlen (const char *yystr)
+#else
+static YYSIZE_T
+yystrlen (yystr)
+    const char *yystr;
+#endif
+{
+  YYSIZE_T yylen;
+  for (yylen = 0; yystr[yylen]; yylen++)
+    continue;
+  return yylen;
+}
+#  endif
+# endif
+
+# ifndef yystpcpy
+#  if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+#   define yystpcpy stpcpy
+#  else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+   YYDEST.  */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+#else
+static char *
+yystpcpy (yydest, yysrc)
+    char *yydest;
+    const char *yysrc;
+#endif
+{
+  char *yyd = yydest;
+  const char *yys = yysrc;
+
+  while ((*yyd++ = *yys++) != '\0')
+    continue;
+
+  return yyd - 1;
+}
+#  endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      YYSIZE_T yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into YYRESULT an error message about the unexpected token
+   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
+   including the terminating null byte.  If YYRESULT is null, do not
+   copy anything; just return the number of bytes that would be
+   copied.  As a special case, return 0 if an ordinary "syntax error"
+   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
+   size calculation.  */
+static YYSIZE_T
+yysyntax_error (char *yyresult, int yystate, int yychar)
+{
+  int yyn = yypact[yystate];
+
+  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
+    return 0;
+  else
+    {
+      int yytype = YYTRANSLATE (yychar);
+      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+      YYSIZE_T yysize = yysize0;
+      YYSIZE_T yysize1;
+      int yysize_overflow = 0;
+      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+      int yyx;
+
+# if 0
+      /* This is so xgettext sees the translatable formats that are
+	 constructed on the fly.  */
+      YY_("syntax error, unexpected %s");
+      YY_("syntax error, unexpected %s, expecting %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+# endif
+      char *yyfmt;
+      char const *yyf;
+      static char const yyunexpected[] = "syntax error, unexpected %s";
+      static char const yyexpecting[] = ", expecting %s";
+      static char const yyor[] = " or %s";
+      char yyformat[sizeof yyunexpected
+		    + sizeof yyexpecting - 1
+		    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+		       * (sizeof yyor - 1))];
+      char const *yyprefix = yyexpecting;
+
+      /* Start YYX at -YYN if negative to avoid negative indexes in
+	 YYCHECK.  */
+      int yyxbegin = yyn < 0 ? -yyn : 0;
+
+      /* Stay within bounds of both yycheck and yytname.  */
+      int yychecklim = YYLAST - yyn + 1;
+      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+      int yycount = 1;
+
+      yyarg[0] = yytname[yytype];
+      yyfmt = yystpcpy (yyformat, yyunexpected);
+
+      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	  {
+	    if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+	      {
+		yycount = 1;
+		yysize = yysize0;
+		yyformat[sizeof yyunexpected - 1] = '\0';
+		break;
+	      }
+	    yyarg[yycount++] = yytname[yyx];
+	    yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+	    yysize_overflow |= (yysize1 < yysize);
+	    yysize = yysize1;
+	    yyfmt = yystpcpy (yyfmt, yyprefix);
+	    yyprefix = yyor;
+	  }
+
+      yyf = YY_(yyformat);
+      yysize1 = yysize + yystrlen (yyf);
+      yysize_overflow |= (yysize1 < yysize);
+      yysize = yysize1;
+
+      if (yysize_overflow)
+	return YYSIZE_MAXIMUM;
+
+      if (yyresult)
+	{
+	  /* Avoid sprintf, as that infringes on the user's name space.
+	     Don't have undefined behavior even if the translation
+	     produced a string with the wrong number of "%s"s.  */
+	  char *yyp = yyresult;
+	  int yyi = 0;
+	  while ((*yyp = *yyf) != '\0')
+	    {
+	      if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		{
+		  yyp += yytnamerr (yyp, yyarg[yyi++]);
+		  yyf += 2;
+		}
+	      else
+		{
+		  yyp++;
+		  yyf++;
+		}
+	    }
+	}
+      return yysize;
+    }
+}
+#endif /* YYERROR_VERBOSE */
+

+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  YYUSE (yyvaluep);
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+
+      default:
+	break;
+    }
+}
+
+/* Prevent warnings from -Wmissing-prototypes.  */
+#ifdef YYPARSE_PARAM
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void *YYPARSE_PARAM);
+#else
+int yyparse ();
+#endif
+#else /* ! YYPARSE_PARAM */
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+/* The lookahead symbol.  */
+int yychar;
+
+/* The semantic value of the lookahead symbol.  */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far.  */
+int yynerrs;
+
+
+
+/*-------------------------.
+| yyparse or yypush_parse.  |
+`-------------------------*/
+
+#ifdef YYPARSE_PARAM
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void *YYPARSE_PARAM)
+#else
+int
+yyparse (YYPARSE_PARAM)
+    void *YYPARSE_PARAM;
+#endif
+#else /* ! YYPARSE_PARAM */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+     || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void)
+#else
+int
+yyparse ()
+
+#endif
+#endif
+{
+
+
+    int yystate;
+    /* Number of tokens to shift before error messages enabled.  */
+    int yyerrstatus;
+
+    /* The stacks and their tools:
+       `yyss': related to states.
+       `yyvs': related to semantic values.
+
+       Refer to the stacks thru separate pointers, to allow yyoverflow
+       to reallocate them elsewhere.  */
+
+    /* The state stack.  */
+    yytype_int16 yyssa[YYINITDEPTH];
+    yytype_int16 *yyss;
+    yytype_int16 *yyssp;
+
+    /* The semantic value stack.  */
+    YYSTYPE yyvsa[YYINITDEPTH];
+    YYSTYPE *yyvs;
+    YYSTYPE *yyvsp;
+
+    YYSIZE_T yystacksize;
+
+  int yyn;
+  int yyresult;
+  /* Lookahead token as an internal (translated) token number.  */
+  int yytoken;
+  /* The variables used to return semantic value and location from the
+     action routines.  */
+  YYSTYPE yyval;
+
+#if YYERROR_VERBOSE
+  /* Buffer for error messages, and its allocated size.  */
+  char yymsgbuf[128];
+  char *yymsg = yymsgbuf;
+  YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))
+
+  /* The number of symbols on the RHS of the reduced rule.
+     Keep to zero when no symbol should be popped.  */
+  int yylen = 0;
+
+  yytoken = 0;
+  yyss = yyssa;
+  yyvs = yyvsa;
+  yystacksize = YYINITDEPTH;
+
+  YYDPRINTF ((stderr, "Starting parse\n"));
+
+  yystate = 0;
+  yyerrstatus = 0;
+  yynerrs = 0;
+  yychar = YYEMPTY; /* Cause a token to be read.  */
+
+  /* Initialize stack pointers.
+     Waste one element of value and location stack
+     so that they stay on the same level as the state stack.
+     The wasted elements are never initialized.  */
+  yyssp = yyss;
+  yyvsp = yyvs;
+
+  goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate.  |
+`------------------------------------------------------------*/
+ yynewstate:
+  /* In all cases, when you get here, the value and location stacks
+     have just been pushed.  So pushing a state here evens the stacks.  */
+  yyssp++;
+
+ yysetstate:
+  *yyssp = yystate;
+
+  if (yyss + yystacksize - 1 <= yyssp)
+    {
+      /* Get the current used size of the three stacks, in elements.  */
+      YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+      {
+	/* Give user a chance to reallocate the stack.  Use copies of
+	   these so that the &'s don't force the real ones into
+	   memory.  */
+	YYSTYPE *yyvs1 = yyvs;
+	yytype_int16 *yyss1 = yyss;
+
+	/* Each stack pointer address is followed by the size of the
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
+		    &yyss1, yysize * sizeof (*yyssp),
+		    &yyvs1, yysize * sizeof (*yyvsp),
+		    &yystacksize);
+
+	yyss = yyss1;
+	yyvs = yyvs1;
+      }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+      goto yyexhaustedlab;
+# else
+      /* Extend the stack our own way.  */
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
+      yystacksize *= 2;
+      if (YYMAXDEPTH < yystacksize)
+	yystacksize = YYMAXDEPTH;
+
+      {
+	yytype_int16 *yyss1 = yyss;
+	union yyalloc *yyptr =
+	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+	if (! yyptr)
+	  goto yyexhaustedlab;
+	YYSTACK_RELOCATE (yyss_alloc, yyss);
+	YYSTACK_RELOCATE (yyvs_alloc, yyvs);
+#  undef YYSTACK_RELOCATE
+	if (yyss1 != yyssa)
+	  YYSTACK_FREE (yyss1);
+      }
+# endif
+#endif /* no yyoverflow */
+
+      yyssp = yyss + yysize - 1;
+      yyvsp = yyvs + yysize - 1;
+
+      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+		  (unsigned long int) yystacksize));
+
+      if (yyss + yystacksize - 1 <= yyssp)
+	YYABORT;
+    }
+
+  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+  if (yystate == YYFINAL)
+    YYACCEPT;
+
+  goto yybackup;
+
+/*-----------.
+| yybackup.  |
+`-----------*/
+yybackup:
+
+  /* Do appropriate processing given the current state.  Read a
+     lookahead token if we need one and don't already have one.  */
+
+  /* First try to decide what to do without reference to lookahead token.  */
+  yyn = yypact[yystate];
+  if (yyn == YYPACT_NINF)
+    goto yydefault;
+
+  /* Not known => get a lookahead token if don't already have one.  */
+
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol.  */
+  if (yychar == YYEMPTY)
+    {
+      YYDPRINTF ((stderr, "Reading a token: "));
+      yychar = YYLEX;
+    }
+
+  if (yychar <= YYEOF)
+    {
+      yychar = yytoken = YYEOF;
+      YYDPRINTF ((stderr, "Now at end of input.\n"));
+    }
+  else
+    {
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+    }
+
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+    goto yydefault;
+  yyn = yytable[yyn];
+  if (yyn <= 0)
+    {
+      if (yyn == 0 || yyn == YYTABLE_NINF)
+	goto yyerrlab;
+      yyn = -yyn;
+      goto yyreduce;
+    }
+
+  /* Count tokens shifted since error; after three, turn off error
+     status.  */
+  if (yyerrstatus)
+    yyerrstatus--;
+
+  /* Shift the lookahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+  /* Discard the shifted token.  */
+  yychar = YYEMPTY;
+
+  yystate = yyn;
+  *++yyvsp = yylval;
+
+  goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state.  |
+`-----------------------------------------------------------*/
+yydefault:
+  yyn = yydefact[yystate];
+  if (yyn == 0)
+    goto yyerrlab;
+  goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction.  |
+`-----------------------------*/
+yyreduce:
+  /* yyn is the number of a rule to reduce with.  */
+  yylen = yyr2[yyn];
+
+  /* If YYLEN is nonzero, implement the default value of the action:
+     `$$ = $1'.
+
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
+     users should not rely upon it.  Assigning to YYVAL
+     unconditionally makes the parser a bit smaller, and it avoids a
+     GCC warning that YYVAL may be used uninitialized.  */
+  yyval = yyvsp[1-yylen];
+
+
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 2:
+
+/* Line 1455 of yacc.c  */
+#line 132 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+	root.next_sibling = root.children;
+	root.next_sibling->next_sibling = root.next_sibling->children;
+
+	struct device *dev = &root;
+	while (dev) {
+		/* skip "chip" elements in children chain */
+		while (dev->children && (dev->children->type == chip)) dev->children = dev->children->children;
+		/* skip "chip" elements and functions of the same device in sibling chain */
+		while (dev->sibling && dev->sibling->used) dev->sibling = dev->sibling->sibling;
+		/* If end of chain, and parent is a chip, move on */
+		if (!dev->sibling && (dev->parent->type == chip)) dev->sibling = dev->parent->sibling;
+		/* skip chips */
+		while (dev->sibling && dev->sibling->type == chip) dev->sibling = dev->sibling->children;
+		/* skip duplicate function elements in nextdev chain */
+		while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev;
+		dev = dev->next_sibling;
+	}
+	;}
+    break;
+
+  case 11:
+
+/* Line 1455 of yacc.c  */
+#line 158 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+	(yyval.device) = new_dev();
+	(yyval.device)->chiph_exists = 1;
+	(yyval.device)->name = (yyvsp[(2) - (2)].string);
+	(yyval.device)->name_underscore = strdup((yyval.device)->name);
+	char *c;
+	for (c = (yyval.device)->name_underscore; *c; c++) {
+		if (*c == '/') *c = '_';
+	}
+	(yyval.device)->type = chip;
+	(yyval.device)->chip = (yyval.device);
+
+	struct stat st;
+	char *chip_h = malloc(strlen((yyvsp[(2) - (2)].string))+12);
+	sprintf(chip_h, "src/%s/chip.h", (yyvsp[(2) - (2)].string));
+	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
+		(yyval.device)->chiph_exists = 0;
+
+	if (cur_parent->latestchild) {
+		cur_parent->latestchild->next_sibling = (yyval.device);
+		cur_parent->latestchild->sibling = (yyval.device);
+	}
+	cur_parent->latestchild = (yyval.device);
+	if (!cur_parent->children)
+		cur_parent->children = (yyval.device);
+
+	cur_parent = (yyval.device);
+;}
+    break;
+
+  case 12:
+
+/* Line 1455 of yacc.c  */
+#line 186 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+	cur_parent = (yyvsp[(3) - (5)].device)->parent;
+
+	fold_in((yyvsp[(3) - (5)].device));
+
+	if ((yyvsp[(3) - (5)].device)->chiph_exists) {
+		int include_exists = 0;
+		struct header *h = &headers;
+		while (h->next) {
+			int result = strcmp((yyvsp[(3) - (5)].device)->name, h->next->name);
+			if (result == 0) {
+				include_exists = 1;
+				break;
+			}
+			if (result < 0) break;
+			h = h->next;
+		}
+		if (!include_exists) {
+			struct header *tmp = h->next;
+			h->next = malloc(sizeof(struct header));
+			memset(h->next, 0, sizeof(struct header));
+			h->next->name = (yyvsp[(3) - (5)].device)->name;
+			h->next->next = tmp;
+			break;
+		}
+	}
+;}
+    break;
+
+  case 13:
+
+/* Line 1455 of yacc.c  */
+#line 214 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+	(yyval.device) = new_dev();
+	(yyval.device)->bustype = (yyvsp[(2) - (4)].number);
+
+	char *tmp;
+	(yyval.device)->path_a = strtol(strdup((yyvsp[(3) - (4)].string)), &tmp, 16);
+	if (*tmp == '.') {
+		tmp++;
+		(yyval.device)->path_b = strtol(tmp, NULL, 16);
+	}
+
+	char *name = malloc(10);
+	sprintf(name, "_dev%d", (yyval.device)->id);
+	(yyval.device)->name = name;
+	(yyval.device)->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr
+	(yyval.device)->type = device;
+	(yyval.device)->enabled = (yyvsp[(4) - (4)].number);
+	(yyval.device)->chip = (yyval.device)->parent->chip;
+
+	if (cur_parent->latestchild) {
+		cur_parent->latestchild->next_sibling = (yyval.device);
+		cur_parent->latestchild->sibling = (yyval.device);
+	}
+	cur_parent->latestchild = (yyval.device);
+	if (!cur_parent->children)
+		cur_parent->children = (yyval.device);
+
+	lastdev->nextdev = (yyval.device);
+	lastdev = (yyval.device);
+	if ((yyvsp[(2) - (4)].number) == PCI) {
+		(yyval.device)->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}";
+	}
+	if ((yyvsp[(2) - (4)].number) == PNP) {
+		(yyval.device)->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}";
+	}
+	if ((yyvsp[(2) - (4)].number) == I2C) {
+		(yyval.device)->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}";
+	}
+	if ((yyvsp[(2) - (4)].number) == APIC) {
+		(yyval.device)->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}";
+	}
+	if ((yyvsp[(2) - (4)].number) == APIC_CLUSTER) {
+		(yyval.device)->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}";
+	}
+	if ((yyvsp[(2) - (4)].number) == PCI_DOMAIN) {
+		(yyval.device)->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}";
+	}
+	cur_parent = (yyval.device);
+	cur_bus = (yyval.device);
+;}
+    break;
+
+  case 14:
+
+/* Line 1455 of yacc.c  */
+#line 264 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+	cur_parent = (yyvsp[(5) - (7)].device)->parent;
+	cur_bus = (yyvsp[(5) - (7)].device)->bus;
+
+	fold_in((yyvsp[(5) - (7)].device));
+
+	struct device *d = (yyvsp[(5) - (7)].device)->children;
+	while (d) {
+		int link = 0;
+		struct device *cmp = d->next_sibling;
+		while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) {
+			if (cmp->type==device && !cmp->used) {
+				if (device_match(d, cmp)) {
+					d->multidev = 1;
+
+					cmp->aliased_name = malloc(12);
+					sprintf(cmp->aliased_name, "_dev%d", cmp->id);
+					cmp->id = d->id;
+					cmp->name = d->name;
+					cmp->used = 1;
+					cmp->link = ++link;
+				}
+			}
+			cmp = cmp->next_sibling;
+		}
+		d = d->next_sibling;
+	}
+;}
+    break;
+
+  case 15:
+
+/* Line 1455 of yacc.c  */
+#line 294 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+		struct resource *r = malloc(sizeof(struct resource));
+		memset (r, 0, sizeof(struct resource));
+		r->type = (yyvsp[(1) - (4)].number);
+		r->index = strtol((yyvsp[(2) - (4)].string), NULL, 0);
+		r->base = strtol((yyvsp[(4) - (4)].string), NULL, 0);
+		if (cur_parent->res) {
+			struct resource *head = cur_parent->res;
+			while (head->next) head = head->next;
+			head->next = r;
+		} else {
+			cur_parent->res = r;
+		}
+		cur_parent->rescnt++;
+	;}
+    break;
+
+  case 16:
+
+/* Line 1455 of yacc.c  */
+#line 312 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+    {
+		struct reg *r = malloc(sizeof(struct reg));
+		memset (r, 0, sizeof(struct reg));
+		r->key = (yyvsp[(2) - (4)].string);
+		r->value = (yyvsp[(4) - (4)].string);
+		if (cur_parent->reg) {
+			struct reg *head = cur_parent->reg;
+			// sorting to be equal to sconfig's behaviour
+			int sort = strcmp(r->key, head->key);
+			if (sort == 0) {
+				printf("ERROR: duplicate 'register' key.\n");
+				exit(1);
+			}
+			if (sort<0) {
+				r->next = head;
+				cur_parent->reg = r;
+			} else {
+				while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next;
+				r->next = head->next;
+				head->next = r;
+			}
+		} else {
+			cur_parent->reg = r;
+		}
+	;}
+    break;
+
+
+
+/* Line 1455 of yacc.c  */
+#line 1715 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
+      default: break;
+    }
+  YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+
+  *++yyvsp = yyval;
+
+  /* Now `shift' the result of the reduction.  Determine what state
+     that goes to, based on the state we popped back to and the rule
+     number reduced by.  */
+
+  yyn = yyr1[yyn];
+
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+    yystate = yytable[yystate];
+  else
+    yystate = yydefgoto[yyn - YYNTOKENS];
+
+  goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+  /* If not already recovering from an error, report this error.  */
+  if (!yyerrstatus)
+    {
+      ++yynerrs;
+#if ! YYERROR_VERBOSE
+      yyerror (YY_("syntax error"));
+#else
+      {
+	YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
+	if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
+	  {
+	    YYSIZE_T yyalloc = 2 * yysize;
+	    if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
+	      yyalloc = YYSTACK_ALLOC_MAXIMUM;
+	    if (yymsg != yymsgbuf)
+	      YYSTACK_FREE (yymsg);
+	    yymsg = (char *) YYSTACK_ALLOC (yyalloc);
+	    if (yymsg)
+	      yymsg_alloc = yyalloc;
+	    else
+	      {
+		yymsg = yymsgbuf;
+		yymsg_alloc = sizeof yymsgbuf;
+	      }
+	  }
+
+	if (0 < yysize && yysize <= yymsg_alloc)
+	  {
+	    (void) yysyntax_error (yymsg, yystate, yychar);
+	    yyerror (yymsg);
+	  }
+	else
+	  {
+	    yyerror (YY_("syntax error"));
+	    if (yysize != 0)
+	      goto yyexhaustedlab;
+	  }
+      }
+#endif
+    }
+
+
+
+  if (yyerrstatus == 3)
+    {
+      /* If just tried and failed to reuse lookahead token after an
+	 error, discard it.  */
+
+      if (yychar <= YYEOF)
+	{
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+	}
+      else
+	{
+	  yydestruct ("Error: discarding",
+		      yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
+    }
+
+  /* Else will try to reuse lookahead token after shifting the error
+     token.  */
+  goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
+
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (/*CONSTCOND*/ 0)
+     goto yyerrorlab;
+
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYERROR.  */
+  YYPOPSTACK (yylen);
+  yylen = 0;
+  YY_STACK_PRINT (yyss, yyssp);
+  yystate = *yyssp;
+  goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
+
+  for (;;)
+    {
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
+
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
+
+
+      yydestruct ("Error: popping",
+		  yystos[yystate], yyvsp);
+      YYPOPSTACK (1);
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
+    }
+
+  *++yyvsp = yylval;
+
+
+  /* Shift the error token.  */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here.  |
+`-------------------------------------*/
+yyacceptlab:
+  yyresult = 0;
+  goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here.  |
+`-----------------------------------*/
+yyabortlab:
+  yyresult = 1;
+  goto yyreturn;
+
+#if !defined(yyoverflow) || YYERROR_VERBOSE
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
+  yyresult = 2;
+  /* Fall through.  */
+#endif
+
+yyreturn:
+  if (yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  /* Do not reclaim the symbols of the rule which action triggered
+     this YYABORT or YYACCEPT.  */
+  YYPOPSTACK (yylen);
+  YY_STACK_PRINT (yyss, yyssp);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK (1);
+    }
+#ifndef yyoverflow
+  if (yyss != yyssa)
+    YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+  if (yymsg != yymsgbuf)
+    YYSTACK_FREE (yymsg);
+#endif
+  /* Make sure YYID is used.  */
+  return YYID (yyresult);
+}
+
+
+
+/* Line 1675 of yacc.c  */
+#line 339 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+
+void pass0(FILE *fil, struct device *ptr) {
+	if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used))
+		fprintf(fil, "struct device %s;\n", ptr->name);
+	if ((ptr->type == device) && (ptr->id != 0) && ptr->used)
+		fprintf(fil, "struct device %s;\n", ptr->aliased_name);
+}
+
+void pass1(FILE *fil, struct device *ptr) {
+	if (!ptr->used && (ptr->type == device)) {
+		fprintf(fil, "struct device %s = {\n", ptr->name);
+		fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0");
+		fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link);
+		fprintf(fil, "\t.path = {");
+		fprintf(fil, ptr->path, ptr->path_a, ptr->path_b);
+		fprintf(fil, "},\n");
+		fprintf(fil, "\t.enabled = %d,\n", ptr->enabled);
+		fprintf(fil, "\t.on_mainboard = 1,\n");
+		if (ptr->rescnt > 0) {
+			fprintf(fil, "\t.resources = %d,\n", ptr->rescnt);
+			fprintf(fil, "\t.resource = {\n");
+			struct resource *r = ptr->res;
+			while (r) {
+				fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_");
+				if (r->type == IRQ) fprintf(fil, "IRQ");
+				if (r->type == DRQ) fprintf(fil, "DRQ");
+				if (r->type == IO) fprintf(fil, "IO");
+				fprintf(fil, ", .index=0x%x, .base=0x%x},\n", r->index, r->base);
+				r = r->next;
+			}
+			fprintf(fil, "\t },\n");
+		}
+		int link = 0;
+		fprintf(fil, "\t.link = {\n");
+		if (ptr->multidev) {
+			struct device *d = ptr;
+			while (d) {
+				if (device_match(d, ptr)) {
+					fprintf(fil, "\t\t[%d] = {\n", d->link);
+					fprintf(fil, "\t\t\t.link = %d,\n", d->link);
+					fprintf(fil, "\t\t\t.dev = &%s,\n", d->name);
+					if (d->children)
+						fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name);
+					fprintf(fil, "\t\t},\n");
+					link++;
+				}
+				d = d->next_sibling;
+			}
+		} else {
+			if (ptr->children) {
+				fprintf(fil, "\t\t[0] = {\n");
+				fprintf(fil, "\t\t\t.link = 0,\n");
+				fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name);
+				fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name);
+				fprintf(fil, "\t\t},\n");
+				link++;
+			}
+		}
+		fprintf(fil, "\t},\n");
+		fprintf(fil, "\t.links = %d,\n", link);
+		if (ptr->sibling)
+			fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name);
+		if (ptr->chip->chiph_exists) {
+			fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore);
+			fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id);
+		}
+		if (ptr->nextdev)
+			fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name);
+		fprintf(fil, "};\n");
+	}
+	if ((ptr->type == chip) && (ptr->chiph_exists)) {
+		if (ptr->reg) {
+			fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			struct reg *r = ptr->reg;
+			while (r) {
+				fprintf(fil, "\t.%s = %s,\n", r->key, r->value);
+				r = r->next;
+			}
+			fprintf(fil, "};\n\n");
+		} else {
+			fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+		}
+	}
+}
+
+void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) {
+	do {
+		func(fil, ptr);
+		ptr = ptr->next_sibling;
+	} while (ptr);
+}
+
+struct device mainboard = {
+	.name = "mainboard",
+	.name_underscore = "mainboard",
+	.id = 0,
+	.chip = &mainboard,
+	.type = chip,
+	.chiph_exists = 1,
+	.children = &root
+};
+
+struct device root = {
+	.name = "dev_root",
+	.name_underscore = "dev_root",
+	.id = 0,
+	.chip = &mainboard,
+	.type = device,
+	.path = " .type = DEVICE_PATH_ROOT ",
+	.ops = "&default_dev_ops_root",
+	.parent = &root,
+	.bus = &root,
+	.enabled = 1
+};
+
+int main(int argc, char** argv) {
+	if (argc != 3) {
+		printf("usage: sconfig vendor/mainboard outputdir\n");
+		return 1;
+	}
+	char *mainboard=argv[1];
+	char *outputdir=argv[2];
+	char *devtree=malloc(strlen(mainboard)+30);
+	char *outputc=malloc(strlen(outputdir)+10);
+	sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard);
+	sprintf(outputc, "%s/static.c", outputdir);
+
+	headers.next = malloc(sizeof(struct header));
+	headers.next->name = malloc(strlen(mainboard)+12);
+	headers.next->next = 0;
+	sprintf(headers.next->name, "mainboard/%s", mainboard);
+
+	FILE *filec = fopen(devtree, "r");
+	yyrestart(filec);
+
+	FILE *staticc = fopen(outputc, "w");
+
+	cur_bus = cur_parent = lastdev = head = &root;
+	yyparse();
+	fclose(filec);
+
+	if ((head->type == chip) && (!head->chiph_exists)) {
+		struct device *tmp = head;
+		head = &root;
+		while (head->next != tmp) head = head->next;
+	}
+
+	fprintf(staticc, "#include <device/device.h>\n");
+	fprintf(staticc, "#include <device/pci.h>\n");
+	struct header *h = &headers;
+	while (h->next) {
+		h = h->next;
+		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
+	}
+	fprintf(staticc, "\n/* pass 0 */\n");
+	walk_device_tree(staticc, &root, pass0, NULL);
+	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device **last_dev_p = &%s.next;\n", lastdev->name);
+	walk_device_tree(staticc, &root, pass1, NULL);
+
+	fclose(staticc);
+}
+

Added: trunk/util/sconfig/sconfig.tab.h_shipped
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/sconfig.tab.h_shipped	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,90 @@
+
+/* A Bison parser, made by GNU Bison 2.4.1.  */
+
+/* Skeleton interface for Bison's Yacc-like parsers in C
+   
+      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
+   
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation, either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* As a special exception, you may create a larger work that contains
+   part or all of the Bison parser skeleton and distribute that work
+   under terms of your choice, so long as that work isn't itself a
+   parser generator using the skeleton or a modified version thereof
+   as a parser skeleton.  Alternatively, if you modify or redistribute
+   the parser skeleton itself, you may (at your option) remove this
+   special exception, which will cause the skeleton and the resulting
+   Bison output files to be licensed under the GNU General Public
+   License without this special exception.
+   
+   This special exception was added by the Free Software Foundation in
+   version 2.2 of Bison.  */
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     CHIP = 258,
+     DEVICE = 259,
+     REGISTER = 260,
+     BOOL = 261,
+     BUS = 262,
+     RESOURCE = 263,
+     END = 264,
+     EQUALS = 265,
+     HEX = 266,
+     STRING = 267,
+     PCI = 268,
+     PNP = 269,
+     I2C = 270,
+     APIC = 271,
+     APIC_CLUSTER = 272,
+     PCI_DOMAIN = 273,
+     IRQ = 274,
+     DRQ = 275,
+     IO = 276,
+     NUMBER = 277
+   };
+#endif
+
+
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE
+{
+
+/* Line 1676 of yacc.c  */
+#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+
+	struct device *device;
+	char *string;
+	int number;
+
+
+
+/* Line 1676 of yacc.c  */
+#line 82 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.h_shipped"
+} YYSTYPE;
+# define YYSTYPE_IS_TRIVIAL 1
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+#endif
+
+extern YYSTYPE yylval;
+
+

Added: trunk/util/sconfig/sconfig.y
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/sconfig/sconfig.y	Thu Apr  8 13:37:43 2010	(r5373)
@@ -0,0 +1,499 @@
+%{
+/*
+ * sconfig, coreboot device tree compiler
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *                 written by Patrick Georgi <patrick.georgi at coresystems.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <errno.h>
+
+enum devtype { chip, device };
+
+struct resource;
+struct resource {
+	int type;
+	int index;
+	int base;
+	struct resource *next;
+};
+
+struct reg;
+struct reg {
+	char *key;
+	char *value;
+	struct reg *next;
+};
+
+struct device;
+struct device {
+	int id;
+	int enabled;
+	int used;
+	int multidev;
+	int link;
+	int rescnt;
+	int chiph_exists;
+	char *ops;
+	char *name;
+	char *aliased_name;
+	char *name_underscore;
+	char *path;
+	int path_a;
+	int path_b;
+	int bustype;
+	enum devtype type;
+	struct device *parent;
+	struct device *bus;
+	struct device *next;
+	struct device *nextdev;
+	struct device *children;
+	struct device *latestchild;
+	struct device *next_sibling;
+	struct device *sibling;
+	struct device *chip;
+	struct resource *res;
+	struct reg *reg;
+} *head, *lastdev, *cur_parent, *cur_bus, root;
+
+struct header;
+struct header {
+	char *name;
+	struct header *next;
+} headers;
+
+int devcount = 0;
+
+struct device *new_dev() {
+	struct device *dev = malloc(sizeof(struct device));
+	memset(dev, 0, sizeof(struct device));
+	dev->id = ++devcount;
+	dev->parent = cur_parent;
+	dev->bus = cur_bus;
+	head->next = dev;
+	head = dev;
+	return dev;
+}
+
+int device_match(struct device *a, struct device *b) {
+	if ((a->bustype == b->bustype) && (a->bus == b->bus) && (a->path_a == b->path_a) && (a->path_b == b->path_b))
+		return 1;
+	return 0;
+}
+
+void fold_in(struct device *parent) {
+	struct device *child = parent->children;
+	struct device *latest = 0;
+	while (child != latest) {
+		if (child->children) {
+			if (!latest) latest = child->children;
+			parent->latestchild->next_sibling = child->children;
+			parent->latestchild = child->latestchild;
+		}
+		child = child->next_sibling;
+	}
+}
+
+int yywrap(void) {
+	return 1;
+}
+
+void yyerror (char const *str)
+{
+	fprintf (stderr, "%s\n", str);
+}
+%}
+%union {
+	struct device *device;
+	char *string;
+	int number;
+}
+%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER
+%%
+devtree: devchip {
+	root.next_sibling = root.children;
+	root.next_sibling->next_sibling = root.next_sibling->children;
+
+	struct device *dev = &root;
+	while (dev) {
+		/* skip "chip" elements in children chain */
+		while (dev->children && (dev->children->type == chip)) dev->children = dev->children->children;
+		/* skip "chip" elements and functions of the same device in sibling chain */
+		while (dev->sibling && dev->sibling->used) dev->sibling = dev->sibling->sibling;
+		/* If end of chain, and parent is a chip, move on */
+		if (!dev->sibling && (dev->parent->type == chip)) dev->sibling = dev->parent->sibling;
+		/* skip chips */
+		while (dev->sibling && dev->sibling->type == chip) dev->sibling = dev->sibling->children;
+		/* skip duplicate function elements in nextdev chain */
+		while (dev->nextdev && dev->nextdev->used) dev->nextdev = dev->nextdev->nextdev;
+		dev = dev->next_sibling;
+	}
+	};
+
+devchip: chip | device ;
+
+devices: devices devchip | devices registers | ;
+
+devicesorresources: devicesorresources devchip | devicesorresources resource | ;
+
+chip: CHIP STRING /* == path */ {
+	$<device>$ = new_dev();
+	$<device>$->chiph_exists = 1;
+	$<device>$->name = $<string>2;
+	$<device>$->name_underscore = strdup($<device>$->name);
+	char *c;
+	for (c = $<device>$->name_underscore; *c; c++) {
+		if (*c == '/') *c = '_';
+	}
+	$<device>$->type = chip;
+	$<device>$->chip = $<device>$;
+
+	struct stat st;
+	char *chip_h = malloc(strlen($<string>2)+12);
+	sprintf(chip_h, "src/%s/chip.h", $<string>2);
+	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
+		$<device>$->chiph_exists = 0;
+
+	if (cur_parent->latestchild) {
+		cur_parent->latestchild->next_sibling = $<device>$;
+		cur_parent->latestchild->sibling = $<device>$;
+	}
+	cur_parent->latestchild = $<device>$;
+	if (!cur_parent->children)
+		cur_parent->children = $<device>$;
+
+	cur_parent = $<device>$;
+}
+	devices END {
+	cur_parent = $<device>3->parent;
+
+	fold_in($<device>3);
+
+	if ($<device>3->chiph_exists) {
+		int include_exists = 0;
+		struct header *h = &headers;
+		while (h->next) {
+			int result = strcmp($<device>3->name, h->next->name);
+			if (result == 0) {
+				include_exists = 1;
+				break;
+			}
+			if (result < 0) break;
+			h = h->next;
+		}
+		if (!include_exists) {
+			struct header *tmp = h->next;
+			h->next = malloc(sizeof(struct header));
+			memset(h->next, 0, sizeof(struct header));
+			h->next->name = $<device>3->name;
+			h->next->next = tmp;
+			break;
+		}
+	}
+};
+
+device: DEVICE BUS NUMBER /* == devnum */ BOOL {
+	$<device>$ = new_dev();
+	$<device>$->bustype = $<number>2;
+
+	char *tmp;
+	$<device>$->path_a = strtol(strdup($<string>3), &tmp, 16);
+	if (*tmp == '.') {
+		tmp++;
+		$<device>$->path_b = strtol(tmp, NULL, 16);
+	}
+
+	char *name = malloc(10);
+	sprintf(name, "_dev%d", $<device>$->id);
+	$<device>$->name = name;
+	$<device>$->name_underscore = name; // shouldn't be necessary, but avoid 0-ptr
+	$<device>$->type = device;
+	$<device>$->enabled = $<number>4;
+	$<device>$->chip = $<device>$->parent->chip;
+
+	if (cur_parent->latestchild) {
+		cur_parent->latestchild->next_sibling = $<device>$;
+		cur_parent->latestchild->sibling = $<device>$;
+	}
+	cur_parent->latestchild = $<device>$;
+	if (!cur_parent->children)
+		cur_parent->children = $<device>$;
+
+	lastdev->nextdev = $<device>$;
+	lastdev = $<device>$;
+	if ($<number>2 == PCI) {
+		$<device>$->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}";
+	}
+	if ($<number>2 == PNP) {
+		$<device>$->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}";
+	}
+	if ($<number>2 == I2C) {
+		$<device>$->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}";
+	}
+	if ($<number>2 == APIC) {
+		$<device>$->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}";
+	}
+	if ($<number>2 == APIC_CLUSTER) {
+		$<device>$->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}";
+	}
+	if ($<number>2 == PCI_DOMAIN) {
+		$<device>$->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}";
+	}
+	cur_parent = $<device>$;
+	cur_bus = $<device>$;
+}
+	devicesorresources END {
+	cur_parent = $<device>5->parent;
+	cur_bus = $<device>5->bus;
+
+	fold_in($<device>5);
+
+	struct device *d = $<device>5->children;
+	while (d) {
+		int link = 0;
+		struct device *cmp = d->next_sibling;
+		while (cmp && (cmp->bus == d->bus) && (cmp->path_a == d->path_a) && (cmp->path_b == d->path_b)) {
+			if (cmp->type==device && !cmp->used) {
+				if (device_match(d, cmp)) {
+					d->multidev = 1;
+
+					cmp->aliased_name = malloc(12);
+					sprintf(cmp->aliased_name, "_dev%d", cmp->id);
+					cmp->id = d->id;
+					cmp->name = d->name;
+					cmp->used = 1;
+					cmp->link = ++link;
+				}
+			}
+			cmp = cmp->next_sibling;
+		}
+		d = d->next_sibling;
+	}
+};
+
+resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */
+	{
+		struct resource *r = malloc(sizeof(struct resource));
+		memset (r, 0, sizeof(struct resource));
+		r->type = $<number>1;
+		r->index = strtol($<string>2, NULL, 0);
+		r->base = strtol($<string>4, NULL, 0);
+		if (cur_parent->res) {
+			struct resource *head = cur_parent->res;
+			while (head->next) head = head->next;
+			head->next = r;
+		} else {
+			cur_parent->res = r;
+		}
+		cur_parent->rescnt++;
+	}
+	;
+
+registers: REGISTER STRING /* == regname */ EQUALS STRING /* == regval */
+	{
+		struct reg *r = malloc(sizeof(struct reg));
+		memset (r, 0, sizeof(struct reg));
+		r->key = $<string>2;
+		r->value = $<string>4;
+		if (cur_parent->reg) {
+			struct reg *head = cur_parent->reg;
+			// sorting to be equal to sconfig's behaviour
+			int sort = strcmp(r->key, head->key);
+			if (sort == 0) {
+				printf("ERROR: duplicate 'register' key.\n");
+				exit(1);
+			}
+			if (sort<0) {
+				r->next = head;
+				cur_parent->reg = r;
+			} else {
+				while ((head->next) && (strcmp(head->next->key, r->key)<0)) head = head->next;
+				r->next = head->next;
+				head->next = r;
+			}
+		} else {
+			cur_parent->reg = r;
+		}
+	}
+	;
+
+%%
+void pass0(FILE *fil, struct device *ptr) {
+	if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used))
+		fprintf(fil, "struct device %s;\n", ptr->name);
+	if ((ptr->type == device) && (ptr->id != 0) && ptr->used)
+		fprintf(fil, "struct device %s;\n", ptr->aliased_name);
+}
+
+void pass1(FILE *fil, struct device *ptr) {
+	if (!ptr->used && (ptr->type == device)) {
+		fprintf(fil, "struct device %s = {\n", ptr->name);
+		fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0");
+		fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link);
+		fprintf(fil, "\t.path = {");
+		fprintf(fil, ptr->path, ptr->path_a, ptr->path_b);
+		fprintf(fil, "},\n");
+		fprintf(fil, "\t.enabled = %d,\n", ptr->enabled);
+		fprintf(fil, "\t.on_mainboard = 1,\n");
+		if (ptr->rescnt > 0) {
+			fprintf(fil, "\t.resources = %d,\n", ptr->rescnt);
+			fprintf(fil, "\t.resource = {\n");
+			struct resource *r = ptr->res;
+			while (r) {
+				fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_");
+				if (r->type == IRQ) fprintf(fil, "IRQ");
+				if (r->type == DRQ) fprintf(fil, "DRQ");
+				if (r->type == IO) fprintf(fil, "IO");
+				fprintf(fil, ", .index=0x%x, .base=0x%x},\n", r->index, r->base);
+				r = r->next;
+			}
+			fprintf(fil, "\t },\n");
+		}
+		int link = 0;
+		fprintf(fil, "\t.link = {\n");
+		if (ptr->multidev) {
+			struct device *d = ptr;
+			while (d) {
+				if (device_match(d, ptr)) {
+					fprintf(fil, "\t\t[%d] = {\n", d->link);
+					fprintf(fil, "\t\t\t.link = %d,\n", d->link);
+					fprintf(fil, "\t\t\t.dev = &%s,\n", d->name);
+					if (d->children)
+						fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name);
+					fprintf(fil, "\t\t},\n");
+					link++;
+				}
+				d = d->next_sibling;
+			}
+		} else {
+			if (ptr->children) {
+				fprintf(fil, "\t\t[0] = {\n");
+				fprintf(fil, "\t\t\t.link = 0,\n");
+				fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name);
+				fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name);
+				fprintf(fil, "\t\t},\n");
+				link++;
+			}
+		}
+		fprintf(fil, "\t},\n");
+		fprintf(fil, "\t.links = %d,\n", link);
+		if (ptr->sibling)
+			fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name);
+		if (ptr->chip->chiph_exists) {
+			fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore);
+			fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id);
+		}
+		if (ptr->nextdev)
+			fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name);
+		fprintf(fil, "};\n");
+	}
+	if ((ptr->type == chip) && (ptr->chiph_exists)) {
+		if (ptr->reg) {
+			fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+			struct reg *r = ptr->reg;
+			while (r) {
+				fprintf(fil, "\t.%s = %s,\n", r->key, r->value);
+				r = r->next;
+			}
+			fprintf(fil, "};\n\n");
+		} else {
+			fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id);
+		}
+	}
+}
+
+void walk_device_tree(FILE *fil, struct device *ptr, void (*func)(FILE *, struct device*), struct device *chips) {
+	do {
+		func(fil, ptr);
+		ptr = ptr->next_sibling;
+	} while (ptr);
+}
+
+struct device mainboard = {
+	.name = "mainboard",
+	.name_underscore = "mainboard",
+	.id = 0,
+	.chip = &mainboard,
+	.type = chip,
+	.chiph_exists = 1,
+	.children = &root
+};
+
+struct device root = {
+	.name = "dev_root",
+	.name_underscore = "dev_root",
+	.id = 0,
+	.chip = &mainboard,
+	.type = device,
+	.path = " .type = DEVICE_PATH_ROOT ",
+	.ops = "&default_dev_ops_root",
+	.parent = &root,
+	.bus = &root,
+	.enabled = 1
+};
+
+int main(int argc, char** argv) {
+	if (argc != 3) {
+		printf("usage: sconfig vendor/mainboard outputdir\n");
+		return 1;
+	}
+	char *mainboard=argv[1];
+	char *outputdir=argv[2];
+	char *devtree=malloc(strlen(mainboard)+30);
+	char *outputc=malloc(strlen(outputdir)+10);
+	sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard);
+	sprintf(outputc, "%s/static.c", outputdir);
+
+	headers.next = malloc(sizeof(struct header));
+	headers.next->name = malloc(strlen(mainboard)+12);
+	headers.next->next = 0;
+	sprintf(headers.next->name, "mainboard/%s", mainboard);
+
+	FILE *filec = fopen(devtree, "r");
+	yyrestart(filec);
+
+	FILE *staticc = fopen(outputc, "w");
+
+	cur_bus = cur_parent = lastdev = head = &root;
+	yyparse();
+	fclose(filec);
+
+	if ((head->type == chip) && (!head->chiph_exists)) {
+		struct device *tmp = head;
+		head = &root;
+		while (head->next != tmp) head = head->next;
+	}
+
+	fprintf(staticc, "#include <device/device.h>\n");
+	fprintf(staticc, "#include <device/pci.h>\n");
+	struct header *h = &headers;
+	while (h->next) {
+		h = h->next;
+		fprintf(staticc, "#include \"%s/chip.h\"\n", h->name);
+	}
+	fprintf(staticc, "\n/* pass 0 */\n");
+	walk_device_tree(staticc, &root, pass0, NULL);
+	fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device **last_dev_p = &%s.next;\n", lastdev->name);
+	walk_device_tree(staticc, &root, pass1, NULL);
+
+	fclose(staticc);
+}



From info at coresystems.de  Thu Apr  8 13:56:17 2010
From: info at coresystems.de (coreboot information)
Date: Thu, 08 Apr 2010 13:56:17 +0200
Subject: [coreboot] build service results for r5373
Message-ID: <E1NzqLJ-0003Qb-Rc@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5373 to
the coreboot repository. This caused the following 
changes:

Change Log:
Replace sconfig with a C implementation.
(smaller, faster, standard parser generator, no more python)

Provide precompiled parser, so bison and flex are optional dependencies.

Adapt Makefile and abuild (which uses some sconfig file as a
magic path) to match.

Drop python as dependency from README, and add bison and flex
as optional dependencies

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Build Log:
Compilation of asi:mb_5blgp has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373&device=mb_5blgp&vendor=asi&num=2
Compilation of digitallogic:adl855pc has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373&device=adl855pc&vendor=digitallogic&num=2
Compilation of kontron:kt690 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373&device=kt690&vendor=kontron&num=2
Compilation of tyan:s2850 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373&device=s2850&vendor=tyan&num=2
Compilation of tyan:s2881 has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5373&device=s2881&vendor=tyan&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Apr  8 14:00:35 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 14:00:35 +0200
Subject: [coreboot] [commit] r5374 - in trunk:
	src/mainboard/digitallogic/adl855pc util/sconfig
Message-ID: <E1NzqPT-0004wP-VO@ra.coresystems.de>

Author: oxygene
Date: Thu Apr  8 14:00:35 2010
New Revision: 5374
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5374

Log:
Remove duplicate registers in digitallogic/adl855pc's device tree
Create directories before trying to copy files into them

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb
   trunk/util/sconfig/Makefile.inc

Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb	Thu Apr  8 13:37:43 2010	(r5373)
+++ trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb	Thu Apr  8 14:00:35 2010	(r5374)
@@ -13,8 +13,6 @@
 #			pci 12.0 on end
 			register "enable_usb" = "0"
 			register "enable_native_ide" = "0"
-			register "enable_usb" = "0"
-			register "enable_native_ide" = "0"
 			chip superio/winbond/w83627hf # link 1
                 	        device pnp 2e.0 on      #  Floppy
                 	                 io 0x60 = 0x3f0

Modified: trunk/util/sconfig/Makefile.inc
==============================================================================
--- trunk/util/sconfig/Makefile.inc	Thu Apr  8 13:37:43 2010	(r5373)
+++ trunk/util/sconfig/Makefile.inc	Thu Apr  8 14:00:35 2010	(r5374)
@@ -23,6 +23,7 @@
 $(obj)/util/sconfig/lex.yy.o: $(obj)/util/sconfig/sconfig.tab.h
 
 $(obj)/util/sconfig/%: $(top)/util/sconfig/%_shipped
+	mkdir -p $(dir $@)
 	cp $< $@
 
 $(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj))



From joe at settoplinux.org  Thu Apr  8 14:01:08 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 08 Apr 2010 08:01:08 -0400
Subject: [coreboot] [PATCH] CAR on Intel P6 Series - Support for
	model_6bx
In-Reply-To: <1270708617.3726.13.camel@mattotaupa>
References: <4BBD7305.9060702@settoplinux.org>
	<1270708617.3726.13.camel@mattotaupa>
Message-ID: <4BBDC584.3040302@settoplinux.org>

On 04/08/2010 02:36 AM, Paul Menzel wrote:
> Dear Joseph,
>
>
> Am Donnerstag, den 08.04.2010, 02:09 -0400 schrieb Joseph Smith:
>> 1. This patch adds CAR for Intel P6 series processors.
>> 2. Add support for Micro-FCBGA 479 Celeron and PIII's
>> 3. Add support for model_6bx and microcode updates
>> 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000
>
> sorry for my dump question. Does supporting CAR have any practical
> improvements besides going with coreboot features(?). For example did
> boot time improve?
>
Yes it seems to boot alot faster :-)

>> Build and boot tested (bootlog attached).
>
> It says ?Boot failed.? at the end. But that is due to the payload, is
> not it?
>
Yes that log was without a payload.

> Anyway, I just spotted one indentation error. Someone knowledgeable has
> to do the review. Sorry!
>
> [?]
>
>> Index: src/cpu/intel/model_6bx/cache_as_ram_disable.c
>> ===================================================================
>> --- src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
>> +++ src/cpu/intel/model_6bx/cache_as_ram_disable.c      (revision 0)
>> @@ -0,0 +1,89 @@
>> +/*
>> + * This file is part of the coreboot project.
>> + *
>> + * Copyright (C) 2007-2009 coresystems GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; version 2 of
>> + * the License.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>> + */
>> +
>> +#include "cpu/x86/car/copy_and_run.c"
>> +
>> +/* called from assembler code */
>> +void stage1_main(unsigned long bist);
>> +
>> +/* from romstage.c */
>> +void real_main(unsigned long bist);
>> +
>> +void stage1_main(unsigned long bist)
>> +{
>> +       unsigned int cpu_reset = 0;
>> +
>> +       real_main(bist);
>> +
>> +       /* No servicable parts below this line .. */
>> +#ifdef CAR_DEBUG
>> +        /* Check value of esp to verify if we have enough rom for
>> stack in Cache as RAM */
>> +       unsigned v_esp;
>> +       __asm__ volatile (
>> +               "movl   %%esp, %0\n"
>> +               : "=a" (v_esp)
>> +       );
>> +       printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
>> +#endif
>> +
>> +        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
>> +       printk(BIOS_SPEW, "No cache as ram now - ");
>
> This indentation looks different. I do not know if it is just my MUA.
>
ah thanks.


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org



From info at coresystems.de  Thu Apr  8 14:18:09 2010
From: info at coresystems.de (coreboot information)
Date: Thu, 08 Apr 2010 14:18:09 +0200
Subject: [coreboot] build service results for r5374
Message-ID: <E1NzqgT-0000Ku-8S@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5374 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove duplicate registers in digitallogic/adl855pc's device tree
Create directories before trying to copy files into them

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of asi:mb_5blgp has been fixed
Compilation of digitallogic:adl855pc has been fixed
Compilation of kontron:kt690 has been fixed
Compilation of tyan:s2850 has been fixed
Compilation of tyan:s2881 has been fixed


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Apr  8 14:46:18 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 14:46:18 +0200
Subject: [coreboot] [commit] r5375 - trunk/util/sconfig
Message-ID: <E1Nzr7i-0002qU-Fi@ra.coresystems.de>

Author: oxygene
Date: Thu Apr  8 14:46:18 2010
New Revision: 5375
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5375

Log:
sconfig: Mangle - to _ for struct names, too.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/util/sconfig/sconfig.tab.c_shipped
   trunk/util/sconfig/sconfig.y

Modified: trunk/util/sconfig/sconfig.tab.c_shipped
==============================================================================
--- trunk/util/sconfig/sconfig.tab.c_shipped	Thu Apr  8 14:00:35 2010	(r5374)
+++ trunk/util/sconfig/sconfig.tab.c_shipped	Thu Apr  8 14:46:18 2010	(r5375)
@@ -562,7 +562,7 @@
 static const yytype_uint16 yyrline[] =
 {
        0,   132,   132,   152,   152,   154,   154,   154,   156,   156,
-     156,   158,   158,   214,   214,   293,   311
+     156,   158,   158,   215,   215,   294,   312
 };
 #endif
 
@@ -1511,6 +1511,7 @@
 	char *c;
 	for (c = (yyval.device)->name_underscore; *c; c++) {
 		if (*c == '/') *c = '_';
+		if (*c == '-') *c = '_';
 	}
 	(yyval.device)->type = chip;
 	(yyval.device)->chip = (yyval.device);
@@ -1536,7 +1537,7 @@
   case 12:
 
 /* Line 1455 of yacc.c  */
-#line 186 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 187 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	cur_parent = (yyvsp[(3) - (5)].device)->parent;
 
@@ -1569,7 +1570,7 @@
   case 13:
 
 /* Line 1455 of yacc.c  */
-#line 214 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 215 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	(yyval.device) = new_dev();
 	(yyval.device)->bustype = (yyvsp[(2) - (4)].number);
@@ -1625,7 +1626,7 @@
   case 14:
 
 /* Line 1455 of yacc.c  */
-#line 264 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	cur_parent = (yyvsp[(5) - (7)].device)->parent;
 	cur_bus = (yyvsp[(5) - (7)].device)->bus;
@@ -1659,7 +1660,7 @@
   case 15:
 
 /* Line 1455 of yacc.c  */
-#line 294 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 295 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 		struct resource *r = malloc(sizeof(struct resource));
 		memset (r, 0, sizeof(struct resource));
@@ -1680,7 +1681,7 @@
   case 16:
 
 /* Line 1455 of yacc.c  */
-#line 312 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 313 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 		struct reg *r = malloc(sizeof(struct reg));
 		memset (r, 0, sizeof(struct reg));
@@ -1711,7 +1712,7 @@
 
 
 /* Line 1455 of yacc.c  */
-#line 1715 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
+#line 1716 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
       default: break;
     }
   YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
@@ -1923,7 +1924,7 @@
 
 
 /* Line 1675 of yacc.c  */
-#line 339 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
+#line 340 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
 
 void pass0(FILE *fil, struct device *ptr) {
 	if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used))

Modified: trunk/util/sconfig/sconfig.y
==============================================================================
--- trunk/util/sconfig/sconfig.y	Thu Apr  8 14:00:35 2010	(r5374)
+++ trunk/util/sconfig/sconfig.y	Thu Apr  8 14:46:18 2010	(r5375)
@@ -163,6 +163,7 @@
 	char *c;
 	for (c = $<device>$->name_underscore; *c; c++) {
 		if (*c == '/') *c = '_';
+		if (*c == '-') *c = '_';
 	}
 	$<device>$->type = chip;
 	$<device>$->chip = $<device>$;



From svn at coreboot.org  Thu Apr  8 14:47:36 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 14:47:36 +0200
Subject: [coreboot] [commit] r5376 - trunk/src/mainboard/emulation/qemu-x86
Message-ID: <E1Nzr8y-0004mi-AS@ra.coresystems.de>

Author: oxygene
Date: Thu Apr  8 14:47:35 2010
New Revision: 5376
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5376

Log:
cpu/emulation/qemu-x86 doesn't exist anymore, as this
is folded into mainboard/emulation/qemu-x86. Adapt code.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/emulation/qemu-x86/chip.h
   trunk/src/mainboard/emulation/qemu-x86/devicetree.cb
   trunk/src/mainboard/emulation/qemu-x86/northbridge.c

Modified: trunk/src/mainboard/emulation/qemu-x86/chip.h
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/chip.h	Thu Apr  8 14:46:18 2010	(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/chip.h	Thu Apr  8 14:47:35 2010	(r5376)
@@ -3,9 +3,9 @@
 struct mainboard_config {
 };
 
-struct cpu_emulation_qemu_x86_config
+struct mainboard_emulation_qemu_x86_config
 {
 };
 
-extern struct chip_operations cpu_emulation_qemu_x86_ops;
+extern struct chip_operations mainboard_emulation_qemu_x86_ops;
 

Modified: trunk/src/mainboard/emulation/qemu-x86/devicetree.cb
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/devicetree.cb	Thu Apr  8 14:46:18 2010	(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/devicetree.cb	Thu Apr  8 14:47:35 2010	(r5376)
@@ -1,4 +1,4 @@
-chip cpu/emulation/qemu-x86
+chip mainboard/emulation/qemu-x86
 	device pci_domain 0 on 
 		device pci 0.0 on end
 

Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/northbridge.c	Thu Apr  8 14:46:18 2010	(r5375)
+++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c	Thu Apr  8 14:47:35 2010	(r5376)
@@ -152,7 +152,7 @@
 	}
 }
 
-struct chip_operations cpu_emulation_qemu_x86_ops = {
+struct chip_operations mainboard_emulation_qemu_x86_ops = {
 	CHIP_NAME("QEMU Northbridge")
 	.enable_dev = enable_dev,
 };



From svn at coreboot.org  Thu Apr  8 14:59:42 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 14:59:42 +0200
Subject: [coreboot] [commit] r5377 - trunk/util/sconfig
Message-ID: <E1NzrKg-0007fg-15@ra.coresystems.de>

Author: oxygene
Date: Thu Apr  8 14:59:41 2010
New Revision: 5377
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5377

Log:
Remove #line statements in processed parser source,
to avoid clutter in revision history.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>

Modified:
   trunk/util/sconfig/Makefile.inc
   trunk/util/sconfig/lex.yy.c_shipped
   trunk/util/sconfig/sconfig.tab.c_shipped
   trunk/util/sconfig/sconfig.tab.h_shipped

Modified: trunk/util/sconfig/Makefile.inc
==============================================================================
--- trunk/util/sconfig/Makefile.inc	Thu Apr  8 14:47:35 2010	(r5376)
+++ trunk/util/sconfig/Makefile.inc	Thu Apr  8 14:59:41 2010	(r5377)
@@ -11,12 +11,12 @@
 
 ifdef SCONFIG_GENPARSER
 $(top)/util/sconfig/lex.yy.c_shipped: $(top)/util/sconfig/sconfig.l
-	flex -o $@ $<
+	flex -L -o $@ $<
 
 # the .c rule also creates .h
 $(top)/util/sconfig/sconfig.tab.h_shipped: $(top)/util/sconfig/sconfig.tab.c_shipped
 $(top)/util/sconfig/sconfig.tab.c_shipped: $(top)/util/sconfig/sconfig.y
-	bison --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $<
+	bison -l --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $<
 
 endif
 

Modified: trunk/util/sconfig/lex.yy.c_shipped
==============================================================================
--- trunk/util/sconfig/lex.yy.c_shipped	Thu Apr  8 14:47:35 2010	(r5376)
+++ trunk/util/sconfig/lex.yy.c_shipped	Thu Apr  8 14:59:41 2010	(r5377)
@@ -1,6 +1,5 @@
-#line 2 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
 
-#line 4 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
+#line 3 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
 
 #define  YY_INT_ALIGNED short int
 
@@ -508,8 +507,6 @@
 #define YY_MORE_ADJ 0
 #define YY_RESTORE_YY_MORE_OFFSET
 char *yytext;
-#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
-#line 2 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 /*
  * sconfig, coreboot device tree compiler
  *
@@ -533,7 +530,6 @@
 #include "sconfig.tab.h"
 
 int linenum = 0;
-#line 537 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
 
 #define INITIAL 0
 
@@ -715,10 +711,6 @@
 	register char *yy_cp, *yy_bp;
 	register int yy_act;
     
-#line 27 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
-
-#line 721 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
-
 	if ( !(yy_init) )
 		{
 		(yy_init) = 1;
@@ -802,133 +794,107 @@
 
 case 1:
 YY_RULE_SETUP
-#line 28 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {}
 	YY_BREAK
 case 2:
 /* rule 2 can match eol */
 YY_RULE_SETUP
-#line 29 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {linenum++;}
 	YY_BREAK
 case 3:
 /* rule 3 can match eol */
 YY_RULE_SETUP
-#line 30 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {linenum++;}
 	YY_BREAK
 case 4:
 YY_RULE_SETUP
-#line 31 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {return(CHIP);}
 	YY_BREAK
 case 5:
 YY_RULE_SETUP
-#line 32 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {return(DEVICE);}
 	YY_BREAK
 case 6:
 YY_RULE_SETUP
-#line 33 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {return(REGISTER);}
 	YY_BREAK
 case 7:
 YY_RULE_SETUP
-#line 34 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=1; return(BOOL);}
 	YY_BREAK
 case 8:
 YY_RULE_SETUP
-#line 35 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=0; return(BOOL);}
 	YY_BREAK
 case 9:
 YY_RULE_SETUP
-#line 36 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=PCI; return(BUS);}
 	YY_BREAK
 case 10:
 YY_RULE_SETUP
-#line 37 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=PNP; return(BUS);}
 	YY_BREAK
 case 11:
 YY_RULE_SETUP
-#line 38 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=I2C; return(BUS);}
 	YY_BREAK
 case 12:
 YY_RULE_SETUP
-#line 39 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=APIC; return(BUS);}
 	YY_BREAK
 case 13:
 YY_RULE_SETUP
-#line 40 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=APIC_CLUSTER; return(BUS);}
 	YY_BREAK
 case 14:
 YY_RULE_SETUP
-#line 41 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=PCI_DOMAIN; return(BUS);}
 	YY_BREAK
 case 15:
 YY_RULE_SETUP
-#line 42 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=IRQ; return(RESOURCE);}
 	YY_BREAK
 case 16:
 YY_RULE_SETUP
-#line 43 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=DRQ; return(RESOURCE);}
 	YY_BREAK
 case 17:
 YY_RULE_SETUP
-#line 44 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.number=IO; return(RESOURCE);}
 	YY_BREAK
 case 18:
 YY_RULE_SETUP
-#line 45 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {return(END);}
 	YY_BREAK
 case 19:
 YY_RULE_SETUP
-#line 46 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {return(EQUALS);}
 	YY_BREAK
 case 20:
 YY_RULE_SETUP
-#line 47 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 21:
 YY_RULE_SETUP
-#line 48 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 22:
 YY_RULE_SETUP
-#line 49 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
 	YY_BREAK
 case 23:
 /* rule 23 can match eol */
 YY_RULE_SETUP
-#line 50 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
 	YY_BREAK
 case 24:
 YY_RULE_SETUP
-#line 51 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
 	YY_BREAK
 case 25:
 YY_RULE_SETUP
-#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
 ECHO;
 	YY_BREAK
-#line 932 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped"
 case YY_STATE_EOF(INITIAL):
 	yyterminate();
 
@@ -1926,7 +1892,3 @@
 
 #define YYTABLES_NAME "yytables"
 
-#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l"
-
-
-

Modified: trunk/util/sconfig/sconfig.tab.c_shipped
==============================================================================
--- trunk/util/sconfig/sconfig.tab.c_shipped	Thu Apr  8 14:47:35 2010	(r5376)
+++ trunk/util/sconfig/sconfig.tab.c_shipped	Thu Apr  8 14:59:41 2010	(r5377)
@@ -67,8 +67,6 @@
 
 /* Copy the first part of user declarations.  */
 
-/* Line 189 of yacc.c  */
-#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
 
 /*
  * sconfig, coreboot device tree compiler
@@ -194,8 +192,6 @@
 }
 
 
-/* Line 189 of yacc.c  */
-#line 199 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
 
 /* Enabling traces.  */
 #ifndef YYDEBUG
@@ -251,8 +247,6 @@
 typedef union YYSTYPE
 {
 
-/* Line 214 of yacc.c  */
-#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
 
 	struct device *device;
 	char *string;
@@ -260,8 +254,6 @@
 
 
 
-/* Line 214 of yacc.c  */
-#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
@@ -272,8 +264,6 @@
 /* Copy the second part of user declarations.  */
 
 
-/* Line 264 of yacc.c  */
-#line 277 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
 
 #ifdef short
 # undef short
@@ -1476,8 +1466,6 @@
     {
         case 2:
 
-/* Line 1455 of yacc.c  */
-#line 132 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	root.next_sibling = root.children;
 	root.next_sibling->next_sibling = root.next_sibling->children;
@@ -1501,8 +1489,6 @@
 
   case 11:
 
-/* Line 1455 of yacc.c  */
-#line 158 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	(yyval.device) = new_dev();
 	(yyval.device)->chiph_exists = 1;
@@ -1536,8 +1522,6 @@
 
   case 12:
 
-/* Line 1455 of yacc.c  */
-#line 187 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	cur_parent = (yyvsp[(3) - (5)].device)->parent;
 
@@ -1569,8 +1553,6 @@
 
   case 13:
 
-/* Line 1455 of yacc.c  */
-#line 215 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	(yyval.device) = new_dev();
 	(yyval.device)->bustype = (yyvsp[(2) - (4)].number);
@@ -1625,8 +1607,6 @@
 
   case 14:
 
-/* Line 1455 of yacc.c  */
-#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 	cur_parent = (yyvsp[(5) - (7)].device)->parent;
 	cur_bus = (yyvsp[(5) - (7)].device)->bus;
@@ -1659,8 +1639,6 @@
 
   case 15:
 
-/* Line 1455 of yacc.c  */
-#line 295 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 		struct resource *r = malloc(sizeof(struct resource));
 		memset (r, 0, sizeof(struct resource));
@@ -1680,8 +1658,6 @@
 
   case 16:
 
-/* Line 1455 of yacc.c  */
-#line 313 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
     {
 		struct reg *r = malloc(sizeof(struct reg));
 		memset (r, 0, sizeof(struct reg));
@@ -1711,8 +1687,6 @@
 
 
 
-/* Line 1455 of yacc.c  */
-#line 1716 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped"
       default: break;
     }
   YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
@@ -1923,8 +1897,6 @@
 
 
 
-/* Line 1675 of yacc.c  */
-#line 340 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
 
 void pass0(FILE *fil, struct device *ptr) {
 	if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used))

Modified: trunk/util/sconfig/sconfig.tab.h_shipped
==============================================================================
--- trunk/util/sconfig/sconfig.tab.h_shipped	Thu Apr  8 14:47:35 2010	(r5376)
+++ trunk/util/sconfig/sconfig.tab.h_shipped	Thu Apr  8 14:59:41 2010	(r5377)
@@ -68,8 +68,6 @@
 typedef union YYSTYPE
 {
 
-/* Line 1676 of yacc.c  */
-#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y"
 
 	struct device *device;
 	char *string;
@@ -77,8 +75,6 @@
 
 
 
-/* Line 1676 of yacc.c  */
-#line 82 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.h_shipped"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */



From svn at coreboot.org  Thu Apr  8 15:16:38 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 15:16:38 +0200
Subject: [coreboot] [commit] r5378 - in trunk: . util/sconfig
Message-ID: <E1Nzrb4-0005uK-W2@ra.coresystems.de>

Author: stepan
Date: Thu Apr  8 15:16:32 2010
New Revision: 5378
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5378

Log:
output cosmetics

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/Makefile
   trunk/util/sconfig/Makefile.inc

Modified: trunk/Makefile
==============================================================================
--- trunk/Makefile	Thu Apr  8 14:59:41 2010	(r5377)
+++ trunk/Makefile	Thu Apr  8 15:16:32 2010	(r5378)
@@ -150,6 +150,7 @@
 # needed objects that every mainboard uses 
 # Creation of these is architecture and mainboard independent
 $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb  $(obj)/util/sconfig/sconfig
+	@printf "    SCONFIG    $(subst $(src)/,,$(<))\n"
 	mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
 	$(obj)/util/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR)
 

Modified: trunk/util/sconfig/Makefile.inc
==============================================================================
--- trunk/util/sconfig/Makefile.inc	Thu Apr  8 14:59:41 2010	(r5377)
+++ trunk/util/sconfig/Makefile.inc	Thu Apr  8 15:16:32 2010	(r5378)
@@ -27,5 +27,5 @@
 	cp $< $@
 
 $(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj))
-	printf "    HOSTCXX    $(subst $(obj)/,,$(@)) (link)\n"
-	$(HOSTCXX) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj))
+	printf "    HOSTCC     $(subst $(obj)/,,$(@)) (link)\n"
+	$(HOSTCC) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj))



From info at coresystems.de  Thu Apr  8 15:46:52 2010
From: info at coresystems.de (coreboot information)
Date: Thu, 08 Apr 2010 15:46:52 +0200
Subject: [coreboot] build service results for r5377
Message-ID: <E1Nzs4K-0007R4-Vm@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "oxygene" checked in revision 5377 to
the coreboot repository. This caused the following 
changes:

Change Log:
Remove #line statements in processed parser source,
to avoid clutter in revision history.

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>


Build Log:
Compilation of amd:norwich has been broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5377&device=norwich&vendor=amd&num=2


If something broke during this checkin please be a pain 
in oxygene's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From info at coresystems.de  Thu Apr  8 16:12:43 2010
From: info at coresystems.de (coreboot information)
Date: Thu, 08 Apr 2010 16:12:43 +0200
Subject: [coreboot] build service results for r5378
Message-ID: <E1NzsTL-0004lT-Bn@ra.coresystems.de>

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "stepan" checked in revision 5378 to
the coreboot repository. This caused the following 
changes:

Change Log:
output cosmetics

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Build Log:
Compilation of amd:norwich has been fixed


If something broke during this checkin please be a pain 
in stepan's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system





From svn at coreboot.org  Thu Apr  8 17:02:40 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 17:02:40 +0200
Subject: [coreboot] [commit] r5379 - in trunk/src: . northbridge/amd
	northbridge/amd/amdht
Message-ID: <E1NztFg-00015n-C1@ra.coresystems.de>

Author: myles
Date: Thu Apr  8 17:02:39 2010
New Revision: 5379
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5379

Log:
Move Kconfig for HT limits to northbridge/amd/Kconfig.

Guard the code with CONFIG_EXPERT to remove warnings.

Make it only show up for fam10, since it isn't implemented for K8 yet.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/Kconfig
   trunk/src/northbridge/amd/Kconfig
   trunk/src/northbridge/amd/amdht/h3finit.c

Modified: trunk/src/Kconfig
==============================================================================
--- trunk/src/Kconfig	Thu Apr  8 15:16:32 2010	(r5378)
+++ trunk/src/Kconfig	Thu Apr  8 17:02:39 2010	(r5379)
@@ -90,96 +90,6 @@
 comment "CPU"
 source src/cpu/Kconfig
 comment "Northbridge"
-
-menu "HyperTransport setup"
-	depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
-
-choice
-	prompt "HyperTransport frequency"
-	default LIMIT_HT_SPEED_AUTO
-	help
-	  This option sets the maximum permissible HyperTransport link
-	  frequency.
-
-	  Use of this option will only limit the autodetected HT frequency.
-	  It will not (and cannot) increase the frequency beyond the
-	  autodetected limits.
-
-	  This is primarily used to work around poorly designed or laid out
-	  HT traces on certain motherboards.
-
-config LIMIT_HT_SPEED_200
-	bool "Limit HT frequency to 200MHz"
-config LIMIT_HT_SPEED_400
-	bool "Limit HT frequency to 400MHz"
-config LIMIT_HT_SPEED_600
-	bool "Limit HT frequency to 600MHz"
-config LIMIT_HT_SPEED_800
-	bool "Limit HT frequency to 800MHz"
-config LIMIT_HT_SPEED_1000
-	bool "Limit HT frequency to 1.0GHz"
-config LIMIT_HT_SPEED_1200
-	bool "Limit HT frequency to 1.2GHz"
-config LIMIT_HT_SPEED_1400
-	bool "Limit HT frequency to 1.4GHz"
-config LIMIT_HT_SPEED_1600
-	bool "Limit HT frequency to 1.6GHz"
-config LIMIT_HT_SPEED_1800
-	bool "Limit HT frequency to 1.8GHz"
-config LIMIT_HT_SPEED_2000
-	bool "Limit HT frequency to 2.0GHz"
-config LIMIT_HT_SPEED_2200
-	bool "Limit HT frequency to 2.2GHz"
-config LIMIT_HT_SPEED_2400
-	bool "Limit HT frequency to 2.4GHz"
-config LIMIT_HT_SPEED_2600
-	bool "Limit HT frequency to 2.6GHz"
-config LIMIT_HT_SPEED_AUTO
-	bool "Autodetect HT frequency"
-endchoice
-
-choice
-	prompt "HyperTransport downlink width"
-	default LIMIT_HT_DOWN_WIDTH_16
-	help
-	  This option sets the maximum permissible HyperTransport
-	  downlink width.
-
-	  Use of this option will only limit the autodetected HT width.
-	  It will not (and cannot) increase the width beyond the autodetected
-	  limits.
-
-	  This is primarily used to work around poorly designed or laid out HT
-	  traces on certain motherboards.
-
-config LIMIT_HT_DOWN_WIDTH_8
-	bool "8 bits"
-config LIMIT_HT_DOWN_WIDTH_16
-	bool "16 bits"
-endchoice
-
-choice
-	prompt "HyperTransport uplink width"
-	default LIMIT_HT_UP_WIDTH_16
-	help
-	  This option sets the maximum permissible HyperTransport
-	  uplink width.
-
-	  Use of this option will only limit the autodetected HT width.
-	  It will not (and cannot) increase the width beyond the autodetected
-	  limits.
-
-	  This is primarily used to work around poorly designed or laid out HT
-	  traces on certain motherboards.
-
-config LIMIT_HT_UP_WIDTH_8
-	bool "8 bits"
-config LIMIT_HT_UP_WIDTH_16
-	bool "16 bits"
-endchoice
-
-endmenu
-
 source src/northbridge/Kconfig
 comment "Southbridge"
 source src/southbridge/Kconfig

Modified: trunk/src/northbridge/amd/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/Kconfig	Thu Apr  8 15:16:32 2010	(r5378)
+++ trunk/src/northbridge/amd/Kconfig	Thu Apr  8 17:02:39 2010	(r5379)
@@ -3,3 +3,92 @@
 source src/northbridge/amd/gx2/Kconfig
 source src/northbridge/amd/amdfam10/Kconfig
 source src/northbridge/amd/lx/Kconfig
+menu "HyperTransport setup"
+	#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
+	depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
+
+choice
+	prompt "HyperTransport frequency"
+	default LIMIT_HT_SPEED_AUTO
+	help
+	  This option sets the maximum permissible HyperTransport link
+	  frequency.
+
+	  Use of this option will only limit the autodetected HT frequency.
+	  It will not (and cannot) increase the frequency beyond the
+	  autodetected limits.
+
+	  This is primarily used to work around poorly designed or laid out
+	  HT traces on certain motherboards.
+
+config LIMIT_HT_SPEED_200
+	bool "Limit HT frequency to 200MHz"
+config LIMIT_HT_SPEED_400
+	bool "Limit HT frequency to 400MHz"
+config LIMIT_HT_SPEED_600
+	bool "Limit HT frequency to 600MHz"
+config LIMIT_HT_SPEED_800
+	bool "Limit HT frequency to 800MHz"
+config LIMIT_HT_SPEED_1000
+	bool "Limit HT frequency to 1.0GHz"
+config LIMIT_HT_SPEED_1200
+	bool "Limit HT frequency to 1.2GHz"
+config LIMIT_HT_SPEED_1400
+	bool "Limit HT frequency to 1.4GHz"
+config LIMIT_HT_SPEED_1600
+	bool "Limit HT frequency to 1.6GHz"
+config LIMIT_HT_SPEED_1800
+	bool "Limit HT frequency to 1.8GHz"
+config LIMIT_HT_SPEED_2000
+	bool "Limit HT frequency to 2.0GHz"
+config LIMIT_HT_SPEED_2200
+	bool "Limit HT frequency to 2.2GHz"
+config LIMIT_HT_SPEED_2400
+	bool "Limit HT frequency to 2.4GHz"
+config LIMIT_HT_SPEED_2600
+	bool "Limit HT frequency to 2.6GHz"
+config LIMIT_HT_SPEED_AUTO
+	bool "Autodetect HT frequency"
+endchoice
+
+choice
+	prompt "HyperTransport downlink width"
+	default LIMIT_HT_DOWN_WIDTH_16
+	help
+	  This option sets the maximum permissible HyperTransport
+	  downlink width.
+
+	  Use of this option will only limit the autodetected HT width.
+	  It will not (and cannot) increase the width beyond the autodetected
+	  limits.
+
+	  This is primarily used to work around poorly designed or laid out HT
+	  traces on certain motherboards.
+
+config LIMIT_HT_DOWN_WIDTH_8
+	bool "8 bits"
+config LIMIT_HT_DOWN_WIDTH_16
+	bool "16 bits"
+endchoice
+
+choice
+	prompt "HyperTransport uplink width"
+	default LIMIT_HT_UP_WIDTH_16
+	help
+	  This option sets the maximum permissible HyperTransport
+	  uplink width.
+
+	  Use of this option will only limit the autodetected HT width.
+	  It will not (and cannot) increase the width beyond the autodetected
+	  limits.
+
+	  This is primarily used to work around poorly designed or laid out HT
+	  traces on certain motherboards.
+
+config LIMIT_HT_UP_WIDTH_8
+	bool "8 bits"
+config LIMIT_HT_UP_WIDTH_16
+	bool "16 bits"
+endchoice
+
+endmenu

Modified: trunk/src/northbridge/amd/amdht/h3finit.c
==============================================================================
--- trunk/src/northbridge/amd/amdht/h3finit.c	Thu Apr  8 15:16:32 2010	(r5378)
+++ trunk/src/northbridge/amd/amdht/h3finit.c	Thu Apr  8 17:02:39 2010	(r5379)
@@ -1327,47 +1327,47 @@
 
 	for (i = 0; i < pDat->TotalLinks*2; i += 2)
 	{
-#if CONFIG_LIMIT_HT_SPEED_200
+#if CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_200
 		cbPCBFreqLimit = 0x0001;
-#elif CONFIG_LIMIT_HT_SPEED_300
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_300
 		cbPCBFreqLimit = 0x0003;
-#elif CONFIG_LIMIT_HT_SPEED_400
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_400
 		cbPCBFreqLimit = 0x0007;
-#elif CONFIG_LIMIT_HT_SPEED_500
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_500
 		cbPCBFreqLimit = 0x000F;
-#elif CONFIG_LIMIT_HT_SPEED_600
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_600
 		cbPCBFreqLimit = 0x001F;
-#elif CONFIG_LIMIT_HT_SPEED_800
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_800
 		cbPCBFreqLimit = 0x003F;
-#elif CONFIG_LIMIT_HT_SPEED_1000
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1000
 		cbPCBFreqLimit = 0x007F;
-#elif CONFIG_LIMIT_HT_SPEED_1200
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1200
 		cbPCBFreqLimit = 0x00FF;
-#elif CONFIG_LIMIT_HT_SPEED_1400
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1400
 		cbPCBFreqLimit = 0x01FF;
-#elif CONFIG_LIMIT_HT_SPEED_1600
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1600
 		cbPCBFreqLimit = 0x03FF;
-#elif CONFIG_LIMIT_HT_SPEED_1800
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1800
 		cbPCBFreqLimit = 0x07FF;
-#elif CONFIG_LIMIT_HT_SPEED_2000
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2000
 		cbPCBFreqLimit = 0x0FFF;
-#elif CONFIG_LIMIT_HT_SPEED_2200
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2200
 		cbPCBFreqLimit = 0x1FFF;
-#elif CONFIG_LIMIT_HT_SPEED_2400
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2400
 		cbPCBFreqLimit = 0x3FFF;
-#elif CONFIG_LIMIT_HT_SPEED_2600
+#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2600
 		cbPCBFreqLimit = 0x7FFF;
 #else
 		cbPCBFreqLimit = 0xFFFF;		// Maximum allowed by autoconfiguration
 #endif
 
-#if CONFIG_LIMIT_HT_DOWN_WIDTH_8
+#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8
 		cbPCBABDownstreamWidth = 8;
 #else
 		cbPCBABDownstreamWidth = 16;
 #endif
 
-#if CONFIG_LIMIT_HT_UP_WIDTH_8
+#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8
 		cbPCBBAUpstreamWidth = 8;
 #else
 		cbPCBBAUpstreamWidth = 16;



From svn at coreboot.org  Thu Apr  8 17:06:45 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 17:06:45 +0200
Subject: [coreboot] [commit] r5380 - in trunk/src: cpu/amd/dualcore
	cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore
	mainboard/amd/db800 mainboard/amd/dbm690t
	mainboard/amd/mahogany mainboard/amd/mahogany_fam10 ...
Message-ID: <E1NztJd-0007HH-L6@ra.coresystems.de>

Author: myles
Date: Thu Apr  8 17:06:44 2010
New Revision: 5380
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5380

Log:
Replace dual_core and quad_core CMOS (nvram) options with multi_core.  Fix some white space.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/cpu/amd/dualcore/amd_sibling.c
   trunk/src/cpu/amd/dualcore/dualcore.c
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_fxx/init_cpus.c
   trunk/src/cpu/amd/quadcore/amd_sibling.c
   trunk/src/cpu/amd/quadcore/quadcore.c
   trunk/src/mainboard/amd/db800/cmos.layout
   trunk/src/mainboard/amd/dbm690t/cmos.layout
   trunk/src/mainboard/amd/mahogany/cmos.layout
   trunk/src/mainboard/amd/mahogany_fam10/cmos.layout
   trunk/src/mainboard/amd/norwich/cmos.layout
   trunk/src/mainboard/amd/pistachio/cmos.layout
   trunk/src/mainboard/amd/rumba/cmos.layout
   trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout
   trunk/src/mainboard/arima/hdama/cmos.layout
   trunk/src/mainboard/artecgroup/dbe61/cmos.layout
   trunk/src/mainboard/asrock/939a785gmh/cmos.layout
   trunk/src/mainboard/asus/a8n_e/cmos.layout
   trunk/src/mainboard/asus/a8v-e_se/cmos.layout
   trunk/src/mainboard/asus/m2v-mx_se/cmos.layout
   trunk/src/mainboard/asus/mew-vm/cmos.layout
   trunk/src/mainboard/bcom/winnetp680/cmos.layout
   trunk/src/mainboard/broadcom/blast/cmos.layout
   trunk/src/mainboard/dell/s1850/cmos.layout
   trunk/src/mainboard/digitallogic/adl855pc/cmos.layout
   trunk/src/mainboard/digitallogic/msm586seg/cmos.layout
   trunk/src/mainboard/digitallogic/msm800sev/cmos.layout
   trunk/src/mainboard/eaglelion/5bcm/cmos.layout
   trunk/src/mainboard/emulation/qemu-x86/cmos.layout
   trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
   trunk/src/mainboard/gigabyte/m57sli/cmos.layout
   trunk/src/mainboard/hp/dl145_g3/cmos.layout
   trunk/src/mainboard/ibm/e325/cmos.layout
   trunk/src/mainboard/ibm/e326/cmos.layout
   trunk/src/mainboard/iei/juki-511p/cmos.layout
   trunk/src/mainboard/iei/nova4899r/cmos.layout
   trunk/src/mainboard/intel/jarrell/cmos.layout
   trunk/src/mainboard/intel/xe7501devkit/cmos.layout
   trunk/src/mainboard/iwill/dk8_htx/cmos.layout
   trunk/src/mainboard/iwill/dk8s2/cmos.layout
   trunk/src/mainboard/iwill/dk8x/cmos.layout
   trunk/src/mainboard/jetway/j7f24/cmos.layout
   trunk/src/mainboard/kontron/kt690/cmos.layout
   trunk/src/mainboard/lippert/frontrunner/cmos.layout
   trunk/src/mainboard/msi/ms7135/cmos.layout
   trunk/src/mainboard/msi/ms7260/cmos.layout
   trunk/src/mainboard/msi/ms9185/cmos.layout
   trunk/src/mainboard/msi/ms9282/cmos.layout
   trunk/src/mainboard/msi/ms9652_fam10/cmos.layout
   trunk/src/mainboard/newisys/khepri/cmos.layout
   trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout
   trunk/src/mainboard/olpc/btest/cmos.layout
   trunk/src/mainboard/olpc/rev_a/cmos.layout
   trunk/src/mainboard/pcengines/alix1c/cmos.layout
   trunk/src/mainboard/sunw/ultra40/cmos.layout
   trunk/src/mainboard/supermicro/h8dme/cmos.layout
   trunk/src/mainboard/supermicro/h8dmr/cmos.layout
   trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout
   trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout
   trunk/src/mainboard/supermicro/x6dai_g/cmos.layout
   trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout
   trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout
   trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout
   trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout
   trunk/src/mainboard/technexion/tim5690/cmos.layout
   trunk/src/mainboard/technexion/tim8690/cmos.layout
   trunk/src/mainboard/technologic/ts5300/cmos.layout
   trunk/src/mainboard/tyan/s2735/cmos.layout
   trunk/src/mainboard/tyan/s2850/cmos.layout
   trunk/src/mainboard/tyan/s2875/cmos.layout
   trunk/src/mainboard/tyan/s2880/cmos.layout
   trunk/src/mainboard/tyan/s2881/cmos.layout
   trunk/src/mainboard/tyan/s2882/cmos.layout
   trunk/src/mainboard/tyan/s2885/cmos.layout
   trunk/src/mainboard/tyan/s2891/cmos.layout
   trunk/src/mainboard/tyan/s2892/cmos.layout
   trunk/src/mainboard/tyan/s2895/cmos.layout
   trunk/src/mainboard/tyan/s2912/cmos.layout
   trunk/src/mainboard/tyan/s2912_fam10/cmos.layout
   trunk/src/mainboard/tyan/s4880/cmos.layout
   trunk/src/mainboard/tyan/s4882/cmos.layout
   trunk/src/mainboard/via/epia-cn/cmos.layout
   trunk/src/mainboard/via/epia-m/cmos.layout
   trunk/src/mainboard/via/epia-m700/cmos.layout
   trunk/src/mainboard/via/epia-n/cmos.layout
   trunk/src/mainboard/via/epia/cmos.layout
   trunk/src/mainboard/winent/pl6064/cmos.layout
   trunk/src/northbridge/amd/amdfam10/northbridge.c
   trunk/src/northbridge/amd/amdk8/coherent_ht.c
   trunk/src/northbridge/amd/amdk8/northbridge.c

Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c
==============================================================================
--- trunk/src/cpu/amd/dualcore/amd_sibling.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/dualcore/amd_sibling.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -61,7 +61,7 @@
 	unsigned nb_cfg_54;
         int bsp_apic_id = lapicid(); // bsp apicid
 
-        get_option(&disable_siblings, "dual_core");
+        get_option(&disable_siblings, "multi_core");
 
         //get the nodes number
         dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
@@ -129,7 +129,7 @@
 	/* On the bootstrap processor see if I want sibling cpus enabled */
 	if (first_time) {
 		first_time = 0;
-		get_option(&disable_siblings, "dual_core");
+		get_option(&disable_siblings, "multi_core");
 	}
 	result = cpuid(0x80000008);
 	/* See how many sibling cpus we have */

Modified: trunk/src/cpu/amd/dualcore/dualcore.c
==============================================================================
--- trunk/src/cpu/amd/dualcore/dualcore.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/dualcore/dualcore.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -57,8 +57,8 @@
 	unsigned nodeid;
 
 	if (CONFIG_HAVE_OPTION_TABLE &&
-	    read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0)  {
-		return; // disable dual_core
+	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)  {
+		return; // disable multi_core
 	}
 
         nodes = get_nodes();

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -131,7 +131,7 @@
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
 
 #if CONFIG_LOGICAL_CPUS == 1
-	if(read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) { // 0 mean quad core
+	if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
 		disable_siblings = 1;
 	}
 #endif

Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -57,7 +57,7 @@
 
         disable_siblings = !CONFIG_LOGICAL_CPUS;
 #if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
-        if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
+        if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
                 disable_siblings = 1;
         }
 #endif

Modified: trunk/src/cpu/amd/quadcore/amd_sibling.c
==============================================================================
--- trunk/src/cpu/amd/quadcore/amd_sibling.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/quadcore/amd_sibling.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -82,7 +82,7 @@
 
 	u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
 
-	get_option(&disable_siblings, "quad_core");
+	get_option(&disable_siblings, "multi_core");
 
 	siblings = get_max_siblings(sysconf.nodes);
 

Modified: trunk/src/cpu/amd/quadcore/quadcore.c
==============================================================================
--- trunk/src/cpu/amd/quadcore/quadcore.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/cpu/amd/quadcore/quadcore.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -86,8 +86,8 @@
 	u32 nodes;
 	u32 nodeid;
 
-	// disable quad_core
-	if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0)  {
+	// disable multi_core
+	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)  {
 		printk(BIOS_DEBUG, "Skip additional core init\n");
 		return;
 	}

Modified: trunk/src/mainboard/amd/db800/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/db800/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/db800/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/amd/dbm690t/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/dbm690t/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/amd/mahogany/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/mahogany/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/mahogany/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/amd/mahogany_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/mahogany_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/amd/norwich/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/norwich/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/norwich/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,8 +35,8 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
-440	     1	     e	     0	      dcon_present
+432          8       h       0        boot_countdown
+440          1       e       0        dcon_present
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/amd/pistachio/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/pistachio/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/pistachio/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/amd/rumba/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/rumba/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/rumba/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/arima/hdama/cmos.layout
==============================================================================
--- trunk/src/mainboard/arima/hdama/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/arima/hdama/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/artecgroup/dbe61/cmos.layout
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/artecgroup/dbe61/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/asrock/939a785gmh/cmos.layout
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/asus/a8n_e/cmos.layout
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/asus/a8n_e/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -31,7 +31,7 @@
     395 1 e 1 hw_scrubber
     396 1 e 1 interleave_chip_selects
     397 2 e 8 max_mem_clock
-    399 1 e 2 dual_core
+    399 1 e 2 multi_core
     400 1 e 1 power_on_after_fail
     412 4 e 6 debug_level
     416 4 e 7 boot_first

Modified: trunk/src/mainboard/asus/a8v-e_se/cmos.layout
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/asus/a8v-e_se/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,7 +32,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399         1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/asus/m2v-mx_se/cmos.layout
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/asus/m2v-mx_se/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,7 +32,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399         1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/asus/mew-vm/cmos.layout
==============================================================================
--- trunk/src/mainboard/asus/mew-vm/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/asus/mew-vm/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/bcom/winnetp680/cmos.layout
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/bcom/winnetp680/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/broadcom/blast/cmos.layout
==============================================================================
--- trunk/src/mainboard/broadcom/blast/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/broadcom/blast/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/dell/s1850/cmos.layout
==============================================================================
--- trunk/src/mainboard/dell/s1850/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/dell/s1850/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/digitallogic/adl855pc/cmos.layout
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/digitallogic/adl855pc/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/digitallogic/msm586seg/cmos.layout
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/digitallogic/msm586seg/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/digitallogic/msm800sev/cmos.layout
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/digitallogic/msm800sev/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/eaglelion/5bcm/cmos.layout
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/eaglelion/5bcm/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/emulation/qemu-x86/cmos.layout
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/emulation/qemu-x86/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/gigabyte/m57sli/cmos.layout
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/gigabyte/m57sli/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/hp/dl145_g3/cmos.layout
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/hp/dl145_g3/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432         8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/ibm/e325/cmos.layout
==============================================================================
--- trunk/src/mainboard/ibm/e325/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/ibm/e325/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/ibm/e326/cmos.layout
==============================================================================
--- trunk/src/mainboard/ibm/e326/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/ibm/e326/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/iei/juki-511p/cmos.layout
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/iei/juki-511p/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/iei/nova4899r/cmos.layout
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/iei/nova4899r/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/intel/jarrell/cmos.layout
==============================================================================
--- trunk/src/mainboard/intel/jarrell/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/intel/jarrell/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -24,7 +24,7 @@
 #95           1       r       0        disable_clock_updates
 #96         288       r       0        temporary_filler
 0          376       r       0        reserved_memory
-376	     1       e       1        power_up_watchdog
+376          1       e       1        power_up_watchdog
 384          1       e       4        boot_option
 385          1       e       4        last_boot
 386          1       e       1        ECC_memory
@@ -38,7 +38,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/intel/xe7501devkit/cmos.layout
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/intel/xe7501devkit/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -1,16 +1,16 @@
 # NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: 
-#		"Error - Name  is an invalid identifier in line"
+# "Error - Name  is an invalid identifier in line"
 
 entries
 
 #start-bit length  config config-ID    name
-0           512      r       0        reserved_memory1			# We know nothing about the factory BIOS
-512         512      r       0        reserved_memory2			# More factory BIOS
+0           512      r       0        reserved_memory1	# We know nothing about the factory BIOS
+512         512      r       0        reserved_memory2	# More factory BIOS
 
 # Work in progress.
 # This is where we would put the LB RTC_BOOT_BYTE options once the code
 # supports finding them there.
-#1024         1       e       4        boot_option		
+#1024         1       e       4        boot_option
 #1025         1       e       4        last_boot
 #1026         1       e       1        ECC_memory
 #1028         4       r       0        reboot_bits

Modified: trunk/src/mainboard/iwill/dk8_htx/cmos.layout
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/iwill/dk8_htx/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/iwill/dk8s2/cmos.layout
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/iwill/dk8s2/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/iwill/dk8x/cmos.layout
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/iwill/dk8x/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/jetway/j7f24/cmos.layout
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/jetway/j7f24/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/kontron/kt690/cmos.layout
==============================================================================
--- trunk/src/mainboard/kontron/kt690/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/kontron/kt690/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/lippert/frontrunner/cmos.layout
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/lippert/frontrunner/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/msi/ms7135/cmos.layout
==============================================================================
--- trunk/src/mainboard/msi/ms7135/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/msi/ms7135/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432         8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/msi/ms7260/cmos.layout
==============================================================================
--- trunk/src/mainboard/msi/ms7260/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/msi/ms7260/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -54,14 +54,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/msi/ms9185/cmos.layout
==============================================================================
--- trunk/src/mainboard/msi/ms9185/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/msi/ms9185/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,7 +32,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399         1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/msi/ms9282/cmos.layout
==============================================================================
--- trunk/src/mainboard/msi/ms9282/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/msi/ms9282/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,7 +32,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399         1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/msi/ms9652_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/msi/ms9652_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,7 +53,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/newisys/khepri/cmos.layout
==============================================================================
--- trunk/src/mainboard/newisys/khepri/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/newisys/khepri/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,7 +53,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/olpc/btest/cmos.layout
==============================================================================
--- trunk/src/mainboard/olpc/btest/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/olpc/btest/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,8 +35,8 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
-440	     1	     e	     0	      dcon_present
+432          8       h       0        boot_countdown
+440          1       e       0        dcon_present
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/olpc/rev_a/cmos.layout
==============================================================================
--- trunk/src/mainboard/olpc/rev_a/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/olpc/rev_a/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,8 +35,8 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
-440	     1	     e	     0	      dcon_present
+432          8       h       0        boot_countdown
+440          1       e       0        dcon_present
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/pcengines/alix1c/cmos.layout
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/pcengines/alix1c/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/sunw/ultra40/cmos.layout
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/sunw/ultra40/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/supermicro/h8dme/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/h8dme/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/supermicro/h8dmr/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/h8dmr/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/supermicro/x6dai_g/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/x6dai_g/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -36,7 +36,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 728        256       h       0        user_data
 984         16       h       0        check_sum
 # Reserve the extended AMD configuration registers

Modified: trunk/src/mainboard/technexion/tim5690/cmos.layout
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/technexion/tim5690/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/technexion/tim8690/cmos.layout
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/technexion/tim8690/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,14 +53,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/technologic/ts5300/cmos.layout
==============================================================================
--- trunk/src/mainboard/technologic/ts5300/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/technologic/ts5300/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/tyan/s2735/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2735/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2735/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -38,7 +38,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 #440          4       e       9        slow_cpu
 444          1       e       1        nmi
 728        256       h       0        user_data

Modified: trunk/src/mainboard/tyan/s2850/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2850/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2850/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2875/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2875/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2875/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2880/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2880/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2880/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2881/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2881/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2881/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2882/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2882/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2882/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2885/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2885/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2885/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2891/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2891/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2891/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2892/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2892/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2892/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2895/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2895/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2895/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s2912/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2912/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2912/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,7 +53,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/tyan/s2912_fam10/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s2912_fam10/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -53,7 +53,7 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399          1       e       2        quad_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first

Modified: trunk/src/mainboard/tyan/s4880/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s4880/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s4880/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/tyan/s4882/cmos.layout
==============================================================================
--- trunk/src/mainboard/tyan/s4882/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/tyan/s4882/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -32,14 +32,14 @@
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399          1       e       2        multi_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 440          4       e       9        slow_cpu
 444          1       e       1        nmi
 445          1       e       1        iommu

Modified: trunk/src/mainboard/via/epia-cn/cmos.layout
==============================================================================
--- trunk/src/mainboard/via/epia-cn/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/via/epia-cn/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/via/epia-m/cmos.layout
==============================================================================
--- trunk/src/mainboard/via/epia-m/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/via/epia-m/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/via/epia-m700/cmos.layout
==============================================================================
--- trunk/src/mainboard/via/epia-m700/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/via/epia-m700/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/via/epia-n/cmos.layout
==============================================================================
--- trunk/src/mainboard/via/epia-n/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/via/epia-n/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/via/epia/cmos.layout
==============================================================================
--- trunk/src/mainboard/via/epia/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/via/epia/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/mainboard/winent/pl6064/cmos.layout
==============================================================================
--- trunk/src/mainboard/winent/pl6064/cmos.layout	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/mainboard/winent/pl6064/cmos.layout	Thu Apr  8 17:06:44 2010	(r5380)
@@ -35,7 +35,7 @@
 420          4       e       7        boot_second
 424          4       e       7        boot_third
 428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
+432          8       h       0        boot_countdown
 1008         16      h       0        check_sum
 
 enumerations

Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/northbridge.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/northbridge/amd/amdfam10/northbridge.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -1234,7 +1234,7 @@
 
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
 #if CONFIG_LOGICAL_CPUS == 1
-	get_option(&disable_siblings, "quad_core");
+	get_option(&disable_siblings, "multi_core");
 #endif
 
 	// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it

Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -1595,7 +1595,7 @@
 	unsigned total_cpus;
 
 	if ((!CONFIG_HAVE_OPTION_TABLE) ||
-	    read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
 		total_cpus = verify_dualcore(nodes);
 	}
 	else {

Modified: trunk/src/northbridge/amd/amdk8/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/northbridge.c	Thu Apr  8 17:02:39 2010	(r5379)
+++ trunk/src/northbridge/amd/amdk8/northbridge.c	Thu Apr  8 17:06:44 2010	(r5380)
@@ -1142,7 +1142,7 @@
 
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
 #if CONFIG_LOGICAL_CPUS == 1
-	get_option(&disable_siblings, "dual_core");
+	get_option(&disable_siblings, "multi_core");
 #endif
 
 	// for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)



From svn at coreboot.org  Thu Apr  8 17:09:54 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 17:09:54 +0200
Subject: [coreboot] [commit] r5381 - in trunk/src: cpu/amd/model_10xxx
	cpu/amd/model_fxx mainboard/amd/dbm690t
	mainboard/amd/mahogany mainboard/amd/mahogany_fam10
	mainboard/amd/pistachio mainboard/amd/serengeti_cheeta...
Message-ID: <E1NztMg-0003vY-GW@ra.coresystems.de>

Author: myles
Date: Thu Apr  8 17:09:53 2010
New Revision: 5381
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5381

Log:
Clean up fidvid files using indent.
Remove some special print statements.

In general, make them easier to compare.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/cpu/amd/model_10xxx/fidvid.c
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_fxx/fidvid.c
   trunk/src/cpu/amd/model_fxx/init_cpus.c
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c

Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/fidvid.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/cpu/amd/model_10xxx/fidvid.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -17,41 +17,39 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 #include "../../../northbridge/amd/amdht/AsPsDefs.h"
 
-#define FAM10_SET_FIDVID_DEBUG 1
+#define SET_FIDVID_DEBUG 1
 
 // if we are tight of CAR stack, disable it
-#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
+#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
 
 static inline void print_debug_fv(const char *str, u32 val)
 {
-#if FAM10_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x\n", str, val);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, u8 val)
 {
-#if FAM10_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%02x\n", str, val);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
-#if FAM10_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
 
-
 struct fidvid_st {
 	u32 common_fid;
 };
 
-
 static void enable_fid_change(u8 fid)
 {
 	u32 dword;
@@ -61,24 +59,24 @@
 
 	nodes = get_nodes();
 
-	for(i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i,3);
+	for (i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 3);
 		dword = pci_read_config32(dev, 0xd4);
 		dword &= ~0x1F;
 		dword |= (u32) fid & 0x1F;
 		dword |= 1 << 5;	// enable
 		pci_write_config32(dev, 0xd4, dword);
-		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
+		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
+		       dword);
 	}
 }
 
-
 static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
 {
 	u8 pviModeFlag;
 	u8 highVoltageVid, lowVoltageVid, bValue;
 	u16 minimumSlamTime;
-	u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */
+	u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 };	/* Reg settings scaled by 100 */
 	u32 dtemp;
 	msr_t msr;
 
@@ -94,12 +92,10 @@
 	 * decimals.
 	 */
 
-
-
 	/* Determine if this is a PVI or SVI system */
 	dtemp = pci_read_config32(dev, 0xA0);
 
-	if( dtemp & PVI_MODE )
+	if (dtemp & PVI_MODE)
 		pviModeFlag = 1;
 	else
 		pviModeFlag = 0;
@@ -113,7 +109,7 @@
 	 */
 	if (pviModeFlag) {
 		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
-		if( highVoltageVid > bValue )
+		if (highVoltageVid > bValue)
 			highVoltageVid = bValue;
 	}
 
@@ -130,7 +126,7 @@
 	 */
 	if (pviModeFlag) {
 		bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
-		if( lowVoltageVid > bValue )
+		if (lowVoltageVid > bValue)
 			lowVoltageVid = bValue;
 	}
 
@@ -139,13 +135,13 @@
 	bValue = (u8) (dtemp & BIT_MASK_7);
 
 	/* Use the VID with the lowest voltage (higher VID) */
-	if( lowVoltageVid < bValue )
+	if (lowVoltageVid < bValue)
 		lowVoltageVid = bValue;
 
 	/* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */
 	if (lowVoltageVid > 0x7C) {
 		lowVoltageVid = 0x7C;
-		if(highVoltageVid > 0x7C)
+		if (highVoltageVid > 0x7C)
 			highVoltageVid = 0x7C;
 	}
 
@@ -161,8 +157,8 @@
 	 * Note that if we don't find a value, we
 	 * will fall through to a value of 7
 	 */
-	for(bValue=0; bValue < 7; bValue++) {
-		if(minimumSlamTime <= vSlamTimes[bValue])
+	for (bValue = 0; bValue < 7; bValue++) {
+		if (minimumSlamTime <= vSlamTimes[bValue])
 			break;
 	}
 
@@ -173,7 +169,6 @@
 	pci_write_config32(dev, 0xd8, dtemp);
 }
 
-
 static void prep_fid_change(void)
 {
 	u32 dword, dtemp;
@@ -185,9 +180,9 @@
 
 	nodes = get_nodes();
 
-	for(i = 0; i < nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
-		dev = NODE_PCI(i,3);
+		dev = NODE_PCI(i, 3);
 
 		dword = pci_read_config32(dev, 0xd8);
 		dword &= VSRAMP_MASK;
@@ -214,20 +209,18 @@
 			 */
 			dword = pci_read_config32(dev, 0xd4);
 			dword &= CPTC0_MASK;
-			dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 |
-				 LNK_PLL_LOCK; /* per BKDG */
+			dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK;	/* per BKDG */
 			pci_write_config32(dev, 0xd4, dword);
 		} else {
 			dword = pci_read_config32(dev, 0xd4);
 			dword &= CPTC0_MASK;
 			/* get number of cores for PowerStepUp & PowerStepDown in server
-			    1 core - 400nS  - 0000b
-			    2 cores - 200nS - 0010b
-			    3 cores - 133nS -> 100nS - 0011b
-			    4 cores - 100nS - 0011b
-			*/
-			switch(get_core_num_in_bsp(i))
-			{
+			   1 core - 400nS  - 0000b
+			   2 cores - 200nS - 0010b
+			   3 cores - 133nS -> 100nS - 0011b
+			   4 cores - 100nS - 0011b
+			 */
+			switch (get_core_num_in_bsp(i)) {
 			case 0:
 				dword |= PW_STP_UP400 | PW_STP_DN400;
 				break;
@@ -248,12 +241,12 @@
 
 		/* check PVI/SVI */
 		dword = pci_read_config32(dev, 0xA0);
-		if(dword & PVI_MODE) {	/* PVI */
+		if (dword & PVI_MODE) {	/* PVI */
 			/* set slamVidMode to 0 for PVI */
 			dword &= VID_SLAM_OFF | PLLLOCK_OFF;
 			dword |= PLLLOCK_DFT_L;
 			pci_write_config32(dev, 0xA0, dword);
-		} else {		/* SVI */
+		} else {	/* SVI */
 			/* set slamVidMode to 1 for SVI */
 			dword &= PLLLOCK_OFF;
 			dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
@@ -264,7 +257,7 @@
 			/* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd]  */
 			dword = pci_read_config32(dev, 0xD8);
 
-			if( dtemp & DUAL_VDD_BIT)
+			if (dtemp & DUAL_VDD_BIT)
 				dword |= PWR_PLN_ON;
 			else
 				dword &= PWR_PLN_OFF;
@@ -275,7 +268,7 @@
 		 * function setFidVidRegs()
 		 */
 		dword = pci_read_config32(dev, 0xDc);
-		dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
+		dword |= 0x5 << 12;	/* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
 		pci_write_config32(dev, 0xdc, dword);
 
 		/* Rev B settings - FIXME: support other revs. */
@@ -313,20 +306,18 @@
 		nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
 		cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
 
-		if( nbVid != cpuVid ) {
-			if(nbVid > cpuVid)
+		if (nbVid != cpuVid) {
+			if (nbVid > cpuVid)
 				nbVid = cpuVid;
 
 			msr.lo = msr.lo & PS_BOTH_VID_OFF;
-			msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT);
-			msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT);
+			msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
+			msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
 			wrmsr(PS_REG_BASE + i, msr);
 		}
 	}
 }
 
-
-
 static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
 {
 	msr_t msr;
@@ -343,7 +334,7 @@
 	 */
 
 	msr = rdmsr(0xc0010071);
-	startup_pstate = (msr.hi >> (32-32)) & 0x07;
+	startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
 
 	/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
 	 * Then transition to P1 for corex and P0 for core0.
@@ -379,8 +370,7 @@
 	}
 }
 
-
-static void coreDelay (void)
+static void coreDelay(void)
 {
 	u32 saved;
 	u32 hi, lo, msr;
@@ -390,23 +380,22 @@
 	   This seems like a hack to me...
 	   It would be nice to have a central delay function. */
 
-	cycles = 8000 << 3;		/* x8 (number of 1.25ns ticks) */
+	cycles = 8000 << 3;	/* x8 (number of 1.25ns ticks) */
 
-	msr = 0x10;			/* TSC */
+	msr = 0x10;		/* TSC */
 	_RDMSR(msr, &lo, &hi);
 	saved = lo;
 	do {
 		_RDMSR(msr, &lo, &hi);
-	} while (lo - saved < cycles );
+	} while (lo - saved < cycles);
 }
 
-
 static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
 {
 	u32 currentVid, dtemp;
 	msr_t msr;
 	u8 vsTimecode;
-	u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500};
+	u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 };
 	int vsTime;
 
 	/* This function steps or slam the Nb VID to the target VID.
@@ -416,7 +405,7 @@
 
 	/* get the current VID */
 	msr = rdmsr(0xC0010071);
-	if(isNb)
+	if (isNb)
 		currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7;
 	else
 		currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7;
@@ -426,11 +415,11 @@
 
 	/* check PVI/SPI */
 	dtemp = pci_read_config32(dev, 0xA0);
-	if (dtemp & PVI_MODE) { 		/* PVI, step VID */
+	if (dtemp & PVI_MODE) {	/* PVI, step VID */
 		if (currentVid < targetVid) {
 			while (currentVid < targetVid) {
 				currentVid++;
-				if(isNb)
+				if (isNb)
 					msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
 				else
 					msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
@@ -438,17 +427,17 @@
 
 				/* read F3xD8[VSRampTime]  */
 				dtemp = pci_read_config32(dev, 0xD8);
-				vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
-				vsTime = (int) timeTable[vsTimecode];
+				vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
+				vsTime = (int)timeTable[vsTimecode];
 				do {
 					coreDelay();
-					vsTime -=40;
-				} while(vsTime  > 0);
+					vsTime -= 40;
+				} while (vsTime > 0);
 			}
 		} else if (currentVid > targetVid) {
 			while (currentVid > targetVid) {
 				currentVid--;
-				if(isNb)
+				if (isNb)
 					msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
 				else
 					msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
@@ -456,16 +445,16 @@
 
 				/* read F3xD8[VSRampTime]  */
 				dtemp = pci_read_config32(dev, 0xD8);
-				vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
-				vsTime = (int) timeTable[vsTimecode];
+				vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
+				vsTime = (int)timeTable[vsTimecode];
 				do {
 					coreDelay();
-					vsTime -=40;
-				} while(vsTime  > 0);
+					vsTime -= 40;
+				} while (vsTime > 0);
 			}
 		}
 	} else {		/* SVI, slam VID */
-		if(isNb)
+		if (isNb)
 			msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS);
 		else
 			msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS);
@@ -473,12 +462,12 @@
 
 		/* read F3xD8[VSRampTime]  */
 		dtemp = pci_read_config32(dev, 0xD8);
-		vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
-		vsTime = (int) timeTable[vsTimecode];
+		vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
+		vsTime = (int)timeTable[vsTimecode];
 		do {
 			coreDelay();
-			vsTime -=40;
-		} while(vsTime  > 0);
+			vsTime -= 40;
+		} while (vsTime > 0);
 	}
 }
 
@@ -505,13 +494,13 @@
 	nodes = get_nodes();
 	nb_cof_vid_update = 0;
 	for (i = 0; i < nodes; i++) {
-		if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
+		if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
 			nb_cof_vid_update = 1;
 			break;
 		}
 	}
 
-	dev = NODE_PCI(nodeid,3);
+	dev = NODE_PCI(nodeid, 3);
 	pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
 	reg1fc = pci_read_config32(dev, 0x1FC);
 
@@ -537,7 +526,7 @@
 	}
 
 	send = (nb_cof_vid_update << 16) | (fid_max << 8);
-	send |= (apicid << 24); // ap apicid
+	send |= (apicid << 24);	// ap apicid
 
 	// Send signal to BSP about this AP max fid
 	// This also indicates this AP is ready for warm reset (if required).
@@ -553,50 +542,50 @@
 
 	fidmax_new = (fid_packed_new >> 8) & 0xFF;
 
-	if(fidmax > fidmax_new) {
+	if (fidmax > fidmax_new) {
 		fidmax = fidmax_new;
 	}
 
 	fid_packed &= 0xFF << 16;
 	fid_packed |= (fidmax << 8);
-	fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
+	fid_packed |= fid_packed_new & (0xFF << 16);	// set nb_cof_vid_update
 
 	return fid_packed;
 }
 
-
-static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
+static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
 {
-		u32 readback = 0;
-		u32 timeout = 1;
+	u32 readback = 0;
+	u32 timeout = 1;
 
-		struct fidvid_st *fvp = gp;
-		int loop;
+	struct fidvid_st *fvp = gp;
+	int loop;
 
-		print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
-
-		loop = 100000;
-		while(--loop > 0) {
-			if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue;
-			if((readback & 0x3f) == 1) {
-				timeout = 0;
-				break; //target ap is in stage 1
-			}
-		}
+	print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
 
-		if(timeout) {
-			print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
-			return;
+	loop = 100000;
+	while (--loop > 0) {
+		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
+			continue;
+		if ((readback & 0x3f) == 1) {
+			timeout = 0;
+			break;	/* target ap is in stage 1 */
 		}
+	}
 
-		print_debug_fv("\treadback = ", readback);
+	if (timeout) {
+		printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
+		       __func__, ap_apicid);
+		return;
+	}
 
-		fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
+	print_debug_fv("\treadback = ", readback);
 
-		print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
+	fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
 
-}
+	print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
 
+}
 
 static void updateSviPsNbVidAfterWR(u32 newNbVid)
 {
@@ -607,7 +596,7 @@
 	 * for SVI mode.
 	 */
 
-	for( i = 0; i < 5; i++) {
+	for (i = 0; i < 5; i++) {
 		msr = rdmsr(0xC0010064 + i);
 		if ((msr.hi >> 31) & 1) {	/* PstateEn? */
 			msr.lo &= ~(0x7F << 25);
@@ -632,13 +621,13 @@
 	 */
 
 	/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
-	for( i = 0; i < 5; i++) {
+	for (i = 0; i < 5; i++) {
 		msr = rdmsr(0xC0010064 + i);
 		/*  NbDid (bit 22 of P-state Reg) == 0  or NbVidUpdatedAll = 1 */
 		if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
 			msr.lo &= ~(0x7F << 25);
 			msr.lo |= (newNbVid & 0x7F) << 25;
-			wrmsr (0xC0010064 + i, msr);
+			wrmsr(0xC0010064 + i, msr);
 		}
 	}
 
@@ -651,13 +640,12 @@
 	msr.lo = StartupPstate;
 	wrmsr(0xC0010062, msr);
 
-	/* Wait for StartupPstate to set.*/
+	/* Wait for StartupPstate to set. */
 	do {
 		msr = rdmsr(0xC0010063);
 	} while (msr.lo != StartupPstate);
 }
 
-
 static void set_p0(void)
 {
 	msr_t msr;
@@ -673,8 +661,8 @@
 	} while (msr.lo != 0);
 }
 
-
-static void finalPstateChange (void) {
+static void finalPstateChange(void)
+{
 	/* Enble P0 on all cores for best performance.
 	 * Linux can slow them down later if need be.
 	 * It is safe since they will be in C1 halt
@@ -683,7 +671,6 @@
 	set_p0();
 }
 
-
 static void init_fidvid_stage2(u32 apicid, u32 nodeid)
 {
 	msr_t msr;
@@ -703,13 +690,13 @@
 	nodes = get_nodes();
 	nb_cof_vid_update = 0;
 	for (i = 0; i < nodes; i++) {
-		if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
+		if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
 			nb_cof_vid_update = 1;
 			break;
 		}
 	}
 
-	dev = NODE_PCI(nodeid,3);
+	dev = NODE_PCI(nodeid, 3);
 	pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
 	reg1fc = pci_read_config32(dev, 0x1FC);
 	nbvid = (reg1fc >> 7) & 0x7F;
@@ -724,7 +711,7 @@
 			nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
 			updateSviPsNbVidAfterWR(nbvid);
 		}
-	} else { 	/* !nb_cof_vid_update */
+	} else {		/* !nb_cof_vid_update */
 		if (pvimode)
 			UpdateSinglePlaneNbVid();
 	}
@@ -742,7 +729,7 @@
 }
 
 
-#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 struct ap_apicid_st {
 	u32 num;
 	// it could use 256 bytes for 64 node quad core system
@@ -761,7 +748,7 @@
 
 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 {
-#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 	struct ap_apicid_st ap_apicidx;
 	u32 i;
 #endif
@@ -785,7 +772,7 @@
 	/* If any node has nb_cof_vid_update set all nodes need an update. */
 	nb_cof_vid_update = 0;
 	for (i = 0; i < nodes; i++) {
-		if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
+		if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
 			nb_cof_vid_update = 1;
 			break;
 		}
@@ -810,29 +797,29 @@
 
 		/*  fid setup is handled by the BSP at the end. */
 
-	} else {	/* ! nb_cof_vid_update */
+	} else {		/* ! nb_cof_vid_update */
 		/* Use max values */
 		if (pvimode)
 			UpdateSinglePlaneNbVid();
 	}
 
-	fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ;
+	fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
 	print_debug_fv("BSP fid = ", fv.common_fid);
 
-#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
 	/* For all APs (We know the APIC ID of all APs even when the APIC ID
 	   is lifted) remote read from AP LAPIC_MSG_REG about max fid.
 	   Then calculate the common max fid that can be used for all
 	   APs and BSP */
 	ap_apicidx.num = 0;
 
-	for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
+	for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
 
-	for(i = 0; i < ap_apicidx.num; i++) {
+	for (i = 0; i < ap_apicidx.num; i++) {
 		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
 	}
 #else
-	for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
+	for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
 #endif
 
 	print_debug_fv("common_fid = ", fv.common_fid);
@@ -846,6 +833,6 @@
 		return 1;
 	}
 
-	return 0; // No FID/VID changes. Don't reset
+	return 0;		// No FID/VID changes. Don't reset
 }
 #endif

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -20,14 +20,14 @@
 #include "defaults.h"
 
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
-#ifndef FAM10_SET_FIDVID
-	#define FAM10_SET_FIDVID 1
+#ifndef SET_FIDVID
+	#define SET_FIDVID 1
 #endif
 
-#ifndef FAM10_SET_FIDVID_CORE0_ONLY
+#ifndef SET_FIDVID_CORE0_ONLY
 	/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
 	   Need to do every AP to set common FID/VID*/
-	#define FAM10_SET_FIDVID_CORE0_ONLY 0
+	#define SET_FIDVID_CORE0_ONLY 0
 #endif
 
 static void print_initcpu8 (const char *strval, u8 val)
@@ -217,7 +217,7 @@
 #define LAPIC_MSG_REG 0x380
 
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
@@ -398,8 +398,8 @@
 		cpuSetAMDMSR();
 
 
-#if FAM10_SET_FIDVID == 1
-	#if (CONFIG_LOGICAL_CPUS == 1)  && (FAM10_SET_FIDVID_CORE0_ONLY == 1)
+#if SET_FIDVID == 1
+	#if (CONFIG_LOGICAL_CPUS == 1)  && (SET_FIDVID_CORE0_ONLY == 1)
 		// Run on all AP for proper FID/VID setup.
 		if(id.coreid == 0 ) // only need set fid for core0
 	#endif
@@ -994,7 +994,7 @@
 		cpuSetAMDPCI(i);
 	}
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	// Prep each node for FID/VID setup.
 	prep_fid_change();
 #endif

Modified: trunk/src/cpu/amd/model_fxx/fidvid.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/fidvid.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/cpu/amd/model_fxx/fidvid.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -1,10 +1,10 @@
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
-#define K8_SET_FIDVID_DEBUG 0
+#define SET_FIDVID_DEBUG 0
 
-#define K8_SET_FIDVID_ONE_BY_ONE 1
+#define SET_FIDVID_ONE_BY_ONE 1
 
-#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
+#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
 
 #ifndef SB_VFSMAF
 #define SB_VFSMAF 1
@@ -12,78 +12,77 @@
 
 #define FX_SUPPORT 1
 
-static inline void print_debug_fv(const char *str, unsigned val)
+static inline void print_debug_fv(const char *str, u32 val)
 {
-#if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x\n", str, val);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
-static inline void print_debug_fv_8(const char *str, unsigned val)
+static inline void print_debug_fv_8(const char *str, u8 val)
 {
-#if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%02x\n", str, val);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
-static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
+static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
-#if K8_SET_FIDVID_DEBUG == 1
-		printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
+#if SET_FIDVID_DEBUG == 1
+	printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
 
-
 static void enable_fid_change(void)
 {
-	uint32_t dword;
-	unsigned nodes;
+	u32 dword;
+	u32 nodes;
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 4) & 7) + 1;
 
 	for (i = 0; i < nodes; i++) {
-		dword = pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xd8);
+		dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8);
 		dword &= 0x8ff00000;
 		dword |= (2 << 28) | (0x02710);
-		pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd8, dword);
+		pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8, dword);
 
 		dword = 0x04e2a707;
-		pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd4, dword);
+		pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword);
 
 		/* disable the DRAM interface at first, it will be enabled
 		 * by raminit again */
-		dword = pci_read_config32(PCI_DEV(0, 0x18+i, 2), 0x94);
+		dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94);
 		dword |= (1 << 14);
-		pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword);
+		pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword);
 
-		dword = 0x23070700; /* enable FID/VID change */
-//		dword = 0x00070000; /* enable FID/VID change */
-		pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
+		dword = 0x23070700;	/* enable FID/VID change */
+//              dword = 0x00070000; /* enable FID/VID change */
+		pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword);
 
 #if CONFIG_HAVE_ACPI_RESUME
 		dword = 0x21132113;
 #else
 		dword = 0x00132113;
 #endif
-		pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword);
+		pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x84, dword);
 
 	}
 }
 
-#if K8_SET_FIDVID_ONE_BY_ONE == 0
+#if SET_FIDVID_ONE_BY_ONE == 0
 static unsigned set_fidvid_without_init(unsigned fidvid)
 {
 	msr_t msr;
-	uint32_t vid;
-	uint32_t fid;
+	u32 vid;
+	u32 fid;
 
 	fid = (fidvid >> 8) & 0x3f;
 	vid = (fidvid >> 16) & 0x3f;
 
 	/* set new FID/VID */
 	msr.hi = 1;
-	msr.lo = (vid<<8) | fid;
+	msr.lo = (vid << 8) | fid;
 	wrmsr(0xc0010041, msr);
 	return fidvid;
 }
@@ -117,12 +116,12 @@
 	};
 
 	msr_t msr;
-	uint32_t vid_new;
-	uint32_t fid_new;
-	uint32_t vid_max;
-	uint32_t fid_max;
-	uint32_t vid_cur;
-	uint32_t fid_cur;
+	u32 vid_new;
+	u32 fid_new;
+	u32 vid_max;
+	u32 fid_max;
+	u32 vid_cur;
+	u32 fid_cur;
 	unsigned apicidx;
 
 	int step_limit;
@@ -131,7 +130,9 @@
 	apicidx = lapicid();
 
 	if (apicid != apicidx) {
-		printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
+		printk(BIOS_ERR,
+		       "wrong apicid, we want change %x, but it is %x\n",
+		       apicid, apicidx);
 		return fidvid;
 	}
 
@@ -146,14 +147,14 @@
 	if ((vid_cur == vid_new) && (fid_cur == fid_new))
 		return fidvid;
 
-	vid_max = (msr.hi >> (48-32)) & 0x3f;
-	fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
+	vid_max = (msr.hi >> (48 - 32)) & 0x3f;
+	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 
 #if FX_SUPPORT
-	if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */
-		fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */
-		if (fid_max >= ((25-4) * 2)) {
-			fid_max = (10-4) * 2; /* hard set to 2G */
+	if (fid_max >= ((25 - 4) * 2)) {	/* FX max fid is 5G */
+		fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2;	/* max FID is min fid + 1G */
+		if (fid_max >= ((25 - 4) * 2)) {
+			fid_max = (10 - 4) * 2;	/* hard set to 2G */
 		}
 	}
 #endif
@@ -162,25 +163,24 @@
 	/* TODO - make this more correct. Not a big deal for setting max...
 	 * BKDG figure 11
 	 * if TargetFID > InitialFID
-	 *	TargetVID = FinalVID - RVO
+	 *      TargetVID = FinalVID - RVO
 	 * else
-	 *	if CurrentVID > FinalVID
-	 *		TargetVID = FinalVID - RVO
-	 *	else
-	 *		TargetVID = CurrentVIDD - RVO
+	 *      if CurrentVID > FinalVID
+	 *              TargetVID = FinalVID - RVO
+	 *      else
+	 *              TargetVID = CurrentVIDD - RVO
 	 */
 	msr.hi = 1;
 	msr.lo = (vid_max << 8) | (fid_cur);
 #if SB_VFSMAF == 1
-	msr.lo |= (1 << 16); /* init changes */
+	msr.lo |= (1 << 16);	/* init changes */
 #endif
 	wrmsr(0xc0010041, msr);
 #if SB_VFSMAF == 0
 	ldtstop_sb();
 #endif
 
-
-	for (loop=0; loop < 100000; loop++){
+	for (loop = 0; loop < 100000; loop++) {
 		msr = rdmsr(0xc0010042);
 		if (!(msr.lo & (1 << 31)))
 			break;
@@ -201,19 +201,20 @@
 	 *	transition to target fid
 	 */
 
-	printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
+	printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur,
+	       fid_max);
 	printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
 
-	step_limit = 8; /* max 8 steps just in case... */
+	step_limit = 8;		/* max 8 steps just in case... */
 	while ((fid_cur != fid_new) && (step_limit--)) {
 		u32 fid_temp;
 		int step;
 
 		if (fid_cur < fid_new)
 			/* Force Fid steps even. step == 0 means 100MHz step */
-			step = ((fid_new/2) - (fid_cur/2)) * 2;
+			step = ((fid_new / 2) - (fid_cur / 2)) * 2;
 		else
-			step = ((fid_cur/2) - (fid_new/2)) * 2;
+			step = ((fid_cur / 2) - (fid_new / 2)) * 2;
 
 		/* If 200Mhz step OR past 3200 max table value */
 		if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) {
@@ -226,23 +227,23 @@
 			else
 				fid_temp = fid_cur - 2;
 
-
-		} else if ( step > 2) {	/* If more than a 200Mhz step */
+		} else if (step > 2) {	/* If more than a 200Mhz step */
 			int temp;
 
 			/* look it up in the table */
 			printk(BIOS_DEBUG, "FidVid table step ");
 
-			temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)];
+			temp =
+			    next_fid_200[((fid_new / 2) * 13) + (fid_cur / 2)];
 
 			if (temp > 0)
-				fid_temp = (temp-4) * 2; /* Table 108 */
+				fid_temp = (temp - 4) * 2;	/* Table 108 */
 			else if (temp == 0)
 				fid_temp = fid_new;
 			else
-				break; /* table error */
+				break;	/* table error */
 
-		} else { /* step < 2 (100MHZ) */
+		} else {	/* step < 2 (100MHZ) */
 			printk(BIOS_DEBUG, "100MHZ step ");
 
 			/* The table adjust in 200MHz increments. If requested,
@@ -256,41 +257,41 @@
 			}
 		}
 
-		if(fid_temp > fid_max) {
-			printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
+		if (fid_temp > fid_max) {
+			printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n",
+			       fid_temp, fid_max);
 			break;
 		}
 
 		printk(BIOS_DEBUG, "fidvid: 0x%x\n", fid_temp);
 
 		/* set target fid */
-		msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */
+		msr.hi = 0x190;	/* 2 us for AMD NPT Family 0Fh Processors */
 		msr.lo = (vid_cur << 8) | fid_temp;
 #if SB_VFSMAF == 1
-		msr.lo |= (1 << 16); /* init changes */
+		msr.lo |= (1 << 16);	/* init changes */
 #endif
 		wrmsr(0xc0010041, msr);
 #if SB_VFSMAF == 0
 		ldtstop_sb();
 #endif
 
-
-#if K8_SET_FIDVID_DEBUG == 1
+#if SET_FIDVID_DEBUG == 1
 		if (showmessage) {
 			print_debug_fv_8("set_fidvid APICID = ", apicid);
 			print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);
 		}
 #endif
 
-		for (loop = 0; loop < 100000; loop++){
+		for (loop = 0; loop < 100000; loop++) {
 			msr = rdmsr(0xc0010042);
 			if (!(msr.lo & (1 << 31)))
 				break;
 		}
 		fid_cur = msr.lo & 0x3f;
 
-#if K8_SET_FIDVID_DEBUG == 1
-		if (showmessage)	{
+#if SET_FIDVID_DEBUG == 1
+		if (showmessage) {
 			print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);
 		}
 #endif
@@ -310,14 +311,14 @@
 	msr.hi = 1;
 	msr.lo = (vid_new << 8) | (fid_cur);
 #if SB_VFSMAF == 1
-	msr.lo |= (1 << 16); // init changes
+	msr.lo |= (1 << 16);	// init changes
 #endif
 	wrmsr(0xc0010041, msr);
 #if SB_VFSMAF == 0
 	ldtstop_sb();
 #endif
 
-	for (loop = 0; loop < 100000; loop++){
+	for (loop = 0; loop < 100000; loop++) {
 		msr = rdmsr(0xc0010042);
 		if (!(msr.lo & (1 << 31)))
 			break;
@@ -328,10 +329,12 @@
 
 	if (showmessage) {
 		if (vid_new != vid_cur) {
-			print_err("set vid failed for apicid ="); print_err_hex8(apicidx);  print_err("\n");
+			printk(BIOS_ERR, "set vid failed for apicid =%02x\n",
+			       apicidx);
 		}
 		if (fid_new != fid_cur) {
-			print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
+			printk(BIOS_ERR, "set fid failed for apicid =%02x\n",
+			       apicidx);
 		}
 	}
 
@@ -341,35 +344,35 @@
 
 static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
 {
-	uint32_t send;
-	uint32_t readback = 0;
+	u32 send;
+	u32 readback = 0;
 	unsigned timeout = 1;
 	msr_t msr;
-	uint32_t vid_cur;
-	uint32_t fid_cur;
-	uint32_t fid_max;
+	u32 vid_cur;
+	u32 fid_cur;
+	u32 fid_max;
 	int loop;
 
-	msr =	rdmsr(0xc0010042);
-	fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
+	msr = rdmsr(0xc0010042);
+	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 #if FX_SUPPORT
-	if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */
-		fid_max = ((msr.lo>>8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */
-		if (fid_max >= ((25-4) * 2)) {
-			fid_max = (10-4) * 2; // hard set to 2G
+	if (fid_max >= ((25 - 4) * 2)) {	/* FX max fid is 5G */
+		fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2;	/* maxFID = minFID + 1G */
+		if (fid_max >= ((25 - 4) * 2)) {
+			fid_max = (10 - 4) * 2;	// hard set to 2G
 		}
 	}
 #endif
-	send = fid_max<<8;
+	send = fid_max << 8;
 
-	send |= ((msr.hi >> (48-32)) & 0x3f) << 16; /* max vid */
-	send |= (apicid << 24); /* ap apicid */
+	send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16;	/* max vid */
+	send |= (apicid << 24);	/* ap apicid */
 
-#if K8_SET_FIDVID_ONE_BY_ONE == 1
+#if SET_FIDVID_ONE_BY_ONE == 1
 	vid_cur = msr.hi & 0x3f;
 	fid_cur = msr.lo & 0x3f;
 
-	/* set to current */ 
+	/* set to current */
 	msr.hi = 1;
 	msr.lo = (vid_cur << 8) | (fid_cur);
 	wrmsr(0xc0010041, msr);
@@ -377,52 +380,55 @@
 
 	timeout = wait_cpu_state(bsp_apicid, 1);
 	if (timeout) {
-		print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid);
+		printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading"
+		       " from BSP on %02x\n", apicid);
 	}
 	/* send signal to BSP about this AP max fid and vid */
 	/* AP at state 1 that sent our fid and vid */
 	lapic_write(LAPIC_MSG_REG, send | 1);
 
-//	wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */
+//      wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */
 	loop = 1000000;
 	while (--loop > 0) {
 		/* remote read BSP signal that include vid/fid that need to set */
-		if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0)
+		if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback) !=
+		    0)
 			continue;
 		if (((readback >> 24) & 0xff) == apicid)
-			break; /* it is this cpu turn */
+			break;	/* it is this cpu turn */
 	}
 
 	if (loop > 0) {
-	#if K8_SET_FIDVID_ONE_BY_ONE == 1
-			readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
-	#else
-		readback = set_fidvid_without_init(readback & 0xffff00); // this AP
-	#endif
+#if SET_FIDVID_ONE_BY_ONE == 1
+		readback = set_fidvid(apicid, readback & 0xffff00, 1);	// this AP
+#else
+		readback = set_fidvid_without_init(readback & 0xffff00);	// this AP
+#endif
 		/* send signal to BSP that this AP fid/vid is set */
 		/* allow to change state2 is together with apicid */
 		/* AP at state that We set the requested fid/vid */
-		send = (apicid<<24) | (readback & 0x00ffff00); 
+		send = (apicid << 24) | (readback & 0x00ffff00);
 	} else {
-		print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid);
+		printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
+		       __func__, apicid);
 	}
 
-		lapic_write(LAPIC_MSG_REG, send | 2);
+	lapic_write(LAPIC_MSG_REG, send | 2);
 
 	timeout = wait_cpu_state(bsp_apicid, 3);
 	if (timeout) {
-		print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid);
+		printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
+		       __func__, apicid);
 	}
 }
 
-static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
+static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
 {
 	/* FIXME: need to check the change path to verify if it is reachable 
 	 * when common fid is small than 1.6G */
 	if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
 		return fidvid;
-	}
-	else {
+	} else {
 		return fidvidx;
 	}
 }
@@ -431,10 +437,10 @@
 	unsigned common_fidvid;
 };
 
-static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
+static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
 {
-	unsigned readback = 0;
-	unsigned timeout = 1;
+	u32 readback = 0;
+	u32 timeout = 1;
 
 	struct fidvid_st *fvp = gp;
 	int loop;
@@ -443,19 +449,21 @@
 
 	loop = 1000000;
 	while (--loop > 0) {
-		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0)
+		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
 			continue;
 		if ((readback & 0xff) == 1) {
 			timeout = 0;
-			break; /* target ap is in stage 1 */
+			break;	/* target ap is in stage 1 */
 		}
 	}
+
 	if (timeout) {
-		print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
+		printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
+		       __func__, ap_apicid);
 		return;
 	}
 
-	print_debug_fv("\treadback=", readback);
+	print_debug_fv("\treadback = ", readback);
 
 	fvp->common_fidvid = calc_common_fidvid(fvp->common_fidvid, readback & 0xffff00);
 
@@ -473,31 +481,31 @@
 	print_debug_fv("state 2: ap_apicid=", ap_apicid);
 
 	/* all set to state2 */
-	lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2);
+	lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid << 24) | 2);
 
 	loop = 1000000;
 	while (--loop > 0) {
-		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0)
+		if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
 			continue;
 		if ((readback & 0xff) == 2) {
 			timeout = 0;
-			break; /* target ap is stage 2, it's FID has beed set */
+			break;	/* target ap is stage 2, it's FID has beed set */
 		}
 	}
 
 	if (timeout) {
-		print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid);
+		printk(BIOS_DEBUG, "%s: time out while reading from ap %02x",
+		       __func__, ap_apicid);
 		return;
 	}
 
 	print_debug_fv("\treadback=", readback);
 }
 
-#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 struct ap_apicid_st {
-	unsigned num;
-	unsigned apicid[16]; /* 8 way dual core need 16 */
-	/* FIXME: 32 node quad core, may need 128 */
+	u32 num;
+	unsigned apicid[16];	/* 8 way dual core need 16 */
 };
 
 static void store_ap_apicid(unsigned ap_apicid, void *gp)
@@ -511,77 +519,75 @@
 
 static void init_fidvid_bsp(unsigned bsp_apicid)
 {
-	uint32_t vid_max;
-	uint32_t fid_max;
+	u32 vid_max;
+	u32 fid_max;
 
 	struct fidvid_st fv;
 
-#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 	struct ap_apicid_st ap_apicidx;
 	unsigned i;
 #endif
 
 	msr_t msr;
-	msr =	rdmsr(0xc0010042);
-	fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */
+	msr = rdmsr(0xc0010042);
+	fid_max = ((msr.lo >> 16) & 0x3f);	/* max fid */
 #if FX_SUPPORT == 1
-	if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */
-		fid_max = ((msr.lo >> 8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */
-		if (fid_max >= ((25-4) * 2)) {
-			fid_max = (10-4) * 2; /* hard set to 2G */
+	if (fid_max >= ((25 - 4) * 2)) {	/* FX max fid is 5G */
+		fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2;	/* maxFID = minFID + 1G */
+		if (fid_max >= ((25 - 4) * 2)) {
+			fid_max = (10 - 4) * 2;	/* hard set to 2G */
 		}
 	}
 #endif
-	vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid
-	fv.common_fidvid = (fid_max << 8)|(vid_max << 16);
-
+	vid_max = ((msr.hi >> (48 - 32)) & 0x3f);	//max vid
+	fv.common_fidvid = (fid_max << 8) | (vid_max << 16);
 
 	/* for all APs (We know the APIC ID of all APs even the APIC ID is lifted)
 	 * remote read from AP about max fid/vid */
 
 	/* let all ap trains to state 1 */
-	lapic_write(LAPIC_MSG_REG,  (bsp_apicid << 24) | 1);
+	lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
 
 	/* calculate the common max fid/vid that could be used for 
 	 * all APs and BSP */
-#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 	ap_apicidx.num = 0;
 
-	for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
+	for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
 
 	for (i = 0; i < ap_apicidx.num; i++) {
 		init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
 	}
 #else
-	for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
+	for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
 #endif
 
-
 #if 0
 	unsigned fid, vid;
 	/* Can we use max only? So we can only set fid in one around,
 	 * otherwise we need to set that to max after raminit */
 	/* set fid vid to DQS training required */
-	fid = (fv.common_fidvid >> 8)  & 0x3f;
+	fid = (fv.common_fidvid >> 8) & 0x3f;
 	vid = (fv.common_fidvid >> 16) & 0x3f;
 
-	if (fid > (10-4) * 2) {
-		fid = (10-4) * 2; // x10
+	if (fid > (10 - 4) * 2) {
+		fid = (10 - 4) * 2;	// x10
 	}
 
 	if (vid >= 0x1f) {
-		vid += 4; /* unit is 12.5mV */
+		vid += 4;	/* unit is 12.5mV */
 	} else {
-		vid += 2; /* unit is 25mV */
+		vid += 2;	/* unit is 25mV */
 	}
 
-	fv.common_fidvid = (fid<<8) | (vid<<16);
+	fv.common_fidvid = (fid << 8) | (vid << 16);
 
 	print_debug_fv("common_fidvid=", fv.common_fidvid);
 
 #endif
 
-#if K8_SET_FIDVID_ONE_BY_ONE == 1
+#if SET_FIDVID_ONE_BY_ONE == 1
 	/* set BSP fid and vid */
 	print_debug_fv("bsp apicid=", bsp_apicid);
 	fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@@ -595,15 +601,15 @@
 	fv.common_fidvid &= 0xffff00;
 
 	/* set state 2 allow is in init_fidvid_bsp_stage2 */
-#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
 	for (i = 0; i < ap_apicidx.num; i++) {
 		init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
 	}
 #else
-	for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
+	for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
 #endif
 
-#if K8_SET_FIDVID_ONE_BY_ONE == 0
+#if SET_FIDVID_ONE_BY_ONE == 0
 	/* set BSP fid and vid */
 	print_debug_fv("bsp apicid=", bsp_apicid);
 	fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@@ -616,7 +622,5 @@
 
 	/* here wait a while, so last ap could read pack, and stop it, don't
 	 * call init_timer too early or just don't use init_timer */
-
 }
-
 #endif

Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -1,17 +1,17 @@
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
-#ifndef K8_SET_FIDVID
+#ifndef SET_FIDVID
 	#if CONFIG_K8_REV_F_SUPPORT == 0
-		#define K8_SET_FIDVID 0
+		#define SET_FIDVID 0
 	#else
 		// for rev F, need to set FID to max
-		#define K8_SET_FIDVID 1
+		#define SET_FIDVID 1
 	#endif
 	
 #endif
 
-#ifndef K8_SET_FIDVID_CORE0_ONLY
+#ifndef SET_FIDVID_CORE0_ONLY
 	/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/
-       	#define K8_SET_FIDVID_CORE0_ONLY 1
+       	#define SET_FIDVID_CORE0_ONLY 1
 #endif
 
 static inline void print_initcpu8 (const char *strval, unsigned val)
@@ -149,7 +149,7 @@
 #define LAPIC_MSG_REG 0x380
 
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
 #endif
 
@@ -302,8 +302,8 @@
 		if(apicid != bsp_apicid) {
 			unsigned timeout=1;
 			unsigned loop = 100;
-	#if K8_SET_FIDVID == 1
-		#if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1)
+	#if SET_FIDVID == 1
+		#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
 			if(id.coreid == 0 ) // only need set fid for core0
 		#endif 
        		                init_fidvid_ap(bsp_apicid, apicid);

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -34,8 +34,8 @@
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -208,7 +208,7 @@
 	rs780_early_setup();
 	sb700_early_setup();
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -164,7 +164,7 @@
 
         int needs_reset;
         unsigned bsp_apicid = 0;
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	struct cpuid_result cpuid1;
 #endif
 
@@ -228,7 +228,7 @@
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -34,8 +34,8 @@
 #define FAM10_ALLOCATE_IO_RANGE 0
 
 //used by init_cpus and fidvid
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -211,7 +211,7 @@
 
 	post_code(0x38);
 
- #if FAM10_SET_FIDVID == 1
+ #if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -19,7 +19,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -32,10 +32,10 @@
 #define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -32,10 +32,10 @@
 #define QRANK_DIMM_SUPPORT 1
 
 /* Used by init_cpus and fidvid */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -32,9 +32,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -235,7 +235,7 @@
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -249,7 +249,7 @@
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -36,9 +36,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -252,7 +252,7 @@
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 	bcm5785_early_setup();
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -10,9 +10,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -188,7 +188,7 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -19,7 +19,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -33,10 +33,10 @@
 #endif
 
 /* Used by init_cpus and fidvid. */
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 
 /* If we want to wait for core1 done before DQS training, set it to 0. */
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -214,7 +214,7 @@
 	/* Set up chains and store link pair for optimization later. */
 	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	{
 		msr_t msr = rdmsr(0xc0010042);
 		print_debug("begin msr fid, vid ");

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -35,9 +35,9 @@
 //#define K8_ALLOCATE_IO_RANGE 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>
@@ -221,7 +221,7 @@
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 #endif
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -31,9 +31,9 @@
 #define QRANK_DIMM_SUPPORT 1
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #include <stdint.h>
 #include <string.h>

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -248,7 +248,7 @@
 
 	post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -236,7 +236,7 @@
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -27,9 +27,9 @@
 #endif
 
 // used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -295,7 +295,7 @@
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -223,7 +223,7 @@
         /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
         {
                 msr_t msr;

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -235,7 +235,7 @@
 
  post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #include <stdint.h>
 #include <string.h>
@@ -280,7 +280,7 @@
 
  post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
  msr = rdmsr(0xc0010071);
  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -18,7 +18,7 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,9 +30,9 @@
 #endif
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
+#define SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
+#define SET_FIDVID_CORE0_ONLY 1
 
 #if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@@ -232,7 +232,7 @@
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if K8_SET_FIDVID == 1
+#if SET_FIDVID == 1
 
 	{
 		msr_t msr;

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Thu Apr  8 17:06:44 2010	(r5380)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Thu Apr  8 17:09:53 2010	(r5381)
@@ -30,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -243,7 +243,7 @@
 
 	post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 



From svn at coreboot.org  Thu Apr  8 17:12:19 2010
From: svn at coreboot.org (repository service)
Date: Thu, 08 Apr 2010 17:12:19 +0200
Subject: [coreboot] [commit] r5382 - in trunk/src: cpu/amd/model_10xxx
	cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdfam10
	northbridge/amd/amdmct/mct
Message-ID: <E1NztP1-00073x-9M@ra.coresystems.de>

Author: myles
Date: Thu Apr  8 17:12:18 2010
New Revision: 5382
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5382

Log:
Cosmetically make init_cpus more similar for fam10 and K8.

Remove some fam10 warnings.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Myles Watson <mylesgw at gmail.com>

Modified:
   trunk/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
   trunk/src/cpu/amd/model_fxx/init_cpus.c
   trunk/src/include/cpu/amd/model_10xxx_msr.h
   trunk/src/include/cpu/amd/model_fxx_rev.h
   trunk/src/northbridge/amd/amdfam10/northbridge.c
   trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c
   trunk/src/northbridge/amd/amdmct/mct/mct_d.h
   trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c
   trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c
   trunk/src/northbridge/amd/amdmct/mct/mctsrc.c

Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:09:53 2010	(r5381)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c	Thu Apr  8 17:12:18 2010	(r5382)
@@ -26,33 +26,10 @@
 
 #ifndef SET_FIDVID_CORE0_ONLY
 	/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
-	   Need to do every AP to set common FID/VID*/
+	   Need to do every AP to set common FID/VID */
 	#define SET_FIDVID_CORE0_ONLY 0
 #endif
 
-static void print_initcpu8 (const char *strval, u8 val)
-{
-	printk(BIOS_DEBUG, "%s%02x\n", strval, val);
-}
-
-static void print_initcpu8_nocr (const char *strval, u8 val)
-{
-	printk(BIOS_DEBUG, "%s%02x", strval, val);
-}
-
-
-static void print_initcpu16 (const char *strval, u16 val)
-{
-	printk(BIOS_DEBUG, "%s%04x\n", strval, val);
-}
-
-
-static void print_initcpu(const char *strval, u32 val)
-{
-	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
-}
-
-
 void update_microcode(u32 cpu_deviceid);
 static void prep_fid_change(void);
 static void init_fidvid_stage2(u32 apicid, u32 nodeid);
@@ -65,14 +42,13 @@
 	msr_t msr;
 	msr = rdmsr(NB_CFG_MSR);
 	// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
-	msr.hi |= (1<<(46-32));
+	msr.hi |= (1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 }
 #else
 static void set_EnableCf8ExtCfg(void) { }
 #endif
 
-
 /*[39:8] */
 #define PCI_MMIO_BASE 0xfe000000
 /* because we will use gs to store hi, so need to make sure lo can start
@@ -85,34 +61,31 @@
 	msr = rdmsr(0xc0010058);
 	msr.lo &= ~(0xfff00000 | (0xf << 2));
 	// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
-	msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
+	msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
 	msr.hi &= ~(0x0000ffff);
-	msr.hi |= (PCI_MMIO_BASE >> (32-8));
-	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
+	msr.hi |= (PCI_MMIO_BASE >> (32 - 8));
+	wrmsr(0xc0010058, msr);	// MMIO Config Base Address Reg
 
 	//mtrr for that range?
 	// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
 
 	set_wrap32dis();
 
-	msr.hi = (PCI_MMIO_BASE >> (32-8));
+	msr.hi = (PCI_MMIO_BASE >> (32 - 8));
 	msr.lo = 0;
-	wrmsr(0xc0000101, msr); //GS_Base Reg
-
-
+	wrmsr(0xc0000101, msr);	//GS_Base Reg
 
 #endif
 }
 
-
-typedef void (*process_ap_t)(u32 apicid, void *gp);
+typedef void (*process_ap_t) (u32 apicid, void *gp);
 
 //core_range = 0 : all cores
 //core range = 1 : core 0 only
 //core range = 2 : cores other than core0
 
-static void for_each_ap(u32 bsp_apicid, u32 core_range,
-				process_ap_t process_ap, void *gp)
+static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
+			void *gp)
 {
 	// here assume the OS don't change our apicid
 	u32 ap_apicid;
@@ -122,7 +95,7 @@
 	u32 disable_siblings;
 	u32 cores_found;
 	u32 nb_cfg_54;
-	int i,j;
+	int i, j;
 	u32 ApicIdCoreIdSize;
 
 	/* get_nodes define in ht_wrapper.c */
@@ -130,8 +103,8 @@
 
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
 
-#if CONFIG_LOGICAL_CPUS == 1
-	if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
+#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
+	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 mean multi core
 		disable_siblings = 1;
 	}
 #endif
@@ -141,10 +114,10 @@
 	nb_cfg_54 = read_nb_cfg_54();
 
 	ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
-	if(ApicIdCoreIdSize) {
+	if (ApicIdCoreIdSize) {
 		siblings = ((1 << ApicIdCoreIdSize) - 1);
 	} else {
-		siblings = 3; //quad core
+		siblings = 3;	//quad core
 	}
 
 	for (i = 0; i < nodes; i++) {
@@ -158,24 +131,26 @@
 			jstart = 0;
 		}
 
-		if (disable_siblings || (core_range==1)) {
+		if (disable_siblings || (core_range == 1)) {
 			jend = 0;
 		} else {
 			jend = cores_found;
 		}
 
-
 		for (j = jstart; j <= jend; j++) {
-			ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
+			ap_apicid =
+			    i * (nb_cfg_54 ? (siblings + 1) : 1) +
+			    j * (nb_cfg_54 ? 1 : 64);
 
-		#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
-			#if CONFIG_LIFT_BSP_APIC_ID == 0
-			if( (i != 0) || (j != 0)) /* except bsp */
-			#endif
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG_LIFT_BSP_APIC_ID == 0
+			if ((i != 0) || (j != 0))	/* except bsp */
+#endif
 				ap_apicid += CONFIG_APIC_ID_OFFSET;
-		#endif
+#endif
 
-			if(ap_apicid == bsp_apicid) continue;
+			if (ap_apicid == bsp_apicid)
+				continue;
 
 			process_ap(ap_apicid, gp);
 
@@ -183,8 +158,7 @@
 	}
 }
 
-/* FIXME: Duplicate of what is in lapic.h? */
-static int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 {
 	int timeout;
 	u32 status;
@@ -192,8 +166,9 @@
 	lapic_wait_icr_idle();
 	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 	lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
-	timeout = 0;
 
+/* Extra busy check compared to lapic.h */
+	timeout = 0;
 	do {
 		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 	} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
@@ -212,31 +187,33 @@
 	return result;
 }
 
-
 /* Use the LAPIC timer count register to hold each cores init status */
 #define LAPIC_MSG_REG 0x380
 
-
 #if SET_FIDVID == 1
 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
-static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
+static inline __attribute__ ((always_inline))
+void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
+				const char *str)
 {
-		printk(BIOS_DEBUG, "%s --- {	 APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
+	printk(BIOS_DEBUG,
+	       "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str,
+	       apicid, id.nodeid, id.coreid);
 }
 
-
-static unsigned wait_cpu_state(u32 apicid, u32 state)
+static u32 wait_cpu_state(u32 apicid, u32 state)
 {
 	u32 readback = 0;
 	u32 timeout = 1;
 	int loop = 4000000;
 	while (--loop > 0) {
-		if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) continue;
+		if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0)
+			continue;
 		if ((readback & 0x3f) == state) {
 			timeout = 0;
-			break; //target cpu is in stage started
+			break;	//target cpu is in stage started
 		}
 	}
 	if (timeout) {
@@ -248,30 +225,26 @@
 	return timeout;
 }
 
-
-static void wait_ap_started(u32 ap_apicid, void *gp )
+static void wait_ap_started(u32 ap_apicid, void *gp)
 {
 	u32 timeout;
-	timeout = wait_cpu_state(ap_apicid, 0x13); // started
-	if(timeout) {
-		print_initcpu8_nocr("* AP ", ap_apicid);
-		print_initcpu(" didn't start timeout:", timeout);
-	}
-	else {
-		print_initcpu8_nocr("AP started: ", ap_apicid);
+	timeout = wait_cpu_state(ap_apicid, 0x13);	// started
+	printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
+	if (timeout) {
+		printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
+	} else {
+		printk(BIOS_DEBUG, "started\n");
 	}
 }
 
-
 static void wait_all_other_cores_started(u32 bsp_apicid)
 {
 	// all aps other than core0
-	print_debug("started ap apicid: ");
-	for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
-	print_debug("\n");
+	printk(BIOS_DEBUG, "started ap apicid: ");
+	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
+	printk(BIOS_DEBUG, "\n");
 }
 
-
 static void allow_all_aps_stop(u32 bsp_apicid)
 {
 	/* Called by the BSP to indicate AP can stop */
@@ -292,7 +265,6 @@
 	pci_write_config32(NODE_HT(node), 0x68, val);
 }
 
-
 static void STOP_CAR_AND_CPU(void)
 {
 	msr_t msr;
@@ -302,12 +274,13 @@
 	msr.lo &= ~(1 << ClLinesToNbDis);
 	wrmsr(BU_CFG2, msr);
 
-	disable_cache_as_ram(); // inline
+	disable_cache_as_ram();	// inline
+	/* stop all cores except node0/core0 the bsp .... */
 	stop_this_cpu();
 }
 
 #if RAMINIT_SYSINFO == 1
-static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo)
+static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 #else
 static u32 init_cpus(u32 cpu_init_detectedx)
 #endif
@@ -320,7 +293,7 @@
 	 * already set early mtrr in cache_as_ram.inc
 	 */
 
-	/* enable access pci conf via mmio*/
+	/* enable access pci conf via mmio */
 	set_pci_mmio_conf_reg();
 
 	/* that is from initial apicid, we need nodeid and coreid
@@ -328,36 +301,35 @@
 	id = get_node_core_id_x();
 
 	/* NB_CFG MSR is shared between cores, so we need make sure
-	  core0 is done at first --- use wait_all_core0_started  */
-	if(id.coreid == 0) {
-		set_apicid_cpuid_lo(); /* only set it on core0 */
-		set_EnableCf8ExtCfg(); /* only set it on core0 */
-		#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+	   core0 is done at first --- use wait_all_core0_started  */
+	if (id.coreid == 0) {
+		set_apicid_cpuid_lo();	/* only set it on core0 */
+		set_EnableCf8ExtCfg();	/* only set it on core0 */
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
 		enable_apic_ext_id(id.nodeid);
-		#endif
+#endif
 	}
 
 	enable_lapic();
 
-
 #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
 	u32 initial_apicid = get_initial_apicid();
 
-	#if CONFIG_LIFT_BSP_APIC_ID == 0
-	if( initial_apicid != 0 ) // other than bsp
-	#endif
+#if CONFIG_LIFT_BSP_APIC_ID == 0
+	if (initial_apicid != 0)	// other than bsp
+#endif
 	{
 		/* use initial apic id to lift it */
 		u32 dword = lapic_read(LAPIC_ID);
 		dword &= ~(0xff << 24);
-		dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
+		dword |=
+		    (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
 
 		lapic_write(LAPIC_ID, dword);
 	}
-
-	#if CONFIG_LIFT_BSP_APIC_ID == 1
+#if CONFIG_LIFT_BSP_APIC_ID == 1
 	bsp_apicid += CONFIG_APIC_ID_OFFSET;
-	#endif
+#endif
 
 #endif
 
@@ -365,31 +337,28 @@
 	apicid = lapicid();
 
 	// show our apicid, nodeid, and coreid
-	if( id.coreid==0 ) {
-		if (id.nodeid!=0) //all core0 except bsp
+	if (id.coreid == 0) {
+		if (id.nodeid != 0)	//all core0 except bsp
 			print_apicid_nodeid_coreid(apicid, id, " core0: ");
-	}
-	else { //all other cores
+	} else {		//all other cores
 		print_apicid_nodeid_coreid(apicid, id, " corex: ");
 	}
 
-
 	if (cpu_init_detectedx) {
-		print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
-		print_debug("\nIssuing SOFT_RESET...\n");
+		print_apicid_nodeid_coreid(apicid, id,
+					   "\n\n\nINIT detected from ");
+		printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
 		soft_reset();
 	}
 
-	if(id.coreid == 0) {
-		if(!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets?
-			distinguish_cpu_resets(id.nodeid); // Also indicates we are started
+	if (id.coreid == 0) {
+		if (!(warm_reset_detect(id.nodeid)))	//FIXME: INIT is checked above but check for more resets?
+			distinguish_cpu_resets(id.nodeid);	// Also indicates we are started
 	}
-
 	// Mark the core as started.
 	lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x13);
 
-
-	if(apicid != bsp_apicid) {
+	if (apicid != bsp_apicid) {
 		/* Setup each AP's cores MSRs.
 		 * This happens after HTinit.
 		 * The BSP runs this code in it's own path.
@@ -397,20 +366,24 @@
 		update_microcode(cpuid_eax(1));
 		cpuSetAMDMSR();
 
-
 #if SET_FIDVID == 1
-	#if (CONFIG_LOGICAL_CPUS == 1)  && (SET_FIDVID_CORE0_ONLY == 1)
+#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
 		// Run on all AP for proper FID/VID setup.
-		if(id.coreid == 0 ) // only need set fid for core0
-	#endif
+		if (id.coreid == 0)	// only need set fid for core0
+#endif
 		{
-		// check warm(bios) reset to call stage2 otherwise do stage1
+			// check warm(bios) reset to call stage2 otherwise do stage1
 			if (warm_reset_detect(id.nodeid)) {
-				printk(BIOS_DEBUG, "init_fidvid_stage2 apicid: %02x\n", apicid);
+				printk(BIOS_DEBUG,
+				       "init_fidvid_stage2 apicid: %02x\n",
+				       apicid);
 				init_fidvid_stage2(apicid, id.nodeid);
 			} else {
-				printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid);
-				init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
+				printk(BIOS_DEBUG,
+				       "init_fidvid_ap(stage1) apicid: %02x\n",
+				       apicid);
+				init_fidvid_ap(bsp_apicid, apicid, id.nodeid,
+					       id.coreid);
 			}
 		}
 #endif
@@ -424,13 +397,14 @@
 		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
 		STOP_CAR_AND_CPU();
-		printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid);
+		printk(BIOS_DEBUG,
+		       "\nAP %02x should be halted but you are reading this....\n",
+		       apicid);
 	}
 
 	return bsp_apicid;
 }
 
-
 static u32 is_core0_started(u32 nodeid)
 {
 	u32 htic;
@@ -441,21 +415,22 @@
 	return htic;
 }
 
-
 static void wait_all_core0_started(void)
 {
 	/* When core0 is started, it will distingush_cpu_resets
-	  . So wait for that to finish */
+	 * So wait for that to finish */
 	u32 i;
 	u32 nodes = get_nodes();
 
-	printk(BIOS_DEBUG, "Wait all core0s started \n");
-	for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
-		while(!is_core0_started(i)) {}
-		print_initcpu8("  Core0 started on node: ", i);
+	printk(BIOS_DEBUG, "core0 started: ");
+	for (i = 1; i < nodes; i++) {	// skip bsp, because it is running on bsp
+		while (!is_core0_started(i)) {
+		}
+		printk(BIOS_DEBUG, " %02x", i);
 	}
-	printk(BIOS_DEBUG, "Wait all core0s started done\n");
+	printk(BIOS_DEBUG, "\n");
 }
+
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 /**
  * void start_node(u32 node)
@@ -480,14 +455,13 @@
 #endif
 
 	/* Allow APs to make requests (ROM fetch) */
-	val=pci_read_config32(NODE_HT(node), 0x6c);
+	val = pci_read_config32(NODE_HT(node), 0x6c);
 	val &= ~(1 << 1);
 	pci_write_config32(NODE_HT(node), 0x6c, val);
 
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-
 /**
  * static void setup_remote_node(u32 node)
  *
@@ -517,7 +491,7 @@
 	printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
 
 	/* copy the default resource map from node 0 */
-	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
+	for (i = 0; i < ARRAY_SIZE(pci_reg); i++) {
 		u32 value;
 		u16 reg;
 		reg = pci_reg[i];
@@ -527,7 +501,7 @@
 	}
 	printk(BIOS_DEBUG, " done\n");
 }
-#endif	/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
+#endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
 static void AMD_Errata281(u8 node, u32 revision, u32 platform)
 {
@@ -546,7 +520,8 @@
 		/* For each node we need to check for a "broken" node */
 		if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) {
 			for (i = 0; i < nodes; i++) {
-				if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) {
+				if (mctGetLogicalCPUID(i) &
+				    (AMD_DR_B0 | AMD_DR_B1)) {
 					mixed = 1;
 					break;
 				}
@@ -590,7 +565,6 @@
 	}
 }
 
-
 static void AMD_Errata298(void)
 {
 	/* Workaround for L2 Eviction May Occur during operation to
@@ -612,36 +586,35 @@
 
 	if (affectedRev) {
 		msr = rdmsr(HWCR);
-		msr.lo |= 0x08;		/* Set TlbCacheDis bit[3] */
+		msr.lo |= 0x08;	/* Set TlbCacheDis bit[3] */
 		wrmsr(HWCR, msr);
 
 		msr = rdmsr(BU_CFG);
-		msr.lo |= 0x02;		/* Set TlbForceMemTypeUc bit[1] */
+		msr.lo |= 0x02;	/* Set TlbForceMemTypeUc bit[1] */
 		wrmsr(BU_CFG, msr);
 
 		msr = rdmsr(OSVW_ID_Length);
-		msr.lo |= 0x01;		/* OS Visible Workaround - MSR */
+		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
 		wrmsr(OSVW_ID_Length, msr);
 
 		msr = rdmsr(OSVW_Status);
-		msr.lo |= 0x01;		/* OS Visible Workaround - MSR */
+		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
 		wrmsr(OSVW_Status, msr);
 	}
 
 	if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) {
 		msr = rdmsr(OSVW_ID_Length);
-		msr.lo |= 0x01;		/* OS Visible Workaround - MSR */
+		msr.lo |= 0x01;	/* OS Visible Workaround - MSR */
 		wrmsr(OSVW_ID_Length, msr);
 
 	}
 }
 
-
-u32 get_platform_type(void)
+static u32 get_platform_type(void)
 {
 	u32 ret = 0;
 
-	switch(SYSTEM_TYPE) {
+	switch (SYSTEM_TYPE) {
 	case 1:
 		ret |= AMD_PTYPE_DSK;
 		break;
@@ -663,8 +636,7 @@
 	return ret;
 }
 
-
-void AMD_SetupPSIVID_d (u32 platform_type, u8 node)
+static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
 {
 	u32 dword;
 	int i;
@@ -672,27 +644,26 @@
 
 	if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) {
 
-	/* The following code sets the PSIVID to the lowest support P state
-	 * assuming that the VID for the lowest power state is below
-	 * the VDD voltage regulator threshold. (This also assumes that there
-	 * is a Pstate lower than P0)
-	 */
+		/* The following code sets the PSIVID to the lowest support P state
+		 * assuming that the VID for the lowest power state is below
+		 * the VDD voltage regulator threshold. (This also assumes that there
+		 * is a Pstate lower than P0)
+		 */
 
-		for( i = 4; i >= 0; i--) {
+		for (i = 4; i >= 0; i--) {
 			msr = rdmsr(PS_REG_BASE + i);
 			/*  Pstate valid? */
 			if (msr.hi & PS_EN_MASK) {
-				dword = pci_read_config32(NODE_PCI(i,3), 0xA0);
+				dword = pci_read_config32(NODE_PCI(i, 3), 0xA0);
 				dword &= ~0x7F;
 				dword |= (msr.lo >> 9) & 0x7F;
-				pci_write_config32(NODE_PCI(i,3), 0xA0, dword);
+				pci_write_config32(NODE_PCI(i, 3), 0xA0, dword);
 				break;
 			}
 		}
 	}
 }
 
-
 /**
  * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
  *  HT Phy operations are not valid on links that aren't present, so this
@@ -700,29 +671,29 @@
  *
  * Returns the offset of the link register.
  */
-BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset)
+static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
 {
-       u32 reg;
+	u32 reg;
 	u32 val;
 
 	/* get start of CPU HT Host Capabilities */
 	val = pci_read_config32(NODE_PCI(node, 0), 0x34);
-       val &= 0xFF;  //reg offset of first link
+	val &= 0xFF;		//reg offset of first link
 
 	cap_count++;
 
 	/* Traverse through the capabilities. */
 	do {
-               reg = pci_read_config32(NODE_PCI(node, 0), val);
+		reg = pci_read_config32(NODE_PCI(node, 0), val);
 		/* Is the capability block a HyperTransport capability block? */
-               if ((reg & 0xFF) == 0x08) {
+		if ((reg & 0xFF) == 0x08) {
 			/* Is the HT capability block an HT Host Capability? */
-                       if ((reg & 0xE0000000) == (1 << 29))
+			if ((reg & 0xE0000000) == (1 << 29))
 				cap_count--;
 		}
 
-               if(cap_count)
-                   val = (reg >> 8)  & 0xFF; //update reg offset
+		if (cap_count)
+			val = (reg >> 8) & 0xFF;	//update reg offset
 	} while (cap_count && val);
 
 	*offset = (u8) val;
@@ -734,14 +705,13 @@
 		return FALSE;
 }
 
-
 /**
  * AMD_checkLinkType - Compare desired link characteristics using a logical
  *     link type mask.
  *
  * Returns the link characteristic mask.
  */
-u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff)
+static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
 {
 	u32 val;
 	u32 linktype = 0;
@@ -765,11 +735,10 @@
 		else
 			linktype |= HTPHY_LINKTYPE_HT1;
 
-
 		/* Check ganged */
 		val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170);
 
-		if ( val & 1)
+		if (val & 1)
 			linktype |= HTPHY_LINKTYPE_GANGED;
 		else
 			linktype |= HTPHY_LINKTYPE_UNGANGED;
@@ -777,12 +746,11 @@
 	return linktype;
 }
 
-
 /**
  * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update
  *   a phy setting for that link.
  */
-void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry)
+static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
 {
 	u32 phyReg;
 	u32 phyBase;
@@ -792,8 +760,7 @@
 	if (link > 3)
 		link -= 4;
 
-	phyBase = ((u32)link << 3) | 0x180;
-
+	phyBase = ((u32) link << 3) | 0x180;
 
 	/* Get the portal control register's initial value
 	 * and update it to access the desired phy register
@@ -834,7 +801,6 @@
 	} while (!(val & HTPHY_IS_COMPLETE_MASK));
 }
 
-
 void cpuSetAMDMSR(void)
 {
 	/* This routine loads the CPU with default settings in fam10_msr_default
@@ -852,7 +818,7 @@
 	revision = mctGetLogicalCPUID(0xFF);
 	platform = get_platform_type();
 
-	for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
+	for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
 		if ((fam10_msr_default[i].revision & revision) &&
 		    (fam10_msr_default[i].platform & platform)) {
 			msr = rdmsr(fam10_msr_default[i].msr);
@@ -868,8 +834,7 @@
 	printk(BIOS_DEBUG, " done\n");
 }
 
-
-void cpuSetAMDPCI(u8 node)
+static void cpuSetAMDPCI(u8 node)
 {
 	/* This routine loads the CPU with default settings in fam10_pci_default
 	 * table . It must be run after Cache-As-RAM has been enabled, and
@@ -883,39 +848,41 @@
 
 	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
 
-
 	revision = mctGetLogicalCPUID(node);
 	platform = get_platform_type();
 
 	AMD_SetupPSIVID_d(platform, node);	/* Set PSIVID offset which is not table driven */
 
-	for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
+	for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
 		if ((fam10_pci_default[i].revision & revision) &&
 		    (fam10_pci_default[i].platform & platform)) {
 			val = pci_read_config32(NODE_PCI(node,
-				fam10_pci_default[i].function),
-				fam10_pci_default[i].offset);
+							 fam10_pci_default[i].
+							 function),
+						fam10_pci_default[i].offset);
 			val &= ~fam10_pci_default[i].mask;
 			val |= fam10_pci_default[i].data;
 			pci_write_config32(NODE_PCI(node,
-				fam10_pci_default[i].function),
-				fam10_pci_default[i].offset, val);
+						    fam10_pci_default[i].
+						    function),
+					   fam10_pci_default[i].offset, val);
 		}
 	}
 
-	for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
+	for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
 		if ((fam10_htphy_default[i].revision & revision) &&
 		    (fam10_htphy_default[i].platform & platform)) {
 			/* HT Phy settings either apply to both sublinks or have
 			 * separate registers for sublink zero and one, so there
 			 * will be two table entries. So, here we only loop
-			 cd t	* through the sublink zeros in function zero.
+			 cd t   * through the sublink zeros in function zero.
 			 */
 			for (j = 0; j < 4; j++) {
 				if (AMD_CpuFindCapability(node, j, &offset)) {
 					if (AMD_checkLinkType(node, j, offset)
 					    & fam10_htphy_default[i].linktype) {
-						AMD_SetHtPhyRegister(node, j, i);
+						AMD_SetHtPhyRegister(node, j,
+								     i);
 					}
 				} else {
 					/* No more capabilities,
@@ -932,14 +899,13 @@
 	AMD_Errata281(node, revision, platform);
 
 	/* FIXME: if the dct phy doesn't init correct it needs to reset.
-	if (revision & (AMD_DR_B2 | AMD_DR_B3))
-		dctPhyDiag(); */
+	   if (revision & (AMD_DR_B2 | AMD_DR_B3))
+	   dctPhyDiag(); */
 
 	printk(BIOS_DEBUG, " done\n");
 }
 
-
-void cpuInitializeMCA(void)
+static void cpuInitializeMCA(void)
 {
 	/* Clears Machine Check Architecture (MCA) registers, which power on
 	 * containing unknown data, on currently running processor.
@@ -951,30 +917,29 @@
 	u32 reg;
 	u8 i;
 
-	if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */
+	if (cpuid_edx(1) & 0x4080) {	/* MCE and MCA (edx[7] and edx[14]) */
 		msr = rdmsr(MCG_CAP);
-		if (msr.lo & MCG_CTL_P){	/* MCG_CTL_P bit is set? */
+		if (msr.lo & MCG_CTL_P) {	/* MCG_CTL_P bit is set? */
 			msr.lo &= 0xFF;
 			msr.lo--;
-			msr.lo <<= 2;		/* multiply the count by 4 */
+			msr.lo <<= 2;	/* multiply the count by 4 */
 			reg = MC0_STA + msr.lo;
 			msr.lo = msr.hi = 0;
-			for (i=0; i < 4; i++) {
-				wrmsr (reg, msr);
-				reg -=4;	/* Touch status regs for each bank */
+			for (i = 0; i < 4; i++) {
+				wrmsr(reg, msr);
+				reg -= 4;	/* Touch status regs for each bank */
 			}
 		}
 	}
 }
 
-
 /**
  * finalize_node_setup()
  *
  * Do any additional post HT init
  *
  */
-void finalize_node_setup(struct sys_info *sysinfo)
+static void finalize_node_setup(struct sys_info *sysinfo)
 {
 	u8 i;
 	u8 nodes = get_nodes();
@@ -983,13 +948,12 @@
 #if RAMINIT_SYSINFO == 1
 	/* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
 	reg = pci_read_config32(NODE_HT(0), 0x64);
-	sysinfo->sblk = (reg>>8) & 7;
+	sysinfo->sblk = (reg >> 8) & 7;
 	sysinfo->sbbusn = 0;
 	sysinfo->nodes = nodes;
 	sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
 #endif
 
-
 	for (i = 0; i < nodes; i++) {
 		cpuSetAMDPCI(i);
 	}
@@ -1001,10 +965,9 @@
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 	/* Skip the BSP, start at node 1 */
-	for(i=1; i<nodes; i++) {
+	for (i = 1; i < nodes; i++) {
 		setup_remote_node(i);
 		start_node(i);
 	}
 #endif
 }
-

Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c	Thu Apr  8 17:09:53 2010	(r5381)
+++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c	Thu Apr  8 17:12:18 2010	(r5382)
@@ -38,13 +38,9 @@
 #include <cpu/amd/model_10xxx_msr.h>
 
 extern device_t get_node_pci(u32 nodeid, u32 fn);
-extern int init_processor_name(void);
-
-
 
 #define MCI_STATUS 0x401
 
-
 msr_t rdmsr_amd(u32 index)
 {
 	 msr_t result;
@@ -67,7 +63,7 @@
 }
 
 
-void model_10xxx_init(device_t dev)
+static void model_10xxx_init(device_t dev)
 {
 	u8 i;
 	msr_t msr;

Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:09:53 2010	(r5381)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c	Thu Apr  8 17:12:18 2010	(r5382)
@@ -1,357 +1,344 @@
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID
-	#if CONFIG_K8_REV_F_SUPPORT == 0
-		#define SET_FIDVID 0
-	#else
+#if CONFIG_K8_REV_F_SUPPORT == 0
+	#define SET_FIDVID 0
+#else
 		// for rev F, need to set FID to max
-		#define SET_FIDVID 1
-	#endif
-	
+	#define SET_FIDVID 1
 #endif
 
-#ifndef SET_FIDVID_CORE0_ONLY
-	/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/
-       	#define SET_FIDVID_CORE0_ONLY 1
 #endif
 
-static inline void print_initcpu8 (const char *strval, unsigned val)
-{
-        printk(BIOS_DEBUG, "%s%02x\n", strval, val);
-}
-
-static inline void print_initcpu8_nocr (const char *strval, unsigned val)
-{
-        printk(BIOS_DEBUG, "%s%02x", strval, val);
-}
-
-
-static inline void print_initcpu16 (const char *strval, unsigned val)
-{
-        printk(BIOS_DEBUG, "%s%04x\n", strval, val);
-}
-
-static inline void print_initcpu(const char *strval, unsigned val)
-{
-        printk(BIOS_DEBUG, "%s%08x\n", strval, val);
-}
+#ifndef SET_FIDVID_CORE0_ONLY
+	/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */
+	#define SET_FIDVID_CORE0_ONLY 1
+#endif
 
-typedef void (*process_ap_t)(unsigned apicid, void *gp);
+typedef void (*process_ap_t) (u32 apicid, void *gp);
 
 //core_range = 0 : all cores
 //core range = 1 : core 0 only
 //core range = 2 : cores other than core0
-static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t process_ap, void *gp)
+
+static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
+			void *gp)
 {
 	// here assume the OS don't change our apicid
-	unsigned ap_apicid;
+	u32 ap_apicid;
 
-	unsigned nodes;
-        unsigned siblings = 0;
-        unsigned disable_siblings;
-        unsigned e0_later_single_core;
-        unsigned nb_cfg_54;
-        int i,j;
+	u32 nodes;
+	u32 siblings = 0;
+	u32 disable_siblings;
+	u32 e0_later_single_core;
+	u32 nb_cfg_54;
+	int i, j;
 
 	/* get_nodes define in in_coherent_ht.c */
 	nodes = get_nodes();
 
-        disable_siblings = !CONFIG_LOGICAL_CPUS;
+	disable_siblings = !CONFIG_LOGICAL_CPUS;
+
 #if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
-        if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
-                disable_siblings = 1;
-        }
+	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 mean multi core
+		disable_siblings = 1;
+	}
 #endif
 
 	/* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */
-        nb_cfg_54 = read_nb_cfg_54();
+	nb_cfg_54 = read_nb_cfg_54();
 
-
-        for(i=0; i<nodes;i++) {
+	for (i = 0; i < nodes; i++) {
 		e0_later_single_core = 0;
-                j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
-                if(nb_cfg_54) {
- 	               if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation 
-                       #if CONFIG_K8_REV_F_SUPPORT == 0
-        	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
-                       #else
-                               e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
-                       #endif
-                       } 
-                       if(e0_later_single_core) {
-                                j=1;
-                       }
-                }
-                siblings = j;
-
-                unsigned jstart, jend;
-
-                if(core_range == 2) {
-                        jstart = 1;
-                }
-		else {
+		j = ((pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xe8) >> 12) &
+		     3);
+		if (nb_cfg_54) {
+			if (j == 0) {	// if it is single core, we need to increase siblings for apic calculation
+#if CONFIG_K8_REV_F_SUPPORT == 0
+				e0_later_single_core = is_e0_later_in_bsp(i);	// single core
+#else
+				e0_later_single_core = is_cpu_f0_in_bsp(i);	// We can read cpuid(1) from Func3
+#endif
+			}
+			if (e0_later_single_core) {
+				j = 1;
+			}
+		}
+		siblings = j;
+
+		u32 jstart, jend;
+
+		if (core_range == 2) {
+			jstart = 1;
+		} else {
 			jstart = 0;
 		}
 
-                if(e0_later_single_core || disable_siblings || (core_range==1)) {
-                        jend = 0;
-                } else {
-                        jend = siblings;
-		}	
-		
-	
-                for(j=jstart; j<=jend; j++) {
-
-                        ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
-
-                #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
-			#if CONFIG_LIFT_BSP_APIC_ID == 0
-			if( (i!=0) || (j!=0)) /* except bsp */
-			#endif
-                        	ap_apicid += CONFIG_APIC_ID_OFFSET;
-                #endif
-
-			if(ap_apicid == bsp_apicid) continue;
-
-			process_ap(ap_apicid, gp); 
-
-                }
-        }
-}
+		if (e0_later_single_core || disable_siblings
+		    || (core_range == 1)) {
+			jend = 0;
+		} else {
+			jend = siblings;
+		}
+
+		for (j = jstart; j <= jend; j++) {
+			ap_apicid =
+			    i * (nb_cfg_54 ? (siblings + 1) : 1) +
+			    j * (nb_cfg_54 ? 1 : 8);
+
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_LIFT_BSP_APIC_ID == 0
+			if ((i != 0) || (j != 0))	/* except bsp */
+#endif
+				ap_apicid += CONFIG_APIC_ID_OFFSET;
+#endif
+
+			if (ap_apicid == bsp_apicid)
+				continue;
 
+			process_ap(ap_apicid, gp);
 
-static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue)
-{
-        int timeout;
-        unsigned status;
-        int result;
-        lapic_wait_icr_idle();
-        lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
-        lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
-        timeout = 0;
-
-        do {
-                status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
-        } while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
-
-        timeout = 0;
-        do {
-                status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
-        } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
-
-        result = -1;
-        if (status == LAPIC_ICR_RR_VALID) {
-                *pvalue = lapic_read(LAPIC_RRR);
-                result = 0;
-        }
-        return result;
+		}
+	}
 }
 
-#define LAPIC_MSG_REG 0x380
+static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+{
+	int timeout;
+	u32 status;
+	int result;
+	lapic_wait_icr_idle();
+	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+	lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+
+/* Extra busy check compared to lapic.h */
+	timeout = 0;
+	do {
+		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
+	} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
+
+	timeout = 0;
+	do {
+		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
+	} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
+
+	result = -1;
+
+	if (status == LAPIC_ICR_RR_VALID) {
+		*pvalue = lapic_read(LAPIC_RRR);
+		result = 0;
+	}
+	return result;
+}
 
+#define LAPIC_MSG_REG 0x380
 
 #if SET_FIDVID == 1
-static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
+static void init_fidvid_ap(u32 bsp_apicid, u32 apicid);
 #endif
 
-static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
+static inline __attribute__ ((always_inline))
+void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
+				const char *str)
 {
-                printk(BIOS_DEBUG, "%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
+	printk(BIOS_DEBUG,
+	       "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str,
+	       apicid, id.nodeid, id.coreid);
 }
 
-
-static unsigned wait_cpu_state(unsigned apicid, unsigned state)
+static u32 wait_cpu_state(u32 apicid, u32 state)
 {
-        unsigned readback = 0;
-	unsigned timeout = 1;
+	u32 readback = 0;
+	u32 timeout = 1;
 	int loop = 2000000;
-        while(--loop>0) {
-                if(lapic_remote_read(apicid, LAPIC_MSG_REG, &readback)!=0) continue;
-                if((readback & 0xff) == state) {
+	while (--loop > 0) {
+		if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0)
+			continue;
+		if ((readback & 0xff) == state) {
 			timeout = 0;
-			break; //target cpu is in stage started
+			break;	//target cpu is in stage started
 		}
-        }
-	if(timeout) {
-		if(readback) {
+	}
+	if (timeout) {
+		if (readback) {
 			timeout = readback;
 		}
 	}
 
 	return timeout;
 }
-static void wait_ap_started(unsigned ap_apicid, void *gp )
+
+static void wait_ap_started(u32 ap_apicid, void *gp)
 {
-	unsigned timeout;
-        timeout = wait_cpu_state(ap_apicid, 0x33); // started
-	if(timeout) {
-	        print_initcpu8_nocr("*", ap_apicid);
-	        print_initcpu("*", timeout);
-	}
-	else {
-        	print_initcpu8_nocr(" ", ap_apicid);
+	u32 timeout;
+	timeout = wait_cpu_state(ap_apicid, 0x33);	// started
+	printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
+	if (timeout) {
+		printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
+	} else {
+		printk(BIOS_DEBUG, "started\n");
 	}
 }
 
-static void wait_all_aps_started(unsigned bsp_apicid)
+static void wait_all_aps_started(u32 bsp_apicid)
 {
-        for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
+	for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0);
 }
 
-static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0
+static void wait_all_other_cores_started(u32 bsp_apicid)
 {
-        print_debug("started ap apicid: ");
-        for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
-        print_debug("\n");
+	// all aps other than core0
+	printk(BIOS_DEBUG, "started ap apicid: ");
+	for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0);
+	printk(BIOS_DEBUG, "\n");
 }
 
-static void allow_all_aps_stop(unsigned bsp_apicid)
+static void allow_all_aps_stop(u32 bsp_apicid)
 {
-        lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop
+	// allow aps to stop
+
+	lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44);
 }
 
 static void STOP_CAR_AND_CPU(void)
 {
-	disable_cache_as_ram(); // inline
-	stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
+	disable_cache_as_ram();	// inline
+	/* stop all cores except node0/core0 the bsp .... */
+	stop_this_cpu();
 }
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); 
-#endif
-
 #if RAMINIT_SYSINFO == 1
-static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo)
+static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 #else
-static unsigned init_cpus(unsigned cpu_init_detectedx)
+static u32 init_cpus(u32 cpu_init_detectedx)
 #endif
 {
-		unsigned bsp_apicid = 0;
-		unsigned apicid;
-                struct node_core_id id;
-
-		/* 
-                 * already set early mtrr in cache_as_ram.inc
-		 */
-
-		/* that is from initial apicid, we need nodeid and coreid later */
-		id = get_node_core_id_x(); 
-
-
-                /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started  */
-		if(id.coreid == 0) {
-                	set_apicid_cpuid_lo(); /* only set it on core0 */
-			#if CONFIG_ENABLE_APIC_EXT_ID == 1
-                        enable_apic_ext_id(id.nodeid);
-			#endif
-                }
-
-		enable_lapic();
-//              init_timer(); // We need TMICT to pass msg for FID/VID change
-
-        #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
-		unsigned initial_apicid = get_initial_apicid();	
-                #if CONFIG_LIFT_BSP_APIC_ID == 0
-                if( initial_apicid != 0 ) // other than bsp
-                #endif
-                {
-                                /* use initial apic id to lift it */
-                                uint32_t dword = lapic_read(LAPIC_ID);
-                                dword &= ~(0xff<<24);
-                                dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24);
-
-                                lapic_write(LAPIC_ID, dword);
-                }
-
-                #if CONFIG_LIFT_BSP_APIC_ID == 1
-                bsp_apicid += CONFIG_APIC_ID_OFFSET;
-                #endif
-
-        #endif
-
-		/* get the apicid, it may be lifted already */
-		apicid = lapicid();
-
-#if 0 
-		// show our apicid, nodeid, and coreid
-		if( id.coreid==0 ) {
-			if (id.nodeid!=0) //all core0 except bsp
-				print_apicid_nodeid_coreid(apicid, id, " core0: ");
-		}
-	#if 0 
-                else { //all core1
-			print_a