[coreboot] [commit] r5350 - in trunk/src: cpu/amd/model_gx2 northbridge/amd/amdht northbridge/amd/gx2 southbridge/amd/rs780

[repository service]

Author: stepan
Date: Sat Apr  3 00:31:35 2010
New Revision: 5350
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5350

Log:
remove more warnings.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/cpu/amd/model_gx2/cpubug.c
   trunk/src/northbridge/amd/amdht/h3finit.h
   trunk/src/northbridge/amd/amdht/h3ncmn.c
   trunk/src/northbridge/amd/gx2/northbridgeinit.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c

Modified: trunk/src/cpu/amd/model_gx2/cpubug.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/cpubug.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/cpu/amd/model_gx2/cpubug.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -92,7 +92,7 @@
  *
  ****************************************************************************/
 
-void bug784(void)
+static void bug784(void)
 {
 	msr_t msr;
 	//static char *name = "Geode by NSC";
@@ -133,7 +133,7 @@
  *	Modified:
  *
  **************************************************************************/
-void eng1398(void)
+static void eng1398(void)
 {
 	msr_t msr;
 
@@ -164,7 +164,7 @@
  *	Modified:
  *
  **************************************************************************/
-void
+static void
 eng2900(void)
 {
 	msr_t msr;
@@ -248,7 +248,7 @@
 	}
 }
 
-void bug118253(void)
+static void bug118253(void)
 {
 	/* GLPCI PIO Post Control shouldn't be enabled */
 	msr_t msr;
@@ -258,7 +258,7 @@
 	wrmsr(GLPCI_SPARE, msr);
 }
 
-void bug118339(void)
+static void bug118339(void)
 {
 	/* per AMD, do this always */
 	msr_t msr = {0,0};
@@ -337,7 +337,7 @@
 /**	Modified:*/
 /***/
 /****************************************************************************/
-void disablememoryreadorder(void)
+static void disablememoryreadorder(void)
 {	
 	msr_t msr;
 	msr = rdmsr(MC_CF8F_DATA);

Modified: trunk/src/northbridge/amd/amdht/h3finit.h
==============================================================================
--- trunk/src/northbridge/amd/amdht/h3finit.h	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/amdht/h3finit.h	Sat Apr  3 00:31:35 2010	(r5350)
@@ -353,7 +353,7 @@
 	 *
 	 * ---------------------------------------------------------------------------------------
 	 */
-	BOOL (*AMD_CB_CustomizeTrafficDistribution)();
+	BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
 
 
 	/**----------------------------------------------------------------------------------------

Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c
==============================================================================
--- trunk/src/northbridge/amd/amdht/h3ncmn.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/amdht/h3ncmn.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -1041,7 +1041,7 @@
 
 /**----------------------------------------------------------------------------------------
  *
- * void
+ * static void
  * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
  *
  *  Description:
@@ -1058,7 +1058,7 @@
  *
  * ---------------------------------------------------------------------------------------
  */
-void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
+static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
 {
 	u8 curNode;
 	SBDFO linkBase;

Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c
==============================================================================
--- trunk/src/northbridge/amd/gx2/northbridgeinit.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/northbridge/amd/gx2/northbridgeinit.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -704,7 +704,6 @@
 	int i;
 	msr_t msr;
 	uint8_t SysMemCacheProp;
-	uint8_t RegionProp;
 
 	/* Locate SYSMEM entry in GLIU0table */
 	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {

Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Sat Apr  3 00:13:27 2010	(r5349)
+++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Sat Apr  3 00:31:35 2010	(r5350)
@@ -17,6 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
+#endif
+
 #include "rs780_rev.h"
 
 #define NBHTIU_INDEX		0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
@@ -142,7 +146,7 @@
 	}
 }
 
-static void get_cpu_rev()
+static void get_cpu_rev(void)
 {
 	u32 eax;
 
@@ -168,17 +172,17 @@
 		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
 }
 
-static u8 is_famly10()
+static u8 is_famly10(void)
 {
 	return (cpuid_eax(1) & 0xff00000) != 0;
 }
 
-static u8 l3_cache()
+static u8 l3_cache(void)
 {
 	return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
 }
 
-static u8 cpu_core_number()
+static u8 cpu_core_number(void)
 {
 	return (cpuid_ecx(0x80000008) & 0xFF) + 1;
 }
@@ -226,7 +230,7 @@
 	[0xe] = 0xC6,		/* 2.6Ghz HyperTransport 3 only */
 };
 
-static void rs780_htinit()
+static void rs780_htinit(void)
 {
 	/*
 	 * About HT, it has been done in enumerate_ht_chain().
@@ -325,7 +329,7 @@
 *	Function2: DRAM and HT technology Trace mode configuration
 *	Function3: Miscellaneous configuration
 *******************************************************/
-static void k8_optimization()
+static void k8_optimization(void)
 {
 	device_t k8_f0, k8_f2, k8_f3;
 	msr_t msr;
@@ -367,7 +371,7 @@
 #endif	/* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
-void fam10_optimization()
+void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
 	msr_t msr;