[coreboot] [PATCH] VIA C7 CAR fixes / cleanup
patrick.georgi at coresystems.de
Mon Apr 12 11:56:45 CEST 2010
Am 12.04.2010 06:41, schrieb Kevin O'Connor:
> 00.412: *post ddr_ram_setup()
> 00.415: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000
> 01.369: coreboot-4.0-r5408M Mon Apr 12 00:19:03 EDT 2010 booting...
> Indeed, the time to "Stage:..." is faster than romcc now. Just need
> to fix that delay after "Stage:"..
Your other mail seems to indicate that this is because of the stack at 64MB.
How about this:
While building the romstage, the location and size of the ramstage area
is already known.
- Move the intermediate stack to wherever the ramstage stack resides
(somewhere close to RAMTOP),
- change the stage loaders (copy and ulzma) to leave out %esp..RAMTOP
(with some safety margin below %esp), which should always be "0" anyway, and
- enable caching for RAMBASE..RAMTOP (already done, I think)
we should use a harmless memory area for stack (esp. in light of wakeup
from suspend) and have caching enabled for all relevant memory regions,
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