[coreboot] [PATCH] VIA C7 CAR fixes / cleanup
kevin at koconnor.net
Mon Apr 12 15:39:24 CEST 2010
On Mon, Apr 12, 2010 at 11:56:45AM +0200, Patrick Georgi wrote:
> Am 12.04.2010 06:41, schrieb Kevin O'Connor:
> > Indeed, the time to "Stage:..." is faster than romcc now. Just need
> > to fix that delay after "Stage:"..
> Your other mail seems to indicate that this is because of the stack at 64MB.
That's my guess - I'll try and confirm tonight.
> If we:
> - Move the intermediate stack to wherever the ramstage stack resides
> (somewhere close to RAMTOP),
> - change the stage loaders (copy and ulzma) to leave out %esp..RAMTOP
> (with some safety margin below %esp), which should always be "0" anyway, and
> - enable caching for RAMBASE..RAMTOP (already done, I think)
I didn't understand the first two points. The third point makes sense
- right now on my board RAMBASE is 0x4000 and RAMTOP is 0x200000. So,
if we make sure to cache everything up to RAMTOP and then place the
ulzma stack somewhere in that memory range I think it should work.
Right now, the code in src/cpu/via/car/cache_as_ram.inc isn't setting
up the cache using RAMBASE or RAMTOP - it just does it's own range
(which I think is the first 1Meg and a small part of flash) - it's the
code between "call main" and "call copy_and_run". (BTW, having this
all in one assembler file is much nicer than the old code.)
> we should use a harmless memory area for stack (esp. in light of wakeup
> from suspend) and have caching enabled for all relevant memory regions,
As a side note, for suspend, I wonder if it would be better to not
enable CAR - just unsuspend ram and place the stack in an area of high
memory that was reserved during the initial boot.
More information about the coreboot