[coreboot] [PATCH] stack location

Kevin O'Connor kevin at koconnor.net
Tue Apr 13 02:53:02 CEST 2010

On Mon, Apr 12, 2010 at 05:23:34PM +0200, Stefan Reinauer wrote:
> see patch. Not sure if this area is cached, but I think it should be,
> none the less.

Thanks!  That brings the early timings on epia-cn to:

00.000: <00>
00.005: <00>
00.382: 0
00.382: coreboot-4.0-r5415M Mon Apr 12 20:37:07 EDT 2010 starting...
00.383: *pre enable_smbus()
00.405: *post enable_smbus()
00.409: *pre ddr_ram_setup()
00.420: *post ddr_ram_setup()
00.423: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000
00.469: coreboot-4.0-r5415M Mon Apr 12 20:37:07 EDT 2010 rebooting...

The romcc code is a little faster (~16ms), but that's only because I
hacked it to read the coreboot_ram file into cache while waiting for
the smbus power well to stabilize.  (With car it isn't possible to
seed the cache, but that's not a big deal.)


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