[coreboot] (no subject)
stepan at coresystems.de
Tue Apr 20 00:34:32 CEST 2010
On 4/19/10 11:34 PM, Uwe Hermann wrote:
> On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
>> Signed-off-by: Marc Bertens <mbertens at xs4all.nl>
> Thanks, committed in r5458 with some of the changes I mentioned.
> Sorry for the delay.
> Can you please post lspci -tvnn and some more status info? I'd like
> to add a wiki page for the board, similar to this one:
Just reading that page... it says level 2 cache is not enabled...
However, the cpu driver (model_6xx_init.c) says:
static void model_6xx_init(device_t dev)
/* Turn on caching if we haven't already */
/* Update the microcode */
/* Enable the local cpu apics */
So it should be enough to add your CPU to the cpu_table in order to get
L2 cache enabled.
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