[coreboot] EP80579 reference platform
stefan.reinauer at coresystems.de
Thu Apr 22 22:05:16 CEST 2010
Try tracing the original BIOS and coreboot with SerialICE and compare
the differences ... It's a bunch of work but not as ugly as debugging
ROMCC assembler output... :-) http://www.serialice.com/
On 22.04.2010, at 20:16, Dustin Harrison <dustin.harrison at sutus.com>
> I did a diff of romstage.inc, using the same codebase (rev 5351) the
> only difference between romcc 4051 and 5351 was the timestamp. This
> is consistent with my finding that compiling trunk with an older
> romcc didn't help the situation.
> When I get done with my RAM timing I'll try an svn bisect to narrow
> it down.
> Unfortunately I was not as lucky as Arnaud for timing. I switched
> to 2T and that didn't help. Unfortunately I am using unbuffered
> non-ECC SODIMMs and only have one slot unlike the truxton with ECC
> DIMMs and two slots. The proprietary Truxton BIOS boots this board
> so I know there is hope, just need to nail the settings.
> On 21/04/2010 10:17 PM, Peter Stuge wrote:
>> Dustin Harrison wrote:
>>> if anyone has some ideas I'll give them a shot in between hacking
>>> the RAM.
>> It would be interesting to also look at output from a recent version
>> of romcc compiling the old code, and an old romcc compiling the new
>> code. That could hint to either a romcc bug or something gone bad in
>> the coreboot code.
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