[coreboot] [commit] r5498 - in trunk/src: arch/i386/include/arch arch/i386/init arch/i386/lib arch/i386/llshell cpu/x86/lapic cpu/x86/smm include/cpu/x86
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Sun Apr 25 22:42:03 CEST 2010
Author: stepan
Date: Sun Apr 25 22:42:02 2010
New Revision: 5498
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5498
Log:
drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h"
(which could at some time hold global post code definitions, too)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Added:
trunk/src/include/cpu/x86/post_code.h
Deleted:
trunk/src/arch/i386/include/arch/asm.h
trunk/src/arch/i386/include/arch/intel.h
Modified:
trunk/src/arch/i386/include/arch/cpu.h
trunk/src/arch/i386/init/bootblock_prologue.c
trunk/src/arch/i386/init/crt0_prologue.inc
trunk/src/arch/i386/lib/c_start.S
trunk/src/arch/i386/lib/cpu.c
trunk/src/arch/i386/llshell/console.inc
trunk/src/arch/i386/llshell/llshell.inc
trunk/src/cpu/x86/lapic/secondary.S
trunk/src/cpu/x86/smm/smmhandler.S
trunk/src/cpu/x86/smm/smmrelocate.S
Modified: trunk/src/arch/i386/include/arch/cpu.h
==============================================================================
--- trunk/src/arch/i386/include/arch/cpu.h Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/include/arch/cpu.h Sun Apr 25 22:42:02 2010 (r5498)
@@ -28,6 +28,7 @@
uint32_t ecx;
uint32_t edx;
};
+
/*
* Generic CPUID function
*/
@@ -44,7 +45,6 @@
return result;
}
-
/*
* CPUID functions returning a single datum
*/
@@ -58,6 +58,7 @@
: "ebx", "ecx", "edx");
return eax;
}
+
static inline unsigned int cpuid_ebx(unsigned int op)
{
unsigned int eax, ebx;
@@ -68,6 +69,7 @@
: "ecx", "edx" );
return ebx;
}
+
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ecx;
@@ -78,6 +80,7 @@
: "ebx", "edx" );
return ecx;
}
+
static inline unsigned int cpuid_edx(unsigned int op)
{
unsigned int eax, edx;
@@ -89,8 +92,6 @@
return edx;
}
-
-
#define X86_VENDOR_INVALID 0
#define X86_VENDOR_INTEL 1
#define X86_VENDOR_CYRIX 2
@@ -112,6 +113,7 @@
unsigned vendor;
unsigned device;
};
+
struct cpu_driver {
struct device_operations *ops;
struct cpu_device_id *id_table;
@@ -141,7 +143,6 @@
return ci->index;
}
-
struct cpuinfo_x86 {
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
Modified: trunk/src/arch/i386/init/bootblock_prologue.c
==============================================================================
--- trunk/src/arch/i386/init/bootblock_prologue.c Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/init/bootblock_prologue.c Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,37 +1,28 @@
-/* -*- asm -*-
- * $ $
- *
- */
-
-/*
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
*
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * - Converted to gas assembly, and refitted to work with etherboot.
- * Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- * Eric Biederman 26 Sept 2002
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/post_code.h>
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>
-
-/*
- * This is the entry code the code in .reset section
- * jumps to this address.
- *
- */
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- post_code(0x01) /* delay for chipsets */
+/* This is the entry codde. The code in the .reset section jumps here. */
+
+ post_code(0x01)
Modified: trunk/src/arch/i386/init/crt0_prologue.inc
==============================================================================
--- trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,22 +1,28 @@
-/*
- * Copyright 2002 Eric Biederman
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
*
- * This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <arch/asm.h>
-#include <arch/intel.h>
-#include <console/loglevel.h>
+#include <cpu/x86/post_code.h>
-/*
- * This is the entry code.
- * The code in the .reset section jumps to this address.
- *
- */
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- post_code(0x01) /* delay for chipsets */
+/* This is the entry code. The code in the .reset section jumps here. */
+
+ post_code(0x01)
Modified: trunk/src/arch/i386/lib/c_start.S
==============================================================================
--- trunk/src/arch/i386/lib/c_start.S Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/lib/c_start.S Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,5 +1,4 @@
-#include <arch/asm.h>
-#include <arch/intel.h>
+#include <cpu/x86/post_code.h>
.section ".text"
.code32
Modified: trunk/src/arch/i386/lib/cpu.c
==============================================================================
--- trunk/src/arch/i386/lib/cpu.c Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/lib/cpu.c Sun Apr 25 22:42:02 2010 (r5498)
@@ -238,7 +238,8 @@
get_fms(&c, cpu->device);
- printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
+ printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n",
+ c.x86, c.x86_model, c.x86_mask);
/* Lookup the cpu's operations */
set_cpu_ops(cpu);
Modified: trunk/src/arch/i386/llshell/console.inc
==============================================================================
--- trunk/src/arch/i386/llshell/console.inc Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/llshell/console.inc Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,4 +1,3 @@
-// #include <loglevel.h>
jmp console0
Modified: trunk/src/arch/i386/llshell/llshell.inc
==============================================================================
--- trunk/src/arch/i386/llshell/llshell.inc Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/arch/i386/llshell/llshell.inc Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,3 +1,20 @@
+
+#define RET_LABEL(label) \
+ jmp label##_done
+
+#define CALL_LABEL(label) \
+ jmp label ;\
+label##_done:
+
+#define CALLSP(func) \
+ lea 0f, %esp ; \
+ jmp func ; \
+0:
+
+#define RETSP \
+ jmp *%esp
+
+
#include "console.inc"
#include "pci.inc"
#include "ramtest.inc"
Modified: trunk/src/cpu/x86/lapic/secondary.S
==============================================================================
--- trunk/src/cpu/x86/lapic/secondary.S Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/cpu/x86/lapic/secondary.S Sun Apr 25 22:42:02 2010 (r5498)
@@ -1,7 +1,6 @@
-#include <arch/asm.h>
-#include <arch/intel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
+
.text
.globl _secondary_start, _secondary_start_end
.balign 4096
Modified: trunk/src/cpu/x86/smm/smmhandler.S
==============================================================================
--- trunk/src/cpu/x86/smm/smmhandler.S Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/cpu/x86/smm/smmhandler.S Sun Apr 25 22:42:02 2010 (r5498)
@@ -52,8 +52,6 @@
*
*/
-#include <arch/asm.h>
-
#define LAPIC_ID 0xfee00020
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
Modified: trunk/src/cpu/x86/smm/smmrelocate.S
==============================================================================
--- trunk/src/cpu/x86/smm/smmrelocate.S Sun Apr 25 22:24:09 2010 (r5497)
+++ trunk/src/cpu/x86/smm/smmrelocate.S Sun Apr 25 22:42:02 2010 (r5498)
@@ -19,13 +19,13 @@
* MA 02110-1301 USA
*/
-#include <arch/asm.h>
-
// Make sure no stage 2 code is included:
#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
+// It's needed right now because we get our PM_BASE from
+// here.
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#undef DEBUG_SMM_RELOCATION
Added: trunk/src/include/cpu/x86/post_code.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/include/cpu/x86/post_code.h Sun Apr 25 22:42:02 2010 (r5498)
@@ -0,0 +1,6 @@
+
+
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $0x80
+
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