[coreboot] Porting to RS780/SB700 board
Ed Swierk
eswierk at aristanetworks.com
Wed Apr 28 09:14:00 CEST 2010
I'm attempting to port Coreboot to an Asus M4A78XTD board, which has
an RS780/SB700 chipset with a socket AM3 (Fam10h+DDR3) CPU.
Starting with the tilapia_10h mainboard code, the first problem I'm
hitting occurs very early on: any attempt to call pci_locate_device(),
for example in sb700_lpc_init(), hangs forever (or at least longer
than I'm willing to wait), unless I disable all the PCIe bridges on
the 780 by inserting the following into enable_rs780_dev8():
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x0c, 0, 0x000300fc);
If I leave even one of the bridges enabled, I get the hang. See
section 2.5.6 in
http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf
for a description of this register.
With the PCIe bridges out of the picture, I get through memory
initialization (woo hoo!), but for some reason ram_fill() and
ram_verify() take many minutes to complete, and it hangs shortly
thereafter. Boot log attached.
Any clues would be appreciated!
--Ed
-------------- next part --------------
coreboot-4.0-r5511M Tue Apr 27 23:52:18 PDT 2010 starting...
BSP Family_Model: 00100f43
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810024
F3xD8: 00000510
F3xDC: 0000502c
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
started ap apicid: cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000321 NNNOOODDDEEEIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000213}}} ---------
qqmmmAiPii cccrr0roo1ocscctoooddadereet::: eeedeq
ii*v vvAaaalllPee en0nn2ttt srtrraeeevvvr t ieiidddd
en ==*= A000xxxP11 10000444333s3,t,,a cccruuturerrrrrdee
ttt
pppraaasttt7ccchhh8 0i_iieddd a=r==l 000yxx_x0s00e000000t00u00p00(000000)00
get_cpummmii_icrccerrrooovcc coEooAdddeeeX:=::0 pppxaa1at0tt0ccchhhf 4 3iiidd t
bbttoooC P Uaaappp ppRpelllyyyv =i==s 000 xxKx0800_11100100000.000000
a b666f
m
mi1mmi0circc_rrooopcotoccdooiddmeei:ez ::u autpuidppaddoaantt(et)dee dd
0001xx roosp 7a 8tppcaa0tt_hcp coihhd rii_ i=dd n==i0 tx
_ss 00010010000000b006bb 6 6 s ususcuccscbce7cseess0
e
a
cr
SMRRS yc_upSSuesSteeAtteuAtMMADpMM(DS)MD
ee Rs b 7d0 odd0oo_nndene
v
s(icniineinstiitt___pf_oiffdiirdd_vviivndii_ddi_ta_(aap()pp(
tssattsaabgg7eg1ee0110))_ )da paaeppviiicicicciiedds:d_ ::0 p3o00r12
_
Fi
InFFIIDiDVtDI(VV)IIDDD : o nSooMnn ABAPuA:sPP:: 0D 3e00v12
i
c
e, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x00800000 0x50005840
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 2
readback = 2010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 3
readback = 3010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810026
End FIDVIDMSR 0xc0010071 0x00800000 0x48005840
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
...WARM RESET...
coreboot-4.0-r5511M Tue Apr 27 23:52:18 PDT 2010 starting...
BSP Family_Model: 00100f43
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810026
F3xD8: 00000510
F3xDC: 0000502c
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
started ap apicid: cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000321 NNNOOODDDEEEIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000132}}} ---------
qqmmmAiiPic cc0rrrooo1cscctooodddaeere:t:: eeedeq
i*iv vvAaaalllPe ee0nnnttt2 s trrreeeavvrv t eiiidddd
ee ==*= 000AxxPx1 11000044343s33t,,, accrcutuurrrerrdre
nnnttt
pppraaas7tttccc8hhh0 _iieidaddr ==l= y _000xxxs00e0t000000u00p00(00)000000
00g
dt_cpu_mmmiiriceccvrrroo ocEccAooodddXee=e0::: xpp1pa0aa0tttccfch4hh3 iii.dd
00 tttCooPo U aaa ppRppeppvlllyyy i s=== 00K08xxx000_11110000000.00
00bbbf6a66m
1
eemmmiii_ccocprrroootccicomooidddeeez:a::t uuuippopndddaaa(tt)te
0xddd rtttosoo7 ppp8aa0at_ttpccchhoh r _iiidddi n i=== t00
r xx000111000000000000bbb666 ssssubuuccc7cc0ce0ee_sssssse
l
y
MM_cccsepppuuutSSuSepee(tttAA)AM
e DDDMMMsSSSbRR7R0 0_ d dddeoovoninnceee
s
_siiinnpnioiitttr____fiffniiiddidvtvv(iiiddd)__
r ssstttaabag7gg0eee2220 _ adaapppeiiviciccciiiddde:s::_ 000p312o
_
init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x00800000 0x48005840
End FIDVIDMSR 0xc0010071 0x00800000 0x48005840
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=3
DIMMPresence: DIMMPresent=3
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=3
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=3
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=3
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=10
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=2
DIMMPresence: MAload[1]=10
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 1002
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1002
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1002
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1002
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 3
SPDSetBanks: Status 1002
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 1002
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1002
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1002
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1002
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1002
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 3
SPDSetBanks: Status 1002
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = fffffe
StitchMemory: Status 1002
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1002
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1002
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: ffffff BottomIO: e00000
Node: 00 base: 03 limit: 11fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:e00000
CPUMemTyping: Bottom32bIO:e00000
CPUMemTyping: Bottom40bIO:1200000
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1102
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1102
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1102
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1102
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1102
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1102
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1102
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:
Testing DRAM : 00200000 - 002a0000
DRAM fill: 0x00200000-0x002a0000
002a0000
DRAM filled
DRAM verify: 0x00200000-0x002a0000
002a0000
DRAM range verified.
Done.
Testing DRAM : 40200000 - 402a0000
DRAM fill: 0x40200000-0x402a0000
402a0000
DRAM filled
DRAM verify: 0x40200000-0x402a0000
402a0000
DRAM range verified.
Done.
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
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