[coreboot] Trouble building coreboot with SeaBIOS for QEMU.
Neil Turton
nturton at solarflare.com
Thu Apr 29 12:32:37 CEST 2010
Hi Myles,
Thanks for the reply. I understand about it being hard to keep the
tutorials up to date.
You wrote:
> 1. svn co svn://coreboot.org/coreboot/trunk coreboot
> 2. make menuconfig
> select mainboard emulation qemu
> select payload (Add a payload)
> 3. copy FILO or SeaBIOS to coreboot/payload.elf
> 4. make
I've just tried that and I see the VGA BIOS screen before qemu quits.
The end of the build phase is below, followed by the serial output. If
I omit -no-reboot, it gets stuck in an endless reboot loops. This is
using bios.bin.elf-0.6.0 as the payload.
I tried with FILO and got to the boot prompt. I've not worked out how
to boot the MBR though. What are the commands to do this?
Cheers, Neil.
[...]
CBFSPRINT coreboot.rom
coreboot.rom: 256 kB, bootblocksize 658, romsize 262144, offset 0x0
Alignment: 64 bytes
Name Offset Type Size
fallback/romstage 0x0 stage 8117
fallback/coreboot_ram 0x2000 stage 27540
fallback/payload 0x8c00 payload 40443
(empty) 0x12a40 null 185062
coreboot-4.0-r5511 Thu Apr 29 10:30:17 BST 2010 starting...
Loading stage image.
Check CBFS header at fffffd4e
magic is 4f524243
Found CBFS header at fffffd4e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @
0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r5511 Thu Apr 29 10:30:17 BST 2010 booting...
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1237] enabled
PCI: 00:01.0 [8086/7000] bus ops
PCI: 00:01.0 [8086/7000] enabled
PCI: 00:01.1 [8086/7010] ops
PCI: 00:01.1 [8086/7010] enabled
malloc Enter, size 1092, free_mem_ptr 00118000
malloc 00118000
PCI: 00:01.3 [8086/7113] bus ops
PCI: 00:01.3 [8086/7113] enabled
malloc Enter, size 1092, free_mem_ptr 00118444
malloc 00118444
PCI: 00:02.0 [1013/00b8] ops
PCI: 00:02.0 [1013/00b8] enabled
malloc Enter, size 1092, free_mem_ptr 00118888
malloc 00118888
PCI: 00:03.0 [8086/100e] enabled
scan_static_bus for PCI: 00:01.0
scan_static_bus for PCI: 00:01.0 done
scan_static_bus for PCI: 00:01.3
scan_static_bus for PCI: 00:01.3 done
PCI: pci_scan_bus returning with max=000
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device links 1 child on link 0 PCI_DOMAIN: 0000
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff
flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0
limit ffffffff flags e0000200 index 2
PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0
limit ffffffff flags e0000200 index 3
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:01.0 links 0 child on link 0 NULL
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff
flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit
0 flags c0000200 index 2
PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
PCI: 00:01.1 links 0 child on link 0 NULL
PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags
100 index 20
PCI: 00:01.3 links 0 child on link 0 NULL
PCI: 00:02.0 links 0 child on link 0 NULL
PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit
ffffffff flags 1200 index 10
PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffff flags 200 index 14
PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit
ffffffff flags 2200 index 30
PCI: 00:03.0 links 0 child on link 0 NULL
PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit
ffffffff flags 200 index 10
PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags
100 index 14
PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit
ffffffff flags 2200 index 30
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff
PCI: 00:03.0 14 * [0x0 - 0x3f] io
PCI: 00:01.1 20 * [0x40 - 0x4f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 50 size: 50 align: 6 gran:
0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff
PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem
PCI: 00:03.0 10 * [0x2000000 - 0x201ffff] mem
PCI: 00:02.0 30 * [0x2020000 - 0x202ffff] mem
PCI: 00:03.0 30 * [0x2030000 - 0x203ffff] mem
PCI: 00:02.0 14 * [0x2040000 - 0x2040fff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 2041000 size: 2041000
align: 25 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:01.3
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:03.0
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:50 align:6 gran:0
limit:ffff
Assigned: PCI: 00:03.0 14 * [0x1000 - 0x103f] io
Assigned: PCI: 00:01.1 20 * [0x1040 - 0x104f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1050 size: 50 align:
6 gran: 0 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2041000
align:25 gran:0 limit:febfffff
Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem
Assigned: PCI: 00:03.0 10 * [0xfe000000 - 0xfe01ffff] mem
Assigned: PCI: 00:02.0 30 * [0xfe020000 - 0xfe02ffff] mem
Assigned: PCI: 00:03.0 30 * [0xfe030000 - 0xfe03ffff] mem
Assigned: PCI: 00:02.0 14 * [0xfe040000 - 0xfe040fff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe041000 size:
2041000 align: 25 gran: 0 done
Root Device assign_resources, bus 0 link: 0
RAM size config registers are empty; defaulting to 64 MBytes
I would set ram size to 0x10000 Kbytes
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 20 <- [0x0000001040 - 0x000000104f] size 0x00000010 gran
0x04 io
PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran
0x19 prefmem
PCI: 00:02.0 14 <- [0x00fe040000 - 0x00fe040fff] size 0x00001000 gran
0x0c mem
PCI: 00:02.0 30 <- [0x00fe020000 - 0x00fe02ffff] size 0x00010000 gran
0x10 romem
PCI: 00:03.0 10 <- [0x00fe000000 - 0x00fe01ffff] size 0x00020000 gran
0x11 mem
PCI: 00:03.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran
0x06 io
PCI: 00:03.0 30 <- [0x00fe030000 - 0x00fe03ffff] size 0x00010000 gran
0x10 romem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device links 1 child on link 0 PCI_DOMAIN: 0000
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff
flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0
limit febfffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0
limit ffffffff flags e0000200 index 2
PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0
limit ffffffff flags e0000200 index 3
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0
flags e0004200 index a
PCI_DOMAIN: 0000 resource base c0000 size 3f40000 align 0 gran 0 limit
0 flags e0004200 index b
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:01.0 links 0 child on link 0 NULL
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff
flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit
0 flags c0000200 index 2
PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
PCI: 00:01.1 links 0 child on link 0 NULL
PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff
flags 60000100 index 20
PCI: 00:01.3 links 0 child on link 0 NULL
PCI: 00:02.0 links 0 child on link 0 NULL
PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25
limit febfffff flags 60001200 index 10
PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 14
PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit
febfffff flags 60002200 index 30
PCI: 00:03.0 links 0 child on link 0 NULL
PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit
febfffff flags 60000200 index 10
PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff
flags 60000100 index 14
PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit
febfffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 00/00
PCI: 00:00.0 cmd <- 00
PCI: 00:01.0 cmd <- 07
PCI: 00:01.1 cmd <- 01
PCI: 00:01.3 cmd <- 00
PCI: 00:02.0 cmd <- 03
PCI: 00:03.0 cmd <- 03
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
Check CBFS header at fffffd4e
magic is 4f524243
Found CBFS header at fffffd4e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000
Check fallback/coreboot_ram
CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00
Check fallback/payload
CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40
Check
CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80
CBFS: Could not find file pci8086,1237.rom
PCI: 00:01.0 init
RTC Init
RTC: Checksum invalid zeroing cmos
Invalid CMOS LB checksum
PCI: 00:01.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: off
PCI: 00:02.0 init
Check CBFS header at fffffd4e
magic is 4f524243
Found CBFS header at fffffd4e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000
Check fallback/coreboot_ram
CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00
Check fallback/payload
CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40
Check
CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80
CBFS: Could not find file pci1013,00b8.rom
On card, rom address for PCI: 00:02.0 = fe020000
PCI Expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038
PCI ROM Image, Vendor 1013, Device 00b8,
PCI ROM Image, Class Code 030000, Code Type 00
copying VGA ROM Image from fe020000 to 0xc0000, 0x8c00 bytes
Real mode stub @00000600: 422 bytes
Calling Option ROM...
... Option ROM returned.
Keyboard init...
Keyboard controller output buffer result timeout
setting ethernet
Assigning IRQ 11 to 0:3.0
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x800
PCI: 00:03.0 init
Check CBFS header at fffffd4e
magic is 4f524243
Found CBFS header at fffffd4e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000
Check fallback/coreboot_ram
CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00
Check fallback/payload
CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40
Check
CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80
CBFS: Could not find file pci8086,100e.rom
On card, rom address for PCI: 00:03.0 = fe030000
PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect Expansion ROM Header Signature 0000
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 6 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 00:01.1: enabled 1, 1 resources
PCI: 00:01.3: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 3 resources
PCI: 00:03.0: enabled 1, 3 resources
Initializing CBMEM area to 0x3ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 03ff0200...ok
High Tables Base is 3ff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x03ff0400... done.
PIRQ table: 128 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum e7df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x03ff1400
rom_table_end = 0x03ff1400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x03ff1400 to 0x04000000
Adding high table area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-0000000003feffff: RAM
3. 0000000003ff0000-0000000003ffffff: CONFIGURATION TABLES
Wrote coreboot table at: 03ff1400 - 03ff1a4c checksum 6ba1
coreboot table: 1612 bytes.
0. FREE SPACE 03ff3400 0000cc00
1. GDT 03ff0200 00000200
2. IRQ TABLE 03ff0400 00001000
3. COREBOOT 03ff1400 00002000
Check CBFS header at fffffd4e
magic is 4f524243
Found CBFS header at fffffd4e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000
Check fallback/coreboot_ram
CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00
Check fallback/payload
Got a payload
Loading segment from rom address 0xfffc8c38
data (compression=1)
malloc Enter, size 36, free_mem_ptr 00118ccc
malloc 00118ccc
New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfffc8c70
filesize 0x9dc3
(cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfffc8c70
filesize 0x9dc3
Loading segment from rom address 0xfffc8c54
Entry Point 0x000fdf82
Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00
filesz: 0x0000000000009dc3
lb: [0x0000000000100000, 0x000000000011c000)
Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00
filesz: 0x0000000000009dc3
using LZMA
lzma: Decoding error = 1
[ 0x00000000000ec400, 00000000000ec400, 0x0000000000100000) <-
00000000fffc8c70
Clearing Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00
dest 000ec400, end 00100000, bouncebuffer 3fb8000
Loaded segments
Jumping to boot code at fdf82
entry = 0x000fdf82
lb_start = 0x00100000
lb_size = 0x0001c000
adjust = 0x03ed4000
buffer = 0x03fb8000
elf_boot_notes = 0x0010c854
adjusted_boot_notes = 0x03fe0854
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