[coreboot] [review 2/2] Subject: LGA775 and P4-6x0 Support

Pat Erley pat-lkml at erley.org
Thu Apr 29 20:16:35 CEST 2010


This adds a new socket and processor family.
---
 src/cpu/intel/Kconfig                       |    1 +
 src/cpu/intel/Makefile.inc                  |    1 +
 src/cpu/intel/model_f4x/model_f4x_init.c    |    1 +
 src/cpu/intel/socket_LGA775/Kconfig         |    8 ++++++++
 src/cpu/intel/socket_LGA775/Makefile.inc    |   13 +++++++++++++
 src/cpu/intel/socket_LGA775/chip.h          |    4 ++++
 src/cpu/intel/socket_LGA775/socket_LGA775.c |    7 +++++++
 src/mainboard/clevo/d900t/Kconfig           |    3 +--
 8 files changed, 36 insertions(+), 2 deletions(-)
 create mode 100644 src/cpu/intel/socket_LGA775/Kconfig
 create mode 100644 src/cpu/intel/socket_LGA775/Makefile.inc
 create mode 100644 src/cpu/intel/socket_LGA775/chip.h
 create mode 100644 src/cpu/intel/socket_LGA775/socket_LGA775.c

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 426122b..eb187c6 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -17,6 +17,7 @@ source src/cpu/intel/ep80579/Kconfig
 source src/cpu/intel/bga956/Kconfig
 source src/cpu/intel/slot_2/Kconfig
 source src/cpu/intel/slot_1/Kconfig
+source src/cpu/intel/socket_LGA775/Kconfig
 source src/cpu/intel/socket_mFCBGA479/Kconfig
 source src/cpu/intel/socket_mFCPGA478/Kconfig
 source src/cpu/intel/socket_mPGA478/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 870490c..a965ed6 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -6,6 +6,7 @@
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956
 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index d6acdde..c5615a9 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -49,6 +49,7 @@ static struct device_operations cpu_dev_ops = {
 };
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */
+	{ X86_VENDOR_INTEL, 0x0f40 }, /* P4 6x0 */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
new file mode 100644
index 0000000..6814c23
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -0,0 +1,8 @@
+config CPU_INTEL_SOCKET_LGA775
+	bool
+	select MMX
+	select SSE
+	select SSE2
+	select SSE3
+	select UDELAY_TSC
+	select CPU_INTEL_MODEL_F4X
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
new file mode 100644
index 0000000..44e33a0
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -0,0 +1,13 @@
+obj-y += socket_LGA775.o
+subdirs-$(CONFIG_CPU_INTEL_MODEL_F2X) += ../model_f2x
+subdirs-$(CONFIG_CPU_INTEL_MODEL_F3X) += ../model_f3x
+subdirs-$(CONFIG_CPU_INTEL_MODEL_F4X) += ../model_f4x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
+
diff --git a/src/cpu/intel/socket_LGA775/chip.h b/src/cpu/intel/socket_LGA775/chip.h
new file mode 100644
index 0000000..d1273be
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_LGA775_ops;
+
+struct cpu_intel_socket_LGA775_config {
+};
diff --git a/src/cpu/intel/socket_LGA775/socket_LGA775.c b/src/cpu/intel/socket_LGA775/socket_LGA775.c
new file mode 100644
index 0000000..a564c61
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/socket_LGA775.c
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_LGA775 {
+	CHIP_NAME("Socket LGA775 CPU")
+};
diff --git a/src/mainboard/clevo/d900t/Kconfig b/src/mainboard/clevo/d900t/Kconfig
index 50e272f..78735b3 100644
--- a/src/mainboard/clevo/d900t/Kconfig
+++ b/src/mainboard/clevo/d900t/Kconfig
@@ -20,8 +20,7 @@
 config BOARD_CLEVO_D900T
 	bool "D900T"
 	select ARCH_X86
-#	select CPU_INTEL_MODEL_F4X
-#	select CPU_INTEL_SOCKET_LGA775
+	select CPU_INTEL_SOCKET_LGA775
 #	select CPU_INTEL_ATOM_230
 #	select CPU_INTEL_SOCKET_441
 #	select NORTHBRIDGE_INTEL_I945
-- 
1.7.0.4





More information about the coreboot mailing list