[coreboot] [PATCH] include workaround for AMD erratum 372
xdrudis
xdrudis at tinet.cat
Fri Aug 20 00:01:04 CEST 2010
with this one it stops here or earlier (as soon as before the patch, sometimes):
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
Signed off by: Xavi Drudis Ferran <xdrudis at tinet.cat>
-------------- next part --------------
documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
apply after patch.rbc3inErr346
Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h (revision 5692)
+++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h (working copy)
@@ -175,6 +177,7 @@
#define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */
#define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */
+#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */
/*=============================================================================
SW Initialization
============================================================================*/
Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 5692)
+++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy)
@@ -400,14 +400,31 @@
coreDelay();
}
+
+static void vErratum372(struct DCTStatStruc *pDCTstat)
+{
+ msr_t msr = rdmsr(NB_CFG_MSR);
+
+ int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ;
+
+ // is this the right way to check for NB pstate 1 or DDR3-1333 ?
+ if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+ &&(!pDCTstat->GangedMode)) {
+ /* DisableCf8ExtCfg */
+ msr.hi &= ~(3 << (51 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+ }
+}
#endif
static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
- if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) {
+ /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */
+ if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) {
vErrata350(pMCTstat, pDCTstatA);
+ vErratum372(pDCTstatA);
}
#endif
}
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