[coreboot] [PATCH 1/3] mPGA479M Sockets can take Intel Mobile Celeron. The 1.2GHz model has CPUID F29 This adds them to the list of CPUs for that socket.

[Andreas Schultz]

Signed-off-by: Andreas Schultz <aschultz at tpip.net>
---
 src/cpu/intel/socket_mPGA479M/Kconfig      |    1 +
 src/cpu/intel/socket_mPGA479M/Makefile.inc |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig
index 4ee8e1b..8598eaf 100644
--- a/src/cpu/intel/socket_mPGA479M/Kconfig
+++ b/src/cpu/intel/socket_mPGA479M/Kconfig
@@ -3,5 +3,6 @@ config CPU_INTEL_SOCKET_MPGA479M
 	select CPU_INTEL_MODEL_69X
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6DX
+	select CPU_INTEL_MODEL_F2X
 	select MMX
 	select SSE
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index d16cc76..2cf418f 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -1,6 +1,7 @@
 obj-y += socket_mPGA479M.o
 subdirs-y += ../model_69x
 subdirs-y += ../model_6dx
+subdirs-y += ../model_f2x
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
@@ -9,3 +10,4 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
\ No newline at end of file
-- 
1.7.0.4