From Zheng.Bao at amd.com  Wed Dec  1 06:50:25 2010
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Wed, 1 Dec 2010 13:50:25 +0800
Subject: [coreboot] [PATCH] More explicite and straight way to set seed
Message-ID: <DD1CC71B621B004FA76856E5129D6B17045084A3@sbjgexmb1.amd.com>

More explicite and straight way to set seed.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>


Index: src/northbridge/amd/amdmct/mct/mctsrc.c
===================================================================
--- src/northbridge/amd/amdmct/mct/mctsrc.c	(revision 6135)
+++ src/northbridge/amd/amdmct/mct/mctsrc.c	(working copy)
@@ -1023,13 +1023,9 @@
 
 	dev = pDCTstat->dev_dct;
 	for (index = 0x50; index <= 0x52; index ++) {
-		val = Get_NB32_index_wait(dev, index_reg, index);
-		val |= (FenceTrnFinDlySeed & 0x1F);
+		val = (FenceTrnFinDlySeed & 0x1F);
 		if (index != 0x52) {
-			val &= ~(0xFF << 8);
-			val |= (val & 0xFF) << 8;
-			val &= 0xFFFF;
-			val |= val << 16;
+			val |= val << 8 | val << 16 | val << 24;
 		}
 		Set_NB32_index_wait(dev, index_reg, index, val);
 	}
Index: src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	(revision 6135)
+++ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	(working copy)
@@ -972,13 +972,9 @@
 	 */
 	dev = pDCTstat->dev_dct;
 	for (index = 0x50; index <= 0x52; index ++) {
-		val = Get_NB32_index_wait(dev, index_reg, index) &
~0xFF;
-		val |= (FenceTrnFinDlySeed & 0x1F);
+		val = (FenceTrnFinDlySeed & 0x1F);
 		if (index != 0x52) {
-			val &= ~(0xFF << 8);
-			val |= (val & 0xFF) << 8;
-			val &= 0xFFFF;
-			val |= val << 16;
+			val |= val << 8 | val << 16 | val << 24;
 		}
 		Set_NB32_index_wait(dev, index_reg, index, val);
 	}
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From ranma+coreboot at tdiedrich.de  Wed Dec  1 15:34:43 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 1 Dec 2010 15:34:43 +0100
Subject: [coreboot] [commit] r6127 - in trunk/src:
	mainboard/asus/p2b	northbridge/intel/i440bx/acpi
	southbridge/intel/i82371eb	southbridge/intel/i82371eb/acpi
In-Reply-To: <20101130223104.GA28050@coreboot.org>
References: <E1PMHGT-0005cI-6y@ra.coresystems.de>
	<4CF207B0.7020100@coresystems.de>
	<20101128104303.GD32428@yumi.tdiedrich.de>
	<20101130223104.GA28050@coreboot.org>
Message-ID: <20101201143443.GV32428@yumi.tdiedrich.de>

Stefan Reinauer wrote:
> * Tobias Diedrich <ranma+coreboot at tdiedrich.de> [101128 11:43]:
> > The IO port is ok (and I wrote the comment myself ;)):
> > DEFAULT_PMBASE is 0xe400
> > PCNTRL reg offset is 0x10
> 
> Oh, I think that's even worse... ;)
> 
> 1) DEFAULT_PMBASE must be lower than 0x1000 to avoid conflicts with the
>    resource allocator.

It's registered as a fixed resource in i82371eb_smbus.c (added by me
in the acpi patch), so it shouldn't be a problem.

> 2) The IO address in the Processor field should be configured
>    in the MSR PMG_IO_BASE_ADDR (0xe3).

This is only for newer processors I think, I didn't see an this msr
in the msr list for PIII processors.
It's handled by the 440bx chipset acpi registers instead.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From marcj303 at gmail.com  Wed Dec  1 17:44:14 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 1 Dec 2010 09:44:14 -0700
Subject: [coreboot] [PATCH] 939a785gmh ACPI diet
In-Reply-To: <4CF569C1.2060905@assembler.cz>
References: <4CF569C1.2060905@assembler.cz>
Message-ID: <AANLkTimgzwsoi6G0kORTaK+HdTamKVmuc6vj1ZWwExMe@mail.gmail.com>

2010/11/30 Rudolf Marek <r.marek at assembler.cz>:
> Hello,
>
> Following patch removes the cut-and-paste stuff from Mahagony and fixes the
> _CRS object to make it work (same code as on M2V-MX SE)
>
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Acked-by: Marc Jones <marcj303 at gmail.com>


-- 
http://se-eng.com



From marcj303 at gmail.com  Wed Dec  1 18:35:41 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 1 Dec 2010 10:35:41 -0700
Subject: [coreboot] [PATCH] More explicite and straight way to set seed
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B17045084A3@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B17045084A3@sbjgexmb1.amd.com>
Message-ID: <AANLkTi=NeTxVttn_XLm6UpmcTmiXghPwuKmuq0v2+2g=@mail.gmail.com>

On Tue, Nov 30, 2010 at 10:50 PM, Bao, Zheng <Zheng.Bao at amd.com> wrote:
> More explicite and straight way to set seed.
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
>
> Index: src/northbridge/amd/amdmct/mct/mctsrc.c
> ===================================================================
> --- src/northbridge/amd/amdmct/mct/mctsrc.c ? ? (revision 6135)
> +++ src/northbridge/amd/amdmct/mct/mctsrc.c ? ? (working copy)
> @@ -1023,13 +1023,9 @@
>
> ? ? ? ?dev = pDCTstat->dev_dct;
> ? ? ? ?for (index = 0x50; index <= 0x52; index ++) {
> - ? ? ? ? ? ? ? val = Get_NB32_index_wait(dev, index_reg, index);
> - ? ? ? ? ? ? ? val |= (FenceTrnFinDlySeed & 0x1F);
> + ? ? ? ? ? ? ? val = (FenceTrnFinDlySeed & 0x1F);
> ? ? ? ? ? ? ? ?if (index != 0x52) {
> - ? ? ? ? ? ? ? ? ? ? ? val &= ~(0xFF << 8);
> - ? ? ? ? ? ? ? ? ? ? ? val |= (val & 0xFF) << 8;
> - ? ? ? ? ? ? ? ? ? ? ? val &= 0xFFFF;
> - ? ? ? ? ? ? ? ? ? ? ? val |= val << 16;
> + ? ? ? ? ? ? ? ? ? ? ? val |= val << 8 | val << 16 | val << 24;
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?Set_NB32_index_wait(dev, index_reg, index, val);
> ? ? ? ?}
> Index: src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
> ===================================================================
> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ? ? ? ?(revision 6135)
> +++ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ? ? ? ?(working copy)
> @@ -972,13 +972,9 @@
> ? ? ? ? */
> ? ? ? ?dev = pDCTstat->dev_dct;
> ? ? ? ?for (index = 0x50; index <= 0x52; index ++) {
> - ? ? ? ? ? ? ? val = Get_NB32_index_wait(dev, index_reg, index) &
> ~0xFF;
> - ? ? ? ? ? ? ? val |= (FenceTrnFinDlySeed & 0x1F);
> + ? ? ? ? ? ? ? val = (FenceTrnFinDlySeed & 0x1F);
> ? ? ? ? ? ? ? ?if (index != 0x52) {
> - ? ? ? ? ? ? ? ? ? ? ? val &= ~(0xFF << 8);
> - ? ? ? ? ? ? ? ? ? ? ? val |= (val & 0xFF) << 8;
> - ? ? ? ? ? ? ? ? ? ? ? val &= 0xFFFF;
> - ? ? ? ? ? ? ? ? ? ? ? val |= val << 16;
> + ? ? ? ? ? ? ? ? ? ? ? val |= val << 8 | val << 16 | val << 24;
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?Set_NB32_index_wait(dev, index_reg, index, val);
> ? ? ? ?}
>

Yes, the read-modify-write wasn't needed. This easier to understand.

Acked-by: Marc Jones <marcj303 at gmail.com>


-- 
http://se-eng.com



From marcj303 at gmail.com  Wed Dec  1 17:40:03 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 1 Dec 2010 09:40:03 -0700
Subject: [coreboot] [patch] update crossgcc
In-Reply-To: <AANLkTinVTcdMEPLMvq6vZAwPTT08Lw1u0q0xepdGAKBU@mail.gmail.com>
References: <AANLkTinVTcdMEPLMvq6vZAwPTT08Lw1u0q0xepdGAKBU@mail.gmail.com>
Message-ID: <AANLkTi=EJsk8VeC_ZGBvTHtHeUiVUZAiMaf2fzkw+_dC@mail.gmail.com>

On Thu, Nov 18, 2010 at 4:55 PM, Marc Jones <marcj303 at gmail.com> wrote:
> Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2.
> Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
> Add GDB patch to handle #pragma pack in the i386-elf gcc target.
>
> Signed-off-by: Marc Jones <marcj303 at gmail.com>
>
> Tested on IEI Kino Fam10 mainboard. Can someone test that this works
> on some other mainboards, maybe Intel or Via based?

ScottD and Patrick have tested on a few platforms. Has anyone else
tested this? Are we ready for an Ack?

Marc



-- 
http://se-eng.com



From stefan.reinauer at coresystems.de  Wed Dec  1 19:02:31 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Wed, 1 Dec 2010 10:02:31 -0800
Subject: [coreboot] [patch] update crossgcc
In-Reply-To: <AANLkTi=EJsk8VeC_ZGBvTHtHeUiVUZAiMaf2fzkw+_dC@mail.gmail.com>
References: <AANLkTinVTcdMEPLMvq6vZAwPTT08Lw1u0q0xepdGAKBU@mail.gmail.com>
	<AANLkTi=EJsk8VeC_ZGBvTHtHeUiVUZAiMaf2fzkw+_dC@mail.gmail.com>
Message-ID: <68F88724-A79C-42F9-94AB-22229C118276@coresystems.de>



On 01.12.2010, at 08:40, Marc Jones <marcj303 at gmail.com> wrote:

> On Thu, Nov 18, 2010 at 4:55 PM, Marc Jones <marcj303 at gmail.com> wrote:
>> Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2.
>> Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
>> Add GDB patch to handle #pragma pack in the i386-elf gcc target.
>> 
>> Signed-off-by: Marc Jones <marcj303 at gmail.com>
>> 
>> Tested on IEI Kino Fam10 mainboard. Can someone test that this works
>> on some other mainboards, maybe Intel or Via based?
> 
> ScottD and Patrick have tested on a few platforms. Has anyone else
> tested this? Are we ready for an Ack?
> 
> Marc

Acked-by: Stefan Reinauer <stepan at coreboot.org>



> 



From ranma+coreboot at tdiedrich.de  Wed Dec  1 19:10:57 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 1 Dec 2010 19:10:57 +0100
Subject: [coreboot] [commit] r6127 - in trunk/src:
	mainboard/asus/p2b	northbridge/intel/i440bx/acpi
	southbridge/intel/i82371eb	southbridge/intel/i82371eb/acpi
In-Reply-To: <20101130223104.GA28050@coreboot.org>
	<20101130094609.GQ32428@yumi.tdiedrich.de>
References: <20101130223104.GA28050@coreboot.org>
	<E1PMHGT-0005cI-6y@ra.coresystems.de>
	<4CF207B0.7020100@coresystems.de>
	<20101128104303.GD32428@yumi.tdiedrich.de>
	<20101128110656.GE32428@yumi.tdiedrich.de>
	<20101128202652.GD21636@greenwood>
	<20101129204240.GL32428@yumi.tdiedrich.de>
	<20101130005855.GP32428@yumi.tdiedrich.de>
	<4CF4B217.4000000@assembler.cz>
	<20101130094609.GQ32428@yumi.tdiedrich.de>
Message-ID: <20101201181057.GX32428@yumi.tdiedrich.de>

Tobias Diedrich wrote:
> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.

Here is a solution using the SSDT.

Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.

Abuild-tested.

Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

---

Index: src/mainboard/asus/p2b/dsdt.asl
===================================================================
--- src/mainboard/asus/p2b/dsdt.asl.orig	2010-12-01 17:50:26.000000000 +0100
+++ src/mainboard/asus/p2b/dsdt.asl	2010-12-01 18:29:22.000000000 +0100
@@ -21,15 +21,6 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 {
-	/* Define the main processor.*/
-	Scope (\_PR)
-	{
-		/* Looks like the P_CNT field can't be a name or method (except
-		 * builtins like Add()) and has to be hardcoded or generated
-		 * into SSDT */
-		Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {}
-	}
-
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on
 	 *  - S5 which is soft off
Index: src/southbridge/intel/i82371eb/acpi_tables.c
===================================================================
--- src/southbridge/intel/i82371eb/acpi_tables.c.orig	2010-12-01 17:50:26.000000000 +0100
+++ src/southbridge/intel/i82371eb/acpi_tables.c	2010-12-01 18:30:47.000000000 +0100
@@ -26,9 +26,46 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
+#include "i82371eb.h"
 
 extern const unsigned char AmlCode[];
 
+static int determine_total_number_of_cores(void)
+{
+	device_t cpu;
+	int count = 0;
+	for(cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+			(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+			continue;
+		}
+		if (!cpu->enabled) {
+			continue;
+		}
+		count++;
+	}
+	return count;
+}
+
+void generate_cpu_entries(void)
+{
+	int len;
+	int len_pr;
+	int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6;
+	int numcpus = determine_total_number_of_cores();
+	printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
+
+	/* without the outer scope, furhter ssdt addition will end up
+	 * within the processor statement */
+	len = acpigen_write_scope("\\_PR");
+	for (cpu=0; cpu < numcpus; cpu++) {
+		len_pr = acpigen_write_processor(cpu, pcontrol_blk, plen);
+		acpigen_patch_len(len_pr - 1);
+		len += len_pr;
+	}
+	acpigen_patch_len(len - 1);
+}
+
 unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
@@ -57,6 +94,10 @@
 						 const char *oem_table_id)
 {
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+	/* generate_cpu_entries() generates weird bytecode and has to come
+	 * last or else the following entries will end up inside the
+	 * processor scope */
+	generate_cpu_entries();
 	return (unsigned long) acpigen_get_current();
 }
 



From peter at stuge.se  Wed Dec  1 21:42:01 2010
From: peter at stuge.se (Peter Stuge)
Date: Wed, 1 Dec 2010 21:42:01 +0100
Subject: [coreboot] [commit] r6127 - in trunk/src:
	mainboard/asus/p2b	northbridge/intel/i440bx/acpi
	southbridge/intel/i82371eb	southbridge/intel/i82371eb/acpi
In-Reply-To: <20101201181057.GX32428@yumi.tdiedrich.de>
References: <E1PMHGT-0005cI-6y@ra.coresystems.de>
	<4CF207B0.7020100@coresystems.de>
	<20101128104303.GD32428@yumi.tdiedrich.de>
	<20101128110656.GE32428@yumi.tdiedrich.de>
	<20101128202652.GD21636@greenwood>
	<20101129204240.GL32428@yumi.tdiedrich.de>
	<20101130005855.GP32428@yumi.tdiedrich.de>
	<4CF4B217.4000000@assembler.cz>
	<20101130094609.GQ32428@yumi.tdiedrich.de>
	<20101201181057.GX32428@yumi.tdiedrich.de>
Message-ID: <20101201204201.10024.qmail@stuge.se>

Tobias Diedrich wrote:
> Here is a solution using the SSDT.
> 
> Unfortunately iasl does not resolve simple arithmetic at compile
> time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
> Processor statement.
> This patch instead dynamically generates the processor statement.
> I can't use the speedstep generate_cpu_entries() directly since the
> cpu doesn't support speedstep.
> For now the code is in the southbridge directory, but maybe it
> should go into cpu/intel/ somewhere.
> IIRC notebook cpus of the era can already have speedstep, so it
> would probably be possible to pair the i82371eb with a
> speedstep-capable cpu...
> Also, I don't know if multiprocessor boards (abit bp6?) would need
> to be handled differently.
> 
> Abuild-tested.
> 
> Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

Not lovely to generate something that is so simple, but sure, if it
works.

Acked-by: Peter Stuge <peter at stuge.se>



From ranma+coreboot at tdiedrich.de  Wed Dec  1 20:46:57 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 01 Dec 2010 20:46:57 +0100
Subject: [coreboot] [patch 2/3] Use ACPI table area to store cbmem_toc
	pointer needed for resume
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
Message-ID: <20101201210354.952358768@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Wed Dec  1 20:46:56 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 01 Dec 2010 20:46:56 +0100
Subject: [coreboot] [patch 1/3] Add acpi_get_sleep_type() to i82371eb and
	P2B _PTS/_WAK methods
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
Message-ID: <20101201210354.600579949@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Wed Dec  1 20:46:58 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 01 Dec 2010 20:46:58 +0100
Subject: [coreboot] [patch 3/3] Implement post_main/post_cache_as_ram resume
	hooks for romstage on Intel and use them for Slot-1 cpus if
	CONFIG_GENERATE_ACPI_TABLES=y.
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
Message-ID: <20101201210355.263647660@yamamaya.is-a-geek.org>

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From ranma+coreboot at tdiedrich.de  Wed Dec  1 20:46:55 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Wed, 01 Dec 2010 20:46:55 +0100
Subject: [coreboot] [patch 0/3] ASUS P2B S2/S3 sleep support
Message-ID: <20101201194655.526093264@yamamaya.is-a-geek.org>

Add support for S2/S3 sleep (resume from reset vector).

Part1 adds the get_acpi_sleep_type() function to read the sleep type and
sets acpi_slp_type.

Part2 adds generic infrastructure to save a pointer to cbmem_toc in the
ACPI memory area.  This could also replace the vt8237 solution of using
special nvram (which the I82371EB chipset doesn't have).

Part3 adds the necessary code to save the memory area overwritten by ramstage
into the reserved backup memory space.

All three patches are abuild-tested and should be applied after the ssdt cpu
generation patch
(http://www.coreboot.org/pipermail/coreboot/2010-December/062229.html).

I tested the complete stack on both the P2B board which I wrote it for and the amd am2
base M2V board to check that it doesn't break anything there.

Keith: It should probably be rather simple to enable this on P2B-LS/P3B-F too if
you'd like to test.

Here is the serial log (cold boot, s3, poweroff).
Note: While S5 poweroff works and does poweroff the power supply,
S3 seems to still need some magic to really power off, even though we tell the chipset
to go to S3 sleep. However investigating this will have to wait since I won't have access
to these boards, starting tomorrow, for the next month or so.

coreboot-4.0-r6132M Wed Dec  1 21:51:49 CET 2010 starting...
Wakeup from ACPI sleep type S5 (PMCNTRL=0000)
v_esp=000cffc8
testx = 5a5a5a5a
resume_backup_memory=00000000
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
After cache as ram disabled 
resume_backup_memory=00000000
Clearing initial memory region: Done
Loading image.
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r6132M Wed Dec  1 21:51:49 CET 2010 booting...
clocks_per_usec: 502
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.9: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:04.0: enabled 1
   PNP: 03f0.0: enabled 1
   PNP: 03f0.1: enabled 1
   PNP: 03f0.2: enabled 1
   PNP: 03f0.3: enabled 1
   PNP: 03f0.5: enabled 1
   PNP: 03f0.7: enabled 1
   PNP: 03f0.8: enabled 1
   PNP: 03f0.9: enabled 1
   PNP: 03f0.a: enabled 1
  PCI: 00:04.1: enabled 1
  PCI: 00:04.2: enabled 1
  PCI: 00:04.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:04.0 [8086/7110] bus ops
PCI: 00:04.0 [8086/7110] enabled
PCI: 00:04.1 [8086/7111] ops
PCI: 00:04.1 [8086/7111] enabled
PCI: 00:04.2 [8086/7112] ops
PCI: 00:04.2 [8086/7112] enabled
PCI: 00:04.3 [8086/7113] bus ops
Wakeup from ACPI sleep type S5 (PMCNTRL=0000)
PCI: 00:04.3 [8086/7113] enabled
PCI: 00:09.0 [10ec/8169] enabled
PCI: 00:0c.0 [102b/0519] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:04.0
PNP: 03f0.0 enabled
PNP: 03f0.1 enabled
PNP: 03f0.2 enabled
PNP: 03f0.3 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PNP: 03f0.9 enabled
PNP: 03f0.a enabled
PNP: 03f0.6 enabled
scan_static_bus for PCI: 00:04.0 done
scan_static_bus for PCI: 00:04.3
scan_static_bus for PCI: 00:04.3 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 00:0c.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PNP: 03f0.8 missing read_resources
PNP: 03f0.9 missing read_resources
PCI: 00:04.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:04.0 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
    PNP: 03f0.0
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 03f0.1
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 03f0.2
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.3
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.5
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
    PNP: 03f0.7
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.8
    PNP: 03f0.9
    PNP: 03f0.a
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.6
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:04.1
   PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:04.2
   PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:04.3
   PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:09.0
   PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
   PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:0c.0
   PCI: 00:0c.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
   PCI: 00:0c.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 1200 index 14
   PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:09.0 10 *  [0x0 - 0xff] io
PCI: 00:04.2 20 *  [0x400 - 0x41f] io
PCI: 00:04.1 20 *  [0x420 - 0x42f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 430 size: 430 align: 8 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:00.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:0c.0 14 *  [0x10000000 - 0x107fffff] prefmem
PCI: 00:09.0 30 *  [0x10800000 - 0x1081ffff] mem
PCI: 00:0c.0 30 *  [0x10820000 - 0x1082ffff] mem
PCI: 00:0c.0 10 *  [0x10830000 - 0x10833fff] mem
PCI: 00:09.0 14 *  [0x10834000 - 0x108340ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 10834100 size: 10834100 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:04.0
constrain_resources: PNP: 03f0.0
constrain_resources: PNP: 03f0.1
constrain_resources: PNP: 03f0.2
constrain_resources: PNP: 03f0.3
constrain_resources: PNP: 03f0.5
constrain_resources: PNP: 03f0.7
constrain_resources: PNP: 03f0.8
constrain_resources: PNP: 03f0.9
constrain_resources: PNP: 03f0.a
constrain_resources: PNP: 03f0.6
constrain_resources: PCI: 00:04.1
constrain_resources: PCI: 00:04.2
constrain_resources: PCI: 00:04.3
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 00:0c.0
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000e3ff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
	lim->base 00000000 lim->limit ff7fffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:430 align:8 gran:0 limit:e3ff
Assigned: PCI: 00:09.0 10 *  [0x1000 - 0x10ff] io
Assigned: PCI: 00:04.2 20 *  [0x1400 - 0x141f] io
Assigned: PCI: 00:04.1 20 *  [0x1420 - 0x142f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1430 size: 430 align: 8 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:e3ff size:0 align:12 gran:12 limit:e3ff
PCI: 00:01.0 allocate_resources_io: next_base: e3ff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10834100 align:28 gran:0 limit:ff7fffff
Assigned: PCI: 00:00.0 10 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:0c.0 14 *  [0xf0000000 - 0xf07fffff] prefmem
Assigned: PCI: 00:09.0 30 *  [0xf0800000 - 0xf081ffff] mem
Assigned: PCI: 00:0c.0 30 *  [0xf0820000 - 0xf082ffff] mem
Assigned: PCI: 00:0c.0 10 *  [0xf0830000 - 0xf0833fff] mem
Assigned: PCI: 00:09.0 14 *  [0xf0834000 - 0xf08340ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0834100 size: 10834100 align: 28 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff
PCI: 00:01.0 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 512 MB
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned
PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned
ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned
ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned
ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x0000001420 - 0x000000142f] size 0x00000010 gran 0x04 io
PCI: 00:04.2 20 <- [0x0000001400 - 0x000000141f] size 0x00000020 gran 0x05 io
PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:09.0 14 <- [0x00f0834000 - 0x00f08340ff] size 0x00000100 gran 0x08 mem
PCI: 00:09.0 30 <- [0x00f0800000 - 0x00f081ffff] size 0x00020000 gran 0x11 romem
PCI: 00:0c.0 10 <- [0x00f0830000 - 0x00f0833fff] size 0x00004000 gran 0x0e mem
PCI: 00:0c.0 14 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem
PCI: 00:0c.0 30 <- [0x00f0820000 - 0x00f082ffff] size 0x00010000 gran 0x10 romem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 430 align 8 gran 0 limit e3ff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base e0000000 size 10834100 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b
   PCI: 00:00.0
   PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10
   PCI: 00:01.0
   PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c
   PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24
   PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20
   PCI: 00:04.0 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
    PNP: 03f0.0
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
    PNP: 03f0.1
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 03f0.2
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.3
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.5
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
    PNP: 03f0.7
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.8
    PNP: 03f0.9
    PNP: 03f0.a
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 03f0.6
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
   PCI: 00:04.1
   PCI: 00:04.1 resource base 1420 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20
   PCI: 00:04.2
   PCI: 00:04.2 resource base 1400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20
   PCI: 00:04.3
   PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:09.0
   PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10
   PCI: 00:09.0 resource base f0834000 size 100 align 8 gran 8 limit ff7fffff flags 60000200 index 14
   PCI: 00:09.0 resource base f0800000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30
   PCI: 00:0c.0
   PCI: 00:0c.0 resource base f0830000 size 4000 align 14 gran 14 limit ff7fffff flags 60000200 index 10
   PCI: 00:0c.0 resource base f0000000 size 800000 align 23 gran 23 limit ff7fffff flags 60001200 index 14
   PCI: 00:0c.0 resource base f0820000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0083
PCI: 00:01.0 cmd <- 00
PCI: 00:04.0 cmd <- 07
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 cmd <- 01
PCI: 00:09.0 cmd <- 03
PCI: 00:0c.0 cmd <- 83
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Intel device 672
CPU: family 06, model 07, stepping 02
microcode_info: sig = 0x00000672 pf=0x00000001 rev = 0x00000000
microcode updated to revision: 00000010 from revision 00000000
Enabling cache

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Disabling local apic...done.
CPU #0 initialized
PCI: 00:00.0 init
Northbridge Init
PCI: 00:04.0 init
RTC Init
PCI: 00:04.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:04.2 init
PCI: 00:09.0 init
PCI: 00:0c.0 init
PNP: 03f0.0 init
PNP: 03f0.1 init
PNP: 03f0.2 init
PNP: 03f0.3 init
PNP: 03f0.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xaa
PNP: 03f0.7 init
PNP: 03f0.a init
PNP: 03f0.6 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:04.0: enabled 1
PNP: 03f0.0: enabled 1
PNP: 03f0.1: enabled 1
PNP: 03f0.2: enabled 1
PNP: 03f0.3: enabled 1
PNP: 03f0.5: enabled 1
PNP: 03f0.7: enabled 1
PNP: 03f0.8: enabled 1
PNP: 03f0.9: enabled 1
PNP: 03f0.a: enabled 1
PCI: 00:04.1: enabled 1
PCI: 00:04.2: enabled 1
PCI: 00:04.3: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0c.0: enabled 1
PNP: 03f0.6: enabled 1
CPU: 00: enabled 1
Initializing CBMEM area to 0x1feefc00 (1115136 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 1feefe00...ok
High Tables Base is 1feefc00.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x1fef0000... done.
PIRQ table: 128 bytes.
Adding CBMEM entry as no. 3
ACPI: Writing ACPI tables at 1fef1000...
ACPI: Writing cbmem_toc pointer at 1fef1024...
ACPI:     * FACS
ACPI:     * DSDT @ 1fef1140 Length 683
ACPI:     * FADT
ACPI: added table 1/32, length now 40
ACPI:    * MADT
ACPI:    * SSDT
Found 1 CPU(s).
ACPI: added table 2/32, length now 44
ACPI: done.
ACPI tables: 2354 bytes.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum 13ef
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x1fefcc00
rom_table_end = 0x1fefcc00
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x1fefcc00 to 0x1ff00000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000001feefbff: RAM
 3. 000000001feefc00-000000001fffffff: CONFIGURATION TABLES
 4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 1fefcc00 - 1fefcdbc  checksum ad8c
coreboot table: 444 bytes.
Adding CBMEM entry as no. 5
Multiboot Information structure has been written.
 0. FREE SPACE 1fffec00 00001400
 1. GDT        1feefe00 00000200
 2. IRQ TABLE  1fef0000 00001000
 3. ACPI       1fef1000 0000bc00
 4. COREBOOT   1fefcc00 00002000
 5. ACPI RESUME1fefec00 00100000
Check CBFS header at fffffc9e
magic is 4f524243
Found CBFS header at fffffc9e
Check fallback/romstage
CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700
Check fallback/coreboot_ram
CBFS: follow chain: fffc3700 + 38 + 148bf + align -> fffd8000
Check fallback/payload
Got a payload
Loading segment from rom address 0xfffd8038
  data (compression=1)
  New segment dstaddr 0xe9368 memsize 0x16c98 srcaddr 0xfffd8070 filesize 0xb69e
  (cleaned up) New segment addr 0xe9368 size 0x16c98 offset 0xfffd8070 filesize 0xb69e
Loading segment from rom address 0xfffd8054
  Entry Point 0x000fc9ef
Loading Segment: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e
lb: [0x0000000000100000, 0x0000000000134000)
Post relocation: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e
using LZMA
[ 0x000e9368, 00100000, 0x00100000) <- fffd8070
dest 000e9368, end 00100000, bouncebuffer 1fe87c00
Loaded segments
Jumping to boot code at fc9ef
entry    = 0x000fc9ef
lb_start = 0x00100000
lb_size  = 0x00034000
adjust   = 0x1fdbbc00
buffer   = 0x1fe87c00
     elf_boot_notes = 0x00124aa0
adjusted_boot_notes = 0x1fee06a0
Start bios (version pre-0.6.2-20101129_001420-nukunuku)
Found mainboard ASUS P2B
Found CBFS header at 0xfffffc9e
Ram Size=0x1feefc00 (0x0000000000000000 high)
Relocating init from 0x000e9800 to 0x1fed6500 (size 38360)
CPU Mhz=501
No apic - only the main cpu is present.
Copying PIR from 0x1fef0000 to 0x000fdc70
Copying ACPI RSDP from 0x1fef1000 to 0x000fdc50
SMBIOS ptr=0x000fdc30 table=0x1feefaf0
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version pre-0.6.2-20101129_001420-nukunuku)

UHCI init on dev 00:04.2 (io=1400)
Found 1 lpt ports
Found 2 serial ports
ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21)
ATA controller 1 at 170/374/0 (irq 15 dev 21)
ata0-0: WDC WD1200JB-00DUA0 ATA-6 Hard-Disk (111 GiBytes)
drive 0x000fdbe0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648
ebda moved from 9fc00 to 9f800
USB mouse initialized
Got ps2 nak (status=51)
All threads complete.
Scan for option roms
Press F12 for boot menu.

Returned 57344 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009f800 = 1
  1: 000000000009f800 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000001feedc00 = 1
  4: 000000001feedc00 - 0000000020000000 = 2
  5: 00000000ff800000 - 0000000100000000 = 2
enter handle_19:
  NULL
Booting from Floppy...
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from DVD/CD...
Boot failed: Could not read from CDROM (code 0001)
enter handle_18:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
[    0.000000] Linux version 2.6.35.8-netboot (ranma at nukunuku) (gcc version 4.4.5 (Debian 4.4.5-6) ) #55 Thu Nov 25 16:34:16 CET 2010
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
[    0.000000]  BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000001feedc00 (usable)
[    0.000000]  BIOS-e820: 000000001feedc00 - 0000000020000000 (reserved)
[    0.000000]  BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved)
[    0.000000] Notice: NX (Execute Disable) protection missing in CPU or disabled in BIOS!
[    0.000000] DMI 2.4 present.
[    0.000000] last_pfn = 0x1feed max_arch_pfn = 0x1000000
[    0.000000] PAT not supported by CPU.
[    0.000000] get_mtrr(0): base hi=00000000 lo=00000006, mask hi=0000000f lo=e0000800
[    0.000000] init_memory_mapping: 0000000000000000-000000001feed000
[    0.000000] ACPI: RSDP 000fdc50 00014 (v00 CORE  )
[    0.000000] ACPI: RSDT 1fef102c 0002C (v01 CORE   COREBOOT 00000000 CORE 00000000)
[    0.000000] ACPI: FACP 1fef17c3 000F4 (v01 CORE   COREBOOT 00000000 CORE 0000002A)
[    0.000000] ACPI: DSDT 1fef1140 00683 (v02 CORE   COREBOOT 00000001 INTL 20100528)
[    0.000000] ACPI: FACS 1fef1100 00040
[    0.000000] ACPI: SSDT 1fef18b7 0007B (v02 CORE   DYNADATA 0000002A CORE 0000002A)
[    0.000000] 0MB HIGHMEM available.
[    0.000000] 510MB LOWMEM available.
[    0.000000]   mapped low ram: 0 - 1feed000
[    0.000000]   low ram: 0 - 1feed000
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000001 -> 0x00001000
[    0.000000]   Normal   0x00001000 -> 0x0001feed
[    0.000000]   HighMem  empty
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[2] active PFN ranges
[    0.000000]     0: 0x00000001 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x0001feed
[    0.000000] Using APIC driver default
[    0.000000] ACPI: PM-Timer IO Port: 0xe408
[    0.000000] Local APIC disabled by BIOS -- you can enable it with "lapic"
[    0.000000] APIC: disable apic facility
[    0.000000] APIC: switched to apic NOOP
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000
[    0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000
[    0.000000] Allocating PCI resources starting at 20000000 (gap: 20000000:df800000)
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 129677
[    0.000000] Kernel command line: console=tty0 vga=ext root=/dev/sda2 ro radeon.modeset=1 console=ttyS0,115200 no_console_suspend video=matroxfb:off
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Enabling fast FPU save and restore... done.
[    0.000000] Enabling unmasked SIMD FPU exception support... done.
[    0.000000] Initializing CPU#0
[    0.000000] Subtract (24 early reservations)
[    0.000000]   #0 [0001000000 - 00018314f4]   TEXT DATA BSS
[    0.000000]   #1 [000009f800 - 0000100000]   BIOS reserved
[    0.000000]   #2 [0001832000 - 0001840049]             BRK
[    0.000000]   #3 [0000001000 - 0000005000]     ACPI WAKEUP
[    0.000000]   #4 [0000007000 - 0000008000]         PGTABLE
[    0.000000]   #5 [0001841000 - 0001842000]         BOOTMEM
[    0.000000]   #6 [0001842000 - 0001c42000]         BOOTMEM
[    0.000000]   #7 [0001831500 - 0001831504]         BOOTMEM
[    0.000000]   #8 [0001831540 - 00018315c0]         BOOTMEM
[    0.000000]   #9 [00018315c0 - 00018315f0]         BOOTMEM
[    0.000000]   #10 [0001c42000 - 0001c43000]         BOOTMEM
[    0.000000]   #11 [0001831600 - 00018316fc]         BOOTMEM
[    0.000000]   #12 [0001831700 - 0001831740]         BOOTMEM
[    0.000000]   #13 [0001831740 - 0001831780]         BOOTMEM
[    0.000000]   #14 [0001831780 - 00018317c0]         BOOTMEM
[    0.000000]   #15 [00018317c0 - 0001831800]         BOOTMEM
[    0.000000]   #16 [0001831800 - 0001831840]         BOOTMEM
[    0.000000]   #17 [0001831840 - 0001831880]         BOOTMEM
[    0.000000]   #18 [0001831880 - 0001831890]         BOOTMEM
[    0.000000]   #19 [00018318c0 - 0001831933]         BOOTMEM
[    0.000000]   #20 [0001831940 - 00018319b3]         BOOTMEM
[    0.000000]   #21 [0001c43000 - 0001c45000]         BOOTMEM
[    0.000000]   #22 [0001c45000 - 0001c85000]         BOOTMEM
[    0.000000]   #23 [0001c85000 - 0001ca5000]         BOOTMEM
[    0.000000] Initializing HighMem for node 0 (00000000:00000000)
[    0.000000] Memory: 509828k/523188k available (5091k kernel code, 12968k reserved, 2440k data, 356k init, 0k highmem)
[    0.000000] virtual kernel memory layout:
[    0.000000]     fixmap  : 0xfffa3000 - 0xfffff000   ( 368 kB)
[    0.000000]     pkmap   : 0xffc00000 - 0xffe00000   (2048 kB)
[    0.000000]     vmalloc : 0xe06ed000 - 0xffbfe000   ( 501 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xdfeed000   ( 510 MB)
[    0.000000]       .init : 0xc175c000 - 0xc17b5000   ( 356 kB)
[    0.000000]       .data : 0xc14f8e35 - 0xc175afe4   (2440 kB)
[    0.000000]       .text : 0xc1000000 - 0xc14f8e35   (5091 kB)
[    0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok.
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU-based detection of stalled CPUs is disabled.
[    0.000000] 	Verbose stalled-CPUs detection is disabled.
[    0.000000] NR_IRQS:288
[    0.000000] Console: colour VGA+ 80x50
[    0.000000] console [tty0] enabled
[    0.000000] console [ttyS0] enabled
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 501.221 MHz processor.
[    0.020014] Calibrating delay loop (skipped), value calculated using timer frequency.. 1002.44 BogoMIPS (lpj=5012210)
[    0.033010] pid_max: default: 32768 minimum: 301
[    0.040245] Mount-cache hash table entries: 512
[    0.045477] CPU serial number disabled.
[    0.050037] mce: CPU supports 5 MCE banks
[    0.054251] Performance Events: 
[    0.057342] no APIC, boot with the "lapic" boot parameter to force-enable it.
[    0.060024] no hardware sampling interrupt available.
[    0.070021] p6 PMU driver.
[    0.072926] ... version:                0
[    0.077129] ... bit width:              32
[    0.080022] ... generic registers:      2
[    0.084244] ... value mask:             00000000ffffffff
[    0.090021] ... max period:             000000007fffffff
[    0.095478] ... fixed-purpose events:   0
[    0.100020] ... event mask:             0000000000000003
[    0.105533] CPU: Intel Pentium III (Katmai) stepping 02
[    0.114924] ACPI: Core revision 20100428
[    0.125968] ACPI: setting ELCR to 0200 (from 0000)
[    0.130032] ACPI: FADT smi_command is not set, mode transitions not supported.
[    0.137646] ACPI: SCI_EN status: 1
[    0.140024] ACPI: FADT smi_command is not set, mode transitions not supported.
[    0.147644] ACPI: SCI_EN status: 1
[    0.150841] devtmpfs: initialized
[    0.155904] NET: Registered protocol family 16
[    0.163413] ACPI: bus type pci registered
[    0.171702] PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=1
[    0.178271] PCI: Using configuration type 1 for base access
[    0.276065] bio: create slab <bio-0> at 0
[    0.289230] ACPI: Interpreter enabled
[    0.290147] ACPI: (supports S0 S1 S2 S3 S5)
[    0.295061] ACPI: Using PIC for interrupt routing
[    0.319114] ACPI: No dock devices found.
[    0.320114] PCI: DMI: pci_use_crs=1 pci_probe=0000000b
[    0.325407] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.331781] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.343577] pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7]
[    0.350113] pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff]
[    0.360038] pci_root PNP0A03:00: host bridge window [mem 0x20000000-0xffffffff]
[    0.370566] * Found PM-Timer Bug on the chipset. Due to workarounds for a bug,
[    0.370574] * this clock source is slow. Consider trying other clock sources
[    0.380096] pci 0000:00:04.3: quirk: [io  0xe400-0xe43f] claimed by PIIX4 ACPI
[    0.390036] pci 0000:00:04.3: quirk: [io  0x0f00-0x0f0f] claimed by PIIX4 SMB
[    0.400527] pci 0000:00:01.0: PCI bridge to [bus 01-01]
[    0.417502] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 11 12) *0, disabled.
[    0.425108] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 12) *0, disabled.
[    0.435050] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12) *0, disabled.
[    0.445057] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 12) *0, disabled.
[    0.455640] vgaarb: device added: PCI:0000:00:0c.0,decodes=io+mem,owns=io+mem,locks=none
[    0.460096] vgaarb: loaded
[    0.464385] SCSI subsystem initialized
[    0.472061] usbcore: registered new interface driver usbfs
[    0.480474] usbcore: registered new interface driver hub
[    0.486473] usbcore: registered new device driver usb
[    0.492657] Advanced Linux Sound Architecture Driver Version 1.0.23.
[    0.500422] PCI: Using ACPI for IRQ routing
[    0.506809] cfg80211: Calling CRDA to update world regulatory domain
[    0.510567] Switching to clocksource tsc
[    0.520250] pnp: PnP ACPI init
[    0.523568] ACPI: bus type pnp registered
[    0.530439] ERROR: Unable to locate IOAPIC for GSI 1
[    0.536605] ERROR: Unable to locate IOAPIC for GSI 12
[    0.542893] ERROR: Unable to locate IOAPIC for GSI 6
[    0.550609] pnp: PnP ACPI: found 5 devices
[    0.554863] ACPI: ACPI bus type pnp unregistered
[    0.559822] system 00:04: [io  0xe400-0xe43f] has been reserved
[    0.565953] system 00:04: [io  0x0f00-0x0f0f] has been reserved
[    0.572157] system 00:04: [mem 0xff800000-0xffffffff] has been reserved
[    0.653284] pci 0000:00:01.0: PCI bridge to [bus 01-01]
[    0.658730] pci 0000:00:01.0:   bridge window [io  disabled]
[    0.664639] pci 0000:00:01.0:   bridge window [mem disabled]
[    0.670550] pci 0000:00:01.0:   bridge window [mem pref disabled]
[    0.677091] NET: Registered protocol family 2
[    0.681913] IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.689638] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    0.697862] TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
[    0.704980] TCP: Hash tables configured (established 16384 bind 16384)
[    0.711710] TCP reno registered
[    0.715075] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.721180] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.727928] NET: Registered protocol family 1
[    0.732959] RPC: Registered udp transport module.
[    0.737875] RPC: Registered tcp transport module.
[    0.742935] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.749649] pci 0000:00:00.0: Limiting direct PCI/PCI transfers
[    0.756186] kvm: no hardware support
[    0.760076] has_svm: not amd
[    0.763161] kvm: no hardware support
[    0.768562] platform rtc_cmos: registered platform RTC device (no PNP device found)
[    0.783023] VFS: Disk quotas dquot_6.5.2
[    0.787238] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.795198] fuse init (API version 7.14)
[    0.800786] Btrfs loaded
[    0.803572] msgmni has been set to 995
[    0.809702] io scheduler noop registered
[    0.813838] io scheduler deadline registered
[    0.818385] io scheduler cfq registered (default)
[    0.827368] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0
[    0.835241] ACPI: Power Button [PWRF]
[    1.387649] lp: driver loaded but no devices found
[    1.392977] Linux agpgart interface v0.103
[    1.397556] agpgart-intel 0000:00:00.0: Intel 440BX Chipset
[    1.421908] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000
[    1.430195] [drm] Initialized drm 1.1.0 20060810
[    1.435404] [drm] radeon kernel modesetting enabled.
[    1.441523] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.448620] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    1.456233] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[    1.469916] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE,EPP]
[    1.477276] parport0: irq 7 detected
[    1.560065] lp0: using parport0 (polling).
[    1.573877] loop: module loaded
[    1.580950] scsi0 : ata_piix
[    1.585086] scsi1 : ata_piix
[    1.588981] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1420 irq 14
[    1.596158] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1428 irq 15
[    1.609413] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k6-NAPI
[    1.616678] e1000: Copyright (c) 1999-2006 Intel Corporation.
[    1.623186] e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2-k4
[    1.629395] e1000e: Copyright (c) 1999 - 2009 Intel Corporation.
[    1.637221] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
[    1.643612] e100: Copyright(c) 1999-2006 Intel Corporation
[    1.654073] tun: Universal TUN/TAP device driver, 1.6
[    1.659458] tun: (C) 1999-2004 Max Krasnyansky <maxk at qualcomm.com>
[    1.666843] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
[    1.674388] ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
[    1.689610] r8169 0000:00:09.0: PCI INT A -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11
[    1.698168] r8169 0000:00:09.0: (unregistered net_device): no PCI Express capability
[    1.707107] r8169 0000:00:09.0: eth0: RTL8110s at 0xe0704000, 00:08:54:38:a1:44, XID 04000000 IRQ 11
[    1.722213] console [netcon0] enabled
[    1.726084] netconsole: network logging started
[    1.730926] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.738046] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.744970] uhci_hcd: USB Universal Host Controller Interface driver
[    1.751812] uhci_hcd 0000:00:04.2: PCI INT D -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11
[    1.760657] uhci_hcd 0000:00:04.2: UHCI Host Controller
[    1.766160] uhci_hcd 0000:00:04.2: new USB bus registered, assigned bus number 1
[    1.774070] uhci_hcd 0000:00:04.2: irq 11, io base 0x00001400
[    1.782234] hub 1-0:1.0: USB hub found
[    1.786230] hub 1-0:1.0: 2 ports detected
[    1.791224] Initializing USB Mass Storage driver...
[    1.796765] usbcore: registered new interface driver usb-storage
[    1.803095] USB Mass Storage support registered.
[    1.809199] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
[    1.817389] ata1.00: ATA-6: WDC WD1200JB-00DUA0, 65.13G65, max UDMA/100
[    1.824264] ata1.00: 234441648 sectors, multi 0: LBA48 
[    1.832453] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.837625] serio: i8042 AUX port at 0x60,0x64 irq 12
[    1.845732] mice: PS/2 mouse device common for all mice
[    1.853133] input: PC Speaker as /devices/platform/pcspkr/input/input1
[    1.860802] rtc_cmos rtc_cmos: RTC can wake from S4
[    1.866788] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    1.873560] rtc0: alarms up to one month, 114 bytes nvram
[    1.879842] i2c /dev entries driver
[    1.883982] ata1.00: configured for UDMA/33
[    1.889217] scsi 0:0:0:0: Direct-Access     ATA      WDC WD1200JB-00D 65.1 PQ: 0 ANSI: 5
[    1.901906] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB)
[    1.911646] piix4_smbus 0000:00:04.3: SMBus Host Controller at 0xf00, revision 0
[    1.919817] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input2
[    1.928927] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    1.935157] sd 0:0:0:0: [sda] Write Protect is off
[    1.941860] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    1.955158] coretemp: CPU (model=0x7) has no thermal sensor.
[    1.961398]  sda: sda1 sda2 sda3 < sda5 > sda4
[    2.024169] sd 0:0:0:0: [sda] Attached SCSI disk
[    2.110100] usb 1-1: new low speed USB device using uhci_hcd and address 2
[    2.342160] Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60 sec (nowayout= 0)
[    2.351723] md: raid1 personality registered for level 1
[    2.358459] device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel at redhat.com
[    2.367679] cpuidle: using governor ladder
[    2.372082] cpuidle: using governor menu
[    2.409011] input: Microsoft Microsoft 5-Button Mouse with IntelliEye(TM) as /devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.0/input/input3
[    2.422751] generic-usb 0003:045E:0047.0001: input: USB HID v1.10 Mouse [Microsoft Microsoft 5-Button Mouse with IntelliEye(TM)] on usb-0000:00:04.2-1/input0
[    2.437597] usbcore: registered new interface driver usbhid
[    2.443477] usbhid: USB HID core driver
[    2.447528] ramzswap: num_devices not specified. Using default: 1
[    2.453864] ramzswap: Creating 1 devices ...
[    2.462241] ALSA device list:
[    2.465365]   No soundcards found.
[    2.468987] u32 classifier
[    2.471991]     Actions configured
[    2.475612] Netfilter messages via NETLINK v0.30.
[    2.480650] nf_conntrack version 0.5.0 (7966 buckets, 31864 max)
[    2.487494] ctnetlink v0.93: registering with nfnetlink.
[    2.493259] IPv4 over IPv4 tunneling driver
[    2.498974] ip_tables: (C) 2000-2006 Netfilter Core Team
[    2.504777] TCP bic registered
[    2.507995] TCP cubic registered
[    2.511487] TCP westwood registered
[    2.515183] TCP vegas registered
[    2.518837] NET: Registered protocol family 10
[    2.525549] ip6_tables: (C) 2000-2006 Netfilter Core Team
[    2.531403] IPv6 over IPv4 tunneling driver
[    2.537852] NET: Registered protocol family 17
[    2.542668] lib80211: common routines for IEEE802.11 drivers
[    2.548627] Using IPI Shortcut mode
[    2.555356] rtc_cmos rtc_cmos: setting system clock to 2010-12-01 21:56:43 UTC (1291240603)
[    2.564577] md: Waiting for all devices to be available before autodetect
[    2.571727] md: If you don't use raid, use raid=noautodetect
[    2.578890] md: Autodetecting RAID arrays.
[    2.583339] md: Scanned 0 and added 0 devices.
[    2.588039] md: autorun ...
[    2.591107] md: ... autorun DONE.
[    2.623263] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[    2.631628] VFS: Mounted root (ext2 filesystem) readonly on device 8:2.
[    2.655607] devtmpfs: mounted
[    2.658915] Freeing unused kernel memory: 356k freed
[    2.666126] Write protecting the kernel text: 5092k
[    2.671612] Write protecting the kernel read-only data: 1896k

INIT: version 2.88 booting
booting...
Starting the hotplug events dispatcher: udevd[    4.537857] udev[1260]: starting version 163



From r.marek at assembler.cz  Wed Dec  1 22:20:35 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 01 Dec 2010 22:20:35 +0100
Subject: [coreboot] [PATCH] preview - suspend/resume S3 on K8 and 785G/710
Message-ID: <4CF6BC23.4090705@assembler.cz>

Hi all

attached patch adds the suspend/resume support for socket 939 and AMD 785G/710 
(on asrock board)

The patch is still WIP but works right now. The purpose is just to show how it 
is done.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Proper patches will hopefully follow.

Thanks
Rudolf
-------------- next part --------------
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From r.marek at assembler.cz  Wed Dec  1 22:24:03 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 01 Dec 2010 22:24:03 +0100
Subject: [coreboot] [patch 2/3] Use ACPI table area to store cbmem_toc
 pointer needed for resume
In-Reply-To: <20101201210354.952358768@yamamaya.is-a-geek.org>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
	<20101201210354.952358768@yamamaya.is-a-geek.org>
Message-ID: <4CF6BCF3.40508@assembler.cz>

Hi,

In fact I was thinking that we can add custom "OEMx" tables to ACPI and dump 
them using acpi tools. I mean we can add the hooks to ACPI so cbmem stuff is 
available per table in ACPI.

The AMD chipsets needs to use NVRAM because there is stored DQS driving values 
for memory controller. Also the cbmem address is stored there because one cannot 
find it very easily if there is frambuffer (and on AMD all access is uncached 
that time). This NVRAM is not CMOS it is just 256 bytes of storage which 
survives S3 state.

Thanks,
Rudolf



From namedylan at gmail.com  Wed Dec  1 23:07:39 2010
From: namedylan at gmail.com (Fengwei Zhang)
Date: Wed, 01 Dec 2010 17:07:39 -0500
Subject: [coreboot] source tree for ASUS M2V-MX SE cannot boot
Message-ID: <4CF6C72B.4050800@gmail.com>

Hi all,

I don't know why it doesn't work on my machine. My situation is:

revision 6061 works on my machine

revision 6062 doesn't. Serial port information is:
coreboot-4.0-r6062 Wed Dec  1 16:07:14 EST 2010 starting...
now booting...
INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
soft reset


If I remove the diff of 6061 and 6062 from the latest source tree, 
everything will work.
The diff is:

	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
			PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);

	if (dev == PCI_DEV_INVALID)


To Rodulf: My gcc version is,
[root at localhost vt8237r]# gcc --version
gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-48)


I know this is weird. It would be great if someone could help me out.

Best,
Fengwei


---
below is the message from Rudolf:

Message: 1
Date: Sun, 21 Nov 2010 16:13:25 +0100
From: Rudolf Marek <r.marek at assembler.cz>
To: coreboot at coreboot.org
Subject: Re: [coreboot] Current coreboot source tree ( revision 6084 )
	for ASUS M2V-MX SE cannot boot?
Message-ID: <4CE93715.1000701 at assembler.cz>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Hi

Just for a record I use the latest version without problems. Maybe your
binutils/gcc is wrong? What distribution/version you use?

Thanks,
Rudolf



From svn at coreboot.org  Thu Dec  2 02:50:39 2010
From: svn at coreboot.org (repository service)
Date: Thu, 02 Dec 2010 02:50:39 +0100
Subject: [coreboot] [commit] r6136 - in trunk/src/northbridge/amd/amdmct:
	mct mct_ddr3
Message-ID: <E1PNyJj-00074p-40@ra.coresystems.de>

Author: zbao
Date: Thu Dec  2 02:50:38 2010
New Revision: 6136
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6136

Log:
More explicite and straight way to set seed.
The read-modify-write wasn't needed. This is easier to understand.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Tue Nov 30 22:21:33 2010	(r6135)
+++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c	Thu Dec  2 02:50:38 2010	(r6136)
@@ -1023,13 +1023,9 @@
 
 	dev = pDCTstat->dev_dct;
 	for (index = 0x50; index <= 0x52; index ++) {
-		val = Get_NB32_index_wait(dev, index_reg, index);
-		val |= (FenceTrnFinDlySeed & 0x1F);
+		val = (FenceTrnFinDlySeed & 0x1F);
 		if (index != 0x52) {
-			val &= ~(0xFF << 8);
-			val |= (val & 0xFF) << 8;
-			val &= 0xFFFF;
-			val |= val << 16;
+			val |= val << 8 | val << 16 | val << 24;
 		}
 		Set_NB32_index_wait(dev, index_reg, index, val);
 	}

Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Tue Nov 30 22:21:33 2010	(r6135)
+++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c	Thu Dec  2 02:50:38 2010	(r6136)
@@ -972,13 +972,9 @@
 	 */
 	dev = pDCTstat->dev_dct;
 	for (index = 0x50; index <= 0x52; index ++) {
-		val = Get_NB32_index_wait(dev, index_reg, index) & ~0xFF;
-		val |= (FenceTrnFinDlySeed & 0x1F);
+		val = (FenceTrnFinDlySeed & 0x1F);
 		if (index != 0x52) {
-			val &= ~(0xFF << 8);
-			val |= (val & 0xFF) << 8;
-			val &= 0xFFFF;
-			val |= val << 16;
+			val |= val << 8 | val << 16 | val << 24;
 		}
 		Set_NB32_index_wait(dev, index_reg, index, val);
 	}



From juhe at iki.fi  Thu Dec  2 15:04:51 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Thu, 02 Dec 2010 16:04:51 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi>
	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
Message-ID: <4CF7A783.7010006@iki.fi>

30.11.2010 3:46, Liu Tao kirjoitti:
> Hi Juhana,
>
> Is the problem possiable caused by ACPI tables?
> Maybe you can remove HAVE_ACPI_TABLES from mainboard Kconfig file
> and have a try.
>

Hello Liu and others,

I tried commenting out HAVE_ACPI_TABLES, but the result was the same. I 
think ACPI tables are not accessed from SeaBIOS (or FILO, or Grub, or 
syslinux) at all. I think the first read access to ACPI tables is from 
Linux kernel. (Except for BIOS e820 calls to query available RAM.)


On the other hand, there is more progress with this port:

FILO works nicely. It recognizes IDE CD and SATA disk, and can load 
Linux kernel and initrd from SATA.

However, trying to boot that kernel results in "Decompressing Linux ... 
Out of memory while allocating output buffer."

I guess this is some kind of problem with RAM allocation. Someone is 
confused about what RAM is available and where.

Also a modified Memtest86 can be executed from SeaBIOS, but clearly it 
gets a wrong idea of memory regions to test and quickly overwrites the 
VGA buffer (display trashed) and its own executable (crash with register 
dump). If the memtest is quickly interrupted to configuration menu and 
the test region is limited to only, e.g. addresses 300M - 1G, then it 
seems to run ok. Memtest claims that it is reading the coreboot tables 
to find out RAM areas to test.



Now that I look again at the various memory maps, something seems out of 
place. Coreboot log shows that there is RAM available in two regions:

coreboot memory table:
  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1. 0000000000001000-000000000009ffff: RAM
  2. 00000000000c0000-000000002ffeffff: RAM
  3. 000000002fff0000-000000002fffffff: CONFIGURATION TABLES
  4. 0000000030000000-000000003fffffff: RESERVED
  5. 00000000e0000000-00000000efffffff: RESERVED

Then later from SeaBIOS:

e820 map has 6 items:
   0: 0000000000000000 - 000000000009f400 = 1
   1: 000000000009f400 - 00000000000a0000 = 2
   2: 00000000000f0000 - 0000000000100000 = 2
   3: 0000000000100000 - 000000002ffef000 = 1
   4: 000000002ffef000 - 0000000040000000 = 2
   5: 00000000e0000000 - 00000000f0000000 = 2

Now e820 map is not marking Coreboot map region 0, "configuration 
tables" as reserved (=2) but usable (=1). Can this be correct?

Also, the PCI resource allocation puts resources to addresses
1000 - 3fff, but maybe those are IO ports and have nothing to do with 
memory addresses?


Best regards,
Juhana Helovuo






From scott at notabs.org  Thu Dec  2 16:31:25 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 2 Dec 2010 09:31:25 -0600
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <4CF7A783.7010006@iki.fi>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi>
Message-ID: <3624A23C43C24F4C806AC7D5A5140088@m3a78>

-----Original Message-----
From: coreboot-bounces+scott=notabs.org at coreboot.org [mailto:coreboot-bounces+scott=notabs.org at coreboot.org] On Behalf Of Juhana
Helovuo
Sent: Thursday, December 02, 2010 08:05 AM
To: Liu Tao
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] Porting to Asus M4A78-EM

30.11.2010 3:46, Liu Tao kirjoitti:
> Hi Juhana,
>
> Is the problem possiable caused by ACPI tables?
> Maybe you can remove HAVE_ACPI_TABLES from mainboard Kconfig file
> and have a try.
>

]Hello Liu and others,
]
]I tried commenting out HAVE_ACPI_TABLES, but the result was the same. I 
]think ACPI tables are not accessed from SeaBIOS (or FILO, or Grub, or 
]syslinux) at all. I think the first read access to ACPI tables is from 
]Linux kernel. (Except for BIOS e820 calls to query available RAM.)
]
]
]On the other hand, there is more progress with this port:
]
]FILO works nicely. It recognizes IDE CD and SATA disk, and can load 
]Linux kernel and initrd from SATA.
]
]However, trying to boot that kernel results in "Decompressing Linux ... 
]Out of memory while allocating output buffer."
]
]I guess this is some kind of problem with RAM allocation. Someone is 
]confused about what RAM is available and where.
]
]Also a modified Memtest86 can be executed from SeaBIOS, but clearly it 
]gets a wrong idea of memory regions to test and quickly overwrites the 
]VGA buffer (display trashed) and its own executable (crash with register 
]dump). If the memtest is quickly interrupted to configuration menu and 
]the test region is limited to only, e.g. addresses 300M - 1G, then it 
]seems to run ok. Memtest claims that it is reading the coreboot tables 
]to find out RAM areas to test.

I am not too familiar with memtest86, but an overwrite of the UMA memory
should be easy to debug. From your e820 map, it looks like the DRAM
reserved for UMA use is at 30000000-3fffffff. The frame buffer maps the
same DRAM to a different address, such as D0000000. If the display is
written, then one of these two ranges is getting written. What is your
frame buffer address? 

An experiment you could do is add a PCI video card and build without UMA
graphics support.

]Now that I look again at the various memory maps, something seems out of 
]place. Coreboot log shows that there is RAM available in two regions:
]
]coreboot memory table:
]  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
]  1. 0000000000001000-000000000009ffff: RAM
]  2. 00000000000c0000-000000002ffeffff: RAM
]  3. 000000002fff0000-000000002fffffff: CONFIGURATION TABLES
]  4. 0000000030000000-000000003fffffff: RESERVED
]  5. 00000000e0000000-00000000efffffff: RESERVED
]
]Then later from SeaBIOS:
]
]e820 map has 6 items:
]   0: 0000000000000000 - 000000000009f400 = 1
]   1: 000000000009f400 - 00000000000a0000 = 2
]   2: 00000000000f0000 - 0000000000100000 = 2
]   3: 0000000000100000 - 000000002ffef000 = 1
]   4: 000000002ffef000 - 0000000040000000 = 2
]   5: 00000000e0000000 - 00000000f0000000 = 2

This looks reasonable if you are using a 1GB DIMM and 256MB
is used by UMA.

]Now e820 map is not marking Coreboot map region 0, "configuration 
]tables" as reserved (=2) but usable (=1). Can this be correct?

I think the table memory eventually becomes free for OS use.

]Also, the PCI resource allocation puts resources to addresses
]1000 - 3fff, but maybe those are IO ports and have nothing to do with 
]memory addresses?

True, memory addresses and port I/O address are unrelated.

Thanks,
Scott


]Best regards,
]Juhana Helovuo




From juhe at iki.fi  Thu Dec  2 16:53:02 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Thu, 02 Dec 2010 17:53:02 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <3624A23C43C24F4C806AC7D5A5140088@m3a78>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
Message-ID: <4CF7C0DE.7090406@iki.fi>

2.12.2010 17:31, Scott Duplichan kirjoitti:

> ]Also a modified Memtest86 can be executed from SeaBIOS, but clearly it
> ]gets a wrong idea of memory regions to test and quickly overwrites the
> ]VGA buffer (display trashed) and its own executable (crash with register
> ]dump). If the memtest is quickly interrupted to configuration menu and
> ]the test region is limited to only, e.g. addresses 300M - 1G, then it
> ]seems to run ok. Memtest claims that it is reading the coreboot tables
> ]to find out RAM areas to test.
>
> I am not too familiar with memtest86, but an overwrite of the UMA memory
> should be easy to debug. From your e820 map, it looks like the DRAM
> reserved for UMA use is at 30000000-3fffffff. The frame buffer maps the
> same DRAM to a different address, such as D0000000. If the display is
> written, then one of these two ranges is getting written. What is your
> frame buffer address?
>
> An experiment you could do is add a PCI video card and build without UMA
> graphics support.

Hello Scott,

Coreboot maps the frame buffer (or overall GPU memory) to
e0000000-efffffff.

Testing without UMA also crossed my mind, but it has to wait until I 
manage to get a VGA card with DVI and PCI or PCI-E, so I can connect to 
the mainboard and monitor. My current junk^H^H^H^Hspare parts box has 
only cards with either analog VGA & PCI or DVI & AGP.

Still, my main concern is not memtest86, but getting Linux to boot at 
least so far that I can see some kernel boot messages to know what is 
happening.


Best regards,
Juhana Helovuo




From joe at settoplinux.org  Thu Dec  2 17:04:04 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Thu, 02 Dec 2010 11:04:04 -0500
Subject: [coreboot] =?utf-8?q?iWill_mainboards=3F=3F=3F?=
Message-ID: <6996196c3e35b7fd0f3b245a6999cc16@imap.1and1.com>

Hello,
I was just looking a iWill DK8S2 Opteron board but can not find the iWill
website on the web. Anyone know what happened to them?

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From scott at notabs.org  Thu Dec  2 17:14:56 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 2 Dec 2010 10:14:56 -0600
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <4CF7C0DE.7090406@iki.fi>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
	<4CF7C0DE.7090406@iki.fi>
Message-ID: <3D745430C93A402688CDA9A631DD0114@m3a78>

-----Original Message-----
From: Juhana Helovuo [mailto:juhe at iki.fi] 
Sent: Thursday, December 02, 2010 09:53 AM
To: Scott Duplichan
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] Porting to Asus M4A78-EM

2.12.2010 17:31, Scott Duplichan kirjoitti:

> ]Also a modified Memtest86 can be executed from SeaBIOS, but clearly it
> ]gets a wrong idea of memory regions to test and quickly overwrites the
> ]VGA buffer (display trashed) and its own executable (crash with register
> ]dump). If the memtest is quickly interrupted to configuration menu and
> ]the test region is limited to only, e.g. addresses 300M - 1G, then it
> ]seems to run ok. Memtest claims that it is reading the coreboot tables
> ]to find out RAM areas to test.
>
> I am not too familiar with memtest86, but an overwrite of the UMA memory
> should be easy to debug. From your e820 map, it looks like the DRAM
> reserved for UMA use is at 30000000-3fffffff. The frame buffer maps the
> same DRAM to a different address, such as D0000000. If the display is
> written, then one of these two ranges is getting written. What is your
> frame buffer address?
>
> An experiment you could do is add a PCI video card and build without UMA
> graphics support.

]Hello Scott,
]
]Coreboot maps the frame buffer (or overall GPU memory) to
]e0000000-efffffff.
]
]Testing without UMA also crossed my mind, but it has to wait until I 
]manage to get a VGA card with DVI and PCI or PCI-E, so I can connect to 
]the mainboard and monitor. My current junk^H^H^H^Hspare parts box has 
]only cards with either analog VGA & PCI or DVI & AGP.
]
]Still, my main concern is not memtest86, but getting Linux to boot at 
]least so far that I can see some kernel boot messages to know what is 
]happening.
]
]
]Best regards,
]Juhana Helovuo

Hello Juhana,

>From your 11/28/2010 log file it looks like both mmconf and uma are
getting assigned a memory address of E0000000. A while back I found
such a conflict is possible:

"Why does the current code for handling fixed resources allow the mmconf
space to get allocated to a PCI device? Function avoid_fixed_resources
calls function constrain_resources, which recursively searches the
device tree for fixed io and memory resources. The ioapic fixed memory
address is found and avoided during the recursive search because this
southbridge device is below the level where the search starts. On the
other hand, the mmconf fixed resource is added from the northbridge code,
and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
for two reasons. One is that it is not at or below 'pci_domain 0' in the
device tree. Another reason is that its type is APIC_CLUSTER and not
PCI_DOMAIN."

My current work around for this problem is to set mmconf_base_address
to f8000000 and mmconf_bus_number to 16.

Thanks,
Scott




From mylesgw at gmail.com  Thu Dec  2 17:17:57 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Dec 2010 09:17:57 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <3D745430C93A402688CDA9A631DD0114@m3a78>
References: <4CF2B0F3.8030106@iki.fi>
	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
	<4CF7C0DE.7090406@iki.fi> <3D745430C93A402688CDA9A631DD0114@m3a78>
Message-ID: <AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>

> "Why does the current code for handling fixed resources allow the mmconf
> space to get allocated to a PCI device? Function avoid_fixed_resources
> calls function constrain_resources, which recursively searches the
> device tree for fixed io and memory resources. The ioapic fixed memory
> address is found and avoided during the recursive search because this
> southbridge device is below the level where the search starts. On the
> other hand, the mmconf fixed resource is added from the northbridge code,
> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
> for two reasons. One is that it is not at or below 'pci_domain 0' in the
> device tree. Another reason is that its type is APIC_CLUSTER and not
> PCI_DOMAIN."
I don't see any reason not to move that resource into the northbridge
to avoid that issue.  It's a simple fix.  Is there a good reason for
having the MMCONF BAR in the APIC cluster?

Thanks,
Myles



From mylesgw at gmail.com  Thu Dec  2 17:28:32 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Dec 2010 09:28:32 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi>
	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
	<4CF7C0DE.7090406@iki.fi> <3D745430C93A402688CDA9A631DD0114@m3a78>
	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
Message-ID: <AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>

On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> "Why does the current code for handling fixed resources allow the mmconf
>> space to get allocated to a PCI device? Function avoid_fixed_resources
>> calls function constrain_resources, which recursively searches the
>> device tree for fixed io and memory resources. The ioapic fixed memory
>> address is found and avoided during the recursive search because this
>> southbridge device is below the level where the search starts. On the
>> other hand, the mmconf fixed resource is added from the northbridge code,
>> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
>> for two reasons. One is that it is not at or below 'pci_domain 0' in the
>> device tree. Another reason is that its type is APIC_CLUSTER and not
>> PCI_DOMAIN."
> I don't see any reason not to move that resource into the northbridge
> to avoid that issue. ?It's a simple fix. ?Is there a good reason for
> having the MMCONF BAR in the APIC cluster?
This is what I was thinking.  Build tested only.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
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From uwe at hermann-uwe.de  Fri Dec  3 00:35:31 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Dec 2010 00:35:31 +0100
Subject: [coreboot] [patch 1/3] Add acpi_get_sleep_type() to i82371eb
 and P2B _PTS/_WAK methods
In-Reply-To: <20101201210354.600579949@yamamaya.is-a-geek.org>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
	<20101201210354.600579949@yamamaya.is-a-geek.org>
Message-ID: <20101202233531.GH21636@greenwood>

On Wed, Dec 01, 2010 at 08:46:56PM +0100, Tobias Diedrich wrote:
> Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>

Looks good (though not tested on hardware by me).

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


> Index: src/arch/i386/boot/acpi.c
> ===================================================================
> --- src/arch/i386/boot/acpi.c.orig	2010-12-01 17:50:18.000000000 +0100
> +++ src/arch/i386/boot/acpi.c	2010-12-01 17:54:01.000000000 +0100

Hm, are you diffing this stuff by hand? If so, "svn diff > foo.patch" from
the top-level dir is much simpler.


> Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
> ===================================================================
> --- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig	2010-12-01 17:50:26.000000000 +0100
> +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c	2010-12-01 17:57:09.000000000 +0100
> @@ -87,7 +88,13 @@
>  	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
>  	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
>  
> -	/* set pmcntrl default */
> +#if CONFIG_HAVE_ACPI_RESUME == 1

No "== 1" needed.

  
> Index: src/lib/cbmem.c
> ===================================================================
> --- src/lib/cbmem.c.orig	2010-12-01 17:50:18.000000000 +0100
> +++ src/lib/cbmem.c	2010-12-01 17:54:01.000000000 +0100
> @@ -198,8 +198,10 @@
>  void cbmem_initialize(void)
>  {
>  #if CONFIG_HAVE_ACPI_RESUME
> -	if (acpi_slp_type == 3) {
> +	/* Both resume from S2 and resume from S3 restart at CPU reset */
> +	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
>  		if (!cbmem_reinit(high_tables_base)) {
> +			printk(BIOS_DEBUG, "cbmem_reinit failed\n");

Does printk work at this stage already? Hm, guess it should.


> Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c
> ===================================================================
> --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> +++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c	2010-12-01 17:53:27.000000000 +0100
> @@ -0,0 +1,59 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>

Nope, (C) Tobias Diedrich, I didn't write any of this.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Dec  3 00:44:04 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Dec 2010 00:44:04 +0100
Subject: [coreboot] [PATCH] ASUS P2B ACPI sleep preparations
In-Reply-To: <20101129210200.GO32428@yumi.tdiedrich.de>
References: <20101127110246.GC32428@yumi.tdiedrich.de>
	<20101128203647.GE21636@greenwood>
	<20101129204702.GM32428@yumi.tdiedrich.de>
	<20101129210200.GO32428@yumi.tdiedrich.de>
Message-ID: <20101202234404.GI21636@greenwood>

On Mon, Nov 29, 2010 at 10:02:01PM +0100, Tobias Diedrich wrote:
> southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
> 
> Interestingly i82801gx_lpc.c has the extern but doesn't use it.

Probably some left-over. I'd drop it unless somebody objects.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Fri Dec  3 01:05:51 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Fri, 3 Dec 2010 01:05:51 +0100
Subject: [coreboot] [PATCH]Allow relocated .config location
In-Reply-To: <4CEB7289.90104@georgi-clan.de>
References: <4CEB7289.90104@georgi-clan.de>
Message-ID: <20101203000550.GJ21636@greenwood>

On Tue, Nov 23, 2010 at 08:51:37AM +0100, Patrick Georgi wrote:
> Hi,
> 
> right now, the build system assumes that .config is in $(top). abuild
> stores each board's .config by copying it into the build directory after
> the fact, while clobbering any existing files.
> 
> With the attached patch, it's possible to define a new location for
> .config, using the DOTCONFIG variable, and abuild makes use of that.
> 
> It still messes around with .xcompile and the various .config copies, so
> this is only the second step of many (I already started on that topic a
> while ago, with a minor change to Makefile), but it's a start, and
> should be self contained.
> 
> ==
> Allow user to relocate .config by using the DOTCONFIG variable.
> Make abuild use that.
> 
> Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

I built a few boards with abuild, seems to work fine.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Fri Dec  3 01:45:57 2010
From: svn at coreboot.org (repository service)
Date: Fri, 03 Dec 2010 01:45:57 +0100
Subject: [coreboot] [commit] r6137 - in trunk: payloads/libpayload/bin
	util/crossgcc
Message-ID: <E1POJmf-0004BZ-BA@ra.coresystems.de>

Author: mjones
Date: Fri Dec  3 01:45:56 2010
New Revision: 6137
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6137

Log:
Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2.
Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
Add GDB patch to handle #pragma pack in the i386-elf gcc target.

Signed-off-by: Marc Jones <marcj303 at gmail.com>
Acked-by: Stefan Reinauer <stepan at coreboot.org>

Modified:
   trunk/payloads/libpayload/bin/lpgcc
   trunk/util/crossgcc/buildgcc

Modified: trunk/payloads/libpayload/bin/lpgcc
==============================================================================
--- trunk/payloads/libpayload/bin/lpgcc	Thu Dec  2 02:50:38 2010	(r6136)
+++ trunk/payloads/libpayload/bin/lpgcc	Fri Dec  3 01:45:56 2010	(r6137)
@@ -30,6 +30,8 @@
 # let's not recurse.
 # This is a hack, I know, but it makes sure that really simple user errors
 # don't fork-bomb your machine.
+echo "CC = $CC"
+
 b=`basename $CC`
 if [ "$b" = "lpgcc" ]; then
 CC=""

Modified: trunk/util/crossgcc/buildgcc
==============================================================================
--- trunk/util/crossgcc/buildgcc	Thu Dec  2 02:50:38 2010	(r6136)
+++ trunk/util/crossgcc/buildgcc	Fri Dec  3 01:45:56 2010	(r6137)
@@ -18,8 +18,8 @@
 # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
 #
 
-CROSSGCC_DATE="May 18th, 2010"
-CROSSGCC_VERSION="1.01"
+CROSSGCC_DATE="November 16th, 2010"
+CROSSGCC_VERSION="1.02"
 
 # default settings
 TARGETDIR=`pwd`/xgcc
@@ -28,15 +28,13 @@
 
 # version numbers
 GMP_VERSION=5.0.1
-MPFR_VERSION=2.4.2
+MPFR_VERSION=3.0.0
 MPC_VERSION=0.8.2
 LIBELF_VERSION=0.8.13
-# GCC 4.5.0 is broken on some AMD boards:
-# GCC_VERSION=4.5.0 # enable for Link Time Optimization & Co
-GCC_VERSION=4.4.4
+GCC_VERSION=4.5.1
 BINUTILS_VERSION=2.20.1
-GDB_VERSION=7.1
-W32API_VERSION=3.14
+GDB_VERSION=7.2
+W32API_VERSION=3.15
 MINGWRT_VERSION=3.18
 
 # archive locations
@@ -47,8 +45,8 @@
 GCC_ARCHIVE="ftp://ftp.gwdg.de/pub/gnu/ftp/gnu/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar.bz2"
 BINUTILS_ARCHIVE="http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2"
 GDB_ARCHIVE="http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2"
-W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windows/w32api-${W32API_VERSION}/w32api-${W32API_VERSION}-mingw32-src.tar.gz"
-MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20Runtime/mingwrt-${MINGWRT_VERSION}/mingwrt-${MINGWRT_VERSION}-mingw32-src.tar.gz"
+W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibrary/Win32-API/w32api-${W32API_VERSION}/w32api-${W32API_VERSION}-mingw32-src.tar.gz"
+MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibrary/MinGW-RT/mingwrt-${MINGWRT_VERSION}/mingwrt-${MINGWRT_VERSION}-mingw32-src.tar.gz"
 
 GMP_DIR="gmp-${GMP_VERSION}"
 MPFR_DIR="mpfr-${MPFR_VERSION}"
@@ -356,7 +354,7 @@
 	cd build-libelf
 	rm -f .failed
 	echo "$HOSTCFLAGS"
-	CFLAGS="$HOSTCFLAGS"  ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \
+	CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \
 		--infodir=$TARGETDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed
 	$MAKE $JOBS || touch .failed
 	$MAKE install DESTDIR=$DESTDIR || touch .failed



From marcj303 at gmail.com  Fri Dec  3 01:46:49 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 2 Dec 2010 17:46:49 -0700
Subject: [coreboot] [patch] update crossgcc
In-Reply-To: <68F88724-A79C-42F9-94AB-22229C118276@coresystems.de>
References: <AANLkTinVTcdMEPLMvq6vZAwPTT08Lw1u0q0xepdGAKBU@mail.gmail.com>
	<AANLkTi=EJsk8VeC_ZGBvTHtHeUiVUZAiMaf2fzkw+_dC@mail.gmail.com>
	<68F88724-A79C-42F9-94AB-22229C118276@coresystems.de>
Message-ID: <AANLkTi=asisW8C0w58xyV-zcwc6uXk3s7PWU6e22PG3W@mail.gmail.com>

On Wed, Dec 1, 2010 at 11:02 AM, Stefan Reinauer
<stefan.reinauer at coresystems.de> wrote:
>
>
> On 01.12.2010, at 08:40, Marc Jones <marcj303 at gmail.com> wrote:
>
>> On Thu, Nov 18, 2010 at 4:55 PM, Marc Jones <marcj303 at gmail.com> wrote:
>>> Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2.
>>> Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
>>> Add GDB patch to handle #pragma pack in the i386-elf gcc target.
>>>
>>> Signed-off-by: Marc Jones <marcj303 at gmail.com>
>>>
>>> Tested on IEI Kino Fam10 mainboard. Can someone test that this works
>>> on some other mainboards, maybe Intel or Via based?
>>
>> ScottD and Patrick have tested on a few platforms. Has anyone else
>> tested this? Are we ready for an Ack?
>>
>> Marc
>
> Acked-by: Stefan Reinauer <stepan at coreboot.org>
>


r6137

Thanks,
Marc


-- 
http://se-eng.com



From scott at notabs.org  Fri Dec  3 01:57:32 2010
From: scott at notabs.org (Scott Duplichan)
Date: Thu, 2 Dec 2010 18:57:32 -0600
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com><4CF7A783.7010006@iki.fi>
	<3624A23C43C24F4C806AC7D5A5140088@m3a78><4CF7C0DE.7090406@iki.fi>
	<3D745430C93A402688CDA9A631DD0114@m3a78><AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
Message-ID: <7F6E40CAE8EB483E917B84CC19659098@m3a78>

On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> "Why does the current code for handling fixed resources allow the mmconf
>> space to get allocated to a PCI device? Function avoid_fixed_resources
>> calls function constrain_resources, which recursively searches the
>> device tree for fixed io and memory resources. The ioapic fixed memory
>> address is found and avoided during the recursive search because this
>> southbridge device is below the level where the search starts. On the
>> other hand, the mmconf fixed resource is added from the northbridge code,
>> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
>> for two reasons. One is that it is not at or below 'pci_domain 0' in the
>> device tree. Another reason is that its type is APIC_CLUSTER and not
>> PCI_DOMAIN."
> I don't see any reason not to move that resource into the northbridge
> to avoid that issue. ?It's a simple fix. ?Is there a good reason for
> having the MMCONF BAR in the APIC cluster?
This is what I was thinking.  Build tested only.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles



Thanks Myles. I tested using the Kino project. With mmconf_base_address
set to e0000000, mmconf_bus_number set to 256, and no patch, booting 
hangs in vbios init. Adding the patch allows it to boot, and I find no
bars overlapping the mmconf area. This patch seems to solve the problem
for me. If I get a chance, I will try Win7 boot also.

Thanks,
Scott




From mylesgw at gmail.com  Fri Dec  3 02:54:46 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Thu, 2 Dec 2010 18:54:46 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <7F6E40CAE8EB483E917B84CC19659098@m3a78>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com><4CF7A783.7010006@iki.fi>
	<3624A23C43C24F4C806AC7D5A5140088@m3a78><4CF7C0DE.7090406@iki.fi>
	<3D745430C93A402688CDA9A631DD0114@m3a78><AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<7F6E40CAE8EB483E917B84CC19659098@m3a78>
Message-ID: <C1111D702E0A4003BEE9055F8F7ED6A1@chimp>

> > I don't see any reason not to move that resource into the northbridge
> > to avoid that issue. ?It's a simple fix. ?Is there a good reason for
> > having the MMCONF BAR in the APIC cluster?
> This is what I was thinking.  Build tested only.
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
> 
> Thanks,
> Myles
> 
> Thanks Myles. I tested using the Kino project. With mmconf_base_address
> set to e0000000, mmconf_bus_number set to 256, and no patch, booting
> hangs in vbios init. Adding the patch allows it to boot, and I find no
> bars overlapping the mmconf area. This patch seems to solve the problem
> for me. If I get a chance, I will try Win7 boot also.

I'm glad it worked.  The next thing would be to fix it so that it didn't
have to be in a fixed location.  It should be relatively easy to do.

Thanks,
Myles




From stefan.reinauer at coresystems.de  Fri Dec  3 03:55:27 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Thu, 2 Dec 2010 18:55:27 -0800
Subject: [coreboot] [patch 2/3] Use ACPI table area to store cbmem_toc
	pointer needed for resume
In-Reply-To: <20101201210354.952358768@yamamaya.is-a-geek.org>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
	<20101201210354.952358768@yamamaya.is-a-geek.org>
Message-ID: <27711B6D-1DC7-4B5B-9A49-82F1C463B20A@coresystems.de>

On 01.12.2010, at 11:46, Tobias Diedrich <ranma+coreboot at tdiedrich.de> wrote:

> This adds a cbmem_toc_ptr_t structure, which is written just below the FADT,
> so we can find it using the FADP information.  The actual writing is only
> implemented for the Intel 82371EB southbridge.

Why is that needed?

Stefan

> 



From Zheng.Bao at amd.com  Fri Dec  3 06:21:42 2010
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 3 Dec 2010 13:21:42 +0800
Subject: [coreboot] [patch] add missing code for rs780 lane reversal
Message-ID: <DD1CC71B621B004FA76856E5129D6B1704551E5D@sbjgexmb1.amd.com>

Before lane reversal,
De-asserts STRAP_BIF_all_valid for PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for PCIE-GFX core.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>

Index: src/southbridge/amd/rs780/rs780_gfx.c
===================================================================
--- src/southbridge/amd/rs780/rs780_gfx.c	(revision 6137)
+++ src/southbridge/amd/rs780/rs780_gfx.c	(working copy)
@@ -1302,8 +1302,10 @@
 		if(is_dev3_present()){
 			/* step 1, lane reversal (only need if CMOS
option is enabled) */
 			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1
<< 31, 1 << 31);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1
<< 2, 1 << 2);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1
<< 3, 1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1
<< 31, 0 << 31);
 			}
 			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
 			/* step 1.1, dual-slot gfx configuration (only
need if CMOS option is enabled) */
@@ -1317,10 +1319,11 @@
 
 		}else{
 			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1
<< 31, 1 << 31);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1
<< 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1
<< 31, 0 << 31);
 			}
 			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
-			printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
 
 			if((dev->path.pci.devfn >> 3) == 2)
 				single_port_configuration(nb_dev, dev);
-------------- next part --------------
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Name: rs780_lane_reversal.patch
Type: application/octet-stream
Size: 1397 bytes
Desc: rs780_lane_reversal.patch
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20101203/ef1d5d3b/attachment.obj>

From wangqingpei at gmail.com  Fri Dec  3 07:54:07 2010
From: wangqingpei at gmail.com (Qing Pei Wang)
Date: Fri, 3 Dec 2010 14:54:07 +0800
Subject: [coreboot] [patch] add missing code for rs780 lane reversal
In-Reply-To: <DD1CC71B621B004FA76856E5129D6B1704551E5D@sbjgexmb1.amd.com>
References: <DD1CC71B621B004FA76856E5129D6B1704551E5D@sbjgexmb1.amd.com>
Message-ID: <AANLkTim+GAd__mC0DaDZg76ZCTe9vPfKdW9eEyPcJpFh@mail.gmail.com>

Acked-by: QingPei Wang<wangqingpei at gmail.com>

Best wishes
Wang Qing Pei
Phone: 86+18930528086


On Fri, Dec 3, 2010 at 1:21 PM, Bao, Zheng <Zheng.Bao at amd.com> wrote:

> Before lane reversal,
> De-asserts STRAP_BIF_all_valid for PCIE-GFX core.
> After lane reversal,
> Asserts STRAP_BIF_all_valid for PCIE-GFX core.
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
> Index: src/southbridge/amd/rs780/rs780_gfx.c
> ===================================================================
> --- src/southbridge/amd/rs780/rs780_gfx.c       (revision 6137)
> +++ src/southbridge/amd/rs780/rs780_gfx.c       (working copy)
> @@ -1302,8 +1302,10 @@
>                if(is_dev3_present()){
>                        /* step 1, lane reversal (only need if CMOS
> option is enabled) */
>                        if (cfg->gfx_lane_reversal) {
> +                               set_nbmisc_enable_bits(nb_dev, 0x36, 1
> << 31, 1 << 31);
>                                set_nbmisc_enable_bits(nb_dev, 0x33, 1
> << 2, 1 << 2);
>                                set_nbmisc_enable_bits(nb_dev, 0x33, 1
> << 3, 1 << 3);
> +                               set_nbmisc_enable_bits(nb_dev, 0x36, 1
> << 31, 0 << 31);
>                        }
>                        printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
>                        /* step 1.1, dual-slot gfx configuration (only
> need if CMOS option is enabled) */
> @@ -1317,10 +1319,11 @@
>
>                }else{
>                        if (cfg->gfx_lane_reversal) {
> +                               set_nbmisc_enable_bits(nb_dev, 0x36, 1
> << 31, 1 << 31);
>                                set_nbmisc_enable_bits(nb_dev, 0x33, 1
> << 2, 1 << 2);
> +                               set_nbmisc_enable_bits(nb_dev, 0x36, 1
> << 31, 0 << 31);
>                        }
>                        printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
> -                       printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
>
>                        if((dev->path.pci.devfn >> 3) == 2)
>                                single_port_configuration(nb_dev, dev);
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From ranma+coreboot at tdiedrich.de  Fri Dec  3 13:39:26 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Fri, 3 Dec 2010 13:39:26 +0100
Subject: [coreboot] [patch 1/3] Add acpi_get_sleep_type() to i82371eb
	and P2B	_PTS/_WAK methods
In-Reply-To: <20101202233531.GH21636@greenwood>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
	<20101201210354.600579949@yamamaya.is-a-geek.org>
	<20101202233531.GH21636@greenwood>
Message-ID: <20101203123926.GB3958@yumi.tdiedrich.de>

Uwe Hermann wrote:
> On Wed, Dec 01, 2010 at 08:46:56PM +0100, Tobias Diedrich wrote:
> > Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
> 
> Looks good (though not tested on hardware by me).
> 
> Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Great :)

> > Index: src/arch/i386/boot/acpi.c
> > ===================================================================
> > --- src/arch/i386/boot/acpi.c.orig	2010-12-01 17:50:18.000000000 +0100
> > +++ src/arch/i386/boot/acpi.c	2010-12-01 17:54:01.000000000 +0100
> 
> Hm, are you diffing this stuff by hand? If so, "svn diff > foo.patch" from
> the top-level dir is much simpler.

No, I'm using quilt.

> > Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
> > ===================================================================
> > --- src/southbridge/intel/i82371eb/i82371eb_smbus.c.orig	2010-12-01 17:50:26.000000000 +0100
> > +++ src/southbridge/intel/i82371eb/i82371eb_smbus.c	2010-12-01 17:57:09.000000000 +0100
> > @@ -87,7 +88,13 @@
> >  	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
> >  	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
> >  
> > -	/* set pmcntrl default */
> > +#if CONFIG_HAVE_ACPI_RESUME == 1
> 
> No "== 1" needed.

Ah, missed that one.

> > Index: src/lib/cbmem.c
> > ===================================================================
> > --- src/lib/cbmem.c.orig	2010-12-01 17:50:18.000000000 +0100
> > +++ src/lib/cbmem.c	2010-12-01 17:54:01.000000000 +0100
> > @@ -198,8 +198,10 @@
> >  void cbmem_initialize(void)
> >  {
> >  #if CONFIG_HAVE_ACPI_RESUME
> > -	if (acpi_slp_type == 3) {
> > +	/* Both resume from S2 and resume from S3 restart at CPU reset */
> > +	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
> >  		if (!cbmem_reinit(high_tables_base)) {
> > +			printk(BIOS_DEBUG, "cbmem_reinit failed\n");
> 
> Does printk work at this stage already? Hm, guess it should.

Yes, it does. :)

> > Index: src/southbridge/intel/i82371eb/i82371eb_wakeup.c
> > ===================================================================
> > --- /dev/null	1970-01-01 00:00:00.000000000 +0000
> > +++ src/southbridge/intel/i82371eb/i82371eb_wakeup.c	2010-12-01 17:53:27.000000000 +0100
> > @@ -0,0 +1,59 @@
> > +/*
> > + * This file is part of the coreboot project.
> > + *
> > + * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
> 
> Nope, (C) Tobias Diedrich, I didn't write any of this.

Ah, that's still in there because I first added the function to
i82371eb_pm.c, and later split it up and just copied the copyright
header from that file... 

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From ranma+coreboot at tdiedrich.de  Fri Dec  3 13:47:56 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Fri, 3 Dec 2010 13:47:56 +0100
Subject: [coreboot] [patch 2/3] Use ACPI table area to store cbmem_toc
	pointer	needed for resume
In-Reply-To: <27711B6D-1DC7-4B5B-9A49-82F1C463B20A@coresystems.de>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>
	<20101201210354.952358768@yamamaya.is-a-geek.org>
	<27711B6D-1DC7-4B5B-9A49-82F1C463B20A@coresystems.de>
Message-ID: <20101203124756.GC3958@yumi.tdiedrich.de>

Stefan Reinauer wrote:
> On 01.12.2010, at 11:46, Tobias Diedrich <ranma+coreboot at tdiedrich.de> wrote:
> 
> > This adds a cbmem_toc_ptr_t structure, which is written just below the FADT,
> > so we can find it using the FADP information.  The actual writing is only
> > implemented for the Intel 82371EB southbridge.
> 
> Why is that needed?

There needs to be some way to find the backup area needed for saving
the memory parts that will be overwritten by coreboot after
disabling CAR.  I chose to add a structure relative to the FADT
address, because thats rather easy to find.
And as Rudolf already said, maybe this should be
exported as a coreboot-specific ACPI table (but that would make
finding it a tad bit more complex I think).
Another option would be to always use a fixed area directly after 1MB
(as this should not be affected by framebuffers in main memory) instead of
below TOM.

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From joe at settoplinux.org  Fri Dec  3 16:02:57 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Dec 2010 10:02:57 -0500
Subject: [coreboot] FYI  IWILL DK8S2's CHEAP
Message-ID: <db8472af9081d2141dbfa922738c0597@imap.1and1.com>

Hello,
Just an FYI for anyone interested in a cheap powerful sever board to
develop coreboot on:

IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at $29.99
and there is 248 of them available :-)

http://cgi.ebay.com/IWILL-DK8S2-eATX-Quad-Core-2-2GHz-Opteron-Motherboard-/230548264166?pt=Motherboards&hash=item35adbf54e6


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From joe at settoplinux.org  Fri Dec  3 16:32:41 2010
From: joe at settoplinux.org (Joseph Smith)
Date: Fri, 03 Dec 2010 10:32:41 -0500
Subject: [coreboot] FYI  IWILL DK8S2's CHEAP
In-Reply-To: <db8472af9081d2141dbfa922738c0597@imap.1and1.com>
References: <db8472af9081d2141dbfa922738c0597@imap.1and1.com>
Message-ID: <f46137ac9faebe26dd00e44570408186@imap.1and1.com>



On Fri, 03 Dec 2010 10:02:57 -0500, Joseph Smith <joe at settoplinux.org>
wrote:
> Hello,
> Just an FYI for anyone interested in a cheap powerful server board to
> develop coreboot on:
> 
> IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at
$29.99
> and there is 248 of them available :-)
> 
>
http://cgi.ebay.com/IWILL-DK8S2-eATX-Quad-Core-2-2GHz-Opteron-Motherboard-/230548264166?pt=Motherboards&hash=item35adbf54e6
> 
> 
Only 247 now.... I just purchased one for myself as an early B-day present
:-)

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org




From namedylan at gmail.com  Fri Dec  3 22:02:20 2010
From: namedylan at gmail.com (Fengwei Zhang)
Date: Fri, 03 Dec 2010 16:02:20 -0500
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
Message-ID: <4CF95ADC.7010309@gmail.com>

Hi all,

 From previous emails, I have learned that S3 works at ASUS M2V_MX_SE 
after patching by Rudolf. However,I was trying to test S3 on board Asus 
M2V_MX_SE, and I have following situation, which I don't quite understand.

Testing S3 on my board M2V_MX_SE:

m2v_mx_se + coreboot: after suspend to ram, it cannot wake up(no GUI on 
monitor)

m2v_mx_se + external video card + manufacture BIOS: S3 works

m2v_mx_se + manufacture BIOS: S3 doesn't work

m2v_mx_se + external video card + coreboot: for Ubunut 10.4, I got 
kernel panic error; for CentOS 5.5, I got ACPI system tables error.


I would appreciate if someone could give me some suggestions.

Best,
Fengwei



From cristi.magherusan at net.utcluj.ro  Fri Dec  3 22:04:06 2010
From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan)
Date: Fri, 3 Dec 2010 23:04:06 +0200 (EET)
Subject: [coreboot] FYI  IWILL DK8S2's CHEAP
In-Reply-To: <f46137ac9faebe26dd00e44570408186@imap.1and1.com>
References: <db8472af9081d2141dbfa922738c0597@imap.1and1.com>
	<f46137ac9faebe26dd00e44570408186@imap.1and1.com>
Message-ID: <39623.188.24.109.204.1291410246.squirrel@intranet.utcluj.ro>

Hi,

Quite yummy for that price, too bad they won't ship outside North America...

Can anyone in the US make me a favor and buy a couple of those for me?

Thanks,
Cristi





From r.marek at assembler.cz  Fri Dec  3 23:40:45 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Fri, 03 Dec 2010 23:40:45 +0100
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
In-Reply-To: <4CF95ADC.7010309@gmail.com>
References: <4CF95ADC.7010309@gmail.com>
Message-ID: <4CF971ED.1010709@assembler.cz>

I think you need to boot kernel with acpi_sleep=s3_bios

Thanks,
Rudolf



From ranma+coreboot at tdiedrich.de  Sat Dec  4 00:09:17 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sat, 4 Dec 2010 00:09:17 +0100
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
In-Reply-To: <4CF95ADC.7010309@gmail.com>
References: <4CF95ADC.7010309@gmail.com>
Message-ID: <20101203230917.GG3958@yumi.tdiedrich.de>

Fengwei Zhang wrote:
> m2v_mx_se + external video card + coreboot: for Ubunut 10.4, I got  
> kernel panic error; for CentOS 5.5, I got ACPI system tables error.
>
> I would appreciate if someone could give me some suggestions.

For me S3 works well with an external Radeon PCIe and the radeon KMS
driver.  For a Matrox PCI card I need to use 'vbetool post' after resume
in text mode, resuming with matroxfb doesn't work).

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From namedylan at gmail.com  Sat Dec  4 02:59:35 2010
From: namedylan at gmail.com (Fengwei Zhang)
Date: Fri, 03 Dec 2010 20:59:35 -0500
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
In-Reply-To: <20101203230917.GG3958@yumi.tdiedrich.de>
References: <4CF95ADC.7010309@gmail.com>
	<20101203230917.GG3958@yumi.tdiedrich.de>
Message-ID: <4CF9A087.5000103@gmail.com>

Hi Tobias,

Could you please tell me your video card model? and what OS did you use 
for testing? Thank you!

Best,
Fengwei

On 12/03/2010 06:09 PM, Tobias Diedrich wrote:
> Fengwei Zhang wrote:
>> m2v_mx_se + external video card + coreboot: for Ubunut 10.4, I got
>> kernel panic error; for CentOS 5.5, I got ACPI system tables error.
>>
>> I would appreciate if someone could give me some suggestions.
>
> For me S3 works well with an external Radeon PCIe and the radeon KMS
> driver.  For a Matrox PCI card I need to use 'vbetool post' after resume
> in text mode, resuming with matroxfb doesn't work).
>



From r.marek at assembler.cz  Sat Dec  4 11:05:23 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 11:05:23 +0100
Subject: [coreboot] [PATCH] W83627DHG/W83627EHG fixups for virtual LDNs
In-Reply-To: <20101119092103.GB21609@greenwood>
References: <20101119092103.GB21609@greenwood>
Message-ID: <4CFA1263.908@assembler.cz>

Acked-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf



From svn at coreboot.org  Sat Dec  4 11:08:55 2010
From: svn at coreboot.org (repository service)
Date: Sat, 04 Dec 2010 11:08:55 +0100
Subject: [coreboot] [commit] r6138 - in
	trunk/src/mainboard/asrock/939a785gmh: . acpi
Message-ID: <E1POp31-0001Uu-RS@ra.coresystems.de>

Author: ruik
Date: Sat Dec  4 11:08:55 2010
New Revision: 6138
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6138

Log:
Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE)

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Acked-by: Marc Jones <marcj303 at gmail.com>

Modified:
   trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl
   trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl
   trunk/src/mainboard/asrock/939a785gmh/dsdt.asl

Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl	Fri Dec  3 01:45:56 2010	(r6137)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl	Sat Dec  4 11:08:55 2010	(r6138)
@@ -1,198 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
-	DefinitionBlock (
-		"DSDT.AML",
-		"DSDT",
-		0x01,
-		"XXXXXX",
-		"XXXXXXXX",
-		0x00010001
-		)
-	{
-		#include "debug.asl"
-	}
-*/
-
-/*
-* 0x80: POST_BASE
-* 0x3F8: DEBCOM_BASE
-* X80: POST_REGION
-* P80: PORT80
-*
-* CREG: DEBCOM_REGION
-* CUAR: DEBCOM_UART
-* CDAT: DEBCOM_DATA
-* CDLM: DEBCOM_DLM
-* DLCR: DEBCOM_LCR
-* CMCR: DEBCOM_MCR
-* CLSR: DEBCOM_LSR
-*
-* DEBUG_INIT	DINI
-*/
-
-OperationRegion(X80, SystemIO, 0x80, 1)
-	Field(X80, ByteAcc, NoLock, Preserve)
-{
-	P80, 8
-}
-
-OperationRegion(CREG, SystemIO, 0x3F8, 8)
-	Field(CREG, ByteAcc, NoLock, Preserve)
-{
-	CDAT, 8,
-	CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
-}
-
-/*
-* DINI
-* Initialize the COM port to 115,200 8-N-1
-*/
-Method(DINI)
-{
-	store(0x83, DLCR)
-	store(0x01, CDAT)	/* 115200 baud (low) */
-	store(0x00, CDLM)	/* 115200 baud (high) */
-	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
-	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
-	store(0x00, CDLM)	/* turn off interrupts */
-}
-
-/*
-* THRE
-* Wait for COM port transmitter holding register to go empty
-*/
-Method(THRE)
-{
-	and(CLSR, 0x20, local0)
-	while (Lequal(local0, Zero)) {
-		and(CLSR, 0x20, local0)
-	}
-}
-
-/*
-* OUTX
-* Send a single raw character
-*/
-Method(OUTX, 1)
-{
-	THRE()
-	store(Arg0, CDAT)
-}
-
-/*
-* OUTC
-* Send a single character, expanding LF into CR/LF
-*/
-Method(OUTC, 1)
-{
-	if (LEqual(Arg0, 0x0a)) {
-		OUTX(0x0d)
-	}
-	OUTX(Arg0)
-}
-
-/*
-* DBGN
-* Send a single hex nibble
-*/
-Method(DBGN, 1)
-{
-	and(Arg0, 0x0f, Local0)
-	if (LLess(Local0, 10)) {
-		add(Local0, 0x30, Local0)
-	} else {
-		add(Local0, 0x37, Local0)
-	}
-	OUTC(Local0)
-}
-
-/*
-* DBGB
-* Send a hex byte
-*/
-Method(DBGB, 1)
-{
-	ShiftRight(Arg0, 4, Local0)
-	DBGN(Local0)
-	DBGN(Arg0)
-}
-
-/*
-* DBGW
-* Send a hex word
-*/
-Method(DBGW, 1)
-{
-	ShiftRight(Arg0, 8, Local0)
-	DBGB(Local0)
-	DBGB(Arg0)
-}
-
-/*
-* DBGD
-* Send a hex Dword
-*/
-Method(DBGD, 1)
-{
-	ShiftRight(Arg0, 16, Local0)
-	DBGW(Local0)
-	DBGW(Arg0)
-}
-
-/*
-* DBGO
-* Send either a string or an integer
-*/
-Method(DBGO, 1)
-{
-	/* DINI() */
-	if (LEqual(ObjectType(Arg0), 1)) {
-		if (LGreater(Arg0, 0xffff)) {
-			DBGD(Arg0)
-		} else {
-			if (LGreater(Arg0, 0xff)) {
-				DBGW(Arg0)
-			} else {
-				DBGB(Arg0)
-			}
-		}
-	} else {
-		Name(BDBG, Buffer(80) {})
-		store(Arg0, BDBG)
-		store(0, Local1)
-		while (One) {
-			store(GETC(BDBG, Local1), Local0)
-			if (LEqual(Local0, 0)) {
-				return (0)
-			}
-			OUTC(Local0)
-			Increment(Local1)
-		}
-	}
-	return (0)
-}
-
-/* Get a char from a string */
-Method(GETC, 2)
-{
-	CreateByteField(Arg0, Arg1, DBGC)
-	return (DBGC)
-}

Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl	Fri Dec  3 01:45:56 2010	(r6137)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl	Sat Dec  4 11:08:55 2010	(r6138)
@@ -1,244 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
-
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
-		}
-		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
-		}
-		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, NotSerialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
-			}
-		}
-
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
-
-			Or(PPMM, 0x08, POMD)
-
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
-
-			Or(PPSM, 0x08, POMD)
-
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}

Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl	Fri Dec  3 01:45:56 2010	(r6137)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl	Sat Dec  4 11:08:55 2010	(r6138)
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00120000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}

Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl	Fri Dec  3 01:45:56 2010	(r6137)
+++ trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl	Sat Dec  4 11:08:55 2010	(r6138)
@@ -1,161 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* simple name description */
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-    	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- 	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}

Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl	Fri Dec  3 01:45:56 2010	(r6137)
+++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl	Sat Dec  4 11:08:55 2010	(r6138)
@@ -28,34 +28,12 @@
 	)
 {	/* Start of ASL file */
 	/* #include "acpi/debug.asl" */		/* Include global debug methods if needed */
+	#include "northbridge/amd/amdk8/amdk8_util.asl"
 
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
 
-	/* USB overcurrent mapping pins.   */
-	Name(UOM0, 0)
-	Name(UOM1, 2)
-	Name(UOM2, 0)
-	Name(UOM3, 7)
-	Name(UOM4, 2)
-	Name(UOM5, 2)
-	Name(UOM6, 6)
-	Name(UOM7, 2)
-	Name(UOM8, 6)
-	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
 	Name(PMOD, One)	/* Assume APIC */
 
 	/* PIC IRQ mapping registers, C00h-C01h */
@@ -80,320 +58,10 @@
 		PINH, 0x00000008,	/* Index C */
 	}
 
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI,      8,
-		/* Client Management Data register */
-		G64E,   1,
-		G64O,      1,
-		G32O,      2,
-		,       2,
-		GPSL,     2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		,     0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
-		T1EE, 1,
-		T2EE, 1,
-		Offset(0x01),	/* MiscStatus */
-		, 1,
-		T1E, 1,
-		T2E, 1,
-		Offset(0x04),	/* SmiWakeUpEventEnable3 */
-		, 7,
-		SSEN, 1,
-		Offset(0x07),	/* SmiWakeUpEventStatus3 */
-		, 7,
-		CSSM, 1,
-		Offset(0x10),	/* AcpiEnable */
-		, 6,
-		PWDE, 1,
-		Offset(0x1C),	/* ProgramIoEnable */
-		, 3,
-		MKME, 1,
-		IO3E, 1,
-		IO2E, 1,
-		IO1E, 1,
-		IO0E, 1,
-		Offset(0x1D),	/* IOMonitorStatus */
-		, 3,
-		MKMS, 1,
-		IO3S, 1,
-		IO2S, 1,
-		IO1S, 1,
-		IO0S,1,
-		Offset(0x20),	/* AcpiPmEvtBlk */
-		APEB, 16,
-		Offset(0x36),	/* GEvtLevelConfig */
-		, 6,
-		ELC6, 1,
-		ELC7, 1,
-		Offset(0x37),	/* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),	/* GPMLevelConfig1 */
-		, 1,
-		 PLC4, 1,
-		 PLC5, 1,
-		, 1,
-		 PLC6, 1,
-		 PLC7, 1,
-		Offset(0x3B),	/* PMEStatus1 */
-		GP0S, 1,
-		GM4S, 1,
-		GM5S, 1,
-		APS, 1,
-		GM6S, 1,
-		GM7S, 1,
-		GP2S, 1,
-		STSS, 1,
-		Offset(0x55),	/* SoftPciRst */
-		SPRE, 1,
-		, 1,
-		, 1,
-		PNAT, 1,
-		PWMK, 1,
-		PWNS, 1,
-
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
-
-		Offset(0x65),	/* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x68),	/* MiscEnable68 */
-		, 3,
-		TMTE, 1,
-		, 1,
-		Offset(0x92),	/* GEVENTIN */
-		, 7,
-		E7IS, 1,
-		Offset(0x96),	/* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),	/* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xA8),	/* PIO7654Enable */
-		IO4E, 1,
-		IO5E, 1,
-		IO6E, 1,
-		IO7E, 1,
-		Offset(0xA9),	/* PIO7654Status */
-		IO4S, 1,
-		IO5S, 1,
-		IO6S, 1,
-		IO7S, 1,
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
-		Field(P1EB, ByteAcc, NoLock, Preserve) {
-		TMST, 1,
-		,    3,
-		BMST,    1,
-		GBST,   1,
-		Offset(0x01),
-		PBST, 1,
-		, 1,
-		RTST, 1,
-		, 3,
-		PWST, 1,
-		SPWS, 1,
-		Offset(0x02),
-		TMEN, 1,
-		, 4,
-		GBEN, 1,
-		Offset(0x03),
-		PBEN, 1,
-		, 1,
-		RTEN, 1,
-		, 3,
-		PWDA, 1,
-	}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for 16 busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
-			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00090024),	/* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
-			STB5, 32,
-			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-			PT0D, 1,
-			PT1D, 1,
-			PT2D, 1,
-			PT3D, 1,
-			PT4D, 1,
-			PT5D, 1,
-			PT6D, 1,
-			PT7D, 1,
-			PT8D, 1,
-			PT9D, 1,
-			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
-			SBIE, 1,
-			SBME, 1,
-			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
-			SBRI, 8,
-			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
-			SBB1, 32,
-			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
-			,14,
-			P92E, 1,		/* Port92 decode enable */
-		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve){
-			/* Port 0 */
-			Offset(0x120),		/* Port 0 Task file status */
-			P0ER, 1,
-			, 2,
-			P0DQ, 1,
-			, 3,
-			P0BY, 1,
-			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
-			, 4,
-			P0IS, 4,
-			Offset(0x12C),		/* Port 0 Serial ATA control */
-			P0DI, 4,
-			Offset(0x130),		/* Port 0 Serial ATA error */
-			, 16,
-			P0PR, 1,
-
-			/* Port 1 */
-			offset(0x1A0),		/* Port 1 Task file status */
-			P1ER, 1,
-			, 2,
-			P1DQ, 1,
-			, 3,
-			P1BY, 1,
-			Offset(0x1A8),		/* Port 1 Serial ATA status */
-			P1DD, 4,
-			, 4,
-			P1IS, 4,
-			Offset(0x1AC),		/* Port 1 Serial ATA control */
-			P1DI, 4,
-			Offset(0x1B0),		/* Port 1 Serial ATA error */
-			, 16,
-			P1PR, 1,
-
-			/* Port 2 */
-			Offset(0x220),		/* Port 2 Task file status */
-			P2ER, 1,
-			, 2,
-			P2DQ, 1,
-			, 3,
-			P2BY, 1,
-			Offset(0x228),		/* Port 2 Serial ATA status */
-			P2DD, 4,
-			, 4,
-			P2IS, 4,
-			Offset(0x22C),		/* Port 2 Serial ATA control */
-			P2DI, 4,
-			Offset(0x230),		/* Port 2 Serial ATA error */
-			, 16,
-			P2PR, 1,
-
-			/* Port 3 */
-			Offset(0x2A0),		/* Port 3 Task file status */
-			P3ER, 1,
-			, 2,
-			P3DQ, 1,
-			, 3,
-			P3BY, 1,
-			Offset(0x2A8),		/* Port 3 Serial ATA status */
-			P3DD, 4,
-			, 4,
-			P3IS, 4,
-			Offset(0x2AC),		/* Port 3 Serial ATA control */
-			P3DI, 4,
-			Offset(0x2B0),		/* Port 3 Serial ATA error */
-			, 16,
-			P3PR, 1,
-		}
-	}
-
-
 	#include "acpi/routing.asl"
 
 	Scope(\_SB) {
 
-		Method(CkOT, 0){
-
-			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
-
-			if(CondRefOf(\_OSI,Local1))
-			{
-				Store(1, OSTP)                /* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSTP)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSTP)            /* Linux */
-				} Else {
-					Store(4, OSTP)            /* Gotta be WinCE */
-				}
-			}
-			Return(OSTP)
-		}
-
 		Method(_PIC, 0x01, NotSerialized)
 		{
 			If (Arg0)
@@ -402,6 +70,7 @@
 			}
 			Store(Arg0, PMOD)
 		}
+
 		Method(CIRQ, 0x00, NotSerialized){
 			Store(0, PINA)
 			Store(0, PINB)
@@ -786,333 +455,8 @@
 	Name(CSMS, 0)			/* Current System State */
 
 	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort	the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*  	\_GTS OEM Going To Sleep method
-	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*  	Exit:
-	*  		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
 
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, PWST)
-
-		/* if(DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW (Arg0)
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		/* Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 1  */
-		/* Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 2  */
-		/* Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 3  */
-		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		/* Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 5  */
-		/* Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 7 - Used for GPM7, moved to USB.asl */
-		/* Method(_L07) {
-		*	DBGO("\\_GPE\\_L07\n")
-		* }
-		*/
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		/* Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
-		* }
-		*/
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
-		* }
-		*/
-
-		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
-		* }
-		*/
-
-		/*  GPM9 SCI event - Moved to USB.asl */
-		/* Method(_L0E) {
-		*	DBGO("\\_GPE\\_L0E\n")
-		* }
-		*/
-
-		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
-		* }
-		*/
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
-		}
-
-		/*  PCIe PME# event  */
-		/* Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
-		* }
-		*/
-
-		/*  GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
-		* }
-		*/
-
-		/*  GPM1 SCI event - Moved to USB.asl */
-		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
-		* }
-		*/
-
-		/*  GPM2 SCI event - Moved to USB.asl */
-		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
-		* }
-		*/
-
-		/*  GPM3 SCI event - Moved to USB.asl */
-		/* Method(_L16) {
-		*	DBGO("\\_GPE\\_L16\n")
-		* }
-		*/
-
-		/*  GPM8 SCI event - Moved to USB.asl */
-		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
-		* }
-		*/
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
-		* }
-		*/
-
-		/*  GPM5 SCI event - Moved to USB.asl */
-		/* Method(_L1A) {
-		*	DBGO("\\_GPE\\_L1A\n")
-		* }
-		*/
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
-		* }
-		*/
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
-		* }
-		*/
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
-		* }
-		*/
-
-		/*  SATA SCI event - Moved to sata.asl */
-		/* Method(_L1F) {
-		*	 DBGO("\\_GPE\\_L1F\n")
-		* }
-		*/
-
-	} 	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
+	Name(WKST,Package(){Zero, Zero})
 
 	/* South Bridge */
 	Scope(\_SB) { /* Start \_SB scope */
@@ -1121,8 +465,7 @@
 		/*  _SB.PCI0 */
 		/* Note: Only need HID on Primary Bus */
 		Device(PCI0) {
-			External (TOM1)
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+
 			Name(_HID, EISAID("PNP0A03"))
 			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
 			Method(_BBN, 0) { /* Bus number = 0 */
@@ -1193,87 +536,6 @@
 				}
 			}
 
-			/* Describe the Southbridge devices */
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00130001)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130003)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00130004)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00130005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-
-				Method(_INI) {
-					If(LEqual(OSTP,3)){   /* If we are running Linux */
-						Store(zero, NSEN)
-						Store(one, NSDO)
-						Store(one, NSDI)
-					}
-				}
-			} /* end AZHD */
-
 			Device(LIBR) {
 				Name(_ADR, 0x00140003)
 				/* Method(_INI) {
@@ -1354,413 +616,45 @@
 				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
 			} /* end LIBR */
 
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
+		    External (BUSN)
+		    External (MMIO)
+		    External (PCIO)
+		    External (SBLK)
+		    External (TOM1)
+		    External (HCLK)
+		    External (SBDN)
+		    External (HCDN)
 
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			/* ITE8718 Support */
-			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
-				Field (IOID, ByteAcc, NoLock, Preserve)
-				{
-					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
-				}
-
-			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+		    Method (_CRS, 0, NotSerialized)
 			{
-					Offset (0x07),
-				LDN,	8,	/* Logical Device Number */
-					Offset (0x20),
-				CID1,	8,	/* Chip ID Byte 1, 0x87 */
-				CID2,	8,	/* Chip ID Byte 2, 0x12 */
-					Offset (0x30),
-				ACTR,	8,	/* Function activate */
-					Offset (0xF0),
-				APC0,	8,	/* APC/PME Event Enable Register */
-				APC1,	8,	/* APC/PME Status Register */
-				APC2,	8,	/* APC/PME Control Register 1 */
-				APC3,	8,	/* Environment Controller Special Configuration Register */
-				APC4,	8	/* APC/PME Control Register 2 */
-			}
-
-			/* Enter the 8718 MB PnP Mode */
-			Method (EPNP)
-			{
-				Store(0x87, SIOI)
-				Store(0x01, SIOI)
-				Store(0x55, SIOI)
-				Store(0x55, SIOI) /* 8718 magic number */
-			}
-			/* Exit the 8718 MB PnP Mode */
-			Method (XPNP)
-			{
-				Store (0x02, SIOI)
-				Store (0x02, SIOD)
-			}
-			/*
-			 * Keyboard PME is routed to SB600 Gevent3. We can wake
-			 * up the system by pressing the key.
-			 */
-			Method (SIOS, 1)
-			{
-				/* We only enable KBD PME for S5. */
-				If (LLess (Arg0, 0x05))
-				{
-					EPNP()
-					/* DBGO("8718F\n") */
-
-					Store (0x4, LDN)
-					Store (One, ACTR)  /* Enable EC */
-					/*
-					Store (0x4, LDN)
-					Store (0x04, APC4)
-					*/  /* falling edge. which mode? Not sure. */
-
-					Store (0x4, LDN)
-					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
-					Store (0x4, LDN)
-					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
-					XPNP()
-				}
-			}
-			Method (SIOW, 1)
-			{
-				EPNP()
-				Store (0x4, LDN)
-				Store (Zero, APC0) /* disable keyboard PME */
-				Store (0x4, LDN)
-				Store (0xFF, APC1) /* clear keyboard PME status */
-				XPNP()
-			}
-
-			Name(CRES, ResourceTemplate() {
-				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0000,			/* range minimum */
-					0x0CF7,			/* range maximum */
-					0x0000,			/* translation */
-					0x0CF8			/* length */
-				)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0D00,			/* range minimum */
-					0xFFFF,			/* range maximum */
-					0x0000,			/* translation */
-					0xF300			/* length */
-				)
-
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
-				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
-				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
-
-				/* DRAM Memory from 1MB to TopMem */
-				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
-
-				/* BIOS space just below 4GB */
-				DWORDMemory(
-					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00,			/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PCBM
+			    Name (BUF0, ResourceTemplate ()
+			    {
+				IO (Decode16,
+				0x0CF8,             // Address Range Minimum
+				0x0CF8,             // Address Range Maximum
+				0x01,               // Address Alignment
+				0x08,               // Address Length
 				)
+				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000,             // Address Space Granularity
+				0x0000,             // Address Range Minimum
+				0x0CF7,             // Address Range Maximum
+				0x0000,             // Address Translation Offset
+				0x0CF8,             // Address Length
+				,, , TypeStatic)
+			    })
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				 */
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
 
-				/* DRAM memory from 4GB to TopMem2 */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					DMHI
-				)
-
-				/* BIOS space just below 16EB */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PEBM
-				)
-
-			}) /* End Name(_SB.PCI0.CRES) */
-
-			Method(_CRS, 0) {
-				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
-				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
-				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
-				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
-				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
-				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
-				CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
-				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
-				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
-				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
-				CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
-				If(LGreater(LOMH, 0xC0000)){
-					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
-					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
-				}
-
-				/* Set size of memory from 1MB to TopMem */
-				Subtract(TOM1, 0x100000, DMLL)
-
-				/*
-				* If(LNotEqual(TOM2, 0x00000000)){
-				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	ShiftLeft(TOM2, 20, Local0)
-				*	Subtract(Local0, 0x100000000, DMHL)
-				* }
-				*/
-
-				/* If there is no memory above 4GB, put the BIOS just below 4GB */
-				If(LEqual(TOM2, 0x00000000)){
-					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
-					Store(PBLN,PBML)
-				}
-				Else {  /* Otherwise, put the BIOS just below 16EB */
-					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
-					Store(PBLN,EBML)
-				}
-
-				Return(CRES) /* note to change the Name buffer */
-			}  /* end of Method(_SB.PCI0._CRS) */
-
-			/*
-			*
-			*               FIRST METHOD CALLED UPON BOOT
-			*
-			*  1. If debugging, print current OS and ACPI interpreter.
-			*  2. Get PCI Interrupt routing from ACPI VSM, this
-			*     value is based on user choice in BIOS setup.
-			*/
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				CkOT()
-
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
-				* }
-				*/
-			} /* End Method(_SB._INI) */
 		} /* End Device(PCI0)  */
 
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
 	} /* End \_SB scope */
-
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
-
-	/* SMBUS Support */
-	Mutex (SBX0, 0x00)
-	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
-		Field (SMB0, ByteAcc, NoLock, Preserve) {
-			HSTS,   8, /* SMBUS status */
-			SSTS,   8,  /* SMBUS slave status */
-			HCNT,   8,  /* SMBUS control */
-			HCMD,   8,  /* SMBUS host cmd */
-			HADD,   8,  /* SMBUS address */
-			DAT0,   8,  /* SMBUS data0 */
-			DAT1,   8,  /* SMBUS data1 */
-			BLKD,   8,  /* SMBUS block data */
-			SCNT,   8,  /* SMBUS slave control */
-			SCMD,   8,  /* SMBUS shaow cmd */
-			SEVT,   8,  /* SMBUS slave event */
-			SDAT,   8  /* SMBUS slave data */
-	}
-
-	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
-		Store (0x1E, HSTS)
-		Store (0xFA, Local0)
-		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
-			Stall (0x64)
-			Decrement (Local0)
-		}
-
-		Return (Local0)
-	}
-
-	Method (SWTC, 1, NotSerialized) {
-		Store (Arg0, Local0)
-		Store (0x07, Local2)
-		Store (One, Local1)
-		While (LEqual (Local1, One)) {
-			Store (And (HSTS, 0x1E), Local3)
-			If (LNotEqual (Local3, Zero)) { /* read sucess */
-				If (LEqual (Local3, 0x02)) {
-					Store (Zero, Local2)
-				}
-
-				Store (Zero, Local1)
-			}
-			Else {
-				If (LLess (Local0, 0x0A)) { /* read failure */
-					Store (0x10, Local2)
-					Store (Zero, Local1)
-				}
-				Else {
-					Sleep (0x0A) /* 10 ms, try again */
-					Subtract (Local0, 0x0A, Local0)
-				}
-			}
-		}
-
-		Return (Local2)
-	}
-
-	Method (SMBR, 3, NotSerialized) {
-		Store (0x07, Local0)
-		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
-			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
-			If (LEqual (Local0, Zero)) {
-				Release (SBX0)
-				Return (0x0)
-			}
-
-			Store (0x1F, HSTS)
-			Store (Or (ShiftLeft (Arg1, One), One), HADD)
-			Store (Arg2, HCMD)
-			If (LEqual (Arg0, 0x07)) {
-				Store (0x48, HCNT) /* read byte */
-			}
-
-			Store (SWTC (0x03E8), Local1) /* 1000 ms */
-			If (LEqual (Local1, Zero)) {
-				If (LEqual (Arg0, 0x07)) {
-					Store (DAT0, Local0)
-				}
-			}
-			Else {
-				Store (Local1, Local0)
-			}
-
-			Release (SBX0)
-		}
-
-		/* DBGO("the value of SMBusData0 register ") */
-		/* DBGO(Arg2) */
-		/* DBGO(" is ") */
-		/* DBGO(Local0) */
-		/* DBGO("\n") */
-
-		Return (Local0)
-	}
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
 }
 /* End of ASL file */



From r.marek at assembler.cz  Sat Dec  4 11:12:11 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 11:12:11 +0100
Subject: [coreboot] [PATCH] 939a785gmh ACPI diet
In-Reply-To: <AANLkTimgzwsoi6G0kORTaK+HdTamKVmuc6vj1ZWwExMe@mail.gmail.com>
References: <4CF569C1.2060905@assembler.cz>
	<AANLkTimgzwsoi6G0kORTaK+HdTamKVmuc6vj1ZWwExMe@mail.gmail.com>
Message-ID: <4CFA13FB.5000806@assembler.cz>

Committed revision 6138.
Thanks,
Rudolf



From r.marek at assembler.cz  Sat Dec  4 14:05:40 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 14:05:40 +0100
Subject: [coreboot] [PATCH] SB700 common FADT
Message-ID: <4CFA3CA4.30506@assembler.cz>

Following patch makes just one fadt.c file.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

svn remove src/./asus/m4a785-m/fadt.c
svn remove src/./amd/mahogany/fadt.c
svn remove src/./amd/mahogany_fam10/fadt.c
svn remove src/./amd/tilapia_fam10/fadt.c
svn remove src/./gigabyte/ma78gm/fadt.c
svn remove src/./gigabyte/ma785gmt/fadt.c
svn remove src/./jetway/pa78vm5/fadt.c
svn remove src/./asrock/939a785gmh/fadt.c
svn remove src/./iei/kino-780am2-fam10/fadt.c

I think the init of IO can be moved more early so we can use it for 
suspend/resune. As well the IO should be reserved. Maybe next patch.
Similar patch should be done for SB600. This patch is only compile tested I can 
test this on asrock next week.

Thanks,
Rudolf
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From r.marek at assembler.cz  Sat Dec  4 15:20:23 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 15:20:23 +0100
Subject: [coreboot] [patch 2/3] Use ACPI table area to store cbmem_toc
 pointer	needed for resume
In-Reply-To: <20101203124756.GC3958@yumi.tdiedrich.de>
References: <20101201194655.526093264@yamamaya.is-a-geek.org>	<20101201210354.952358768@yamamaya.is-a-geek.org>	<27711B6D-1DC7-4B5B-9A49-82F1C463B20A@coresystems.de>
	<20101203124756.GC3958@yumi.tdiedrich.de>
Message-ID: <4CFA4E27.2080002@assembler.cz>

> Another option would be to always use a fixed area directly after 1MB
> (as this should not be affected by framebuffers in main memory) instead of
> below TOM.
Nope the memory must be free (and not reserved) all bootloaders expect that it 
is free. ACPI specs says first hole can be 15-16MB.

Thanks,
Rudolf




From uwe at hermann-uwe.de  Sat Dec  4 15:47:08 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 4 Dec 2010 15:47:08 +0100
Subject: [coreboot] [patch] update crossgcc
In-Reply-To: <AANLkTi=asisW8C0w58xyV-zcwc6uXk3s7PWU6e22PG3W@mail.gmail.com>
References: <AANLkTinVTcdMEPLMvq6vZAwPTT08Lw1u0q0xepdGAKBU@mail.gmail.com>
	<AANLkTi=EJsk8VeC_ZGBvTHtHeUiVUZAiMaf2fzkw+_dC@mail.gmail.com>
	<68F88724-A79C-42F9-94AB-22229C118276@coresystems.de>
	<AANLkTi=asisW8C0w58xyV-zcwc6uXk3s7PWU6e22PG3W@mail.gmail.com>
Message-ID: <20101204144707.GK21636@greenwood>

On Thu, Dec 02, 2010 at 05:46:49PM -0700, Marc Jones wrote:
> >>> Tested on IEI Kino Fam10 mainboard. Can someone test that this works
> >>> on some other mainboards, maybe Intel or Via based?
> >>
> >> ScottD and Patrick have tested on a few platforms. Has anyone else
> >> tested this? Are we ready for an Ack?
> >>
> >> Marc
> >
> > Acked-by: Stefan Reinauer <stepan at coreboot.org>
> >
> 
> 
> r6137

Yup, also did a few tests on mingw and Linux, didn't notice any issues
so far and both abuilds did complete without errors. I'll test on a
bunch of boards (Intel, VIA, others) soonish but I don't expect issues.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Sat Dec  4 15:51:32 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sat, 4 Dec 2010 15:51:32 +0100
Subject: [coreboot] [PATCH] SB700 common FADT
In-Reply-To: <4CFA3CA4.30506@assembler.cz>
References: <4CFA3CA4.30506@assembler.cz>
Message-ID: <20101204145131.GL21636@greenwood>

On Sat, Dec 04, 2010 at 02:05:40PM +0100, Rudolf Marek wrote:
> Following patch makes just one fadt.c file.
> 
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
> 
> svn remove src/./asus/m4a785-m/fadt.c
> svn remove src/./amd/mahogany/fadt.c
> svn remove src/./amd/mahogany_fam10/fadt.c
> svn remove src/./amd/tilapia_fam10/fadt.c
> svn remove src/./gigabyte/ma78gm/fadt.c
> svn remove src/./gigabyte/ma785gmt/fadt.c
> svn remove src/./jetway/pa78vm5/fadt.c
> svn remove src/./asrock/939a785gmh/fadt.c
> svn remove src/./iei/kino-780am2-fam10/fadt.c

Yup, great! These are full copies, even the MD5 sums match.
Good riddance.

Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

And yes, I think we should do the same on a bunch of other chipsets
indeed.

 
Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From juhe at iki.fi  Sat Dec  4 18:12:43 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Sat, 04 Dec 2010 19:12:43 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
Message-ID: <4CFA768B.5010008@iki.fi>

Myles Watson wrote:
> On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>> "Why does the current code for handling fixed resources allow the mmconf
>>> space to get allocated to a PCI device? Function avoid_fixed_resources
>>> calls function constrain_resources, which recursively searches the
>>> device tree for fixed io and memory resources. The ioapic fixed memory
>>> address is found and avoided during the recursive search because this
>>> southbridge device is below the level where the search starts. On the
>>> other hand, the mmconf fixed resource is added from the northbridge code,
>>> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
>>> for two reasons. One is that it is not at or below 'pci_domain 0' in the
>>> device tree. Another reason is that its type is APIC_CLUSTER and not
>>> PCI_DOMAIN."
>> I don't see any reason not to move that resource into the northbridge
>> to avoid that issue.  It's a simple fix.  Is there a good reason for
>> having the MMCONF BAR in the APIC cluster?
> This is what I was thinking.  Build tested only.
> 
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
> 

Oh, this was very good! Thank you! Now I can load Linux kernel on the 
M4A78-EM, although it doesn't boot successfully yet.

The boot is via Coreboot -> SeaBIOS -> Grub2 (Debian default) from SATA 
-> Linux from SATA disk.

Linux boot seems to proceed otherwise nicely, except that it has 
problems initializing SATA and USB controllers on the SB700. IDE works 
better, as it can at least identify the CD drive model. ACPI does not 
work either. The boot log is attached.

At least USB is complaining about missing interrupts. Perhaps that is 
also the case with SATA.

I'll have to do some more testing to find out more.


Best regards,
Juhana Helovuo
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From r.marek at assembler.cz  Sat Dec  4 18:28:28 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 18:28:28 +0100
Subject: [coreboot] [PATCH] let high memory size be decided in cbmem.h
Message-ID: <4CFA7A3C.3020206@assembler.cz>

Hi all,

We hardcode highmemory size in  every northbridge! This is bad, and especially 
if suspend to ram is involved. Let the default be taken from cbmem.h which also 
handles the suspend logic.

Abuild tested. Please check all changes if I did not make any wrong while 
converting this to bytes.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf
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From juhe at iki.fi  Sat Dec  4 20:26:30 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Sat, 04 Dec 2010 21:26:30 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <4CFA768B.5010008@iki.fi>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<4CFA768B.5010008@iki.fi>
Message-ID: <4CFA95E6.8030800@iki.fi>

Juhana Helovuo wrote:
> Oh, this was very good! Thank you! Now I can load Linux kernel on the 
> M4A78-EM, although it doesn't boot successfully yet.
[...]
> 
> I'll have to do some more testing to find out more.

More testing done, and now Linux boots to login prompt.

I regenerated irq_tables.c, and noticed that ACPI was missing because 
-oops- it was disabled in Kconfig. After these fixes, Linux finds 
interrupts for USB and SATA controllers.

The system seems to run quite nicely, e.g. SATA, IDE, Ethernet, USB, and 
VGA work. All of this is integrated to the mainboard.  Linux boots to 
X.org and it works, USB mouse and all. "sensors" finds (CPU?) 
temperature sensor and gives a sane readout. ACPI poweroff does not yet 
work. The kernel is also adjusting CPU frequency with "powernow-k8" 
right out of the box.

Also booting Debian installer CD from SeaBIOS seems to work, although I 
did not test through the entire install process.

The only changes from M4A785-M to M4A78-EM so far are:

* config option SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not needed
* changed MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
* regenerated irq_tables.c


Should I make patches for this board to create an almost identical 
board-specific directory?

I am in doubt, because there is already much stuff there that I suspect 
to be invalid, unnecessary, or otherwise needlessly duplicated, since it 
has been originally copy-pasted from AMD Tilapia board.

Best regards,
Juhana Helovuo




From r.marek at assembler.cz  Sat Dec  4 20:55:18 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 20:55:18 +0100
Subject: [coreboot] [PATCH] exit from self-refresh on AMD K8 CPUs (pre revF)
Message-ID: <4CFA9CA6.3070904@assembler.cz>

Hello,

Following patch adds support to bring out the memory out of self refresh when 
doing resume.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

The patch is based on my 2008 patch.

Thanks,
Rudolf
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From stefan.reinauer at coresystems.de  Sat Dec  4 21:00:08 2010
From: stefan.reinauer at coresystems.de (Stefan Reinauer)
Date: Sat, 04 Dec 2010 12:00:08 -0800
Subject: [coreboot] [RFC] simplify names
Message-ID: <4CFA9DC8.7010908@coresystems.de>


stepan at ra:~/svn/coreboot/src/southbridge/amd/sb700> ls
chip.h
Kconfig
Makefile.inc
sb700.c
sb700_early_setup.c
sb700_enable_usbdebug.c
sb700.h
sb700_hda.c
sb700_ide.c
sb700_lpc.c
sb700_pci.c
sb700_reset.c
sb700_sata.c
sb700_smbus.c
sb700_smbus.h
sb700_sm.c
sb700_usb.c

The sb700_ prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan at coresystems.de>
I'm not going to post a patch, as it can not properly reflect the file
renames anyways.

What do you think?


Stefan



From svn at coreboot.org  Sat Dec  4 21:50:39 2010
From: svn at coreboot.org (repository service)
Date: Sat, 04 Dec 2010 21:50:39 +0100
Subject: [coreboot] [commit] r6139 - trunk/util/acpi
Message-ID: <E1POz43-0002es-KN@ra.coresystems.de>

Author: stepan
Date: Sat Dec  4 21:50:39 2010
New Revision: 6139
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6139

Log:
ACPI table dumping wrapper script

Signed-off-by: Stefan Reinauer <stepan at coreboot.org>
Acked-by: Stefan Reinauer <stepan at coreboot.org>

Added:
   trunk/util/acpi/
   trunk/util/acpi/acpidump-all   (contents, props changed)

Added: trunk/util/acpi/acpidump-all
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/util/acpi/acpidump-all	Sat Dec  4 21:50:39 2010	(r6139)
@@ -0,0 +1,50 @@
+#!/bin/bash
+#
+# Copyright (C) 2007-2010 by coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
+#
+
+rm -rf out
+mkdir out
+ 
+# walk through all ACPI tables with their addresses
+# example: 
+#    RSDT @ 0xcf6794ba
+# we can not just dump the tables by their names because some 
+# machines have double ACPI tables
+
+acpidump | grep "@ 0x" | while read line
+do
+  NAME=$( echo `echo $line|cut -f1 -d@` )
+  FNAME=$( echo $NAME | sed s/\ /_/g |sed s/\!/b/g )
+  ADDR=$( echo `echo $line|cut -f2 -d@` )
+  if [ "${!FNAME}" == "" ]; then
+    eval $FNAME=0
+  else
+    eval $FNAME=$(( ${!FNAME} + 1 ))
+  fi
+  printf "Processing table \"$NAME\" at $ADDR ... "
+  printf "${!FNAME} tables of that kind found before.\n"
+
+  # acpidump -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.txt
+  acpidump -b -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.bin
+  if [ "`file -b out/$FNAME-$ADDR-${!FNAME}.bin`" != "ASCII text" ]; then
+    iasl -d out/$FNAME-$ADDR-${!FNAME}.bin &>/dev/null
+  else
+    printf "Skipping $NAME because it was not dumped correctly.\n\n"
+  fi
+
+done
+



From r.marek at assembler.cz  Sat Dec  4 22:55:04 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 22:55:04 +0100
Subject: [coreboot] [PATCH] Add SB700 suspend/resume code
Message-ID: <4CFAB8B8.1040609@assembler.cz>

Hello,

Following patch adds support for suspend/resume functions. I had to change the 
get_cbmem_toc because macro magic did not work well.

The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should 
work when used with am2 boards. In fact maybe the suspend will work on mahogany 
or others ;) - with some  simple patch which follows for asrock.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf
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From r.marek at assembler.cz  Sat Dec  4 22:57:33 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sat, 04 Dec 2010 22:57:33 +0100
Subject: [coreboot] [PATCH] Add Asrock board s3 support
Message-ID: <4CFAB94D.2020509@assembler.cz>

Hello,

This patch just turns on the ACPI resume support and adds needed cbmem.c. I 
think this can be changed not to include it in some further patch.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

I can test all patches next week, now they are just compile tested and based on 
the preview patch.

Rudolf
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From patrick at georgi-clan.de  Sat Dec  4 23:32:27 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sat, 04 Dec 2010 23:32:27 +0100
Subject: [coreboot] [RFC] simplify names
In-Reply-To: <4CFA9DC8.7010908@coresystems.de>
References: <4CFA9DC8.7010908@coresystems.de>
Message-ID: <4CFAC17B.3030702@georgi-clan.de>

Am 04.12.2010 21:00, schrieb Stefan Reinauer:
> Since Kconfig (actually since shortly before we switched to Kconfig) we
> don't suffer from that problem anymore. So we could drop the sb700_
> prefix from all those filenames (or, the <componentname>_ prefix in general)
> 
> - makes it easier to fork off a new chipset
> - makes it easier to diff against other chipsets
> - storing redundant information in filenames seems wrong
> 
> Signed-off-by: <stepan at coresystems.de>
> I'm not going to post a patch, as it can not properly reflect the file
> renames anyways.
> 
> What do you think?
I really like that!

Once abuild-tested:
Acked-by: Patrick Georgi <patrick at georgi-clan.de>


Thanks,
Patrick



From mylesgw at gmail.com  Sun Dec  5 04:06:34 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Sat, 4 Dec 2010 20:06:34 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <4CFA768B.5010008@iki.fi>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<4CFA768B.5010008@iki.fi>
Message-ID: <B2874E69A60E4811A9FAD70CBB35493F@chimp>

> >> I don't see any reason not to move that resource into the northbridge
> >> to avoid that issue.  It's a simple fix.  Is there a good reason for
> >> having the MMCONF BAR in the APIC cluster?
> > This is what I was thinking.  Build tested only.
> >
> > Signed-off-by: Myles Watson <mylesgw at gmail.com>
> >
> 
> Oh, this was very good! Thank you! Now I can load Linux kernel on the
> M4A78-EM, although it doesn't boot successfully yet.

I'm glad it's getting better.  Your e820 doesn't look right, though.

[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
[    0.000000]  BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000002ffef000 (usable)
[    0.000000]  BIOS-e820: 000000002ffef000 - 0000000040000000 (reserved)
[    0.000000]  BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved)

Your devices have resources mapped from c0000000-e0000000 that don't show
up.  I can't remember where it would get that value from, but I think it is
worth looking into.

Thanks,
Myles




From juhe at iki.fi  Sun Dec  5 11:59:32 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Sun, 05 Dec 2010 12:59:32 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <B2874E69A60E4811A9FAD70CBB35493F@chimp>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<4CFA768B.5010008@iki.fi> <B2874E69A60E4811A9FAD70CBB35493F@chimp>
Message-ID: <4CFB7094.4030608@iki.fi>

Myles Watson wrote:
>>>> I don't see any reason not to move that resource into the northbridge
>>>> to avoid that issue.  It's a simple fix.  Is there a good reason for
>>>> having the MMCONF BAR in the APIC cluster?
>>> This is what I was thinking.  Build tested only.
>>>
>>> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>>>
>> Oh, this was very good! Thank you! Now I can load Linux kernel on the
>> M4A78-EM, although it doesn't boot successfully yet.
> 
> I'm glad it's getting better.  Your e820 doesn't look right, though.
> 
> [    0.000000] BIOS-provided physical RAM map:
> [    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
> [    0.000000]  BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
> [    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
> [    0.000000]  BIOS-e820: 0000000000100000 - 000000002ffef000 (usable)
> [    0.000000]  BIOS-e820: 000000002ffef000 - 0000000040000000 (reserved)
> [    0.000000]  BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved)
> 
> Your devices have resources mapped from c0000000-e0000000 that don't show
> up.  I can't remember where it would get that value from, but I think it is
> worth looking into.

Yes, now I have the board booting to Linux.

And you are right, the PCI resources do not show up. The resources of 
the PCI root device include

PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit 
dff8
PCI: 00:18.0 resource base d0000000 size 4400000 align 26 gran 20 limit 
dfff0


These resources do not show up in the coreboot table either:

coreboot memory table:
  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1. 0000000000001000-000000000009ffff: RAM
  2. 00000000000c0000-000000002ffeffff: RAM
  3. 000000002fff0000-000000002fffffff: CONFIGURATION TABLES
  4. 0000000030000000-000000003fffffff: RESERVED
  5. 00000000e0000000-00000000efffffff: RESERVED
Wrote coreboot table at: 2fffe000 - 2fffe1bc  checksum ba50


But does it really matter? There is now physical RAM only up to 
40000000. Or is it going to be a problem if there is more than 3 GB RAM?

Best regards,
Juhana Helovuo






From juhe at iki.fi  Sun Dec  5 12:26:36 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Sun, 05 Dec 2010 13:26:36 +0200
Subject: [coreboot] Upgrading SPI ROM chip?
Message-ID: <4CFB76EC.7090106@iki.fi>

Hello All,

How does a chipset know the size of the SPI BIOS ROM on board? I am 
thinking specifically the AMD RS780+SB7x0 chipset.

It could be that the chipset reads the SPI ROM size from the ROM chip 
itself at boot. In such case it should be possible to upgrade a 1 MByte 
chip to 2M or 4M just by plugging in another chip. Has anyone tried this?

Best regards,
Juhana Helovuo



From sander at vermin.nl  Sun Dec  5 13:31:50 2010
From: sander at vermin.nl (Sander Vermin)
Date: Sun, 05 Dec 2010 13:31:50 +0100
Subject: [coreboot] MSI K9A2 Platinum v2 support?
Message-ID: <4CFB8636.1000408@vermin.nl>

Hey guys,

I have a MSI K9A2 Platinum v2 (MS-7376) [1] motherboard, it has a AMD? 
790FX+SB600 chipset. I would like to experiment with coreboot (and 
seabios). How much work would it be to get this board supported?

I boot my system from a 3ware SE9650 raid controller is this supported 
in coreboot?

I have some skills soldering (smd 0402, tssop and other small stuff) can 
read/write c (lowlevel) code and develop hardware for $DAYJOB. What kind 
of debugging tools do I need? I saw the post cards and usb debug port 
debuggers how much do these cost?

Best regards,

Sander Vermin

[1]http://www.msi.com/index.php?func=proddesc&maincat_no=1&cat2_no=171&prod_no=1395



From r.marek at assembler.cz  Sun Dec  5 14:13:06 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 05 Dec 2010 14:13:06 +0100
Subject: [coreboot] Upgrading SPI ROM chip?
In-Reply-To: <4CFB76EC.7090106@iki.fi>
References: <4CFB76EC.7090106@iki.fi>
Message-ID: <4CFB8FE2.5010600@assembler.cz>

> chip to 2M or 4M just by plugging in another chip. Has anyone tried this?

Yes the chipset support 16MB chip. But I think we dont have tinybootblock yet 
and one must setup the decodes early. Check regs 48 annd 6c 6a.

I just use 1MB.

Thanks,
Rudolf



From c-d.hailfinger.devel.2006 at gmx.net  Sun Dec  5 14:33:34 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Sun, 05 Dec 2010 14:33:34 +0100
Subject: [coreboot] Upgrading SPI ROM chip?
In-Reply-To: <4CFB76EC.7090106@iki.fi>
References: <4CFB76EC.7090106@iki.fi>
Message-ID: <4CFB94AE.7090008@gmx.net>

On 05.12.2010 12:26, Juhana Helovuo wrote:
> How does a chipset know the size of the SPI BIOS ROM on board

Chipsets do not know the size of the flash ROM chip.


> It could be that the chipset reads the SPI ROM size from the ROM chip
> itself at boot.

That is not possible because the flash chip does not have any command
which returns the chip size.

Chipsets and flash chips cooperate with a trick:
The chipset sends the full mapped address (e.g. 0xfff00000) to the flash
chip, and the flash chip simply ignores the upper address bits. This
ensures that all flash chips are automatically aligned to the top of the
4 GB address space regardless of flash chip size.

Note: Sometimes the chipset strips the upper address bits (e.g. strip 8
upper bits, keep lower 24 bits) if it knows that no compatible flash
chip is larger than any stripped address. You don't have to care about
that, the chipset and the flash chip will just work right automatically
with their ignore-upper-address-bits trick.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From juhe at iki.fi  Sun Dec  5 15:39:54 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Sun, 05 Dec 2010 16:39:54 +0200
Subject: [coreboot] [PATCH] Support for Asus M4A78-EM mainboard
Message-ID: <4CFBA43A.6030306@iki.fi>

Hello,

Here is a patch to get Asus M4A78-EM supported and booting Linux.

Files attached are:

* Boot log with the patches applied.

* Board-specific patch for SVN 6139

* Resend of Myles Watson's patch for AMD Northbridge, because the 
original did not work for me without manual editing. It is also needed 
for booting Linux.


Before applying the patch, the board directory should be created with

% svn cp src/mainboard/asus/m4a785-m src/mainboard/asus/m4a78-em


Signed-off-by: Juhana Helovuo <juhe at iki.fi>


Best regards,
Juhana Helovuo
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From r.marek at assembler.cz  Sun Dec  5 17:57:39 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 05 Dec 2010 17:57:39 +0100
Subject: [coreboot] [PATCH] compile cbmem.c instead of including it in
	romstage
Message-ID: <4CFBC483.9050508@assembler.cz>

Hi all,

The subjects says that. Compile cbmem.c instead of including it in romstage,
and do that only if resume is done.

Signed-off-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf
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From patrick at georgi-clan.de  Sun Dec  5 19:07:15 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Sun, 05 Dec 2010 19:07:15 +0100
Subject: [coreboot] [PATCH] compile cbmem.c instead of including it in
 romstage
In-Reply-To: <4CFBC483.9050508@assembler.cz>
References: <4CFBC483.9050508@assembler.cz>
Message-ID: <4CFBD4D3.60800@georgi-clan.de>

Am 05.12.2010 17:57, schrieb Rudolf Marek:
> [patch]
__PRE_RAM__ isn't necessary anymore because the code is only ever run
after RAM is around, yes?

> +	printk(BIOS_WARNING, "WARNING: you need to define this for your chipset\n");
> +	return NULL;
Also, please specify "this" some more here - "need to define
get_cbmem_toc()" maybe?


Patrick



From namedylan at gmail.com  Sun Dec  5 19:35:43 2010
From: namedylan at gmail.com (Fengwei Zhang)
Date: Sun, 05 Dec 2010 13:35:43 -0500
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
In-Reply-To: <20101203230917.GG3958@yumi.tdiedrich.de>
References: <4CF95ADC.7010309@gmail.com>
	<20101203230917.GG3958@yumi.tdiedrich.de>
Message-ID: <4CFBDB7F.5080107@gmail.com>

Hi Tobias,

Thank you for your reply.
Have you test S3 on the integrated video card on board M2V_MX_SE? What 
is the result if you did?

Have you test S3 on the GeForce video card. What is the result? What is 
the result if you did?

Thank you very much!

Best,
Fengwei

on 12/03/2010 06:09 PM, Tobias Diedrich wrote:
> Fengwei Zhang wrote:
>> m2v_mx_se + external video card + coreboot: for Ubunut 10.4, I got
>> kernel panic error; for CentOS 5.5, I got ACPI system tables error.
>>
>> I would appreciate if someone could give me some suggestions.
>
> For me S3 works well with an external Radeon PCIe and the radeon KMS
> driver.  For a Matrox PCI card I need to use 'vbetool post' after resume
> in text mode, resuming with matroxfb doesn't work).
>



From r.marek at assembler.cz  Sun Dec  5 19:58:11 2010
From: r.marek at assembler.cz (Rudolf Marek)
Date: Sun, 05 Dec 2010 19:58:11 +0100
Subject: [coreboot] [PATCH] compile cbmem.c instead of including it in
 romstage
In-Reply-To: <4CFBD4D3.60800@georgi-clan.de>
References: <4CFBC483.9050508@assembler.cz> <4CFBD4D3.60800@georgi-clan.de>
Message-ID: <4CFBE0C3.5060500@assembler.cz>

Dne 5.12.2010 19:07, Patrick Georgi napsal(a):
> Am 05.12.2010 17:57, schrieb Rudolf Marek:
>> [patch]
> __PRE_RAM__ isn't necessary anymore because the code is only ever run
> after RAM is around, yes?
>
>> +	printk(BIOS_WARNING, "WARNING: you need to define this for your chipset\n");
>> +	return NULL;
> Also, please specify "this" some more here - "need to define
> get_cbmem_toc()" maybe?


Yeah I will fix it - i will retry in the week with all those changes.

Thanks,
Rudolf

>
>
> Patrick
>



From ranma+coreboot at tdiedrich.de  Sun Dec  5 21:15:13 2010
From: ranma+coreboot at tdiedrich.de (Tobias Diedrich)
Date: Sun, 5 Dec 2010 21:15:13 +0100
Subject: [coreboot] S3(Suspend to RAM) on board ASUS M2V_MX -SE
In-Reply-To: <4CFBDB7F.5080107@gmail.com>
References: <4CF95ADC.7010309@gmail.com>
	<20101203230917.GG3958@yumi.tdiedrich.de>
	<4CFBDB7F.5080107@gmail.com>
Message-ID: <20101205201513.GJ3958@yumi.tdiedrich.de>

Fengwei Zhang wrote:
> Have you test S3 on the integrated video card on board M2V_MX_SE? What  
> is the result if you did?
>
> Have you test S3 on the GeForce video card. What is the result? What is  
> the result if you did?

The M2V I have does not have builtin graphics (plain M2V, not M2V MX
SE).  I also don't have a GeForce card I could test with.

HTH,

-- 
Tobias						PGP: http://8ef7ddba.uguu.de



From svn at coreboot.org  Sun Dec  5 23:36:15 2010
From: svn at coreboot.org (repository service)
Date: Sun, 05 Dec 2010 23:36:15 +0100
Subject: [coreboot] [commit] r6140 - in trunk/src: include/device
	mainboard/asrock/939a785gmh mainboard/asus/a8v-e_deluxe
	mainboard/asus/a8v-e_se mainboard/ibase/mb899
	mainboard/kontron/kt690 mainboard/msi/ms7260 main...
Message-ID: <E1PPNBn-0005UF-40@ra.coresystems.de>

Author: uwe
Date: Sun Dec  5 23:36:14 2010
New Revision: 6140
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6140

Log:
W83627DHG/W83627EHG fixups for virtual LDNs.

W83627DHG:

 - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
   that don't have their "enable" bit in bit 0 of the 0x30 register).

 - Fix various I/O masks in the pnp_dev_info[] array as per
   datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.

W83627EHG:

 - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
   mostly implemented already, though).

 - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.

Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.

include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.

asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.

ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek at assembler.cz>

Modified:
   trunk/src/include/device/pnp.h
   trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
   trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/devicetree.cb
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/ibase/mb899/devicetree.cb
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/kontron/kt690/devicetree.cb
   trunk/src/mainboard/msi/ms7260/devicetree.cb
   trunk/src/mainboard/msi/ms9282/devicetree.cb
   trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb
   trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb
   trunk/src/superio/winbond/w83627dhg/superio.c
   trunk/src/superio/winbond/w83627dhg/w83627dhg.h
   trunk/src/superio/winbond/w83627ehg/superio.c
   trunk/src/superio/winbond/w83627ehg/w83627ehg.h

Modified: trunk/src/include/device/pnp.h
==============================================================================
--- trunk/src/include/device/pnp.h	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/include/device/pnp.h	Sun Dec  5 23:36:14 2010	(r6140)
@@ -31,7 +31,7 @@
 
 struct pnp_info {
 	struct device_operations *ops;
-	unsigned int function;
+	unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */
 	unsigned int flags;
 #define PNP_IO0  0x001
 #define PNP_IO1  0x002

Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -85,7 +85,7 @@
 								io 0x60 = 0x2f8
 								irq 0x70 = 3
 							end
-							device pnp 2e.5 on #  Keyboard
+							device pnp 2e.5 on #  PS/2 keyboard & mouse
 								io 0x60 = 0x60
 								io 0x62 = 0x64
 								irq 0x70 = 1

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -49,8 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
-#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
+#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -49,9 +49,9 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 off		# PS/2 keyboard (off)
+              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
               end
-              device pnp 2e.106 off		# Serial flash
+              device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
               device pnp 2e.007 off		# GPIO 1
@@ -65,15 +65,15 @@
               end
               device pnp 2e.307 off		# GPIO 6
               end
-              device pnp 2e.8 off		# WDTO_PLED
+              device pnp 2e.8 off		# WDTO#, PLED
               end
-              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              device pnp 2e.009 on		# GPIO 2
               end
               device pnp 2e.109 off		# GPIO 3
               end
               device pnp 2e.209 off		# GPIO 4
               end
-              device pnp 2e.309 on		# GPIO5
+              device pnp 2e.309 on		# GPIO 5
               end
               device pnp 2e.a off		# ACPI
               end

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -49,7 +49,7 @@
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/asus/a8v-e_se/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/a8v-e_se/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -49,9 +49,9 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 off		# PS/2 keyboard (off)
+              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
               end
-              device pnp 2e.106 off		# Serial flash
+              device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
               device pnp 2e.007 off		# GPIO 1
@@ -65,15 +65,15 @@
               end
               device pnp 2e.307 off		# GPIO 6
               end
-              device pnp 2e.8 off		# WDTO_PLED
+              device pnp 2e.8 off		# WDTO#, PLED
               end
-              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              device pnp 2e.009 on		# GPIO 2
               end
               device pnp 2e.109 off		# GPIO 3
               end
               device pnp 2e.209 off		# GPIO 4
               end
-              device pnp 2e.309 on		# GPIO5
+              device pnp 2e.309 on		# GPIO 5
               end
               device pnp 2e.a off		# ACPI
               end

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -49,7 +49,7 @@
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/ibase/mb899/devicetree.cb
==============================================================================
--- trunk/src/mainboard/ibase/mb899/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/ibase/mb899/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -63,29 +63,38 @@
                                                 irq 0x70 = 3
 						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
                                         end
-					device pnp 4e.5 on		# Keyboard+Mouse
+					device pnp 4e.5 on		# PS/2 keyboard & mouse
 						 io 0x60 = 0x60
 						 io 0x62 = 0x64
 						irq 0x70 = 1
 						irq 0x72 = 12
 						irq 0xf0 = 0x82		# HW accel A20.
 					end
-					device pnp 4e.7 on		# GPIO1, GAME, MIDI
-						 io 0x62 = 0x330
+					device pnp 4e.106 off end	# Serial flash interface (SFI)
+					device pnp 4e.007 off end	# GPIO 1
+					device pnp 4e.107 off end	# Game port
+					device pnp 4e.207 on		# MIDI
+						io 0x62 = 0x330
 						irq 0x70 = 9
 					end
-					device pnp 4e.8 on		# GPIO2
-						# all default
+					device pnp 4e.307 off end	# GPIO 6
+					device pnp 4e.8 off end		# WDTO#, PLED
+					device pnp 4e.009 on		# GPIO 2
+						# All default
 					end
-					device pnp 4e.9 on		# GPIO3/4
-						irq 0x30 = 0x03		# does this work?
+					device pnp 4e.109 on		# GPIO 3
 						irq 0xf0 = 0xfb		# set inputs/outputs
 						irq 0xf1 = 0x66
 					end
+					device pnp 4e.209 on		# GPIO 4
+					end
+					device pnp 4e.309 off		# GPIO 5
+					end
 					device pnp 4e.a on		# ACPI
+						# TODO: IRQ
 					end
 					device pnp 4e.b on		# HWM
-						 io 0x60 = 0x290
+						io 0x60 = 0x290
 						irq 0x70 = 0
 					end
 

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -38,6 +38,7 @@
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+#define DUMMY_DEV PNP_DEV(0x4e, 0)
 
 void enable_smbus(void);
 
@@ -79,7 +80,7 @@
 {
 	device_t dev;
 
-	dev=PNP_DEV(0x4e, W83627EHG_SP1);
+	dev = DUMMY_DEV;
 	pnp_enter_ext_func_mode(dev);
 
 	pnp_write_config(dev, 0x24, 0xc4); // PNPCSV

Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb
==============================================================================
--- trunk/src/mainboard/kontron/kt690/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/kontron/kt690/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -83,11 +83,17 @@
 							end
 							#device pnp 2e.6 off #  SPI
 							#end
-							device pnp 2e.7 off #  GPIO
+							device pnp 2e.307 off #  GPIO 1
 							end
 							device pnp 2e.8 on #  WDTO#, PLED
 							end
-							device pnp 2e.9 off #  GPIO
+							device pnp 2e.009 off #  GPIO2
+							end
+							device pnp 2e.109 off #  GPIO3
+							end
+							device pnp 2e.209 off #  GPIO4
+							end
+							device pnp 2e.309 off #  GPIO5
 							end
 							device pnp 2e.a off #  ACPI
 							end

Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms7260/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/msi/ms7260/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -28,28 +28,41 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 4e.5 on		# PS/2 keyboard
+              device pnp 4e.5 on		# PS/2 keyboard & mouse
                 io 0x60 = 0x60
                 io 0x62 = 0x64
                 irq 0x70 = 1			# PS/2 keyboard IRQ
                 irq 0x72 = 12			# PS/2 mouse IRQ
               end
-              device pnp 4e.6 off		# Serial flash interface
+              device pnp 4e.106 off		# Serial flash interface (SFI)
                 # io 0x62 = 0x100
               end
-              device pnp 4e.7 off		# GPIO1/6, game port, MIDI port
+              device pnp 4e.007 off		# GPIO 1
+              end
+              device pnp 4e.107 off		# Game port
                 # io 0x60 = 0x220		# Datasheet: 0x201
+              end
+              device pnp 4e.207 off		# MIDI
                 # io 0x62 = 0x300		# Datasheet: 0x330
                 # irq 0x70 = 9
               end
+              device pnp 4e.307 off		# GPIO 6
+              end
               device pnp 4e.8 off		# WDTO#, PLED
               end
-              device pnp 4e.9 off		# GPIO2/3/4/5, SUSLED
+              device pnp 4e.009 off		# GPIO 2
+              end
+              device pnp 4e.109 off		# GPIO 3
+              end
+              device pnp 4e.209 off		# GPIO 4
+              end
+              device pnp 4e.309 off		# GPIO 5
               end
               device pnp 4e.a off		# ACPI
               end
-              device pnp 4e.b on		# HWM (for lm-sensors)
+              device pnp 4e.b on		# Hardware monitor
                 io 0x60 = 0xa10
+                # TODO: IRQ?
               end
             end
           end

Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms9282/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/msi/ms9282/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -28,22 +28,35 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 on		# PS/2 keyboard
+              device pnp 2e.5 on		# PS/2 keyboard & mouse
                 io 0x60 = 0x60
                 io 0x62 = 0x64
                 irq 0x70 = 1
                 irq 0x72 = 12
               end
-              device pnp 2e.6 off		# Serial flash
+              device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
-              device pnp 2e.7 off		# Game port, MIDI, GPIO1
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 off		# Game port
                 io 0x60 = 0x220
+              end
+              device pnp 2e.207 off		# MIDI
                 io 0x62 = 0x300
                 irq 0x70 = 9
               end
-              device pnp 2e.8 off end		# WDTO PLED
-              device pnp 2e.9 off end		# GPIO2, GPIO3, GPIO4, GPIO5
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off end		# WDTO#, PLED
+              device pnp 2e.009 off		# GPIO 2
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 off		# GPIO 5
+              end
               device pnp 2e.a off end		# ACPI
               device pnp 2e.b on		# Hardware monitor
                 io 0x60 = 0x290

Modified: trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -51,34 +51,41 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 on		# PS/2 keyboard
+              device pnp 2e.5 on		# PS/2 keyboard & mouse
                 io 0x60 = 0x60
                 io 0x62 = 0x64
                 irq 0x70 = 1
                 irq 0x72 = 12
               end
-              device pnp 2e.6 off		# Serial flash
+              device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
-              device pnp 2e.7 off		# Game port, MIDI, GPIO1
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 on		# Game port
                 io 0x60 = 0x220
-                io 0x62 = 0x300
-                irq 0x70 = 9
               end
-              device pnp 2e.8 off end		# WDTO PLED
-              device pnp 2e.9 off end		# GPIO2, GPIO3, GPIO4, GPIO5
+              device pnp 2e.207 on		# MIDI
+                io 0x62 = 0x330
+                irq 0x70 = 0xa
+              end
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO#, PLED
+              end
+              device pnp 2e.009 off		# GPIO 2
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 off		# GPIO 5
+              end
               device pnp 2e.a off end		# ACPI
               device pnp 2e.b on		# Hardware monitor
                 io 0x60 = 0x290
                 irq 0x70 = 5
               end
-              device pnp 2e.106 off		# Serial flash
-                io 0x60 = 0x100
-              end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
-              end
             end
           end
           device pci 1.1 on			# SM 0

Modified: trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb	Sun Dec  5 23:36:14 2010	(r6140)
@@ -28,22 +28,36 @@
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 on		# PS/2 keyboard
+              device pnp 2e.5 on		# PS/2 keyboard & mouse
                 io 0x60 = 0x60
                 io 0x62 = 0x64
                 irq 0x70 = 1
                 irq 0x72 = 12
               end
-              device pnp 2e.6 off		# SFI
-                io 0x62 = 0x100
+              device pnp 2e.106 off		# Serial flash interface (SFI)
+                io 0x60 = 0x100
               end
-              device pnp 2e.7 off		# GPIO, Game port, MIDI
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 off		# Game port
                 io 0x60 = 0x220
+              end
+              device pnp 2e.207 off		# MIDI
                 io 0x62 = 0x300
                 irq 0x70 = 9
               end
-              device pnp 2e.8 off end		# WDTO PLED
-              device pnp 2e.9 off end		# GPIO SUSLED
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO#, PLED
+              end
+              device pnp 2e.009 off		# GPIO 2
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 off		# GPIO 5
+              end
               device pnp 2e.a off end		# ACPI
               device pnp 2e.b on		# Hardware monitor
                 io 0x60 = 0x290

Modified: trunk/src/superio/winbond/w83627dhg/superio.c
==============================================================================
--- trunk/src/superio/winbond/w83627dhg/superio.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/superio/winbond/w83627dhg/superio.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -94,18 +94,21 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
-	{ &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
-	{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
-	{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
-	{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, },
+	{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
 	/* the next line makes coreboot hang in pnp_enable_devices() */
-	/* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */
+	/* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */
 	{ &ops, W83627DHG_GPIO6, },
 	{ &ops, W83627DHG_WDTO_PLED, },
-	{ &ops, W83627DHG_GPIO2345, },
-	{ &ops, W83627DHG_ACPI, },
-	{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, },
+	{ &ops, W83627DHG_GPIO2, },
+	{ &ops, W83627DHG_GPIO3, },
+	{ &ops, W83627DHG_GPIO4, },
+	{ &ops, W83627DHG_GPIO5, },
+	{ &ops, W83627DHG_ACPI, PNP_IRQ0, },
+	{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
 	{ &ops, W83627DHG_PECI_SST, },
 };
 

Modified: trunk/src/superio/winbond/w83627dhg/w83627dhg.h
==============================================================================
--- trunk/src/superio/winbond/w83627dhg/w83627dhg.h	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/superio/winbond/w83627dhg/w83627dhg.h	Sun Dec  5 23:36:14 2010	(r6140)
@@ -25,13 +25,30 @@
 #define W83627DHG_PP               1   /* Parallel port */
 #define W83627DHG_SP1              2   /* Com1 */
 #define W83627DHG_SP2              3   /* Com2 */
-#define W83627DHG_KBC              5   /* PS/2 keyboard + mouse */
+#define W83627DHG_KBC              5   /* PS/2 keyboard & mouse */
 #define W83627DHG_SPI              6   /* Serial peripheral interface */
-#define W83627DHG_GPIO6            7   /* GPIO6 */
 #define W83627DHG_WDTO_PLED        8   /* WDTO#, PLED */
-#define W83627DHG_GPIO2345         9   /* GPIO2, GPIO3, GPIO4, GPIO5 */
 #define W83627DHG_ACPI            10   /* ACPI */
 #define W83627DHG_HWM             11   /* Hardware monitor */
 #define W83627DHG_PECI_SST        12   /* PECI, SST */
 
+/* The following are handled using "virtual LDNs" (hence the _V suffix). */
+#define W83627DHG_GPIO6_V          7   /* GPIO6 */
+#define W83627DHG_GPIO2345_V       9   /* GPIO2, GPIO3, GPIO4, GPIO5 */
+
+/*
+ * Virtual devices sharing the enables are encoded as follows:
+ *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
+ */
+
+/* GPIO6 has bit 3 as enable (instead of bit 0 as usual). */
+#define W83627DHG_GPIO6	((3 << 8) | W83627DHG_GPIO6_V)
+
+#define W83627DHG_GPIO2	((0 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO3	((1 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO4	((2 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO5	((3 << 8) | W83627DHG_GPIO2345_V)
+
+/* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
+
 #endif

Modified: trunk/src/superio/winbond/w83627ehg/superio.c
==============================================================================
--- trunk/src/superio/winbond/w83627ehg/superio.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/superio/winbond/w83627ehg/superio.c	Sun Dec  5 23:36:14 2010	(r6140)
@@ -178,17 +178,18 @@
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
-	{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+	{ &ops, W83627EHG_SFI,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, W83627EHG_WDTO_PLED, },
-	{ &ops, W83627EHG_ACPI, },
-	{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, W83627EHG_ACPI, PNP_IRQ0, },
+	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
+
 	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
-	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
+	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
 	{ &ops, W83627EHG_GPIO1, },
 	{ &ops, W83627EHG_GPIO2, },
 	{ &ops, W83627EHG_GPIO3, },

Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg.h
==============================================================================
--- trunk/src/superio/winbond/w83627ehg/w83627ehg.h	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/superio/winbond/w83627ehg/w83627ehg.h	Sun Dec  5 23:36:14 2010	(r6140)
@@ -27,27 +27,32 @@
 #define W83627EHG_SP1              2   /* Com1 */
 #define W83627EHG_SP2              3   /* Com2 */
 #define W83627EHG_KBC              5   /* PS/2 keyboard & mouse */
-#define W83627EHG_GPIO_GAME_MIDI   7   /* GPIO1, GPIO6, Game port, MIDI port */
-#define W83627EHG_WDTO_PLED        8   /* TODO */
-#define W83627EHG_GPIO_SUSLED      9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
+#define W83627EHG_WDTO_PLED        8   /* Watchdog timer timeout, power LED */
 #define W83627EHG_ACPI            10   /* ACPI */
 #define W83627EHG_HWM             11   /* Hardware monitor */
 
+/* The following are handled using "virtual LDNs" (hence the _V suffix). */
+#define W83627EHG_SFI_V            6   /* Serial flash interface (SFI) */
+#define W83627EHG_GPIO_GAME_MIDI_V 7   /* GPIO1, GPIO6, game port, MIDI */
+#define W83627EHG_GPIO_SUSLED_V    9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
+
 /*
  * Virtual devices sharing the enables are encoded as follows:
  *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
  */
 
-#define W83627EHG_SFI	((1 << 8) | 6)           /* Flash has bit1 as enable */
-#define W83627EHG_GPIO1	W83627EHG_GPIO_GAME_MIDI /* GPIO1: LDN 7, bit 0 */
-#define W83627EHG_GAME	((1 << 8) | 7)
-#define W83627EHG_MIDI	((2 << 8) | 7)
-#define W83627EHG_GPIO6	((3 << 8) | 7)
-
-#define W83627EHG_GPIO2	W83627EHG_GPIO_SUSLED    /* GPIO2: LDN 9, bit 0 */
-#define W83627EHG_GPIO3	((1 << 8) | 9)
-#define W83627EHG_GPIO4	((2 << 8) | 9)
-#define W83627EHG_GPIO5	((3 << 8) | 9)
+/* SFI has bit 1 as enable (instead of bit 0 as usual). */
+#define W83627EHG_SFI	((1 << 8) | W83627EHG_SFI_V)
+
+#define W83627EHG_GPIO1	((0 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_GAME	((1 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_MIDI	((2 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_GPIO6	((3 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+
+#define W83627EHG_GPIO2	((0 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO3	((1 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO4	((2 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO5	((3 << 8) | W83627EHG_GPIO_SUSLED_V)
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
 void w83627ehg_enable_dev(device_t dev, u16 iobase);



From uwe at hermann-uwe.de  Sun Dec  5 23:36:46 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Sun, 5 Dec 2010 23:36:46 +0100
Subject: [coreboot] [PATCH] W83627DHG/W83627EHG fixups for virtual LDNs
In-Reply-To: <4CFA1263.908@assembler.cz>
References: <20101119092103.GB21609@greenwood>
 <4CFA1263.908@assembler.cz>
Message-ID: <20101205223646.GM21636@greenwood>

On Sat, Dec 04, 2010 at 11:05:23AM +0100, Rudolf Marek wrote:
> Acked-by: Rudolf Marek <r.marek at assembler.cz>

Thanks, r6140.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Mon Dec  6 02:11:12 2010
From: svn at coreboot.org (repository service)
Date: Mon, 06 Dec 2010 02:11:12 +0100
Subject: [coreboot] [commit] r6141 - in trunk/src/mainboard/asus: . m4a78-em
	m4a785-m
Message-ID: <E1PPPbk-0003wa-R6@ra.coresystems.de>

Author: uwe
Date: Mon Dec  6 02:11:12 2010
New Revision: 6141
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6141

Log:
Add initial support for the ASUS M4A78-EM.

Signed-off-by: Juhana Helovuo <juhe at iki.fi>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Added:
   trunk/src/mainboard/asus/m4a78-em/
      - copied from r6139, trunk/src/mainboard/asus/m4a785-m/
Modified:
   trunk/src/mainboard/asus/Kconfig
   trunk/src/mainboard/asus/m4a78-em/Kconfig
   trunk/src/mainboard/asus/m4a78-em/devicetree.cb
   trunk/src/mainboard/asus/m4a78-em/irq_tables.c
   trunk/src/mainboard/asus/m4a78-em/mainboard.c
   trunk/src/mainboard/asus/m4a78-em/mptable.c
   trunk/src/mainboard/asus/m4a785-m/irq_tables.c
   trunk/src/mainboard/asus/m4a785-m/mainboard.c

Modified: trunk/src/mainboard/asus/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/Kconfig	Sun Dec  5 23:36:14 2010	(r6140)
+++ trunk/src/mainboard/asus/Kconfig	Mon Dec  6 02:11:12 2010	(r6141)
@@ -33,6 +33,8 @@
 	bool "M2V-MX SE"
 config BOARD_ASUS_M4A785M
 	bool "M4A785-M"
+config BOARD_ASUS_M4A78_EM
+	bool "M4A78-EM"
 config BOARD_ASUS_MEW_AM
 	bool "MEW-AM"
 config BOARD_ASUS_MEW_VM
@@ -58,6 +60,7 @@
 source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
 source "src/mainboard/asus/m4a785-m/Kconfig"
+source "src/mainboard/asus/m4a78-em/Kconfig"
 source "src/mainboard/asus/mew-am/Kconfig"
 source "src/mainboard/asus/mew-vm/Kconfig"
 source "src/mainboard/asus/p2b/Kconfig"

Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/m4a78-em/Kconfig	Mon Dec  6 02:11:12 2010	(r6141)
@@ -1,4 +1,4 @@
-if BOARD_ASUS_M4A785M
+if BOARD_ASUS_M4A78_EM
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -8,7 +8,6 @@
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
-	select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	select SUPERIO_ITE_IT8712F
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
@@ -31,7 +30,7 @@
 
 config MAINBOARD_DIR
 	string
-	default asus/m4a785-m
+	default asus/m4a78-em
 
 config APIC_ID_OFFSET
 	hex
@@ -39,7 +38,7 @@
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "M4A785-M"
+	default "M4A78-EM"
 
 config MAX_CPUS
 	int
@@ -67,7 +66,7 @@
 
 config IRQ_SLOT_COUNT
 	int
-	default 19
+	default 18
 
 config AMD_UCODE_PATCH_FILE
 	string
@@ -83,7 +82,7 @@
 
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
-	default 0x83a2
+	default 0x83f1
 
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 	hex

Modified: trunk/src/mainboard/asus/m4a78-em/devicetree.cb
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/devicetree.cb	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/m4a78-em/devicetree.cb	Mon Dec  6 02:11:12 2010	(r6141)
@@ -10,15 +10,15 @@
 				chip southbridge/amd/rs780
 					device pci 0.0 on end # HT  	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
-					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
-					device pci 3.0 off end # PCIE P2P bridge	0x960b
-					device pci 4.0 off end # PCIE P2P bridge 0x9604
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 on end # PCIE P2P bridge	0x960b
+					device pci 4.0 on end # PCIE P2P bridge 0x9604
 					device pci 5.0 off end # PCIE P2P bridge 0x9605
 					device pci 6.0 off end # PCIE P2P bridge 0x9606
 					device pci 7.0 off end # PCIE P2P bridge 0x9607
 					device pci 8.0 off end # NB/SB Link P2P bridge
-					device pci 9.0 off end #
-					device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet
+					device pci 9.0 on end #
+					device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet
 					register "gppsb_configuration" = "1"   # Configuration B
 					register "gpp_configuration" = "3"   # Configuration D default
 					register "port_enable" = "0x6fc"

Modified: trunk/src/mainboard/asus/m4a78-em/irq_tables.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/irq_tables.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/m4a78-em/irq_tables.c	Mon Dec  6 02:11:12 2010	(r6141)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 200x TODO <TODO at TODO>
+ * Copyright (C) 2010 Juhana Helovuo <juhe at iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * 19,		/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x14 << 3) | 0x3,	/* Interrupt router dev */
 	0,			/* IRQs devoted exclusively to PCI usage */
@@ -31,7 +31,7 @@
 	0x439d,			/* Device */
 	0,			/* Miniport */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x8,			/* Checksum (has to be set to some value that
+	0xca,			/* Checksum (has to be set to some value that
 				 * would give 0 after the sum of all bytes
 				 * for this structure (including checksum).
                                  */
@@ -53,9 +53,8 @@
 		{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
 		{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
 		{0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
-		{0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
+		{0x03, (0x06 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xd, 0x0},
+		{0x03, (0x07 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xe, 0x0},
 	}
 };
 

Modified: trunk/src/mainboard/asus/m4a78-em/mainboard.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/mainboard.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/m4a78-em/mainboard.c	Mon Dec  6 02:11:12 2010	(r6141)
@@ -27,19 +27,11 @@
 #include <southbridge/amd/sb700/sb700.h>
 #include "chip.h"
 
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS     0x0C /* Alert Response Address */
 
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 			       u8 val);
 
-#define ADT7461_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
-	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
 #define SMBUS_IO_BASE 0x6000
 
@@ -132,7 +124,7 @@
 /*
  * justify the dev3 is exist or not
  * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown it it will work at all for Asus M4A785-A
+ * It is completly unknown if it will work at all for this board.
  */
 u8 is_dev3_present(void)
 {
@@ -159,77 +151,14 @@
 	}
 }
 
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
-	u8 byte;
-	u16 word;
-	device_t sm_dev;
-
-	/* set ADT 7461 */
-	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
-	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
-	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
-	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */
-
-	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
-	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
-
-	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
-	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
-	/* sb700 settings for thermal config */
-	/* set SB700 GPIO 64 to GPIO with pull-up */
-	byte = pm2_ioread(0x42);
-	byte &= 0x3f;
-	pm2_iowrite(0x42, byte);
-
-	/* set GPIO 64 to input */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
-
-	/* set GPIO 64 internal pull-up */
-	byte = pm2_ioread(0xf0);
-	byte &= 0xee;
-	pm2_iowrite(0xf0, byte);
-
-	/* set Talert to be active low */
-	byte = pm_ioread(0x67);
-	byte &= ~(1 << 5);
-	pm_iowrite(0x67, byte);
-
-	/* set Talert to generate ACPI event */
-	byte = pm_ioread(0x3c);
-	byte &= 0xf3;
-	pm_iowrite(0x3c, byte);
-
-	/* THERMTRIP pin */
-	/* byte = pm_ioread(0x68);
-	 * byte |= 1 << 3;
-	 * pm_iowrite(0x68, byte);
-	 *
-	 * byte = pm_ioread(0x55);
-	 * byte |= 1 << 0;
-	 * pm_iowrite(0x55, byte);
-	 *
-	 * byte = pm_ioread(0x67);
-	 * byte &= ~( 1 << 6);
-	 * pm_iowrite(0x67, byte);
-	 */
-}
 
 /*************************************************
-* enable the dedicated function in m4a785m board.
+* enable the dedicated function in this board.
 * This function called early than rs780_enable.
 *************************************************/
-static void m4a785m_enable(device_t dev)
+static void m4a78em_enable(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
@@ -272,10 +201,10 @@
 
 	set_pcie_dereset();
 	/* get_ide_dma66(); */
-	set_thermal_config();
+	/* set_thermal_config(); */
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD M4A785M   Mainboard")
-	.enable_dev = m4a785m_enable,
+	CHIP_NAME("ASUS M4A78-EM Mainboard")
+	.enable_dev = m4a78em_enable,
 };

Modified: trunk/src/mainboard/asus/m4a78-em/mptable.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/mptable.c	Sat Dec  4 21:50:39 2010	(r6139)
+++ trunk/src/mainboard/asus/m4a78-em/mptable.c	Mon Dec  6 02:11:12 2010	(r6141)
@@ -40,7 +40,7 @@
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, "M4A785-M    ", LAPIC_ADDR);
+	mptable_init(mc, "M4A78-EM    ", LAPIC_ADDR);
 
 	smp_write_processors(mc);
 

Modified: trunk/src/mainboard/asus/m4a785-m/irq_tables.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/irq_tables.c	Sun Dec  5 23:36:14 2010	(r6140)
+++ trunk/src/mainboard/asus/m4a785-m/irq_tables.c	Mon Dec  6 02:11:12 2010	(r6141)
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 200x TODO <TODO at TODO>
+ * Copyright (C) 2010 Juhana Helovuo <juhe at iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * 19,		/* Max. number of devices on the bus */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
 	0x00,			/* Interrupt router bus */
 	(0x14 << 3) | 0x3,	/* Interrupt router dev */
 	0,			/* IRQs devoted exclusively to PCI usage */

Modified: trunk/src/mainboard/asus/m4a785-m/mainboard.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/mainboard.c	Sun Dec  5 23:36:14 2010	(r6140)
+++ trunk/src/mainboard/asus/m4a785-m/mainboard.c	Mon Dec  6 02:11:12 2010	(r6141)
@@ -132,7 +132,7 @@
 /*
  * justify the dev3 is exist or not
  * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown it it will work at all for Asus M4A785-A
+ * It is completly unknown it it will work at all for ASUS M4A785-M.
  */
 u8 is_dev3_present(void)
 {
@@ -224,12 +224,12 @@
 }
 
 /*************************************************
-* enable the dedicated function in m4a785m board.
+* enable the dedicated function in this board.
 * This function called early than rs780_enable.
 *************************************************/
 static void m4a785m_enable(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
 
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
@@ -276,6 +276,6 @@
 }
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD M4A785M   Mainboard")
+	CHIP_NAME("ASUS M4A785-M Mainboard")
 	.enable_dev = m4a785m_enable,
 };



From uwe at hermann-uwe.de  Mon Dec  6 02:19:55 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 6 Dec 2010 02:19:55 +0100
Subject: [coreboot] [PATCH] Support for Asus M4A78-EM mainboard
In-Reply-To: <4CFBA43A.6030306@iki.fi>
References: <4CFBA43A.6030306@iki.fi>
Message-ID: <20101206011954.GN21636@greenwood>

On Sun, Dec 05, 2010 at 04:39:54PM +0200, Juhana Helovuo wrote:
> Hello,
> 
> Here is a patch to get Asus M4A78-EM supported and booting Linux.
> 
> Files attached are:
> 
> * Boot log with the patches applied.
> 
> * Board-specific patch for SVN 6139
> 
> * Resend of Myles Watson's patch for AMD Northbridge, because the
> original did not work for me without manual editing. It is also
> needed for booting Linux.
> 
> 
> Before applying the patch, the board directory should be created with
> 
> % svn cp src/mainboard/asus/m4a785-m src/mainboard/asus/m4a78-em
> 
> 
> Signed-off-by: Juhana Helovuo <juhe at iki.fi>

Thanks, committed the board as r6141 with some small changes.

I'll leave the northbridge patch out for now, it should be
acked/reviewed in the original thread.

Please review the code carefully for more code/configs which are not
actually specific to this board but rather copy-paste remainders from
the other board dirs this is based on, and/or need to be fixed anyway,
e.g. all of the ACPI files, mptable.c, etc. etc.

 
Thanks, Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From svn at coreboot.org  Mon Dec  6 09:19:38 2010
From: svn at coreboot.org (repository service)
Date: Mon, 06 Dec 2010 09:19:38 +0100
Subject: [coreboot] [commit] r6142 - trunk/src/southbridge/amd/rs780
Message-ID: <E1PPWIM-0003Hm-FQ@ra.coresystems.de>

Author: zbao
Date: Mon Dec  6 09:19:38 2010
New Revision: 6142
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6142

Log:
Before lane reversal,
De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: QingPei Wang <wangqingpei at gmail.com>

Modified:
   trunk/src/southbridge/amd/rs780/rs780_gfx.c

Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c	Mon Dec  6 02:11:12 2010	(r6141)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c	Mon Dec  6 09:19:38 2010	(r6142)
@@ -1302,8 +1302,10 @@
 		if(is_dev3_present()){
 			/* step 1, lane reversal (only need if CMOS option is enabled) */
 			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
 			}
 			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
 			/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
@@ -1317,10 +1319,11 @@
 
 		}else{
 			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
 			}
 			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
-			printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
 
 			if((dev->path.pci.devfn >> 3) == 2)
 				single_port_configuration(nb_dev, dev);



From svn at coreboot.org  Mon Dec  6 16:00:01 2010
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 06 Dec 2010 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1PPcXp-0005Kj-To@ra.coresystems.de>

An HTML attachment was scrubbed...
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From towardsoss at gmail.com  Mon Dec  6 15:43:22 2010
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Mon, 06 Dec 2010 16:43:22 +0200
Subject: [coreboot] Buying a new mainboard. Which vendors support
	coreboot?
Message-ID: <1291646602.12689.17.camel@gnewsense>

Hi again,.

Jonathan wrote:
> What makes you think the open source ATI drivers aren't
> any good?
I'm not saying they are not good. If I didn't have an appreciation for
free libre or open source software I would have another idea of what
'good' means for me. What bothers me(although I'm not sure if you
understand why) though is some graphics microcode that AMD or ATI
doesn't want to release, possibly because it will spoil some Digital
Rights Management(DRM) technology that they have. Maybe I am mistaken
and they have released some of the "microcode" for some of their
integrated graphics cards?(if you know please tell) I don't know if you
consider "secret microcode" an issue. Also I just read about that this
"microcode" has not been released and I found the reference on an
AMD/ATI forum.
I'm not 100% that Intel has released the "microcode" for their G43
chipset.
So you can supply arguments(if you wish to help me with this) that
microcode isn't an important issue or find a reference that Intel
doesn't release their G43 graphics "microcode" either.

> AFAICT they're doing pretty well these days.
Any specific card? If yes, compare it to integrated Intel GMA
G43("X4500")

Regards,
Niklas
-- 

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From svens-coreboot at stackframe.org  Mon Dec  6 17:04:25 2010
From: svens-coreboot at stackframe.org (Sven Schnelle)
Date: Mon, 06 Dec 2010 17:04:25 +0100
Subject: [coreboot] FLASHROM: Add support for M25P16.RES
Message-ID: <4CFD0989.2000607@stackframe.org>

i've tried using flashrom for reading the SPI Flash of my Thinkpad X60s.
It seems like it is using the (yet) unsupported M25P16.RES.
I've added the few lines required to get it working, and at least
reading the Flash works. Haven't tried writing the Flash (yes, i know
about the risk regarding EC and friends) ;-)

Signed-off-by: Sven Schnelle <svens at stackframe.org>

Index: flashchips.c
===================================================================
--- flashchips.c	(revision 1246)
+++ flashchips.c	(working copy)
@@ -6188,9 +6188,33 @@
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 	},
-
 	{
 		.vendor		= "ST",
+		.name		= "M25P16.RES",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= 0, /* Unused */
+		.model_id	= ST_M25P16_RES,
+		.total_size	= 2048,
+		.page_size	= 256,
+		.tested		= TEST_OK_PR,
+		.probe		= probe_spi_res1,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 32} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {2 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+	{
+		.vendor		= "ST",
 		.name		= "M25P32",
 		.bustype	= CHIP_BUSTYPE_SPI,
 		.manufacture_id	= ST_ID,
Index: flashchips.h
===================================================================
--- flashchips.h	(revision 1246)
+++ flashchips.h	(working copy)
@@ -528,6 +528,7 @@
 #define ST_M25P40_RES		0x12
 #define ST_M25P80		0x2014
 #define ST_M25P16		0x2015
+#define ST_M25P16_RES		0x14
 #define ST_M25P32		0x2016
 #define ST_M25P64		0x2017
 #define ST_M25P128		0x2018




From marcj303 at gmail.com  Mon Dec  6 17:59:36 2010
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 6 Dec 2010 09:59:36 -0700
Subject: [coreboot] [RFC] simplify names
In-Reply-To: <4CFAC17B.3030702@georgi-clan.de>
References: <4CFA9DC8.7010908@coresystems.de> <4CFAC17B.3030702@georgi-clan.de>
Message-ID: <AANLkTi=mcK8+VQFFPNM7nTBr6fvZX5mCUei3=LN85y==@mail.gmail.com>

On Sat, Dec 4, 2010 at 3:32 PM, Patrick Georgi <patrick at georgi-clan.de> wrote:
> Am 04.12.2010 21:00, schrieb Stefan Reinauer:
>> Since Kconfig (actually since shortly before we switched to Kconfig) we
>> don't suffer from that problem anymore. So we could drop the sb700_
>> prefix from all those filenames (or, the <componentname>_ prefix in general)
>>
>> - makes it easier to fork off a new chipset
>> - makes it easier to diff against other chipsets
>> - storing redundant information in filenames seems wrong
>>
>> Signed-off-by: <stepan at coresystems.de>
>> I'm not going to post a patch, as it can not properly reflect the file
>> renames anyways.
>>
>> What do you think?
> I really like that!
>
> Once abuild-tested:
> Acked-by: Patrick Georgi <patrick at georgi-clan.de>
>

Sounds good to me.

Marc



-- 
http://se-eng.com



From peter at stuge.se  Mon Dec  6 18:36:45 2010
From: peter at stuge.se (Peter Stuge)
Date: Mon, 6 Dec 2010 18:36:45 +0100
Subject: [coreboot] [RFC] simplify names
In-Reply-To: <4CFA9DC8.7010908@coresystems.de>
References: <4CFA9DC8.7010908@coresystems.de>
Message-ID: <20101206173645.30866.qmail@stuge.se>

Stefan Reinauer wrote:
> The sb700_ prefix was introduced in the early v2 tree many years ago
> because our old build system "newconfig" could not handle two files with
> the same name in different paths like /path/to/usb.c and
> /another/path/to/usb.c correctly. Only one of the files would end up
> being compiled into the final image.
> 
> Since Kconfig (actually since shortly before we switched to Kconfig) we
> don't suffer from that problem anymore. So we could drop the sb700_
> prefix from all those filenames (or, the <componentname>_ prefix in general)
> 
> - makes it easier to fork off a new chipset
> - makes it easier to diff against other chipsets
> - storing redundant information in filenames seems wrong
> 
> Signed-off-by: <stepan at coresystems.de>

Acked-by: Peter Stuge <peter at stuge.se>



From svn at coreboot.org  Mon Dec  6 19:17:02 2010
From: svn at coreboot.org (repository service)
Date: Mon, 06 Dec 2010 19:17:02 +0100
Subject: [coreboot] [commit] r6143 - in trunk/src/mainboard: msi/ms6178
	supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10
	supermicro/h8qme_fam10 supermicro/x6dai_g supermicro/x6dhe_g
	supermicro/x6dhr_ig supermi...
Message-ID: <E1PPfcU-00084g-1V@ra.coresystems.de>

Author: uwe
Date: Mon Dec  6 19:17:01 2010
New Revision: 6143
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6143

Log:
Winbond W83627HF: Use existing functions instead of open-coding.

Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of 
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/msi/ms6178/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/supermicro/x6dai_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/mainboard/via/epia-n/romstage.c

Modified: trunk/src/mainboard/msi/ms6178/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6178/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/msi/ms6178/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -33,18 +33,15 @@
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 void enable_smbus(void);
 int smbus_read_byte(u8 device, u8 address);
 
 void main(unsigned long bist)
 {
-	/* FIXME */
-	outb(0x87, 0x2e);
-	outb(0x87, 0x2e);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
+	w83627hf_set_clksel_48(DUMMY_DEV);
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	outb(0x87, 0xaa);
 
 	uart_init();
 	console_init();

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -48,6 +48,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
@@ -193,10 +194,8 @@
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	uart_init();
 	console_init();

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -51,6 +51,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -122,10 +123,8 @@
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
-        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- 	w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+ 	w83627hf_set_clksel_48(DUMMY_DEV);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
         uart_init();
         console_init();

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -50,6 +50,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -125,10 +126,8 @@
 
 	post_code(0x32);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	uart_init();
 	console_init();

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -50,6 +50,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -176,10 +177,8 @@
 
   post_code(0x32);
 
-	pnp_enter_ext_func_mode(SERIAL_DEV);
-	pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- 	w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	pnp_exit_ext_func_mode(SERIAL_DEV);
+ 	w83627hf_set_clksel_48(DUMMY_DEV);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	uart_init();
 	console_init();

Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -16,13 +16,14 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
 	DEVPRES_D1F0 | \
@@ -63,11 +64,8 @@
 			skip_romstage();
 	}
 
-	/* Setup the console */
-	outb(0x87,0x2e);
-	outb(0x87,0x2e);
-	pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -17,13 +17,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
 	DEVPRES_D1F0 | \
@@ -60,11 +61,8 @@
 			skip_romstage();
 	}
 
-	/* Setup the console */
-	outb(0x87,0x2e);
-	outb(0x87,0x2e);
-	pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -15,13 +15,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhr_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
 	DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@
 			skip_romstage();
 	}
 
-	/* Setup the console */
-	outb(0x87,0x2e);
-	outb(0x87,0x2e);
-	pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -15,13 +15,14 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "x6dhr2_fixups.c"
-#include "superio/winbond/w83627hf/w83627hf_early_init.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 #define DEVPRES_CONFIG  ( \
 	DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@
 			skip_romstage();
 	}
 
-	/* Setup the console */
-	outb(0x87,0x2e);
-	outb(0x87,0x2e);
-	pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-	w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
 

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -46,6 +46,7 @@
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 /*
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@@ -384,7 +385,7 @@
 	 */
 	pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
 	/* EmbedComInit(); */
-	w83697hf_set_clksel_48(SERIAL_DEV);
+	w83697hf_set_clksel_48(DUMMY_DEV);
 	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	/* enable_vx800_serial(); */

Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c	Mon Dec  6 09:19:38 2010	(r6142)
+++ trunk/src/mainboard/via/epia-n/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
@@ -38,6 +38,7 @@
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 static const struct mem_controller ctrl = {
 	.d0f0 = 0x0000,
@@ -109,7 +110,7 @@
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	w83697hf_set_clksel_48(SERIAL_DEV);
+	w83697hf_set_clksel_48(DUMMY_DEV);
 	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();



From svn at coreboot.org  Mon Dec  6 19:20:49 2010
From: svn at coreboot.org (repository service)
Date: Mon, 06 Dec 2010 19:20:49 +0100
Subject: [coreboot] [commit] r6144 - in trunk/src/mainboard/supermicro:
	x6dhe_g x6dhe_g2 x6dhr_ig x6dhr_ig2
Message-ID: <E1PPfg9-0006DJ-Fh@ra.coresystems.de>

Author: uwe
Date: Mon Dec  6 19:20:48 2010
New Revision: 6144
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6144

Log:
Get rid of some useless/empty *_fixups.c files.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Deleted:
   trunk/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c
   trunk/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c
   trunk/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c
Modified:
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Mon Dec  6 19:20:48 2010	(r6144)
@@ -16,7 +16,6 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "x6dhe_g_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
@@ -35,6 +34,10 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+static void mch_reset(void) {}
+static void mainboard_set_e7520_pll(unsigned bits) {}
+static void mainboard_set_e7520_leds(void) {}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Mon Dec  6 19:20:48 2010	(r6144)
@@ -14,7 +14,6 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "x6dhe_g2_fixups.c"
 #include "superio/nsc/pc87427/pc87427_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
@@ -32,6 +31,10 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+static void mch_reset(void) {}
+static void mainboard_set_e7520_pll(unsigned bits) {}
+static void mainboard_set_e7520_leds(void) {}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Mon Dec  6 19:20:48 2010	(r6144)
@@ -14,7 +14,6 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "x6dhr_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
@@ -34,6 +33,10 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+static void mch_reset(void) {}
+static void mainboard_set_e7520_pll(unsigned bits) {}
+static void mainboard_set_e7520_leds(void) {}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Mon Dec  6 19:17:01 2010	(r6143)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Mon Dec  6 19:20:48 2010	(r6144)
@@ -14,7 +14,6 @@
 #include "debug.c"
 #include "watchdog.c"
 #include "reset.c"
-#include "x6dhr2_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
@@ -34,6 +33,10 @@
 	0 )
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
+static void mch_reset(void) {}
+static void mainboard_set_e7520_pll(unsigned bits) {}
+static void mainboard_set_e7520_leds(void) {}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);



From mylesgw at gmail.com  Mon Dec  6 19:41:21 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 6 Dec 2010 11:41:21 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <4CFB7094.4030608@iki.fi>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<4CFA768B.5010008@iki.fi> <B2874E69A60E4811A9FAD70CBB35493F@chimp>
	<4CFB7094.4030608@iki.fi>
Message-ID: <BA34F2C0A97F442E933DC1A15B4B7F35@chimp>

> And you are right, the PCI resources do not show up. The resources of
> the PCI root device include
> 
> PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit
> dff8
> PCI: 00:18.0 resource base d0000000 size 4400000 align 26 gran 20 limit
> dfff0
> 
> 
> These resources do not show up in the coreboot table either:
> 
> coreboot memory table:
>   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
>   1. 0000000000001000-000000000009ffff: RAM
>   2. 00000000000c0000-000000002ffeffff: RAM
>   3. 000000002fff0000-000000002fffffff: CONFIGURATION TABLES
>   4. 0000000030000000-000000003fffffff: RESERVED
>   5. 00000000e0000000-00000000efffffff: RESERVED
> Wrote coreboot table at: 2fffe000 - 2fffe1bc  checksum ba50
> 
> 
> But does it really matter? There is now physical RAM only up to
> 40000000. Or is it going to be a problem if there is more than 3 GB RAM?
I'm worried that Linux will put something in the wrong place if it doesn't
know what areas are used.  It may not matter in practice, but as long as
things are broken for you it's probably worth checking into.

Thanks,
Myles




From namedylan at gmail.com  Mon Dec  6 21:19:38 2010
From: namedylan at gmail.com (Fengwei Zhang)
Date: Mon, 06 Dec 2010 15:19:38 -0500
Subject: [coreboot] Buying CPU and memory for board M2V-MX_SE with S3 support
Message-ID: <4CFD455A.1080503@gmail.com>

Hi all,

I am going to buy CPU and memory for board M2V-MX_SE with S3 support. 
According to Ruldof, the CPU with core stepping BH-G1, DH-G2 and BH-G2 
might support S3.

I am considering to buy AMD Sempron 64 LE-1300, and its core stepping is 
DH-G2. How do you think? Following is the link of this CPU
http://www.cpu-world.com/CPUs/K8/AMD-Sempron%2064%20LE-1300%20-%20SDH1300IAA4DP%20%28SDH1300DPBOX%29.html

Another question is about the RAM. What is size of RAM that you would 
suggest to use? The goal is to make sure S3 would work.

I would appreciate any precious suggestions and comments.

Best,
Fengwei



From svn at coreboot.org  Mon Dec  6 21:27:12 2010
From: svn at coreboot.org (repository service)
Date: Mon, 06 Dec 2010 21:27:12 +0100
Subject: [coreboot] [commit] r6145 - in trunk/src/mainboard:
	amd/mahogany_fam10 amd/tilapia_fam10 asus/m4a78-em
	asus/m4a785-m gigabyte/ma785gmt gigabyte/ma78gm
	iei/kino-780am2-fam10 jetway/pa78vm5
Message-ID: <E1PPheS-0007SJ-LT@ra.coresystems.de>

Author: uwe
Date: Mon Dec  6 21:27:12 2010
New Revision: 6145
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6145

Log:
Drop unused/obsolete CONFIG_COMPRESS from a few board Kconfigs.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/tilapia_fam10/Kconfig
   trunk/src/mainboard/asus/m4a78-em/Kconfig
   trunk/src/mainboard/asus/m4a785-m/Kconfig
   trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
   trunk/src/mainboard/gigabyte/ma78gm/Kconfig
   trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
   trunk/src/mainboard/jetway/pa78vm5/Kconfig

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,8 +94,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif # BOARD_AMD_MAHOGANY_FAM10

Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,8 +94,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif # BOARD_AMD_TILAPIA_FAM10

Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/asus/m4a78-em/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -92,8 +92,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif

Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/asus/m4a785-m/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -93,8 +93,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif

Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,8 +94,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif # BOARD_GIGABYTE_GA785GMT

Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,8 +94,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif # BOARD_GIGABYTE_MA78GM

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,10 +94,6 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 config FALLBACK_VGA_BIOS_ID
 	string
 	default "1002,9615"

Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/Kconfig	Mon Dec  6 19:20:48 2010	(r6144)
+++ trunk/src/mainboard/jetway/pa78vm5/Kconfig	Mon Dec  6 21:27:12 2010	(r6145)
@@ -94,8 +94,4 @@
 	hex
 	default 0x200000
 
-config COMPRESS
-	hex
-	default 0
-
 endif # BOARD_JETWAY_PA78VM5



From uwe at hermann-uwe.de  Mon Dec  6 23:14:01 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 6 Dec 2010 23:14:01 +0100
Subject: [coreboot] [RFC] simplify names
In-Reply-To: <4CFA9DC8.7010908@coresystems.de>
References: <4CFA9DC8.7010908@coresystems.de>
Message-ID: <20101206221400.GO21636@greenwood>

On Sat, Dec 04, 2010 at 12:00:08PM -0800, Stefan Reinauer wrote:
> The sb700_ prefix was introduced in the early v2 tree many years ago
> because our old build system "newconfig" could not handle two files with
> the same name in different paths like /path/to/usb.c and
> /another/path/to/usb.c correctly. Only one of the files would end up
> being compiled into the final image.
> 
> Since Kconfig (actually since shortly before we switched to Kconfig) we
> don't suffer from that problem anymore. So we could drop the sb700_
> prefix from all those filenames (or, the <componentname>_ prefix in general)

Yup, I like it. I'd do it in small steps though (one SB/NB/superio at a
time) otherwise it's probably too much tedious work and will break lots of
pending patches etc.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Mon Dec  6 23:16:32 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 6 Dec 2010 23:16:32 +0100
Subject: [coreboot] [PATCH] Deduplicate various ACPI .asl files
In-Reply-To: <20101127091801.GU31364@yumi.tdiedrich.de>
References: <20101126222818.GY21636@greenwood>
	<4CF07404.4090803@coresystems.de>
	<20101127091801.GU31364@yumi.tdiedrich.de>
Message-ID: <20101206221632.GP21636@greenwood>

On Sat, Nov 27, 2010 at 10:18:01AM +0100, Tobias Diedrich wrote:
> > Since it's amd specific (in a sense that it's not much benefit and only
> > used on amd based boards), we should move it to cpu/amd/acpi or
> > cpu/amd/amdk8/acpi?
> 
> It doesn't look amd-specific though.
> At the very least the STA_* definitions in statdef.asl look useful.
> globutil.asl and debug.asl are not specific to amd at all.
> And the debugging primitives are probably quite useful for more
> complicated acpi code.

Yup, those files are not AMD-specific and are potentially reusable by
other chipsets, keeping them outside of amd/ dirs makes sense IMHO.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org



From uwe at hermann-uwe.de  Mon Dec  6 23:45:52 2010
From: uwe at hermann-uwe.de (Uwe Hermann)
Date: Mon, 6 Dec 2010 23:45:52 +0100
Subject: [coreboot] [PATCH] Move "select CACHE_AS_RAM" lines from boards
 into CPU socket
Message-ID: <20101206224552.GQ21636@greenwood>

See patch.


Uwe.
-- 
http://hermann-uwe.de     | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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From c-d.hailfinger.devel.2006 at gmx.net  Tue Dec  7 02:46:59 2010
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 07 Dec 2010 02:46:59 +0100
Subject: [coreboot] FLASHROM: Add support for M25P16.RES
In-Reply-To: <4CFD0989.2000607@stackframe.org>
References: <4CFD0989.2000607@stackframe.org>
Message-ID: <4CFD9213.4070901@gmx.net>

Hi Sven,
[adding flashrom at flashrom.org to CC]

thanks for your patch.

Please note that a huge number of incompatible chips share the same RES
ID. A quick glance at my datasheet collection (I stopped after 5
minutes) resulted in the following matches:
AMIC A25L016, A25L16P
Eon EN25P16
ESMT F25L016A
Generalplus GPR25L161B
Macronix MX25L1605*, MX25L1635*
PMC Pm25LV016B
Spansion S25FL016A
ST M25P16
Winbond W25Q16*

Are you 100% sure you have a ST M25P16?

Regards,
Carl-Daniel

Your mail follows unqoted so flashrom patchwork will pick it up.

On 06.12.2010 17:04, Sven Schnelle wrote:

i've tried using flashrom for reading the SPI Flash of my Thinkpad X60s.
It seems like it is using the (yet) unsupported M25P16.RES.
I've added the few lines required to get it working, and at least
reading the Flash works. Haven't tried writing the Flash (yes, i know
about the risk regarding EC and friends) ;-)

Signed-off-by: Sven Schnelle <svens at stackframe.org>

Index: flashchips.c
===================================================================
--- flashchips.c	(revision 1246)
+++ flashchips.c	(working copy)
@@ -6188,9 +6188,33 @@
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 	},
-
 	{
 		.vendor		= "ST",
+		.name		= "M25P16.RES",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= 0, /* Unused */
+		.model_id	= ST_M25P16_RES,
+		.total_size	= 2048,
+		.page_size	= 256,
+		.tested		= TEST_OK_PR,
+		.probe		= probe_spi_res1,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 32} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {2 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},
+	{
+		.vendor		= "ST",
 		.name		= "M25P32",
 		.bustype	= CHIP_BUSTYPE_SPI,
 		.manufacture_id	= ST_ID,
Index: flashchips.h
===================================================================
--- flashchips.h	(revision 1246)
+++ flashchips.h	(working copy)
@@ -528,6 +528,7 @@
 #define ST_M25P40_RES		0x12
 #define ST_M25P80		0x2014
 #define ST_M25P16		0x2015
+#define ST_M25P16_RES		0x14
 #define ST_M25P32		0x2016
 #define ST_M25P64		0x2017
 #define ST_M25P128		0x2018







From mylesgw at gmail.com  Tue Dec  7 05:31:11 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Mon, 6 Dec 2010 21:31:11 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <BA34F2C0A97F442E933DC1A15B4B7F35@chimp>
References: <4CF2B0F3.8030106@iki.fi>
	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
	<4CF7C0DE.7090406@iki.fi> <3D745430C93A402688CDA9A631DD0114@m3a78>
	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<4CFA768B.5010008@iki.fi> <B2874E69A60E4811A9FAD70CBB35493F@chimp>
	<4CFB7094.4030608@iki.fi> <BA34F2C0A97F442E933DC1A15B4B7F35@chimp>
Message-ID: <AANLkTin=G9Ek8CvxN_5PM-=7e2b8fuQj+f12AM-QO4WP@mail.gmail.com>

On Mon, Dec 6, 2010 at 11:41 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> And you are right, the PCI resources do not show up. The resources of
>> the PCI root device include
>>
>> PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit
>> dff8
>> PCI: 00:18.0 resource base d0000000 size 4400000 align 26 gran 20 limit
>> dfff0
>>
>>
>> These resources do not show up in the coreboot table either:
>>
>> coreboot memory table:
>> ? 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
>> ? 1. 0000000000001000-000000000009ffff: RAM
>> ? 2. 00000000000c0000-000000002ffeffff: RAM
>> ? 3. 000000002fff0000-000000002fffffff: CONFIGURATION TABLES
>> ? 4. 0000000030000000-000000003fffffff: RESERVED
>> ? 5. 00000000e0000000-00000000efffffff: RESERVED
>> Wrote coreboot table at: 2fffe000 - 2fffe1bc ?checksum ba50
>>
>>
>> But does it really matter? There is now physical RAM only up to
>> 40000000. Or is it going to be a problem if there is more than 3 GB RAM?
> I'm worried that Linux will put something in the wrong place if it doesn't
> know what areas are used. ?It may not matter in practice, but as long as
> things are broken for you it's probably worth checking into.
Never mind.  I don't have any reserved areas in my tables.  I was
confusing myself.

So the only problem that you have now is incorrectly routed
interrupts?  Or is there something more?

Thanks,
Myles



From svn at coreboot.org  Tue Dec  7 07:27:45 2010
From: svn at coreboot.org (repository service)
Date: Tue, 07 Dec 2010 07:27:45 +0100
Subject: [coreboot] [commit] r6146 - in trunk/src/mainboard:
	amd/mahogany_fam10 amd/serengeti_cheetah
	amd/serengeti_cheetah_fam10 amd/tilapia_fam10 asus/m4a78-em
	asus/m4a785-m gigabyte/ma785gmt gigabyte/ma78gm iei/kin...
Message-ID: <E1PPr1d-0007is-D0@ra.coresystems.de>

Author: zbao
Date: Tue Dec  7 07:27:44 2010
New Revision: 6146
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6146

Log:
Trivial. Fix typo.
sh> find -name "acpi_tables.c" | xargs sed -i "s/FDAT/FADT/g"

Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Acked-by: Zheng Bao <zheng.bao at amd.com>

Modified:
   trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
   trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c
   trunk/src/mainboard/asus/m4a78-em/acpi_tables.c
   trunk/src/mainboard/asus/m4a785-m/acpi_tables.c
   trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c
   trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c
   trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c
   trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c
   trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c

Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -235,7 +235,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -282,7 +282,7 @@
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 
-	/* FDAT */
+	/* FADT */
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -305,7 +305,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -235,7 +235,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/asus/m4a78-em/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/asus/m4a78-em/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -234,7 +234,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/asus/m4a785-m/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/asus/m4a785-m/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -234,7 +234,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -233,7 +233,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -233,7 +233,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -235,7 +235,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;

Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -292,7 +292,7 @@
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
-	/* FDAT */
+	/* FADT */
 	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);

Modified: trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c	Mon Dec  6 21:27:12 2010	(r6145)
+++ trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c	Tue Dec  7 07:27:44 2010	(r6146)
@@ -234,7 +234,7 @@
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	  = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;



From juhe at iki.fi  Tue Dec  7 09:55:52 2010
From: juhe at iki.fi (Juhana Helovuo)
Date: Tue, 07 Dec 2010 10:55:52 +0200
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTin=G9Ek8CvxN_5PM-=7e2b8fuQj+f12AM-QO4WP@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi>	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>	<4CF7A783.7010006@iki.fi>	<3624A23C43C24F4C806AC7D5A5140088@m3a78>	<4CF7C0DE.7090406@iki.fi>	<3D745430C93A402688CDA9A631DD0114@m3a78>	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>	<4CFA768B.5010008@iki.fi>	<B2874E69A60E4811A9FAD70CBB35493F@chimp>	<4CFB7094.4030608@iki.fi>	<BA34F2C0A97F442E933DC1A15B4B7F35@chimp>
	<AANLkTin=G9Ek8CvxN_5PM-=7e2b8fuQj+f12AM-QO4WP@mail.gmail.com>
Message-ID: <4CFDF698.8070601@iki.fi>

7.12.2010 6:31, Myles Watson kirjoitti:
>
> So the only problem that you have now is incorrectly routed
> interrupts?  Or is there something more?
>

Hello,

Now I have interrupts working for at least SATA, IDE, USB, and Ethernet. 
Audio is still untested.

The next thing I am missing is to have the mmconf patch you sent to this 
list on 2nd December commited to SVN. That should create a trunk 
revision, which is usable on this board without any source patching.


Best regards,
Juhana Helovuo



From patrick at georgi-clan.de  Tue Dec  7 16:35:15 2010
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Tue, 07 Dec 2010 16:35:15 +0100
Subject: [coreboot] [PATCH] Move "select CACHE_AS_RAM" lines from boards
 into CPU socket
In-Reply-To: <20101206224552.GQ21636@greenwood>
References: <20101206224552.GQ21636@greenwood>
Message-ID: <4CFE5433.4080808@georgi-clan.de>

Am 06.12.2010 23:45, schrieb Uwe Hermann:
> See patch.
src/cpu/Kconfig defines CACHE_AS_RAM to "!ROMCC", so I think these can
be dropped completely. Right?

We basically assume it's CAR unless romcc is used.


Patrick



From scott at notabs.org  Tue Dec  7 16:44:34 2010
From: scott at notabs.org (Scott Duplichan)
Date: Tue, 7 Dec 2010 09:44:34 -0600
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
References: <4CF2B0F3.8030106@iki.fi><AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com><4CF7A783.7010006@iki.fi>
	<3624A23C43C24F4C806AC7D5A5140088@m3a78><4CF7C0DE.7090406@iki.fi>
	<3D745430C93A402688CDA9A631DD0114@m3a78><AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
Message-ID: <E20C9CC2E19341CA92FEFA54730B1638@m3a78>

On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>> "Why does the current code for handling fixed resources allow the mmconf
>> space to get allocated to a PCI device? Function avoid_fixed_resources
>> calls function constrain_resources, which recursively searches the
>> device tree for fixed io and memory resources. The ioapic fixed memory
>> address is found and avoided during the recursive search because this
>> southbridge device is below the level where the search starts. On the
>> other hand, the mmconf fixed resource is added from the northbridge code,
>> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
>> for two reasons. One is that it is not at or below 'pci_domain 0' in the
>> device tree. Another reason is that its type is APIC_CLUSTER and not
>> PCI_DOMAIN."
> I don't see any reason not to move that resource into the northbridge
> to avoid that issue. ?It's a simple fix. ?Is there a good reason for
> having the MMCONF BAR in the APIC cluster?
This is what I was thinking.  Build tested only.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles


Thanks for this patch Myles.
Acked-by: Scott Duplichan <scott at notabs.org>

Thanks,
Scott




From svens at stackframe.org  Mon Dec  6 15:43:06 2010
From: svens at stackframe.org (Sven Schnelle)
Date: Mon, 06 Dec 2010 15:43:06 +0100
Subject: [coreboot] FLASHROM: Add support for M25P80.RES
Message-ID: <4CFCF67A.7020002@stackframe.org>

Hi List,

i've tried using flashrom for reading the SPI Flash of my Thinkpad X60s.
It seems like it is using the (yet) unsupported M25P80.RES.
I've added the few lines required to get it working, and at least
reading the NVM works. Haven't tried writing the Flash (yes, i know
about the risk regarding EC and friends) ;-)

/sven

Signed-off-by: Sven Schnelle <svens at stackframe.org>

Index: flashchips.c
===================================================================
--- flashchips.c	(revision 1246)
+++ flashchips.c	(working copy)
@@ -6162,6 +6162,31 @@
 		.write		= spi_chip_write_256,
 		.read		= spi_chip_read,
 	},
+	{
+		.vendor		= "ST",
+		.name		= "M25P80.RES",
+		.bustype	= CHIP_BUSTYPE_SPI,
+		.manufacture_id	= 0, /* Not used */
+		.model_id	= ST_M25P80_RES,
+		.total_size	= 1024,
+		.page_size	= 256,
+		.tested		= TEST_OK_PR,
+		.probe		= probe_spi_res1,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 16} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { {1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+	},

 	{
 		.vendor		= "ST",
Index: flashchips.h
===================================================================
--- flashchips.h	(revision 1246)
+++ flashchips.h	(working copy)
@@ -527,6 +527,7 @@
 #define ST_M25P40		0x2013
 #define ST_M25P40_RES		0x12
 #define ST_M25P80		0x2014
+#define ST_M25P80_RES           0x14
 #define ST_M25P16		0x2015
 #define ST_M25P32		0x2016
 #define ST_M25P64		0x2017



From svens at stackframe.org  Tue Dec  7 09:50:29 2010
From: svens at stackframe.org (Sven Schnelle)
Date: Tue, 07 Dec 2010 09:50:29 +0100
Subject: [coreboot] FLASHROM: Add support for M25P16.RES
In-Reply-To: <4CFD9213.4070901@gmx.net>
References: <4CFD0989.2000607@stackframe.org> <4CFD9213.4070901@gmx.net>
Message-ID: <4CFDF555.3030905@stackframe.org>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi Carl-Daniel,

On 12/07/2010 02:46 AM, Carl-Daniel Hailfinger wrote:

> Please note that a huge number of incompatible chips share the same RES
> ID. A quick glance at my datasheet collection (I stopped after 5
> minutes) resulted in the following matches:
> AMIC A25L016, A25L16P
> Eon EN25P16
> ESMT F25L016A
> Generalplus GPR25L161B
> Macronix MX25L1605*, MX25L1635*
> PMC Pm25LV016B
> Spansion S25FL016A
> ST M25P16
> Winbond W25Q16*
>
> Are you 100% sure you have a ST M25P16?

i've disassembled my X60s yesterday, and indeed it is not a M25P16.
Instead it is a MX25L160AM2C. So i think the best is to discard this
patch. I'll send an updated one after i re-assembled my X60s (which
may take a while, as i'm trying to fit a SXGA+ TFT in it)

Regards and sorry for the noise,

Sven.

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iEYEARECAAYFAkz99VQACgkQIp3lOhiYlUr9PACeO9RAJyLbISZryo4A0Jw/iVfA
zrgAn0ZQ3VR9WgDDGOlHcyr+YJbxMP27
=QqHu
-----END PGP SIGNATURE-----



From svn at coreboot.org  Tue Dec  7 20:16:08 2010
From: svn at coreboot.org (repository service)
Date: Tue, 07 Dec 2010 20:16:08 +0100
Subject: [coreboot] [commit] r6147 - in trunk/src:
	mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240
	mainboard/abit/be6-ii_v2_0 mainboard/amd/mahogany_fam10
	mainboard/amd/tilapia_fam10 mainboard/asus/m4a78-em main...
Message-ID: <E1PQ31E-0005Zo-BP@ra.coresystems.de>

Author: uwe
Date: Tue Dec  7 20:16:07 2010
New Revision: 6147
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6147

Log:
Get rid of some unneeded function prototypes in romstage.c files.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/src/mainboard/a-trend/atc-6220/romstage.c
   trunk/src/mainboard/a-trend/atc-6240/romstage.c
   trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/asus/m4a78-em/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/asus/mew-am/romstage.c
   trunk/src/mainboard/asus/mew-vm/romstage.c
   trunk/src/mainboard/asus/p2b-d/romstage.c
   trunk/src/mainboard/asus/p2b-ds/romstage.c
   trunk/src/mainboard/asus/p2b-f/romstage.c
   trunk/src/mainboard/asus/p2b-ls/romstage.c
   trunk/src/mainboard/asus/p2b/romstage.c
   trunk/src/mainboard/asus/p3b-f/romstage.c
   trunk/src/mainboard/azza/pt-6ibd/romstage.c
   trunk/src/mainboard/biostar/m6tba/romstage.c
   trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
   trunk/src/mainboard/ecs/p6iwp-fe/romstage.c
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c
   trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/intel/d810e2cb/romstage.c
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/mitac/6513wu/romstage.c
   trunk/src/mainboard/msi/ms6119/romstage.c
   trunk/src/mainboard/msi/ms6147/romstage.c
   trunk/src/mainboard/msi/ms6156/romstage.c
   trunk/src/mainboard/msi/ms6178/romstage.c
   trunk/src/mainboard/nec/powermate2000/romstage.c
   trunk/src/mainboard/nokia/ip530/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
   trunk/src/mainboard/tyan/s1846/romstage.c
   trunk/src/northbridge/intel/i945/i945.h
   trunk/src/southbridge/intel/i82371eb/i82371eb.h
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
   trunk/src/southbridge/intel/i82801ax/i82801ax.h
   trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
   trunk/src/southbridge/intel/i82801bx/i82801bx.h
   trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
   trunk/src/southbridge/intel/i82801gx/i82801gx.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h

Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c
==============================================================================
--- trunk/src/mainboard/a-trend/atc-6220/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/a-trend/atc-6220/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c
==============================================================================
--- trunk/src/mainboard/a-trend/atc-6240/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/a-trend/atc-6240/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c
==============================================================================
--- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/m4a78-em/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/asus/mew-am/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/mew-am/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/mew-am/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -34,9 +34,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/asus/mew-vm/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/mew-vm/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/mew-vm/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -34,9 +34,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/asus/p2b-d/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-d/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p2b-d/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -37,9 +37,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-ds/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p2b-ds/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/asus/p2b-f/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-f/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p2b-f/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-ls/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p2b-ls/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/asus/p2b/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p2b/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/asus/p3b-f/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p3b-f/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/asus/p3b-f/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -35,10 +35,6 @@
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include <lib.h>
 
-void enable_pm(void);
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 

Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c
==============================================================================
--- trunk/src/mainboard/azza/pt-6ibd/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/azza/pt-6ibd/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/biostar/m6tba/romstage.c
==============================================================================
--- trunk/src/mainboard/biostar/m6tba/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/biostar/m6tba/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
==============================================================================
--- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 /* FIXME: This should be PC97307 (but it's buggy at the moment)! */
 #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/ecs/p6iwp-fe/romstage.c
==============================================================================
--- trunk/src/mainboard/ecs/p6iwp-fe/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/ecs/p6iwp-fe/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -33,9 +33,6 @@
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <lib.h>
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	it8712f_24mhz_clkin();

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/getac/p470/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -35,8 +35,6 @@
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
-void enable_smbus(void);
-
 void setup_ich7_gpios(void)
 {
 	u32 gpios;

Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -37,9 +37,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,7 +38,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -38,9 +38,6 @@
 /* TODO: It's a PC87364 actually! */
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	/* TODO: It's a PC87364 actually! */

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -40,8 +40,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 #define DUMMY_DEV PNP_DEV(0x4e, 0)
 
-void enable_smbus(void);
-
 void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -42,7 +42,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/fintek/f71859/f71859_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d810e2cb/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/intel/d810e2cb/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -35,9 +35,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	/* Set southbridge and Super I/O GPIOs. */

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -39,8 +39,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
-void enable_smbus(void);
-
 void setup_ich7_gpios(void)
 {
 	/* TODO: This is highly board specific and should be moved */

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -43,7 +43,6 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-static int smbus_read_byte(u32 device, u32 address);
 #include "superio/fintek/f71863fg/f71863fg_early_serial.c"
 #include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -34,7 +34,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-void enable_smbus(void);
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"

Modified: trunk/src/mainboard/mitac/6513wu/romstage.c
==============================================================================
--- trunk/src/mainboard/mitac/6513wu/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/mitac/6513wu/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -35,9 +35,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/msi/ms6119/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6119/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/msi/ms6119/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/msi/ms6147/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6147/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/msi/ms6147/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/msi/ms6156/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6156/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/msi/ms6156/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/msi/ms6178/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6178/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/msi/ms6178/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -35,9 +35,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	w83627hf_set_clksel_48(DUMMY_DEV);

Modified: trunk/src/mainboard/nec/powermate2000/romstage.c
==============================================================================
--- trunk/src/mainboard/nec/powermate2000/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/nec/powermate2000/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -34,9 +34,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Modified: trunk/src/mainboard/nokia/ip530/romstage.c
==============================================================================
--- trunk/src/mainboard/nokia/ip530/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/nokia/ip530/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -37,8 +37,6 @@
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
-void enable_smbus(void);
-
 void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");

Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
==============================================================================
--- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -37,9 +37,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/mainboard/tyan/s1846/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s1846/romstage.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/mainboard/tyan/s1846/romstage.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,9 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
 
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);

Modified: trunk/src/northbridge/intel/i945/i945.h
==============================================================================
--- trunk/src/northbridge/intel/i945/i945.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/northbridge/intel/i945/i945.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -337,9 +337,6 @@
 void i945_early_initialization(void);
 void i945_late_initialization(void);
 
-/* provided by southbridge code */
-int smbus_read_byte(unsigned device, unsigned address);
-
 /* provided by mainboard code */
 void setup_ich7_gpios(void);
 

Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -36,6 +36,12 @@
 #endif
 #endif
 
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+void enable_pm(void);
+#endif
+
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
  * 'reg' variable, otherwise it clears those bits.
  *

Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -26,8 +26,6 @@
 #include <console/console.h>
 #include "i82371eb.h"
 
-void enable_pm(void);
-
 void enable_pm(void)
 {
 	device_t dev;

Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -27,8 +27,6 @@
 #include "i82371eb.h"
 #include "i82371eb_smbus.h"
 
-int smbus_read_byte(u8 device, u8 address);
-
 void enable_smbus(void)
 {
 	device_t dev;

Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -1,4 +1,5 @@
 #include <device/smbus_def.h>
+#include "i82371eb.h"
 
 #define SMBHST_STATUS 	0x0
 #define SMBHST_CTL    	0x2
@@ -10,7 +11,6 @@
 #define SMBUS_STATUS_MASK 0x1e
 #define SMBUS_ERROR_FLAG (1<<2)
 
-void enable_smbus(void);
 int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
 
 static inline void smbus_delay(void)

Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801ax/i82801ax.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -23,7 +23,12 @@
 
 #if !defined(__PRE_RAM__)
 #include "chip.h"
-extern void i82801ax_enable(device_t dev);
+void i82801ax_enable(device_t dev);
+#endif
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
 #endif
 
 #define SMBUS_IO_BASE		0x0f00

Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -28,8 +28,6 @@
 #include "i82801ax.h"
 #include "i82801ax_smbus.h"
 
-int smbus_read_byte(u8 device, u8 address);
-
 void enable_smbus(void)
 {
 	device_t dev;

Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -19,8 +19,8 @@
  */
 
 #include <device/smbus_def.h>
+#include "i82801ax.h"
 
-void enable_smbus(void);
 int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
 
 static void smbus_delay(void)

Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -26,6 +26,11 @@
 extern void i82801bx_enable(device_t dev);
 #endif
 
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+#endif
+
 #define SMBUS_IO_BASE		0x0f00
 #define PMBASE_ADDR		0x0400
 #define GPIO_BASE_ADDR		0x0500

Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -28,8 +28,6 @@
 #include "i82801bx.h"
 #include "i82801bx_smbus.h"
 
-int smbus_read_byte(u8 device, u8 address);
-
 void enable_smbus(void)
 {
 	device_t dev;

Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -20,8 +20,6 @@
 
 #include <device/smbus_def.h>
 
-void enable_smbus(void);
-
 static void smbus_delay(void)
 {
 	inb(0x80);

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -46,6 +46,11 @@
 void i82801gx_enable_usbdebug(unsigned int port);
 #endif
 
+#if defined(__PRE_RAM__) && !defined(__ROMCC__) && !defined(ASSEMBLY)
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+#endif
+
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	Tue Dec  7 20:16:07 2010	(r6147)
@@ -26,8 +26,6 @@
 #include "i82801gx.h"
 #include "i82801gx_smbus.h"
 
-int smbus_read_byte(unsigned device, unsigned address);
-
 void enable_smbus(void)
 {
 	device_t dev;

Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h	Tue Dec  7 07:27:44 2010	(r6146)
+++ trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h	Tue Dec  7 20:16:07 2010	(r6147)
@@ -19,8 +19,7 @@
  */
 
 #include <device/smbus_def.h>
-
-void enable_smbus(void);
+#include "i82801gx.h"
 
 static void smbus_delay(void)
 {



From svn at coreboot.org  Tue Dec  7 20:34:02 2010
From: svn at coreboot.org (repository service)
Date: Tue, 07 Dec 2010 20:34:02 +0100
Subject: [coreboot] [commit] r6148 - trunk/src/northbridge/amd/amdfam10
Message-ID: <E1PQ3IY-00053Z-Fr@ra.coresystems.de>

Author: myles
Date: Tue Dec  7 20:34:01 2010
New Revision: 6148
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6148

Log:
Move MMCONF resource into the domain for fam10 for the resource allocator.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Scott Duplichan <scott at notabs.org>

Modified:
   trunk/src/northbridge/amd/amdfam10/northbridge.c

Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/northbridge.c	Tue Dec  7 20:16:07 2010	(r6147)
+++ trunk/src/northbridge/amd/amdfam10/northbridge.c	Tue Dec  7 20:34:01 2010	(r6148)
@@ -684,6 +684,13 @@
 		resource->flags = IORESOURCE_MEM;
 	}
 #endif
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *res = new_resource(dev, 0xc0010058);
+	res->base = CONFIG_MMCONF_BASE_ADDRESS;
+	res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+	res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
 }
 
 static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
@@ -1447,13 +1454,6 @@
 
 static void cpu_bus_read_resources(device_t dev)
 {
-#if CONFIG_MMCONF_SUPPORT
-	struct resource *resource = new_resource(dev, 0xc0010058);
-	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
-		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void cpu_bus_set_resources(device_t dev)



From mylesgw at gmail.com  Tue Dec  7 20:36:54 2010
From: mylesgw at gmail.com (Myles Watson)
Date: Tue, 7 Dec 2010 12:36:54 -0700
Subject: [coreboot] Porting to Asus M4A78-EM
In-Reply-To: <E20C9CC2E19341CA92FEFA54730B1638@m3a78>
References: <4CF2B0F3.8030106@iki.fi>
	<AANLkTinKyz9bAo1RAk-dD2hqfgdAOupChYdVRBh+4KBk@mail.gmail.com>
	<4CF7A783.7010006@iki.fi> <3624A23C43C24F4C806AC7D5A5140088@m3a78>
	<4CF7C0DE.7090406@iki.fi> <3D745430C93A402688CDA9A631DD0114@m3a78>
	<AANLkTi=SckeeJqhBdBv85LkOazQ1B7w1CdQRe_pBvmVM@mail.gmail.com>
	<AANLkTinXS0cTww=P-FttP2Gor+4gKkP7ZrOnkhYmDxRe@mail.gmail.com>
	<E20C9CC2E19341CA92FEFA54730B1638@m3a78>
Message-ID: <AANLkTinemJkxUaBtztKJhuba9wU8gA8oaRew7bggtYGi@mail.gmail.com>

On Tue, Dec 7, 2010 at 8:44 AM, Scott Duplichan <scott at notabs.org> wrote:
> On Thu, Dec 2, 2010 at 9:17 AM, Myles Watson <mylesgw at gmail.com> wrote:
>>> "Why does the current code for handling fixed resources allow the mmconf
>>> space to get allocated to a PCI device? Function avoid_fixed_resources
>>> calls function constrain_resources, which recursively searches the
>>> device tree for fixed io and memory resources. The ioapic fixed memory
>>> address is found and avoided during the recursive search because this
>>> southbridge device is below the level where the search starts. On the
>>> other hand, the mmconf fixed resource is added from the northbridge code,
>>> and falls under 'APIC_CLUSTER: 0'. This device is not part of the search
>>> for two reasons. One is that it is not at or below 'pci_domain 0' in the
>>> device tree. Another reason is that its type is APIC_CLUSTER and not
>>> PCI_DOMAIN."
>> I don't see any reason not to move that resource into the northbridge
>> to avoid that issue. ?It's a simple fix. ?Is there a good reason for
>> having the MMCONF BAR in the APIC cluster?
> This is what I was thinking. ?Build tested only.
>
> Signed-off-by: Myles Watson <mylesgw at gmail.com>
>
> Thanks,
> Myles
>
>
> Thanks for this patch Myles.
> Acked-by: Scott Duplichan <scott at notabs.org>
Rev 6148.

I think that some nice next steps would be:

- Set the size of the MMCONF area based on the number of busses in the machine.
- Let the resource allocator assign the location so that it doesn't
waste address space.

I don't think it would be too difficult, but it would require some testing.

Thanks,
Myles



From stepan at coreboot.org  Tue Dec  7 23:05:19 2010
From: stepan at coreboot.org (Stefan Reinauer)
Date: Tue, 7 Dec 2010 23:05:19 +0100
Subject: [coreboot] [PATCH] Move "select CACHE_AS_RAM" lines from boards
 into CPU socket
In-Reply-To: <20101206224552.GQ21636@greenwood>
References: <20101206224552.GQ21636@greenwood>
Message-ID: <20101207220518.GA7288@coreboot.org>

Hi Uwe,

good approach!

* Uwe Hermann <uwe at hermann-uwe.de> [101206 23:45]:
> Move "select CACHE_AS_RAM" lines from boards into CPU socket.

I generally like this idea, but that is not the only thing the patch
does. If it did, it were Acked-by: Stefan Reinauer <stepan at coreboot.org>

> All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
> into model_fxx/Kconfig and model_10xxx/Kconfig, and remove it from the
> individual boards and the individual sockets using model_fxx/model_10xxx.
 
I think CAR should be selected in the socket, not in the model. In case
of the AMD K8 CPUs it is not a big difference, but in general, a socket
should be the entity to decide whether a given setup can run CAR or not.

The rationale is that the socket is what enforces which CPU models can
run on a board. And if there is only one model for that socket that does
not support CAR, we can't do CAR for that socket (or would need to
define a new socket for that) 

Unfortunately we can not well model the above logic in model_* Kconfig
files very nicely, so it will have keep living in the socket.

In short, please drop the following part of the patch, add select
CACHE_AS_RAM to the K8/Fam10 sockets if it's missing there instead, and
it's all fine.

> Index: src/cpu/amd/socket_940/Kconfig
> ===================================================================
> --- src/cpu/amd/socket_940/Kconfig	(Revision 6145)
> +++ src/cpu/amd/socket_940/Kconfig	(Arbeitskopie)
> @@ -7,7 +7,6 @@
>  	def_bool y
>  	select K8_HT_FREQ_1G_SUPPORT
>  	select CPU_AMD_MODEL_FXX
> -	select CACHE_AS_RAM
>  
>  config CPU_ADDR_BITS
>  	int
> Index: src/cpu/amd/model_fxx/Kconfig
> ===================================================================
> --- src/cpu/amd/model_fxx/Kconfig	(Revision 6145)
> +++ src/cpu/amd/model_fxx/Kconfig	(Arbeitskopie)
> @@ -3,6 +3,7 @@
>  	select MMX
>  	select SSE
>  	select SSE2
> +	select CACHE_AS_RAM
>  
>  if CPU_AMD_MODEL_FXX
>  config UDELAY_IO
> Index: src/cpu/amd/socket_754/Kconfig
> ===================================================================
> --- src/cpu/amd/socket_754/Kconfig	(Revision 6145)
> +++ src/cpu/amd/socket_754/Kconfig	(Arbeitskopie)
> @@ -6,7 +6,6 @@
>  config SOCKET_SPECIFIC_OPTIONS
>  	def_bool y
>  	select CPU_AMD_MODEL_FXX
> -	select CACHE_AS_RAM
>  
>  config CPU_ADDR_BITS
>  	int

In addition, this is ugly because the actual code selection for CAR
still happens in the socket_*** Makefile.inc, so if there is a good
reason for moving from socket to model (except we wouldn't have to add
a line to each socket rather than just two models, i think this is no
sufficient reason to start becoming inconsistent across CPUs), the
Makefile.inc portion should be moved, too, and live where the Kconfig
portion lives.

Best case would be to remove CACHE_AS_RAM/ROMCC from Kconfig all
together, and plug it into the Makefiles, so we have less files to look
at for this one piece of logic. (By forgetting the Makefile.inc change
you proved this point ;)

Stefan





From stepan at coreboot.org  Tue Dec  7 23:06:37 2010
From: stepan at coreboot.org (Stefan Reinauer)
Date: Tue, 7 Dec 2010 23:06:37 +0100
Subject: [coreboot] [PATCH] Move "select CACHE_AS_RAM" lines from boards
 into CPU socket
In-Reply-To: <4CFE5433.4080808@georgi-clan.de>
References: <20101206224552.GQ21636@greenwood>
	<4CFE5433.4080808@georgi-clan.de>
Message-ID: <20101207220637.GB7288@coreboot.org>

* Patrick Georgi <patrick at georgi-clan.de> [101207 16:35]:
> Am 06.12.2010 23:45, schrieb Uwe Hermann:
> > See patch.
> src/cpu/Kconfig defines CACHE_AS_RAM to "!ROMCC", so I think these can
> be dropped completely. Right?
> 
> We basically assume it's CAR unless romcc is used.

This seems to make a lot of sense.

Do we need this stuff in Kconfig at all?

Stefan



From stepan at coreboot.org  Tue Dec  7 23:11:23 2010
From: stepan at coreboot.org (Stefan Reinauer)
Date: Tue, 7 Dec 2010 23:11:23 +0100
Subject: [coreboot] [PATCH] Move "select CACHE_AS_RAM" lines from boards
 into CPU socket
In-Reply-To: <20101207220637.GB7288@coreboot.org>
References: <20101206224552.GQ21636@greenwood>
	<4CFE5433.4080808@georgi-clan.de>
	<20101207220637.GB7288@coreboot.org>
Message-ID: <20101207221123.GA14819@coreboot.org>

* Stefan Reinauer <stepan at coreboot.org> [101207 23:06]:
> * Patrick Georgi <patrick at georgi-clan.de> [101207 16:35]:
> > Am 06.12.2010 23:45, schrieb Uwe Hermann:
> > > See patch.
> > src/cpu/Kconfig defines CACHE_AS_RAM to "!ROMCC", so I think these can
> > be dropped completely. Right?
> > 
> > We basically assume it's CAR unless romcc is used.
> 
> This seems to make a lot of sense.
> 
> Do we need this stuff in Kconfig at all?

There are only very few places in the Makefile that need the
distinction:

./src/arch/i386/Makefile.inc:ifeq ($(CONFIG_ROMCC),y)
./src/arch/i386/Makefile.inc:ifeq ($(CONFIG_ROMCC),y)
./src/pc80/Makefile.inc:romstage-$(CONFIG_CACHE_AS_RAM) += serial.c
./src/console/Makefile.inc:romstage-$(CONFIG_CACHE_AS_RAM) += console.c
./src/lib/Makefile.inc:romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c

And some in the .c files, but I think it would be safe to replace those
#if CONFIG_CACHE_AS_RAM with #ifndef __ROMCC__ 

Stefan



From svn at coreboot.org  Wed Dec  8 06:42:48 2010
From: svn at coreboot.org (repository service)
Date: Wed, 08 Dec 2010 06:42:48 +0100
Subject: [coreboot] [commit] r6149 - in trunk/src:
	mainboard/advantech/pcm-5820 mainboard/amd/db800
	mainboard/amd/dbm690t mainboard/amd/mahogany
	mainboard/amd/mahogany_fam10 mainboard/amd/norwich
	mainboard/amd/pistach...
Message-ID: <E1PQCng-00066m-9d@ra.coresystems.de>

Author: stepan
Date: Wed Dec  8 06:42:47 2010
New Revision: 6149
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6149

Log:
first round name simplification. drop the <component>_ prefix.

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan at coresystems.de>

Acked-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/southbridge/amd/amd8111/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c
   trunk/src/southbridge/amd/amd8111/acpi.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c
   trunk/src/southbridge/amd/amd8111/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
   trunk/src/southbridge/amd/amd8111/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c
   trunk/src/southbridge/amd/amd8111/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c
   trunk/src/southbridge/amd/amd8111/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c
   trunk/src/southbridge/amd/amd8111/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/src/southbridge/amd/amd8111/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c
   trunk/src/southbridge/amd/amd8111/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c
   trunk/src/southbridge/amd/amd8111/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c
   trunk/src/southbridge/amd/amd8111/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c
   trunk/src/southbridge/amd/amd8111/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c
   trunk/src/southbridge/amd/amd8111/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c
   trunk/src/southbridge/amd/amd8131-disable/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8131/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8132/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/src/southbridge/amd/amd8151/agp3.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c
   trunk/src/southbridge/amd/cs5530/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c
   trunk/src/southbridge/amd/cs5530/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c
   trunk/src/southbridge/amd/cs5530/isa.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/src/southbridge/amd/cs5530/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c
   trunk/src/southbridge/amd/cs5530/vga.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c
   trunk/src/southbridge/amd/cs5535/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c
   trunk/src/southbridge/amd/cs5535/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c
   trunk/src/southbridge/amd/cs5535/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c
   trunk/src/southbridge/amd/cs5535/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h
   trunk/src/southbridge/amd/cs5536/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
   trunk/src/southbridge/amd/cs5536/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c
   trunk/src/southbridge/amd/cs5536/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c
   trunk/src/southbridge/amd/cs5536/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c
   trunk/src/southbridge/amd/cs5536/smbus2.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h
   trunk/src/southbridge/amd/rs690/cmn.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/src/southbridge/amd/rs690/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c
   trunk/src/southbridge/amd/rs690/gfx.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/src/southbridge/amd/rs690/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c
   trunk/src/southbridge/amd/rs690/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c
   trunk/src/southbridge/amd/rs780/cmn.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c
   trunk/src/southbridge/amd/rs780/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/amd/rs780/gfx.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c
   trunk/src/southbridge/amd/rs780/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c
   trunk/src/southbridge/amd/rs780/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c
   trunk/src/southbridge/amd/rs780/rev.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h
   trunk/src/southbridge/amd/sb600/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c
   trunk/src/southbridge/amd/sb600/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_early_setup.c
   trunk/src/southbridge/amd/sb600/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c
   trunk/src/southbridge/amd/sb600/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
   trunk/src/southbridge/amd/sb600/hda.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c
   trunk/src/southbridge/amd/sb600/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c
   trunk/src/southbridge/amd/sb600/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/src/southbridge/amd/sb600/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c
   trunk/src/southbridge/amd/sb600/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c
   trunk/src/southbridge/amd/sb600/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c
   trunk/src/southbridge/amd/sb600/sm.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_sm.c
   trunk/src/southbridge/amd/sb600/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.c
   trunk/src/southbridge/amd/sb600/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h
   trunk/src/southbridge/amd/sb600/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c
   trunk/src/southbridge/amd/sb700/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_early_setup.c
   trunk/src/southbridge/amd/sb700/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
   trunk/src/southbridge/amd/sb700/hda.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c
   trunk/src/southbridge/amd/sb700/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c
   trunk/src/southbridge/amd/sb700/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c
   trunk/src/southbridge/amd/sb700/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c
   trunk/src/southbridge/amd/sb700/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c
   trunk/src/southbridge/amd/sb700/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c
   trunk/src/southbridge/amd/sb700/sm.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_sm.c
   trunk/src/southbridge/amd/sb700/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.c
   trunk/src/southbridge/amd/sb700/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h
   trunk/src/southbridge/amd/sb700/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c
   trunk/src/southbridge/broadcom/bcm21000/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c
   trunk/src/southbridge/broadcom/bcm5780/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/pcix.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
   trunk/src/southbridge/broadcom/bcm5785/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
   trunk/src/southbridge/broadcom/bcm5785/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
   trunk/src/southbridge/broadcom/bcm5785/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
   trunk/src/southbridge/broadcom/bcm5785/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
   trunk/src/southbridge/broadcom/bcm5785/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/src/southbridge/broadcom/bcm5785/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
   trunk/src/southbridge/broadcom/bcm5785/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
   trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c
      - copied, changed from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/src/southbridge/broadcom/bcm5785/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
   trunk/src/southbridge/broadcom/bcm5785/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
   trunk/src/southbridge/intel/esb6300/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c
   trunk/src/southbridge/intel/esb6300/bridge1c.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/src/southbridge/intel/esb6300/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/src/southbridge/intel/esb6300/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c
   trunk/src/southbridge/intel/esb6300/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c
   trunk/src/southbridge/intel/esb6300/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/src/southbridge/intel/esb6300/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c
   trunk/src/southbridge/intel/esb6300/pic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c
   trunk/src/southbridge/intel/esb6300/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c
   trunk/src/southbridge/intel/esb6300/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/src/southbridge/intel/esb6300/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.c
   trunk/src/southbridge/intel/esb6300/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h
   trunk/src/southbridge/intel/esb6300/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c
   trunk/src/southbridge/intel/i3100/early_lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/src/southbridge/intel/i3100/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/src/southbridge/intel/i3100/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c
   trunk/src/southbridge/intel/i3100/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/src/southbridge/intel/i3100/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c
   trunk/src/southbridge/intel/i3100/pciexp_portb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c
   trunk/src/southbridge/intel/i3100/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c
   trunk/src/southbridge/intel/i3100/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c
   trunk/src/southbridge/intel/i3100/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.c
   trunk/src/southbridge/intel/i3100/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h
   trunk/src/southbridge/intel/i3100/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c
   trunk/src/southbridge/intel/i82371eb/early_pm.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
   trunk/src/southbridge/intel/i82371eb/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
   trunk/src/southbridge/intel/i82371eb/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
   trunk/src/southbridge/intel/i82371eb/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c
   trunk/src/southbridge/intel/i82371eb/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c
   trunk/src/southbridge/intel/i82371eb/isa.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/src/southbridge/intel/i82371eb/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c
   trunk/src/southbridge/intel/i82371eb/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c
   trunk/src/southbridge/intel/i82371eb/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
   trunk/src/southbridge/intel/i82371eb/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c
   trunk/src/southbridge/intel/i82801ax/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c
   trunk/src/southbridge/intel/i82801ax/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
   trunk/src/southbridge/intel/i82801ax/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c
   trunk/src/southbridge/intel/i82801ax/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
   trunk/src/southbridge/intel/i82801ax/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c
   trunk/src/southbridge/intel/i82801ax/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c
   trunk/src/southbridge/intel/i82801ax/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c
   trunk/src/southbridge/intel/i82801ax/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
   trunk/src/southbridge/intel/i82801ax/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c
   trunk/src/southbridge/intel/i82801ax/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
   trunk/src/southbridge/intel/i82801bx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c
   trunk/src/southbridge/intel/i82801bx/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
   trunk/src/southbridge/intel/i82801bx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c
   trunk/src/southbridge/intel/i82801bx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
   trunk/src/southbridge/intel/i82801bx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c
   trunk/src/southbridge/intel/i82801bx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c
   trunk/src/southbridge/intel/i82801bx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c
   trunk/src/southbridge/intel/i82801bx/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c
   trunk/src/southbridge/intel/i82801bx/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
   trunk/src/southbridge/intel/i82801bx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c
   trunk/src/southbridge/intel/i82801bx/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
   trunk/src/southbridge/intel/i82801cx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c
   trunk/src/southbridge/intel/i82801cx/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
   trunk/src/southbridge/intel/i82801cx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c
   trunk/src/southbridge/intel/i82801cx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
   trunk/src/southbridge/intel/i82801cx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c
   trunk/src/southbridge/intel/i82801cx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c
   trunk/src/southbridge/intel/i82801cx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c
   trunk/src/southbridge/intel/i82801cx/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c
   trunk/src/southbridge/intel/i82801cx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c
   trunk/src/southbridge/intel/i82801dx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c
   trunk/src/southbridge/intel/i82801dx/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
   trunk/src/southbridge/intel/i82801dx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c
   trunk/src/southbridge/intel/i82801dx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
   trunk/src/southbridge/intel/i82801dx/nvs.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h
   trunk/src/southbridge/intel/i82801dx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c
   trunk/src/southbridge/intel/i82801dx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c
   trunk/src/southbridge/intel/i82801dx/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c
   trunk/src/southbridge/intel/i82801dx/smi.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c
   trunk/src/southbridge/intel/i82801dx/smihandler.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c
   trunk/src/southbridge/intel/i82801dx/tco_timer.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
   trunk/src/southbridge/intel/i82801dx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c
   trunk/src/southbridge/intel/i82801dx/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c
   trunk/src/southbridge/intel/i82801ex/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c
   trunk/src/southbridge/intel/i82801ex/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
   trunk/src/southbridge/intel/i82801ex/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c
   trunk/src/southbridge/intel/i82801ex/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c
   trunk/src/southbridge/intel/i82801ex/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
   trunk/src/southbridge/intel/i82801ex/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c
   trunk/src/southbridge/intel/i82801ex/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c
   trunk/src/southbridge/intel/i82801ex/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c
   trunk/src/southbridge/intel/i82801ex/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c
   trunk/src/southbridge/intel/i82801ex/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h
   trunk/src/southbridge/intel/i82801ex/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c
   trunk/src/southbridge/intel/i82801ex/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
   trunk/src/southbridge/intel/i82801gx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c
   trunk/src/southbridge/intel/i82801gx/acpi/ac97.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
   trunk/src/southbridge/intel/i82801gx/acpi/audio.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
   trunk/src/southbridge/intel/i82801gx/acpi/irqlinks.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
   trunk/src/southbridge/intel/i82801gx/acpi/lpc.asl
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pata.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pci.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pcie.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
   trunk/src/southbridge/intel/i82801gx/acpi/sata.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/smbus.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
   trunk/src/southbridge/intel/i82801gx/acpi/usb.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
   trunk/src/southbridge/intel/i82801gx/azalia.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c
   trunk/src/southbridge/intel/i82801gx/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c
   trunk/src/southbridge/intel/i82801gx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/src/southbridge/intel/i82801gx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c
   trunk/src/southbridge/intel/i82801gx/nvs.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h
   trunk/src/southbridge/intel/i82801gx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c
   trunk/src/southbridge/intel/i82801gx/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c
   trunk/src/southbridge/intel/i82801gx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c
   trunk/src/southbridge/intel/i82801gx/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c
   trunk/src/southbridge/intel/i82801gx/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c
   trunk/src/southbridge/intel/i82801gx/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
   trunk/src/southbridge/intel/i82801gx/smi.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c
   trunk/src/southbridge/intel/i82801gx/smihandler.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
   trunk/src/southbridge/intel/i82801gx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c
   trunk/src/southbridge/intel/i82801gx/usb_debug.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
   trunk/src/southbridge/intel/i82801gx/usb_ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
   trunk/src/southbridge/intel/i82801gx/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
   trunk/src/southbridge/intel/i82870/ioapic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_ioapic.c
   trunk/src/southbridge/intel/i82870/pci_parity.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c
   trunk/src/southbridge/intel/i82870/pcibridge.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c
   trunk/src/southbridge/intel/pxhd/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
   trunk/src/southbridge/nvidia/ck804/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ac97.c
   trunk/src/southbridge/nvidia/ck804/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/src/southbridge/nvidia/ck804/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
   trunk/src/southbridge/nvidia/ck804/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/src/southbridge/nvidia/ck804/early_smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.h
   trunk/src/southbridge/nvidia/ck804/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c
   trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
   trunk/src/southbridge/nvidia/ck804/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_fadt.c
   trunk/src/southbridge/nvidia/ck804/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ht.c
   trunk/src/southbridge/nvidia/ck804/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ide.c
   trunk/src/southbridge/nvidia/ck804/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/src/southbridge/nvidia/ck804/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/src/southbridge/nvidia/ck804/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/src/southbridge/nvidia/ck804/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_pcie.c
   trunk/src/southbridge/nvidia/ck804/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_reset.c
   trunk/src/southbridge/nvidia/ck804/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/src/southbridge/nvidia/ck804/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/ck804/ck804_smbus.c
   trunk/src/southbridge/nvidia/ck804/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/src/southbridge/nvidia/ck804/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_usb.c
   trunk/src/southbridge/nvidia/ck804/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_usb2.c
   trunk/src/southbridge/nvidia/mcp55/azalia.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c
   trunk/src/southbridge/nvidia/mcp55/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/src/southbridge/nvidia/mcp55/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
   trunk/src/southbridge/nvidia/mcp55/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/src/southbridge/nvidia/mcp55/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
   trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
   trunk/src/southbridge/nvidia/mcp55/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c
   trunk/src/southbridge/nvidia/mcp55/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_ht.c
   trunk/src/southbridge/nvidia/mcp55/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_ide.c
   trunk/src/southbridge/nvidia/mcp55/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/src/southbridge/nvidia/mcp55/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_nic.c
   trunk/src/southbridge/nvidia/mcp55/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/src/southbridge/nvidia/mcp55/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_pcie.c
   trunk/src/southbridge/nvidia/mcp55/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/src/southbridge/nvidia/mcp55/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_sata.c
   trunk/src/southbridge/nvidia/mcp55/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/src/southbridge/nvidia/mcp55/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h
   trunk/src/southbridge/nvidia/mcp55/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_usb.c
   trunk/src/southbridge/nvidia/mcp55/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_usb2.c
   trunk/src/southbridge/sis/sis966/aza.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_aza.c
   trunk/src/southbridge/sis/sis966/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/src/southbridge/sis/sis966/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c
   trunk/src/southbridge/sis/sis966/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_setup_ss.h
   trunk/src/southbridge/sis/sis966/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/src/southbridge/sis/sis966/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_enable_rom.c
   trunk/src/southbridge/sis/sis966/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
   trunk/src/southbridge/sis/sis966/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_ide.c
   trunk/src/southbridge/sis/sis966/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/src/southbridge/sis/sis966/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_nic.c
   trunk/src/southbridge/sis/sis966/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_pcie.c
   trunk/src/southbridge/sis/sis966/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_reset.c
   trunk/src/southbridge/sis/sis966/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_sata.c
   trunk/src/southbridge/sis/sis966/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_smbus.h
   trunk/src/southbridge/sis/sis966/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_usb.c
   trunk/src/southbridge/sis/sis966/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/src/southbridge/ti/pci7420/cardbus.c
      - copied unchanged from r6148, trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c
   trunk/src/southbridge/ti/pci7420/firewire.c
      - copied unchanged from r6148, trunk/src/southbridge/ti/pci7420/pci7420_firewire.c
   trunk/src/southbridge/via/k8t890/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_bridge.c
   trunk/src/southbridge/via/k8t890/chrome.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8m890_chrome.c
   trunk/src/southbridge/via/k8t890/ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/dram.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_dram.c
   trunk/src/southbridge/via/k8t890/early_car.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/southbridge/via/k8t890/error.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_error.c
   trunk/src/southbridge/via/k8t890/host.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_host.c
   trunk/src/southbridge/via/k8t890/host_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c
   trunk/src/southbridge/via/k8t890/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_pcie.c
   trunk/src/southbridge/via/k8t890/traf_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
   trunk/src/southbridge/via/vt8231/acpi.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_acpi.c
   trunk/src/southbridge/via/vt8231/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
   trunk/src/southbridge/via/vt8231/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
   trunk/src/southbridge/via/vt8231/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
   trunk/src/southbridge/via/vt8231/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_ide.c
   trunk/src/southbridge/via/vt8231/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/src/southbridge/via/vt8231/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_nic.c
   trunk/src/southbridge/via/vt8231/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_usb.c
   trunk/src/southbridge/via/vt8235/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
   trunk/src/southbridge/via/vt8235/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
   trunk/src/southbridge/via/vt8235/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_ide.c
   trunk/src/southbridge/via/vt8235/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/src/southbridge/via/vt8235/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_nic.c
   trunk/src/southbridge/via/vt8235/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_usb.c
   trunk/src/southbridge/via/vt8237r/ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/src/southbridge/via/vt8237r/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
   trunk/src/southbridge/via/vt8237r/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/src/southbridge/via/vt8237r/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/src/southbridge/via/vt8237r/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_nic.c
   trunk/src/southbridge/via/vt8237r/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c
   trunk/src/southbridge/via/vt8237r/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_sata.c
   trunk/src/southbridge/via/vt8237r/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_usb.c
   trunk/src/southbridge/via/vt82c686/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c
Deleted:
   trunk/src/southbridge/amd/amd8111/amd8111_ac97.c
   trunk/src/southbridge/amd/amd8111/amd8111_acpi.c
   trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
   trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c
   trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c
   trunk/src/southbridge/amd/amd8111/amd8111_ide.c
   trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/src/southbridge/amd/amd8111/amd8111_nic.c
   trunk/src/southbridge/amd/amd8111/amd8111_pci.c
   trunk/src/southbridge/amd/amd8111/amd8111_reset.c
   trunk/src/southbridge/amd/amd8111/amd8111_smbus.c
   trunk/src/southbridge/amd/amd8111/amd8111_usb.c
   trunk/src/southbridge/amd/amd8111/amd8111_usb2.c
   trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/src/southbridge/amd/amd8151/amd8151_agp3.c
   trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c
   trunk/src/southbridge/amd/cs5530/cs5530_ide.c
   trunk/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/src/southbridge/amd/cs5530/cs5530_pirq.c
   trunk/src/southbridge/amd/cs5530/cs5530_vga.c
   trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c
   trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c
   trunk/src/southbridge/amd/cs5535/cs5535_ide.c
   trunk/src/southbridge/amd/cs5535/cs5535_smbus.h
   trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
   trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c
   trunk/src/southbridge/amd/cs5536/cs5536_ide.c
   trunk/src/southbridge/amd/cs5536/cs5536_pirq.c
   trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h
   trunk/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/src/southbridge/amd/rs690/rs690_early_setup.c
   trunk/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/src/southbridge/amd/rs690/rs690_ht.c
   trunk/src/southbridge/amd/rs690/rs690_pcie.c
   trunk/src/southbridge/amd/rs780/rs780_cmn.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/amd/rs780/rs780_gfx.c
   trunk/src/southbridge/amd/rs780/rs780_ht.c
   trunk/src/southbridge/amd/rs780/rs780_pcie.c
   trunk/src/southbridge/amd/rs780/rs780_rev.h
   trunk/src/southbridge/amd/sb600/sb600_ac97.c
   trunk/src/southbridge/amd/sb600/sb600_early_setup.c
   trunk/src/southbridge/amd/sb600/sb600_enable_rom.c
   trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
   trunk/src/southbridge/amd/sb600/sb600_hda.c
   trunk/src/southbridge/amd/sb600/sb600_ide.c
   trunk/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/src/southbridge/amd/sb600/sb600_pci.c
   trunk/src/southbridge/amd/sb600/sb600_reset.c
   trunk/src/southbridge/amd/sb600/sb600_sata.c
   trunk/src/southbridge/amd/sb600/sb600_sm.c
   trunk/src/southbridge/amd/sb600/sb600_smbus.c
   trunk/src/southbridge/amd/sb600/sb600_smbus.h
   trunk/src/southbridge/amd/sb600/sb600_usb.c
   trunk/src/southbridge/amd/sb700/sb700_early_setup.c
   trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
   trunk/src/southbridge/amd/sb700/sb700_hda.c
   trunk/src/southbridge/amd/sb700/sb700_ide.c
   trunk/src/southbridge/amd/sb700/sb700_lpc.c
   trunk/src/southbridge/amd/sb700/sb700_pci.c
   trunk/src/southbridge/amd/sb700/sb700_reset.c
   trunk/src/southbridge/amd/sb700/sb700_sata.c
   trunk/src/southbridge/amd/sb700/sb700_sm.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.h
   trunk/src/southbridge/amd/sb700/sb700_usb.c
   trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
   trunk/src/southbridge/intel/esb6300/esb6300_ac97.c
   trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/src/southbridge/intel/esb6300/esb6300_ehci.c
   trunk/src/southbridge/intel/esb6300/esb6300_ide.c
   trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/src/southbridge/intel/esb6300/esb6300_pci.c
   trunk/src/southbridge/intel/esb6300/esb6300_pic.c
   trunk/src/southbridge/intel/esb6300/esb6300_reset.c
   trunk/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/src/southbridge/intel/esb6300/esb6300_smbus.c
   trunk/src/southbridge/intel/esb6300/esb6300_smbus.h
   trunk/src/southbridge/intel/esb6300/esb6300_uhci.c
   trunk/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/src/southbridge/intel/i3100/i3100_ehci.c
   trunk/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/src/southbridge/intel/i3100/i3100_pci.c
   trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c
   trunk/src/southbridge/intel/i3100/i3100_reset.c
   trunk/src/southbridge/intel/i3100/i3100_sata.c
   trunk/src/southbridge/intel/i3100/i3100_smbus.c
   trunk/src/southbridge/intel/i3100/i3100_smbus.h
   trunk/src/southbridge/intel/i3100/i3100_uhci.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
   trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
   trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
   trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h
   trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h
   trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
   trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
   trunk/src/southbridge/intel/i82870/p64h2_ioapic.c
   trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c
   trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c
   trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
   trunk/src/southbridge/nvidia/ck804/ck804_ac97.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
   trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.h
   trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c
   trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
   trunk/src/southbridge/nvidia/ck804/ck804_fadt.c
   trunk/src/southbridge/nvidia/ck804/ck804_ht.c
   trunk/src/southbridge/nvidia/ck804/ck804_ide.c
   trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/src/southbridge/nvidia/ck804/ck804_pcie.c
   trunk/src/southbridge/nvidia/ck804/ck804_reset.c
   trunk/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/src/southbridge/nvidia/ck804/ck804_smbus.c
   trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/src/southbridge/nvidia/ck804/ck804_usb.c
   trunk/src/southbridge/nvidia/ck804/ck804_usb2.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_ht.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_ide.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_nic.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_pcie.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_sata.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h
   trunk/src/southbridge/nvidia/mcp55/mcp55_usb.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_usb2.c
   trunk/src/southbridge/sis/sis966/sis966_aza.c
   trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c
   trunk/src/southbridge/sis/sis966/sis966_early_setup_ss.h
   trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/src/southbridge/sis/sis966/sis966_enable_rom.c
   trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
   trunk/src/southbridge/sis/sis966/sis966_ide.c
   trunk/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/src/southbridge/sis/sis966/sis966_nic.c
   trunk/src/southbridge/sis/sis966/sis966_pcie.c
   trunk/src/southbridge/sis/sis966/sis966_reset.c
   trunk/src/southbridge/sis/sis966/sis966_sata.c
   trunk/src/southbridge/sis/sis966/sis966_smbus.h
   trunk/src/southbridge/sis/sis966/sis966_usb.c
   trunk/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c
   trunk/src/southbridge/ti/pci7420/pci7420_firewire.c
   trunk/src/southbridge/via/k8t890/k8m890_chrome.c
   trunk/src/southbridge/via/k8t890/k8t890_bridge.c
   trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_dram.c
   trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/southbridge/via/k8t890/k8t890_error.c
   trunk/src/southbridge/via/k8t890/k8t890_host.c
   trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_pcie.c
   trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
   trunk/src/southbridge/via/vt8231/vt8231_acpi.c
   trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
   trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
   trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
   trunk/src/southbridge/via/vt8231/vt8231_ide.c
   trunk/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/src/southbridge/via/vt8231/vt8231_nic.c
   trunk/src/southbridge/via/vt8231/vt8231_usb.c
   trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
   trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
   trunk/src/southbridge/via/vt8235/vt8235_ide.c
   trunk/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/src/southbridge/via/vt8235/vt8235_nic.c
   trunk/src/southbridge/via/vt8235/vt8235_usb.c
   trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/src/southbridge/via/vt8237r/vt8237r_nic.c
   trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c
   trunk/src/southbridge/via/vt8237r/vt8237r_sata.c
   trunk/src/southbridge/via/vt8237r/vt8237r_usb.c
   trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c
Modified:
   trunk/src/mainboard/advantech/pcm-5820/romstage.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/norwich/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/artecgroup/dbe61/romstage.c
   trunk/src/mainboard/asi/mb_5blgp/romstage.c
   trunk/src/mainboard/asi/mb_5blmp/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/m2v/romstage.c
   trunk/src/mainboard/asus/m4a78-em/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/axus/tc320/romstage.c
   trunk/src/mainboard/bcom/winnet100/romstage.c
   trunk/src/mainboard/bcom/winnetp680/romstage.c
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/dell/s1850/romstage.c
   trunk/src/mainboard/digitallogic/adl855pc/romstage.c
   trunk/src/mainboard/digitallogic/msm800sev/romstage.c
   trunk/src/mainboard/eaglelion/5bcm/romstage.c
   trunk/src/mainboard/getac/p470/acpi_tables.c
   trunk/src/mainboard/getac/p470/mainboard_smi.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/dl145_g1/romstage.c
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
   trunk/src/mainboard/ibase/mb899/acpi_tables.c
   trunk/src/mainboard/ibase/mb899/mainboard_smi.c
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/iei/juki-511p/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/iei/nova4899r/romstage.c
   trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
   trunk/src/mainboard/intel/d945gclf/acpi_tables.c
   trunk/src/mainboard/intel/d945gclf/mainboard_smi.c
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/mainboard/intel/jarrell/romstage.c
   trunk/src/mainboard/intel/mtarvon/romstage.c
   trunk/src/mainboard/intel/truxton/romstage.c
   trunk/src/mainboard/intel/xe7501devkit/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c
   trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/lanner/em8510/romstage.c
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/lippert/hurricane-lx/romstage.c
   trunk/src/mainboard/lippert/literunner-lx/romstage.c
   trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
   trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/pcengines/alix1c/romstage.c
   trunk/src/mainboard/pcengines/alix2d/romstage.c
   trunk/src/mainboard/rca/rm4100/romstage.c
   trunk/src/mainboard/roda/rk886ex/acpi_tables.c
   trunk/src/mainboard/roda/rk886ex/mainboard_smi.c
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/supermicro/x6dai_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/televideo/tc7020/romstage.c
   trunk/src/mainboard/thomson/ip1000/romstage.c
   trunk/src/mainboard/traverse/geos/romstage.c
   trunk/src/mainboard/tyan/s2735/romstage.c
   trunk/src/mainboard/tyan/s2850/romstage.c
   trunk/src/mainboard/tyan/s2875/romstage.c
   trunk/src/mainboard/tyan/s2880/romstage.c
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2882/romstage.c
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2892/romstage.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/mainboard/tyan/s4882/romstage.c
   trunk/src/mainboard/via/epia-cn/romstage.c
   trunk/src/mainboard/via/epia-m/romstage.c
   trunk/src/mainboard/via/epia-n/romstage.c
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/mainboard/via/pc2500e/romstage.c
   trunk/src/mainboard/winent/pl6064/romstage.c
   trunk/src/mainboard/wyse/s50/romstage.c
   trunk/src/southbridge/amd/amd8111/Makefile.inc
   trunk/src/southbridge/amd/amd8111/bootblock.c
   trunk/src/southbridge/amd/amd8131/Makefile.inc
   trunk/src/southbridge/amd/amd8132/Makefile.inc
   trunk/src/southbridge/amd/amd8151/Makefile.inc
   trunk/src/southbridge/amd/cs5530/Makefile.inc
   trunk/src/southbridge/amd/cs5535/Makefile.inc
   trunk/src/southbridge/amd/cs5536/Makefile.inc
   trunk/src/southbridge/amd/rs690/Makefile.inc
   trunk/src/southbridge/amd/rs780/Makefile.inc
   trunk/src/southbridge/amd/rs780/rs780.h
   trunk/src/southbridge/amd/sb600/Makefile.inc
   trunk/src/southbridge/amd/sb600/bootblock.c
   trunk/src/southbridge/amd/sb700/Makefile.inc
   trunk/src/southbridge/broadcom/bcm21000/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5780/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5785/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5785/bootblock.c
   trunk/src/southbridge/intel/esb6300/Makefile.inc
   trunk/src/southbridge/intel/i3100/Makefile.inc
   trunk/src/southbridge/intel/i82371eb/Makefile.inc
   trunk/src/southbridge/intel/i82371eb/bootblock.c
   trunk/src/southbridge/intel/i82801ax/Makefile.inc
   trunk/src/southbridge/intel/i82801bx/Makefile.inc
   trunk/src/southbridge/intel/i82801cx/Makefile.inc
   trunk/src/southbridge/intel/i82801dx/Makefile.inc
   trunk/src/southbridge/intel/i82801ex/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl
   trunk/src/southbridge/intel/i82870/Makefile.inc
   trunk/src/southbridge/intel/pxhd/Makefile.inc
   trunk/src/southbridge/nvidia/ck804/Makefile.inc
   trunk/src/southbridge/nvidia/ck804/bootblock.c
   trunk/src/southbridge/nvidia/mcp55/Makefile.inc
   trunk/src/southbridge/nvidia/mcp55/bootblock.c
   trunk/src/southbridge/sis/sis966/Makefile.inc
   trunk/src/southbridge/ti/pci7420/Makefile.inc
   trunk/src/southbridge/via/k8t890/Makefile.inc
   trunk/src/southbridge/via/vt8231/Makefile.inc
   trunk/src/southbridge/via/vt8235/Makefile.inc
   trunk/src/southbridge/via/vt8237r/Makefile.inc

Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/advantech/pcm-5820/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/db800/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,9 +43,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 #include <spd.h>
 
@@ -69,7 +69,7 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {

Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/norwich/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,9 +38,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,8 +10,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -26,7 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -48,7 +48,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 

Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,8 +33,8 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blgp/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asi/mb_5blgp/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 

Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blmp/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asi/mb_5blmp/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,9 +44,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -41,8 +41,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -41,8 +41,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -62,7 +62,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m2v/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m2v/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -64,7 +64,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m4a78-em/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/axus/tc320/romstage.c
==============================================================================
--- trunk/src/mainboard/axus/tc320/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/axus/tc320/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/bcom/winnet100/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnet100/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/bcom/winnet100/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/dell/s1850/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc8374/pc8374_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"

Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,8 +12,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/eaglelion/5bcm/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

Modified: trunk/src/mainboard/getac/p470/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/getac/p470/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/getac/p470/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 
 extern unsigned char AmlCode[];
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {

Modified: trunk/src/mainboard/getac/p470/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/getac/p470/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/getac/p470/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/i82801gx.h"
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 #include "northbridge/intel/i945/udelay.c"
 #include "ec.c"
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -39,8 +39,8 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/sis/sis966/sis966.h"
-#include "southbridge/sis/sis966/sis966_early_smbus.c"
-#include "southbridge/sis/sis966/sis966_enable_rom.c"
+#include "southbridge/sis/sis966/early_smbus.c"
+#include "southbridge/sis/sis966/enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -52,7 +52,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/sis/sis966/sis966_early_ctrl.c"
+#include "southbridge/sis/sis966/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
@@ -86,7 +86,7 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
+#include "southbridge/sis/sis966/early_setup_ss.h"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <usbdebug.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
@@ -69,8 +69,8 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -64,7 +64,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -40,7 +40,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -53,7 +53,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -39,7 +39,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

Modified: trunk/src/mainboard/ibase/mb899/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibase/mb899/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/ibase/mb899/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibase/mb899/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)

Modified: trunk/src/mainboard/iei/juki-511p/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/juki-511p/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "northbridge/amd/gx1/raminit.c"

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -70,7 +70,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/iei/nova4899r/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/nova4899r/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/intel/d945gclf/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/d945gclf/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -66,7 +66,7 @@
 } __attribute__((packed)) acpi_oemb_t;
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 #if OLD_ACPI
 static void acpi_create_oemb(acpi_oemb_t *oemb)

Modified: trunk/src/mainboard/intel/d945gclf/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/d945gclf/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/acpi.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"

Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/jarrell/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,8 +27,8 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/truxton/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,8 +28,8 @@
 #include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/xe7501devkit/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
+#include "southbridge/intel/i82801cx/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/debug.c"

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,7 +31,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 #include <lib.h>
 #include <spd.h>

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -48,8 +48,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #if CONFIG_TTYS0_BASE == 0x2f8
@@ -75,7 +75,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,8 +45,8 @@
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/lanner/em8510/romstage.c
==============================================================================
--- trunk/src/mainboard/lanner/em8510/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lanner/em8510/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,8 +11,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
-#include "southbridge/amd/cs5535/cs5535_early_setup.c"
+#include "southbridge/amd/cs5535/early_smbus.c"
+#include "southbridge/amd/cs5535/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum. */

Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/literunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/literunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */

Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 #define ManualConf 1		/* No automatic strapped PLL config */

Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -50,7 +50,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
@@ -78,8 +78,8 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -46,7 +46,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,7 +32,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include <spd.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <device/pci_ids.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -82,7 +82,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
 
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
@@ -91,7 +91,7 @@
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -72,8 +72,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -17,7 +17,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -28,7 +28,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -37,7 +37,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -77,8 +77,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.

Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix2d/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/pcengines/alix2d/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.
  *

Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/rca/rm4100/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,12 +32,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 

Modified: trunk/src/mainboard/roda/rk886ex/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/roda/rk886ex/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -91,7 +91,7 @@
 }
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/roda/rk886ex/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/roda/rk886ex/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -127,8 +127,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -68,8 +68,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -64,8 +64,8 @@
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -70,8 +70,8 @@
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/televideo/tc7020/romstage.c
==============================================================================
--- trunk/src/mainboard/televideo/tc7020/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/televideo/tc7020/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,12 +33,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 

Modified: trunk/src/mainboard/traverse/geos/romstage.c
==============================================================================
--- trunk/src/mainboard/traverse/geos/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/traverse/geos/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,8 +32,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2735/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "northbridge/intel/e7501/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"

Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2850/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2875/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2880/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -39,8 +39,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2892/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -38,7 +38,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -47,7 +47,7 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -37,7 +37,7 @@
 #include <spd.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -77,8 +77,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -73,8 +73,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s4882/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-cn/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,8 +32,8 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 #include <spd.h>
 
 static inline int spd_read_byte(unsigned device, unsigned address)

Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-m/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -14,8 +14,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8235/vt8235_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8235/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-n/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #include <spd.h>
 

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,9 +12,9 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8231/vt8231_early_smbus.c"
-#include "southbridge/via/vt8231/vt8231_early_serial.c"
-#include "southbridge/via/vt8231/vt8231_enable_rom.c"
+#include "southbridge/via/vt8231/early_smbus.c"
+#include "southbridge/via/vt8231/early_serial.c"
+#include "southbridge/via/vt8231/enable_rom.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/pc2500e/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,7 +32,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include <spd.h>
 

Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/winent/pl6064/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,8 +33,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/wyse/s50/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/southbridge/amd/amd8111/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8111/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8111/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,11 +1,11 @@
 driver-y += amd8111.c
-driver-y += amd8111_usb.c
-driver-y += amd8111_lpc.c
-driver-y += amd8111_ide.c
-driver-y += amd8111_acpi.c
-driver-y += amd8111_usb2.c
-driver-y += amd8111_ac97.c
-driver-y += amd8111_nic.c
-driver-y += amd8111_pci.c
-driver-y += amd8111_smbus.c
-ramstage-y += amd8111_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += acpi.c
+driver-y += usb2.c
+driver-y += ac97.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += smbus.c
+ramstage-y += reset.c

Copied: trunk/src/southbridge/amd/amd8111/ac97.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c)
@@ -0,0 +1,52 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x2c,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ac97audio_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = amd8111_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97audio_driver __pci_driver = {
+	.ops    = &ac97audio_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x746D,
+};
+
+
+static struct device_operations ac97modem_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = amd8111_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97modem_driver __pci_driver = {
+	.ops    = &ac97modem_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x746E,
+};

Copied: trunk/src/southbridge/amd/amd8111/acpi.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/acpi.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c)
@@ -0,0 +1,220 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include "amd8111.h"
+#include "amd8111_smbus.h"
+
+#define PREVIOUS_POWER_STATE 0x43
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define SLOW_CPU_OFF 0
+#define SLOW_CPU__ON 1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+
+static int lsmbus_recv_byte(device_t dev)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_recv_byte(res->base, device);
+}
+
+static int lsmbus_send_byte(device_t dev, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_send_byte(res->base, device, val);
+}
+
+
+static int lsmbus_read_byte(device_t dev, uint8_t address)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_read_byte(res->base, device, address);
+}
+
+static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_write_byte(res->base, device, address, val);
+}
+
+#if CONFIG_GENERATE_ACPI_TABLES == 1
+unsigned pm_base;
+#endif
+
+static void acpi_init(struct device *dev)
+{
+	uint8_t byte;
+	uint16_t pm10_bar;
+	uint32_t dword;
+	int on;
+
+#if 0
+	uint16_t word;
+	printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
+	byte = pci_read_config8(dev, 0x49);
+	pci_write_config8(dev, 0x49, byte | (1<<2));
+
+
+	byte = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
+
+	/* added from sourceforge */
+	byte = pci_read_config8(dev, 0x48);
+	pci_write_config8(dev, 0x48, byte | (1<<3));
+
+	printk(BIOS_DEBUG, "done.\n");
+
+
+	printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
+	word = pci_read_config16(dev, 0x46);
+	pci_write_config16(dev, 0x46, word | (1<<9));
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+	/* To enable the register 0xcf9 in the IO space
+	 * bit [D5] is set in the amd8111 configuration register.
+	 * The config. reg. is devBx41.  Register 0xcf9 allows
+	 * hard reset capability to the system.  For the ACPI
+	 * reset.reg values in fadt.c to work this register
+	 * must be enabled.
+	 */
+	byte = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
+
+	/* power on after power fail */
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	get_option(&on, "power_on_after_fail");
+	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
+	byte &= ~0x40;
+	if (!on) {
+		byte |= 0x40;
+	}
+	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
+
+	/* switch serial irq logic from quiet mode to continuous
+	 * mode for Winbond W83627HF Rev. 17
+	 */
+	byte = pci_read_config8(dev, 0x4a);
+	pci_write_config8(dev, 0x4a, byte | (1<<6));
+
+	/* Throttle the CPU speed down for testing */
+	on = SLOW_CPU_OFF;
+	get_option(&on, "slow_cpu");
+	if(on) {
+		pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
+		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
+		dword = inl(pm10_bar + 0x10);
+		on = 8-on;
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
+				(on*12)+(on>>1),(on&1)*5);
+	}
+
+#if CONFIG_GENERATE_ACPI_TABLES == 1
+	pm_base = pci_read_config16(dev, 0x58) & 0xff00;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
+#endif
+
+}
+
+static void acpi_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Handle the generic bars */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI/SMBUS bar */
+	resource = new_resource(dev, 0x58);
+	resource->base  = 0;
+	resource->size  = 256;
+	resource->align = log2(256);
+	resource->gran  = log2(256);
+	resource->limit = 65536;
+	resource->flags = IORESOURCE_IO;
+	resource->index = 0x58;
+}
+
+static void acpi_enable_resources(device_t dev)
+{
+	uint8_t byte;
+	/* Enable the generic pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI/SMBUS Bar */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1 << 7);
+	pci_write_config8(dev, 0x41, byte);
+
+	/* Set the class code */
+	pci_write_config32(dev, 0x60, 0x06800000);
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x7c,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+	.recv_byte  = lsmbus_recv_byte,
+	.send_byte  = lsmbus_send_byte,
+	.read_byte  = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
+};
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations acpi_ops  = {
+	.read_resources   = acpi_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = acpi_enable_resources,
+	.init             = acpi_init,
+	.scan_bus         = scan_static_bus,
+	/*  We don't need amd8111_enable, chip ops takes care of it.
+	 *  It could be useful if these devices were not
+	 *  enabled by default.
+	 */
+//	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+	.ops_smbus_bus    = &lops_smbus_bus,
+};
+
+static const struct pci_driver acpi_driver __pci_driver = {
+	.ops    = &acpi_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_ACPI,
+};
+

Modified: trunk/src/southbridge/amd/amd8111/bootblock.c
==============================================================================
--- trunk/src/southbridge/amd/amd8111/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8111/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "southbridge/amd/amd8111/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/amd/amd8111/early_ctrl.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/early_ctrl.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c)
@@ -0,0 +1,83 @@
+#include "amd8111.h"
+#include <reset.h>
+
+/* by yhlu 2005.10 */
+static unsigned get_sbdn(unsigned bus)
+{
+        device_t dev;
+
+        /* Find the device.
+         * There can only be one 8111 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
+{
+	device_t dev;
+	uint8_t byte;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
+	/* enable cf9 */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1<<6) | (1<<5);
+	pci_write_config8(dev, 0x41, byte);
+}
+
+static void enable_cf9(void)
+{
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	enable_cf9_x(sbbusn, sbdn);
+}
+
+void hard_reset(void)
+{
+        set_bios_reset();
+        /* reset */
+        enable_cf9();
+        outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+}
+
+void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+        device_t dev;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
+
+        pci_write_config8(dev, 0x74, 4);
+
+        /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+        pci_write_config32(dev, 0x70, 2<<12);
+
+}
+
+static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
+{
+        device_t dev;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
+
+        /* Reset */
+        set_bios_reset();
+        pci_write_config8(dev, 0x47, 1);
+
+}
+
+void soft_reset(void)
+{
+
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	return soft_reset_x(sbbusn, sbdn);
+
+}

Copied: trunk/src/southbridge/amd/amd8111/early_smbus.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c)
@@ -0,0 +1,48 @@
+#include "amd8111_smbus.h"
+
+#define SMBUS_IO_BASE 0x0f00
+
+static void enable_smbus(void)
+{
+	device_t dev;
+	uint8_t enable;
+
+	dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\n");
+	}
+
+	pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
+	enable = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, enable | (1 << 7));
+
+	/* check that we can see the smbus controller I/O. */
+	if (inw(SMBUS_IO_BASE)==0xFF){
+		die("SMBUS controller I/O not found\n");
+	}
+
+	/* clear any lingering errors, so the transaction will run */
+	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
+	print_spew("SMBus controller enabled\n");
+}
+
+static inline int smbus_recv_byte(unsigned device)
+{
+	return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+}
+
+static inline int smbus_send_byte(unsigned device, unsigned char val)
+{
+	return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+}
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+}
+

Copied: trunk/src/southbridge/amd/amd8111/enable_rom.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
+static void amd8111_enable_rom(void)
+{
+	u8 byte;
+	device_t dev;
+
+	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
+					  PCI_DEVICE_ID_AMD_8111_ISA), 0);
+
+	/* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
+
+	/* Set the 5MB enable bits. */
+	byte = pci_io_read_config8(dev, 0x43);
+	byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
+	byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
+	pci_io_write_config8(dev, 0x43, byte);
+}

Copied: trunk/src/southbridge/amd/amd8111/ide.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c)
@@ -0,0 +1,66 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	uint16_t word;
+	uint8_t byte;
+	conf = dev->chip_info;
+
+	word = pci_read_config16(dev, 0x40);
+	/* Ensure prefetch is disabled */
+	word &= ~((1 << 15) | (1 << 13));
+	if (conf->ide1_enable) {
+		/* Enable secondary ide interface */
+		word |= (1<<0);
+		printk(BIOS_DEBUG, "IDE1 ");
+	}
+	if (conf->ide0_enable) {
+		/* Enable primary ide interface */
+		word |= (1<<1);
+		printk(BIOS_DEBUG, "IDE0 ");
+	}
+
+	word |= (1<<12);
+	word |= (1<<14);
+
+	pci_write_config16(dev, 0x40, word);
+
+
+        byte = 0x20 ; // Latency: 64-->32
+        pci_write_config8(dev, 0xd, byte);
+
+	word = 0x0f;
+	pci_write_config16(dev, 0x42, word);
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_IDE,
+};
+

Copied: trunk/src/southbridge/amd/amd8111/lpc.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c)
@@ -0,0 +1,133 @@
+/*
+ * (C) 2003 Linux Networx, SuSE Linux AG
+ *  2006.1 yhlu add dest apicid for IRQ0
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
+#include <stdlib.h>
+#include "amd8111.h"
+
+#define NMI_OFF 0
+
+static void enable_hpet(struct device *dev)
+{
+	unsigned long hpet_address;
+
+	pci_write_config32(dev,0xa0, 0xfed00001);
+	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
+
+}
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	int nmi_option;
+
+	/* IO APIC initialization */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1;
+	pci_write_config8(dev, 0x4B, byte);
+	/* Don't rename IO APIC */
+	setup_ioapic(IO_APIC_ADDR, 0);
+
+	/* posted memory write enable */
+	byte = pci_read_config8(dev, 0x46);
+	pci_write_config8(dev, 0x46, byte | (1<<0));
+
+	/* Enable 5Mib Rom window */
+	byte = pci_read_config8(dev, 0x43);
+	byte |= 0xc0;
+	pci_write_config8(dev, 0x43, byte);
+
+	/* Enable Port 92 fast reset */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1 << 5);
+	pci_write_config8(dev, 0x41, byte);
+
+	/* Enable Error reporting */
+	/* Set up sync flood detected */
+	byte = pci_read_config8(dev, 0x47);
+	byte |= (1 << 1);
+	pci_write_config8(dev, 0x47, byte);
+
+	/* Set up NMI on errors */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 1); /* clear PW2LPC error */
+	byte |= (1 << 6); /* clear LPCERR */
+	pci_write_config8(dev, 0x40, byte);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte |= (1 << 7); /* set NMI */
+		pci_write_config8(dev, 0x40, byte);
+	}
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers */
+	enable_hpet(dev);
+}
+
+static void amd8111_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = amd8111_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_ISA,
+};

Copied: trunk/src/southbridge/amd/amd8111/nic.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c)
@@ -0,0 +1,90 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "amd8111.h"
+
+
+#define CMD3		0x54
+
+typedef enum {
+	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
+	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
+	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
+	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+	/* VAL3 */
+	ASF_INIT_DONE_ALIAS	= (1 << 29),
+	/* VAL2 */
+	JUMBO			= (1 << 21),
+	VSIZE			= (1 << 20),
+	VLONLY			= (1 << 19),
+	VL_TAG_DEL		= (1 << 18),
+	/* VAL1 */
+	EN_PMGR			= (1 << 14),
+	INTLEVEL		= (1 << 13),
+	FORCE_FULL_DUPLEX	= (1 << 12),
+	FORCE_LINK_STATUS	= (1 << 11),
+	APEP			= (1 << 10),
+	MPPLBA			= (1 << 9),
+	/* VAL0 */
+	RESET_PHY_PULSE		= (1 << 2),
+	RESET_PHY		= (1 << 1),
+	PHY_RST_POL		= (1 << 0),
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	struct resource *resource;
+	unsigned long mmio;
+
+	conf = dev->chip_info;
+	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+	mmio = resource->base;
+
+	/* Hard Reset PHY */
+	printk(BIOS_DEBUG, "Reseting PHY... ");
+	if (conf->phy_lowreset) {
+		write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
+	} else {
+		write32((mmio + CMD3), VAL0 | RESET_PHY);
+	}
+	mdelay(15);
+	write32((mmio + CMD3), RESET_PHY);
+	printk(BIOS_DEBUG, "Done\n");
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0xc8,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = nic_init,
+	.scan_bus         = 0,
+	.enable		  = amd8111_enable,
+	.ops_pci	  = &lops_pci,
+};
+
+static const struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_NIC,
+};

Copied: trunk/src/southbridge/amd/amd8111/pci.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c)
@@ -0,0 +1,68 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void pci_init(struct device *dev)
+{
+
+	/* Enable pci error detecting */
+	uint32_t dword;
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (7<<28); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/* System,Parity,timer,and abort error enable */
+	dword = pci_read_config32(dev, 0x3c);
+	dword |= (1<<16); /* Parity */
+	dword |= (1<<17); /* System */
+	dword |= (1<<21); /* Master abort */
+//	dword &= ~(1<<21); /* Master abort */
+//	dword |= (1<<27); /* Discard timer */
+	dword &= ~(1<<27); /* Discard timer */
+	dword |= (1<<26); /* DTSTAT error clear  */
+	pci_write_config32(dev, 0x3c, dword);
+
+	/* CRC flood enable */
+	dword = pci_read_config32(dev, 0xc4);
+	dword |= (1<<1); /* CRC Flood enable */
+	dword |= (1<<8); /* Clear any CRC errors */
+	dword |= (1<<4); /* Clear any LKFAIL errors */
+	pci_write_config32(dev, 0xc4, dword);
+
+	/* Clear possible errors */
+	dword = pci_read_config32(dev, 0x1c);
+	dword |= (1<<27); /* STA */
+	dword |= (1<<28); /* RTA */
+	dword |= (1<<29); /* RMA */
+	dword |= (1<<30); /* RSE */
+	dword |= (1<<31); /* DPE */
+	dword |= (1<<24); /* MDPE */
+	pci_write_config32(dev, 0x1c, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	/* PCI Subordinate bus reset is not implemented */
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_PCI,
+};
+

Copied: trunk/src/southbridge/amd/amd8111/reset.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c)
@@ -0,0 +1,76 @@
+#include <arch/io.h>
+#include <reset.h>
+#include <device/pci_ids.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFFF) << 20) | \
+	(((DEV) & 0x1F) << 15) | \
+	(((FN)  & 0x7) << 12))
+
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+typedef unsigned device_t;
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#define PCI_DEV_INVALID (0xffffffffU)
+static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+{
+	device_t dev, last;
+	dev = PCI_DEV(bus, 0, 0);
+	last = PCI_DEV(bus, 31, 7);
+	for(; dev <= last; dev += PCI_DEV(0,0,1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id) {
+			return dev;
+		}
+	}
+	return PCI_DEV_INVALID;
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+
+void hard_reset(void)
+{
+	device_t dev;
+	unsigned bus;
+	unsigned node = 0;
+	unsigned link = get_sblk();
+
+	/* Find the device.
+	 * There can only be one 8111 on a hypertransport chain/bus.
+	 */
+	bus = node_link_to_bus(node, link);
+	dev = pci_locate_device_on_bus(
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
+		bus);
+
+	/* Reset */
+	set_bios_reset();
+	pci_write_config8(dev, 0x47, 1);
+}

Copied: trunk/src/southbridge/amd/amd8111/smbus.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c)
@@ -0,0 +1,41 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <arch/io.h>
+#include "amd8111.h"
+
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x44,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+	/* I haven't seen the 2.0 SMBUS controller used yet. */
+};
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+static struct device_operations smbus_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = scan_static_bus,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+	.ops_smbus_bus    = &lops_smbus_bus,
+};
+
+static const struct pci_driver smbus_driver __pci_driver = {
+	.ops = &smbus_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_SMB,
+};

Copied: trunk/src/southbridge/amd/amd8111/usb.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c)
@@ -0,0 +1,37 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "amd8111.h"
+
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations usb_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = scan_static_bus,
+//	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb_driver __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_USB,
+};

Copied: trunk/src/southbridge/amd/amd8111/usb2.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/usb2.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c)
@@ -0,0 +1,45 @@
+//2003 Copywright Tyan
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+#if 0
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+#endif
+
+static void amd8111_usb2_enable(device_t dev)
+{
+	// Due to buggy USB2 we force it to disable.
+	dev->enabled = 0;
+	amd8111_enable(dev);
+	printk(BIOS_DEBUG, "USB2 disabled.\n");
+}
+
+static struct device_operations usb2_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.enable           = amd8111_usb2_enable,
+	// .ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &usb2_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_USB2,
+};

Copied: trunk/src/southbridge/amd/amd8131-disable/bridge.c (from r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8131-disable/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c)
@@ -0,0 +1,116 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+
+static void amd8131_bus_read_resources(device_t dev)
+{
+	return;
+}
+
+static void amd8131_bus_set_resources(device_t dev)
+{
+#if 0
+	pci_bus_read_resources(dev);
+#endif
+	return;
+}
+
+static void amd8131_bus_enable_resources(device_t dev)
+{
+#if 0
+	pci_dev_set_resources(dev);
+#endif
+	return;
+}
+
+static void amd8131_bus_init(device_t dev)
+{
+#if 0
+	pcix_init(dev);
+#endif
+	return;
+}
+
+static unsigned int amd8131_scan_bus(device_t bus, unsigned int max)
+{
+#if 0
+	max = pcix_scan_bridge(bus, max);
+#endif
+	return max;
+}
+
+static void amd8131_enable(device_t dev)
+{
+	uint32_t buses;
+	uint16_t cr;
+
+	/* Clear all status bits and turn off memory, I/O and master enables. */
+	pci_write_config16(dev, PCI_COMMAND, 0x0000);
+	pci_write_config16(dev, PCI_STATUS, 0xffff);
+
+	/*
+	 * Read the existing primary/secondary/subordinate bus
+	 * number configuration.
+	 */
+	buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+
+	/* Configure the bus numbers for this bridge: the configuration
+	 * transactions will not be propagated by the bridge if it is not
+	 * correctly configured.
+	 */
+	buses &= 0xff000000;
+	buses |= (((unsigned int) (dev->bus->secondary) << 0) |
+		((unsigned int) (dev->bus->secondary) << 8) |
+		((unsigned int) (dev->bus->secondary) << 16));
+	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
+}
+
+static struct device_operations pcix_ops  = {
+        .read_resources   = amd8131_bus_read_resources,
+        .set_resources    = amd8131_bus_set_resources,
+	.enable_resources = amd8131_bus_enable_resources,
+        .init             = amd8131_bus_init,
+	.scan_bus         = 0,
+	.enable           = amd8131_enable,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7450,
+};
+
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = 0,
+	.scan_bus = 0,
+	.enable   = ioapic_enable,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7451,
+
+};

Modified: trunk/src/southbridge/amd/amd8131/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8131/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8131/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8131_bridge.c
+driver-y += bridge.c

Copied: trunk/src/southbridge/amd/amd8131/bridge.c (from r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8131/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c)
@@ -0,0 +1,432 @@
+/*
+ * (C) 2003-2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <device/pcix.h>
+
+#define NMI_OFF 0
+
+#define NPUML 0xD9	/* Non prefetchable upper memory limit */
+#define NPUMB 0xD8	/* Non prefetchable upper memory base */
+
+static void amd8131_walk_children(struct bus *bus,
+	void (*visit)(device_t dev, void *ptr), void *ptr)
+{
+	device_t child;
+	for(child = bus->children; child; child = child->sibling)
+	{
+		if (child->path.type != DEVICE_PATH_PCI) {
+			continue;
+		}
+		if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+			amd8131_walk_children(child->link_list, visit, ptr);
+		}
+		visit(child, ptr);
+	}
+}
+
+struct amd8131_bus_info {
+	unsigned sstatus;
+	unsigned rev;
+	int errata_56;
+	int master_devices;
+	int max_func;
+};
+
+static void amd8131_count_dev(device_t dev, void *ptr)
+{
+	struct amd8131_bus_info *info = ptr;
+	/* Don't count pci bridges */
+	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+		info->master_devices++;
+	}
+	if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
+		info->max_func = PCI_FUNC(dev->path.pci.devfn);
+	}
+}
+
+
+static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
+{
+	struct amd8131_bus_info *info = ptr;
+	unsigned cap;
+	unsigned status, cmd, orig_cmd;
+	unsigned max_read, max_tran;
+	int sib_funcs, sibs;
+	device_t sib;
+
+	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
+		return;
+	}
+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+	if (!cap) {
+		return;
+	}
+	/* How many siblings does this device have? */
+	sibs = info->master_devices - 1;
+	/* Count how many sibling functions this device has */
+	sib_funcs = 0;
+	for(sib = dev->bus->children; sib; sib = sib->sibling) {
+		if (sib == dev) {
+			continue;
+		}
+		if (PCI_SLOT(sib->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) {
+			continue;
+		}
+		sib_funcs++;
+	}
+
+
+	printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev));
+	status = pci_read_config32(dev, cap + PCI_X_STATUS);
+	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
+
+	max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
+	max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
+
+	/* Errata #49 don't allow 4K transactions */
+	if (max_read >= 2) {
+		max_read = 2;
+	}
+
+	/* Errata #37 Limit the number of split transactions to avoid starvation */
+	if (sibs >= 2) {
+		/* At most 2 outstanding split transactions when we have
+		 * 3 or more bus master devices on the bus.
+		 */
+		if (max_tran > 1) {
+			max_tran = 1;
+		}
+	}
+	else if (sibs == 1) {
+		/* At most 4 outstanding split transactions when we have
+		 * 2 bus master devices on the bus.
+		 */
+		if (max_tran > 3) {
+			max_tran = 3;
+		}
+	}
+	else {
+		/* At most 8 outstanding split transactions when we have
+		 * only one bus master device on the bus.
+		 */
+		if (max_tran > 4) {
+			max_tran = 4;
+		}
+	}
+	/* Errata #56 additional limits when the bus runs at 133Mhz */
+	if (info->errata_56 &&
+		(PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))
+	{
+		unsigned limit_read;
+		/* Look at the number of siblings and compute the
+		 * largest legal read size.
+		 */
+		if (sib_funcs == 0) {
+			/* 2k reads */
+			limit_read = 2;
+		}
+		else if (sib_funcs <= 1) {
+			/* 1k reads */
+			limit_read = 1;
+		}
+		else {
+			/* 512 byte reads */
+			limit_read = 0;
+		}
+		if (max_read > limit_read) {
+			max_read = limit_read;
+		}
+		/* Look at the read size and the nubmer of siblings
+		 * and compute how many outstanding transactions I can have.
+		 */
+		if (max_read == 2) {
+			/* 2K reads */
+			if (max_tran > 0) {
+				/* Only 1 outstanding transaction allowed */
+				max_tran = 0;
+			}
+		}
+		else if (max_read == 1) {
+			/* 1K reads */
+			if (max_tran > (1 - sib_funcs)) {
+				/* At most 2 outstanding transactions */
+				max_tran = 1 - sib_funcs;
+			}
+		}
+		else {
+			/* 512 byte reads */
+			max_read = 0;
+			if (max_tran > (2 - sib_funcs)) {
+				/* At most 3 outstanding transactions */
+				max_tran = 2 - sib_funcs;
+			}
+		}
+	}
+#if 0
+	printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
+		dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs);
+#endif
+	if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
+		cmd &= ~PCI_X_CMD_MAX_READ;
+		cmd |= max_read << 2;
+		}
+	if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
+		cmd &= ~PCI_X_CMD_MAX_SPLIT;
+		cmd |= max_tran << 4;
+	}
+
+	/* Don't attempt to handle PCI-X errors */
+	cmd &= ~PCI_X_CMD_DPERR_E;
+	/* The 8131 does not work properly with relax ordering enabled.
+	 * Errata #58
+	 */
+	cmd &= ~PCI_X_CMD_ERO;
+	if (orig_cmd != cmd) {
+		pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+	}
+}
+static unsigned int amd8131_scan_bus(struct bus *bus,
+	unsigned min_devfn, unsigned max_devfn, unsigned int max)
+{
+	struct amd8131_bus_info info;
+	struct bus *pbus;
+	unsigned pos;
+
+
+	/* Find the children on the bus */
+	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+
+	/* Find the revision of the 8131 */
+	info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
+
+	/* See which errata apply */
+	info.errata_56 = info.rev <= 0x12;
+
+	/* Find the pcix capability and get the secondary bus status */
+	pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
+	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
+
+	/* Print the PCI-X bus speed */
+	printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
+
+
+	/* Examine the bus and find out how loaded it is */
+	info.max_func = 0;
+	info.master_devices  = 0;
+	amd8131_walk_children(bus, amd8131_count_dev, &info);
+
+	/* Disable the bus if there are no devices on it or
+	 * we are running at 133Mhz and have a 4 function device.
+	 * see errata #56
+	 */
+	if (!bus->children ||
+		(info.errata_56 &&
+			(info.max_func >= 3) &&
+			(PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)))
+	{
+		unsigned pcix_misc;
+		/* Disable all of my children */
+		disable_children(bus);
+
+		/* Remember the device is disabled */
+		bus->dev->enabled = 0;
+
+		/* Disable the PCI-X clocks */
+		pcix_misc = pci_read_config32(bus->dev, 0x40);
+		pcix_misc &= ~(0x1f << 16);
+		pci_write_config32(bus->dev, 0x40, pcix_misc);
+
+		return max;
+	}
+
+	/* If we are in conventional PCI mode nothing more is necessary.
+	 */
+	if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
+		return max;
+	}
+
+
+	/* Tune the devices on the bus */
+	amd8131_walk_children(bus, amd8131_pcix_tune_dev, &info);
+
+	/* Don't allow the 8131 or any of it's parent busses to
+	 * implement relaxed ordering.  Errata #58
+	 */
+	for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
+		printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
+			bus_path(pbus));
+		pbus->disable_relaxed_ordering = 1;
+	}
+	return max;
+}
+
+static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, amd8131_scan_bus);
+}
+
+
+static void amd8131_pcix_init(device_t dev)
+{
+	uint32_t dword;
+	uint16_t word;
+	uint8_t byte;
+	int nmi_option;
+
+	/* Enable memory write and invalidate ??? */
+	byte = pci_read_config8(dev, 0x04);
+        byte |= 0x10;
+        pci_write_config8(dev, 0x04, byte);
+
+	/* Set drive strength */
+	word = pci_read_config16(dev, 0xe0);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe0, word);
+	word = pci_read_config16(dev, 0xe4);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe4, word);
+
+	/* Set impedance */
+	word = pci_read_config16(dev, 0xe8);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe8, word);
+
+	/* Set discard unrequested prefetch data */
+	/* Errata #51 */
+	word = pci_read_config16(dev, 0x4c);
+        word |= 1;
+        pci_write_config16(dev, 0x4c, word);
+
+	/* Set split transaction limits */
+	word = pci_read_config16(dev, 0xa8);
+        pci_write_config16(dev, 0xaa, word);
+	word = pci_read_config16(dev, 0xac);
+        pci_write_config16(dev, 0xae, word);
+
+	/* Set up error reporting, enable all */
+	/* system error enable */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= (1<<8);
+        pci_write_config32(dev, 0x04, dword);
+
+	/* system and error parity enable */
+	dword = pci_read_config32(dev, 0x3c);
+        dword |= (3<<16);
+        pci_write_config32(dev, 0x3c, dword);
+
+	/* NMI enable */
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if(nmi_option) {
+		dword = pci_read_config32(dev, 0x44);
+        	dword |= (1<<0);
+        	pci_write_config32(dev, 0x44, dword);
+	}
+
+	/* Set up CRC flood enable */
+	dword = pci_read_config32(dev, 0xc0);
+	if(dword) {  /* do device A only */
+		dword = pci_read_config32(dev, 0xc4);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc4, dword);
+		dword = pci_read_config32(dev, 0xc8);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc8, dword);
+	}
+	return;
+}
+
+#define BRIDGE_40_BIT_SUPPORT 0
+#if BRIDGE_40_BIT_SUPPORT
+static void bridge_read_resources(struct device *dev)
+{
+	struct resource *res;
+	pci_bus_read_resources(dev);
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		res->limit = 0xffffffffffULL;
+	}
+}
+
+static void bridge_set_resources(struct device *dev)
+{
+	struct resource *res;
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		resource_t base, end;
+		/* set the memory range */
+		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		res->flags |= IORESOURCE_STORED;
+		base = res->base;
+		end  = resource_end(res);
+		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
+		pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
+		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
+		pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
+
+		report_resource_stored(dev, res, "");
+	}
+	pci_dev_set_resources(dev);
+}
+#endif /* BRIDGE_40_BIT_SUPPORT */
+
+static struct device_operations pcix_ops  = {
+#if BRIDGE_40_BIT_SUPPORT
+        .read_resources   = bridge_read_resources,
+        .set_resources    = bridge_set_resources,
+#else
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_bus_enable_resources,
+        .init             = amd8131_pcix_init,
+        .scan_bus         = amd8131_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7450,
+};
+
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+	.set_subsystem    = pci_dev_set_subsystem,
+};
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = ioapic_enable,
+	.ops_pci          = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7451,
+
+};

Modified: trunk/src/southbridge/amd/amd8132/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8132/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8132/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8132_bridge.c
+driver-y += bridge.c

Copied: trunk/src/southbridge/amd/amd8132/bridge.c (from r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8132/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c)
@@ -0,0 +1,433 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005,2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <device/pcix.h>
+
+#define NMI_OFF 0
+
+#define NPUML 0xD9	/* Non prefetchable upper memory limit */
+#define NPUMB 0xD8	/* Non prefetchable upper memory base */
+
+static void amd8132_walk_children(struct bus *bus,
+	void (*visit)(device_t dev, void *ptr), void *ptr)
+{
+	device_t child;
+	for(child = bus->children; child; child = child->sibling)
+	{
+		if (child->path.type != DEVICE_PATH_PCI) {
+			continue;
+		}
+		if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+			amd8132_walk_children(child->link_list, visit, ptr);
+		}
+		visit(child, ptr);
+	}
+}
+
+struct amd8132_bus_info {
+	unsigned sstatus;
+	unsigned rev;
+	int master_devices;
+	int max_func;
+};
+
+static void amd8132_count_dev(device_t dev, void *ptr)
+{
+	struct amd8132_bus_info *info = ptr;
+	/* Don't count pci bridges */
+	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+		info->master_devices++;
+	}
+	if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
+		info->max_func = PCI_FUNC(dev->path.pci.devfn);
+	}
+}
+
+
+static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
+{
+	struct amd8132_bus_info *info = ptr;
+	unsigned cap;
+	unsigned status, cmd, orig_cmd;
+	unsigned max_read, max_tran;
+	int  sibs;
+
+	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
+		return;
+	}
+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+	if (!cap) {
+		return;
+	}
+	/* How many siblings does this device have? */
+	sibs = info->master_devices - 1;
+
+	printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev));
+	status = pci_read_config32(dev, cap + PCI_X_STATUS);
+	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
+
+	max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
+	max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
+
+	if (info->rev == 0x01) { // only a1 need it
+		/* Errata #53 Limit the number of split transactions to avoid starvation */
+		if (sibs >= 2) {
+			/* At most 2 outstanding split transactions when we have
+			* 3 or more bus master devices on the bus.
+			*/
+			if (max_tran > 1) {
+				max_tran = 1;
+			}
+		}
+		else if (sibs == 1) {
+			/* At most 4 outstanding split transactions when we have
+			* 2 bus master devices on the bus.
+			*/
+			if (max_tran > 3) {
+				max_tran = 3;
+			}
+		}
+		else {
+			/* At most 8 outstanding split transactions when we have
+			* only one bus master device on the bus.
+			*/
+			if (max_tran > 4) {
+				max_tran = 4;
+			}
+		}
+	}
+
+	if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
+		cmd &= ~PCI_X_CMD_MAX_READ;
+		cmd |= max_read << 2;
+		}
+	if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
+		cmd &= ~PCI_X_CMD_MAX_SPLIT;
+		cmd |= max_tran << 4;
+	}
+
+        /* Don't attempt to handle PCI-X errors */
+        cmd &= ~PCI_X_CMD_DPERR_E;
+        if (orig_cmd != cmd) {
+                pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+        }
+
+
+}
+static unsigned int amd8132_scan_bus(struct bus *bus,
+	unsigned min_devfn, unsigned max_devfn, unsigned int max)
+{
+	struct amd8132_bus_info info;
+	unsigned pos;
+
+
+	/* Find the children on the bus */
+	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+
+	/* Find the revision of the 8132 */
+	info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
+
+	/* Find the pcix capability and get the secondary bus status */
+	pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
+	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
+
+	/* Print the PCI-X bus speed */
+	printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
+
+
+	/* Examine the bus and find out how loaded it is */
+	info.max_func = 0;
+	info.master_devices  = 0;
+	amd8132_walk_children(bus, amd8132_count_dev, &info);
+
+#if 0
+	/* Disable the bus if there are no devices on it
+	 */
+	if (!bus->children)
+	{
+		unsigned pcix_misc;
+		/* Disable all of my children */
+		disable_children(bus);
+
+		/* Remember the device is disabled */
+		bus->dev->enabled = 0;
+
+		/* Disable the PCI-X clocks */
+		pcix_misc = pci_read_config32(bus->dev, 0x40);
+		pcix_misc &= ~(0x1f << 16);
+		pci_write_config32(bus->dev, 0x40, pcix_misc);
+
+		return max;
+	}
+#endif
+
+	/* If we are in conventional PCI mode nothing more is necessary.
+	 */
+	if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
+		return max;
+	}
+
+	/* Tune the devices on the bus */
+	amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
+
+	return max;
+}
+
+static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, amd8132_scan_bus);
+}
+
+
+static void amd8132_pcix_init(device_t dev)
+{
+	uint32_t dword;
+	uint8_t byte;
+	unsigned chip_rev;
+
+	/* Find the revision of the 8132 */
+        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+
+	/* Enable memory write and invalidate ??? */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= 0x10;
+	dword &= ~(1<<6); // PERSP Parity Error Response
+        pci_write_config32(dev, 0x04, dword);
+
+	if (chip_rev == 0x01) {
+		/* Errata #37 */
+		byte = pci_read_config8(dev, 0x0c);
+		if(byte == 0x08 )
+			pci_write_config8(dev, 0x0c, 0x10);
+
+#if 0
+		/* Errata #59*/
+		dword = pci_read_config32(dev, 0x40);
+		dword &= ~(1<<31);
+		pci_write_config32(dev, 0x40, dword);
+#endif
+
+	}
+
+	/* Set up error reporting, enable all */
+	/* system error enable */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= (1<<8);
+        pci_write_config32(dev, 0x04, dword);
+
+	/* system and error parity enable */
+	dword = pci_read_config32(dev, 0x3c);
+        dword |= (3<<16);
+        pci_write_config32(dev, 0x3c, dword);
+
+        dword = pci_read_config32(dev, 0x40);
+//        dword &= ~(1<<31); /* WriteChainEnable */
+	dword |= (1<<31);
+	dword |= (1<<7);// must set to 1
+	dword |= (3<<21); //PCIErrorSerrDisable
+        pci_write_config32(dev, 0x40, dword);
+
+        /* EXTARB = 1, COMPAT = 0 */
+        dword = pci_read_config32(dev, 0x48);
+        dword |= (1<<3);
+	dword &= ~(1<<0);
+	dword |= (1<<15); //CLEARPCILOG_L
+	dword |= (1<<19); //PERR FATAL Enable
+	dword |= (1<<22); // SERR FATAL Enable
+	dword |= (1<<23); // LPMARBENABLE
+	dword |= (0x61<<24); //LPMARBCOUNT
+        pci_write_config32(dev, 0x48, dword);
+
+        dword = pci_read_config32(dev, 0x4c);
+        dword |= (1<<6); //intial prefetch for memory read line request
+	dword |= (1<<9); //continuous prefetch Enable for memory read line request
+        pci_write_config32(dev, 0x4c, dword);
+
+
+       /* Disable Single-Bit-Error Correction [30] = 0 */
+        dword = pci_read_config32(dev, 0x70);
+        dword &= ~(1<<30);
+        pci_write_config32(dev, 0x70, dword);
+
+	//link
+        dword = pci_read_config32(dev, 0xd4);
+        dword |= (0x5c<<16);
+        pci_write_config32(dev, 0xd4, dword);
+
+        /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
+        dword = pci_read_config32(dev, 0xdc);
+	dword |= (1<<1) |  (1<<4); // stream disable 1 to 0 , DBLINSRATE
+        dword |= (1<<18)|(1<<26);
+        dword &= ~((3<<16)|(3<<24));
+        pci_write_config32(dev, 0xdc, dword);
+
+	/* Set up CRC flood enable */
+	dword = pci_read_config32(dev, 0xc0);
+	if(dword) {  /* do device A only */
+#if 0
+		dword = pci_read_config32(dev, 0xc4);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc4, dword);
+		dword = pci_read_config32(dev, 0xc8);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc8, dword);
+#endif
+
+	        if (chip_rev == 0x11) {
+        	        /* [18] Clock Gate Enable = 1 */
+                	dword = pci_read_config32(dev, 0xf0);
+	                dword |= 0x00040008;
+        	        pci_write_config32(dev, 0xf0, dword);
+	        }
+
+	}
+	return;
+}
+
+#define BRIDGE_40_BIT_SUPPORT 0
+#if BRIDGE_40_BIT_SUPPORT
+static void bridge_read_resources(struct device *dev)
+{
+	struct resource *res;
+	pci_bus_read_resources(dev);
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		res->limit = 0xffffffffffULL;
+	}
+}
+
+static void bridge_set_resources(struct device *dev)
+{
+	struct resource *res;
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		resource_t base, end;
+		/* set the memory range */
+		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		res->flags |= IORESOURCE_STORED;
+		base = res->base;
+		end  = resource_end(res);
+		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
+		pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
+		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
+		pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
+
+		report_resource_stored(dev, res, "");
+	}
+	pci_dev_set_resources(dev);
+}
+#endif /* BRIDGE_40_BIT_SUPPORT */
+
+static struct device_operations pcix_ops  = {
+#if BRIDGE_40_BIT_SUPPORT
+        .read_resources   = bridge_read_resources,
+        .set_resources    = bridge_set_resources,
+#else
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_bus_enable_resources,
+        .init             = amd8132_pcix_init,
+        .scan_bus         = amd8132_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7458,
+};
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+static void amd8132_ioapic_init(device_t dev)
+{
+        uint32_t dword;
+        unsigned chip_rev;
+
+        /* Find the revision of the 8132 */
+        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+
+        if (chip_rev == 0x01) {
+#if 0
+                /* Errata #43 */
+                dword = pci_read_config32(dev, 0xc8);
+		dword |= (0x3<<23);
+		pci_write_config32(dev, 0xc8, dword);
+#endif
+
+        }
+
+
+        if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+                //for b1 b2
+                /* Errata #73 */
+                dword = pci_read_config32(dev, 0x80);
+                dword |= (0x1f<<5);
+                pci_write_config32(dev, 0x80, dword);
+                dword = pci_read_config32(dev, 0x88);
+                dword |= (0x1f<<5);
+                pci_write_config32(dev, 0x88, dword);
+
+                /* Errata #74 */
+                dword = pci_read_config32(dev, 0x7c);
+                dword &= ~(0x3<<30);
+                dword |= (0x01<<30);
+                pci_write_config32(dev, 0x7c, dword);
+        }
+
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+	.set_subsystem    = pci_dev_set_subsystem,
+};
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = amd8132_ioapic_init,
+	.scan_bus         = 0,
+	.enable           = ioapic_enable,
+	.ops_pci          = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7459,
+
+};

Modified: trunk/src/southbridge/amd/amd8151/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8151/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8151/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8151_agp3.c
+driver-y += agp3.c

Copied: trunk/src/southbridge/amd/amd8151/agp3.c (from r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8151/agp3.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void agp3bridge_init(device_t dev)
+{
+	uint8_t byte;
+
+	/* Enable BM, MEM and IO */
+	byte = pci_read_config32(dev, 0x04);
+	byte |= 0x07;
+	pci_write_config8(dev, 0x04, byte);
+
+	return;
+}
+
+static struct device_operations agp3bridge_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init		  = agp3bridge_init,
+	.scan_bus	  = pci_scan_bridge,
+};
+
+static const struct pci_driver agp3bridge_driver __pci_driver = {
+	.ops    = &agp3bridge_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7455, // AGP Bridge
+};
+
+static void agp3dev_enable(device_t dev)
+{
+	uint32_t value;
+
+	/* AGP enable */
+	value = pci_read_config32(dev, 0xa8);
+	value |= (3<<8)|2; //AGP 8x
+	pci_write_config32(dev, 0xa8, value);
+
+	/* enable BM and MEM */
+	value = pci_read_config32(dev, 0x4);
+	value |= 6;
+	pci_write_config32(dev, 0x4, value);
+#if 0
+	/* FIXME: should we add agp aperture base and size here ?
+	 * or it is done by AGP drivers */
+#endif
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+        .set_subsystem    = pci_dev_set_subsystem,
+};
+
+static struct device_operations agp3dev_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = 0,
+	.scan_bus = 0,
+	.enable   = agp3dev_enable,
+	.ops_pci  = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver agp3dev_driver __pci_driver = {
+	.ops    = &agp3dev_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7454, //AGP Device
+};

Modified: trunk/src/southbridge/amd/cs5530/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5530/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5530/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,7 +19,7 @@
 ##
 
 driver-y += cs5530.c
-driver-y += cs5530_isa.c
-driver-y += cs5530_ide.c
-driver-y += cs5530_vga.c
-driver-y += cs5530_pirq.c
+driver-y += isa.c
+driver-y += ide.c
+driver-y += vga.c
+driver-y += pirq.c

Copied: trunk/src/southbridge/amd/cs5530/enable_rom.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "cs5530.h"
+
+static void cs5530_enable_rom(void)
+{
+	uint8_t reg8;
+
+	/* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */
+	device_t dev = PCI_DEV(0, 0x12, 0);
+
+	/*
+	 * Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
+	 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
+	 *
+	 * Make the ROM write-protected.
+	 */
+	reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG);
+	reg8 |= LOWER_ROM_ADDRESS_RANGE;
+	reg8 |= UPPER_ROM_ADDRESS_RANGE;
+	reg8 &= ~ROM_WRITE_ENABLE;
+	pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
+
+	/* Set positive decode on ROM. */
+	reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
+	reg8 |= BIOS_ROM_POSITIVE_DECODE;
+	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+}

Copied: trunk/src/southbridge/amd/cs5530/ide.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c)
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "cs5530.h"
+
+/**
+ * Initialize the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
+ * enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init(struct device *dev)
+{
+	uint8_t reg8;
+	struct southbridge_amd_cs5530_config *conf = dev->chip_info;
+
+	reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
+
+	/* Enable/disable the primary IDE interface. */
+	if (conf->ide0_enable) {
+		reg8 |= PRIMARY_IDE_ENABLE;
+	} else {
+		reg8 &= ~(PRIMARY_IDE_ENABLE);
+	}
+
+	/* Enable/disable the secondary IDE interface. */
+	if (conf->ide1_enable) {
+		reg8 |= SECONDARY_IDE_ENABLE;
+	} else {
+		reg8 &= ~(SECONDARY_IDE_ENABLE);
+	}
+
+	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
+		    conf->ide0_enable ? "enabled" : "disabled");
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
+		    conf->ide1_enable ? "enabled" : "disabled");
+}
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.enable			= 0,
+	.scan_bus		= scan_static_bus,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor = PCI_VENDOR_ID_CYRIX,
+	.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5530/isa.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/isa.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "cs5530.h"
+
+static void cs5530_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void isa_init(struct device *dev)
+{
+}
+
+static struct device_operations isa_ops = {
+	.read_resources		= cs5530_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.enable			= 0,
+	.scan_bus		= scan_static_bus,
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_CYRIX,
+	.device	= PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+};

Copied: trunk/src/southbridge/amd/cs5530/pirq.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/pirq.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_CYRIX,
+			       PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0);
+
+	if (pdev) {
+		pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0]));
+		pci_write_config8(pdev, 0x5d, (pIntAtoD[3] << 4 | pIntAtoD[2]));
+	}
+}
+#endif

Copied: trunk/src/southbridge/amd/cs5530/vga.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/vga.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c)
@@ -0,0 +1,495 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+/**
+ * @brief Activate the VGA feature in a Geode GX1 based system with one
+ * of five possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA.
+ * Also it is prepared to display a splash screen.
+ *
+ * In a Geode GX1 environment the companion CS5530 is the VGA
+ * interface only. It contains a PLL for pixel clock generation,
+ * DACs to generate the analogue RGB signals, drivers for HSYNC
+ * and VSYNC and drivers for a digital flatpanel.
+ * The graphic feature itself (framebuffer, acceleration unit)
+ * is not part of this device. It is part of the CPU device.
+ * But both depend on each other, we cannot divide them into
+ * different drivers. So this driver is not only a CS5530 driver,
+ * it is also a Geode GX1 chipset graphic driver.
+ */
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <cpu/amd/gx1def.h>
+#include <delay.h>
+
+#if CONFIG_GX1_VIDEO == 1
+/*
+ * Some register descriptions that are no listed in cpu/amd/gx1def.h
+ */
+#define CS5530_DOT_CLK_CONFIG	0x0024
+#define CS5530_DISPLAY_CONFIG	0x0004
+
+#define DC_FB_ST_OFFSET		0x8310	/* framebuffer start offset */
+#define DC_CB_ST_OFFSET		0x8314	/* compression start offset */
+#define DC_CURS_ST_OFFSET	0x8318	/* cursor start offset */
+#define DC_VID_ST_OFFSET	0x8320	/* video start offset */
+#define DC_LINE_DELTA		0x8324	/* fb and cb skip counts */
+#define DC_BUF_SIZE		0x8328	/* fb and cb line size */
+#define DC_H_TIMING_1		0x8330	/* horizontal timing... */
+#define DC_H_TIMING_2		0x8334
+#define DC_H_TIMING_3		0x8338
+#define DC_FP_H_TIMING		0x833C
+#define DC_V_TIMING_1		0x8340	/* vertical timing... */
+#define DC_V_TIMING_2		0x8344
+#define DC_V_TIMING_3		0x8348
+#define DC_FP_V_TIMING		0x834C
+#define DC_TIMING_CFG		0x8308
+#define DC_OUTPUT_CFG		0x830C
+
+/**
+ * what colour depth should be used as default (in bpp)
+ * Note: Currently no other value than 16 is supported
+ */
+#define COLOUR_DEPTH 16
+
+/**
+ * Support for a few basic video modes
+ * Note: all modes only for CRT. The flatpanel feature is
+ * not supported here (due to the lack of hardware to test)
+ */
+struct video_mode {
+	int pixel_clock;		/*<< pixel clock in Hz */
+	unsigned long pll_value;	/*<< pll register value for this clock */
+
+	int visible_pixel;		/*<< visible pixels in one line */
+	int hsync_start;		/*<< start of hsync behind visible pixels */
+	int hsync_end;			/*<< end of hsync behind its start */
+	int line_length;		/*<< whole line length */
+
+	int visible_lines;		/*<< visible lines on screen */
+	int vsync_start;		/*<< vsync start behind last visible line */
+	int vsync_end;			/*<< end of vsync behind its start */
+	int picture_length;		/*<< whole screen length */
+
+	int sync_pol;		/*<< 0: low, 1: high, bit 0 hsync, bit 1 vsync */
+};
+
+/*
+ * values for .sync_pol in struct video_mode
+ */
+#define HSYNC_HIGH_POL 0
+#define HSYNC_LOW_POL 1
+#define VSYNC_HIGH_POL 0
+#define VSYNC_LOW_POL 2
+
+/**
+ * 640x480 @ 72Hz hsync: 37.9kHz
+ * VESA standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
+ */
+static const struct video_mode mode_640x480 = {
+	.pixel_clock = 31500000,
+	.pll_value = 0x33915801,
+
+	.visible_pixel = 640,
+	.hsync_start = 664,
+	.hsync_end = 704,	/* 1.27 us sync length */
+	.line_length = 832,	/* 26.39us */
+
+	.visible_lines = 480,
+	.vsync_start = 489,
+	.vsync_end = 491,
+	.picture_length = 520, /* 13.89ms */
+
+	.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
+};
+
+/**
+ * 800x600 @ 72Hz hsync: 48.1kHz
+ * VESA standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync
+ */
+static const struct video_mode mode_800x600 = {
+	.pixel_clock = 50000000,
+	.pll_value = 0x23088801,
+
+	.visible_pixel = 800,
+	.hsync_start = 856,
+	.hsync_end = 976,
+	.line_length = 1040, /* 20.8us */
+
+	.visible_lines = 600,
+	.vsync_start = 637,
+	.vsync_end = 643,
+	.picture_length = 666, /* 13.89ms */
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * 1024x768 @ 70Hz (VESA) hsync: 56.5kHz
+ * Standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync
+ */
+static const struct video_mode mode_1024x768 = {
+	.pixel_clock = 75000000,
+	.pll_value = 0x37E22801,
+
+	.visible_pixel = 1024,
+	.hsync_start = 1048,
+	.hsync_end = 1184,
+	.line_length = 1328,	/* 17.7us */
+
+	.visible_lines = 768,
+	.vsync_start = 771,
+	.vsync_end = 777,
+	.picture_length = 806,	/* 14.3us */
+
+	.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
+};
+
+/**
+ * 1280x960 @ 60Hz (VESA) hsync: 60.0kHz
+ * Mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync
+ */
+static const struct video_mode mode_1280x960 = {
+	.pixel_clock = 108000000,
+	.pll_value = 0x2710C805,
+
+	.visible_pixel = 1280,
+	.hsync_start = 1376,
+	.hsync_end = 1488,
+	.line_length = 1800,	/* 16.67us */
+
+	.visible_lines = 960,
+	.vsync_start = 961,
+	.vsync_end = 964,
+	.picture_length = 1000,	/* 16.67ms */
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz
+ * Mode for modern 5:4 flat screens
+ * Copied from X11:
+ * ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync
+ */
+static const struct video_mode mode_1280x1024 = {
+	.pixel_clock = 108000000,
+	.pll_value = 0x2710C805,
+
+	.visible_pixel = 1280,
+	.hsync_start = 1328,
+	.hsync_end = 1440,
+	.line_length = 1688,	/* 15.6us */
+
+	.visible_lines = 1024,
+	.vsync_start = 1025,
+	.vsync_end = 1028,
+	.picture_length = 1066,
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * List of supported common modes
+ */
+static const struct video_mode *modes[] = {
+	&mode_640x480,	/* CONFIG_GX1_VIDEOMODE = 0 */
+	&mode_800x600,	/* CONFIG_GX1_VIDEOMODE = 1 */
+	&mode_1024x768,	/* CONFIG_GX1_VIDEOMODE = 2 */
+	&mode_1280x960,	/* CONFIG_GX1_VIDEOMODE = 3 */
+	&mode_1280x1024	/* CONFIG_GX1_VIDEOMODE = 4 */
+};
+
+/* make a sanity check at buildtime */
+#if CONFIG_GX1_VIDEOMODE > 4
+# error Requested video mode is unknown!
+#endif
+
+/**
+ * Setup the pixel PLL in the companion chip
+ * @param[in] base register's base address
+ * @param[in] pll_val pll register value to be set
+ *
+ * The PLL to program here is located in the CS5530
+ */
+static void cs5530_set_clock_frequency(u32 io_base, unsigned long pll_val)
+{
+	unsigned long reg;
+
+	/* disable the PLL first, reset and power it down */
+	reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
+	reg |= 0x80000100;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* write the new PLL setting */
+	reg |= (pll_val & ~0x80000920);
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	mdelay(1);	/* wait for control voltage to be 0V */
+
+	/* enable the PLL */
+	reg |= 0x00000800;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* clear reset */
+	reg &= ~0x80000000;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* clear bypass */
+	reg &= ~0x00000100;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+}
+
+/**
+ * Setup memory layout
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Memory layout must be setup in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers.
+ * Note: Using compressed buffer is not supported yet!
+ * (makes more sense later, but not while booting)
+ *
+ * At this point a check is missed if the requested video
+ * mode is possible with the provided video memory.
+ * Check if symbol CONFIG_VIDEO_MB is at least:
+ * - 1 (=1MiB) for VGA and SVGA
+ * - 2 (=2MiB) for XGA
+ * - 4 (=4MiB) for SXGA
+ */
+static void dc_setup_layout(u32 gx_base, const struct video_mode *mode)
+{
+	u32 base = 0x00000000;
+
+	write32(gx_base + DC_FB_ST_OFFSET, base);
+
+	base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines;
+
+	write32(gx_base + DC_CB_ST_OFFSET, base);
+	write32(gx_base + DC_CURS_ST_OFFSET, base);
+	write32(gx_base + DC_VID_ST_OFFSET, base);
+	write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2);
+	write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3);
+}
+
+/**
+ * Setup the HSYNC/VSYNC, active video timing
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Sync signal generation is done in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers
+ *
+ * |<------------------------- htotal ----------------------------->|
+ * |<------------ hactive -------------->|                          |
+ * |                       hblankstart-->|                          |
+ * |                                                    hblankend-->|
+ * |                                hsyncstart-->|                  |
+ * |                                           hsyncend-->|         |
+ * |#####################################___________________________| RGB data
+ * |______________________________________________---------_________| HSYNC
+ *
+ * |<------------------------- vtotal ----------------------------->|
+ * |<------------ vactive -------------->|                          |
+ * |                       vblankstart-->|                          |
+ * |                                                    vblankend-->|
+ * |                                vsyncstart-->|                  |
+ * |                                           vsyncend-->|         |
+ * |#####################################___________________________| line data
+ * |______________________________________________---------_________| YSYNC
+ */
+static void dc_setup_timing(u32 gx_base, const struct video_mode *mode)
+{
+	u32 hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
+	u32 vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
+
+	hactive = mode->visible_pixel & 0x7FF;
+	hblankstart = hactive;
+	hsyncstart = mode->hsync_start & 0x7FF;
+	hsyncend =  mode->hsync_end & 0x7FF;
+	hblankend = mode->line_length & 0x7FF;
+	htotal = hblankend;
+
+	vactive = mode->visible_lines & 0x7FF;
+	vblankstart = vactive;
+	vsyncstart = mode->vsync_start & 0x7FF;
+	vsyncend =  mode->vsync_end & 0x7FF;
+	vblankend = mode->picture_length & 0x7FF;
+	vtotal = vblankend;
+
+	/* row description */
+	write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16));
+	/* horizontal blank description */
+	write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16));
+	/* horizontal sync description */
+	write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16));
+	write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16));
+
+	/* line description */
+	write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16));
+	/* vertical blank description */
+	write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16));
+	/* vertical sync description */
+	write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16));
+	write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16));
+}
+
+/**
+ * Setup required internals to bring the mode up and running
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Must be setup in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers.
+ */
+static void cs5530_activate_mode(u32 gx_base, const struct video_mode *mode)
+{
+	write32(gx_base + DC_GENERAL_CFG, 0x00000080);
+	mdelay(1);
+	dc_setup_layout(gx_base,mode);
+	dc_setup_timing(gx_base,mode);
+
+	write32(gx_base + DC_GENERAL_CFG, 0x2000C581);
+	write32(gx_base + DC_TIMING_CFG, 0x0000002F);
+	write32(gx_base + DC_OUTPUT_CFG, 0x00003004);
+}
+
+/**
+ * Activate the current mode to be "visible" outside
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * As we now activate the interface this must be done
+ * in the CS5530
+ */
+static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
+{
+	u32 val;
+
+	val = (u32)mode->sync_pol << 8;
+	write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
+}
+
+#if CONFIG_SPLASH_GRAPHIC == 1
+
+/*
+ * This bitmap file must provide:
+ * int width: pixel count in one line
+ * int height: line count
+ * int colours: ount of used colour
+ * unsigned long colour_map[]: RGB 565 colours to be used
+ * unsigned char bitmap[]: index per pixel into colour_map[], width*height pixels
+ */
+#include "bitmap.c"
+
+/*
+ * show a boot splash screen in the right lower corner of the screen
+ * swidth: screen width in pixel
+ * sheight: screen height in lines
+ * pitch: line pitch in bytes
+ * base: screen base address
+ *
+ * This routine assumes we are using a 16 bit colour depth!
+ */
+static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base)
+{
+	int word_count,i;
+	unsigned short *adr;
+	u32 xstart,ystart,x,y;
+	/*
+	 * fill the screen with the colour of the
+	 * left top pixel in the graphic
+	 */
+	word_count = pitch * sheight;
+	adr = (unsigned short*)base;
+	for (i = 0; i < word_count; i++, adr++)
+		*adr = colour_map[bitmap[0]];
+
+	/*
+	 * paint the splash
+	 */
+	xstart = swidth-width;
+	ystart = sheight-height;
+	for (y = 0; y < height; y++) {
+		adr=(unsigned short*)(base + pitch*(y+ystart) + 2 * xstart);
+		for (x = 0; x < width; x++) {
+			*adr=(unsigned short)colour_map[(int)bitmap[x + y * width]];
+			adr++;
+		}
+	}
+}
+#else
+# define show_boot_splash_16(w, x, y , z)
+#endif
+
+/**
+ * coreboot management part
+ * @param[in] dev Info about the PCI device to initialise
+ */
+static void cs5530_vga_init(device_t dev)
+{
+	const struct video_mode *mode;
+	u32 io_base, gx_base;
+
+	io_base = pci_read_config32(dev, 0x10);
+	gx_base = GX_BASE;
+	mode = modes[CONFIG_GX1_VIDEOMODE];
+
+	printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n",
+		mode->visible_pixel, mode->visible_lines, mode->pixel_clock);
+
+	cs5530_set_clock_frequency(io_base, mode->pll_value);
+
+	write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC);
+
+	show_boot_splash_16(mode->visible_pixel, mode->visible_lines,
+		mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000));
+
+	cs5530_activate_mode(gx_base, mode);
+
+	cs5530_activate_video(io_base, mode);
+	write32(gx_base + DC_UNLOCK, 0x00000000);
+}
+
+static struct device_operations vga_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = cs5530_vga_init,
+	.enable           = NULL, /* not required */
+};
+
+static const struct pci_driver vga_pci_driver __pci_driver = {
+	.ops 	= &vga_ops,
+	.vendor = PCI_VENDOR_ID_CYRIX,
+	.device = PCI_DEVICE_ID_CYRIX_5530_VIDEO,
+};
+
+#endif /* #if CONFIG_GX1_VIDEO == 1 */

Modified: trunk/src/southbridge/amd/cs5535/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5535/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5535/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
 driver-y += cs5535.c
-#driver-y += cs5535_pci.c
-#driver-y += cs5535_ide.c
+#driver-y += pci.c
+#driver-y += ide.c
 ramstage-y += chipsetinit.c

Copied: trunk/src/southbridge/amd/cs5535/early_setup.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c)
@@ -0,0 +1,149 @@
+/*
+ *
+ * cs5535_early_setup.c:	Early chipset initialization for CS5535 companion device
+ *
+ *
+ * This file implements the initialization sequence documented in section 4.2 of
+ * AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
+ *
+ */
+
+/**
+ * @brief Setup PCI IDSEL for CS5535
+ *
+ *
+ */
+
+static void cs5535_setup_extmsr(void)
+{
+	msr_t msr;
+
+	/* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
+	msr.hi = msr.lo = 0x00000000;
+#if CS5535_GLINK_PORT_NUM <= 4
+	msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
+#else
+	msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
+#endif
+	wrmsr(0x5000201e, msr);
+}
+
+static void cs5535_setup_idsel(void)
+{
+	/* write IDSEL to the write once register at address 0x0000 */
+	outl(0x1 << (CS5535_DEV_NUM + 10), 0);
+}
+
+static void cs5535_usb_swapsif(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(0x51600005);
+	//USB Serial short detect bit.
+	if (msr.hi & 0x10) {
+		/* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
+		 * SERSHRT error bit */
+		msr.hi &= 0xFFFFFFFB;
+		wrmsr(0x51600005, msr);
+	}
+}
+
+static void cs5535_setup_iobase(void)
+{
+	msr_t msr;
+	/* setup LBAR for SMBus controller */
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
+	/* setup LBAR for GPIO */
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
+	/* setup LBAR for MFGPT */
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
+
+	/* setup LBAR for ACPI */
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
+
+	/* setup LBAR for PM Support */
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
+}
+
+static void cs5535_setup_gpio(void)
+{
+	uint32_t val;
+
+	/* setup GPIO pins 14/15 for SDA/SCL */
+	val = (1<<14 | 1<<15);
+	/* Output Enable */
+	outl(0x3fffc000, 0x6100 + 0x04);
+	//outl(val, 0x6100 + 0x04);
+	/* Output AUX1 */
+	outl(0x3fffc000, 0x6100 + 0x10);
+	//outl(val, 0x6100 + 0x10);
+	/* Input Enable */
+	//outl(0x0f5af0a5, 0x6100 + 0x20);
+	outl(0x3fffc000, 0x6100 + 0x20);
+	//outl(val, 0x6100 + 0x20);
+	/* Input AUX1 */
+	//outl(0x3ffbc004, 0x6100 + 0x34);
+	outl(0x3fffc000, 0x6100 + 0x34);
+	//outl(val, 0x6100 + 0x34);
+}
+
+void cs5535_disable_internal_uart(void)
+{
+}
+
+static void cs5535_setup_cis_mode(void)
+{
+	msr_t msr;
+
+	/* setup CPU interface serial to mode C on both sides */
+	msr = rdmsr(GLPCI_SB_CTRL);
+	msr.lo &= ~0x18;
+	msr.lo |= 0x10;
+	wrmsr(GLPCI_SB_CTRL, msr);
+	//Only do this if we are building for 5535
+	msr.lo = 0x2;
+	msr.hi = 0x0;
+	wrmsr(VIP_GIO_MSR_SEL, msr);
+}
+
+static void dummy(void)
+{
+}
+
+static void cs5535_early_setup(void)
+{
+	msr_t msr;
+
+	cs5535_setup_extmsr();
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	if (msr.lo & (0x3f << 26)) {
+		/* PLL is already set and we are reboot from PLL reset */
+		print_debug("reboot from BIOS reset\n");
+		return;
+	}
+	print_debug("Setup idsel\n");
+	cs5535_setup_idsel();
+	print_debug("Setup iobase\n");
+	cs5535_usb_swapsif();
+	cs5535_setup_iobase();
+	print_debug("Setup gpio\n");
+	cs5535_setup_gpio();
+	print_debug("Setup cis_mode\n");
+	cs5535_setup_cis_mode();
+	print_debug("Setup smbus\n");
+	cs5535_enable_smbus();
+	dummy();
+}

Copied and modified: trunk/src/southbridge/amd/cs5535/early_smbus.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/cs5535/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "cs5535_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x6000
 

Copied: trunk/src/southbridge/amd/cs5535/ide.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c)
@@ -0,0 +1,30 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "cs5535.h"
+
+static void ide_init(struct device *dev)
+{
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
+}
+
+static void ide_enable(struct device *dev)
+{
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.enable           = ide_enable,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops 	= &ide_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_CS5535_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5535/smbus.h (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h)
@@ -0,0 +1,46 @@
+//#include <device/smbus_def.h>
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+
+#define	SMB_SDA		0x00
+#define SMB_STS		0x01
+#define SMB_CTRL_STS	0x02
+#define	SMB_CTRL1	0x03
+#define SMB_ADD		0x04
+#define SMB_CTRL2	0x05
+#define	SMB_CTRL3	0x06
+
+#define SMB_STS_SLVSTP	(0x01 << 7)
+#define SMB_STS_SDAST	(0x01 << 6)
+#define	SMB_STS_BER	(0x01 << 5)
+#define SMB_STS_NEGACK	(0x01 << 4)
+#define	SMB_STS_STASTR	(0x01 << 3)
+#define SMB_STS_NMATCH	(0x01 << 2)
+#define	SMB_STS_MASTER	(0x01 << 1)
+#define SMB_STS_XMIT	(0x01 << 0)
+
+#define	SMB_CSTS_TGSCL	(0x01 << 5)
+#define SMB_CSTS_TSDA	(0x01 << 4)
+#define	SMB_CSTS_GCMTCH	(0x01 << 3)
+#define SMB_CSTS_MATCH	(0x01 << 2)
+#define	SMB_CSTS_BB	(0x01 << 1)
+#define SMB_CSTS_BUSY	(0x01 << 0)
+
+#define	SMB_CTRL1_STASTRE (0x01 << 7)
+#define SMB_CTRL1_NMINTE  (0x01 << 6)
+#define	SMB_CTRL1_GCMEN   (0x01 << 5)
+#define SMB_CTRL1_ACK     (0x01 << 4)
+#define	SMB_CTRL1_RSVD    (0x01 << 3)
+#define SMB_CTRL1_INTEN   (0x01 << 2)
+#define	SMB_CTRL1_STOP    (0x01 << 1)
+#define SMB_CTRL1_START   (0x01 << 0)
+
+#define	SMB_ADD_SAEN	  (0x01 << 7)
+
+#define	SMB_CTRL2_ENABLE  0x01
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0xfbff
+
+#define SMBUS_IO_BASE 0x6000

Modified: trunk/src/southbridge/amd/cs5536/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5536/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5536/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,5 +18,5 @@
 ##
 
 driver-y += cs5536.c
-driver-y += cs5536_ide.c
-driver-y += cs5536_pirq.c
+driver-y += ide.c
+driver-y += pirq.c

Copied: trunk/src/southbridge/amd/cs5536/early_setup.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c)
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * cs5536_early_setup.c:	Early chipset initialization for CS5536 companion device
+ *	This file implements the initialization sequence documented in section 4.2 of
+ *	AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
+ */
+
+/**
+ * @brief Setup PCI IDSEL for CS5536
+ */
+static void cs5536_setup_extmsr(void)
+{
+	msr_t msr;
+
+	/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
+	msr.hi = msr.lo = 0x00000000;
+#if CS5536_GLINK_PORT_NUM <= 4
+	msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
+#else
+	msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
+#endif
+	wrmsr(GLPCI_ExtMSR, msr);
+}
+
+static void cs5536_setup_idsel(void)
+{
+	/* write IDSEL to the write once register at address 0x0000 */
+	outl(0x1 << (CS5536_DEV_NUM + 10), 0);
+}
+
+static void cs5536_usb_swapsif(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
+	//USB Serial short detect bit.
+	if (msr.hi & 0x10) {
+		/* We need to preserve bits 32,33,35 and not clear any BIST
+		 * error, but clear the SERSHRT error bit */
+
+		msr.hi &= 0xFFFFFFFB;
+		wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
+	}
+}
+
+static void cs5536_setup_iobase(void)
+{
+	msr_t msr;
+	/* setup LBAR for SMBus controller */
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
+	/* setup LBAR for GPIO */
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
+	/* setup LBAR for MFGPT */
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
+
+	/* setup LBAR for ACPI */
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
+
+	/* setup LBAR for PM Support */
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
+}
+
+static void cs5536_setup_power_button(void)
+{
+#if CONFIG_ENABLE_POWER_BUTTON
+	outl(0x40020000, PMS_IO_BASE + 0x40);
+#endif
+
+	/* setup WORK_AUX/GPIO24, it is the external signal for 5536
+	 * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
+	 * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
+	 * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
+	 */
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+
+}
+
+static void cs5536_setup_gpio(void)
+{
+	uint32_t val;
+
+	/* setup GPIO pins 14/15 for SDA/SCL */
+	val = GPIOL_15_SET | GPIOL_14_SET;
+	/* Output Enable */
+	outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* Output AUX1 */
+	outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Input Enable */
+	outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+	/* Input AUX1 */
+	outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+}
+
+void cs5536_disable_internal_uart(void)
+{
+	msr_t msr;
+	/* The UARTs default to enabled.
+	 * Disable and reset them and configure them later. (SIO init)
+	 */
+	msr = rdmsr(MDD_UART1_CONF);
+	msr.lo = 1;		// reset
+	wrmsr(MDD_UART1_CONF, msr);
+	msr.lo = 0;		// disabled
+	wrmsr(MDD_UART1_CONF, msr);
+
+	msr = rdmsr(MDD_UART2_CONF);
+	msr.lo = 1;		// reset
+	wrmsr(MDD_UART2_CONF, msr);
+	msr.lo = 0;		// disabled
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+static void cs5536_setup_cis_mode(void)
+{
+	msr_t msr;
+
+	/* setup CPU interface serial to mode B to match CPU */
+	msr = rdmsr(GLPCI_SB_CTRL);
+	msr.lo &= ~0x18;
+	msr.lo |= 0x10;
+	wrmsr(GLPCI_SB_CTRL, msr);
+}
+
+/**
+ * Enable the on-chip UART.
+ *
+ * See page 412 of the AMD Geode CS5536 Companion Device data book.
+ */
+static void cs5536_setup_onchipuart1(void)
+{
+	msr_t msr;
+
+	/* Setup early for polling only mode.
+	 * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
+	 *        GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
+	 * 2. Enable UART I/O space in MDD.
+	 *        MSR 0x51400014 bit 18:16
+	 * 3. Enable UART controller.
+	 *        MSR 0x5140003A bit 0, 1
+	 */
+
+	/* GPIO8 - UART1_TX */
+	/* Set: Output Enable (0x4) */
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+
+	/* GPIO9 - UART1_RX */
+	/* Set: Input Enable (0x20) */
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select (0x34) */
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set address to 0x3F8. */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x7 << 16;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks)
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* Enable COM1. */
+	wrmsr(MDD_UART1_CONF, msr);
+}
+
+static void cs5536_setup_onchipuart2(void)
+{
+	msr_t msr;
+
+	/* GPIO4 - UART2_TX */
+	/* Set: Output Enable  (0x4) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* GPIO4 - UART2_RX */
+	/* Set: Input Enable   (0x20) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select  (0x34) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set: GPIO 3 + 3 Pull Up  (0x18) */
+	outl(GPIOL_3_SET | GPIOL_4_SET,
+	     GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
+
+	/* set address to 2F8 */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x5 << 20;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* enable COM2 */
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+void cs5536_setup_onchipuart(int uart)
+{
+	switch (uart) {
+	case 1:
+		cs5536_setup_onchipuart1();
+		break;
+	case 2:
+		cs5536_setup_onchipuart2();
+		break;
+	}
+}
+
+
+/* note: you can't do prints in here in most cases,
+ * and we don't want to hang on serial, so they are
+ * commented out
+ */
+static void cs5536_early_setup(void)
+{
+	msr_t msr;
+
+	cs5536_setup_extmsr();
+	cs5536_setup_cis_mode();
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	if (msr.lo & (0x3f << 26)) {
+		/* PLL is already set and we are reboot from PLL reset */
+		//print_debug("reboot from BIOS reset\n");
+		return;
+	}
+	//print_debug("Setup idsel\n");
+	cs5536_setup_idsel();
+	//print_debug("Setup iobase\n");
+	cs5536_usb_swapsif();
+	cs5536_setup_iobase();
+	//print_debug("Setup gpio\n");
+	cs5536_setup_gpio();
+	//print_debug("Setup smbus\n");
+	cs5536_enable_smbus();
+	//print_debug("Setup power button\n");
+	cs5536_setup_power_button();
+}

Copied: trunk/src/southbridge/amd/cs5536/early_smbus.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c)
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "cs5536.h"
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+#define SMBUS_TIMEOUT (1000)
+
+/* initialization for SMBus Controller */
+static void cs5536_enable_smbus(void)
+{
+
+	/* Set SCL freq and enable SMB controller */
+	/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */
+	outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
+
+	/* Setup SMBus host controller address to 0xEF */
+	outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD);
+
+}
+
+static void smbus_delay(void)
+{
+	/* inb(0x80); */
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+	unsigned long loops = SMBUS_TIMEOUT;
+	unsigned char val;
+
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_STS);
+		if ((val & SMB_STS_SDAST) != 0)
+			break;
+		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+			/*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
+			return SMBUS_ERROR;
+		}
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+/* generate a smbus start condition */
+static int smbus_start_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+
+	/* issue a START condition */
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+	/* check for bus conflict */
+	val = inb(smbus_io_base + SMB_STS);
+	if ((val & SMB_STS_BER) != 0)
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	/* check for SDA status */
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_CTRL1);
+		if ((val & SMB_CTRL1_STOP) == 0) {
+			break;
+		}
+		outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_stop_condition(unsigned smbus_io_base)
+{
+	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+	unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+/*	if (state) */
+	outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+/*	else
+		outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+*/
+	return 0;
+}
+
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
+{
+	unsigned char val;
+
+	/* send the slave address */
+	outb(device, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+		/* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
+		return SMBUS_ERROR;
+	}
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+	unsigned char val;
+
+	/* send the command */
+	outb(command, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static unsigned char smbus_get_result(unsigned smbus_io_base)
+{
+	return inb(smbus_io_base + SMB_SDA);
+}
+
+static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+					unsigned char device,
+					unsigned char address)
+{
+	unsigned char error = 0;
+
+	if ((smbus_check_stop_condition(smbus_io_base))) {
+		error = 1;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 2;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
+		error = 3;
+		goto err;
+	}
+
+	smbus_ack(smbus_io_base, 1);
+
+	if ((smbus_send_command(smbus_io_base, address))) {
+		error = 4;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 5;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
+		error = 6;
+		goto err;
+	}
+
+	if ((smbus_stop_condition(smbus_io_base))) {
+		error = 7;
+		goto err;
+	}
+
+	return smbus_get_result(smbus_io_base);
+
+      err:
+	print_debug("SMBUS READ ERROR:");
+	print_debug_hex8(error);
+	print_debug(" device:");
+	print_debug_hex8(device);
+	print_debug("\n");
+	/* stop, clean up the error, and leave */
+	smbus_stop_condition(smbus_io_base);
+	outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
+	outb(0x0, smbus_io_base + SMB_STS);
+	return 0xFF;
+}
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}

Copied: trunk/src/southbridge/amd/cs5536/ide.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "cs5536.h"
+
+#define IDE_CFG	  0x40
+	#define CHANEN  (1L <<  1)
+	#define PWB	(1L << 14)
+	#define CABLE	(1L << 16)
+#define IDE_DTC	  0x48
+#define IDE_CAST  0x4C
+#define IDE_ETC	  0x50
+
+static void ide_init(struct device *dev)
+{
+	uint32_t ide_cfg;
+
+	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
+	/* GPIO and IRQ setup are handled in the main chipset code. */
+
+	// Enable the channel and Post Write Buffer
+	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
+	ide_cfg = pci_read_config32(dev, IDE_CFG);
+	ide_cfg |= CHANEN | PWB;
+	pci_write_config32(dev, IDE_CFG, ide_cfg);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.enable = 0,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5536/pirq.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/pirq.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_AMD,
+			       PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+
+	if (pdev) {
+		pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12
+			| pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));
+	}
+}
+#endif

Copied: trunk/src/southbridge/amd/cs5536/smbus2.h (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/smbus2.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h)
@@ -0,0 +1,317 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+
+#define	SMB_SDA		0x00
+#define SMB_STS		0x01
+#define SMB_CTRL_STS	0x02
+#define	SMB_CTRL1	0x03
+#define SMB_ADD		0x04
+#define SMB_CTRL2	0x05
+#define	SMB_CTRL3	0x06
+
+#define SMB_STS_SLVSTP	(0x01 << 7)
+#define SMB_STS_SDAST	(0x01 << 6)
+#define	SMB_STS_BER	(0x01 << 5)
+#define SMB_STS_NEGACK	(0x01 << 4)
+#define	SMB_STS_STASTR	(0x01 << 3)
+#define SMB_STS_NMATCH	(0x01 << 2)
+#define	SMB_STS_MASTER	(0x01 << 1)
+#define SMB_STS_XMIT	(0x01 << 0)
+
+#define	SMB_CSTS_TGSCL	(0x01 << 5)
+#define SMB_CSTS_TSDA	(0x01 << 4)
+#define	SMB_CSTS_GCMTCH	(0x01 << 3)
+#define SMB_CSTS_MATCH	(0x01 << 2)
+#define	SMB_CSTS_BB	(0x01 << 1)
+#define SMB_CSTS_BUSY	(0x01 << 0)
+
+#define	SMB_CTRL1_STASTRE (0x01 << 7)
+#define SMB_CTRL1_NMINTE  (0x01 << 6)
+#define	SMB_CTRL1_GCMEN   (0x01 << 5)
+#define SMB_CTRL1_ACK     (0x01 << 4)
+#define	SMB_CTRL1_RSVD    (0x01 << 3)
+#define SMB_CTRL1_INTEN   (0x01 << 2)
+#define	SMB_CTRL1_STOP    (0x01 << 1)
+#define SMB_CTRL1_START   (0x01 << 0)
+
+#define	SMB_ADD_SAEN	  (0x01 << 7)
+
+#define	SMB_CTRL2_ENABLE  0x01
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0xfbff
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+	unsigned long loops = SMBUS_TIMEOUT;
+	unsigned char val;
+
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_STS);
+		if ((val & SMB_STS_SDAST) != 0)
+			break;
+		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+			printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val);
+			return SMBUS_ERROR;
+		}
+	} while (--loops);
+
+	outb(0, smbus_io_base + SMB_STS);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_write(unsigned smbus_io_base, unsigned char byte)
+{
+
+	outb(byte, smbus_io_base + SMB_SDA);
+	return smbus_wait(smbus_io_base);
+}
+
+/* generate a smbus start condition */
+static int smbus_start_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+
+	/* issue a START condition */
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+	/* check for bus conflict */
+	val = inb(smbus_io_base + SMB_STS);
+	if ((val & SMB_STS_BER) != 0)
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	/* check for SDA status */
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_CTRL1);
+		if ((val & SMB_CTRL1_STOP) == 0) {
+			break;
+		}
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Make sure everything is cleared and ready to go */
+
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE),
+	     smbus_io_base + SMB_CTRL1);
+
+	outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR,
+	     smbus_io_base + SMB_STS);
+
+	val = inb(smbus_io_base + SMB_CTRL_STS);
+	outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS);
+}
+
+static int smbus_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+
+	return 0;
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+	unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+	if (state)
+		outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+	else
+		outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+
+	return 0;
+}
+
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
+{
+	unsigned char val;
+
+	/* send the slave address */
+	outb(device, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+		printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val);
+		return SMBUS_ERROR;
+	}
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+	unsigned char val;
+
+	/* send the command */
+	outb(command, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static void _doread(unsigned smbus_io_base, unsigned char device,
+		    unsigned char address, unsigned char *data, int count)
+{
+	int ret;
+	int index = 0;
+	unsigned char val;
+
+	if ((ret = smbus_check_stop_condition(smbus_io_base)))
+		goto err;
+
+	index++;
+
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	index++;		/* 2 */
+	if ((ret = smbus_send_slave_address(smbus_io_base, device)))
+		goto err;
+
+	index++;
+	if ((ret = smbus_send_command(smbus_io_base, address)))
+		goto err;
+
+	index++;
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	/* Clear the ack for multiple byte reads */
+	smbus_ack(smbus_io_base, (count == 1) ? 1 : 0);
+
+	index++;
+	if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01)))
+		goto err;
+
+	while (count) {
+		/* Set the ACK if this is the next to last byte */
+		smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
+
+		/* Set the stop bit if this is the last byte to read */
+
+		if (count == 1)
+			smbus_stop_condition(smbus_io_base);
+
+		val = inb(smbus_io_base + SMB_SDA);
+		*data++ = val;
+
+		if (count > 1) {
+			ret = smbus_wait(smbus_io_base);
+			if (ret)
+				return;
+		}
+
+		count--;
+	}
+
+	return;
+
+      err:
+	printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret);
+}
+
+static inline unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+		unsigned char device, unsigned char address)
+{
+	unsigned char val = 0;
+	_doread(smbus_io_base, device, address, &val, sizeof(val));
+	return val;
+}
+
+static inline unsigned short do_smbus_read_word(unsigned smbus_io_base,
+		 unsigned char device, unsigned char address)
+{
+	unsigned short val = 0;
+	_doread(smbus_io_base, device, address, (unsigned char *)&val,
+		sizeof(val));
+	return val;
+}
+
+static int _dowrite(unsigned smbus_io_base, unsigned char device,
+		    unsigned char address, unsigned char *data, int count)
+{
+
+	int ret;
+
+	if ((ret = smbus_check_stop_condition(smbus_io_base)))
+		goto err;
+
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	if ((ret = smbus_send_slave_address(smbus_io_base, device)))
+		goto err;
+
+	if ((ret = smbus_send_command(smbus_io_base, address)))
+		goto err;
+
+	while (count) {
+		if ((ret = smbus_write(smbus_io_base, *data++)))
+			goto err;
+		count--;
+	}
+
+	smbus_stop_condition(smbus_io_base);
+	return 0;
+
+      err:
+	printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret);
+	return -1;
+}
+
+static inline int do_smbus_write_byte(unsigned smbus_io_base,
+		unsigned char device, unsigned char address, unsigned char data)
+{
+	return _dowrite(smbus_io_base, device, address,
+			(unsigned char *)&data, 1);
+}
+
+static inline int do_smbus_write_word(unsigned smbus_io_base,
+		unsigned char device, unsigned char address, unsigned short data)
+{
+	return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
+			2);
+}

Modified: trunk/src/southbridge/amd/rs690/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/rs690/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs690/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,5 +1,5 @@
 driver-y += rs690.c
-driver-y += rs690_cmn.c
-driver-y += rs690_pcie.c
-driver-y += rs690_ht.c
-driver-y += rs690_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c

Copied: trunk/src/southbridge/amd/rs690/cmn.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/cmn.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c)
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include "rs690.h"
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+
+	pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg + 0x4, data);
+
+}
+
+/* extension registers */
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+{
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg;
+	return *((u32 *) addr);
+}
+
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);*/
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg_pos;
+
+	reg = reg_old = *((u32 *) addr);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		*((u32 *) addr) = reg;
+	}
+}
+
+u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+u32 nbpcie_p_read_index(device_t dev, u32 index)
+{
+	return nb_read_index((dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+{
+	nb_write_index((dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+	}
+}
+
+/***********************************************************
+* To access bar3 we need to program PCI MMIO 7 in K8.
+* in_out:
+*	1: enable/enter k8 temp mmio base
+*	0: disable/restore
+***********************************************************/
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
+{
+	/* K8 Function1 is address map */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+
+	if (in_out) {
+		u32 dword, sblk;
+
+		/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* Fill MMIO limit/base pair. */
+		pci_write_config32(k8_f1, 0xbc,
+				   (((pcie_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
+		pci_write_config32(k8_f1, 0xb4,
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
+	} else {
+		pci_write_config32(k8_f1, 0xb8, 0);
+		pci_write_config32(k8_f1, 0xbc, 0);
+		pci_write_config32(k8_f1, 0xb0, 0);
+		pci_write_config32(k8_f1, 0xb4, 0);
+	}
+}
+
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+{
+	switch (port) {
+	case 2:		/* GFX, bit4-5 */
+	case 3:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 2), 0 << (port + 2));
+		break;
+	case 4:		/* GPP, bit20-24 */
+	case 5:
+	case 6:
+	case 7:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 17), 0 << (port + 17));
+		break;
+	}
+}
+
+/********************************************************************************************************
+* Output:
+*	0: no device is present.
+*	1: device is present and is trained.
+********************************************************************************************************/
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 count = 5000;
+	u32 lc_state, reg;
+	int8_t current, res = 0;
+
+	while (count--) {
+		mdelay(40);
+		udelay(200);
+		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
+			     port, lc_state);
+		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
+
+		switch (current) {
+		case 0x00:	/* 0x00-0x04 means no device is present */
+		case 0x01:
+		case 0x02:
+		case 0x03:
+		case 0x04:
+			res = 0;
+			count = 0;
+			break;
+		case 0x07:	/* device is in compliance state (training sequence is doen). Move to train the next device */
+			res = 1;	/* TODO: CIM sets it to 0 */
+			count = 0;
+			break;
+		case 0x10:
+			reg =
+			    pci_ext_read_config32(nb_dev, dev,
+						  PCIE_VC0_RESOURCE_STATUS);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
+			/* check bit1 */
+			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
+				/* set bit8=1, bit0-2=bit4-6 */
+				u32 tmp;
+				reg =
+				    nbpcie_p_read_index(dev,
+							PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg &= 0xfff8;	/* clear bit0-2 */
+				reg += tmp;	/* merge */
+				reg |= 1 << 8;
+				count++;	/* CIM said "keep in loop"?  */
+			} else {
+				res = 1;
+				count = 0;
+			}
+			break;
+		default:	/* reset pcie */
+			res = 0;
+			count = 0;	/* break loop */
+			break;
+		}
+	}
+	return res;
+}
+
+/*
+* Compliant with CIM_33's ATINB_SetToms.
+* Set Top Of Memory below and above 4G.
+*/
+void rs690_set_tom(device_t nb_dev)
+{
+	extern uint64_t uma_memory_base;
+
+	/* set TOM */
+	pci_write_config32(nb_dev, 0x90, uma_memory_base);
+	nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+}
+

Copied: trunk/src/southbridge/amd/rs690/early_setup.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c)
@@ -0,0 +1,484 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#define NBHTIU_INDEX		0xA8
+#define NBMISC_INDEX		0x60
+#define NBMC_INDEX 		0xE8
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+	pci_write_config32(dev, index_reg, index /* | 0x80 */ );
+	pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+static u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+static u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+static u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				 u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				   u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				  u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
+				    u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				 u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+/*
+* Compliant with CIM_33's ATINB_PrepareInit
+*/
+static void get_cpu_rev(void)
+{
+	u32 eax, ebx, ecx, edx;
+	__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
+			  :"0"(1));
+	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
+	if (eax <= 0xfff)
+		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
+	else if (eax <= 0x10fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
+	else if (eax <= 0x20fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
+	else if (eax <= 0x40fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
+	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
+	else if (eax <= 0X60FF0)
+		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
+	else if (eax <= 0x100000)
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
+	else
+		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
+}
+
+static u8 get_nb_rev(device_t nb_dev)
+{
+	u32 reg;
+	reg = pci_read_config32(nb_dev, 0x00);
+	if (0x7911 == (reg >> 16))
+		return 7;
+	reg = pci_read_config8(nb_dev, 0x89);	/* copy from CIM, can't find in doc */
+	if (reg & 0x2)		/* check bit1 */
+		return 7;
+	if (reg & 0x1)		/* check bit0 */
+		return 6;
+	else
+		return 5;
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_HTInit
+* Init HT link speed/width for rs690 -- k8 link
+*****************************************/
+static void rs690_htinit(void)
+{
+	/*
+	 * About HT, it has been done in enumerate_ht_chain().
+	 */
+	device_t k8_f0, rs690_f0;
+	u32 reg;
+	u8 reg8;
+	u8 k8_ht_freq;
+
+	k8_f0 = PCI_DEV(0, 0x18, 0);
+	/************************
+	* get k8's ht freq, in k8's function 0, offset 0x88
+	* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
+	* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
+	* value to this reg, and that value takes effect on the next warm reset or
+	* LDTSTOP_L disconnect sequence.
+	* 0000b = 200Mhz
+	* 0010b = 400Mhz
+	* 0100b = 600Mhz
+	* 0101b = 800Mhz
+	* 0110b = 1Ghz
+	* 1111b = 1Ghz
+	************************/
+	reg = pci_read_config32(k8_f0, 0x88);
+	k8_ht_freq = (reg & 0xf00) >> 8;
+	printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	rs690_f0 = PCI_DEV(0, 0, 0);
+	reg8 = pci_read_config8(rs690_f0, 0x9c);
+	printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+	 */
+	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+		printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		reg8 |= 0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+		printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		reg8 &= ~0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	}
+}
+
+/*******************************************************
+* Optimize k8 with UMA.
+* See BKDG_NPT_0F guide for details.
+* The processor node is addressed by its Node ID on the HT link and can be
+* accessed with a device number in the PCI configuration space on Bus0.
+* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
+* to Device 25, and so on.
+* The processor implements configuration registers in PCI configuration
+* space using the following four headers
+*	Function0: HT technology configuration
+*	Function1: Address map configuration
+*	Function2: DRAM and HT technology Trace mode configuration
+*	Function3: Miscellaneous configuration
+*******************************************************/
+static void k8_optimization(void)
+{
+	device_t k8_f0, k8_f2, k8_f3;
+	msr_t msr;
+
+	printk(BIOS_INFO, "k8_optimization()\n");
+	k8_f0 = PCI_DEV(0, 0x18, 0);
+	k8_f2 = PCI_DEV(0, 0x18, 2);
+	k8_f3 = PCI_DEV(0, 0x18, 3);
+
+	pci_write_config32(k8_f0, 0x90, 0x01700178);	/* CIM NPT_Optimization */
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
+			      1 << 26 | 1 << 27);
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
+	set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15);	/* TODO */
+
+	pci_write_config32(k8_f3, 0x70, 0x51320111);	/* CIM NPT_Optimization */
+	pci_write_config32(k8_f3, 0x74, 0x50304021);
+	pci_write_config32(k8_f3, 0x78, 0x08002A00);
+	if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
+		pci_write_config32(k8_f3, 0x7C, 0x0000211B); /* dual core */
+	else
+		pci_write_config32(k8_f3, 0x7C, 0x0000211C); /* single core */
+	set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
+
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+	set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
+	set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10);
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+
+	msr = rdmsr(0xC001001F);
+	msr.lo &= ~(1 << 9);
+	msr.hi &= ~(1 << 4);
+	wrmsr(0xC001001F, msr);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
+*****************************************/
+static void rs690_por_pcicfg_init(device_t nb_dev)
+{
+	/* enable PCI Memory Access */
+	set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
+	/* Set RCRB Enable */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
+	/* allow decode of 640k-1MB */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
+	/* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
+	/* Power Management Register Enable */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
+
+	/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
+	 * BMMsgEn */
+	set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
+
+	/* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
+	 * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
+	set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
+	/* Reg94h[4:0] = 0x0  P drive strength offset 0
+	 * Reg94h[6:5] = 0x2  P drive strength additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
+
+	/* Reg94h[20:16] = 0x0  N drive strength offset 0
+	 * Reg94h[22:21] = 0x2  N drive strength additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
+
+	/* Reg80h[4:0] = 0x0  Termination offset
+	 * Reg80h[6:5] = 0x2  Termination additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
+
+	/* Reg80h[14] = 0x1   Enable receiver termination control */
+	set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
+
+	/* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
+	 * Reg94h[14] = 0x1  Enable drive strength control */
+	set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
+
+	/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
+	set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
+
+	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
+	 * force this BAR as mem type in rs690_gfx.c */
+	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_MCIndex_POR_TABLE
+*****************************************/
+static void rs690_por_mc_index_init(device_t nb_dev)
+{
+	set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
+	set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
+	set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
+	set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
+	set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
+* Compliant with CIM_33's MISC_INIT_TBL
+*****************************************/
+static void rs690_por_misc_index_init(device_t nb_dev)
+{
+	/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
+	 * Block non-snoop DMA request if PMArbDis is set.
+	 * Set BMSetDis */
+	set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
+	set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
+
+	/* NBCFG (NBMISCIND 0x0): NB_CNTL -
+	 *   HIDE_NB_AGP_CAP  ([0], default=1)HIDE
+	 *   HIDE_P2P_AGP_CAP ([1], default=1)HIDE
+	 *   HIDE_NB_GART_BAR ([2], default=1)HIDE
+	 *   AGPMODE30        ([4], default=0)DISABLE
+	 *   AGP30ENCHANCED   ([5], default=0)DISABLE
+	 *   HIDE_AGP_CAP     ([8], default=1)ENABLE */
+	set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506);	/* set bit 10 for MSI */
+
+	/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
+	 *      set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
+	 * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
+	set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
+
+	/* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
+	set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
+
+	/* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
+	set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
+
+	/* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
+	set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
+
+	/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
+	 * Enable access to DEV8
+	 * Enable setPower message for all ports
+	 */
+	set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
+	set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
+
+	set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
+	set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
+	/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
+	set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE
+*****************************************/
+static void rs690_por_htiu_index_init(device_t nb_dev)
+{
+	/* 0xBC:
+	* Enables GSM mode for C1e or C3 with pop-up
+	* Prevents AllowLdtStop from being asserted during HT link recovery
+	* Allows FID cycles to be serviced faster. Needed for RS690 A12. No harm in RS690 A11 */
+	set_htiu_enable_bits(nb_dev, 0x05, ~0xffffffff, 0x0BC);
+	/* 0x4203A202:
+	* Enables writes to pass in-progress reads
+	* Enables streaming of CPU writes
+	* Enables extended write buffer for CPU writes
+	* Enables additional response buffers
+	* Enables special reads to pass writes
+	* Enables decoding of C1e/C3 and FID cycles
+	* Enables HTIU-display handshake bypass.
+	* Enables tagging fix */
+	set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x4203A202);
+
+	/* Enables byte-write optimization for IOC requests
+	* Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
+	* Disables upstream system-management delay */
+	set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001);
+
+	/* HTIUNBIND 0x16 [1] = 0x1     Enable crc decoding fix */
+	set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_POR_INIT_JMPDI
+* Configure RS690 registers to power-on default RPR.
+* POR: Power On Reset
+* RPR: Register Programming Requirements
+*****************************************/
+static void rs690_por_init(device_t nb_dev)
+{
+	printk(BIOS_INFO, "rs690_por_init\n");
+	/* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
+	rs690_por_pcicfg_init(nb_dev);
+
+	/* ATINB_MCIND_POR_TABLE */
+	rs690_por_mc_index_init(nb_dev);
+
+	/* ATINB_MISCIND_POR_TABLE */
+	rs690_por_misc_index_init(nb_dev);
+
+	/* ATINB_HTIUNBIND_POR_TABLE */
+	rs690_por_htiu_index_init(nb_dev);
+
+	/* ATINB_CLKCFG_PORT_TABLE */
+	/* rs690 A11 SB Link full swing? */
+}
+
+/* enable CFG access to Dev8, which is the SB P2P Bridge */
+static void enable_rs690_dev8(void)
+{
+	set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
+}
+
+
+
+/*
+* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
+*/
+static void rs690_before_pci_init(void)
+{
+}
+
+/*
+* The calling sequence is same as CIM.
+*/
+static void rs690_early_setup(void)
+{
+	device_t nb_dev = PCI_DEV(0, 0, 0);
+	printk(BIOS_INFO, "rs690_early_setup()\n");
+
+	/*ATINB_PrepareInit */
+	get_cpu_rev();
+	switch (get_nb_rev(nb_dev)) {	/* PCIEMiscInit */
+	case 5:
+		printk(BIOS_INFO, "NB Revision is A11.\n");
+		break;
+	case 6:
+		printk(BIOS_INFO, "NB Revision is A12.\n");
+		break;
+	case 7:
+		printk(BIOS_INFO, "NB Revision is A21.\n");
+		break;
+	}
+
+	k8_optimization();
+	rs690_por_init(nb_dev);
+}

Copied: trunk/src/southbridge/amd/rs690/gfx.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/gfx.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c)
@@ -0,0 +1,625 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ *  for rs690 internal graphics device
+ *  device id of internal grphics:
+ *	RS690M/T: 0x791f
+ *    RS690:	   0x791e
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs690.h"
+
+#define CLK_CNTL_INDEX	0x8
+#define CLK_CNTL_DATA	0xC
+
+#ifdef UNUSED_CODE
+static u32 clkind_read(device_t dev, u32 index)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
+	return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
+}
+#endif
+
+static void clkind_write(device_t dev, u32 index, u32 data)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+	/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
+	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
+}
+
+/*
+* pci_dev_read_resources thinks it is a IO type.
+* We have to force it to mem type.
+*/
+static void rs690_gfx_read_resources(device_t dev)
+{
+	printk(BIOS_INFO, "rs690_gfx_read_resources.\n");
+
+	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
+	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
+	   which tells us it is a memory address base.
+	 */
+	pci_write_config32(dev, 0x24, 0x00000000);
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+	compact_resources(dev);
+}
+
+static void internal_gfx_pci_dev_init(struct device *dev)
+{
+	u16 deviceid, vendorid;
+	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
+	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	     deviceid, vendorid);
+
+	pci_dev_init(dev);
+
+	/* clk ind */
+	clkind_write(dev, 0x08, 0x01);
+	clkind_write(dev, 0x0C, 0x22);
+	clkind_write(dev, 0x0F, 0x0);
+	clkind_write(dev, 0x11, 0x0);
+	clkind_write(dev, 0x12, 0x0);
+	clkind_write(dev, 0x14, 0x0);
+	clkind_write(dev, 0x15, 0x0);
+	clkind_write(dev, 0x16, 0x0);
+	clkind_write(dev, 0x17, 0x0);
+	clkind_write(dev, 0x18, 0x0);
+	clkind_write(dev, 0x19, 0x0);
+	clkind_write(dev, 0x1A, 0x0);
+	clkind_write(dev, 0x1B, 0x0);
+	clkind_write(dev, 0x1C, 0x0);
+	clkind_write(dev, 0x1D, 0x0);
+	clkind_write(dev, 0x1E, 0x0);
+	clkind_write(dev, 0x26, 0x0);
+	clkind_write(dev, 0x27, 0x0);
+	clkind_write(dev, 0x28, 0x0);
+	clkind_write(dev, 0x5C, 0x0);
+}
+
+
+/*
+* Set registers in RS690 and CPU to enable the internal GFX.
+* Please refer to CIM source code and BKDG.
+*/
+static void rs690_internal_gfx_enable(device_t dev)
+{
+	u32 l_dword;
+	int i;
+	device_t k8_f0 = 0, k8_f2 = 0;
+	device_t nb_dev = dev_find_slot(0, 0);
+
+	printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
+		    nb_dev);
+
+	/* set APERTURE_SIZE, 128M. */
+	l_dword = pci_read_config32(nb_dev, 0x8c);
+	printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword);
+	l_dword &= 0xffffff8f;
+	pci_write_config32(nb_dev, 0x8c, l_dword);
+
+	/* set TOM */
+	rs690_set_tom(nb_dev);
+
+	/* LPC DMA Deadlock workaround? */
+	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	l_dword = pci_read_config32(k8_f0, 0x68);
+	l_dword &= ~(1 << 22);
+	l_dword |= (1 << 21);
+	pci_write_config32(k8_f0, 0x68, l_dword);
+
+	/* Enable 64bit mode. */
+	set_nbmc_enable_bits(nb_dev, 0x5f, 0, 1 << 9);
+	set_nbmc_enable_bits(nb_dev, 0xb0, 0, 1 << 8);
+
+	/* 64bit Latency. */
+	set_nbmc_enable_bits(nb_dev, 0x5f, 0x7c00, 0x800);
+
+	/* UMA dual channel control register. */
+	nbmc_write_index(nb_dev, 0x86, 0x3d);
+
+	/* check the setting later!! */
+	set_htiu_enable_bits(nb_dev, 0x07, 1 << 7, 0);
+
+	/* UMA mode, powerdown memory PLL. */
+	set_nbmc_enable_bits(nb_dev, 0x74, 0, 1 << 31);
+
+	/* Copy CPU DDR Controller to NB MC. */
+	/* Why K8_MC_REG80 is special? */
+	k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	for (i = 0; i <= (0x80 - 0x40) / 4; i++) {
+		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
+		nbmc_write_index(nb_dev, 0x63 + i, l_dword);
+	}
+
+	/* Set K8 MC for UMA, Family F. */
+	l_dword = pci_read_config32(k8_f2, 0xa0);
+	l_dword |= 0x2c;
+	pci_write_config32(k8_f2, 0xa0, l_dword);
+	l_dword = pci_read_config32(k8_f2, 0x94);
+	l_dword &= 0xf0ffffff;
+	l_dword |= 0x07000000;
+	pci_write_config32(k8_f2, 0x94, l_dword);
+
+	/* set FB size and location. */
+	nbmc_write_index(nb_dev, 0x1b, 0x00);
+	l_dword = nbmc_read_index(nb_dev, 0x1c);
+	l_dword &= 0xffff0;
+	l_dword |= 0x400 << 20;
+	l_dword |= 0x4;
+	nbmc_write_index(nb_dev, 0x1c, l_dword);
+	l_dword = nbmc_read_index(nb_dev, 0x1d);
+	l_dword &= 0xfffff000;
+	l_dword |= 0x0400;
+	nbmc_write_index(nb_dev, 0x1d, l_dword);
+	nbmc_write_index(nb_dev, 0x100, 0x3fff3800);
+
+	/* Program MC table. */
+	set_nbmc_enable_bits(nb_dev, 0x00, 0, 1 << 31);
+	l_dword = nbmc_read_index(nb_dev, 0x91);
+	l_dword |= 0x5;
+	nbmc_write_index(nb_dev, 0x91, l_dword);
+	set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1 << 6);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
+
+	/* TODO: the optimization of voltage and frequency */
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations pcie_ops = {
+	.read_resources = rs690_gfx_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs690_gfx_init, */
+	.scan_bus = 0,
+	.enable = rs690_internal_gfx_enable,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * The dev id of 690G is 791E, while the id of 690M, 690T is 791F.
+ * We should list both of them here.
+ * */
+static const struct pci_driver pcie_driver_690t __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX,
+};
+
+static const struct pci_driver pcie_driver_690 __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690_INT_GFX,
+};
+
+/* step 12 ~ step 14 from rpr */
+static void single_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n");
+
+	/* step 12 training, releases hold training for GFX port 0 (device 2) */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4);
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	result = PcieTrainPort(nb_dev, dev, 2);
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n");
+
+	/* step 13 Power Down Control */
+	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+
+	/* step 13.a Link Training was NOT successful */
+	if (!result) {
+		set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
+		set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
+		if (cfg->gfx_tmds)
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+		else {
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
+			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
+		}
+	} else {		/* step 13.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
+			break;
+		case 8:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
+			break;
+		}
+	}
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n");
+
+	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n");
+}
+
+/* step 15 ~ step 18 from rpr */
+static void dual_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs690_config *cfg =
+		    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* step 15: Training for Device 2 */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+	/* Releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	/* PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, 2);
+
+	/* step 16: Power Down Control for Device 2 */
+	/* step 16.a Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port A */
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f);
+	} else {		/* step 16.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
+			break;
+		}
+	}
+
+	/* step 17: Training for Device 3 */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 5, 0 << 5);
+	/* Releases hold training for GFX port 0 (device 3) */
+	PcieReleasePortTraining(nb_dev, dev, 3);
+	/* PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, 3);
+
+	/*step 18: Power Down Control for Device 3 */
+	/* step 18.a Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port B and PLL1 */
+		nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+	} else {		/* step 18.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7070 : 0xe0e0);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3030 : 0xc0c0);
+			break;
+		}
+	}
+}
+
+
+/* For single port GFX configuration Only
+* width:
+* 	000 = x16
+* 	001 = x1
+*	010 = x2
+*	011 = x4
+*	100 = x8
+*	101 = x12 (not supported)
+*	110 = x16
+*/
+static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
+{
+	u32 reg32;
+	device_t sb_dev;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* step 5.9.1.1 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+
+	/* step 5.9.1.2 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+	/* step 5.9.1.3 */
+	set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
+	/* step 5.9.1.4 */
+	set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
+	/* step 5.9.2.4 */
+	if (0 == cfg->gfx_reconfiguration)
+		set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
+
+	/* step 5.9.1.5 */
+	do {
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+	}
+	while (reg32 & 0x100);
+
+	/* step 5.9.1.6 */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	do {
+		reg32 = pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg32 & VC_NEGOTIATION_PENDING);
+
+	/* step 5.9.1.7 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+	if (((reg32 & 0x70) >> 4) != 0x6) {
+		/* the unused lanes should be powered off. */
+	}
+
+	/* step 5.9.1.8 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
+}
+
+/*
+* GFX Core initialization, dev2, dev3
+*/
+void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 reg16;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+		    nb_dev, dev, port);
+
+	/* step 0, REFCLK_SEL, skip A11 revision */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9,
+			       cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9);
+	printk(BIOS_INFO, "rs690_gfx_init step0.\n");
+
+	/* step 1, lane reversal (only need if CMOS option is enabled) */
+	if (cfg->gfx_lane_reversal) {
+		set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+		if (cfg->gfx_dual_slot)
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+	}
+	printk(BIOS_INFO, "rs690_gfx_init step1.\n");
+
+	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+	/* AMD calls the configuration CrossFire */
+	if (cfg->gfx_dual_slot)
+		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+	printk(BIOS_INFO, "rs690_gfx_init step2.\n");
+
+	/* step 2, TMDS, (only need if CMOS option is enabled) */
+	if (cfg->gfx_tmds) {
+	}
+
+	/* step 3, GFX overclocking, (only need if CMOS option is enabled) */
+	/* skip */
+
+	/* step 4, reset the GFX link */
+	/* step 4.1 asserts both calibration reset and global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
+
+	/* step 4.2 de-asserts calibration reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
+
+	/* step 4.3 wait for at least 200us */
+	udelay(200);
+
+	/* step 4.4 de-asserts global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
+
+	/* step 4.5 asserts both calibration reset and global reset */
+	/* a weird step in RPR, don't do that */
+	/* set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14); */
+
+	/* step 4.6 bring external GFX device out of reset, wait for 1ms */
+	mdelay(1);
+	printk(BIOS_INFO, "rs690_gfx_init step4.\n");
+
+	/* step 5 program PCIE memory mapped configuration space */
+	/* done by enable_pci_bar3() before */
+
+	/* step 6 SBIOS compile flags */
+        if (cfg->gfx_tmds) {
+                /* step 6.2.2 Clock-Muxing Control */
+                /* step 6.2.2.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+
+                /* step 6.2.2.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+
+                /* step 6.2.2.3 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+
+                /* step 6.2.3 Lane-Muxing Control */
+                /* step 6.2.3.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+
+                /* step 6.2.4 Received Data Control */
+                /* step 6.2.4.1 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+
+                /* step 6.2.4.2 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+
+                /* step 6.2.4.3 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+
+                /* step 6.2.4.4 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+
+                /* step 6.2.5 PLL Power Down Control */
+                /* step 6.2.5.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+
+                /* step 6.2.6 Driving Strength Control */
+                /* step 6.2.6.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+
+                /* step 6.2.6.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+        }
+
+        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+
+	/* step 7 compliance state, (only need if CMOS option is enabled) */
+	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+	if (cfg->gfx_compliance) {
+		/* force compliance */
+		set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
+		/* release hold training for device 2. GFX initialization is done. */
+		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
+		printk(BIOS_INFO, "rs690_gfx_init step7.\n");
+		return;
+	}
+
+	/* step 8 common initialization */
+	/* step 8.1 sets RCB timeout to be 25ms */
+	set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16);
+	printk(BIOS_INFO, "rs690_gfx_init step8.1.\n");
+
+	/* step 8.2 disables slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
+	printk(BIOS_INFO, "rs690_gfx_init step8.2.\n");
+
+	/* step 8.3 sets DMA payload size to 64 bytes */
+	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
+	printk(BIOS_INFO, "rs690_gfx_init step8.3.\n");
+
+	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
+	 * time out and go back to Detect Idle.*/
+	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
+	printk(BIOS_INFO, "rs690_gfx_init step8.4.\n");
+
+	/* step 8.5 shortens the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
+	printk(BIOS_INFO, "rs690_gfx_init step8.5.\n");
+
+	/* step 8.6 blocks DMA traffic during C3 state */
+	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+	printk(BIOS_INFO, "rs690_gfx_init step8.6.\n");
+
+	/* step 8.7 Do not gate the electrical idle form the PHY
+	 * step 8.8 Enables the escape from L1L23 */
+	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
+	printk(BIOS_INFO, "rs690_gfx_init step8.8.\n");
+
+	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
+	 * SLOT_IMPLEMENTED at PCIE_CAP */
+	reg16 = pci_read_config16(dev, 0x5a);
+	reg16 |= 0x100;
+	pci_write_config16(dev, 0x5a, reg16);
+	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
+
+	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
+	 * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */
+	set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31);
+	printk(BIOS_INFO, "rs690_gfx_init step8.10.\n");
+
+	/* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */
+	set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0);
+	printk(BIOS_INFO, "rs690_gfx_init step8.11.\n");
+
+	/* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6);
+	printk(BIOS_INFO, "rs690_gfx_init step8.12.\n");
+
+	/* step 8.13 Sets CMGOOD_OVERRIDE. */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
+	printk(BIOS_INFO, "rs690_gfx_init step8.13.\n");
+
+	/* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */
+	/* skip */
+
+	/* step 10 Optional Features, only needed if CMOS option is enabled. */
+	/* step 10.a: L0s */
+	/* enabling L0s in the RS690 GFX port(s) */
+	set_pcie_enable_bits(nb_dev, 0xF9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xA0, 0xf << 8, 8 << 8);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 |= 1 << 0;
+	/* L0s is intended as a power saving state */
+	/* pci_write_config16(dev, 0x68, reg16); */
+
+	/* enabling L0s in the External GFX Device(s) */
+
+	/* step 10.b: active state power management (ASPM L1) */
+	/* TO DO */
+
+	/* step 10.c: turning off PLL During L1/L23 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3);
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9);
+
+	/* step 10.d: TXCLK clock gating */
+	set_nbmisc_enable_bits(nb_dev, 0x7, 3, 3);
+	set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22);
+	set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4);
+
+	/* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */
+
+	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
+	 * While details will be added later in the document, for now assue the single-port configuration. */
+	/* skip */
+
+	/* Single-port/Dual-port configureation. */
+	switch (cfg->gfx_dual_slot) {
+	case 0:
+		single_port_configuration(nb_dev, dev);
+		break;
+	case 1:
+		dual_port_configuration(nb_dev, dev);
+		break;
+	default:
+		printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
+		break;
+	}
+}

Copied: trunk/src/southbridge/amd/rs690/ht.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/ht.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "rs690.h"
+
+/* for UMA internal graphics */
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
+{
+	device_t k8_f0;
+	u8 reg;
+
+	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 21, 1 << 21);
+
+	reg = nbpcie_p_read_index(sb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(sb_dev, 0x10, reg);
+
+	reg = nbpcie_p_read_index(nb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(nb_dev, 0x10, reg);
+
+	/* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
+	 * Set this bit to avoid a deadlock condition. */
+	reg = htiu_read_index(nb_dev, 0x6);
+	reg |= 0x1000000;	/* bit26 */
+	htiu_write_index(nb_dev, 0x6, reg);
+}
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/*
+	 * 1 is APIC enable
+	 * 18 is enable nb to accept A4 interrupt request from SB.
+	 */
+	dword = pci_read_config32(dev, 0x4C);
+	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
+	pci_write_config32(dev, 0x4C, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = pcie_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690_HT,
+};

Copied: trunk/src/southbridge/amd/rs690/pcie.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c)
@@ -0,0 +1,401 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs690.h"
+
+/*------------------------------------------------
+* Global variable
+------------------------------------------------*/
+PCIE_CFG AtiPcieCfg = {
+	PCIE_ENABLE_STATIC_DEV_REMAP,	/* Config */
+	0,			/* ResetReleaseDelay */
+	0,			/* Gfx0Width */
+	0,			/* Gfx1Width */
+	0,			/* GfxPayload */
+	0,			/* GppPayload */
+	0,			/* PortDetect, filled by GppSbInit */
+	0,			/* PortHp */
+	0,			/* DbgConfig */
+	0,			/* DbgConfig2 */
+	0,			/* GfxLx */
+	0,			/* GppLx */
+	0,			/* NBSBLx */
+	0,			/* PortSlotInit */
+	0,			/* Gfx0Pwr */
+	0,			/* Gfx1Pwr */
+	0			/* GppPwr */
+};
+
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
+static void ValidatePortEn(device_t nb_dev);
+
+static void ValidatePortEn(device_t nb_dev)
+{
+}
+
+
+/*****************************************************************
+* Compliant with CIM_33's PCIEPowerOffGppPorts
+* Power off unused GPP lines
+*****************************************************************/
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg;
+	u16 state_save;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+	u8 state = cfg->port_enable;
+
+	if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
+		state &= AtiPcieCfg.PortDetect;
+	state = ~state;
+	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
+	state_save = state << 17;
+	state &= !(AtiPcieCfg.PortHp);
+	reg = nbmisc_read_index(nb_dev, 0x0c);
+	reg |= state;
+	nbmisc_write_index(nb_dev, 0x0c, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x08);
+	reg |= state_save;
+	nbmisc_write_index(nb_dev, 0x08, reg);
+
+	if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
+	    && !(AtiPcieCfg.
+		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
+			   PCIE_GFX_COMPLIANCE))) {
+	}
+
+        if (!cfg->gfx_tmds){
+		/* step 3 Power Down Control for Southbridge */
+		reg = nbpcie_p_read_index(dev, 0xa2);
+
+		switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
+		case 1:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+			break;
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+#ifdef UNUSED_CODE
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+}
+#endif
+
+/**********************************************************************
+**********************************************************************/
+static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* enables GPP reconfiguration */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg |=
+	    (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
+	     RECONFIG_GPPSB_ATOMIC_RESET);
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x67);
+	reg &= 0xffffff0f;		/* clean */
+	reg |= cfg->gpp_configuration << 4;
+	nbmisc_write_index(nb_dev, 0x67, reg);
+
+	/* read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* delay 1ms */
+	mdelay(1);
+
+	/* waits until SB has trained to L0, poll for bit0-5 = 0x10 */
+	do {
+		reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
+		reg &= 0x3f;	/* remain LSB [5:0] bits */
+	} while (LC_STATE_RECONFIG_GPPSB != reg);
+
+	/* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
+	do {
+		reg =
+		    pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg & VC_NEGOTIATION_PENDING);
+}
+
+/*****************************************************************
+* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
+* Space to a 256MB range within the first 4GB of addressable memory.
+*****************************************************************/
+void enable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
+	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
+
+	pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS);	/* PCIEMiscInit */
+	pci_write_config32(nb_dev, 0x20, 0x00000000);
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
+	ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************************************
+* We should disable bar3 when we want to exit rs690_enable, because bar3 will be
+* remapped in set_resource later.
+*****************************************************************/
+void disable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
+	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEGPPInit
+* nb_dev:
+*	root bridge struct
+* dev:
+*	p2p bridge struct
+* port:
+*	p2p bridge number, 4-8
+*****************************************/
+void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u8 reg8;
+	u16 reg16;
+	device_t sb_dev;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
+
+	/* init GPP core */
+	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
+			     1 << 8);
+	/* PCIE initialization 5.10.2: rpr 2.12*/
+	set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0);	/* no description in datasheet. */
+
+	/* init GPPSB port */
+	/* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/
+	set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16);
+	/* PCIE initialization 5.10.2: rpr 2.4 */
+	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
+	/* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */
+	set_pcie_enable_bits(dev, 0xA0, ~0xffffffbf, (3 << 30) | (3 << 12) | (3 << 4));
+	/* PCIE initialization 5.10.2: rpr 2.13 */
+	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 6);
+
+	/* SLOT_IMPLEMENTED in pcieConfig space */
+	reg8 = pci_read_config8(dev, 0x5b);
+	reg8 |= 1 << 0;
+	pci_write_config8(dev, 0x5b, reg8);
+
+	reg16 = pci_read_config16(dev, 0x5a);
+	reg16 |= 0x100;
+	pci_write_config16(dev, 0x5a, reg16);
+	nbmisc_write_index(nb_dev, 0x34, 0);
+
+	/* check compliance rpr step 2.1*/
+	if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
+		u32 tmp;
+		tmp = nbmisc_read_index(nb_dev, 0x67);
+		tmp |= 1 << 3;
+		nbmisc_write_index(nb_dev, 0x67, tmp);
+	}
+
+	/* step 5: dynamic slave CPL buffer allocation */
+	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11);
+
+	/* step 5a: Training for GPP devices */
+	/* init GPP */
+	switch (port) {
+	case 4:		/* GPP */
+	case 5:
+	case 6:
+	case 7:
+		/* Blocks DMA traffic during C3 state */
+		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+		/* Enabels TLP flushing */
+		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+		/* check port enable */
+		if (cfg->port_enable & (1 << port)) {
+			PcieReleasePortTraining(nb_dev, dev, port);
+			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+				u8 res = PcieTrainPort(nb_dev, dev, port);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
+				if (res) {
+					AtiPcieCfg.PortDetect |= 1 << port;
+				}
+			}
+		}
+		break;
+	case 8:		/* SB */
+		break;
+	}
+	PciePowerOffGppPorts(nb_dev, dev, port);
+
+	/* step 5b: GFX devices in a GPP slot */
+
+	/* step 6a: VCI */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	if (port == 8) {
+		/* The code below between #if and #endif causes a hang on HDA init.
+		 * So we skip it. */
+#if 0
+		/* Clear bits 7:1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1);
+		/* Maps Traffic Class 1-7 to VC1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 0x7f << 1, 0x7f << 1);
+		/* Assigns VC ID to 1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24);
+		/* Enables VC1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31);
+
+		do {
+			reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124);
+			reg16 &= 0x2;
+		} while (reg16); /*bit[1] = 0 means VC1 flow control initialization is successful */
+#endif
+	}
+
+	/* step 6b: L0s for the southbridge link */
+	/* To enalbe L0s in the southbridage*/
+
+	/* step 6c: L0s for the GPP link(s) */
+	/* To eable L0s in the RS690 for the GPP port(s) */
+	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 |= 1 << 0;
+	pci_write_config16(dev, 0x68, reg16);
+
+	/* step 6d: ASPM L1 for the southbridge link */
+	/* To enalbe L1s in the southbridage*/
+
+	/* step 6e: ASPM L1 for GPP link(s) */;
+	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
+	set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 &= ~0xff;
+	reg16 |= 1 << 1;
+	pci_write_config16(dev, 0x68, reg16);
+
+	/* step 6f: Turning off PLL during L1/L23 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3);
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9);
+
+	/* step 6g: TXCLK clock gating */
+	set_nbmisc_enable_bits(nb_dev, 0x7, 3 << 4, 3 << 4);
+	set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22);
+	set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4);
+
+	/* step 6h: LCLK clock gating, done in rs690_config_misc_clk() */
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEConfigureGPPCore
+*****************************************/
+void config_gpp_core(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	reg = nbmisc_read_index(nb_dev, 0x20);
+	if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
+		reg &= 0xfffffffd;	/* set bit1 = 0 */
+	else
+		reg |= 0x2;	/* set bit1 = 1 */
+	nbmisc_write_index(nb_dev, 0x20, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x67);	/* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
+	if (cfg->gpp_configuration != ((reg >> 4) & 0xf))
+		switching_gpp_configurations(nb_dev, sb_dev);
+	ValidatePortEn(nb_dev);
+}
+
+#ifdef UNUSED_CODE
+/*****************************************
+* Compliant with CIM_33's PCIEMiscClkProg
+*****************************************/
+void pcie_config_misc_clk(device_t nb_dev)
+{
+	u32 reg;
+	struct bus pbus; /* fake bus for dev0 fun1 */
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg |= 1 << 0;
+	pci_write_config32(nb_dev, 0x4c, reg);
+
+	if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
+		/* TXCLK Clock Gating */
+		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
+		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
+
+		/* LCLK Clock Gating */
+		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg &= ~(1 << 16);
+		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	}
+
+	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
+		/* TXCLK Clock Gating */
+		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
+		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
+
+		/* LCLK Clock Gating */
+		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg &= ~(1 << 24);
+		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	}
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg &= ~(1 << 0);
+	pci_write_config32(nb_dev, 0x4c, reg);
+}
+#endif

Modified: trunk/src/southbridge/amd/rs780/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/rs780/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs780/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,5 +1,5 @@
 driver-y += rs780.c
-driver-y += rs780_cmn.c
-driver-y += rs780_pcie.c
-driver-y += rs780_ht.c
-driver-y += rs780_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c

Copied: trunk/src/southbridge/amd/rs780/cmn.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/cmn.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c)
@@ -0,0 +1,403 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include <cpu/cpu.h>
+#include "rs780.h"
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+	pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+/* extension registers */
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+{
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg;
+	return *((u32 *) addr);
+}
+
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);*/
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg_pos;
+
+	reg = reg_old = *((u32 *) addr);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		*((u32 *) addr) = reg;
+	}
+}
+
+u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+u32 nbpcie_p_read_index(device_t dev, u32 index)
+{
+	return nb_read_index((dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+{
+	nb_write_index((dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+	}
+}
+
+/***********************************************************
+* To access bar3 we need to program PCI MMIO 7 in K8.
+* in_out:
+*	1: enable/enter k8 temp mmio base
+*	0: disable/restore
+***********************************************************/
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
+{
+	/* K8 Function1 is address map */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+
+	if (in_out) {
+		u32 dword, sblk;
+
+		/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* Fill MMIO limit/base pair. */
+		pci_write_config32(k8_f1, 0xbc,
+				   (((pcie_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
+		pci_write_config32(k8_f1, 0xb4,
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
+	} else {
+		pci_write_config32(k8_f1, 0xb8, 0);
+		pci_write_config32(k8_f1, 0xbc, 0);
+		pci_write_config32(k8_f1, 0xb0, 0);
+		pci_write_config32(k8_f1, 0xb4, 0);
+	}
+}
+
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+{
+	switch (port) {
+	case 2:		/* GFX, bit4-5 */
+	case 3:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 2), 0 << (port + 2));
+		break;
+	case 4:		/* GPPSB, bit20-24 */
+	case 5:
+	case 6:
+	case 7:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 17), 0 << (port + 17));
+		break;
+	case 9:		/* GPP, bit 4,5 of miscind 0x2D */
+	case 10:
+		set_nbmisc_enable_bits(nb_dev, 0x2D,
+				      1 << (port - 5), 0 << (port - 5));
+		break;
+	}
+}
+
+/********************************************************************************************************
+* Output:
+*	0: no device is present.
+*	1: device is present and is trained.
+********************************************************************************************************/
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 count = 5000;
+	u32 lc_state, reg, current_link_width, lane_mask;
+	int8_t current, res = 0;
+	u32 gfx_gpp_sb_sel;
+	void set_pcie_dereset(void);
+	void set_pcie_reset(void);
+
+	switch (port) {
+	case 2 ... 3:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX;
+		break;
+	case 4 ... 7:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB;
+		break;
+	case 9 ... 10:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
+		break;
+	default:
+		gfx_gpp_sb_sel = -1;
+		return 0;
+	}
+
+	while (count--) {
+		mdelay(40);
+		udelay(200);
+		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
+			     port, lc_state);
+		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
+
+		switch (current) {
+		case 0x00:	/* 0x00-0x04 means no device is present */
+		case 0x01:
+		case 0x02:
+		case 0x03:
+		case 0x04:
+			res = 0;
+			count = 0;
+			break;
+		case 0x06:
+			/* read back current link width [6:4]. */
+			current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7;
+			/* 4 means 7:4 and 15:12
+			 * 3 means 7:2 and 15:10
+			 * 2 means 7:1 and 15:9
+			 * egnoring the reversal case
+			 */
+			lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
+			reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
+			reg |= lane_mask << 8 | lane_mask;
+			reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */
+			nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg);
+			printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x",
+				     current_link_width, lane_mask);
+			set_pcie_reset();
+			mdelay(1);
+			set_pcie_dereset();
+			break;
+		case 0x07:	/* device is in compliance state (training sequence is done). Move to train the next device */
+			res = 0;
+			count = 0;
+			break;
+		case 0x10:
+			reg =
+			    pci_ext_read_config32(nb_dev, dev,
+						  PCIE_VC0_RESOURCE_STATUS);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
+			/* check bit1 */
+			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
+				/* set bit8=1, bit0-2=bit4-6 */
+				u32 tmp;
+				reg =
+				    nbpcie_p_read_index(dev,
+							PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg &= 0xfff8;	/* clear bit0-2 */
+				reg += tmp;	/* merge */
+				reg |= 1 << 8;
+				count++;	/* CIM said "keep in loop"?  */
+			} else {
+				res = 1;
+				count = 0;
+			}
+			break;
+		default:	/* reset pcie */
+			res = 0;
+			count = 0;	/* break loop */
+			break;
+		}
+	}
+	return res;
+}
+
+/*
+* Compliant with CIM_33's ATINB_SetToms.
+* Set Top Of Memory below and above 4G.
+*/
+void rs780_set_tom(device_t nb_dev)
+{
+	extern uint64_t uma_memory_base;
+
+	/* set TOM */
+	pci_write_config32(nb_dev, 0x90, uma_memory_base);
+	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+}
+
+// extract single bit
+u32 extractbit(u32 data, int bit_number)
+{
+	return (data >> bit_number) & 1;
+}
+
+// extract bit field
+u32 extractbits(u32 source, int lsb, int msb)
+{
+	int field_width = msb - lsb + 1;
+	u32 mask = 0xFFFFFFFF >> (32 - field_width);
+	return (source >> lsb) & mask;
+}
+
+// return AMD cpuid family
+int cpuidFamily(void)
+{
+	u32 baseFamily, extendedFamily, fms;
+	
+	fms = cpuid_eax (1);
+	baseFamily = extractbits (fms, 8, 11);
+	extendedFamily = extractbits (fms, 20, 27);
+	return baseFamily + extendedFamily;
+}
+
+
+// return non-zero for AMD family 0Fh processor found
+int is_family0Fh(void)
+{
+	return cpuidFamily() == 0x0F;
+}
+
+
+// return non-zero for AMD family 10h processor found
+int is_family10h(void)
+{
+	return cpuidFamily() == 0x10;
+}

Copied and modified: trunk/src/southbridge/amd/rs780/early_setup.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/rs780/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
 #endif
 
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBHTIU_INDEX		0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
 #define NBMISC_INDEX		0x60

Copied: trunk/src/southbridge/amd/rs780/gfx.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/gfx.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c)
@@ -0,0 +1,1340 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ *  for rs780 internal graphics device
+ *  device id of internal grphics:
+ *	RS780:	0x9610
+ *	RS780C:	0x9611
+ *	RS780M:	0x9612
+ *	RS780MC:0x9613
+ *	RS780E: 0x9615
+ *	RS785G: 0x9710 - just works, not much tested
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include "rs780.h"
+extern int is_dev3_present(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+extern uint64_t uma_memory_base, uma_memory_size;
+
+/* Trust the original resource allocation. Don't do it again. */
+#undef DONT_TRUST_RESOURCE_ALLOCATION
+//#define DONT_TRUST_RESOURCE_ALLOCATION
+
+#define CLK_CNTL_INDEX	0x8
+#define CLK_CNTL_DATA	0xC
+
+/* The Integrated Info Table. */
+ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
+
+#ifdef UNUSED_CODE
+static u32 clkind_read(device_t dev, u32 index)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
+	return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
+}
+#endif
+
+static void clkind_write(device_t dev, u32 index, u32 data)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+	/* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
+	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
+}
+
+/*
+* pci_dev_read_resources thinks it is a IO type.
+* We have to force it to mem type.
+*/
+static void rs780_gfx_read_resources(device_t dev)
+{
+	printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
+
+	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
+	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
+	   which tells us it is a memory address base.
+	 */
+	pci_write_config32(dev, 0x24, 0x00000000);
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+	compact_resources(dev);
+}
+
+typedef struct _MMIORANGE
+{
+	u32	Base;
+	u32	Limit;
+	u8	Attribute;
+} MMIORANGE;
+
+MMIORANGE MMIO[8], CreativeMMIO[8];
+
+#define CIM_STATUS u32
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR	0x80000000
+#define CIM_UNSUPPORTED	0x80000001
+#define CIM_DISABLEPORT 0x80000002
+
+#define	MMIO_ATTRIB_NP_ONLY	1
+#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
+#define MMIO_ATTRIB_SKIP_ZERO 1<<2
+
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
+static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
+{
+	int i;
+	for (i=0; i<8; i++) {
+		if (pMMIO[i].Limit == 0)
+				return &pMMIO[i];
+	}
+	return 0;
+}
+
+static void FreeMMIO(MMIORANGE* pMMIO)
+{
+	pMMIO->Base = 0;
+	pMMIO->Limit = 0;
+}
+
+static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
+{
+	int i;
+	MMIORANGE * TempRange;
+	for(i=0; i<8; i++)
+	{
+		if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
+		{
+			TempRange = AllocMMIO(pMMIO);
+			if(TempRange == 0) return 0x80000000;
+			TempRange->Base = Limit;
+			TempRange->Limit = pMMIO[i].Limit;
+			TempRange->Attribute = pMMIO[i].Attribute;
+			pMMIO[i].Limit = Base;
+		}
+	}
+	TempRange = AllocMMIO(pMMIO);
+	if(TempRange == 0) return 0x80000000;
+	TempRange->Base = Base;
+	TempRange->Limit = Limit;
+	TempRange->Attribute = Attribute;
+	return 0;
+}
+
+static u8 FinalizeMMIO(MMIORANGE *pMMIO)
+{
+	int i, j, n = 0;
+	for(i=0; i<8; i++)
+	{
+		if (pMMIO[i].Base == pMMIO[i].Limit)
+		{
+			FreeMMIO(&pMMIO[i]);
+			continue;
+		}
+		for(j=0; j<i; j++)
+		{
+			if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
+			{
+				if (pMMIO[i].Base == pMMIO[j].Limit)
+				{
+					pMMIO[j].Limit = pMMIO[i].Limit;
+					 FreeMMIO(&pMMIO[i]);
+				}
+				if (pMMIO[i].Limit == pMMIO[j].Base)
+				{
+					pMMIO[j].Base = pMMIO[i].Base;
+				   FreeMMIO(&pMMIO[i]);
+				}
+			}
+		}
+	}
+	for (i=0; i<8; i++)
+	{
+		if (pMMIO[i].Limit != 0) n++;
+	}
+	return n;
+}
+
+static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
+{
+	CIM_STATUS Status = CIM_UNSUPPORTED;
+	u8 Bus, Dev, Reg, BusStart, BusEnd;
+	u32	Value;
+	device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	device_t tempdev;
+	Value = pci_read_config32(dev0x14, 0x18);
+	BusStart = (Value >> 8) & 0xFF;
+	BusEnd = (Value >> 16) & 0xFF;
+	for(Bus = BusStart; Bus <= BusEnd; Bus++)
+	{
+		for(Dev = 0; Dev <= 0x1f; Dev++)
+		{
+			tempdev = dev_find_slot(Bus, Dev << 3);
+			Value = pci_read_config32(tempdev, 0);
+			printk(BIOS_DEBUG, "Dev ID %x \n", Value);
+			if((Value & 0xffff) == 0x1102)
+			{//Creative
+				//Found Creative SB
+			 	u32	MMIOStart = 0xffffffff;
+				u32 MMIOLimit = 0;
+				for(Reg = 0x10; Reg < 0x20; Reg+=4)
+				{
+					u32	BaseA, LimitA;
+					BaseA = pci_read_config32(tempdev, Reg);
+					Value = BaseA;
+					if(!(Value & 0x01))
+					{
+						Value = Value & 0xffffff00;
+						if(Value !=  0)
+						{
+							if(MMIOStart > Value)
+								MMIOStart = Value;
+							LimitA = 0xffffffff;
+							//WritePCI(PciAddress,AccWidthUint32,&LimitA);
+							pci_write_config32(tempdev, Reg, LimitA);
+							//ReadPCI(PciAddress,AccWidthUint32,&LimitA);
+							LimitA = pci_read_config32(tempdev, Reg);
+							LimitA = Value + (~LimitA + 1);
+							//WritePCI(PciAddress,AccWidthUint32,&BaseA);
+							pci_write_config32(tempdev, Reg, BaseA);
+							if (LimitA > MMIOLimit)
+								MMIOLimit = LimitA;
+						}
+					}
+				}
+				printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+				if (MMIOStart < MMIOLimit)
+				{
+					Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
+					if(Status == CIM_ERROR) return Status;
+				}
+			}
+		}
+	}
+	if(Status == CIM_SUCCESS)
+	{
+		//Lets optimize MMIO
+		if(FinalizeMMIO(pMMIO) > 4)
+		{
+			Status = CIM_ERROR;
+		}
+	}
+
+	return Status;
+}
+
+static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
+{
+	int i, j, n = 7;
+	device_t k8_f1;
+
+	k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+	for(i = 0; i < 8; i++)
+	{
+		int k = 0, MmioReg;
+		u32 Base = 0;
+		u32 Limit = 0;
+		for(j = 0; j < 8; j++)
+		{
+			if (Base < pMMIO[j].Base)
+			{
+				Base = pMMIO[j].Base;
+				k = j;
+			}
+		}
+		if(pMMIO[k].Limit != 0)
+		{
+			if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
+			{
+				Base = 0;
+			}
+			else
+			{
+				Base = pMMIO[k].Base | 0x3;
+				Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
+			}
+			FreeMMIO(&pMMIO[k]);
+		}
+		if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
+		MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
+		n--;
+		//RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
+		pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
+
+		//WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
+		pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
+
+		//WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
+		pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
+	}
+}
+#endif
+
+static void internal_gfx_pci_dev_init(struct device *dev)
+{
+	unsigned char * bpointer;
+	volatile u32 * GpuF0MMReg;
+	volatile u32 * pointer;
+	int i;
+	u16 command;
+	u32 value;
+	u16 deviceid, vendorid;
+	device_t nb_dev = dev_find_slot(0, 0);
+	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
+	static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
+	static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
+	static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
+
+	/* We definetely will use this in future. Just leave it here. */
+	/*struct southbridge_amd_rs780_config *cfg =
+	   (struct southbridge_amd_rs780_config *)dev->chip_info;*/
+
+	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
+	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
+	printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	     deviceid, vendorid);
+
+	command = pci_read_config16(dev, 0x04);
+	command |= 0x7;
+	pci_write_config16(dev, 0x04, command);
+
+	/* Clear vgainfo. */
+	bpointer = (unsigned char *) &vgainfo;
+	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+
+	GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
+
+	/* GFX_InitFBAccess. */
+	value = nbmc_read_index(nb_dev, 0x10);
+	*(GpuF0MMReg + 0x2000/4) = 0x11;
+	*(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
+	*(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
+	*(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
+	*(GpuF0MMReg + 0xF774/4) = 0xffffffff;
+	*(GpuF0MMReg + 0xF770/4) = 0x00000001;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+	*(GpuF0MMReg + 0x200c/4) = 0x00000020;
+	*(GpuF0MMReg + 0x2010/4) = 0x10204810;
+	*(GpuF0MMReg + 0x2010/4) = 0x00204810;
+	*(GpuF0MMReg + 0x2014/4) = 0x10408810;
+	*(GpuF0MMReg + 0x2014/4) = 0x00408810;
+	*(GpuF0MMReg + 0x2414/4) = 0x00000080;
+	*(GpuF0MMReg + 0x2418/4) = 0x84422415;
+	*(GpuF0MMReg + 0x2418/4) = 0x04422415;
+	*(GpuF0MMReg + 0x5490/4) = 0x00000001;
+	*(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
+	/* Force allow LDT_STOP Cool'n'Quiet workaround. */
+	*(GpuF0MMReg + 0x655c/4) |= 1<<4;
+
+	// disable write combining, needed for stability
+	// reference bios does this only for RS780 rev A11
+	// need to figure out why we need it for all revs
+	*(GpuF0MMReg + 0x2000/4) = 0x00000010;
+	*(GpuF0MMReg + 0x2408/4) = 1 << 9;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+
+	/* GFX_InitFBAccess finished. */
+
+#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
+	/* GFX_StartMC. */
+	set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
+	set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
+	set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
+	/* GFX_StartMC finished. */
+#else
+	/* for SP mode. */
+	set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
+	set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
+	set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
+	set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
+	set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
+	nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
+	nbmc_write_index(nb_dev, 0xa5, 0x222222df);
+	nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
+	udelay(10);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
+	udelay(10);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
+	udelay(200);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
+	udelay(500);
+	set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
+	nbmc_write_index(nb_dev, 0xa4, 0x23484576);
+	nbmc_write_index(nb_dev, 0xa5, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+	/* GFX_StartMC finished. */
+
+	/* GFX_SPPowerManagment, don't care for new. */
+	/* Post MC Init table programming. */
+	set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
+
+	/* Do we need Write and Read Calibration? */
+	/* GFX_Init finished. */
+#endif
+
+	/* GFX_InitIntegratedInfo. */
+	/* fill the Integrated Info Table. */
+	vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
+	vgainfo.sHeader.ucTableFormatRevision = 1;
+	vgainfo.sHeader.ucTableContentRevision = 2;
+
+#if (CONFIG_GFXUMA == 0) /* SP mode. */
+	// Side port support is incomplete, do not use it
+	// These parameters must match the motherboard
+	vgainfo.ulBootUpSidePortClock = 667*100;
+	vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
+	vgainfo.ulMinSidePortClock = 333*100;
+#endif
+
+	vgainfo.ulBootUpEngineClock = 500 * 100;	       	// setup option on reference BIOS, 500 is default
+
+	// find the DDR memory frequency
+	if (is_family10h()) {
+		value = pci_read_config32(k8_f2, 0x94);		// read channel 0 DRAM Configuration High Register
+		if (extractbit(value, 14))			// if channel 0 disabled, channel 1 must have memory
+			value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
+	}
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x94);
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
+	}
+
+	/* UMA Channel Number: 1 or 2. */
+	vgainfo.ucUMAChannelNumber = 1;
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x90);
+	if (extractbit(value, 11))  // 128-bit mode
+		vgainfo.ucUMAChannelNumber = 2;
+	}
+	if (is_family10h()) {
+		u32 dch0 = pci_read_config32(k8_f2, 0x94);
+		u32 dch1 = pci_read_config32(k8_f2, 0x194);
+		if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
+			value = pci_read_config32(k8_f2, 0x110);
+			if (extractbit(value, 4))  // ganged mode
+			vgainfo.ucUMAChannelNumber = 2;
+		}
+	}
+      
+	// processor type
+	if (is_family0Fh())
+		vgainfo.ulCPUCapInfo = 3;
+	if (is_family10h())
+		vgainfo.ulCPUCapInfo = 2;
+
+	/* HT speed */
+	value = pci_read_config8(nb_dev, 0xd1);
+	value = ht_freq_lookup [value] * 100;  // HT link frequency in MHz
+	vgainfo.ulHTLinkFreq = value * 100;    // HT frequency in units of 100 MHz
+	vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+
+	if (value <= 1800)
+		vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	else {
+		int sblink, cpuLnkFreqCap, nbLnkFreqCap;
+		value = pci_read_config32(k8_f0, 0x64);
+		sblink = extractbits(value, 8, 10);
+		cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
+		nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
+		if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
+		vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
+	}
+
+	/* HT width. */
+	value = pci_read_config8(nb_dev, 0xcb);
+	vgainfo.usMinDownStreamHTLinkWidth = 
+	vgainfo.usMaxDownStreamHTLinkWidth = 
+	vgainfo.usMinUpStreamHTLinkWidth = 
+	vgainfo.usMaxUpStreamHTLinkWidth =
+	vgainfo.usMinHTLinkWidth =
+	vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
+
+	if (is_family0Fh()) {
+		vgainfo.usUMASyncStartDelay = 322;
+		vgainfo.usUMADataReturnTime = 286;
+	}
+
+	if (is_family10h()) {
+		static u16 t0mult_lookup [] = {10, 50, 200, 2000};
+		int t0time, t0scale;
+		value = pci_read_config32(k8_f0, 0x16c);
+		t0time = extractbits(value, 0, 3);
+		t0scale = extractbits(value, 4, 5);
+		vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
+		vgainfo.usUMASyncStartDelay = 100;
+		if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
+			vgainfo.usUMADataReturnTime = 300;
+			vgainfo.usLinkStatusZeroTime = 6 * 100;   // 6us for GH in HT1 mode
+		}
+		else {
+			int lssel;
+			value = pci_read_config32(nb_dev, 0xac);
+			lssel = extractbits (value, 7, 8);
+			vgainfo.usUMADataReturnTime = 1300;
+			if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
+		}
+	}
+
+	/* Transfer the Table to VBIOS. */
+	pointer = (u32 *)&vgainfo;
+	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
+	{
+#if (CONFIG_GFXUMA == 1)
+		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
+#else
+		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
+#endif
+		*(GpuF0MMReg+1) = *pointer++;
+	}
+
+	/* GFX_InitLate. */
+	{
+		u32 temp;
+		temp = pci_read_config8(dev, 0x4);
+		//temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
+		temp |= 1<<1|1<<2;
+		pci_write_config8(dev, 0x4, temp);
+
+		// if the GFX debug bar is writable, then it has
+		// been programmed and can be safely enabled now
+		temp = pci_read_config32(nb_dev, 0x8c);
+
+		// if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
+		// then enable gfx debug bar (set gxf_debug_decode_enable)
+		if (temp & 0x202)
+			temp |= (1 << 10);
+		pci_write_config32(nb_dev, 0x8c, temp);
+
+	}
+
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
+	/* NB_SetupMGMMIO. */
+
+	/* clear MMIO and CreativeMMIO. */
+	bpointer = (unsigned char *)MMIO;
+	for(i=0; i<sizeof(MMIO); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+	bpointer = (unsigned char *)CreativeMMIO;
+	for(i=0; i<sizeof(CreativeMMIO); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+
+	/* Set MMIO ranges in K8. */
+	/* Set MMIO TOM - 4G. */
+	SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
+	/* Set MMIO for VGA Legacy FB. */
+	SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
+
+	/* Set MMIO for non prefetchable P2P. */
+	temp = pci_read_config32(dev0x14, 0x20);
+	Base32 = (temp & 0x0fff0) << 8;
+	Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+	if(Base32 < Limit32)
+	{
+		Status = GetCreativeMMIO(&CreativeMMIO[0]);
+		if(Status != CIM_ERROR)
+			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+	}
+	/* Set MMIO for prefetchable P2P. */
+	if(Status != CIM_ERROR)
+	{
+		temp = pci_read_config32(dev0x14, 0x24);
+
+		Base32 = (temp & 0x0fff0) <<8;
+		Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+		if(Base32 < Limit32)
+			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+	}
+
+	FinalizeMMIO(&MMIO[0]);
+
+	ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
+	ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
+#endif
+
+	pci_dev_init(dev);
+
+	/* clk ind */
+	clkind_write(dev, 0x08, 0x01);
+	clkind_write(dev, 0x0C, 0x22);
+	clkind_write(dev, 0x0F, 0x0);
+	clkind_write(dev, 0x11, 0x0);
+	clkind_write(dev, 0x12, 0x0);
+	clkind_write(dev, 0x14, 0x0);
+	clkind_write(dev, 0x15, 0x0);
+	clkind_write(dev, 0x16, 0x0);
+	clkind_write(dev, 0x17, 0x0);
+	clkind_write(dev, 0x18, 0x0);
+	clkind_write(dev, 0x19, 0x0);
+	clkind_write(dev, 0x1A, 0x0);
+	clkind_write(dev, 0x1B, 0x0);
+	clkind_write(dev, 0x1C, 0x0);
+	clkind_write(dev, 0x1D, 0x0);
+	clkind_write(dev, 0x1E, 0x0);
+	clkind_write(dev, 0x26, 0x0);
+	clkind_write(dev, 0x27, 0x0);
+	clkind_write(dev, 0x28, 0x0);
+	clkind_write(dev, 0x5C, 0x0);
+}
+
+
+/*
+* Set registers in RS780 and CPU to enable the internal GFX.
+* Please refer to CIM source code and BKDG.
+*/
+
+static void rs780_internal_gfx_enable(device_t dev)
+{
+	u32 l_dword;
+	int i;
+	device_t nb_dev = dev_find_slot(0, 0);
+	msr_t sysmem;
+
+#if (CONFIG_GFXUMA == 0)
+	u32 FB_Start, FB_End;
+#endif
+
+	printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
+
+	sysmem = rdmsr(0xc001001a);
+	printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
+
+	/* The system top memory in 780. */
+	pci_write_config32(nb_dev, 0x90, sysmem.lo);
+	htiu_write_index(nb_dev, 0x30, 0);
+	htiu_write_index(nb_dev, 0x31, 0);
+
+	/* Disable external GFX and enable internal GFX. */
+	l_dword = pci_read_config32(nb_dev, 0x8c);
+	l_dword &= ~(1<<0);
+	l_dword |= 1<<1;
+	pci_write_config32(nb_dev, 0x8c, l_dword);
+
+	/* NB_SetDefaultIndexes */
+	pci_write_config32(nb_dev, 0x94, 0x7f);
+	pci_write_config32(nb_dev, 0x60, 0x7f);
+	pci_write_config32(nb_dev, 0xe0, 0);
+
+	/* NB_InitEarlyNB finished. */
+
+	/* LPC DMA Deadlock workaround? */
+	/* GFX_InitCommon*/
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	l_dword = pci_read_config32(k8_f0, 0x68);
+	l_dword &= ~(3 << 21);
+	l_dword |= (1 << 21);
+	pci_write_config32(k8_f0, 0x68, l_dword);
+
+	/* GFX_InitCommon. */
+	nbmc_write_index(nb_dev, 0x23, 0x00c00010);
+	set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
+	set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
+	set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
+
+#if (CONFIG_GFXUMA == 1)
+	/* GFX_InitUMA. */
+	/* Copy CPU DDR Controller to NB MC. */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
+	for (i = 0; i < 12; i++)
+	{
+		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
+		nbmc_write_index(nb_dev, 0x30 + i, l_dword);
+	}
+
+	l_dword = pci_read_config32(k8_f2, 0x80);
+	nbmc_write_index(nb_dev, 0x3c, l_dword);
+	l_dword = pci_read_config32(k8_f2, 0x94);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
+	l_dword = pci_read_config32(k8_f2, 0x90);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
+   if (is_family10h())
+   {
+	   for (i = 0; i < 12; i++)
+	   {
+		   l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
+		   nbmc_write_index(nb_dev, 0x3d + i, l_dword);
+	   }
+
+	   l_dword = pci_read_config32(k8_f2, 0x180);
+	   nbmc_write_index(nb_dev, 0x49, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x194);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
+	   l_dword = pci_read_config32(k8_f2, 0x190);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
+
+	   l_dword = pci_read_config32(k8_f2, 0x110);
+	   nbmc_write_index(nb_dev, 0x4a, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x114);
+	   nbmc_write_index(nb_dev, 0x4b, l_dword);
+	   l_dword = pci_read_config32(k8_f4, 0x44);
+	   set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
+	   l_dword = pci_read_config32(k8_f1, 0x40);
+	   nbmc_write_index(nb_dev, 0x4c, l_dword);
+	   l_dword = pci_read_config32(k8_f1, 0xf0);
+	   nbmc_write_index(nb_dev, 0x4d, l_dword);
+   }
+
+
+	/* Set UMA in the 780 side. */
+	/* UMA start address, size. */
+	/* The UMA starts at 0xC0000000 of internal RS780 address space
+	    [31:16] addr of last byte | [31:16] addr of first byte
+	*/
+	nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
+	nbmc_write_index(nb_dev, 0x11, uma_memory_base);
+	nbmc_write_index(nb_dev, 0x12, 0);
+	nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
+	/* GFX_InitUMA finished. */
+#else
+	/* GFX_InitSP. */
+	/* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
+
+	/* Enable Async mode. */
+	set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
+	set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
+	/* The last item in AsynchMclkTaskFileIndex. Why? */
+	/* MC_MPLL_CONTROL2. */
+	nbmc_write_index(nb_dev, 0x07, 0x40100028);
+	/* MC_MPLL_DIV_CONTROL. */
+	nbmc_write_index(nb_dev, 0x0b, 0x00000028);
+	/* MC_MPLL_FREQ_CONTROL. */
+	set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
+	/* MC_MPLL_CONTROL3. For PM. */
+	set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
+	/* MPLL_CAL_TRIGGER. */
+	set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
+	udelay(200); /* time is long enough? */
+	set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
+	set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
+	/* MCLK_SRC_USE_MPLL. */
+	set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
+
+	/* Pre Init MC. */
+	nbmc_write_index(nb_dev, 0x01, 0x88108280);
+	set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
+	nbmc_write_index(nb_dev, 0x04, 0x08881018);
+	nbmc_write_index(nb_dev, 0x05, 0x000000bb);
+	nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
+	nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
+	/* MCA_INIT_DLL_PM. */
+	set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
+	nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
+	nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
+	nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
+	nbmc_write_index(nb_dev, 0xb0, 0x88800130);
+	nbmc_write_index(nb_dev, 0xb1, 0x00000040);
+	nbmc_write_index(nb_dev, 0xb4, 0x41247000);
+	nbmc_write_index(nb_dev, 0xb5, 0x00066664);
+	nbmc_write_index(nb_dev, 0xb6, 0x00000022);
+	nbmc_write_index(nb_dev, 0xb7, 0x00000044);
+	nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
+	nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
+	nbmc_write_index(nb_dev, 0xba, 0x55555555);
+	nbmc_write_index(nb_dev, 0xc1, 0x00000000);
+	nbmc_write_index(nb_dev, 0xc2, 0x00000000);
+	nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
+	nbmc_write_index(nb_dev, 0xc4, 0x00066664);
+	nbmc_write_index(nb_dev, 0xc5, 0x00000000);
+	nbmc_write_index(nb_dev, 0xd2, 0x00000022);
+	nbmc_write_index(nb_dev, 0xd3, 0x00000044);
+	nbmc_write_index(nb_dev, 0xd6, 0x00050005);
+	nbmc_write_index(nb_dev, 0xd7, 0x00000000);
+	nbmc_write_index(nb_dev, 0xd8, 0x00700070);
+	nbmc_write_index(nb_dev, 0xd9, 0x00700070);
+	nbmc_write_index(nb_dev, 0xe0, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe1, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe8, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe9, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe0, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe1, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe8, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe9, 0x00180018);
+
+	/* Misc options. */
+	/* Memory Termination. */
+	set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
+#if 0
+	/* Controller Termation. */
+	set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
+#endif
+
+	/* OEM Init MC. 667MHz. */
+	nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
+	nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
+	nbmc_write_index(nb_dev, 0xaa, 0x54400520);
+	nbmc_write_index(nb_dev, 0xab, 0x441460ff);
+	nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
+	set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
+	nbmc_write_index(nb_dev, 0xb2, 0x00000303);
+	set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
+	/* Do it later. */
+	/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
+
+	/* Init PM timing. */
+	for(i=0; i<4; i++)
+	{
+		l_dword = nbmc_read_index(nb_dev, 0xa0+i);
+		nbmc_write_index(nb_dev, 0xc8+i, l_dword);
+	}
+	for(i=0; i<4; i++)
+	{
+		l_dword = nbmc_read_index(nb_dev, 0xa8+i);
+		nbmc_write_index(nb_dev, 0xcc+i, l_dword);
+	}
+	l_dword = nbmc_read_index(nb_dev, 0xb1);
+	set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
+
+	/* Init MC FB. */
+	/* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
+	nbmc_write_index(nb_dev, 0x11, 0x40000000);
+	FB_Start = 0xc00 + 0x080;
+	FB_End = 0xc00 + 0x080;
+	nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
+	set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
+	nbmc_write_index(nb_dev, 0x0f, 0);
+	nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
+#endif
+
+	/* GFX_InitSP finished. */
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations pcie_ops = {
+	.read_resources = rs780_gfx_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs780_gfx_init, */
+	.scan_bus = 0,
+	.enable = rs780_internal_gfx_enable,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * We should list all of them here.
+ * */
+static const struct pci_driver pcie_driver_780 __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
+};
+
+static const struct pci_driver pcie_driver_780c __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780m __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780mc __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780e __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
+};
+static const struct pci_driver pcie_driver_785g __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
+};
+
+/* step 12 ~ step 14 from rpr */
+static void single_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
+
+	/* step 12 training, releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	result = PcieTrainPort(nb_dev, dev, 2);
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
+
+	/* step 13 Power Down Control */
+	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+
+	/* step 13.a Link Training was NOT successful */
+	if (!result) {
+		set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
+		set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
+		if (cfg->gfx_tmds)
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+		else {
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
+			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
+		}
+	} else {		/* step 13.b Link Training was successful */
+		set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
+		reg32 = nbpcie_p_read_index(dev, 0x29);
+		width = reg32 & 0xFF;
+		printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
+			break;
+		case 8:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
+
+	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
+}
+
+static void dual_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
+	struct southbridge_amd_rs780_config *cfg =
+		    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.4.1.2 Dual Port Configuration */
+	set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+	set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+
+	/* 5.7. Training for Device 2 */
+	/* 5.7.1. Releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, dev_ind);
+	/* 5.7.2- 5.7.9. PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, dev_ind);
+
+	/* Power Down Control for Device 2 */
+	/* Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port A */
+		/* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
+		/* Note: I have to disable the slot where there isnt a device,
+		 * otherwise the system will hang. I dont know why. */
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
+
+	} else {		/* step 16.b Link Training was successful */
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
+			break;
+		}
+	}
+}
+
+/* For single port GFX configuration Only
+* width:
+* 	000 = x16
+* 	001 = x1
+*	010 = x2
+*	011 = x4
+*	100 = x8
+*	101 = x12 (not supported)
+*	110 = x16
+*/
+static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
+{
+	u32 reg32;
+	device_t sb_dev;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* step 5.9.1.1 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+
+	/* step 5.9.1.2 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+	/* step 5.9.1.3 */
+	set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
+	/* step 5.9.1.4 */
+	set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
+	/* step 5.9.2.4 */
+	if (0 == cfg->gfx_reconfiguration)
+		set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
+
+	/* step 5.9.1.5 */
+	do {
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+	}
+	while (reg32 & 0x100);
+
+	/* step 5.9.1.6 */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	do {
+		reg32 = pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg32 & VC_NEGOTIATION_PENDING);
+
+	/* step 5.9.1.7 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+	if (((reg32 & 0x70) >> 4) != 0x6) {
+		/* the unused lanes should be powered off. */
+	}
+
+	/* step 5.9.1.8 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
+}
+
+/*
+* GFX Core initialization, dev2, dev3
+*/
+void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg32;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+		    nb_dev, dev, port);
+
+	/* GFX Core Initialization */
+	//if (port == 2) return;
+
+	/* step 2, TMDS, (only need if CMOS option is enabled) */
+	if (cfg->gfx_tmds) {
+	}
+
+#if 1				/* external clock mode */
+	/* table 5-22, 5.9.1. REFCLK */
+	/* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
+	 * REFCLK PAD can be driven by an external source. */
+	/* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
+
+	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+	/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+			       1 << 6 | 1 << 8 | 1 << 10);
+	reg32 = nbmisc_read_index(nb_dev, 0x28);
+	printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
+
+	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
+#else				/* internal clock mode */
+	/* table 5-23, 5.9.1. REFCLK */
+	/* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
+	 * REFCLK PAD can be driven by the SB REFCLK. */
+	/* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
+	 * REFCLK from an external source.*/
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
+
+	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+	/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+			       0);
+	reg32 = nbmisc_read_index(nb_dev, 0x28);
+	printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
+
+	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
+#endif
+
+	/* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
+	/* 5.9.3.1. Increases PLL BW for 6G operation.*/
+	/* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
+	/* skip */
+
+	/* step 5.9.4, reset the GFX link */
+	/* step 5.9.4.1 asserts both calibration reset and global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
+
+	/* step 5.9.4.2 de-asserts calibration reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
+
+	/* step 5.9.4.3 wait for at least 200us */
+	udelay(300);
+
+	/* step 5.9.4.4 de-asserts global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
+
+	/* 5.9.5 Reset PCIE_GFX Slot */
+	/* It is done in mainboard.c */
+	set_pcie_reset();
+	mdelay(1);
+	set_pcie_dereset();
+
+	/* step 5.9.8 program PCIE memory mapped configuration space */
+	/* done by enable_pci_bar3() before */
+
+	/* step 7 compliance state, (only need if CMOS option is enabled) */
+	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+	if (cfg->gfx_compliance) {
+		/* force compliance */
+		set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
+		/* release hold training for device 2. GFX initialization is done. */
+		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
+		printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
+		return;
+	}
+
+	/* 5.9.12 Core Initialization. */
+	/* 5.9.12.1 sets RCB timeout to be 25ms */
+	/* 5.9.12.2. RCB Cpl timeout on link down. */
+	set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
+
+	/* step 5.9.12.3 disables slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
+
+	/* step 5.9.12.4 sets DMA payload size to 64 bytes */
+	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
+	/* 5.9.12.5. Blocks DMA traffic during C3 state. */
+	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+
+	/* 5.9.12.6. Disables RC ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
+
+	/* Enabels TLP flushing. */
+	/* Note: It is got from RS690. The system will hang without this action. */
+	set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+	/* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
+	set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
+
+	/* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+	/* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
+
+	/* 5.9.12.10 Sets the timer in Config state from 20us to */
+	/* 5.9.12.11 De-asserts RX_EN in L0s. */
+	/* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
+	 * recovery parameter when lane is in electrical idle in L0s.*/
+	set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
+
+	/* 5.9.12.13. Turns off offset calibration. */
+	/* 5.9.12.14. Enables Rx Clock gating in CDR */
+	set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
+
+	/* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
+	set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
+
+	/* 5.9.12.16. Lets PI use Electrical Idle from PHY when
+	 * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
+	set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
+
+	/* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+
+	/* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
+	 * acknowledged a request to go to L1. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+	/* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
+
+	/* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
+	set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
+
+	/* 5.9.12.21. Sets Electrical Idle Threshold. */
+	set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
+
+	/* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
+	 * Only if CMOS Option in section. skip */
+
+	/* 5.9.12.23. Disables GEN2 capability of the device. */
+	set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+
+	/* 5.9.12.24.Disables advertising Upconfigure Support. */
+	set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+
+	/* 5.9.12.25. No comment in RPR. */
+	set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
+
+	/* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
+	 * speed are supported */
+	set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
+
+	/* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
+	if (get_nb_rev(nb_dev) == REV_RS780_A12)			/* A12 */
+		set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
+
+	/* 5.9.12.28 Hides and disables the completion timeout method. */
+	set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
+
+	/* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
+	/* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
+
+	/* 5.9.12.30. Set TX arbitration algorithm to round robin */
+	set_pcie_enable_bits(nb_dev, 0x1C,
+			     1 << 0 | 0x1F << 1 | 0x1F << 6,
+			     1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+	/* Single-port/Dual-port configureation. */
+	switch (cfg->gfx_dual_slot) {
+	case 0:
+		/* step 1, lane reversal (only need if build config option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+		}
+		printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+
+		printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+		if((dev->path.pci.devfn >> 3) == 2) {
+			single_port_configuration(nb_dev, dev);
+		} else {
+			set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+			printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
+		}
+
+		break;
+	case 1:
+		/* step 1, lane reversal (only need if build config option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+		}
+		printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+		/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+		/* AMD calls the configuration CrossFire */
+		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+		printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+		printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+		dual_port_configuration(nb_dev, dev);
+		break;
+
+	case 2:
+
+		if(is_dev3_present()){
+			/* step 1, lane reversal (only need if CMOS option is enabled) */
+			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+			}
+			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+			/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+			/* AMD calls the configuration CrossFire */
+			set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+			printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+
+			printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+			dual_port_configuration(nb_dev, dev);
+
+		}else{
+			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+			}
+			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+
+			if((dev->path.pci.devfn >> 3) == 2)
+				single_port_configuration(nb_dev, dev);
+			else{
+				set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+				printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
+			    }
+		}
+
+	default:
+		printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
+		break;
+	}
+}

Copied: trunk/src/southbridge/amd/rs780/ht.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/ht.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "rs780.h"
+
+/* for UMA internal graphics */
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
+{
+	device_t cpu_f0;
+	u8 reg;
+
+	cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21);
+
+	reg = nbpcie_p_read_index(sb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(sb_dev, 0x10, reg);
+
+	reg = nbpcie_p_read_index(nb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(nb_dev, 0x10, reg);
+
+	/* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
+	 * Set this bit to avoid a deadlock condition. */
+	reg = htiu_read_index(nb_dev, 0x6);
+	reg |= 0x1000000;	/* bit26 */
+	htiu_write_index(nb_dev, 0x6, reg);
+}
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/*
+	 * 1 is APIC enable
+	 * 18 is enable nb to accept A4 interrupt request from SB.
+	 */
+	dword = pci_read_config32(dev, 0x4C);
+	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
+	pci_write_config32(dev, 0x4C, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = pcie_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_RS780_HT,
+};

Copied: trunk/src/southbridge/amd/rs780/pcie.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c)
@@ -0,0 +1,392 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs780.h"
+
+/*------------------------------------------------
+* Global variable
+------------------------------------------------*/
+PCIE_CFG AtiPcieCfg = {
+	PCIE_ENABLE_STATIC_DEV_REMAP,	/* Config */
+	0,			/* ResetReleaseDelay */
+	0,			/* Gfx0Width */
+	0,			/* Gfx1Width */
+	0,			/* GfxPayload */
+	0,			/* GppPayload */
+	0,			/* PortDetect, filled by GppSbInit */
+	0,			/* PortHp */
+	0,			/* DbgConfig */
+	0,			/* DbgConfig2 */
+	0,			/* GfxLx */
+	0,			/* GppLx */
+	0,			/* NBSBLx */
+	0,			/* PortSlotInit */
+	0,			/* Gfx0Pwr */
+	0,			/* Gfx1Pwr */
+	0			/* GppPwr */
+};
+
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
+static void ValidatePortEn(device_t nb_dev);
+
+static void ValidatePortEn(device_t nb_dev)
+{
+}
+
+/*****************************************************************
+* Compliant with CIM_33's PCIEPowerOffGppPorts
+* Power off unused GPP lines
+*****************************************************************/
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg;
+	u16 state_save;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+	u8 state = cfg->port_enable;
+
+	if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
+		state &= AtiPcieCfg.PortDetect;
+	state = ~state;
+	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
+	state_save = state << 17;
+	state &= !(AtiPcieCfg.PortHp);
+	reg = nbmisc_read_index(nb_dev, 0x0c);
+	reg |= state;
+	nbmisc_write_index(nb_dev, 0x0c, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x08);
+	reg |= state_save;
+	nbmisc_write_index(nb_dev, 0x08, reg);
+
+	if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
+	    && !(AtiPcieCfg.
+		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
+			   PCIE_GFX_COMPLIANCE))) {
+	}
+	/* step 3 Power Down Control for Southbridge */
+	reg = nbpcie_p_read_index(dev, 0xa2);
+
+	switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
+	case 1:
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+		break;
+	case 2:
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+		break;
+	default:
+		break;
+	}
+}
+
+/**********************************************************************
+**********************************************************************/
+static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.5.7.1-3 enables GPP reconfiguration */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg |=
+	    (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
+	     RECONFIG_GPPSB_ATOMIC_RESET);
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* 5.5.7.4a. De-asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg |= 1 << 31;
+	nbmisc_write_index(nb_dev, 0x66, reg);
+	/* 5.5.7.4b. sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x67);
+	reg &= 0xFFFFff0f;		/* clean */
+	reg |= cfg->gppsb_configuration << 4;
+	nbmisc_write_index(nb_dev, 0x67, reg);
+
+#if 1
+	/* NOTE:
+	 * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way,
+	 * a x4 device in port B (dev 4) of Configuration B can only be detected
+	 * as x1, instead of x4. When the port B is being trained, the
+	 * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. We have
+	 * to set the PCIEIND:0x65 as 0xE0E0 and reset the slot. Then the card
+	 * seems to work in x1 mode.
+	 * In the 2nd way below, we do the 5 & 6 before 4c. it conforms the
+	 * CIMx 4.3.0. It conflicts with RPR. But based on the test result I've
+	 * made so far, I haven't found any mistake.
+	 */
+	/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg &= ~(1 << 31);
+	nbmisc_write_index(nb_dev, 0x66, reg);
+
+	/* 5.5.7.5-6. read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+#else
+	/* 5.5.7.5-6. read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg &= ~(1 << 31);
+	nbmisc_write_index(nb_dev, 0x66, reg);
+#endif
+	/* 5.5.7.7. delay 1ms */
+	mdelay(1);
+
+	/* 5.5.7.8. waits until SB has trained to L0, poll for bit0-5 = 0x10 */
+	do {
+		reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
+		reg &= 0x3f;	/* remain LSB [5:0] bits */
+	} while (LC_STATE_RECONFIG_GPPSB != reg);
+
+	/* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
+	do {
+		reg =
+		    pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg & VC_NEGOTIATION_PENDING);
+}
+
+static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.6.2.1. De-asserts STRAP_BIF_all_valid for PCIE-GPP core */
+	reg = nbmisc_read_index(nb_dev, 0x22);
+	reg |= 1 << 14;
+	nbmisc_write_index(nb_dev, 0x22, reg);
+	/* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x2D);
+	reg &= ~(0xF << 7);		/* clean */
+	reg |= cfg->gpp_configuration << 7;
+	nbmisc_write_index(nb_dev, 0x2D, reg);
+	/* 5.6.2.3. Asserts STRAP_BIF_all_valid for PCIE-GPP core */
+	reg = nbmisc_read_index(nb_dev, 0x22);
+	reg &= ~(1 << 14);
+	nbmisc_write_index(nb_dev, 0x22, reg);
+}
+
+/*****************************************************************
+* The rs780 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
+* Space to a 256MB range within the first 4GB of addressable memory.
+*****************************************************************/
+void enable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
+	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
+
+	pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS);	/* PCIEMiscInit */
+	pci_write_config32(nb_dev, 0x20, 0x00000000);
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
+	ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************************************
+* We should disable bar3 when we want to exit rs780_enable, because bar3 will be
+* remapped in set_resource later.
+*****************************************************************/
+void disable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
+	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0);	/* disable bar3 decode */
+	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEGPPInit
+* nb_dev:
+*	root bridge struct
+* dev:
+*	p2p bridge struct
+* port:
+*	p2p bridge number, 4-10
+*****************************************/
+void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 gfx_gpp_sb_sel;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev->path.pci.devfn, dev->path.pci.devfn, port);
+
+	gfx_gpp_sb_sel = port >= 4 && port <= 8 ?
+				PCIE_CORE_INDEX_GPPSB :		/* 4,5,6,7,8 */
+				PCIE_CORE_INDEX_GPP;		/* 9,10 */
+	/* init GPP core */
+	/* 5.10.8.3. Disable slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8,
+			     1 << 8);
+	/* 5.10.8.7. PCIE initialization 5.10.2: rpr 2.12*/
+	set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0);	/* no description in datasheet. */
+
+	/* init GPPSB port. rpr 5.10.8 */
+	/* 5.10.8.1-5.10.8.2. Sets RCB timeout to be 100ms/4=25ms by setting bits[18:16] to 3 h4
+	 * and shortens the enumeration timer by setting bit[19] to 1
+	 */
+	set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0x4 << 16 | 1 << 19);
+	/* 5.10.8.4. Sets DMA payload size to 64 bytes. */
+	set_pcie_enable_bits(nb_dev, 0x10 | gfx_gpp_sb_sel, 7 << 10, 4 << 10);
+	/* 5.10.8.6. Disable RC ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 9, 1 << 9);
+	/* 5.10.8.7. Ignores DLLs druing L1 */
+	set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0);
+	/* 5.10.8.8. Prevents LCto go from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+	/* 5.10.8.9. Sets timer in Config state from 20us to 1us.
+	 * 5.10.8.10. De-asserts RX_EN in L0s
+	 * 5.10.8.11. Enables de-assertion of PG2RX_CR_EN to lock clock recovery parameter when .. */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 <<23 | 1 << 19 | 1 << 28);
+	/* 5.10.8.12. Turns off offset calibration */
+	/* 5.10.8.13. Enables Rx  Clock gating in CDR */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 14 | 1 << 26, 1 << 14 | 1 << 26); /* 4,5,6,7 */
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x24, 1 << 29 | 1 << 28, 1 << 29 | 1 << 28); /* 9,10 */
+	/* 5.10.8.14. Sets number of TX Clocks to drain TX Pipe to 3 */
+	set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
+	/* 5.10.8.15. empty */
+	/* 5.10.8.16. P_ELEC_IDLE_MODE */
+	set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 0x3 << 14, 0x2 << 14);
+	/* 5.10.8.17. LC_BLOCK_EL_IDLE_IN_L0 */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+	/* 5.10.8.18. LC_DONT_GO_TO_L0S_IFL1_ARMED */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+	/* 5.10.8.19. RXP_REALIGN_ON_EACH_TSX_OR_SKP */
+	set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 1 << 28, 0 << 28);
+	/* 5.10.8.20. Bypass lane de-skew logic if in x1 */
+	set_pcie_enable_bits(nb_dev, 0xC2 | gfx_gpp_sb_sel, 1 << 14, 1 << 14);
+	/* 5.10.8.21. sets electrical idle threshold. */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x6A, 3 << 22, 2 << 22);
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16);
+
+	/* 5.10.8.22. Disable GEN2 */
+	/* TODO: should be 2 seperated cases. */
+	set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5);
+	set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 5, 0 << 5);
+	/* 5.10.8.23. Disables GEN2 capability of the device. RPR says enable? No! */
+	set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+	/* 5.10.8.24. Disable advertising upconfigure support. */
+	set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+	/* 5.10.8.25-26. STRAP_BIF_DSN_EN */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 19, 0 << 19);
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 3, 0 << 3);
+	/* 5.10.8.27-28. */
+	set_pcie_enable_bits(nb_dev, 0xC1 | gfx_gpp_sb_sel, 1 << 0 | 1 << 2, 1 << 0 | 0 << 2);
+	/* 5.10.8.29. Uses the bif_core de-emphasis strength by default. */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) {
+		set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10, 1 << 10);
+		set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 29, 1 << 29);
+	}
+	else {
+		set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 30, 1 << 30);
+	}
+	/* 5.10.8.30. Set TX arbitration algorithm to round robin. */
+	set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel,
+			     1 << 0 | 0x1F << 1 | 0x1F << 6,
+			     1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+	/* check compliance rpr step 2.1*/
+	if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
+		u32 tmp;
+		tmp = nbmisc_read_index(nb_dev, 0x67);
+		tmp |= 1 << 3;
+		nbmisc_write_index(nb_dev, 0x67, tmp);
+	}
+
+	/* step 5: dynamic slave CPL buffer allocation. Disable it, otherwise linux hangs. Why? */
+	/* set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 11, 1 << 11); */
+
+	/* step 5a: Training for GPP devices */
+	/* init GPP */
+	switch (port) {
+	case 4:		/* GPP */
+	case 5:
+	case 6:
+	case 7:
+	case 9:
+	case 10:
+		/* 5.10.8.5. Blocks DMA traffic during C3 state */
+		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+		/* Enabels TLP flushing */
+		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+		/* check port enable */
+		if (cfg->port_enable & (1 << port)) {
+			PcieReleasePortTraining(nb_dev, dev, port);
+			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+				u8 res = PcieTrainPort(nb_dev, dev, port);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
+				if (res) {
+					AtiPcieCfg.PortDetect |= 1 << port;
+				}
+			}
+		}
+		break;
+	case 8:		/* SB */
+		break;
+	}
+	PciePowerOffGppPorts(nb_dev, dev, port);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEConfigureGPPCore
+*****************************************/
+void config_gpp_core(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	reg = nbmisc_read_index(nb_dev, 0x20);
+	if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
+		reg &= 0xfffffffd;	/* set bit1 = 0 */
+	else
+		reg |= 0x2;	/* set bit1 = 1 */
+	nbmisc_write_index(nb_dev, 0x20, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x67);	/* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
+	if (cfg->gppsb_configuration != ((reg >> 4) & 0xf))
+		switching_gppsb_configurations(nb_dev, sb_dev);
+	reg = nbmisc_read_index(nb_dev, 0x2D);	/* get STRAP_BIF_LINK_CONFIG_GPP at bit 7-10 */
+	if (cfg->gpp_configuration != ((reg >> 7) & 0xf))
+		switching_gpp_configurations(nb_dev, sb_dev);
+	ValidatePortEn(nb_dev);
+}

Copied: trunk/src/southbridge/amd/rs780/rev.h (from r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/rev.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __RS780_REV_H__
+#define __RS780_REV_H__
+
+#define	REV_RS780_A11	0
+#define	REV_RS780_A12	1
+#define	REV_RS780_A13	2
+
+#endif	/* __RS780_REV_H__ */

Modified: trunk/src/southbridge/amd/rs780/rs780.h
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780.h	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs780/rs780.h	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <device/pci_ids.h>
 #include "chip.h"
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBMISC_INDEX 	0x60
 #define NBHTIU_INDEX 	0x94

Modified: trunk/src/southbridge/amd/sb600/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb600/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb600/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,11 +1,11 @@
 driver-y += sb600.c
-driver-y += sb600_usb.c
-driver-y += sb600_lpc.c
-driver-y += sb600_sm.c
-driver-y += sb600_ide.c
-driver-y += sb600_sata.c
-driver-y += sb600_hda.c
-driver-y += sb600_ac97.c
-driver-y += sb600_pci.c
-ramstage-y += sb600_reset.c
-romstage-y += sb600_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += ac97.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c

Copied: trunk/src/southbridge/amd/sb600/ac97.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ac97audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+/*	.enable           = sb600_enable, */
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ac97audio_driver __pci_driver = {
+	.ops = &ac97audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_ACI,
+};
+
+static struct device_operations ac97modem_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+/*	.enable           = sb600_enable, */
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ac97modem_driver __pci_driver = {
+	.ops = &ac97modem_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_MCI,
+};

Modified: trunk/src/southbridge/amd/sb600/bootblock.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb600/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/amd/sb600/sb600_enable_rom.c"
+#include "southbridge/amd/sb600/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied and modified: trunk/src/southbridge/amd/sb600/early_setup.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -20,7 +20,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */

Copied: trunk/src/southbridge/amd/sb600/enable_rom.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c)
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/*
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The SB600 power-on default is to map 256K ROM space.
+ *
+ * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
+ */
+static void sb600_enable_rom(void)
+{
+	u8 reg8;
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
+				       PCI_DEVICE_ID_ATI_SB600_LPC), 0);
+
+	/* Decode variable LPC ROM address ranges 1 and 2. */
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= (1 << 3) | (1 << 4);
+	pci_write_config8(dev, 0x48, reg8);
+
+	/* LPC ROM address range 1: */
+	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
+	pci_write_config16(dev, 0x68, 0x000e);
+	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+	pci_write_config16(dev, 0x6a, 0x000f);
+
+	/* LPC ROM address range 2: */
+	/*
+	 * Enable LPC ROM range start at:
+	 * 0xfff8(0000): 512KB
+	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
+	 */
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	/* Enable LPC ROM range end at 0xffff(ffff). */
+	pci_write_config16(dev, 0x6e, 0xffff);
+}

Copied: trunk/src/southbridge/amd/sb600/enable_usbdebug.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/enable_usbdebug.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "sb600.h"
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+	/* TODO: Allow changing the physical USB port used as Debug Port. */
+}
+
+void sb600_enable_usbdebug(unsigned int port)
+{
+	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+
+	/* Select the requested physical USB port (1-15) as the Debug Port. */
+	set_debug_port(port);
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+}

Copied: trunk/src/southbridge/amd/sb600/hda.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/hda.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c)
@@ -0,0 +1,331 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "sb600.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 dword;
+	int count;
+
+	/* Write (val & ~mask) to port */
+	val &= mask;
+	dword = read32(port);
+	dword &= ~mask;
+	dword |= val;
+	write32(port, dword);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		dword = read32(port);
+		dword &= mask;
+	} while ((dword != val) && --count);
+
+	/* Timeout occurred */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static u32 codec_detect(u32 base)
+{
+	u32 dword;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Delay for 1 ms since the BKDG does */
+	mdelay(1);
+
+	/* Read in Codec location (BAR + 0xe)[3..0]*/
+	dword = read32(base + 0xe);
+	dword &= 0x0F;
+	if (!dword)
+		goto no_codec;
+
+	return dword;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "No codec!\n");
+	return 0;
+}
+
+static u32 cim_verb_data[] = {
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+/* 1 */
+	0x01571c12,
+	0x01571d10,
+	0x01571e01,
+	0x01571f01,
+/* 2 */
+	0x01671c11,
+	0x01671d60,
+	0x01671e01,
+	0x01671f01,
+/* 3 */
+	0x01771c14,
+	0x01771d20,
+	0x01771e01,
+	0x01771f01,
+/* 4 */
+	0x01871c30,
+	0x01871d90,
+	0x01871ea1,
+	0x01871f01,
+/* 5 */
+	0x01971cf0,
+	0x01971d11,
+	0x01971e11,
+	0x01971f41,
+/* 6 */
+	0x01a71c80,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+/* 7 */
+	0x01b71cf0,
+	0x01b71d11,
+	0x01b71e11,
+	0x01b71f41,
+/* 8 */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+/* 9 */
+	0x01d71cf0,
+	0x01d71d11,
+	0x01d71e11,
+	0x01d71f41,
+/* 10 */
+	0x01e71c50,
+	0x01e71d11,
+	0x01e71e44,
+	0x01e71f01,
+/* 11 */
+	0x01f71c60,
+	0x01f71d61,
+	0x01f71ec4,
+	0x01f71f01,
+};
+
+static u32 find_verb(u32 viddid, u32 ** verb)
+{
+	device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
+	struct southbridge_amd_sb600_config *cfg =
+	    (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
+	printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
+	printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
+	printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
+	if (!cfg)
+		return 0;
+	if (viddid != cfg->hda_viddid)
+		return 0;
+	*verb = (u32 *) cim_verb_data;
+	return sizeof(cim_verb_data) / sizeof(u32);
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 dword=read32(base +  HDA_ICII_REG);
+		if (!(dword & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+static int wait_for_valid(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		u32 dword = read32(base + HDA_ICII_REG);
+		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return 1;
+}
+
+static void codec_init(u32 base, int addr)
+{
+	u32 dword;
+	u32 *verb;
+	u32 verb_size;
+	int i;
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	dword = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, dword);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	dword = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
+	verb_size = find_verb(dword, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "No verb!\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "verb loaded!\n");
+}
+
+static void codecs_init(u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(base, i);
+	}
+}
+
+static void hda_init(struct device *dev)
+{
+	u8 byte;
+	u32 dword;
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	device_t sm_dev;
+
+	/* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
+	pm_iowrite(0x59, 0xB);
+
+	/* Find the SMBus */
+	/* FIXME: Need to find out why the call below crashes. */
+	/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB600_SM, 0);*/
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
+	pci_write_config32(sm_dev, 0xf8, 0x00);
+	pci_write_config8(sm_dev, 0xfc, 0xAA);
+	/* Set INTA - SMBus 0x63 [2..0] */
+	byte = pci_read_config8(sm_dev, 0x63);
+	byte &= ~0x7;
+	byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
+	pci_write_config8(sm_dev, 0x63, byte);
+
+	/* Program the 2C to 0x437b1002 */
+	dword = 0x437b1002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* Read in BAR */
+	/* Is this right? HDA allows for a 64-bit BAR
+	 * but this is only setup for a 32-bit one
+	 */
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations hda_audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	/*.enable           = sb600_enable, */
+	.init = hda_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver hdaaudio_driver __pci_driver = {
+	.ops = &hda_audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_HDA,
+};

Copied: trunk/src/southbridge/amd/sb600/ide.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c)
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static void ide_init(struct device *dev)
+{
+	/* Enable ide devices so the linux ide driver will work */
+	u32 dword;
+	u8 byte;
+
+	/* RPR10.1 disable MSI */
+	dword = pci_read_config32(dev, 0x70);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x70, dword);
+
+	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
+	byte = pci_read_config8(dev, 0x54);
+	byte |= 0xf;
+	pci_write_config8(dev, 0x54, byte);
+
+	/* Enable I/O Access&& Bus Master */
+	dword = pci_read_config16(dev, 0x4);
+	dword |= 1 << 2;
+	pci_write_config16(dev, 0x4, dword);
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.scan_bus = 0,
+	/* .enable           = sb600_enable, */
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_IDE,
+};

Copied: trunk/src/southbridge/amd/sb600/lpc.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c)
@@ -0,0 +1,225 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "sb600.h"
+
+static void lpc_init(device_t dev)
+{
+	u8 byte;
+	u32 dword;
+	device_t sm_dev;
+
+	/* Enable the LPC Controller */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	dword = pci_read_config32(sm_dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(sm_dev, 0x64, dword);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* RPR 7.2 Enable DMA transaction on the LPC bus */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 7.3 Disable the timeout mechanism on LPC */
+	byte = pci_read_config8(dev, 0x48);
+	byte &= ~(1 << 7);
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 7.5 Disable LPC MSI Capability */
+	byte = pci_read_config8(dev, 0x78);
+	byte &= ~(1 << 1);
+	pci_write_config8(dev, 0x78, byte);
+
+}
+
+static void sb600_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+static void sb600_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+					printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		pci_write_config16(dev, 0x64, reg_var[0]);
+		break;
+	}
+}
+
+static void sb600_lpc_enable_resources(device_t dev)
+{
+	pci_dev_enable_resources(dev);
+	sb600_lpc_enable_childrens_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations lpc_ops = {
+	.read_resources = sb600_lpc_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = sb600_lpc_enable_resources,
+	.init = lpc_init,
+	.scan_bus = scan_static_bus,
+	/* .enable           = sb600_enable, */
+	.ops_pci = &lops_pci,
+};
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_LPC,
+};

Copied: trunk/src/southbridge/amd/sb600/pci.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c)
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static void pci_init(struct device *dev)
+{
+	u32 dword;
+	u16 word;
+	u8 byte;
+
+	/* RPR 4.1 Enables the PCI-bridge subtractive decode */
+	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR4.2 PCI-bridge upstream dual address window */
+	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR 4.3 PCI bus 64-byte DMA read access */
+	/* Enhance the PCI bus DMA performance */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 4;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
+	/* The size of the writes will be set in the Cacheline Register */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 1;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
+	pci_write_config8(dev, 0x0D, 0x40);
+	pci_write_config8(dev, 0x1B, 0x40);
+
+	/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 6;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.8 Adjusts the GNT# de-assertion time */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 4.9 Fast Back to Back transactions support */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 2;
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 4.10 Enable Lock Operation */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 3;
+	pci_write_config8(dev, 0x48, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.11 Enable additional optional PCI clock */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 8;
+	pci_write_config16(dev, 0x64, word);
+
+	/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
+	byte = pci_read_config8(dev, 0x64);
+	byte &= 0xcf;
+	pci_write_config8(dev, 0x64, byte);
+
+	/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 18);
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.13 Enable One-Prefetch-Channel Mode */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.15 Disable PCIB MSI Capability */
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 3);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* rpr4.16 Adjusting CLKRUN# */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 15);
+	pci_write_config32(dev, 0x64, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
+	/* .enable           = sb600_enable, */
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_PCI,
+};

Copied: trunk/src/southbridge/amd/sb600/reset.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <reset.h>
+
+#include "northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/amd/sb600/sata.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c)
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "sb600.h"
+
+static int sata_drive_detect(int portnum, u16 iobar)
+{
+	u8 byte, byte2;
+	int i = 0;
+	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
+		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
+		((byte2 & 0x88) != 0)) {
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
+		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+			/* This will happen at the first iteration of this loop
+			 * if the first SATA port is unpopulated and the
+			 * second SATA port is populated.
+			 */
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
+				"retrying init\n", i * 10);
+			return 1;
+		} else
+			printk(BIOS_SPEW, "drive detection not yet completed, "
+				"waiting...\n");
+		mdelay(10);
+		i++;
+	}
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
+	return 0;
+}
+
+static void sata_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u32 sata_bar5;
+	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+	int i, j;
+
+	struct southbridge_ati_sb600_config *conf;
+	conf = dev->chip_info;
+
+	device_t sm_dev;
+	/* SATA SMBus Disable */
+	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Disable SATA SMBUS */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 1);
+	/* Enable SATA and power saving */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 0);
+	byte |= (1 << 5);
+	pci_write_config8(sm_dev, 0xad, byte);
+	/* Set the interrupt Mapping to INTG# */
+	byte = pci_read_config8(sm_dev, 0xaf);
+	byte = 0x6 << 2;
+	pci_write_config8(sm_dev, 0xaf, byte);
+
+	/* get base address */
+	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
+	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
+	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
+	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
+	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
+
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+
+	/* Program the 2C to 0x43801002 */
+	dword = 0x43801002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* SERR-Enable */
+	word = pci_read_config16(dev, 0x04);
+	word |= (1 << 8);
+	pci_write_config16(dev, 0x04, word);
+
+	/* Dynamic power saving */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Set SATA Operation Mode, Set to IDE mode */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 0);
+	byte |= (1 << 4);
+	pci_write_config8(dev, 0x40, byte);
+
+	dword = 0x01018f00;
+	pci_write_config32(dev, 0x8, dword);
+
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Enable the SATA watchdog counter */
+	byte = pci_read_config8(dev, 0x44);
+	byte |= (1 << 0);
+	pci_write_config8(dev, 0x44, byte);
+
+	/* Program the watchdog counter to 0x10 */
+	byte = 0x10;
+	pci_write_config8(dev, 0x46, byte);
+
+	/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
+	word = 0x2c00;
+	pci_write_config16(dev, 0x86, word);
+
+	/* RPR6.5 Program the Phy Tuning4Ports */
+	dword = 0x00B401D6;
+	pci_write_config32(dev, 0x88, dword);
+	pci_write_config32(dev, 0x8c, dword);
+	pci_write_config32(dev, 0x90, dword);
+	pci_write_config32(dev, 0x94, dword);
+
+	byte = 0xB8;
+	pci_write_config8(dev, 0xA5, byte);
+	pci_write_config8(dev, 0xAD, byte);
+	pci_write_config8(dev, 0xB5, byte);
+	pci_write_config8(dev, 0xBD, byte);
+
+	/* RPR 6.8  */
+	word = pci_read_config16(dev, 0x42);
+	word |= 1 << 7;
+	pci_write_config16(dev, 0x42, word);
+	/* RPR 6.9  */
+	dword = pci_read_config32(dev, 0x40);
+	dword |= 1 << 25;
+	pci_write_config32(dev, 0x40, dword);
+
+	/* Enable the I/O, MM, BusMaster access for SATA */
+	byte = pci_read_config8(dev, 0x4);
+	byte |= 7 << 0;
+	pci_write_config8(dev, 0x4, byte);
+
+	/* RPR6.6 SATA drive detection. */
+	/* Use BAR5+0x128,BAR0 for Primary Slave */
+	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+	/* Use BAR5+0x228,BAR2 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
+
+	for (i = 0; i < 4; i++) {
+		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+		byte &= 0xF;
+
+		if( byte == 0x1 ) {
+			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
+			/* Try to do something about it. */
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
+
+			/* Read in Port-N Serial ATA Control Register */
+			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+
+			/* Set Reset Bit and 1.5g bit */
+			byte |= 0x11;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Clear Reset Bit */
+			byte &= ~0x01;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Reread status */
+			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+			byte &= 0xF;
+		}
+
+		if (byte == 0x3) {
+			for (j = 0; j < 10; j++) {
+				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
+					break;
+			}
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master",
+					(j == 10) ? "not " : "",
+					(j == 10) ? j : j + 1);
+		} else {
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master", i);
+		}
+	}
+
+	/* Below is CIM InitSataLateFar */
+	/* Enable interrupts from the HBA  */
+	byte = read8(sata_bar5 + 0x4);
+	byte |= 1 << 1;
+	write8((sata_bar5 + 0x4), byte);
+
+	/* Clear error status */
+	write32((sata_bar5 + 0x130), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x230), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+
+	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+	/* word = 0x0000; */
+	/* word = pm_ioread(0x28); */
+	/* byte = pm_ioread(0x29); */
+	/* word |= byte<<8; */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
+	/* write32(word, 0x80000000); */
+}
+
+static struct pci_operations lops_pci = {
+	/* .set_subsystem = pci_dev_set_subsystem, */
+};
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	/* .enable           = sb600_enable, */
+	.init = sata_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_SATA,
+};

Copied and modified: trunk/src/southbridge/amd/sb600/sm.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_sm.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_sm.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/sm.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 

Copied and modified: trunk/src/southbridge/amd/sb600/smbus.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "sb600_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {

Copied: trunk/src/southbridge/amd/sb600/smbus.h (from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SB600_SMBUS_H
+#define SB600_SMBUS_H
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+#define AX_INDXC  0
+#define AX_INDXP  1
+#define AXCFG     2
+#define ABCFG     3
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx(0, (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)	\
+	alink_ax_indx(1, (reg), (mask), (val))
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+
+#endif

Copied: trunk/src/southbridge/amd/sb600/usb.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c)
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <usbdebug.h>
+#include <arch/io.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+
+	/* Enable OHCI0-4 and EHCI Controllers */
+	device_t sm_dev;
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	byte = pci_read_config8(sm_dev, 0x68);
+	byte |= 0x3F;
+	pci_write_config8(sm_dev, 0x68, byte);
+
+	/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
+	byte = pm_ioread(0x61);
+	byte |= 1 << 6;
+	pm_iowrite(0x61, byte);
+	byte = pm_ioread(0x65);
+	byte |= 1 << 2;
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.3 Support USB device wakeup from the S4/S5 state */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 0);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.6 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
+	byte = pm_ioread(0x65);
+	byte |= (1 << 4);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.11 Disable OHCI MSI Capability */
+	word = pci_read_config16(dev, 0x40);
+	word |= (0x1F << 8);
+	pci_write_config16(dev, 0x40, word);
+
+	/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature  */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR 5.12 Enable prevention of OHCI accessing the invalid system memory address range */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 15;
+	pci_write_config16(dev, 0x50, word);
+
+	/* RPR 5.15 Disable SMI handshake in between USB and ACPI for USB legacy support. */
+	/* The BIOS should always set this bit to prevent the malfunction on USB legacy keyboard/mouse support */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x50, word);
+}
+
+static void usb_init2(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u32 usb2_bar0;
+	/* dword = pci_read_config32(dev, 0xf8); */
+	/* dword |= 40; */
+	/* pci_write_config32(dev, 0xf8, dword); */
+
+	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+
+	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
+	dword = 0x00020F00;
+	write32(usb2_bar0 + 0xC0, dword);
+
+	/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
+	dword = 0x00200040;
+	write32(usb2_bar0 + 0xA4, dword);
+
+	/* RPR5.9 Disable the EHCI Dynamic Power Saving feature */
+	word = read16(usb2_bar0 + 0xBC);
+	word &= ~(1 << 12);
+	write16(usb2_bar0 + 0xBC, word);
+
+	/* RPR5.10 Disable EHCI MSI support */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR5.13 Disable C3 time enhancement feature */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 28);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */
+	byte = pci_read_config8(dev, 0x54);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x54, byte);
+}
+
+static void usb_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	/*.enable           = sb600_enable, */
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_0_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_0,
+};
+static const struct pci_driver usb_1_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_1,
+};
+static const struct pci_driver usb_2_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_2,
+};
+static const struct pci_driver usb_3_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_3,
+};
+static const struct pci_driver usb_4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_4,
+};
+
+static struct device_operations usb_ops2 = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init2,
+	/*.enable           = sb600_enable, */
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_5_driver __pci_driver = {
+	.ops = &usb_ops2,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB2,
+};
+

Modified: trunk/src/southbridge/amd/sb700/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb700/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb700/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,10 +1,10 @@
 driver-y += sb700.c
-driver-y += sb700_usb.c
-driver-y += sb700_lpc.c
-driver-y += sb700_sm.c
-driver-y += sb700_ide.c
-driver-y += sb700_sata.c
-driver-y += sb700_hda.c
-driver-y += sb700_pci.c
-ramstage-y += sb700_reset.c
-romstage-y += sb700_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c

Copied and modified: trunk/src/southbridge/amd/sb700/early_setup.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x6000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */

Copied: trunk/src/southbridge/amd/sb700/enable_usbdebug.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/enable_usbdebug.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "sb700.h"
+
+#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+
+void set_debug_port(unsigned int port)
+{
+	u32 reg32;
+
+	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 &= ~(0xf << 28);
+	reg32 |= (port << 28);
+	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+	write32(DEBUGPORT_MISC_CONTROL, reg32);
+}
+
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
+void sb700_enable_usbdebug(unsigned int port)
+{
+	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/*
+	* Select the requested physical USB port (1-15) as the Debug Port.
+	* Must be called after the EHCI BAR has been set up (see above).
+	*/
+	set_debug_port(port);
+}

Copied: trunk/src/southbridge/amd/sb700/hda.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/hda.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c)
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "sb700.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 dword;
+	int count;
+
+	/* Write (val & ~mask) to port */
+	val &= mask;
+	dword = read32(port);
+	dword &= ~mask;
+	dword |= val;
+	write32(port, dword);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		dword = read32(port);
+		dword &= mask;
+	} while ((dword != val) && --count);
+
+	/* Timeout occured */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static u32 codec_detect(u32 base)
+{
+	u32 dword;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Delay for 1 ms since the BKDG does */
+	mdelay(1);
+
+	/* Read in Codec location (BAR + 0xe)[3..0]*/
+	dword = read32(base + 0xe);
+	dword &= 0x0F;
+	if (!dword)
+		goto no_codec;
+
+	return dword;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "No codec!\n");
+	return 0;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 dword=read32(base +  HDA_ICII_REG);
+		if (!(dword & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+static int wait_for_valid(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		u32 dword = read32(base + HDA_ICII_REG);
+		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return 1;
+}
+
+static void codec_init(u32 base, int addr)
+{
+	u32 dword;
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	dword = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, dword);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	dword = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
+}
+
+static void codecs_init(u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(base, i);
+	}
+}
+
+static void hda_init(struct device *dev)
+{
+	u8 byte;
+	u32 dword;
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	device_t sm_dev;
+
+	/* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */
+	byte = pm_ioread(0x59);
+	byte |= 1 << 3;
+	pm_iowrite(0x59, byte);
+
+	/* Find the SMBus */
+	/* FIXME: Need to find out why the call below crashes. */
+	/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB700_SM, 0);*/
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
+	pci_write_config32(sm_dev, 0xf8, 0x00);
+	pci_write_config8(sm_dev, 0xfc, 0xAA);
+	/* Set INTA - SMBus 0x63 [2..0] */
+	byte = pci_read_config8(sm_dev, 0x63);
+	byte &= ~0x7;
+	byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
+	pci_write_config8(sm_dev, 0x63, byte);
+
+	/* Program the 2C to 0x437b1002 */
+	dword = 0x437b1002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* Read in BAR */
+	/* Is this right? HDA allows for a 64-bit BAR
+	 * but this is only setup for a 32-bit one
+	 */
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations hda_audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = hda_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver hdaaudio_driver __pci_driver = {
+	.ops = &hda_audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_HDA,
+};

Copied: trunk/src/southbridge/amd/sb700/ide.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb700.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_amd_sb700_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	u32 dword;
+	u8 byte;
+
+	conf = dev->chip_info;
+
+	/* RPR9.1 disable MSI */
+	/* TODO: For A14, it should set as 1. I doubt it. */
+	dword = pci_read_config32(dev, 0x70);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x70, dword);
+
+	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
+	byte = pci_read_config8(dev, 0x54);
+	byte |= 0xf;
+	pci_write_config8(dev, 0x54, byte);
+
+	/* Enable I/O Access&& Bus Master */
+	dword = pci_read_config16(dev, 0x4);
+	dword |= 1 << 2;
+	pci_write_config16(dev, 0x4, dword);
+
+	/* set ide as primary, if you want to boot from IDE, you'd better set it
+	 * in $vendor/$mainboard/devicetree.cb */
+	 
+	
+	if (conf->boot_switch_sata_ide == 1) {
+		struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+		byte = pci_read_config8(sm_dev, 0xAD);
+		byte |= 1 << 4;
+		pci_write_config8(sm_dev, 0xAD, byte);
+	}
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_IDE,
+};

Copied: trunk/src/southbridge/amd/sb700/lpc.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c)
@@ -0,0 +1,238 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "sb700.h"
+
+static void lpc_init(device_t dev)
+{
+	u8 byte;
+	u32 dword;
+	device_t sm_dev;
+
+	/* Enable the LPC Controller */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	dword = pci_read_config32(sm_dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(sm_dev, 0x64, dword);
+
+	/* Initialize isa dma */
+#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+	printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
+#else
+	isa_dma_init();
+#endif
+
+	/* Enable DMA transaction on the LPC bus */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Disable the timeout mechanism on LPC */
+	byte = pci_read_config8(dev, 0x48);
+	byte &= ~(1 << 7);
+	pci_write_config8(dev, 0x48, byte);
+
+	/* Disable LPC MSI Capability */
+	byte = pci_read_config8(dev, 0x78);
+	byte &= ~(1 << 1);
+	pci_write_config8(dev, 0x78, byte);
+}
+
+static void sb700_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+}
+
+static void sb700_lpc_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	res = find_resource(dev, 0xA0);
+	pci_write_config32(dev, 0xA0, res->base | 1 << 1);
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whose children's resources are to be enabled
+ *
+ */
+static void sb700_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		pci_write_config16(dev, 0x64, reg_var[0]);
+		break;
+	}
+}
+
+static void sb700_lpc_enable_resources(device_t dev)
+{
+	pci_dev_enable_resources(dev);
+	sb700_lpc_enable_childrens_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations lpc_ops = {
+	.read_resources = sb700_lpc_read_resources,
+	.set_resources = sb700_lpc_set_resources,
+	.enable_resources = sb700_lpc_enable_resources,
+	.init = lpc_init,
+	.scan_bus = scan_static_bus,
+	.ops_pci = &lops_pci,
+};
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_LPC,
+};

Copied: trunk/src/southbridge/amd/sb700/pci.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c)
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb700.h"
+
+static void pci_init(struct device *dev)
+{
+	u32 dword;
+	u16 word;
+	u8 byte;
+
+	/* RPR 5.1 Enables the PCI-bridge subtractive decode */
+	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR5.2 PCI-bridge upstream dual address window */
+	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR 5.3 PCI bus 64-byte DMA read access */
+	/* Enhance the PCI bus DMA performance */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 4;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
+	/* The size of the writes will be set in the Cacheline Register */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 1;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
+	pci_write_config8(dev, 0x0D, 0x40);
+	pci_write_config8(dev, 0x1B, 0x40);
+
+	/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 6;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.8 Adjusts the GNT# de-assertion time */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 5.9 Fast Back to Back transactions support */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 2;
+	/* pci_write_config8(dev, 0x48, byte); */
+
+	/* RPR 5.10 Enable Lock Operation */
+	/* byte = pci_read_config8(dev, 0x48); */
+	byte |= 1 << 3;
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 5.11 Enable additional optional PCI clock */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 8;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 5.12 Enable One-Prefetch-Channel Mode */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 5.13 Disable PCIB MSI Capability */
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 3);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* rpr5.14 Adjusting CLKRUN# */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 15);
+	pci_write_config32(dev, 0x64, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_PCI,
+};

Copied: trunk/src/southbridge/amd/sb700/reset.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/amd/sb700/sata.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c)
@@ -0,0 +1,294 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "sb700.h"
+
+static int sata_drive_detect(int portnum, u16 iobar)
+{
+	u8 byte, byte2;
+	int i = 0;
+	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
+		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
+		((byte2 & 0x88) != 0)) {
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
+		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+			/* This will happen at the first iteration of this loop
+			 * if the first SATA port is unpopulated and the
+			 * second SATA port is poulated.
+			 */
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
+				"retrying init\n", i * 10);
+			return 1;
+		} else
+			printk(BIOS_SPEW, "drive detection not yet completed, "
+				"waiting...\n");
+		mdelay(10);
+		i++;
+	}
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
+	return 0;
+}
+
+	/* This function can be overloaded in mainboard.c */
+
+void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) {
+	/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+	pci_write_config16(dev, 0x86, 0x2c00);
+
+	/* RPR7.6.2 SATA GENI PHY ports setting */
+	pci_write_config32(dev, 0x88, 0x01B48017);
+	pci_write_config32(dev, 0x8c, 0x01B48019);
+	pci_write_config32(dev, 0x90, 0x01B48016);
+	pci_write_config32(dev, 0x94, 0x01B48016);
+	pci_write_config32(dev, 0x98, 0x01B48016);
+	pci_write_config32(dev, 0x9C, 0x01B48016);
+
+	/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+	pci_write_config16(dev, 0xA0, 0xA09A);
+	pci_write_config16(dev, 0xA2, 0xA09F);
+	pci_write_config16(dev, 0xA4, 0xA07A);
+	pci_write_config16(dev, 0xA6, 0xA07A);
+	pci_write_config16(dev, 0xA8, 0xA07A);
+	pci_write_config16(dev, 0xAA, 0xA07A);
+}
+
+static void sata_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u8 rev_id;
+	u32 sata_bar5;
+	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+	int i, j;
+
+	struct southbridge_ati_sb700_config *conf;
+	conf = dev->chip_info;
+
+	device_t sm_dev;
+	/* SATA SMBus Disable */
+	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Disable SATA SMBUS */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 1);
+	/* Enable SATA and power saving */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 0);
+	byte |= (1 << 5);
+	pci_write_config8(sm_dev, 0xad, byte);
+
+	/* RPR 7.2 SATA Initialization */
+	/* Set the interrupt Mapping to INTG# */
+	byte = pci_read_config8(sm_dev, 0xaf);
+	byte = 0x6 << 2;
+	pci_write_config8(sm_dev, 0xaf, byte);
+
+	/* get rev_id */
+	rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
+
+	/* get base address */
+	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
+	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
+	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
+	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
+	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
+
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+
+	/* disable combined mode */
+	byte = pci_read_config8(sm_dev, 0xAD);
+	byte &= ~(1 << 3);
+	pci_write_config8(sm_dev, 0xAD, byte);
+	/* Program the 2C to 0x43801002 */
+	dword = 0x43801002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* SERR-Enable */
+	word = pci_read_config16(dev, 0x04);
+	word |= (1 << 8);
+	pci_write_config16(dev, 0x04, word);
+
+	/* Dynamic power saving */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Set SATA Operation Mode, Set to IDE mode */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 0);
+	byte |= (1 << 4);
+	pci_write_config8(dev, 0x40, byte);
+
+	dword = 0x01018f00;
+	pci_write_config32(dev, 0x8, dword);
+
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Enable the SATA watchdog counter */
+	byte = pci_read_config8(dev, 0x44);
+	byte |= (1 << 0);
+	pci_write_config8(dev, 0x44, byte);
+
+	/* Set bit 29 and 24 for A12 */
+	dword = pci_read_config32(dev, 0x40);
+	if (rev_id < 0x14)	/* before A12 */
+		dword |= (1 << 29);
+	else
+		dword &= ~(1 << 29); /* A14 and above */
+	pci_write_config32(dev, 0x40, dword);
+
+	/* set bit 21 for A12 */
+	dword = pci_read_config32(dev, 0x48);
+	if (rev_id < 0x14)	/* before A12 */
+		dword |= 1 << 24 | 1 << 21;
+	else {
+		dword &= ~(1 << 24 | 1 << 21); /* A14 and above */
+		dword &= ~0xFF80; /* 15:7 */
+		dword |= 1 << 15 | 0x7F << 7;
+	}
+	pci_write_config32(dev, 0x48, dword);
+
+	/* Program the watchdog counter to 0x10 */
+	byte = 0x10;
+	pci_write_config8(dev, 0x46, byte);
+	sb700_setup_sata_phys(dev);
+	/* Enable the I/O, MM, BusMaster access for SATA */
+	byte = pci_read_config8(dev, 0x4);
+	byte |= 7 << 0;
+	pci_write_config8(dev, 0x4, byte);
+
+	/* RPR7.7 SATA drive detection. */
+	/* Use BAR5+0x128,BAR0 for Primary Slave */
+	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+	/* Use BAR5+0x228,BAR2 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
+	/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
+	/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
+
+	/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
+
+	for (i = 0; i < 4; i++) {
+		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+		byte &= 0xF;
+		if( byte == 0x1 ) {
+			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
+			/* Try to do something about it. */
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
+
+			/* Read in Port-N Serial ATA Control Register */
+			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+
+			/* Set Reset Bit and 1.5g bit */
+			byte |= 0x11;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Clear Reset Bit */
+			byte &= ~0x01;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Reread status */
+			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+			byte &= 0xF;
+		}
+
+		if (byte == 0x3) {
+			for (j = 0; j < 10; j++) {
+				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
+					break;
+			}
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master",
+					(j == 10) ? "not " : "",
+					(j == 10) ? j : j + 1);
+		} else {
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master", i);
+		}
+	}
+
+	/* Below is CIM InitSataLateFar */
+	/* Enable interrupts from the HBA  */
+	byte = read8(sata_bar5 + 0x4);
+	byte |= 1 << 1;
+	write8((sata_bar5 + 0x4), byte);
+
+	/* Clear error status */
+	write32((sata_bar5 + 0x130), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x230), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x330), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
+
+	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+	/* word = 0x0000; */
+	/* word = pm_ioread(0x28); */
+	/* byte = pm_ioread(0x29); */
+	/* word |= byte<<8; */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
+	/* write32(word, 0x80000000); */
+}
+
+static struct pci_operations lops_pci = {
+	/* .set_subsystem = pci_dev_set_subsystem, */
+};
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = sata_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_SATA,
+};

Copied and modified: trunk/src/southbridge/amd/sb700/sm.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_sm.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_sm.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/sm.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 

Copied and modified: trunk/src/southbridge/amd/sb700/smbus.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -20,7 +20,7 @@
 #ifndef _SB700_SMBUS_C_
 #define _SB700_SMBUS_C_
 
-#include "sb700_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {

Copied: trunk/src/southbridge/amd/sb700/smbus.h (from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h)
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SB700_SMBUS_H
+#define SB700_SMBUS_H
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+#define AX_INDXC  0
+#define AX_INDXP  1
+#define AXCFG     2
+#define ABCFG     3
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx(0, (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)	\
+	alink_ax_indx(1, (reg), (mask), (val))
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+
+
+#endif

Copied: trunk/src/southbridge/amd/sb700/usb.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c)
@@ -0,0 +1,253 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <usbdebug.h>
+#include <arch/io.h>
+#include "sb700.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+
+	/* 6.1 Enable OHCI0-4 and EHCI Controllers */
+	device_t sm_dev;
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	byte = pci_read_config8(sm_dev, 0x68);
+	byte |= 0xFF;
+	pci_write_config8(sm_dev, 0x68, byte);
+
+	/* RPR 6.2 Enables the USB PME Event,Enable USB resume support */
+	byte = pm_ioread(0x61);
+	byte |= 1 << 6;
+	pm_iowrite(0x61, byte);
+	byte = pm_ioread(0x65);
+	byte |= 1 << 2;
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.3 Support USB device wakeup from the S4/S5 state */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 0);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.5 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
+	byte = pm_ioread(0x65);
+	byte |= (1 << 4);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.10 Disable OHCI MSI Capability. */
+	word = pci_read_config16(dev, 0x40);
+	word |= (0x3 << 8);
+	pci_write_config16(dev, 0x40, word);
+}
+
+static void usb_init2(struct device *dev)
+{
+	u32 dword;
+	u32 usb2_bar0;
+	device_t sm_dev;
+	u8 rev;
+
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	rev = get_sb700_revision(sm_dev);
+
+	/* dword = pci_read_config32(dev, 0xf8); */
+	/* dword |= 40; */
+	/* pci_write_config32(dev, 0xf8, dword); */
+
+	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+
+	/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
+	dword = 0x00020F00;
+	write32(usb2_bar0 + 0xC0, dword);
+
+	/* RPR6.9 Sets In/OUT FIFO threshold for best performance */
+	dword = 0x00400040;
+	write32(usb2_bar0 + 0xA4, dword);
+
+	/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 28);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR 6.12 EHCI Advance PHY Power Savings */
+	/* RPR says it is just for A12. CIMM sets it when it is above A11. */
+	/* But it makes the linux crash, so we skip it */
+	#if 0
+	dword = pci_read_config32(dev, 0x50);
+	dword |= 1 << 31;
+	pci_write_config32(dev, 0x50, dword);
+	#endif
+
+	/* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */
+	/* RPR says it is just for A12. CIMx sets it when it is above A11. */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 20);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR6.15 EHCI Async Park Mode */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 23);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* Each step below causes the linux crashes. Leave them here
+	 * for future debugging. */
+#if 0
+	u8 byte;
+	u16 word;
+
+	/* RPR6.16 Disable EHCI MSI support */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */
+	word = read32(usb2_bar0 + 0xBC);
+	word &= ~(1 << 12);
+	write16(usb2_bar0 + 0xBC, word);
+
+	/* RPR6.19 USB Controller DMA Read Delay Tolerant. */
+	if (rev >= REV_SB700_A14) {
+		byte = pci_read_config8(dev, 0x50);
+		byte |= (1 << 7);
+		pci_write_config8(dev, 0x50, byte);
+	}
+
+	/* RPR6.20 Async Park Mode. */
+	/* RPR recommends not to set these bits. */
+	#if 0
+	dword = pci_read_config32(dev, 0x50);
+	dword |= 1 << 23;
+	if (rev >= REV_SB700_A14) {
+		dword &= ~(1 << 2);
+	}
+	pci_write_config32(dev, 0x50, dword);
+	#endif
+
+	/* RPR6.22 Advance Async Enhancement */
+	/* RPR6.23 USB Periodic Cache Setting */
+	dword = pci_read_config32(dev, 0x50);
+	if (rev == REV_SB700_A12) {
+		dword |= 1 << 28; /* 6.22 */
+		dword |= 1 << 27; /* 6.23 */
+	} else if (rev >= REV_SB700_A14) {
+		dword |= 1 << 3;
+		dword &= ~(1 << 28); /* 6.22 */
+		dword |= 1 << 8;
+		dword &= ~(1 << 27); /* 6.23 */
+	}
+	printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
+#endif
+}
+
+static void usb_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_0_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_0,
+};
+
+static const struct pci_driver usb_1_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
+};
+
+/* the pci id of usb ctrl 0 and 1 are the same. */
+/*
+ * static const struct pci_driver usb_3_driver __pci_driver = {
+ * 	.ops = &usb_ops,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_0,
+ * };
+ * static const struct pci_driver usb_4_driver __pci_driver = {
+ * 	.ops = &usb_ops,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_1,
+ * };
+ */
+
+static const struct pci_driver usb_4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_20_5,
+};
+
+static struct device_operations usb_ops2 = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init2,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_5_driver __pci_driver = {
+	.ops = &usb_ops2,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_2,
+};
+/*
+ * static const struct pci_driver usb_5_driver __pci_driver = {
+ * 	.ops = &usb_ops2,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_2,
+ * };
+ */

Modified: trunk/src/southbridge/broadcom/bcm21000/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm21000/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm21000/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += bcm21000_pcie.c
+driver-y += pcie.c

Copied: trunk/src/southbridge/broadcom/bcm21000/pcie.c (from r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm21000/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c)
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for
+ * University of Heidelberg.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	uint32_t dword;
+	uint32_t msicap;
+
+	printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/* enable MSI on PCIE: */
+	msicap = pci_read_config32(dev, 0xa0);
+	msicap |= (1<<16); /* enable MSI*/
+	pci_write_config32(dev, 0xa0, msicap);
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = 0,
+};
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pci_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pcie_driver1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0,
+};
+
+static const struct pci_driver pcie_driver2 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1,
+};
+
+static const struct pci_driver pcie_driver3 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2,
+};

Modified: trunk/src/southbridge/broadcom/bcm5780/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5780/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5780/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,3 +1,3 @@
-driver-y += bcm5780_nic.c
-driver-y += bcm5780_pcix.c
-driver-y += bcm5780_pcie.c
+driver-y += nic.c
+driver-y += pcix.c
+driver-y += pcie.c

Copied: trunk/src/southbridge/broadcom/bcm5780/nic.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void nic_init(struct device *dev)
+{
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);// it will init option rom
+#endif
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = nic_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_BROADCOM,
+	.device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC,
+};
+
+static const struct pci_driver nic1_driver __pci_driver = {
+        .ops    = &nic_ops,
+        .vendor = PCI_VENDOR_ID_BROADCOM,
+        .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+};

Copied: trunk/src/southbridge/broadcom/bcm5780/pcie.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c)
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void pcie_init(struct device *dev)
+{
+
+	/* Enable pci error detecting */
+	uint32_t dword;
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = 0,
+};
+
+static struct device_operations pcie_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init             = pcie_init,
+        .scan_bus         = pci_scan_bridge,
+        .reset_bus        = pci_bus_reset,
+        .ops_pci          = &lops_pci,
+
+};
+
+static const struct pci_driver pcie_driver __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE,
+};

Copied: trunk/src/southbridge/broadcom/bcm5780/pcix.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/pcix.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c)
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ht_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init             = 0 ,
+        .scan_bus         = pci_scan_bridge,
+        .reset_bus        = pci_bus_reset,
+        .ops_pci          = &lops_pci,
+
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops    = &ht_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB,
+};

Modified: trunk/src/southbridge/broadcom/bcm5785/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5785/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,7 +1,7 @@
 driver-y += bcm5785.c
-driver-y += bcm5785_usb.c
-driver-y += bcm5785_lpc.c
-driver-y += bcm5785_sb_pci_main.c
-driver-y += bcm5785_ide.c
-driver-y += bcm5785_sata.c
-ramstage-y += bcm5785_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sb_pci_main.c
+driver-y += ide.c
+driver-y += sata.c
+ramstage-y += reset.c

Modified: trunk/src/southbridge/broadcom/bcm5785/bootblock.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5785/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_enable_rom.c"
+#include "enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/broadcom/bcm5785/early_setup.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c)
@@ -0,0 +1,223 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include "bcm5785.h"
+
+static void bcm5785_enable_lpc(void)
+{
+        uint8_t byte;
+        device_t dev;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+        /* LPC Control 0 */
+        byte = pci_read_config8(dev, 0x44);
+        /* Serial 0 */
+        byte |= (1<<6);
+        pci_write_config8(dev, 0x44, byte);
+
+        /* LPC Control 4 */
+        byte = pci_read_config8(dev, 0x48);
+        /* superio port 0x2e/4e enable */
+        byte |=(1<<1)|(1<<0);
+        pci_write_config8(dev, 0x48, byte);
+}
+
+static void bcm5785_enable_wdt_port_cf9(void)
+{
+        device_t dev;
+        uint32_t dword;
+        uint32_t dword_old;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+        dword_old = pci_read_config32(dev, 0x4c);
+        dword = dword_old | (1<<4); //enable Timer Func
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x4c, dword);
+        }
+
+        dword_old = pci_read_config32(dev, 0x6c);
+        dword = dword_old | (1<<9); //unhide Timer Func in pci space
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x6c, dword);
+        }
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+
+        /* enable cf9 */
+        pci_write_config8(dev, 0x40, (1<<2));
+}
+
+unsigned get_sbdn(unsigned bus)
+{
+        device_t dev;
+
+        /* Find the device.
+         * There can only be one bcm5785 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(0x1166, 0x0036),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+#define SB_VFSMAF 0
+
+void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+	//ACPI Decode Enable
+	outb(0x0e, 0xcd6);
+	outb((1<<3), 0xcd7);
+
+	// set port to 0x2060
+	outb(0x67, 0xcd6);
+	outb(0x60, 0xcd7);
+        outb(0x68, 0xcd6);
+        outb(0x20, 0xcd7);
+
+	outb(0x69, 0xcd6);
+	outb(7, 0xcd7);
+
+	outb(0x64, 0xcd6);
+	outb(9, 0xcd7);
+}
+
+void ldtstop_sb(void)
+{
+	outb(1, 0x2060);
+}
+
+
+void hard_reset(void)
+{
+        bcm5785_enable_wdt_port_cf9();
+
+        set_bios_reset();
+
+        /* full reset */
+        outb(0x0a, 0x0cf9);
+        outb(0x0e, 0x0cf9);
+}
+
+void soft_reset(void)
+{
+        bcm5785_enable_wdt_port_cf9();
+
+        set_bios_reset();
+#if 1
+        /* link reset */
+//        outb(0x02, 0x0cf9);
+        outb(0x06, 0x0cf9);
+#endif
+}
+
+static void bcm5785_enable_msg(void)
+{
+        device_t dev;
+        uint32_t dword;
+        uint32_t dword_old;
+        uint8_t byte;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+        byte = pci_read_config8(dev, 0x42);
+        byte = (1<<1); //enable a20
+        pci_write_config8(dev, 0x42, byte);
+
+        dword_old = pci_read_config32(dev, 0x6c);
+        // bit 5: enable A20 Message
+        // bit 4: enable interrupt messages
+        // bit 3: enable reset init message
+        // bit 2: enable keyboard init message
+        // bit 1: enable upsteam messages
+        // bit 0: enable shutdowm message to init generation
+        dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x6c, dword);
+        }
+}
+
+static void bcm5785_early_setup(void)
+{
+        uint8_t byte;
+        uint32_t dword;
+        device_t dev;
+
+//F0
+        // enable device on bcm5785 at first
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+        dword = pci_read_config32(dev, 0x64);
+        dword |=  (1<<15) | (1<<11) | (1<<3); // ioapci enable
+        dword |= (1<<8); // USB enable
+        dword |= /* (1<<27)|*/(1<<14); // IDE enable
+        pci_write_config32(dev, 0x64, dword);
+
+        byte = pci_read_config8(dev, 0x84);
+        byte |= (1<<0); // SATA enable
+        pci_write_config8(dev, 0x84, byte);
+
+// WDT and cf9 for later in coreboot_ram to call hard_reset
+        bcm5785_enable_wdt_port_cf9();
+
+        bcm5785_enable_msg();
+
+
+// IDE related
+	//F0
+        byte = pci_read_config8(dev, 0x4e);
+        byte |= (1<<4); //enable IDE ext regs
+        pci_write_config8(dev, 0x4e, byte);
+
+	//F1
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+        byte = pci_read_config8(dev, 0x48);
+        byte &= ~1; // disable pri channel
+        pci_write_config8(dev, 0x48, byte);
+        pci_write_config8(dev, 0xb0, 0x01);
+        pci_write_config8(dev, 0xb2, 0x02);
+        byte = pci_read_config8(dev, 0x06);
+        byte |= (1<<4); // so b0, b2 can not be changed from now
+        pci_write_config8(dev, 0x06, byte);
+        byte = pci_read_config8(dev, 0x49);
+        byte |= 1; // enable second channel
+        pci_write_config8(dev, 0x49, byte);
+
+	//F2
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+        byte = pci_read_config8(dev, 0x40);
+        byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+        pci_write_config8(dev, 0x40, byte);
+
+        pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+
+// USB related
+        pci_write_config8(dev, 0x90, 0x40);
+        pci_write_config8(dev, 0x92, 0x06);
+        pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+        pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+        pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+        pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+        pci_write_config8(dev, 0xb4, 0x40);
+}

Copied and modified: trunk/src/southbridge/broadcom/bcm5785/early_smbus.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/broadcom/bcm5785/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x1000
 

Copied: trunk/src/southbridge/broadcom/bcm5785/enable_rom.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+static void bcm5785_enable_rom(void)
+{
+	u8 byte;
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
+			PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
+
+	/* Set the 4MB enable bits. */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= 0x0e;
+	pci_write_config8(dev, 0x41, byte);
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/ide.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c)
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "bcm5785.h"
+
+static void bcm5785_ide_read_resources(device_t dev)
+{
+        /* Get the normal pci resources of this device */
+        pci_dev_read_resources(dev);
+
+        /* BAR */
+        pci_get_resource(dev, 0x64);
+
+        compact_resources(dev);
+}
+
+static void ide_init(struct device *dev)
+{
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ide_ops  = {
+	.read_resources   = bcm5785_ide_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+//	.enable           = bcm5785_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE,
+};

Copied: trunk/src/southbridge/broadcom/bcm5785/lpc.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c)
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "bcm5785.h"
+
+static void lpc_init(device_t dev)
+{
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void bcm5785_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+/**
+ * Enable resources for children devices.
+ *
+ * @param dev The device whos children's resources are to be enabled.
+ */
+static void bcm5785_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	uint32_t reg;
+
+	reg = pci_read_config8(dev, 0x44);
+
+	for (link = dev->link_list; link; link = link->next) {
+                device_t child;
+                for (child = link->children; child; child = child->sibling) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for(res = child->resource_list; res; res = res->next) {
+			                unsigned long base, end; // don't need long long
+					if(!(res->flags & IORESOURCE_IO)) continue;
+		        	        base = res->base;
+                			end = resource_end(res);
+					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
+					switch(base) {
+					case 0x60: //KBC
+					case 0x64:
+						reg |= (1<<29);
+					case 0x3f8: // COM1
+						reg |= (1<<6); 	break;
+					case 0x2f8: // COM2
+						reg |= (1<<7);  break;
+					case 0x378: // Parallal 1
+						reg |= (1<<0); break;
+					case 0x3f0: // FD0
+						reg |= (1<<26); break;
+					case 0x220:  // Aduio 0
+						reg |= (1<<14);	break;
+					case 0x300:  // Midi 0
+						reg |= (1<<18);	break;
+					}
+				}
+			}
+                }
+        }
+	pci_write_config32(dev, 0x44, reg);
+
+
+}
+
+static void bcm5785_lpc_enable_resources(device_t dev)
+{
+        pci_dev_enable_resources(dev);
+        bcm5785_lpc_enable_childrens_resources(dev);
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = bcm5785_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = bcm5785_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+//	.enable           = bcm5785_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
+};

Copied: trunk/src/southbridge/broadcom/bcm5785/reset.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c)
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+        (((BUS) & 0xFFF) << 20) | \
+        (((DEV) & 0x1F) << 15) | \
+        (((FN)  & 0x7) << 12))
+
+typedef unsigned device_t;
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+        /* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
+      	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/sata.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c)
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "bcm5785.h"
+
+static void sata_init(struct device *dev)
+{
+	uint8_t byte;
+
+	u32 mmio;
+        struct resource *res;
+        u32 mmio_base;
+	int i;
+
+	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
+		byte = pci_read_config8(dev, 0x78);
+		byte |= (1<<7);
+        	pci_write_config8(dev, 0x78, byte);
+
+	        res = find_resource(dev, 0x24);
+                mmio_base = res->base;
+                mmio_base &= 0xfffffffc;
+
+		write32(mmio_base + 0x10f0, 0x40000001);
+		write32(mmio_base + 0x8c, 0x00ff2007);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x78592009);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x00082004);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x00002004);
+                mdelay( 10 );
+
+		//init PHY
+
+		printk(BIOS_DEBUG, "init PHY...\n");
+		for(i=0; i<4; i++) {
+			mmio = res->base + 0x100 * i;
+			byte = read8(mmio + 0x40);
+			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
+			if(byte & 0x4) {// bit 2 is set
+				byte = read8(mmio+0x48);
+				write8(mmio + 0x48, byte | 1);
+				write8(mmio + 0x48, byte & (~1));
+	                        byte = read8(mmio + 0x40);
+	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
+			}
+		}
+	}
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+//	.enable           = bcm5785_enable,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA,
+};

Copied and modified: trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c)
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/io.h>
 #include <device/smbus.h>
 #include "bcm5785.h"
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define NMI_OFF 0
 

Copied: trunk/src/southbridge/broadcom/bcm5785/smbus.h (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h)
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) { // ready now
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while(--loops);
+	return -2; // time out
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f; // mask off reserved bits
+		if ( val & 0x1c) {
+			return -5; // error
+		}
+		if ( val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT); // clear status
+			return 0; //
+		}
+	} while(--loops);
+	return -3; // timeout
+}
+
+static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+{
+	uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        /* read results of transaction */
+        byte = inb(smbus_io_base + SMBHSTCMD);
+
+	return byte;
+}
+
+static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+{
+        uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the command... */
+        outb(val, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        return 0;
+}
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	uint8_t byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2; // not ready
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3; // Clear [4:2]
+	byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3; // timeout or error
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	return byte;
+}
+
+static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+{
+        uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the command/address... */
+        outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+
+        /* output value */
+        outb(val, smbus_io_base + SMBHSTDAT0);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        return 0;
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/usb.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "bcm5785.h"
+
+static void usb_init(struct device *dev)
+{
+        uint32_t dword;
+
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<2)|(1<<1)|(1<<0);
+	pci_write_config32(dev, 0x04, dword);
+
+	pci_write_config8(dev, 0x41, 0x00); // Serversworks said
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations usb_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = usb_init,
+//	.enable           = bcm5785_enable,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb_driver __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB,
+};

Modified: trunk/src/southbridge/intel/esb6300/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/esb6300/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/esb6300/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,12 +1,12 @@
 driver-y += esb6300.c
-driver-y += esb6300_reset.c
-driver-y += esb6300_uhci.c
-driver-y += esb6300_lpc.c
-driver-y += esb6300_ide.c
-driver-y += esb6300_sata.c
-driver-y += esb6300_ehci.c
-driver-y += esb6300_smbus.c
-driver-y += esb6300_pci.c
-driver-y += esb6300_pic.c
-driver-y += esb6300_bridge1c.c
-driver-y += esb6300_ac97.c
+driver-y += reset.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+driver-y += pic.c
+driver-y += bridge1c.c
+driver-y += ac97.c

Copied: trunk/src/southbridge/intel/esb6300/ac97.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c)
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = ac97_set_subsystem,
+};
+static struct device_operations ac97_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97_audio_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO,
+};
+static const struct pci_driver ac97_modem_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM,
+};

Copied: trunk/src/southbridge/intel/esb6300/bridge1c.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/bridge1c.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c)
@@ -0,0 +1,47 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void bridge1c_init(struct device *dev)
+{
+	/* configuration */
+	pci_write_config8(dev, 0x1b, 0x30);
+//	pci_write_config8(dev, 0x3e, 0x07);
+	pci_write_config8(dev, 0x3e, 0x04);  /* parity ignore */
+	pci_write_config8(dev, 0x6c, 0x0c);  /* undocumented  */
+	pci_write_config8(dev, 0xe0, 0x20);
+
+	/* SRB enable */
+	pci_write_config16(dev, 0xe4, 0x0232);
+
+	/* Burst size */
+	pci_write_config8(dev, 0xf0, 0x02);
+
+	/* prefetch threshold size */
+	pci_write_config16(dev, 0xf8, 0x2121);
+
+	/* primary latency */
+	pci_write_config8(dev, 0x0d, 0x28);
+
+	/* multi transaction timer */
+	pci_write_config8(dev, 0x42, 0x08);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = bridge1c_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
+};
+

Copied and modified: trunk/src/southbridge/intel/esb6300/early_smbus.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/esb6300/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 

Copied: trunk/src/southbridge/intel/esb6300/ehci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c)
@@ -0,0 +1,50 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ehci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	uint8_t access_cntl;
+	access_cntl = pci_read_config8(dev, 0x80);
+	/* Enable writes to protected registers */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+	/* Restore protection */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &ehci_set_subsystem,
+};
+static struct device_operations ehci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ehci_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
+};

Copied: trunk/src/southbridge/intel/esb6300/ide.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c)
@@ -0,0 +1,56 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ide_init(struct device *dev)
+{
+
+	/* Enable ide devices so the linux ide driver will work */
+
+	/* Enable IDE devices */
+        pci_write_config16(dev, 0x40, 0x0a307);
+        pci_write_config16(dev, 0x42, 0x0a307);
+        pci_write_config8(dev, 0x48, 0x05);
+        pci_write_config16(dev, 0x4a, 0x0101);
+        pci_write_config16(dev, 0x54, 0x5055);
+
+#if 0
+	uint16_t word;
+	word = pci_read_config16(dev, 0x40);
+	word |= (1 << 15);
+	pci_write_config16(dev, 0x40, word);
+	word = pci_read_config16(dev, 0x42);
+	word |= (1 << 15);
+	pci_write_config16(dev, 0x42, word);
+#endif
+	printk(BIOS_DEBUG, "IDE Enabled\n");
+}
+
+static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* This value is also visible in uchi[0-2] and smbus functions */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = esb6300_ide_set_subsystem,
+};
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_IDE,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/lpc.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c)
@@ -0,0 +1,374 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "esb6300.h"
+
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x58
+
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define SERIRQ_CNTL 0x64
+static void esb6300_enable_serial_irqs(device_t dev)
+{
+	/* set packet length and toggle silent mode bit */
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+}
+
+#define PCI_DMA_CFG 0x90
+static void esb6300_pci_dma_cfg(device_t dev)
+{
+	/* Set PCI DMA CFG to lpc I/F DMA */
+	pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
+}
+
+#define LPC_EN 0xe6
+static void esb6300_enable_lpc(device_t dev)
+{
+        /* lpc i/f enable */
+        pci_write_config8(dev, LPC_EN, 0x0d);
+}
+
+typedef struct southbridge_intel_esb6300_config config_t;
+
+static void set_esb6300_gpio_use_sel(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_use_sel, gpio_use_sel2;
+
+//	gpio_use_sel  = 0x1B003100;
+//	gpio_use_sel2 = 0x03000000;
+	gpio_use_sel  = 0x1BBC31C0;
+	gpio_use_sel2 = 0x03000FE1;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) {
+		case ESB6300_GPIO_USE_AS_NATIVE: val = 0; break;
+		case ESB6300_GPIO_USE_AS_GPIO:   val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_use_sel  &= ~( 1 << i);
+			gpio_use_sel  |= (val << i);
+		} else {
+			gpio_use_sel2 &= ~( 1 << (i - 32));
+			gpio_use_sel2 |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_use_sel,  res->base + 0x00);
+	outl(gpio_use_sel2, res->base + 0x30);
+}
+
+static void set_esb6300_gpio_direction(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_io_sel, gpio_io_sel2;
+
+//	gpio_io_sel  = 0x0000ffff;
+//	gpio_io_sel2 = 0x00000000;
+	gpio_io_sel  = 0x1900ffff;
+	gpio_io_sel2 = 0x00000fe1;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
+		case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
+		case ESB6300_GPIO_SEL_INPUT:  val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_io_sel  &= ~( 1 << i);
+			gpio_io_sel  |= (val << i);
+		} else {
+			gpio_io_sel2 &= ~( 1 << (i - 32));
+			gpio_io_sel2 |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_io_sel,  res->base + 0x04);
+	outl(gpio_io_sel2, res->base + 0x34);
+}
+
+static void set_esb6300_gpio_level(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_lvl, gpio_lvl2;
+	uint32_t gpio_blink;
+
+//	gpio_lvl   = 0x1b3f0000;
+//	gpio_blink = 0x00040000;
+//	gpio_lvl2  = 0x00000fff;
+	gpio_lvl   = 0x19370000;
+	gpio_blink = 0x00000000;
+	gpio_lvl2  = 0x00000fff;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val, blink;
+		switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) {
+		case ESB6300_GPIO_LVL_LOW:   val = 0; blink = 0; break;
+		case ESB6300_GPIO_LVL_HIGH:  val = 1; blink = 0; break;
+		case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_lvl   &= ~(   1 << i);
+			gpio_blink &= ~(   1 << i);
+			gpio_lvl   |= (  val << i);
+			gpio_blink |= (blink << i);
+		} else {
+			gpio_lvl2  &= ~( 1 << (i - 32));
+			gpio_lvl2  |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_lvl,   res->base + 0x0c);
+	outl(gpio_blink, res->base + 0x18);
+	outl(gpio_lvl2,  res->base + 0x38);
+}
+
+static void set_esb6300_gpio_inv(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_inv;
+
+	gpio_inv   = 0x00003100;
+#if 0
+	int i;
+	for(i = 0; i < 32; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
+		case ESB6300_GPIO_INV_OFF: val = 0; break;
+		case ESB6300_GPIO_INV_ON:  val = 1; break;
+		default:
+			continue;
+		}
+		gpio_inv &= ~( 1 << i);
+		gpio_inv |= (val << i);
+	}
+#endif
+	outl(gpio_inv,   res->base + 0x2c);
+}
+
+static void esb6300_pirq_init(device_t dev)
+{
+	config_t *config;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->pirq_a_d) {
+		pci_write_config32(dev, 0x60, config->pirq_a_d);
+	}
+	if(config->pirq_e_h) {
+		pci_write_config32(dev, 0x68, config->pirq_e_h);
+	}
+}
+
+
+static void esb6300_gpio_init(device_t dev)
+{
+	struct resource *res;
+	config_t *config;
+
+	/* Skip if I don't have any configuration */
+	if (!dev->chip_info) {
+		return;
+	}
+	/* The programmer is responsible for ensuring
+	 * a valid gpio configuration.
+	 */
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+	/* Find the GPIO bar */
+	res = find_resource(dev, GPIO_BAR);
+	if (!res) {
+		return;
+	}
+
+	/* Set the use selects */
+	set_esb6300_gpio_use_sel(dev, res, config);
+
+	/* Set the IO direction */
+	set_esb6300_gpio_direction(dev, res, config);
+
+	/* Setup the input inverters */
+	set_esb6300_gpio_inv(dev, res, config);
+
+	/* Set the value on the GPIO output pins */
+	set_esb6300_gpio_level(dev, res, config);
+
+}
+
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	uint32_t value;
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+	/* sata settings */
+	pci_write_config32(dev, 0x58, 0x00001181);
+
+	/* IO APIC initialization */
+	value = pci_read_config32(dev, 0xd0);
+	value |= (1 << 8)|(1<<7);
+	value |= (6 << 0)|(1<<13)|(1<<11);
+	pci_write_config32(dev, 0xd0, value);
+	setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
+
+	/* disable reset timer */
+	pci_write_config8(dev, 0xd4, 0x02);
+
+	/* cmos ram 2nd 128 */
+	pci_write_config8(dev, 0xd8, 0x04);
+
+	/* comm 2 */
+	pci_write_config8(dev, 0xe0, 0x10);
+
+	/* fwh sellect */
+	pci_write_config32(dev, 0xe8, 0x00112233);
+
+	/* fwh decode */
+	pci_write_config8(dev, 0xf0, 0x0f);
+
+	/* av disable, sata controller */
+	pci_write_config8(dev, 0xf2, 0xc0);
+
+	/* undocumented */
+	pci_write_config8(dev, 0xa0, 0x20);
+	pci_write_config8(dev, 0xad, 0x03);
+	pci_write_config8(dev, 0xbb, 0x09);
+
+	/* apic1 rout */
+	pci_write_config8(dev, 0xf4, 0x40);
+
+	/* undocumented */
+	pci_write_config8(dev, 0xa0, 0x20);
+	pci_write_config8(dev, 0xad, 0x03);
+	pci_write_config8(dev, 0xbb, 0x09);
+
+	esb6300_enable_serial_irqs(dev);
+
+	esb6300_pci_dma_cfg(dev);
+
+	esb6300_enable_lpc(dev);
+
+        get_option(&pwr_on, "power_on_after_fail");
+	byte = pci_read_config8(dev, 0xa4);
+	byte &= 0xfe;
+	if (!pwr_on) {
+		byte |= 1;
+	}
+	pci_write_config8(dev, 0xa4, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
+
+	/* Set up the PIRQ */
+	esb6300_pirq_init(dev);
+
+	/* Set the state of the gpio lines */
+	esb6300_gpio_init(dev);
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void esb6300_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI BAR */
+	res = pci_get_resource(dev, ACPI_BAR);
+
+	/* Add the GPIO BAR */
+	res = pci_get_resource(dev, GPIO_BAR);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void esb6300_lpc_enable_resources(device_t dev)
+{
+	uint8_t acpi_cntl, gpio_cntl;
+
+	/* Enable the normal pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI bar */
+	acpi_cntl = pci_read_config8(dev, 0x44);
+	acpi_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x44, acpi_cntl);
+
+	/* Enable the GPIO bar */
+	gpio_cntl = pci_read_config8(dev, 0x5c);
+	gpio_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x5c, gpio_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = esb6300_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = esb6300_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_LPC,
+};

Copied: trunk/src/southbridge/intel/esb6300/pci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c)
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void pci_init(struct device *dev)
+{
+
+	uint16_t word;
+
+	/* Clear system errors */
+	word = pci_read_config16(dev, 0x06);
+	word |= 0xf900; /* Clear possible errors */
+	pci_write_config16(dev, 0x06, word);
+
+	word = pci_read_config16(dev, 0x1e);
+	word |= 0xf800; /* Clear possible errors */
+	pci_write_config16(dev, 0x1e, word);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/pic.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/pic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c)
@@ -0,0 +1,68 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/ioapic.h>
+#include "esb6300.h"
+
+static void pic_init(struct device *dev)
+{
+
+	uint16_t word;
+
+	/* Clear system errors */
+	word = pci_read_config16(dev, 0x06);
+	word |= 0xf900; /* Clear possible errors */
+	pci_write_config16(dev, 0x06, word);
+
+	/* enable interrupt lines */
+	pci_write_config8(dev, 0x3c, 0xff);
+
+	/* Setup the ioapic */
+	clear_ioapic(IO_APIC_ADDR + 0x10000);
+}
+
+static void pic_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Report the pic1 mbar resource */
+	res = new_resource(dev, 0x44);
+	res->base  = IO_APIC_ADDR + 0x10000;
+	res->size  = 256;
+	res->limit = res->base + res->size -1;
+	res->align = 8;
+	res->gran  = 8;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+}
+
+static struct pci_operations lops_pci = {
+	/* Can we set the pci subsystem and device id? */
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pic_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = pic_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_APIC1,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/reset.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9 */
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/intel/esb6300/sata.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c)
@@ -0,0 +1,75 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void sata_init(struct device *dev)
+{
+	/* Enable sata devices so the linux sata driver will work */
+
+	/* Enable SATA devices */
+
+	printk(BIOS_DEBUG, "SATA init\n");
+        /* SATA configuration */
+        pci_write_config8(dev, 0x04, 0x07);
+        pci_write_config8(dev, 0x09, 0x8f);
+
+        /* Set timmings */
+        pci_write_config16(dev, 0x40, 0x0a307);
+        pci_write_config16(dev, 0x42, 0x0a307);
+
+        /* Sync DMA */
+        pci_write_config16(dev, 0x48, 0x000f);
+        pci_write_config16(dev, 0x4a, 0x1111);
+
+        /* 66 mhz */
+        pci_write_config16(dev, 0x54, 0xf00f);
+
+        /* Combine ide - sata configuration */
+        pci_write_config8(dev, 0x90, 0x0);
+
+        /* port 0 & 1 enable */
+        pci_write_config8(dev, 0x92, 0x33);
+
+        /* initialize SATA  */
+        pci_write_config16(dev, 0xa0, 0x0018);
+        pci_write_config32(dev, 0xa4, 0x00000264);
+        pci_write_config16(dev, 0xa0, 0x0040);
+        pci_write_config32(dev, 0xa4, 0x00220043);
+
+	printk(BIOS_DEBUG, "SATA Enabled\n");
+}
+
+static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* This value is also visible in usb1, usb2 and smbus functions */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = esb6300_sata_set_subsystem,
+};
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+        .ops    = &sata_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA,
+};
+
+static const struct pci_driver sata_driver_nr __pci_driver = {
+        .ops    = &sata_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID,
+};
+

Copied and modified: trunk/src/southbridge/intel/esb6300/smbus.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/esb6300/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "esb6300.h"
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/esb6300/smbus.h (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h)
@@ -0,0 +1,101 @@
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#include <delay.h>
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		udelay(100);
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while(byte & 1);
+	return loops?0:-1;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        udelay(100);
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+	return loops?0:-1;
+}
+
+static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        udelay(100);
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte&(1<<7)) == 0);
+	return loops?0:-1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/esb6300/uhci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/uhci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c)
@@ -0,0 +1,57 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void uhci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+#if 1
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	/* The subsystem id follows the ide controller */
+	.set_subsystem = 0,
+};
+
+static struct device_operations uhci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = uhci_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb1_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB1,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB2,
+};
+
+/* Note: May or may not need different init than UHCI. */
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
+};
+

Modified: trunk/src/southbridge/intel/i3100/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i3100/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i3100/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,9 +1,9 @@
 driver-y += i3100.c
-driver-y += i3100_uhci.c
-driver-y += i3100_lpc.c
-driver-y += i3100_sata.c
-driver-y += i3100_ehci.c
-driver-y += i3100_smbus.c
-driver-y += i3100_pci.c
-ramstage-y += i3100_reset.c
-ramstage-y += i3100_pciexp_portb.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+ramstage-y += reset.c
+ramstage-y += pciexp_portb.c

Copied: trunk/src/southbridge/intel/i3100/early_lpc.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/early_lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+static void i3100_enable_superio(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Enable decoding of I/O locations for SuperIO devices */
+	pci_write_config16(dev, 0x80, 0x0010);
+	pci_write_config16(dev, 0x82, 0x340f);
+
+	/* Enable the SERIRQs (start pulse width is 8 clock cycles) */
+	pci_write_config8(dev, 0x64, 0xD2);
+}
+
+static void i3100_halt_tco_timer(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Temporarily enable the ACPI I/O range at 0x4000 */
+	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(0x4068) | (1 << 11), 0x4068);
+
+	/* Disable the ACPI I/O range */
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));
+}

Copied and modified: trunk/src/southbridge/intel/i3100/early_smbus.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i3100/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  *
  */
 
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 

Copied: trunk/src/southbridge/intel/i3100/ehci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void ehci_init(struct device *dev)
+{
+}
+
+static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+	access_cntl = pci_read_config8(dev, 0x80);
+	/* Enable writes to protected registers */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+	/* Restore protection */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &ehci_set_subsystem,
+};
+static struct device_operations ehci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ehci_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_EHCI,
+};
+
+static const struct pci_driver ehci_driver_ep80579 __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_EHCI,
+};

Copied: trunk/src/southbridge/intel/i3100/lpc.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c)
@@ -0,0 +1,433 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Linux Networx
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i3100.h"
+
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x48
+#define RCBA 0xf0
+
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+static void i3100_enable_serial_irqs(device_t dev)
+{
+	/* set packet length and toggle silent mode bit */
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+}
+
+typedef struct southbridge_intel_i3100_config config_t;
+
+static void set_i3100_gpio_use_sel(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_use_sel, gpio_use_sel2;
+	int i;
+
+	gpio_use_sel = inl(res->base + 0x00) | 0x0000c603;
+	gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100;
+	for (i = 0; i < 64; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_USE_MASK) {
+		case I3100_GPIO_USE_AS_NATIVE:
+			val = 0;
+			break;
+		case I3100_GPIO_USE_AS_GPIO:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_use_sel &= ~(1 << i);
+			gpio_use_sel |= (val << i);
+		} else {
+			gpio_use_sel2 &= ~(1 << (i - 32));
+			gpio_use_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_use_sel, res->base + 0x00);
+	outl(gpio_use_sel2, res->base + 0x30);
+}
+
+static void set_i3100_gpio_direction(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_io_sel, gpio_io_sel2;
+	int i;
+
+	gpio_io_sel = inl(res->base + 0x04);
+	gpio_io_sel2 = inl(res->base + 0x34);
+	for (i = 0; i < 64; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_SEL_MASK) {
+		case I3100_GPIO_SEL_OUTPUT:
+			val = 0;
+			break;
+		case I3100_GPIO_SEL_INPUT:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_io_sel &= ~(1 << i);
+			gpio_io_sel |= (val << i);
+		} else {
+			gpio_io_sel2 &= ~(1 << (i - 32));
+			gpio_io_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_io_sel, res->base + 0x04);
+	outl(gpio_io_sel2, res->base + 0x34);
+}
+
+static void set_i3100_gpio_level(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_lvl, gpio_lvl2;
+	u32 gpio_blink;
+	int i;
+
+	gpio_lvl = inl(res->base + 0x0c);
+	gpio_blink = inl(res->base + 0x18);
+	gpio_lvl2 = inl(res->base + 0x38);
+	for (i = 0; i < 64; i++) {
+		int val, blink;
+		switch (config->gpio[i] & I3100_GPIO_LVL_MASK) {
+		case I3100_GPIO_LVL_LOW:
+			val = 0;
+			blink = 0;
+			break;
+		case I3100_GPIO_LVL_HIGH:
+			val = 1;
+			blink = 0;
+			break;
+		case I3100_GPIO_LVL_BLINK:
+			val = 1;
+			blink = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_lvl &= ~(1 << i);
+			gpio_blink &= ~(1 << i);
+			gpio_lvl |= (val << i);
+			gpio_blink |= (blink << i);
+		} else {
+			gpio_lvl2 &= ~(1 << (i - 32));
+			gpio_lvl2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_lvl, res->base + 0x0c);
+	outl(gpio_blink, res->base + 0x18);
+	outl(gpio_lvl2, res->base + 0x38);
+}
+
+static void set_i3100_gpio_inv(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_inv;
+	int i;
+
+	gpio_inv = inl(res->base + 0x2c);
+	for (i = 0; i < 32; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_INV_MASK) {
+		case I3100_GPIO_INV_OFF:
+			val = 0;
+			break;
+		case I3100_GPIO_INV_ON:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		gpio_inv &= ~(1 << i);
+		gpio_inv |= (val << i);
+	}
+	outl(gpio_inv, res->base + 0x2c);
+}
+
+static void i3100_pirq_init(device_t dev)
+{
+	config_t *config;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->pirq_a_d) {
+		pci_write_config32(dev, 0x60, config->pirq_a_d);
+	}
+	if(config->pirq_e_h) {
+		pci_write_config32(dev, 0x68, config->pirq_e_h);
+	}
+}
+
+static void i3100_power_options(device_t dev) {
+  u8 reg8;
+  u16 reg16;
+  int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+  int nmi_option;
+
+  /* Which state do we want to goto after g3 (power restored)?
+   * 0 == S0 Full On
+   * 1 == S5 Soft Off
+   */
+  get_option(&pwr_on, "power_on_after_fail");
+  reg8 = pci_read_config8(dev, GEN_PMCON_3);
+  reg8 &= 0xfe;
+  if (pwr_on) {
+    reg8 &= ~1;
+  } else {
+    reg8 |= 1;
+  }
+  /* avoid #S4 assertions */
+  reg8 |= (3 << 4);
+  /* minimum asssertion is 1 to 2 RTCCLK */
+  reg8 &= ~(1 << 3);
+  pci_write_config8(dev, GEN_PMCON_3, reg8);
+  printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
+
+  /* Set up NMI on errors. */
+  reg8 = inb(0x61);
+  /* Higher Nibble must be 0 */
+  reg8 &= 0x0f;
+  /* IOCHK# NMI Enable */
+  reg8 &= ~(1 << 3);
+  /* PCI SERR# Enable */
+  // reg8 &= ~(1 << 2);
+  /* PCI SERR# Disable for now */
+  reg8 |= (1 << 2);
+  outb(reg8, 0x61);
+
+  reg8 = inb(0x70);
+  nmi_option = NMI_OFF;
+  get_option(&nmi_option, "nmi");
+  if (nmi_option) {
+    /* Set NMI. */
+    printk(BIOS_INFO, "NMI sources enabled.\n");
+    reg8 &= ~(1 << 7);
+  } else {
+    /* Can't mask NMI from PCI-E and NMI_NOW */
+    printk(BIOS_INFO, "NMI sources disabled.\n");
+    reg8 |= ( 1 << 7);
+  }
+  outb(reg8, 0x70);
+
+  // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+  reg16 = pci_read_config16(dev, GEN_PMCON_1);
+  reg16 &= ~((3 << 0) | (1 << 10));
+  reg16 |= (1 << 3) | (1 << 5);
+  /* CLKRUN_EN */
+  // reg16 |= (1 << 2);
+  pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+  // Set the board's GPI routing.
+  // i82801gx_gpi_routing(dev);
+}
+
+static void i3100_gpio_init(device_t dev)
+{
+	struct resource *res;
+	config_t *config;
+
+	/* Skip if I don't have any configuration */
+	if (!dev->chip_info) {
+		return;
+	}
+	/* The programmer is responsible for ensuring
+	 * a valid gpio configuration.
+	 */
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+	/* Find the GPIO bar */
+	res = find_resource(dev, GPIO_BAR);
+	if (!res) {
+		return;
+	}
+
+	/* Set the use selects */
+	set_i3100_gpio_use_sel(dev, res, config);
+
+	/* Set the IO direction */
+	set_i3100_gpio_direction(dev, res, config);
+
+	/* Setup the input inverters */
+	set_i3100_gpio_inv(dev, res, config);
+
+	/* Set the value on the GPIO output pins */
+	set_i3100_gpio_level(dev, res, config);
+
+}
+
+
+static void lpc_init(struct device *dev)
+{
+	struct resource *res;
+
+	/* Enable IO APIC */
+	res = find_resource(dev, RCBA);
+	if (!res) {
+		return;
+	}
+	*((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0);
+
+	// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+	// (register 0x10/0x11) while the old code used int 1 (register 0x12)
+	// ... Why?
+	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
+
+	/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
+	pci_write_config32(dev, 0xd0, 0x00000000);
+
+	i3100_enable_serial_irqs(dev);
+
+	/* Set up the PIRQ */
+	i3100_pirq_init(dev);
+
+	/* Setup power options */
+	i3100_power_options(dev);
+
+	/* Set the state of the gpio lines */
+	i3100_gpio_init(dev);
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void i3100_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI BAR */
+	res = pci_get_resource(dev, ACPI_BAR);
+
+	/* Add the GPIO BAR */
+	res = pci_get_resource(dev, GPIO_BAR);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	/* Add resource for RCBA */
+	res = new_resource(dev, RCBA);
+	res->size = 0x4000;
+	res->limit = 0xffffc000;
+	res->align = 14;
+	res->gran = 14;
+	res->flags = IORESOURCE_MEM;
+}
+
+static void i3100_lpc_enable_resources(device_t dev)
+{
+	u8 acpi_cntl, gpio_cntl;
+
+	/* Enable the normal pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI bar */
+	acpi_cntl = pci_read_config8(dev, 0x44);
+	acpi_cntl |= (1 << 7);
+	pci_write_config8(dev, 0x44, acpi_cntl);
+
+	/* Enable the GPIO bar */
+	gpio_cntl = pci_read_config8(dev, 0x4c);
+	gpio_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x4c, gpio_cntl);
+
+	/* Enable the RCBA */
+	pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = i3100_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = i3100_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_LPC,
+};
+
+static const struct pci_driver lpc_driver_ep80579 __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_LPC,
+};

Copied: trunk/src/southbridge/intel/i3100/pci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void pci_init(struct device *dev)
+{
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCI,
+};
+

Copied: trunk/src/southbridge/intel/i3100/pciexp_portb.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/pciexp_portb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c)
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <reset.h>
+
+#define PCIE_LCTL 0x50
+#define PCIE_LSTS 0x52
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+}
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+	u16 val;
+	u16 ctl;
+	int flag = 0;
+	do {
+		val = pci_read_config16(dev, PCIE_LSTS);
+		printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);
+		if ((val & (1<<10)) && (!flag)) { /* training error */
+			ctl = pci_read_config16(dev, PCIE_LCTL);
+			pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
+			val = pci_read_config16(dev, PCIE_LSTS);
+			printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);
+			flag=1;
+			hard_reset();
+		}
+	} while	(val & (3<<10));
+	return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pcie_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver_0 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
+};
+
+static const struct pci_driver pci_driver_1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
+};
+
+static const struct pci_driver pci_driver_2 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
+};
+
+static const struct pci_driver pci_driver_3 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
+};

Copied: trunk/src/southbridge/intel/i3100/reset.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	outb(0x06, 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i3100/sata.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c)
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+typedef struct southbridge_intel_i3100_config config_t;
+
+static void sata_init(struct device *dev)
+{
+        u8 ahci;
+
+	/* Get the chip configuration */
+	ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
+
+	/* Enable SATA devices */
+	printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
+
+	if(ahci) {
+	  /* AHCI mode */
+	  pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
+
+	  /* Enable ports */
+	  pci_write_config8(dev, SATA_PCS, 0x03);
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0F);
+
+	  /* Setup timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x8000);
+	  pci_write_config16(dev, SATA_STIM, 0x8000);
+
+	  /* Synchronous DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0);
+
+	  /* IDE I/O configuration */
+	  pci_write_config32(dev, SATA_IIOC, 0);
+
+	} else {
+	  /* SATA configuration */
+	  pci_write_config8(dev, SATA_CMD, 0x07);
+	  pci_write_config8(dev, SATA_PI, 0x8f);
+
+	  /* Set timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x0a307);
+	  pci_write_config16(dev, SATA_STIM, 0x0a307);
+
+	  /* Sync DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0x0f);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
+
+	  /* Fast ATA */
+	  pci_write_config16(dev, SATA_IIOC, 0x1000);
+
+	  /* Select IDE mode */
+	  pci_write_config8(dev, SATA_MAP, 0x00);
+
+	  /* Enable ports 0-3 */
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0f);
+
+	}
+	printk(BIOS_DEBUG, "SATA Enabled\n");
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_IDE,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_AHCI,
+};
+
+static const struct pci_driver ide_driver_ep80579 __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_IDE,
+};
+
+static const struct pci_driver sata_driver_ep80579 __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,
+};

Copied and modified: trunk/src/southbridge/intel/i3100/smbus.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i3100/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "i3100.h"
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i3100/smbus.h (from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h)
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */
+
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+#define SMBSLVCMD  0x11
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+static void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
+{
+	u8 global_status_register;
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i3100/uhci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/uhci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void uhci_init(struct device *dev)
+{
+}
+
+static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &uhci_set_subsystem,
+};
+
+static struct device_operations uhci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = uhci_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver uhci_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_UHCI,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_UHCI2,
+};
+
+static const struct pci_driver uhci_driver_ep80579 __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_UHCI,
+};

Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82371eb/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,13 +19,13 @@
 ##
 
 driver-y +=  i82371eb.c
-driver-y +=  i82371eb_isa.c
-driver-y +=  i82371eb_ide.c
-driver-y +=  i82371eb_usb.c
-driver-y +=  i82371eb_smbus.c
-driver-y +=  i82371eb_reset.c
-driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
+driver-y +=  isa.c
+driver-y +=  ide.c
+driver-y +=  usb.c
+driver-y +=  smbus.c
+driver-y +=  reset.c
+driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
 
-romstage-y += i82371eb_early_pm.c
-romstage-y += i82371eb_early_smbus.c
+romstage-y += early_pm.c
+romstage-y += early_smbus.c

Modified: trunk/src/southbridge/intel/i82371eb/bootblock.c
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82371eb/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/intel/i82371eb/early_pm.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/early_pm.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+void enable_pm(void)
+{
+	device_t dev;
+	u8 reg8;
+	u16 reg16;
+
+	/* Get the SMBus/PM device of the 82371AB/EB/MB. */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
+
+	/* Set the PM I/O base. */
+	pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
+
+	/* Enable access to the PM I/O space. */
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_IO;
+	pci_write_config16(dev, PCI_COMMAND, reg16);
+
+	/* PM I/O Space Enable (PMIOSE). */
+	reg8 = pci_read_config8(dev, PMREGMISC);
+	reg8 |= PMIOSE;
+	pci_write_config8(dev, PMREGMISC, reg8);
+}

Copied and modified: trunk/src/southbridge/intel/i82371eb/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82371eb/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -25,7 +25,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82371eb/enable_rom.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c)
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+static void i82371eb_enable_rom(void)
+{
+	u16 reg16;
+	device_t dev;
+
+	/*
+	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
+	 * PCI bus:device.function locations on different boards.
+	 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
+	 * But scanning for the PCI IDs (instead of hardcoding
+	 * bus/device/function numbers) works on all boards.
+	 */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
+
+	/* Enable access to the whole ROM, disable ROM write access. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= LOWER_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE_1MB;
+	reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
+	pci_write_config16(dev, XBCS, reg16);
+}

Copied: trunk/src/southbridge/intel/i82371eb/fadt.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/fadt.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c)
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9 at btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ * Reference: ACPIspec40a, 5.2.9, page 118
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	device_t dev;
+
+	/* Power management controller */
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 42;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = 0; /* unspecified */
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0; /* smi command port */
+	fadt->acpi_enable = 0; /* acpi enable smi command */
+	fadt->acpi_disable = 0; /* acpi disable smi command */
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = DEFAULT_PMBASE;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
+	fadt->pm1b_cnt_blk = 0x0;
+
+	fadt->pm2_cnt_blk = 0;
+	fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
+	fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
+	fadt->gpe1_blk = 0x0;
+	fadt->gpe1_base = 0;
+	fadt->gpe1_blk_len = 0;
+
+	/* *_len define register width in bytes */
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0; /* not supported */
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 4;
+
+	fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
+	fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
+	fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
+	fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
+	fadt->duty_width = 3; /* this width is in bits */
+	fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+	fadt->mon_alrm = 0x0; /* not supported */
+	fadt->century = 0x0; /* not supported */
+	/*
+	 * bit  meaning
+	 * 0    1: We have user-visible legacy devices
+	 * 1    1: 8042
+	 * 2    0: VGA is ok to probe
+	 * 3    1: MSI are not supported
+	 */
+	fadt->iapc_boot_arch = 0xb;
+	/*
+	 * bit  meaning
+	 * 0    WBINVD
+	 *      Processors in new ACPI-compatible systems are required to
+	 *      support this function and indicate this to OSPM by setting
+	 *      this field.
+	 * 1    WBINVD_FLUSH
+	 *      If set, indicates that the hardware flushes all caches on the
+	 *      WBINVD instruction and maintains memory coherency, but does
+	 *      not guarantee the caches are invalidated.
+	 * 2    PROC_C1
+	 *      C1 power state (x86 hlt instruction) is supported on all cpus
+	 * 3    P_LVL2_UP
+	 *      0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
+	 * 4    PWR_BUTTON
+	 *      0: pwr button is fixed feature
+	 *      1: pwr button has control method device if present
+	 * 5    SLP_BUTTON
+	 *      0: sleep button is fixed feature
+	 *      1: sleep button has control method device if present
+	 * 6    FIX_RTC
+	 *      0: RTC wake status supported in fixed register spce
+	 * 7    RTC_S4
+	 *      1: RTC can wake from S4
+	 * 8    TMR_VAL_EXT
+	 *      1: pmtimer is 32bit, 0: pmtimer is 24bit
+	 * 9    DCK_CAP
+	 *      1: system supports docking station
+	 * 10   RESET_REG_SUPPORT
+	 *      1: fadt describes reset register for system reset
+	 * 11   SEALED_CASE
+	 *      1: No expansion possible, sealed case
+	 * 12   HEADLESS
+	 *      1: Video output, keyboard and mouse are not connected
+	 * 13   CPU_SW_SLP
+	 *      1: Special processor instruction needs to be executed
+	 *      after writing SLP_TYP
+	 * 14   PCI_EXP_WAK
+	 *      1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
+	 *      on platforms with pci express support
+	 * 15   USE_PLATFORM_CLOCK
+	 *      1: OS should prefer platform clock over processor internal
+	 *      clock.
+	 * 16   S4_RTC_STS_VALID
+	 * 17   REMOTE_POWER_ON_CAPABLE
+	 *      1: platform correctly supports OSPM leaving GPE wake events
+	 *      armed prior to an S5 transition.
+	 * 18   FORCE_APIC_CLUSTER_MODEL
+	 * 19   FORCE_APIC_PHYSICAL_DESTINATION_MODE
+	 */
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+	fadt->reset_value = 0;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}

Copied: trunk/src/southbridge/intel/i82371eb/ide.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* TODO: Check if this really works for all of the southbridges. */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
+ * enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * Depending on the configuration variable 'ide_legacy_enable' enable or
+ * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
+ * registers (this is required for e.g. FILO).
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_enable(struct device *dev)
+{
+	u16 reg16;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+	/* Enable/disable the primary IDE interface. */
+	reg16 = pci_read_config16(dev, IDETIM_PRI);
+	reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_PRI, reg16);
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+		     conf->ide0_enable ? "on" : "off");
+
+	/* Enable/disable the secondary IDE interface. */
+	reg16 = pci_read_config16(dev, IDETIM_SEC);
+	reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_SEC, reg16);
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+		     conf->ide1_enable ? "on" : "off");
+
+	/* Enable access to the legacy IDE ports (both primary and secondary),
+	 * and the PCI Bus Master IDE I/O registers.
+	 * Only do this if at least one IDE interface is enabled.
+	 */
+	if (conf->ide0_enable || conf->ide1_enable) {
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 = ONOFF(conf->ide_legacy_enable, reg16,
+			      (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+		printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n",
+			     conf->ide_legacy_enable ? "on" : "off");
+	}
+}
+
+/**
+ * Initialize the Ultra DMA/33 support of the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_drive0_udma33_enable',
+ * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
+ * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
+ * the respective IDE controller and drive.
+ *
+ * Only do that if the respective controller is actually enabled, of course.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_udma33(struct device *dev)
+{
+	u8 reg8;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+	/* Enable/disable UDMA/33 operation (primary IDE interface). */
+	if (conf->ide0_enable) {
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0);
+		reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 0,
+			     conf->ide0_drive0_udma33_enable ? "on" : "off");
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 1,
+			     conf->ide0_drive1_udma33_enable ? "on" : "off");
+	}
+
+	/* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
+	if (conf->ide1_enable) {
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0);
+		reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 0,
+			     conf->ide1_drive0_udma33_enable ? "on" : "off");
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 1,
+			     conf->ide1_drive1_udma33_enable ? "on" : "off");
+	}
+}
+
+/**
+ * IDE init for the Intel 82371FB/SB IDE controller.
+ *
+ * These devices do not support UDMA/33, so don't attempt to enable it.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371fb_sb(struct device *dev)
+{
+	ide_init_enable(dev);
+}
+
+/**
+ * IDE init for the Intel 82371AB/EB/MB IDE controller.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371ab_eb_mb(struct device *dev)
+{
+	ide_init_enable(dev);
+	ide_init_udma33(dev);
+}
+
+/* Intel 82371FB/SB */
+static const struct device_operations ide_ops_fb_sb = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init_i82371fb_sb,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371AB/EB/MB */
+static const struct device_operations ide_ops_ab_eb_mb = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init_i82371ab_eb_mb,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371FB (PIIX) */
+static const struct pci_driver ide_driver_fb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371FB_IDE,
+};
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver ide_driver_sb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_IDE,
+};
+
+/* Intel 82371MX (MPIIX) */
+static const struct pci_driver ide_driver_mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE,
+};
+
+/* Intel 82437MX (part of the 430MX chipset) */
+static const struct pci_driver ide_driver_82437mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE,
+};
+
+/* Intel 82371AB/EB/MB */
+static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = {
+	.ops	= &ide_ops_ab_eb_mb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_IDE,
+};

Copied: trunk/src/southbridge/intel/i82371eb/isa.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/isa.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c)
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/isa-dma.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
+#include "i82371eb.h"
+
+#if CONFIG_IOAPIC
+static void enable_intel_82093aa_ioapic(void)
+{
+	u16 reg16;
+	u32 reg32;
+	u8 ioapic_id = 2;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
+
+	/* Enable IOAPIC. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= (1 << 8); /* APIC Chip Select */
+	pci_write_config16(dev, XBCS, reg16);
+
+	/* Set the IOAPIC ID. */
+	*ioapic_index = 0;
+	*ioapic_data = ioapic_id << 24;
+
+	/* Read back and verify the IOAPIC ID. */
+	*ioapic_index = 0;
+	reg32 = (*ioapic_data >> 24) & 0x0f;
+	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+	if (reg32 != ioapic_id)
+		die("IOAPIC error!\n");
+}
+#endif
+
+static void isa_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Initialize the real time clock (RTC). */
+	rtc_init(0);
+
+	/*
+	 * Enable special cycles, needed for soft poweroff.
+	 */
+	reg32 = pci_read_config16(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_SPECIAL;
+	pci_write_config16(dev, PCI_COMMAND, reg32);
+
+	/*
+	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
+	 * bus, which is a subset of ISA. We select the full ISA bus here.
+	 */
+	reg32 = pci_read_config32(dev, GENCFG);
+	reg32 |= ISA;	/* Select ISA, not EIO. */
+	pci_write_config16(dev, GENCFG, reg32);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+#if CONFIG_IOAPIC
+	/*
+	 * Unlike most other southbridges the 82371EB doesn't have a built-in
+	 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
+	 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
+	 *
+	 * Thus, we can/must only enable the IOAPIC if it actually exists,
+	 * i.e. the respective mainboard does "select IOAPIC".
+	 */
+	enable_intel_82093aa_ioapic();
+#endif
+}
+
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 2);
+	res->base = 0xff800000UL;
+	res->size = 0x00800000UL; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+
+#if CONFIG_IOAPIC
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+#endif
+}
+
+static const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.scan_bus		= scan_static_bus,	/* TODO: Needed? */
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_ISA,
+};
+
+static const struct pci_driver isa_SB_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_ISA,
+};

Copied: trunk/src/southbridge/intel/i82371eb/reset.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "i82371eb.h"
+
+/**
+ * Initiate a hard reset.
+ */
+void i82371eb_hard_reset(void)
+{
+	outb(SRST | RCPU, RC);
+}

Copied and modified: trunk/src/southbridge/intel/i82371eb/smbus.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82371eb/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -29,7 +29,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 static void pwrmgt_enable(struct device *dev)
 {

Copied: trunk/src/southbridge/intel/i82371eb/smbus.h (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h)
@@ -0,0 +1,115 @@
+#include <device/smbus_def.h>
+#include "i82371eb.h"
+
+#define SMBHST_STATUS 	0x0
+#define SMBHST_CTL    	0x2
+#define SMBHST_CMD  	0x3
+#define SMBHST_ADDR 	0x4
+#define SMBHST_DAT  	0x5
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0x1e
+#define SMBUS_ERROR_FLAG (1<<2)
+
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(smbus_io_base + SMBHST_STATUS);
+		if ((val & 0x1) == 0) {
+			break;
+		}
+#if 0
+		if(loops == (SMBUS_TIMEOUT / 2)) {
+			outw(inw(smbus_io_base + SMBHST_STATUS),
+				smbus_io_base + SMBHST_STATUS);
+		}
+#endif
+	} while(--loops);
+	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned short val;
+		smbus_delay();
+
+		val = inb(smbus_io_base + SMBHST_STATUS);
+		// Make sure the command is done
+		if ((val & 0x1) != 0) {
+			continue;
+		}
+		// Don't break out until one of the interrupt
+		// flags is set.
+		if (val & 0xfe) {
+			break;
+		}
+	} while(--loops);
+	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+}
+
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned status_register;
+	unsigned byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+
+	/* setup transaction */
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(0x1e, smbus_io_base + SMBHST_STATUS);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR);
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHST_CMD);
+
+	/* clear the data word...*/
+	outb(0, smbus_io_base + SMBHST_DAT);
+
+	/* start a byte read with interrupts disabled */
+	outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	status_register = inw(smbus_io_base + SMBHST_STATUS);
+
+	/* read results of transaction */
+	byte = inw(smbus_io_base + SMBHST_DAT) & 0xff;
+
+	if (status_register & 0x04) {
+#if 0
+ 		print_debug("Read fail ");
+		print_debug_hex16(status_register);
+		print_debug("\n");
+#endif
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/i82371eb/usb.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c)
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the USB (UHCI) controller.
+ *
+ * Depending on the configuration variable 'usb_enable', enable or
+ * disable the USB (UHCI) controller.
+ *
+ * @param dev The device to use.
+ */
+static void usb_init(struct device *dev)
+{
+	/* TODO: No special init needed? */
+}
+
+static const struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver usb_driver_sb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_USB,
+};
+
+/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */
+/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */
+static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_USB,
+};

Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801ax/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,15 +19,15 @@
 ##
 
 driver-y += i82801ax.c
-driver-y += i82801ax_ac97.c
-driver-y += i82801ax_ide.c
-driver-y += i82801ax_lpc.c
-driver-y += i82801ax_pci.c
-driver-y += i82801ax_smbus.c
-driver-y += i82801ax_usb.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += pci.c
+driver-y += smbus.c
+driver-y += usb.c
 
-ramstage-y += i82801ax_reset.c
-ramstage-y += i82801ax_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-romstage-y += i82801ax_early_smbus.c
+romstage-y += early_smbus.c
 

Copied: trunk/src/southbridge/intel/i82801ax/ac97.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+static struct device_operations ac97_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
+};

Copied and modified: trunk/src/southbridge/intel/i82801ax/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ax/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82801ax/ide.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ * Copyright (C) 2005 Digital Design Corporation
+ * (Written by Steven J. Magnani <steve at digidescorp.com> for Digital Design)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+typedef struct southbridge_intel_i82801ax_config config_t;
+
+static void ide_init(struct device *dev)
+{
+	u16 reg16;
+	config_t *conf = dev->chip_info;
+
+	reg16 = pci_read_config16(dev, IDE_TIM_PRI);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide0_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_PRI, reg16);
+
+	reg16 = pci_read_config16(dev, IDE_TIM_SEC);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide1_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_SEC, reg16);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2411,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2421,
+};

Copied: trunk/src/southbridge/intel/i82801ax/lpc.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c)
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2003 SuSE Linux AG
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801ax.h"
+
+#define GPIO_BASE_ADDR	0x00000500 /* GPIO Base Address Register */
+
+#define NMI_OFF 0
+
+typedef struct southbridge_intel_i82801ax_config config_t;
+
+/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ *
+ * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
+ * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
+ * 1 - The PIRQ is not routed to the 8259.
+ */
+
+#define PIRQA 0x03
+#define PIRQB 0x04
+#define PIRQC 0x05
+#define PIRQD 0x06
+
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your devicetree.cb.
+ */
+static void i82801ax_enable_apic(struct device *dev)
+{
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Enable ACPI I/O range decode and ACPI power management. */
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
+	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
+	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	/* TODO: From i82801ca, needed/useful on other ICH? */
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void i82801ax_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+	/* TODO: Explain/#define the real meaning of these magic numbers. */
+}
+
+static void i82801ax_pirq_init(device_t dev)
+{
+	u8 reg8;
+	config_t *config = dev->chip_info;
+
+	reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
+	pci_write_config8(dev, PIRQA_ROUT, reg8);
+
+	reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
+	pci_write_config8(dev, PIRQB_ROUT, reg8);
+
+	reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
+	pci_write_config8(dev, PIRQC_ROUT, reg8);
+
+	reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
+	pci_write_config8(dev, PIRQD_ROUT, reg8);
+}
+
+static void i82801ax_power_options(device_t dev)
+{
+	uint8_t byte;
+	int pwr_on = -1;
+	int nmi_option;
+
+	/* power after power fail */
+	/* FIXME this doesn't work! */
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 */
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
+
+	/* Set up NMI on errors. */
+	byte = inb(0x61);
+	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	byte &= ~(1 << 2);	/* PCI SERR# Enable */
+	outb(byte, 0x61);
+	byte = inb(0x70);
+
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* Set NMI. */
+		outb(byte, 0x70);
+	}
+}
+
+static void gpio_init(device_t dev)
+{
+	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
+}
+
+static void i82801ax_rtc_init(struct device *dev)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~(1 << 1);	/* Preserve the power fail state. */
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	reg32 = pci_read_config32(dev, GEN_STA);
+	rtc_failed |= reg32 & (1 << 2);
+	rtc_init(rtc_failed);
+
+	/* Enable access to the upper 128 byte bank of CMOS RAM. */
+	pci_write_config8(dev, RTC_CONF, 0x04);
+}
+
+static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
+{
+	uint16_t reg16;
+	int i;
+
+	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+	reg16 &= 0x300;
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, reg16);
+}
+
+static void i82801ax_lpc_decode_en(device_t dev)
+{
+	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+	 * We also need to set the value for LPC I/F Enables Register.
+	 */
+	pci_write_config8(dev, COM_DEC, 0x10);
+	pci_write_config16(dev, LPC_EN, 0x300F);
+}
+
+static void lpc_init(struct device *dev)
+{
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	i82801ax_enable_apic(dev);
+
+	i82801ax_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	i82801ax_pirq_init(dev);
+
+	/* Setup power options. */
+	i82801ax_power_options(dev);
+
+	/* Set the state of the GPIO lines. */
+	gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	i82801ax_rtc_init(dev);
+
+	/* Route DMA. */
+	i82801ax_lpc_route_dma(dev, 0xff);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Setup decode ports and LPC I/F enables. */
+	i82801ax_lpc_decode_en(dev);
+}
+
+static void i82801ax_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources		= i82801ax_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_lpc __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2410,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_lpc __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2420,
+};

Copied: trunk/src/southbridge/intel/i82801ax/pci.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c)
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+
+	/* Clear possible errors. */
+	reg16 = pci_read_config16(dev, PCI_STATUS);
+	reg16 |= 0xf900;
+	pci_write_config16(dev, PCI_STATUS, reg16);
+}
+
+static struct device_operations pci_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_pci __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2418,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_pci __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2428,
+};

Copied: trunk/src/southbridge/intel/i82801ax/reset.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm at xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
+}

Copied and modified: trunk/src/southbridge/intel/i82801ax/smbus.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ax/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i82801ax/smbus.h (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h)
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+#include "i82801ax.h"
+
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_io_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40),
+	     smbus_io_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i82801ax/usb.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+static void usb_init(struct device *dev)
+{
+	/* TODO: Any init needed? Some ports have it, others don't. */
+}
+
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_USB,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_USB,
+};

Copied: trunk/src/southbridge/intel/i82801ax/watchdog.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly a