[coreboot] [commit] r6149 - in trunk/src: mainboard/advantech/pcm-5820 mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/norwich mainboard/amd/pistach...

repository service svn at coreboot.org
Wed Dec 8 06:42:48 CET 2010


Author: stepan
Date: Wed Dec  8 06:42:47 2010
New Revision: 6149
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6149

Log:
first round name simplification. drop the <component>_ prefix.

the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan at coresystems.de>

Acked-by: Patrick Georgi <patrick at georgi-clan.de>
Acked-by: Peter Stuge <peter at stuge.se>

Added:
   trunk/src/southbridge/amd/amd8111/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c
   trunk/src/southbridge/amd/amd8111/acpi.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c
   trunk/src/southbridge/amd/amd8111/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
   trunk/src/southbridge/amd/amd8111/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c
   trunk/src/southbridge/amd/amd8111/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c
   trunk/src/southbridge/amd/amd8111/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c
   trunk/src/southbridge/amd/amd8111/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/src/southbridge/amd/amd8111/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c
   trunk/src/southbridge/amd/amd8111/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c
   trunk/src/southbridge/amd/amd8111/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c
   trunk/src/southbridge/amd/amd8111/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c
   trunk/src/southbridge/amd/amd8111/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c
   trunk/src/southbridge/amd/amd8111/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c
   trunk/src/southbridge/amd/amd8131-disable/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8131/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8132/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/src/southbridge/amd/amd8151/agp3.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c
   trunk/src/southbridge/amd/cs5530/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c
   trunk/src/southbridge/amd/cs5530/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c
   trunk/src/southbridge/amd/cs5530/isa.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/src/southbridge/amd/cs5530/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c
   trunk/src/southbridge/amd/cs5530/vga.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c
   trunk/src/southbridge/amd/cs5535/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c
   trunk/src/southbridge/amd/cs5535/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c
   trunk/src/southbridge/amd/cs5535/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c
   trunk/src/southbridge/amd/cs5535/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h
   trunk/src/southbridge/amd/cs5536/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
   trunk/src/southbridge/amd/cs5536/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c
   trunk/src/southbridge/amd/cs5536/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c
   trunk/src/southbridge/amd/cs5536/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c
   trunk/src/southbridge/amd/cs5536/smbus2.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h
   trunk/src/southbridge/amd/rs690/cmn.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/src/southbridge/amd/rs690/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c
   trunk/src/southbridge/amd/rs690/gfx.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/src/southbridge/amd/rs690/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c
   trunk/src/southbridge/amd/rs690/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c
   trunk/src/southbridge/amd/rs780/cmn.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c
   trunk/src/southbridge/amd/rs780/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/amd/rs780/gfx.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c
   trunk/src/southbridge/amd/rs780/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c
   trunk/src/southbridge/amd/rs780/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c
   trunk/src/southbridge/amd/rs780/rev.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h
   trunk/src/southbridge/amd/sb600/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c
   trunk/src/southbridge/amd/sb600/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_early_setup.c
   trunk/src/southbridge/amd/sb600/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c
   trunk/src/southbridge/amd/sb600/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
   trunk/src/southbridge/amd/sb600/hda.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c
   trunk/src/southbridge/amd/sb600/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c
   trunk/src/southbridge/amd/sb600/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/src/southbridge/amd/sb600/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c
   trunk/src/southbridge/amd/sb600/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c
   trunk/src/southbridge/amd/sb600/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c
   trunk/src/southbridge/amd/sb600/sm.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_sm.c
   trunk/src/southbridge/amd/sb600/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.c
   trunk/src/southbridge/amd/sb600/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h
   trunk/src/southbridge/amd/sb600/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c
   trunk/src/southbridge/amd/sb700/early_setup.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_early_setup.c
   trunk/src/southbridge/amd/sb700/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
   trunk/src/southbridge/amd/sb700/hda.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c
   trunk/src/southbridge/amd/sb700/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c
   trunk/src/southbridge/amd/sb700/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c
   trunk/src/southbridge/amd/sb700/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c
   trunk/src/southbridge/amd/sb700/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c
   trunk/src/southbridge/amd/sb700/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c
   trunk/src/southbridge/amd/sb700/sm.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_sm.c
   trunk/src/southbridge/amd/sb700/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.c
   trunk/src/southbridge/amd/sb700/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h
   trunk/src/southbridge/amd/sb700/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c
   trunk/src/southbridge/broadcom/bcm21000/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c
   trunk/src/southbridge/broadcom/bcm5780/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/pcix.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
   trunk/src/southbridge/broadcom/bcm5785/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
   trunk/src/southbridge/broadcom/bcm5785/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
   trunk/src/southbridge/broadcom/bcm5785/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
   trunk/src/southbridge/broadcom/bcm5785/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
   trunk/src/southbridge/broadcom/bcm5785/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/src/southbridge/broadcom/bcm5785/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
   trunk/src/southbridge/broadcom/bcm5785/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
   trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c
      - copied, changed from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/src/southbridge/broadcom/bcm5785/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
   trunk/src/southbridge/broadcom/bcm5785/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
   trunk/src/southbridge/intel/esb6300/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c
   trunk/src/southbridge/intel/esb6300/bridge1c.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/src/southbridge/intel/esb6300/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/src/southbridge/intel/esb6300/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c
   trunk/src/southbridge/intel/esb6300/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c
   trunk/src/southbridge/intel/esb6300/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/src/southbridge/intel/esb6300/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c
   trunk/src/southbridge/intel/esb6300/pic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c
   trunk/src/southbridge/intel/esb6300/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c
   trunk/src/southbridge/intel/esb6300/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/src/southbridge/intel/esb6300/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.c
   trunk/src/southbridge/intel/esb6300/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h
   trunk/src/southbridge/intel/esb6300/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c
   trunk/src/southbridge/intel/i3100/early_lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/src/southbridge/intel/i3100/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/src/southbridge/intel/i3100/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c
   trunk/src/southbridge/intel/i3100/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/src/southbridge/intel/i3100/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c
   trunk/src/southbridge/intel/i3100/pciexp_portb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c
   trunk/src/southbridge/intel/i3100/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c
   trunk/src/southbridge/intel/i3100/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c
   trunk/src/southbridge/intel/i3100/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.c
   trunk/src/southbridge/intel/i3100/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h
   trunk/src/southbridge/intel/i3100/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c
   trunk/src/southbridge/intel/i82371eb/early_pm.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
   trunk/src/southbridge/intel/i82371eb/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
   trunk/src/southbridge/intel/i82371eb/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
   trunk/src/southbridge/intel/i82371eb/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c
   trunk/src/southbridge/intel/i82371eb/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c
   trunk/src/southbridge/intel/i82371eb/isa.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/src/southbridge/intel/i82371eb/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c
   trunk/src/southbridge/intel/i82371eb/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c
   trunk/src/southbridge/intel/i82371eb/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
   trunk/src/southbridge/intel/i82371eb/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c
   trunk/src/southbridge/intel/i82801ax/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c
   trunk/src/southbridge/intel/i82801ax/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
   trunk/src/southbridge/intel/i82801ax/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c
   trunk/src/southbridge/intel/i82801ax/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
   trunk/src/southbridge/intel/i82801ax/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c
   trunk/src/southbridge/intel/i82801ax/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c
   trunk/src/southbridge/intel/i82801ax/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c
   trunk/src/southbridge/intel/i82801ax/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
   trunk/src/southbridge/intel/i82801ax/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c
   trunk/src/southbridge/intel/i82801ax/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
   trunk/src/southbridge/intel/i82801bx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c
   trunk/src/southbridge/intel/i82801bx/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
   trunk/src/southbridge/intel/i82801bx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c
   trunk/src/southbridge/intel/i82801bx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
   trunk/src/southbridge/intel/i82801bx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c
   trunk/src/southbridge/intel/i82801bx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c
   trunk/src/southbridge/intel/i82801bx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c
   trunk/src/southbridge/intel/i82801bx/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c
   trunk/src/southbridge/intel/i82801bx/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
   trunk/src/southbridge/intel/i82801bx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c
   trunk/src/southbridge/intel/i82801bx/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
   trunk/src/southbridge/intel/i82801cx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c
   trunk/src/southbridge/intel/i82801cx/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
   trunk/src/southbridge/intel/i82801cx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c
   trunk/src/southbridge/intel/i82801cx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
   trunk/src/southbridge/intel/i82801cx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c
   trunk/src/southbridge/intel/i82801cx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c
   trunk/src/southbridge/intel/i82801cx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c
   trunk/src/southbridge/intel/i82801cx/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c
   trunk/src/southbridge/intel/i82801cx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c
   trunk/src/southbridge/intel/i82801dx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c
   trunk/src/southbridge/intel/i82801dx/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
   trunk/src/southbridge/intel/i82801dx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c
   trunk/src/southbridge/intel/i82801dx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
   trunk/src/southbridge/intel/i82801dx/nvs.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h
   trunk/src/southbridge/intel/i82801dx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c
   trunk/src/southbridge/intel/i82801dx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c
   trunk/src/southbridge/intel/i82801dx/smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c
   trunk/src/southbridge/intel/i82801dx/smi.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c
   trunk/src/southbridge/intel/i82801dx/smihandler.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c
   trunk/src/southbridge/intel/i82801dx/tco_timer.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
   trunk/src/southbridge/intel/i82801dx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c
   trunk/src/southbridge/intel/i82801dx/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c
   trunk/src/southbridge/intel/i82801ex/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c
   trunk/src/southbridge/intel/i82801ex/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
   trunk/src/southbridge/intel/i82801ex/ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c
   trunk/src/southbridge/intel/i82801ex/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c
   trunk/src/southbridge/intel/i82801ex/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
   trunk/src/southbridge/intel/i82801ex/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c
   trunk/src/southbridge/intel/i82801ex/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c
   trunk/src/southbridge/intel/i82801ex/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c
   trunk/src/southbridge/intel/i82801ex/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c
   trunk/src/southbridge/intel/i82801ex/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h
   trunk/src/southbridge/intel/i82801ex/uhci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c
   trunk/src/southbridge/intel/i82801ex/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
   trunk/src/southbridge/intel/i82801gx/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c
   trunk/src/southbridge/intel/i82801gx/acpi/ac97.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
   trunk/src/southbridge/intel/i82801gx/acpi/audio.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
   trunk/src/southbridge/intel/i82801gx/acpi/irqlinks.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
   trunk/src/southbridge/intel/i82801gx/acpi/lpc.asl
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pata.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pci.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
   trunk/src/southbridge/intel/i82801gx/acpi/pcie.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
   trunk/src/southbridge/intel/i82801gx/acpi/sata.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/smbus.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
   trunk/src/southbridge/intel/i82801gx/acpi/usb.asl
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
   trunk/src/southbridge/intel/i82801gx/azalia.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c
   trunk/src/southbridge/intel/i82801gx/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c
   trunk/src/southbridge/intel/i82801gx/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/src/southbridge/intel/i82801gx/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c
   trunk/src/southbridge/intel/i82801gx/nvs.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h
   trunk/src/southbridge/intel/i82801gx/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c
   trunk/src/southbridge/intel/i82801gx/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c
   trunk/src/southbridge/intel/i82801gx/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c
   trunk/src/southbridge/intel/i82801gx/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c
   trunk/src/southbridge/intel/i82801gx/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c
   trunk/src/southbridge/intel/i82801gx/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
   trunk/src/southbridge/intel/i82801gx/smi.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c
   trunk/src/southbridge/intel/i82801gx/smihandler.c
      - copied, changed from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
   trunk/src/southbridge/intel/i82801gx/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c
   trunk/src/southbridge/intel/i82801gx/usb_debug.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
   trunk/src/southbridge/intel/i82801gx/usb_ehci.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
   trunk/src/southbridge/intel/i82801gx/watchdog.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
   trunk/src/southbridge/intel/i82870/ioapic.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_ioapic.c
   trunk/src/southbridge/intel/i82870/pci_parity.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c
   trunk/src/southbridge/intel/i82870/pcibridge.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c
   trunk/src/southbridge/intel/pxhd/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
   trunk/src/southbridge/nvidia/ck804/ac97.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ac97.c
   trunk/src/southbridge/nvidia/ck804/early_setup.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/src/southbridge/nvidia/ck804/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
   trunk/src/southbridge/nvidia/ck804/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/src/southbridge/nvidia/ck804/early_smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.h
   trunk/src/southbridge/nvidia/ck804/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c
   trunk/src/southbridge/nvidia/ck804/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
   trunk/src/southbridge/nvidia/ck804/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_fadt.c
   trunk/src/southbridge/nvidia/ck804/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ht.c
   trunk/src/southbridge/nvidia/ck804/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_ide.c
   trunk/src/southbridge/nvidia/ck804/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/src/southbridge/nvidia/ck804/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/src/southbridge/nvidia/ck804/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/src/southbridge/nvidia/ck804/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_pcie.c
   trunk/src/southbridge/nvidia/ck804/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_reset.c
   trunk/src/southbridge/nvidia/ck804/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/src/southbridge/nvidia/ck804/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/ck804/ck804_smbus.c
   trunk/src/southbridge/nvidia/ck804/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/src/southbridge/nvidia/ck804/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_usb.c
   trunk/src/southbridge/nvidia/ck804/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/ck804/ck804_usb2.c
   trunk/src/southbridge/nvidia/mcp55/azalia.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c
   trunk/src/southbridge/nvidia/mcp55/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/src/southbridge/nvidia/mcp55/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
   trunk/src/southbridge/nvidia/mcp55/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/src/southbridge/nvidia/mcp55/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
   trunk/src/southbridge/nvidia/mcp55/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
   trunk/src/southbridge/nvidia/mcp55/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c
   trunk/src/southbridge/nvidia/mcp55/ht.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_ht.c
   trunk/src/southbridge/nvidia/mcp55/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_ide.c
   trunk/src/southbridge/nvidia/mcp55/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/src/southbridge/nvidia/mcp55/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_nic.c
   trunk/src/southbridge/nvidia/mcp55/pci.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/src/southbridge/nvidia/mcp55/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_pcie.c
   trunk/src/southbridge/nvidia/mcp55/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/src/southbridge/nvidia/mcp55/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_sata.c
   trunk/src/southbridge/nvidia/mcp55/smbus.c
      - copied, changed from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/src/southbridge/nvidia/mcp55/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h
   trunk/src/southbridge/nvidia/mcp55/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_usb.c
   trunk/src/southbridge/nvidia/mcp55/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/nvidia/mcp55/mcp55_usb2.c
   trunk/src/southbridge/sis/sis966/aza.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_aza.c
   trunk/src/southbridge/sis/sis966/early_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/src/southbridge/sis/sis966/early_setup_car.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c
   trunk/src/southbridge/sis/sis966/early_setup_ss.h
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_early_setup_ss.h
   trunk/src/southbridge/sis/sis966/early_smbus.c
      - copied, changed from r6148, trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/src/southbridge/sis/sis966/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_enable_rom.c
   trunk/src/southbridge/sis/sis966/enable_usbdebug.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
   trunk/src/southbridge/sis/sis966/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_ide.c
   trunk/src/southbridge/sis/sis966/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/src/southbridge/sis/sis966/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_nic.c
   trunk/src/southbridge/sis/sis966/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_pcie.c
   trunk/src/southbridge/sis/sis966/reset.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_reset.c
   trunk/src/southbridge/sis/sis966/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_sata.c
   trunk/src/southbridge/sis/sis966/smbus.h
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_smbus.h
   trunk/src/southbridge/sis/sis966/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_usb.c
   trunk/src/southbridge/sis/sis966/usb2.c
      - copied unchanged from r6148, trunk/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/src/southbridge/ti/pci7420/cardbus.c
      - copied unchanged from r6148, trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c
   trunk/src/southbridge/ti/pci7420/firewire.c
      - copied unchanged from r6148, trunk/src/southbridge/ti/pci7420/pci7420_firewire.c
   trunk/src/southbridge/via/k8t890/bridge.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_bridge.c
   trunk/src/southbridge/via/k8t890/chrome.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8m890_chrome.c
   trunk/src/southbridge/via/k8t890/ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/dram.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_dram.c
   trunk/src/southbridge/via/k8t890/early_car.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/southbridge/via/k8t890/error.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_error.c
   trunk/src/southbridge/via/k8t890/host.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_host.c
   trunk/src/southbridge/via/k8t890/host_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c
   trunk/src/southbridge/via/k8t890/pcie.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_pcie.c
   trunk/src/southbridge/via/k8t890/traf_ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
   trunk/src/southbridge/via/vt8231/acpi.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_acpi.c
   trunk/src/southbridge/via/vt8231/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
   trunk/src/southbridge/via/vt8231/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
   trunk/src/southbridge/via/vt8231/enable_rom.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
   trunk/src/southbridge/via/vt8231/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_ide.c
   trunk/src/southbridge/via/vt8231/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/src/southbridge/via/vt8231/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_nic.c
   trunk/src/southbridge/via/vt8231/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8231/vt8231_usb.c
   trunk/src/southbridge/via/vt8235/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
   trunk/src/southbridge/via/vt8235/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
   trunk/src/southbridge/via/vt8235/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_ide.c
   trunk/src/southbridge/via/vt8235/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/src/southbridge/via/vt8235/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_nic.c
   trunk/src/southbridge/via/vt8235/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8235/vt8235_usb.c
   trunk/src/southbridge/via/vt8237r/ctrl.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/early_smbus.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/src/southbridge/via/vt8237r/fadt.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
   trunk/src/southbridge/via/vt8237r/ide.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/src/southbridge/via/vt8237r/lpc.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/src/southbridge/via/vt8237r/nic.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_nic.c
   trunk/src/southbridge/via/vt8237r/pirq.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c
   trunk/src/southbridge/via/vt8237r/sata.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_sata.c
   trunk/src/southbridge/via/vt8237r/usb.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt8237r/vt8237r_usb.c
   trunk/src/southbridge/via/vt82c686/early_serial.c
      - copied unchanged from r6148, trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c
Deleted:
   trunk/src/southbridge/amd/amd8111/amd8111_ac97.c
   trunk/src/southbridge/amd/amd8111/amd8111_acpi.c
   trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
   trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c
   trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c
   trunk/src/southbridge/amd/amd8111/amd8111_ide.c
   trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
   trunk/src/southbridge/amd/amd8111/amd8111_nic.c
   trunk/src/southbridge/amd/amd8111/amd8111_pci.c
   trunk/src/southbridge/amd/amd8111/amd8111_reset.c
   trunk/src/southbridge/amd/amd8111/amd8111_smbus.c
   trunk/src/southbridge/amd/amd8111/amd8111_usb.c
   trunk/src/southbridge/amd/amd8111/amd8111_usb2.c
   trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8131/amd8131_bridge.c
   trunk/src/southbridge/amd/amd8132/amd8132_bridge.c
   trunk/src/southbridge/amd/amd8151/amd8151_agp3.c
   trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c
   trunk/src/southbridge/amd/cs5530/cs5530_ide.c
   trunk/src/southbridge/amd/cs5530/cs5530_isa.c
   trunk/src/southbridge/amd/cs5530/cs5530_pirq.c
   trunk/src/southbridge/amd/cs5530/cs5530_vga.c
   trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c
   trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c
   trunk/src/southbridge/amd/cs5535/cs5535_ide.c
   trunk/src/southbridge/amd/cs5535/cs5535_smbus.h
   trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
   trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c
   trunk/src/southbridge/amd/cs5536/cs5536_ide.c
   trunk/src/southbridge/amd/cs5536/cs5536_pirq.c
   trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h
   trunk/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/src/southbridge/amd/rs690/rs690_early_setup.c
   trunk/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/src/southbridge/amd/rs690/rs690_ht.c
   trunk/src/southbridge/amd/rs690/rs690_pcie.c
   trunk/src/southbridge/amd/rs780/rs780_cmn.c
   trunk/src/southbridge/amd/rs780/rs780_early_setup.c
   trunk/src/southbridge/amd/rs780/rs780_gfx.c
   trunk/src/southbridge/amd/rs780/rs780_ht.c
   trunk/src/southbridge/amd/rs780/rs780_pcie.c
   trunk/src/southbridge/amd/rs780/rs780_rev.h
   trunk/src/southbridge/amd/sb600/sb600_ac97.c
   trunk/src/southbridge/amd/sb600/sb600_early_setup.c
   trunk/src/southbridge/amd/sb600/sb600_enable_rom.c
   trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
   trunk/src/southbridge/amd/sb600/sb600_hda.c
   trunk/src/southbridge/amd/sb600/sb600_ide.c
   trunk/src/southbridge/amd/sb600/sb600_lpc.c
   trunk/src/southbridge/amd/sb600/sb600_pci.c
   trunk/src/southbridge/amd/sb600/sb600_reset.c
   trunk/src/southbridge/amd/sb600/sb600_sata.c
   trunk/src/southbridge/amd/sb600/sb600_sm.c
   trunk/src/southbridge/amd/sb600/sb600_smbus.c
   trunk/src/southbridge/amd/sb600/sb600_smbus.h
   trunk/src/southbridge/amd/sb600/sb600_usb.c
   trunk/src/southbridge/amd/sb700/sb700_early_setup.c
   trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
   trunk/src/southbridge/amd/sb700/sb700_hda.c
   trunk/src/southbridge/amd/sb700/sb700_ide.c
   trunk/src/southbridge/amd/sb700/sb700_lpc.c
   trunk/src/southbridge/amd/sb700/sb700_pci.c
   trunk/src/southbridge/amd/sb700/sb700_reset.c
   trunk/src/southbridge/amd/sb700/sb700_sata.c
   trunk/src/southbridge/amd/sb700/sb700_sm.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.c
   trunk/src/southbridge/amd/sb700/sb700_smbus.h
   trunk/src/southbridge/amd/sb700/sb700_usb.c
   trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c
   trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
   trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
   trunk/src/southbridge/intel/esb6300/esb6300_ac97.c
   trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c
   trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/src/southbridge/intel/esb6300/esb6300_ehci.c
   trunk/src/southbridge/intel/esb6300/esb6300_ide.c
   trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
   trunk/src/southbridge/intel/esb6300/esb6300_pci.c
   trunk/src/southbridge/intel/esb6300/esb6300_pic.c
   trunk/src/southbridge/intel/esb6300/esb6300_reset.c
   trunk/src/southbridge/intel/esb6300/esb6300_sata.c
   trunk/src/southbridge/intel/esb6300/esb6300_smbus.c
   trunk/src/southbridge/intel/esb6300/esb6300_smbus.h
   trunk/src/southbridge/intel/esb6300/esb6300_uhci.c
   trunk/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/src/southbridge/intel/i3100/i3100_ehci.c
   trunk/src/southbridge/intel/i3100/i3100_lpc.c
   trunk/src/southbridge/intel/i3100/i3100_pci.c
   trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c
   trunk/src/southbridge/intel/i3100/i3100_reset.c
   trunk/src/southbridge/intel/i3100/i3100_sata.c
   trunk/src/southbridge/intel/i3100/i3100_smbus.c
   trunk/src/southbridge/intel/i3100/i3100_smbus.h
   trunk/src/southbridge/intel/i3100/i3100_uhci.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c
   trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h
   trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h
   trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c
   trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h
   trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c
   trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c
   trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h
   trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c
   trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h
   trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c
   trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
   trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
   trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h
   trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
   trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
   trunk/src/southbridge/intel/i82870/p64h2_ioapic.c
   trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c
   trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c
   trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
   trunk/src/southbridge/nvidia/ck804/ck804_ac97.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
   trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.h
   trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c
   trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
   trunk/src/southbridge/nvidia/ck804/ck804_fadt.c
   trunk/src/southbridge/nvidia/ck804/ck804_ht.c
   trunk/src/southbridge/nvidia/ck804/ck804_ide.c
   trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
   trunk/src/southbridge/nvidia/ck804/ck804_nic.c
   trunk/src/southbridge/nvidia/ck804/ck804_pci.c
   trunk/src/southbridge/nvidia/ck804/ck804_pcie.c
   trunk/src/southbridge/nvidia/ck804/ck804_reset.c
   trunk/src/southbridge/nvidia/ck804/ck804_sata.c
   trunk/src/southbridge/nvidia/ck804/ck804_smbus.c
   trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/src/southbridge/nvidia/ck804/ck804_usb.c
   trunk/src/southbridge/nvidia/ck804/ck804_usb2.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
   trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_ht.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_ide.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_nic.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_pci.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_pcie.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_sata.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h
   trunk/src/southbridge/nvidia/mcp55/mcp55_usb.c
   trunk/src/southbridge/nvidia/mcp55/mcp55_usb2.c
   trunk/src/southbridge/sis/sis966/sis966_aza.c
   trunk/src/southbridge/sis/sis966/sis966_early_ctrl.c
   trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c
   trunk/src/southbridge/sis/sis966/sis966_early_setup_ss.h
   trunk/src/southbridge/sis/sis966/sis966_early_smbus.c
   trunk/src/southbridge/sis/sis966/sis966_enable_rom.c
   trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
   trunk/src/southbridge/sis/sis966/sis966_ide.c
   trunk/src/southbridge/sis/sis966/sis966_lpc.c
   trunk/src/southbridge/sis/sis966/sis966_nic.c
   trunk/src/southbridge/sis/sis966/sis966_pcie.c
   trunk/src/southbridge/sis/sis966/sis966_reset.c
   trunk/src/southbridge/sis/sis966/sis966_sata.c
   trunk/src/southbridge/sis/sis966/sis966_smbus.h
   trunk/src/southbridge/sis/sis966/sis966_usb.c
   trunk/src/southbridge/sis/sis966/sis966_usb2.c
   trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c
   trunk/src/southbridge/ti/pci7420/pci7420_firewire.c
   trunk/src/southbridge/via/k8t890/k8m890_chrome.c
   trunk/src/southbridge/via/k8t890/k8t890_bridge.c
   trunk/src/southbridge/via/k8t890/k8t890_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_dram.c
   trunk/src/southbridge/via/k8t890/k8t890_early_car.c
   trunk/src/southbridge/via/k8t890/k8t890_error.c
   trunk/src/southbridge/via/k8t890/k8t890_host.c
   trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c
   trunk/src/southbridge/via/k8t890/k8t890_pcie.c
   trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
   trunk/src/southbridge/via/vt8231/vt8231_acpi.c
   trunk/src/southbridge/via/vt8231/vt8231_early_serial.c
   trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c
   trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c
   trunk/src/southbridge/via/vt8231/vt8231_ide.c
   trunk/src/southbridge/via/vt8231/vt8231_lpc.c
   trunk/src/southbridge/via/vt8231/vt8231_nic.c
   trunk/src/southbridge/via/vt8231/vt8231_usb.c
   trunk/src/southbridge/via/vt8235/vt8235_early_serial.c
   trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c
   trunk/src/southbridge/via/vt8235/vt8235_ide.c
   trunk/src/southbridge/via/vt8235/vt8235_lpc.c
   trunk/src/southbridge/via/vt8235/vt8235_nic.c
   trunk/src/southbridge/via/vt8235/vt8235_usb.c
   trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c
   trunk/src/southbridge/via/vt8237r/vt8237_fadt.c
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
   trunk/src/southbridge/via/vt8237r/vt8237r_ide.c
   trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
   trunk/src/southbridge/via/vt8237r/vt8237r_nic.c
   trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c
   trunk/src/southbridge/via/vt8237r/vt8237r_sata.c
   trunk/src/southbridge/via/vt8237r/vt8237r_usb.c
   trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c
Modified:
   trunk/src/mainboard/advantech/pcm-5820/romstage.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/norwich/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/amd/tilapia_fam10/romstage.c
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/artecgroup/dbe61/romstage.c
   trunk/src/mainboard/asi/mb_5blgp/romstage.c
   trunk/src/mainboard/asi/mb_5blmp/romstage.c
   trunk/src/mainboard/asrock/939a785gmh/romstage.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/m2v/romstage.c
   trunk/src/mainboard/asus/m4a78-em/romstage.c
   trunk/src/mainboard/asus/m4a785-m/romstage.c
   trunk/src/mainboard/axus/tc320/romstage.c
   trunk/src/mainboard/bcom/winnet100/romstage.c
   trunk/src/mainboard/bcom/winnetp680/romstage.c
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/dell/s1850/romstage.c
   trunk/src/mainboard/digitallogic/adl855pc/romstage.c
   trunk/src/mainboard/digitallogic/msm800sev/romstage.c
   trunk/src/mainboard/eaglelion/5bcm/romstage.c
   trunk/src/mainboard/getac/p470/acpi_tables.c
   trunk/src/mainboard/getac/p470/mainboard_smi.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
   trunk/src/mainboard/gigabyte/ma78gm/romstage.c
   trunk/src/mainboard/hp/dl145_g1/romstage.c
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
   trunk/src/mainboard/ibase/mb899/acpi_tables.c
   trunk/src/mainboard/ibase/mb899/mainboard_smi.c
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/iei/juki-511p/romstage.c
   trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
   trunk/src/mainboard/iei/nova4899r/romstage.c
   trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
   trunk/src/mainboard/intel/d945gclf/acpi_tables.c
   trunk/src/mainboard/intel/d945gclf/mainboard_smi.c
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/mainboard/intel/jarrell/romstage.c
   trunk/src/mainboard/intel/mtarvon/romstage.c
   trunk/src/mainboard/intel/truxton/romstage.c
   trunk/src/mainboard/intel/xe7501devkit/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/mainboard/jetway/pa78vm5/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c
   trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/lanner/em8510/romstage.c
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/lippert/hurricane-lx/romstage.c
   trunk/src/mainboard/lippert/literunner-lx/romstage.c
   trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
   trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/pcengines/alix1c/romstage.c
   trunk/src/mainboard/pcengines/alix2d/romstage.c
   trunk/src/mainboard/rca/rm4100/romstage.c
   trunk/src/mainboard/roda/rk886ex/acpi_tables.c
   trunk/src/mainboard/roda/rk886ex/mainboard_smi.c
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/supermicro/x6dai_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/televideo/tc7020/romstage.c
   trunk/src/mainboard/thomson/ip1000/romstage.c
   trunk/src/mainboard/traverse/geos/romstage.c
   trunk/src/mainboard/tyan/s2735/romstage.c
   trunk/src/mainboard/tyan/s2850/romstage.c
   trunk/src/mainboard/tyan/s2875/romstage.c
   trunk/src/mainboard/tyan/s2880/romstage.c
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2882/romstage.c
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2892/romstage.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/mainboard/tyan/s4882/romstage.c
   trunk/src/mainboard/via/epia-cn/romstage.c
   trunk/src/mainboard/via/epia-m/romstage.c
   trunk/src/mainboard/via/epia-n/romstage.c
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/mainboard/via/pc2500e/romstage.c
   trunk/src/mainboard/winent/pl6064/romstage.c
   trunk/src/mainboard/wyse/s50/romstage.c
   trunk/src/southbridge/amd/amd8111/Makefile.inc
   trunk/src/southbridge/amd/amd8111/bootblock.c
   trunk/src/southbridge/amd/amd8131/Makefile.inc
   trunk/src/southbridge/amd/amd8132/Makefile.inc
   trunk/src/southbridge/amd/amd8151/Makefile.inc
   trunk/src/southbridge/amd/cs5530/Makefile.inc
   trunk/src/southbridge/amd/cs5535/Makefile.inc
   trunk/src/southbridge/amd/cs5536/Makefile.inc
   trunk/src/southbridge/amd/rs690/Makefile.inc
   trunk/src/southbridge/amd/rs780/Makefile.inc
   trunk/src/southbridge/amd/rs780/rs780.h
   trunk/src/southbridge/amd/sb600/Makefile.inc
   trunk/src/southbridge/amd/sb600/bootblock.c
   trunk/src/southbridge/amd/sb700/Makefile.inc
   trunk/src/southbridge/broadcom/bcm21000/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5780/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5785/Makefile.inc
   trunk/src/southbridge/broadcom/bcm5785/bootblock.c
   trunk/src/southbridge/intel/esb6300/Makefile.inc
   trunk/src/southbridge/intel/i3100/Makefile.inc
   trunk/src/southbridge/intel/i82371eb/Makefile.inc
   trunk/src/southbridge/intel/i82371eb/bootblock.c
   trunk/src/southbridge/intel/i82801ax/Makefile.inc
   trunk/src/southbridge/intel/i82801bx/Makefile.inc
   trunk/src/southbridge/intel/i82801cx/Makefile.inc
   trunk/src/southbridge/intel/i82801dx/Makefile.inc
   trunk/src/southbridge/intel/i82801ex/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/Makefile.inc
   trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl
   trunk/src/southbridge/intel/i82870/Makefile.inc
   trunk/src/southbridge/intel/pxhd/Makefile.inc
   trunk/src/southbridge/nvidia/ck804/Makefile.inc
   trunk/src/southbridge/nvidia/ck804/bootblock.c
   trunk/src/southbridge/nvidia/mcp55/Makefile.inc
   trunk/src/southbridge/nvidia/mcp55/bootblock.c
   trunk/src/southbridge/sis/sis966/Makefile.inc
   trunk/src/southbridge/ti/pci7420/Makefile.inc
   trunk/src/southbridge/via/k8t890/Makefile.inc
   trunk/src/southbridge/via/vt8231/Makefile.inc
   trunk/src/southbridge/via/vt8235/Makefile.inc
   trunk/src/southbridge/via/vt8237r/Makefile.inc

Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/advantech/pcm-5820/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/db800/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,9 +43,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 #include <spd.h>
 
@@ -69,7 +69,7 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {

Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/norwich/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,9 +38,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,8 +10,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -26,7 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -48,7 +48,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 

Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,8 +33,8 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blgp/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asi/mb_5blgp/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 

Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blmp/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asi/mb_5blmp/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 

Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,9 +44,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -41,8 +41,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -41,8 +41,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -62,7 +62,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m2v/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m2v/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -64,7 +64,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a78-em/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m4a78-em/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/axus/tc320/romstage.c
==============================================================================
--- trunk/src/mainboard/axus/tc320/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/axus/tc320/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/bcom/winnet100/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnet100/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/bcom/winnet100/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/dell/s1850/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc8374/pc8374_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"

Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,8 +12,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/eaglelion/5bcm/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)

Modified: trunk/src/mainboard/getac/p470/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/getac/p470/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/getac/p470/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 
 extern unsigned char AmlCode[];
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {

Modified: trunk/src/mainboard/getac/p470/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/getac/p470/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/getac/p470/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/i82801gx.h"
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 #include "northbridge/intel/i945/udelay.c"
 #include "ec.c"
 

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -39,8 +39,8 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/sis/sis966/sis966.h"
-#include "southbridge/sis/sis966/sis966_early_smbus.c"
-#include "southbridge/sis/sis966/sis966_enable_rom.c"
+#include "southbridge/sis/sis966/early_smbus.c"
+#include "southbridge/sis/sis966/enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -52,7 +52,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/sis/sis966/sis966_early_ctrl.c"
+#include "southbridge/sis/sis966/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
@@ -86,7 +86,7 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
+#include "southbridge/sis/sis966/early_setup_ss.h"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <usbdebug.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
@@ -69,8 +69,8 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -64,7 +64,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -40,7 +40,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -53,7 +53,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -39,7 +39,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)

Modified: trunk/src/mainboard/ibase/mb899/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibase/mb899/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/ibase/mb899/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibase/mb899/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)

Modified: trunk/src/mainboard/iei/juki-511p/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/juki-511p/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "northbridge/amd/gx1/raminit.c"

Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -70,7 +70,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/iei/nova4899r/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/nova4899r/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)

Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/intel/d945gclf/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/d945gclf/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -66,7 +66,7 @@
 } __attribute__((packed)) acpi_oemb_t;
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 #if OLD_ACPI
 static void acpi_create_oemb(acpi_oemb_t *oemb)

Modified: trunk/src/mainboard/intel/d945gclf/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/d945gclf/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/acpi.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"

Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/jarrell/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,8 +27,8 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/mtrr/earlymtrr.c"

Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/truxton/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,8 +28,8 @@
 #include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/intel/xe7501devkit/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
+#include "southbridge/intel/i82801cx/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/debug.c"

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,7 +31,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 #include <lib.h>
 #include <spd.h>

Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -48,8 +48,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #if CONFIG_TTYS0_BASE == 0x2f8
@@ -75,7 +75,6 @@
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

Modified: trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -45,8 +45,8 @@
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/lanner/em8510/romstage.c
==============================================================================
--- trunk/src/mainboard/lanner/em8510/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lanner/em8510/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,8 +11,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
-#include "southbridge/amd/cs5535/cs5535_early_setup.c"
+#include "southbridge/amd/cs5535/early_smbus.c"
+#include "southbridge/amd/cs5535/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum. */

Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/literunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/literunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */

Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 #define ManualConf 1		/* No automatic strapped PLL config */

Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -50,7 +50,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
@@ -78,8 +78,8 @@
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -46,7 +46,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,7 +32,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include <spd.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <device/pci_ids.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -82,7 +82,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
 
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
@@ -91,7 +91,7 @@
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -72,8 +72,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -17,7 +17,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -28,7 +28,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -37,7 +37,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -77,8 +77,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.

Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix2d/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/pcengines/alix2d/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -38,7 +38,7 @@
 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.
  *

Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/rca/rm4100/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,12 +32,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 

Modified: trunk/src/mainboard/roda/rk886ex/acpi_tables.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/acpi_tables.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/roda/rk886ex/acpi_tables.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -91,7 +91,7 @@
 }
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));

Modified: trunk/src/mainboard/roda/rk886ex/mainboard_smi.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/mainboard_smi.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/roda/rk886ex/mainboard_smi.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -127,8 +127,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -68,8 +68,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -64,8 +64,8 @@
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -70,8 +70,8 @@
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }

Modified: trunk/src/mainboard/televideo/tc7020/romstage.c
==============================================================================
--- trunk/src/mainboard/televideo/tc7020/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/televideo/tc7020/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 

Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,12 +33,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 

Modified: trunk/src/mainboard/traverse/geos/romstage.c
==============================================================================
--- trunk/src/mainboard/traverse/geos/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/traverse/geos/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,8 +32,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2735/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "northbridge/intel/e7501/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"

Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2850/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2875/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2880/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -39,8 +39,8 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2892/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -38,7 +38,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -47,7 +47,7 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -37,7 +37,7 @@
 #include <spd.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -77,8 +77,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -73,8 +73,8 @@
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -11,7 +11,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/tyan/s4882/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -10,7 +10,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-cn/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,8 +32,8 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 #include <spd.h>
 
 static inline int spd_read_byte(unsigned device, unsigned address)

Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-m/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -14,8 +14,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8235/vt8235_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8235/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia-n/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,7 +33,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #include <spd.h>
 

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/epia/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -12,9 +12,9 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8231/vt8231_early_smbus.c"
-#include "southbridge/via/vt8231/vt8231_early_serial.c"
-#include "southbridge/via/vt8231/vt8231_enable_rom.c"
+#include "southbridge/via/vt8231/early_smbus.c"
+#include "southbridge/via/vt8231/early_serial.c"
+#include "southbridge/via/vt8231/enable_rom.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {

Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/via/pc2500e/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -32,7 +32,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include <spd.h>
 

Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/winent/pl6064/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -33,8 +33,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/mainboard/wyse/s50/romstage.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -31,8 +31,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {

Modified: trunk/src/southbridge/amd/amd8111/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8111/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8111/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,11 +1,11 @@
 driver-y += amd8111.c
-driver-y += amd8111_usb.c
-driver-y += amd8111_lpc.c
-driver-y += amd8111_ide.c
-driver-y += amd8111_acpi.c
-driver-y += amd8111_usb2.c
-driver-y += amd8111_ac97.c
-driver-y += amd8111_nic.c
-driver-y += amd8111_pci.c
-driver-y += amd8111_smbus.c
-ramstage-y += amd8111_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += acpi.c
+driver-y += usb2.c
+driver-y += ac97.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += smbus.c
+ramstage-y += reset.c

Copied: trunk/src/southbridge/amd/amd8111/ac97.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_ac97.c)
@@ -0,0 +1,52 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x2c,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ac97audio_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = amd8111_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97audio_driver __pci_driver = {
+	.ops    = &ac97audio_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x746D,
+};
+
+
+static struct device_operations ac97modem_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = amd8111_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97modem_driver __pci_driver = {
+	.ops    = &ac97modem_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x746E,
+};

Copied: trunk/src/southbridge/amd/amd8111/acpi.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/acpi.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_acpi.c)
@@ -0,0 +1,220 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include "amd8111.h"
+#include "amd8111_smbus.h"
+
+#define PREVIOUS_POWER_STATE 0x43
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define SLOW_CPU_OFF 0
+#define SLOW_CPU__ON 1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+
+static int lsmbus_recv_byte(device_t dev)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_recv_byte(res->base, device);
+}
+
+static int lsmbus_send_byte(device_t dev, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_send_byte(res->base, device, val);
+}
+
+
+static int lsmbus_read_byte(device_t dev, uint8_t address)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_read_byte(res->base, device, address);
+}
+
+static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
+{
+	unsigned device;
+	struct resource *res;
+
+	device = dev->path.i2c.device;
+	res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
+
+	return do_smbus_write_byte(res->base, device, address, val);
+}
+
+#if CONFIG_GENERATE_ACPI_TABLES == 1
+unsigned pm_base;
+#endif
+
+static void acpi_init(struct device *dev)
+{
+	uint8_t byte;
+	uint16_t pm10_bar;
+	uint32_t dword;
+	int on;
+
+#if 0
+	uint16_t word;
+	printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
+	byte = pci_read_config8(dev, 0x49);
+	pci_write_config8(dev, 0x49, byte | (1<<2));
+
+
+	byte = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
+
+	/* added from sourceforge */
+	byte = pci_read_config8(dev, 0x48);
+	pci_write_config8(dev, 0x48, byte | (1<<3));
+
+	printk(BIOS_DEBUG, "done.\n");
+
+
+	printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
+	word = pci_read_config16(dev, 0x46);
+	pci_write_config16(dev, 0x46, word | (1<<9));
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+	/* To enable the register 0xcf9 in the IO space
+	 * bit [D5] is set in the amd8111 configuration register.
+	 * The config. reg. is devBx41.  Register 0xcf9 allows
+	 * hard reset capability to the system.  For the ACPI
+	 * reset.reg values in fadt.c to work this register
+	 * must be enabled.
+	 */
+	byte = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
+
+	/* power on after power fail */
+	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	get_option(&on, "power_on_after_fail");
+	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
+	byte &= ~0x40;
+	if (!on) {
+		byte |= 0x40;
+	}
+	pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
+
+	/* switch serial irq logic from quiet mode to continuous
+	 * mode for Winbond W83627HF Rev. 17
+	 */
+	byte = pci_read_config8(dev, 0x4a);
+	pci_write_config8(dev, 0x4a, byte | (1<<6));
+
+	/* Throttle the CPU speed down for testing */
+	on = SLOW_CPU_OFF;
+	get_option(&on, "slow_cpu");
+	if(on) {
+		pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
+		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
+		dword = inl(pm10_bar + 0x10);
+		on = 8-on;
+		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
+				(on*12)+(on>>1),(on&1)*5);
+	}
+
+#if CONFIG_GENERATE_ACPI_TABLES == 1
+	pm_base = pci_read_config16(dev, 0x58) & 0xff00;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
+#endif
+
+}
+
+static void acpi_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Handle the generic bars */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI/SMBUS bar */
+	resource = new_resource(dev, 0x58);
+	resource->base  = 0;
+	resource->size  = 256;
+	resource->align = log2(256);
+	resource->gran  = log2(256);
+	resource->limit = 65536;
+	resource->flags = IORESOURCE_IO;
+	resource->index = 0x58;
+}
+
+static void acpi_enable_resources(device_t dev)
+{
+	uint8_t byte;
+	/* Enable the generic pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI/SMBUS Bar */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1 << 7);
+	pci_write_config8(dev, 0x41, byte);
+
+	/* Set the class code */
+	pci_write_config32(dev, 0x60, 0x06800000);
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x7c,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+	.recv_byte  = lsmbus_recv_byte,
+	.send_byte  = lsmbus_send_byte,
+	.read_byte  = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
+};
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations acpi_ops  = {
+	.read_resources   = acpi_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = acpi_enable_resources,
+	.init             = acpi_init,
+	.scan_bus         = scan_static_bus,
+	/*  We don't need amd8111_enable, chip ops takes care of it.
+	 *  It could be useful if these devices were not
+	 *  enabled by default.
+	 */
+//	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+	.ops_smbus_bus    = &lops_smbus_bus,
+};
+
+static const struct pci_driver acpi_driver __pci_driver = {
+	.ops    = &acpi_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_ACPI,
+};
+

Modified: trunk/src/southbridge/amd/amd8111/bootblock.c
==============================================================================
--- trunk/src/southbridge/amd/amd8111/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8111/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "southbridge/amd/amd8111/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/amd/amd8111/early_ctrl.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/early_ctrl.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c)
@@ -0,0 +1,83 @@
+#include "amd8111.h"
+#include <reset.h>
+
+/* by yhlu 2005.10 */
+static unsigned get_sbdn(unsigned bus)
+{
+        device_t dev;
+
+        /* Find the device.
+         * There can only be one 8111 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
+{
+	device_t dev;
+	uint8_t byte;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
+	/* enable cf9 */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1<<6) | (1<<5);
+	pci_write_config8(dev, 0x41, byte);
+}
+
+static void enable_cf9(void)
+{
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	enable_cf9_x(sbbusn, sbdn);
+}
+
+void hard_reset(void)
+{
+        set_bios_reset();
+        /* reset */
+        enable_cf9();
+        outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+}
+
+void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+        device_t dev;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
+
+        pci_write_config8(dev, 0x74, 4);
+
+        /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+        pci_write_config32(dev, 0x70, 2<<12);
+
+}
+
+static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
+{
+        device_t dev;
+
+	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
+
+        /* Reset */
+        set_bios_reset();
+        pci_write_config8(dev, 0x47, 1);
+
+}
+
+void soft_reset(void)
+{
+
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	return soft_reset_x(sbbusn, sbdn);
+
+}

Copied: trunk/src/southbridge/amd/amd8111/early_smbus.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c)
@@ -0,0 +1,48 @@
+#include "amd8111_smbus.h"
+
+#define SMBUS_IO_BASE 0x0f00
+
+static void enable_smbus(void)
+{
+	device_t dev;
+	uint8_t enable;
+
+	dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\n");
+	}
+
+	pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
+	enable = pci_read_config8(dev, 0x41);
+	pci_write_config8(dev, 0x41, enable | (1 << 7));
+
+	/* check that we can see the smbus controller I/O. */
+	if (inw(SMBUS_IO_BASE)==0xFF){
+		die("SMBUS controller I/O not found\n");
+	}
+
+	/* clear any lingering errors, so the transaction will run */
+	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
+	print_spew("SMBus controller enabled\n");
+}
+
+static inline int smbus_recv_byte(unsigned device)
+{
+	return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+}
+
+static inline int smbus_send_byte(unsigned device, unsigned char val)
+{
+	return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+}
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+}
+

Copied: trunk/src/southbridge/amd/amd8111/enable_rom.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c)
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
+static void amd8111_enable_rom(void)
+{
+	u8 byte;
+	device_t dev;
+
+	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
+					  PCI_DEVICE_ID_AMD_8111_ISA), 0);
+
+	/* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
+
+	/* Set the 5MB enable bits. */
+	byte = pci_io_read_config8(dev, 0x43);
+	byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
+	byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
+	pci_io_write_config8(dev, 0x43, byte);
+}

Copied: trunk/src/southbridge/amd/amd8111/ide.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_ide.c)
@@ -0,0 +1,66 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	uint16_t word;
+	uint8_t byte;
+	conf = dev->chip_info;
+
+	word = pci_read_config16(dev, 0x40);
+	/* Ensure prefetch is disabled */
+	word &= ~((1 << 15) | (1 << 13));
+	if (conf->ide1_enable) {
+		/* Enable secondary ide interface */
+		word |= (1<<0);
+		printk(BIOS_DEBUG, "IDE1 ");
+	}
+	if (conf->ide0_enable) {
+		/* Enable primary ide interface */
+		word |= (1<<1);
+		printk(BIOS_DEBUG, "IDE0 ");
+	}
+
+	word |= (1<<12);
+	word |= (1<<14);
+
+	pci_write_config16(dev, 0x40, word);
+
+
+        byte = 0x20 ; // Latency: 64-->32
+        pci_write_config8(dev, 0xd, byte);
+
+	word = 0x0f;
+	pci_write_config16(dev, 0x42, word);
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_IDE,
+};
+

Copied: trunk/src/southbridge/amd/amd8111/lpc.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_lpc.c)
@@ -0,0 +1,133 @@
+/*
+ * (C) 2003 Linux Networx, SuSE Linux AG
+ *  2006.1 yhlu add dest apicid for IRQ0
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
+#include <stdlib.h>
+#include "amd8111.h"
+
+#define NMI_OFF 0
+
+static void enable_hpet(struct device *dev)
+{
+	unsigned long hpet_address;
+
+	pci_write_config32(dev,0xa0, 0xfed00001);
+	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
+
+}
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	int nmi_option;
+
+	/* IO APIC initialization */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1;
+	pci_write_config8(dev, 0x4B, byte);
+	/* Don't rename IO APIC */
+	setup_ioapic(IO_APIC_ADDR, 0);
+
+	/* posted memory write enable */
+	byte = pci_read_config8(dev, 0x46);
+	pci_write_config8(dev, 0x46, byte | (1<<0));
+
+	/* Enable 5Mib Rom window */
+	byte = pci_read_config8(dev, 0x43);
+	byte |= 0xc0;
+	pci_write_config8(dev, 0x43, byte);
+
+	/* Enable Port 92 fast reset */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= (1 << 5);
+	pci_write_config8(dev, 0x41, byte);
+
+	/* Enable Error reporting */
+	/* Set up sync flood detected */
+	byte = pci_read_config8(dev, 0x47);
+	byte |= (1 << 1);
+	pci_write_config8(dev, 0x47, byte);
+
+	/* Set up NMI on errors */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 1); /* clear PW2LPC error */
+	byte |= (1 << 6); /* clear LPCERR */
+	pci_write_config8(dev, 0x40, byte);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte |= (1 << 7); /* set NMI */
+		pci_write_config8(dev, 0x40, byte);
+	}
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers */
+	enable_hpet(dev);
+}
+
+static void amd8111_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = amd8111_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_ISA,
+};

Copied: trunk/src/southbridge/amd/amd8111/nic.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_nic.c)
@@ -0,0 +1,90 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "amd8111.h"
+
+
+#define CMD3		0x54
+
+typedef enum {
+	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
+	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
+	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
+	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+	/* VAL3 */
+	ASF_INIT_DONE_ALIAS	= (1 << 29),
+	/* VAL2 */
+	JUMBO			= (1 << 21),
+	VSIZE			= (1 << 20),
+	VLONLY			= (1 << 19),
+	VL_TAG_DEL		= (1 << 18),
+	/* VAL1 */
+	EN_PMGR			= (1 << 14),
+	INTLEVEL		= (1 << 13),
+	FORCE_FULL_DUPLEX	= (1 << 12),
+	FORCE_LINK_STATUS	= (1 << 11),
+	APEP			= (1 << 10),
+	MPPLBA			= (1 << 9),
+	/* VAL0 */
+	RESET_PHY_PULSE		= (1 << 2),
+	RESET_PHY		= (1 << 1),
+	PHY_RST_POL		= (1 << 0),
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+	struct southbridge_amd_amd8111_config *conf;
+	struct resource *resource;
+	unsigned long mmio;
+
+	conf = dev->chip_info;
+	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+	mmio = resource->base;
+
+	/* Hard Reset PHY */
+	printk(BIOS_DEBUG, "Reseting PHY... ");
+	if (conf->phy_lowreset) {
+		write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
+	} else {
+		write32((mmio + CMD3), VAL0 | RESET_PHY);
+	}
+	mdelay(15);
+	write32((mmio + CMD3), RESET_PHY);
+	printk(BIOS_DEBUG, "Done\n");
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0xc8,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = nic_init,
+	.scan_bus         = 0,
+	.enable		  = amd8111_enable,
+	.ops_pci	  = &lops_pci,
+};
+
+static const struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_NIC,
+};

Copied: trunk/src/southbridge/amd/amd8111/pci.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_pci.c)
@@ -0,0 +1,68 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+static void pci_init(struct device *dev)
+{
+
+	/* Enable pci error detecting */
+	uint32_t dword;
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (7<<28); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/* System,Parity,timer,and abort error enable */
+	dword = pci_read_config32(dev, 0x3c);
+	dword |= (1<<16); /* Parity */
+	dword |= (1<<17); /* System */
+	dword |= (1<<21); /* Master abort */
+//	dword &= ~(1<<21); /* Master abort */
+//	dword |= (1<<27); /* Discard timer */
+	dword &= ~(1<<27); /* Discard timer */
+	dword |= (1<<26); /* DTSTAT error clear  */
+	pci_write_config32(dev, 0x3c, dword);
+
+	/* CRC flood enable */
+	dword = pci_read_config32(dev, 0xc4);
+	dword |= (1<<1); /* CRC Flood enable */
+	dword |= (1<<8); /* Clear any CRC errors */
+	dword |= (1<<4); /* Clear any LKFAIL errors */
+	pci_write_config32(dev, 0xc4, dword);
+
+	/* Clear possible errors */
+	dword = pci_read_config32(dev, 0x1c);
+	dword |= (1<<27); /* STA */
+	dword |= (1<<28); /* RTA */
+	dword |= (1<<29); /* RMA */
+	dword |= (1<<30); /* RSE */
+	dword |= (1<<31); /* DPE */
+	dword |= (1<<24); /* MDPE */
+	pci_write_config32(dev, 0x1c, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	/* PCI Subordinate bus reset is not implemented */
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_PCI,
+};
+

Copied: trunk/src/southbridge/amd/amd8111/reset.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_reset.c)
@@ -0,0 +1,76 @@
+#include <arch/io.h>
+#include <reset.h>
+#include <device/pci_ids.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFFF) << 20) | \
+	(((DEV) & 0x1F) << 15) | \
+	(((FN)  & 0x7) << 12))
+
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+typedef unsigned device_t;
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+	unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#define PCI_DEV_INVALID (0xffffffffU)
+static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+{
+	device_t dev, last;
+	dev = PCI_DEV(bus, 0, 0);
+	last = PCI_DEV(bus, 31, 7);
+	for(; dev <= last; dev += PCI_DEV(0,0,1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id) {
+			return dev;
+		}
+	}
+	return PCI_DEV_INVALID;
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+
+void hard_reset(void)
+{
+	device_t dev;
+	unsigned bus;
+	unsigned node = 0;
+	unsigned link = get_sblk();
+
+	/* Find the device.
+	 * There can only be one 8111 on a hypertransport chain/bus.
+	 */
+	bus = node_link_to_bus(node, link);
+	dev = pci_locate_device_on_bus(
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
+		bus);
+
+	/* Reset */
+	set_bios_reset();
+	pci_write_config8(dev, 0x47, 1);
+}

Copied: trunk/src/southbridge/amd/amd8111/smbus.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_smbus.c)
@@ -0,0 +1,41 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <arch/io.h>
+#include "amd8111.h"
+
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x44,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+	/* I haven't seen the 2.0 SMBUS controller used yet. */
+};
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+static struct device_operations smbus_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = scan_static_bus,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+	.ops_smbus_bus    = &lops_smbus_bus,
+};
+
+static const struct pci_driver smbus_driver __pci_driver = {
+	.ops = &smbus_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_SMB,
+};

Copied: trunk/src/southbridge/amd/amd8111/usb.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb.c)
@@ -0,0 +1,37 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "amd8111.h"
+
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations usb_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = scan_static_bus,
+//	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb_driver __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_USB,
+};

Copied: trunk/src/southbridge/amd/amd8111/usb2.c (from r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8111/usb2.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8111/amd8111_usb2.c)
@@ -0,0 +1,45 @@
+//2003 Copywright Tyan
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "amd8111.h"
+
+#if 0
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
+
+#endif
+
+static void amd8111_usb2_enable(device_t dev)
+{
+	// Due to buggy USB2 we force it to disable.
+	dev->enabled = 0;
+	amd8111_enable(dev);
+	printk(BIOS_DEBUG, "USB2 disabled.\n");
+}
+
+static struct device_operations usb2_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.enable           = amd8111_usb2_enable,
+	// .ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &usb2_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_8111_USB2,
+};

Copied: trunk/src/southbridge/amd/amd8131-disable/bridge.c (from r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8131-disable/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8131-disable/amd8131_bridge.c)
@@ -0,0 +1,116 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+
+static void amd8131_bus_read_resources(device_t dev)
+{
+	return;
+}
+
+static void amd8131_bus_set_resources(device_t dev)
+{
+#if 0
+	pci_bus_read_resources(dev);
+#endif
+	return;
+}
+
+static void amd8131_bus_enable_resources(device_t dev)
+{
+#if 0
+	pci_dev_set_resources(dev);
+#endif
+	return;
+}
+
+static void amd8131_bus_init(device_t dev)
+{
+#if 0
+	pcix_init(dev);
+#endif
+	return;
+}
+
+static unsigned int amd8131_scan_bus(device_t bus, unsigned int max)
+{
+#if 0
+	max = pcix_scan_bridge(bus, max);
+#endif
+	return max;
+}
+
+static void amd8131_enable(device_t dev)
+{
+	uint32_t buses;
+	uint16_t cr;
+
+	/* Clear all status bits and turn off memory, I/O and master enables. */
+	pci_write_config16(dev, PCI_COMMAND, 0x0000);
+	pci_write_config16(dev, PCI_STATUS, 0xffff);
+
+	/*
+	 * Read the existing primary/secondary/subordinate bus
+	 * number configuration.
+	 */
+	buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+
+	/* Configure the bus numbers for this bridge: the configuration
+	 * transactions will not be propagated by the bridge if it is not
+	 * correctly configured.
+	 */
+	buses &= 0xff000000;
+	buses |= (((unsigned int) (dev->bus->secondary) << 0) |
+		((unsigned int) (dev->bus->secondary) << 8) |
+		((unsigned int) (dev->bus->secondary) << 16));
+	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
+}
+
+static struct device_operations pcix_ops  = {
+        .read_resources   = amd8131_bus_read_resources,
+        .set_resources    = amd8131_bus_set_resources,
+	.enable_resources = amd8131_bus_enable_resources,
+        .init             = amd8131_bus_init,
+	.scan_bus         = 0,
+	.enable           = amd8131_enable,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7450,
+};
+
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = 0,
+	.scan_bus = 0,
+	.enable   = ioapic_enable,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7451,
+
+};

Modified: trunk/src/southbridge/amd/amd8131/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8131/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8131/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8131_bridge.c
+driver-y += bridge.c

Copied: trunk/src/southbridge/amd/amd8131/bridge.c (from r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8131/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8131/amd8131_bridge.c)
@@ -0,0 +1,432 @@
+/*
+ * (C) 2003-2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <device/pcix.h>
+
+#define NMI_OFF 0
+
+#define NPUML 0xD9	/* Non prefetchable upper memory limit */
+#define NPUMB 0xD8	/* Non prefetchable upper memory base */
+
+static void amd8131_walk_children(struct bus *bus,
+	void (*visit)(device_t dev, void *ptr), void *ptr)
+{
+	device_t child;
+	for(child = bus->children; child; child = child->sibling)
+	{
+		if (child->path.type != DEVICE_PATH_PCI) {
+			continue;
+		}
+		if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+			amd8131_walk_children(child->link_list, visit, ptr);
+		}
+		visit(child, ptr);
+	}
+}
+
+struct amd8131_bus_info {
+	unsigned sstatus;
+	unsigned rev;
+	int errata_56;
+	int master_devices;
+	int max_func;
+};
+
+static void amd8131_count_dev(device_t dev, void *ptr)
+{
+	struct amd8131_bus_info *info = ptr;
+	/* Don't count pci bridges */
+	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+		info->master_devices++;
+	}
+	if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
+		info->max_func = PCI_FUNC(dev->path.pci.devfn);
+	}
+}
+
+
+static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
+{
+	struct amd8131_bus_info *info = ptr;
+	unsigned cap;
+	unsigned status, cmd, orig_cmd;
+	unsigned max_read, max_tran;
+	int sib_funcs, sibs;
+	device_t sib;
+
+	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
+		return;
+	}
+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+	if (!cap) {
+		return;
+	}
+	/* How many siblings does this device have? */
+	sibs = info->master_devices - 1;
+	/* Count how many sibling functions this device has */
+	sib_funcs = 0;
+	for(sib = dev->bus->children; sib; sib = sib->sibling) {
+		if (sib == dev) {
+			continue;
+		}
+		if (PCI_SLOT(sib->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) {
+			continue;
+		}
+		sib_funcs++;
+	}
+
+
+	printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev));
+	status = pci_read_config32(dev, cap + PCI_X_STATUS);
+	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
+
+	max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
+	max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
+
+	/* Errata #49 don't allow 4K transactions */
+	if (max_read >= 2) {
+		max_read = 2;
+	}
+
+	/* Errata #37 Limit the number of split transactions to avoid starvation */
+	if (sibs >= 2) {
+		/* At most 2 outstanding split transactions when we have
+		 * 3 or more bus master devices on the bus.
+		 */
+		if (max_tran > 1) {
+			max_tran = 1;
+		}
+	}
+	else if (sibs == 1) {
+		/* At most 4 outstanding split transactions when we have
+		 * 2 bus master devices on the bus.
+		 */
+		if (max_tran > 3) {
+			max_tran = 3;
+		}
+	}
+	else {
+		/* At most 8 outstanding split transactions when we have
+		 * only one bus master device on the bus.
+		 */
+		if (max_tran > 4) {
+			max_tran = 4;
+		}
+	}
+	/* Errata #56 additional limits when the bus runs at 133Mhz */
+	if (info->errata_56 &&
+		(PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))
+	{
+		unsigned limit_read;
+		/* Look at the number of siblings and compute the
+		 * largest legal read size.
+		 */
+		if (sib_funcs == 0) {
+			/* 2k reads */
+			limit_read = 2;
+		}
+		else if (sib_funcs <= 1) {
+			/* 1k reads */
+			limit_read = 1;
+		}
+		else {
+			/* 512 byte reads */
+			limit_read = 0;
+		}
+		if (max_read > limit_read) {
+			max_read = limit_read;
+		}
+		/* Look at the read size and the nubmer of siblings
+		 * and compute how many outstanding transactions I can have.
+		 */
+		if (max_read == 2) {
+			/* 2K reads */
+			if (max_tran > 0) {
+				/* Only 1 outstanding transaction allowed */
+				max_tran = 0;
+			}
+		}
+		else if (max_read == 1) {
+			/* 1K reads */
+			if (max_tran > (1 - sib_funcs)) {
+				/* At most 2 outstanding transactions */
+				max_tran = 1 - sib_funcs;
+			}
+		}
+		else {
+			/* 512 byte reads */
+			max_read = 0;
+			if (max_tran > (2 - sib_funcs)) {
+				/* At most 3 outstanding transactions */
+				max_tran = 2 - sib_funcs;
+			}
+		}
+	}
+#if 0
+	printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
+		dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs);
+#endif
+	if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
+		cmd &= ~PCI_X_CMD_MAX_READ;
+		cmd |= max_read << 2;
+		}
+	if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
+		cmd &= ~PCI_X_CMD_MAX_SPLIT;
+		cmd |= max_tran << 4;
+	}
+
+	/* Don't attempt to handle PCI-X errors */
+	cmd &= ~PCI_X_CMD_DPERR_E;
+	/* The 8131 does not work properly with relax ordering enabled.
+	 * Errata #58
+	 */
+	cmd &= ~PCI_X_CMD_ERO;
+	if (orig_cmd != cmd) {
+		pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+	}
+}
+static unsigned int amd8131_scan_bus(struct bus *bus,
+	unsigned min_devfn, unsigned max_devfn, unsigned int max)
+{
+	struct amd8131_bus_info info;
+	struct bus *pbus;
+	unsigned pos;
+
+
+	/* Find the children on the bus */
+	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+
+	/* Find the revision of the 8131 */
+	info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
+
+	/* See which errata apply */
+	info.errata_56 = info.rev <= 0x12;
+
+	/* Find the pcix capability and get the secondary bus status */
+	pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
+	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
+
+	/* Print the PCI-X bus speed */
+	printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
+
+
+	/* Examine the bus and find out how loaded it is */
+	info.max_func = 0;
+	info.master_devices  = 0;
+	amd8131_walk_children(bus, amd8131_count_dev, &info);
+
+	/* Disable the bus if there are no devices on it or
+	 * we are running at 133Mhz and have a 4 function device.
+	 * see errata #56
+	 */
+	if (!bus->children ||
+		(info.errata_56 &&
+			(info.max_func >= 3) &&
+			(PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)))
+	{
+		unsigned pcix_misc;
+		/* Disable all of my children */
+		disable_children(bus);
+
+		/* Remember the device is disabled */
+		bus->dev->enabled = 0;
+
+		/* Disable the PCI-X clocks */
+		pcix_misc = pci_read_config32(bus->dev, 0x40);
+		pcix_misc &= ~(0x1f << 16);
+		pci_write_config32(bus->dev, 0x40, pcix_misc);
+
+		return max;
+	}
+
+	/* If we are in conventional PCI mode nothing more is necessary.
+	 */
+	if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
+		return max;
+	}
+
+
+	/* Tune the devices on the bus */
+	amd8131_walk_children(bus, amd8131_pcix_tune_dev, &info);
+
+	/* Don't allow the 8131 or any of it's parent busses to
+	 * implement relaxed ordering.  Errata #58
+	 */
+	for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
+		printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
+			bus_path(pbus));
+		pbus->disable_relaxed_ordering = 1;
+	}
+	return max;
+}
+
+static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, amd8131_scan_bus);
+}
+
+
+static void amd8131_pcix_init(device_t dev)
+{
+	uint32_t dword;
+	uint16_t word;
+	uint8_t byte;
+	int nmi_option;
+
+	/* Enable memory write and invalidate ??? */
+	byte = pci_read_config8(dev, 0x04);
+        byte |= 0x10;
+        pci_write_config8(dev, 0x04, byte);
+
+	/* Set drive strength */
+	word = pci_read_config16(dev, 0xe0);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe0, word);
+	word = pci_read_config16(dev, 0xe4);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe4, word);
+
+	/* Set impedance */
+	word = pci_read_config16(dev, 0xe8);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe8, word);
+
+	/* Set discard unrequested prefetch data */
+	/* Errata #51 */
+	word = pci_read_config16(dev, 0x4c);
+        word |= 1;
+        pci_write_config16(dev, 0x4c, word);
+
+	/* Set split transaction limits */
+	word = pci_read_config16(dev, 0xa8);
+        pci_write_config16(dev, 0xaa, word);
+	word = pci_read_config16(dev, 0xac);
+        pci_write_config16(dev, 0xae, word);
+
+	/* Set up error reporting, enable all */
+	/* system error enable */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= (1<<8);
+        pci_write_config32(dev, 0x04, dword);
+
+	/* system and error parity enable */
+	dword = pci_read_config32(dev, 0x3c);
+        dword |= (3<<16);
+        pci_write_config32(dev, 0x3c, dword);
+
+	/* NMI enable */
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if(nmi_option) {
+		dword = pci_read_config32(dev, 0x44);
+        	dword |= (1<<0);
+        	pci_write_config32(dev, 0x44, dword);
+	}
+
+	/* Set up CRC flood enable */
+	dword = pci_read_config32(dev, 0xc0);
+	if(dword) {  /* do device A only */
+		dword = pci_read_config32(dev, 0xc4);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc4, dword);
+		dword = pci_read_config32(dev, 0xc8);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc8, dword);
+	}
+	return;
+}
+
+#define BRIDGE_40_BIT_SUPPORT 0
+#if BRIDGE_40_BIT_SUPPORT
+static void bridge_read_resources(struct device *dev)
+{
+	struct resource *res;
+	pci_bus_read_resources(dev);
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		res->limit = 0xffffffffffULL;
+	}
+}
+
+static void bridge_set_resources(struct device *dev)
+{
+	struct resource *res;
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		resource_t base, end;
+		/* set the memory range */
+		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		res->flags |= IORESOURCE_STORED;
+		base = res->base;
+		end  = resource_end(res);
+		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
+		pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
+		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
+		pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
+
+		report_resource_stored(dev, res, "");
+	}
+	pci_dev_set_resources(dev);
+}
+#endif /* BRIDGE_40_BIT_SUPPORT */
+
+static struct device_operations pcix_ops  = {
+#if BRIDGE_40_BIT_SUPPORT
+        .read_resources   = bridge_read_resources,
+        .set_resources    = bridge_set_resources,
+#else
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_bus_enable_resources,
+        .init             = amd8131_pcix_init,
+        .scan_bus         = amd8131_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7450,
+};
+
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+	.set_subsystem    = pci_dev_set_subsystem,
+};
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = ioapic_enable,
+	.ops_pci          = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7451,
+
+};

Modified: trunk/src/southbridge/amd/amd8132/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8132/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8132/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8132_bridge.c
+driver-y += bridge.c

Copied: trunk/src/southbridge/amd/amd8132/bridge.c (from r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8132/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8132/amd8132_bridge.c)
@@ -0,0 +1,433 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005,2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <device/pcix.h>
+
+#define NMI_OFF 0
+
+#define NPUML 0xD9	/* Non prefetchable upper memory limit */
+#define NPUMB 0xD8	/* Non prefetchable upper memory base */
+
+static void amd8132_walk_children(struct bus *bus,
+	void (*visit)(device_t dev, void *ptr), void *ptr)
+{
+	device_t child;
+	for(child = bus->children; child; child = child->sibling)
+	{
+		if (child->path.type != DEVICE_PATH_PCI) {
+			continue;
+		}
+		if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+			amd8132_walk_children(child->link_list, visit, ptr);
+		}
+		visit(child, ptr);
+	}
+}
+
+struct amd8132_bus_info {
+	unsigned sstatus;
+	unsigned rev;
+	int master_devices;
+	int max_func;
+};
+
+static void amd8132_count_dev(device_t dev, void *ptr)
+{
+	struct amd8132_bus_info *info = ptr;
+	/* Don't count pci bridges */
+	if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
+		info->master_devices++;
+	}
+	if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
+		info->max_func = PCI_FUNC(dev->path.pci.devfn);
+	}
+}
+
+
+static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
+{
+	struct amd8132_bus_info *info = ptr;
+	unsigned cap;
+	unsigned status, cmd, orig_cmd;
+	unsigned max_read, max_tran;
+	int  sibs;
+
+	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
+		return;
+	}
+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+	if (!cap) {
+		return;
+	}
+	/* How many siblings does this device have? */
+	sibs = info->master_devices - 1;
+
+	printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev));
+	status = pci_read_config32(dev, cap + PCI_X_STATUS);
+	orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
+
+	max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
+	max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
+
+	if (info->rev == 0x01) { // only a1 need it
+		/* Errata #53 Limit the number of split transactions to avoid starvation */
+		if (sibs >= 2) {
+			/* At most 2 outstanding split transactions when we have
+			* 3 or more bus master devices on the bus.
+			*/
+			if (max_tran > 1) {
+				max_tran = 1;
+			}
+		}
+		else if (sibs == 1) {
+			/* At most 4 outstanding split transactions when we have
+			* 2 bus master devices on the bus.
+			*/
+			if (max_tran > 3) {
+				max_tran = 3;
+			}
+		}
+		else {
+			/* At most 8 outstanding split transactions when we have
+			* only one bus master device on the bus.
+			*/
+			if (max_tran > 4) {
+				max_tran = 4;
+			}
+		}
+	}
+
+	if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
+		cmd &= ~PCI_X_CMD_MAX_READ;
+		cmd |= max_read << 2;
+		}
+	if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
+		cmd &= ~PCI_X_CMD_MAX_SPLIT;
+		cmd |= max_tran << 4;
+	}
+
+        /* Don't attempt to handle PCI-X errors */
+        cmd &= ~PCI_X_CMD_DPERR_E;
+        if (orig_cmd != cmd) {
+                pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+        }
+
+
+}
+static unsigned int amd8132_scan_bus(struct bus *bus,
+	unsigned min_devfn, unsigned max_devfn, unsigned int max)
+{
+	struct amd8132_bus_info info;
+	unsigned pos;
+
+
+	/* Find the children on the bus */
+	max = pci_scan_bus(bus, min_devfn, max_devfn, max);
+
+	/* Find the revision of the 8132 */
+	info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
+
+	/* Find the pcix capability and get the secondary bus status */
+	pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
+	info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
+
+	/* Print the PCI-X bus speed */
+	printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
+
+
+	/* Examine the bus and find out how loaded it is */
+	info.max_func = 0;
+	info.master_devices  = 0;
+	amd8132_walk_children(bus, amd8132_count_dev, &info);
+
+#if 0
+	/* Disable the bus if there are no devices on it
+	 */
+	if (!bus->children)
+	{
+		unsigned pcix_misc;
+		/* Disable all of my children */
+		disable_children(bus);
+
+		/* Remember the device is disabled */
+		bus->dev->enabled = 0;
+
+		/* Disable the PCI-X clocks */
+		pcix_misc = pci_read_config32(bus->dev, 0x40);
+		pcix_misc &= ~(0x1f << 16);
+		pci_write_config32(bus->dev, 0x40, pcix_misc);
+
+		return max;
+	}
+#endif
+
+	/* If we are in conventional PCI mode nothing more is necessary.
+	 */
+	if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
+		return max;
+	}
+
+	/* Tune the devices on the bus */
+	amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
+
+	return max;
+}
+
+static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)
+{
+	return do_pci_scan_bridge(dev, max, amd8132_scan_bus);
+}
+
+
+static void amd8132_pcix_init(device_t dev)
+{
+	uint32_t dword;
+	uint8_t byte;
+	unsigned chip_rev;
+
+	/* Find the revision of the 8132 */
+        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+
+	/* Enable memory write and invalidate ??? */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= 0x10;
+	dword &= ~(1<<6); // PERSP Parity Error Response
+        pci_write_config32(dev, 0x04, dword);
+
+	if (chip_rev == 0x01) {
+		/* Errata #37 */
+		byte = pci_read_config8(dev, 0x0c);
+		if(byte == 0x08 )
+			pci_write_config8(dev, 0x0c, 0x10);
+
+#if 0
+		/* Errata #59*/
+		dword = pci_read_config32(dev, 0x40);
+		dword &= ~(1<<31);
+		pci_write_config32(dev, 0x40, dword);
+#endif
+
+	}
+
+	/* Set up error reporting, enable all */
+	/* system error enable */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= (1<<8);
+        pci_write_config32(dev, 0x04, dword);
+
+	/* system and error parity enable */
+	dword = pci_read_config32(dev, 0x3c);
+        dword |= (3<<16);
+        pci_write_config32(dev, 0x3c, dword);
+
+        dword = pci_read_config32(dev, 0x40);
+//        dword &= ~(1<<31); /* WriteChainEnable */
+	dword |= (1<<31);
+	dword |= (1<<7);// must set to 1
+	dword |= (3<<21); //PCIErrorSerrDisable
+        pci_write_config32(dev, 0x40, dword);
+
+        /* EXTARB = 1, COMPAT = 0 */
+        dword = pci_read_config32(dev, 0x48);
+        dword |= (1<<3);
+	dword &= ~(1<<0);
+	dword |= (1<<15); //CLEARPCILOG_L
+	dword |= (1<<19); //PERR FATAL Enable
+	dword |= (1<<22); // SERR FATAL Enable
+	dword |= (1<<23); // LPMARBENABLE
+	dword |= (0x61<<24); //LPMARBCOUNT
+        pci_write_config32(dev, 0x48, dword);
+
+        dword = pci_read_config32(dev, 0x4c);
+        dword |= (1<<6); //intial prefetch for memory read line request
+	dword |= (1<<9); //continuous prefetch Enable for memory read line request
+        pci_write_config32(dev, 0x4c, dword);
+
+
+       /* Disable Single-Bit-Error Correction [30] = 0 */
+        dword = pci_read_config32(dev, 0x70);
+        dword &= ~(1<<30);
+        pci_write_config32(dev, 0x70, dword);
+
+	//link
+        dword = pci_read_config32(dev, 0xd4);
+        dword |= (0x5c<<16);
+        pci_write_config32(dev, 0xd4, dword);
+
+        /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
+        dword = pci_read_config32(dev, 0xdc);
+	dword |= (1<<1) |  (1<<4); // stream disable 1 to 0 , DBLINSRATE
+        dword |= (1<<18)|(1<<26);
+        dword &= ~((3<<16)|(3<<24));
+        pci_write_config32(dev, 0xdc, dword);
+
+	/* Set up CRC flood enable */
+	dword = pci_read_config32(dev, 0xc0);
+	if(dword) {  /* do device A only */
+#if 0
+		dword = pci_read_config32(dev, 0xc4);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc4, dword);
+		dword = pci_read_config32(dev, 0xc8);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc8, dword);
+#endif
+
+	        if (chip_rev == 0x11) {
+        	        /* [18] Clock Gate Enable = 1 */
+                	dword = pci_read_config32(dev, 0xf0);
+	                dword |= 0x00040008;
+        	        pci_write_config32(dev, 0xf0, dword);
+	        }
+
+	}
+	return;
+}
+
+#define BRIDGE_40_BIT_SUPPORT 0
+#if BRIDGE_40_BIT_SUPPORT
+static void bridge_read_resources(struct device *dev)
+{
+	struct resource *res;
+	pci_bus_read_resources(dev);
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		res->limit = 0xffffffffffULL;
+	}
+}
+
+static void bridge_set_resources(struct device *dev)
+{
+	struct resource *res;
+	res = find_resource(dev, PCI_MEMORY_BASE);
+	if (res) {
+		resource_t base, end;
+		/* set the memory range */
+		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		res->flags |= IORESOURCE_STORED;
+		base = res->base;
+		end  = resource_end(res);
+		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
+		pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
+		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
+		pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
+
+		report_resource_stored(dev, res, "");
+	}
+	pci_dev_set_resources(dev);
+}
+#endif /* BRIDGE_40_BIT_SUPPORT */
+
+static struct device_operations pcix_ops  = {
+#if BRIDGE_40_BIT_SUPPORT
+        .read_resources   = bridge_read_resources,
+        .set_resources    = bridge_set_resources,
+#else
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_bus_enable_resources,
+        .init             = amd8132_pcix_init,
+        .scan_bus         = amd8132_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_AMD,
+        .device = 0x7458,
+};
+
+static void ioapic_enable(device_t dev)
+{
+	uint32_t value;
+
+	value = pci_read_config32(dev, 0x44);
+	if (dev->enabled) {
+		value |= ((1 << 1) | (1 << 0));
+	} else {
+		value &= ~((1 << 1) | (1 << 0));
+	}
+	pci_write_config32(dev, 0x44, value);
+}
+static void amd8132_ioapic_init(device_t dev)
+{
+        uint32_t dword;
+        unsigned chip_rev;
+
+        /* Find the revision of the 8132 */
+        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+
+        if (chip_rev == 0x01) {
+#if 0
+                /* Errata #43 */
+                dword = pci_read_config32(dev, 0xc8);
+		dword |= (0x3<<23);
+		pci_write_config32(dev, 0xc8, dword);
+#endif
+
+        }
+
+
+        if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+                //for b1 b2
+                /* Errata #73 */
+                dword = pci_read_config32(dev, 0x80);
+                dword |= (0x1f<<5);
+                pci_write_config32(dev, 0x80, dword);
+                dword = pci_read_config32(dev, 0x88);
+                dword |= (0x1f<<5);
+                pci_write_config32(dev, 0x88, dword);
+
+                /* Errata #74 */
+                dword = pci_read_config32(dev, 0x7c);
+                dword &= ~(0x3<<30);
+                dword |= (0x01<<30);
+                pci_write_config32(dev, 0x7c, dword);
+        }
+
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+	.set_subsystem    = pci_dev_set_subsystem,
+};
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = amd8132_ioapic_init,
+	.scan_bus         = 0,
+	.enable           = ioapic_enable,
+	.ops_pci          = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7459,
+
+};

Modified: trunk/src/southbridge/amd/amd8151/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/amd8151/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/amd8151/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += amd8151_agp3.c
+driver-y += agp3.c

Copied: trunk/src/southbridge/amd/amd8151/agp3.c (from r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/amd8151/agp3.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/amd8151/amd8151_agp3.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Tyan Computer
+ * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void agp3bridge_init(device_t dev)
+{
+	uint8_t byte;
+
+	/* Enable BM, MEM and IO */
+	byte = pci_read_config32(dev, 0x04);
+	byte |= 0x07;
+	pci_write_config8(dev, 0x04, byte);
+
+	return;
+}
+
+static struct device_operations agp3bridge_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init		  = agp3bridge_init,
+	.scan_bus	  = pci_scan_bridge,
+};
+
+static const struct pci_driver agp3bridge_driver __pci_driver = {
+	.ops    = &agp3bridge_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7455, // AGP Bridge
+};
+
+static void agp3dev_enable(device_t dev)
+{
+	uint32_t value;
+
+	/* AGP enable */
+	value = pci_read_config32(dev, 0xa8);
+	value |= (3<<8)|2; //AGP 8x
+	pci_write_config32(dev, 0xa8, value);
+
+	/* enable BM and MEM */
+	value = pci_read_config32(dev, 0x4);
+	value |= 6;
+	pci_write_config32(dev, 0x4, value);
+#if 0
+	/* FIXME: should we add agp aperture base and size here ?
+	 * or it is done by AGP drivers */
+#endif
+}
+
+static struct pci_operations pci_ops_pci_dev = {
+        .set_subsystem    = pci_dev_set_subsystem,
+};
+
+static struct device_operations agp3dev_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = 0,
+	.scan_bus = 0,
+	.enable   = agp3dev_enable,
+	.ops_pci  = &pci_ops_pci_dev,
+};
+
+static const struct pci_driver agp3dev_driver __pci_driver = {
+	.ops    = &agp3dev_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x7454, //AGP Device
+};

Modified: trunk/src/southbridge/amd/cs5530/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5530/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5530/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,7 +19,7 @@
 ##
 
 driver-y += cs5530.c
-driver-y += cs5530_isa.c
-driver-y += cs5530_ide.c
-driver-y += cs5530_vga.c
-driver-y += cs5530_pirq.c
+driver-y += isa.c
+driver-y += ide.c
+driver-y += vga.c
+driver-y += pirq.c

Copied: trunk/src/southbridge/amd/cs5530/enable_rom.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_enable_rom.c)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "cs5530.h"
+
+static void cs5530_enable_rom(void)
+{
+	uint8_t reg8;
+
+	/* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */
+	device_t dev = PCI_DEV(0, 0x12, 0);
+
+	/*
+	 * Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
+	 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
+	 *
+	 * Make the ROM write-protected.
+	 */
+	reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG);
+	reg8 |= LOWER_ROM_ADDRESS_RANGE;
+	reg8 |= UPPER_ROM_ADDRESS_RANGE;
+	reg8 &= ~ROM_WRITE_ENABLE;
+	pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
+
+	/* Set positive decode on ROM. */
+	reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
+	reg8 |= BIOS_ROM_POSITIVE_DECODE;
+	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+}

Copied: trunk/src/southbridge/amd/cs5530/ide.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_ide.c)
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "cs5530.h"
+
+/**
+ * Initialize the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
+ * enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init(struct device *dev)
+{
+	uint8_t reg8;
+	struct southbridge_amd_cs5530_config *conf = dev->chip_info;
+
+	reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
+
+	/* Enable/disable the primary IDE interface. */
+	if (conf->ide0_enable) {
+		reg8 |= PRIMARY_IDE_ENABLE;
+	} else {
+		reg8 &= ~(PRIMARY_IDE_ENABLE);
+	}
+
+	/* Enable/disable the secondary IDE interface. */
+	if (conf->ide1_enable) {
+		reg8 |= SECONDARY_IDE_ENABLE;
+	} else {
+		reg8 &= ~(SECONDARY_IDE_ENABLE);
+	}
+
+	pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
+
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
+		    conf->ide0_enable ? "enabled" : "disabled");
+	printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
+		    conf->ide1_enable ? "enabled" : "disabled");
+}
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.enable			= 0,
+	.scan_bus		= scan_static_bus,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor = PCI_VENDOR_ID_CYRIX,
+	.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5530/isa.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/isa.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_isa.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "cs5530.h"
+
+static void cs5530_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void isa_init(struct device *dev)
+{
+}
+
+static struct device_operations isa_ops = {
+	.read_resources		= cs5530_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.enable			= 0,
+	.scan_bus		= scan_static_bus,
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_CYRIX,
+	.device	= PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+};

Copied: trunk/src/southbridge/amd/cs5530/pirq.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/pirq.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_pirq.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_CYRIX,
+			       PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0);
+
+	if (pdev) {
+		pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0]));
+		pci_write_config8(pdev, 0x5d, (pIntAtoD[3] << 4 | pIntAtoD[2]));
+	}
+}
+#endif

Copied: trunk/src/southbridge/amd/cs5530/vga.c (from r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5530/vga.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5530/cs5530_vga.c)
@@ -0,0 +1,495 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+/**
+ * @brief Activate the VGA feature in a Geode GX1 based system with one
+ * of five possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA.
+ * Also it is prepared to display a splash screen.
+ *
+ * In a Geode GX1 environment the companion CS5530 is the VGA
+ * interface only. It contains a PLL for pixel clock generation,
+ * DACs to generate the analogue RGB signals, drivers for HSYNC
+ * and VSYNC and drivers for a digital flatpanel.
+ * The graphic feature itself (framebuffer, acceleration unit)
+ * is not part of this device. It is part of the CPU device.
+ * But both depend on each other, we cannot divide them into
+ * different drivers. So this driver is not only a CS5530 driver,
+ * it is also a Geode GX1 chipset graphic driver.
+ */
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <cpu/amd/gx1def.h>
+#include <delay.h>
+
+#if CONFIG_GX1_VIDEO == 1
+/*
+ * Some register descriptions that are no listed in cpu/amd/gx1def.h
+ */
+#define CS5530_DOT_CLK_CONFIG	0x0024
+#define CS5530_DISPLAY_CONFIG	0x0004
+
+#define DC_FB_ST_OFFSET		0x8310	/* framebuffer start offset */
+#define DC_CB_ST_OFFSET		0x8314	/* compression start offset */
+#define DC_CURS_ST_OFFSET	0x8318	/* cursor start offset */
+#define DC_VID_ST_OFFSET	0x8320	/* video start offset */
+#define DC_LINE_DELTA		0x8324	/* fb and cb skip counts */
+#define DC_BUF_SIZE		0x8328	/* fb and cb line size */
+#define DC_H_TIMING_1		0x8330	/* horizontal timing... */
+#define DC_H_TIMING_2		0x8334
+#define DC_H_TIMING_3		0x8338
+#define DC_FP_H_TIMING		0x833C
+#define DC_V_TIMING_1		0x8340	/* vertical timing... */
+#define DC_V_TIMING_2		0x8344
+#define DC_V_TIMING_3		0x8348
+#define DC_FP_V_TIMING		0x834C
+#define DC_TIMING_CFG		0x8308
+#define DC_OUTPUT_CFG		0x830C
+
+/**
+ * what colour depth should be used as default (in bpp)
+ * Note: Currently no other value than 16 is supported
+ */
+#define COLOUR_DEPTH 16
+
+/**
+ * Support for a few basic video modes
+ * Note: all modes only for CRT. The flatpanel feature is
+ * not supported here (due to the lack of hardware to test)
+ */
+struct video_mode {
+	int pixel_clock;		/*<< pixel clock in Hz */
+	unsigned long pll_value;	/*<< pll register value for this clock */
+
+	int visible_pixel;		/*<< visible pixels in one line */
+	int hsync_start;		/*<< start of hsync behind visible pixels */
+	int hsync_end;			/*<< end of hsync behind its start */
+	int line_length;		/*<< whole line length */
+
+	int visible_lines;		/*<< visible lines on screen */
+	int vsync_start;		/*<< vsync start behind last visible line */
+	int vsync_end;			/*<< end of vsync behind its start */
+	int picture_length;		/*<< whole screen length */
+
+	int sync_pol;		/*<< 0: low, 1: high, bit 0 hsync, bit 1 vsync */
+};
+
+/*
+ * values for .sync_pol in struct video_mode
+ */
+#define HSYNC_HIGH_POL 0
+#define HSYNC_LOW_POL 1
+#define VSYNC_HIGH_POL 0
+#define VSYNC_LOW_POL 2
+
+/**
+ * 640x480 @ 72Hz hsync: 37.9kHz
+ * VESA standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
+ */
+static const struct video_mode mode_640x480 = {
+	.pixel_clock = 31500000,
+	.pll_value = 0x33915801,
+
+	.visible_pixel = 640,
+	.hsync_start = 664,
+	.hsync_end = 704,	/* 1.27 us sync length */
+	.line_length = 832,	/* 26.39us */
+
+	.visible_lines = 480,
+	.vsync_start = 489,
+	.vsync_end = 491,
+	.picture_length = 520, /* 13.89ms */
+
+	.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
+};
+
+/**
+ * 800x600 @ 72Hz hsync: 48.1kHz
+ * VESA standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync
+ */
+static const struct video_mode mode_800x600 = {
+	.pixel_clock = 50000000,
+	.pll_value = 0x23088801,
+
+	.visible_pixel = 800,
+	.hsync_start = 856,
+	.hsync_end = 976,
+	.line_length = 1040, /* 20.8us */
+
+	.visible_lines = 600,
+	.vsync_start = 637,
+	.vsync_end = 643,
+	.picture_length = 666, /* 13.89ms */
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * 1024x768 @ 70Hz (VESA) hsync: 56.5kHz
+ * Standard mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync
+ */
+static const struct video_mode mode_1024x768 = {
+	.pixel_clock = 75000000,
+	.pll_value = 0x37E22801,
+
+	.visible_pixel = 1024,
+	.hsync_start = 1048,
+	.hsync_end = 1184,
+	.line_length = 1328,	/* 17.7us */
+
+	.visible_lines = 768,
+	.vsync_start = 771,
+	.vsync_end = 777,
+	.picture_length = 806,	/* 14.3us */
+
+	.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
+};
+
+/**
+ * 1280x960 @ 60Hz (VESA) hsync: 60.0kHz
+ * Mode for classic 4:3 monitors
+ * Copied from X11:
+ * ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync
+ */
+static const struct video_mode mode_1280x960 = {
+	.pixel_clock = 108000000,
+	.pll_value = 0x2710C805,
+
+	.visible_pixel = 1280,
+	.hsync_start = 1376,
+	.hsync_end = 1488,
+	.line_length = 1800,	/* 16.67us */
+
+	.visible_lines = 960,
+	.vsync_start = 961,
+	.vsync_end = 964,
+	.picture_length = 1000,	/* 16.67ms */
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz
+ * Mode for modern 5:4 flat screens
+ * Copied from X11:
+ * ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync
+ */
+static const struct video_mode mode_1280x1024 = {
+	.pixel_clock = 108000000,
+	.pll_value = 0x2710C805,
+
+	.visible_pixel = 1280,
+	.hsync_start = 1328,
+	.hsync_end = 1440,
+	.line_length = 1688,	/* 15.6us */
+
+	.visible_lines = 1024,
+	.vsync_start = 1025,
+	.vsync_end = 1028,
+	.picture_length = 1066,
+
+	.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
+};
+
+/**
+ * List of supported common modes
+ */
+static const struct video_mode *modes[] = {
+	&mode_640x480,	/* CONFIG_GX1_VIDEOMODE = 0 */
+	&mode_800x600,	/* CONFIG_GX1_VIDEOMODE = 1 */
+	&mode_1024x768,	/* CONFIG_GX1_VIDEOMODE = 2 */
+	&mode_1280x960,	/* CONFIG_GX1_VIDEOMODE = 3 */
+	&mode_1280x1024	/* CONFIG_GX1_VIDEOMODE = 4 */
+};
+
+/* make a sanity check at buildtime */
+#if CONFIG_GX1_VIDEOMODE > 4
+# error Requested video mode is unknown!
+#endif
+
+/**
+ * Setup the pixel PLL in the companion chip
+ * @param[in] base register's base address
+ * @param[in] pll_val pll register value to be set
+ *
+ * The PLL to program here is located in the CS5530
+ */
+static void cs5530_set_clock_frequency(u32 io_base, unsigned long pll_val)
+{
+	unsigned long reg;
+
+	/* disable the PLL first, reset and power it down */
+	reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
+	reg |= 0x80000100;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* write the new PLL setting */
+	reg |= (pll_val & ~0x80000920);
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	mdelay(1);	/* wait for control voltage to be 0V */
+
+	/* enable the PLL */
+	reg |= 0x00000800;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* clear reset */
+	reg &= ~0x80000000;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+
+	/* clear bypass */
+	reg &= ~0x00000100;
+	write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+}
+
+/**
+ * Setup memory layout
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Memory layout must be setup in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers.
+ * Note: Using compressed buffer is not supported yet!
+ * (makes more sense later, but not while booting)
+ *
+ * At this point a check is missed if the requested video
+ * mode is possible with the provided video memory.
+ * Check if symbol CONFIG_VIDEO_MB is at least:
+ * - 1 (=1MiB) for VGA and SVGA
+ * - 2 (=2MiB) for XGA
+ * - 4 (=4MiB) for SXGA
+ */
+static void dc_setup_layout(u32 gx_base, const struct video_mode *mode)
+{
+	u32 base = 0x00000000;
+
+	write32(gx_base + DC_FB_ST_OFFSET, base);
+
+	base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines;
+
+	write32(gx_base + DC_CB_ST_OFFSET, base);
+	write32(gx_base + DC_CURS_ST_OFFSET, base);
+	write32(gx_base + DC_VID_ST_OFFSET, base);
+	write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2);
+	write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3);
+}
+
+/**
+ * Setup the HSYNC/VSYNC, active video timing
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Sync signal generation is done in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers
+ *
+ * |<------------------------- htotal ----------------------------->|
+ * |<------------ hactive -------------->|                          |
+ * |                       hblankstart-->|                          |
+ * |                                                    hblankend-->|
+ * |                                hsyncstart-->|                  |
+ * |                                           hsyncend-->|         |
+ * |#####################################___________________________| RGB data
+ * |______________________________________________---------_________| HSYNC
+ *
+ * |<------------------------- vtotal ----------------------------->|
+ * |<------------ vactive -------------->|                          |
+ * |                       vblankstart-->|                          |
+ * |                                                    vblankend-->|
+ * |                                vsyncstart-->|                  |
+ * |                                           vsyncend-->|         |
+ * |#####################################___________________________| line data
+ * |______________________________________________---------_________| YSYNC
+ */
+static void dc_setup_timing(u32 gx_base, const struct video_mode *mode)
+{
+	u32 hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
+	u32 vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
+
+	hactive = mode->visible_pixel & 0x7FF;
+	hblankstart = hactive;
+	hsyncstart = mode->hsync_start & 0x7FF;
+	hsyncend =  mode->hsync_end & 0x7FF;
+	hblankend = mode->line_length & 0x7FF;
+	htotal = hblankend;
+
+	vactive = mode->visible_lines & 0x7FF;
+	vblankstart = vactive;
+	vsyncstart = mode->vsync_start & 0x7FF;
+	vsyncend =  mode->vsync_end & 0x7FF;
+	vblankend = mode->picture_length & 0x7FF;
+	vtotal = vblankend;
+
+	/* row description */
+	write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16));
+	/* horizontal blank description */
+	write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16));
+	/* horizontal sync description */
+	write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16));
+	write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16));
+
+	/* line description */
+	write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16));
+	/* vertical blank description */
+	write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16));
+	/* vertical sync description */
+	write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16));
+	write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16));
+}
+
+/**
+ * Setup required internals to bring the mode up and running
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * Must be setup in Geode GX1's chipset.
+ * Note: This routine assumes unlocked DC registers.
+ */
+static void cs5530_activate_mode(u32 gx_base, const struct video_mode *mode)
+{
+	write32(gx_base + DC_GENERAL_CFG, 0x00000080);
+	mdelay(1);
+	dc_setup_layout(gx_base,mode);
+	dc_setup_timing(gx_base,mode);
+
+	write32(gx_base + DC_GENERAL_CFG, 0x2000C581);
+	write32(gx_base + DC_TIMING_CFG, 0x0000002F);
+	write32(gx_base + DC_OUTPUT_CFG, 0x00003004);
+}
+
+/**
+ * Activate the current mode to be "visible" outside
+ * @param[in] gx_base GX register area
+ * @param[in] mode Data about the video mode to setup
+ *
+ * As we now activate the interface this must be done
+ * in the CS5530
+ */
+static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
+{
+	u32 val;
+
+	val = (u32)mode->sync_pol << 8;
+	write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
+}
+
+#if CONFIG_SPLASH_GRAPHIC == 1
+
+/*
+ * This bitmap file must provide:
+ * int width: pixel count in one line
+ * int height: line count
+ * int colours: ount of used colour
+ * unsigned long colour_map[]: RGB 565 colours to be used
+ * unsigned char bitmap[]: index per pixel into colour_map[], width*height pixels
+ */
+#include "bitmap.c"
+
+/*
+ * show a boot splash screen in the right lower corner of the screen
+ * swidth: screen width in pixel
+ * sheight: screen height in lines
+ * pitch: line pitch in bytes
+ * base: screen base address
+ *
+ * This routine assumes we are using a 16 bit colour depth!
+ */
+static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base)
+{
+	int word_count,i;
+	unsigned short *adr;
+	u32 xstart,ystart,x,y;
+	/*
+	 * fill the screen with the colour of the
+	 * left top pixel in the graphic
+	 */
+	word_count = pitch * sheight;
+	adr = (unsigned short*)base;
+	for (i = 0; i < word_count; i++, adr++)
+		*adr = colour_map[bitmap[0]];
+
+	/*
+	 * paint the splash
+	 */
+	xstart = swidth-width;
+	ystart = sheight-height;
+	for (y = 0; y < height; y++) {
+		adr=(unsigned short*)(base + pitch*(y+ystart) + 2 * xstart);
+		for (x = 0; x < width; x++) {
+			*adr=(unsigned short)colour_map[(int)bitmap[x + y * width]];
+			adr++;
+		}
+	}
+}
+#else
+# define show_boot_splash_16(w, x, y , z)
+#endif
+
+/**
+ * coreboot management part
+ * @param[in] dev Info about the PCI device to initialise
+ */
+static void cs5530_vga_init(device_t dev)
+{
+	const struct video_mode *mode;
+	u32 io_base, gx_base;
+
+	io_base = pci_read_config32(dev, 0x10);
+	gx_base = GX_BASE;
+	mode = modes[CONFIG_GX1_VIDEOMODE];
+
+	printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n",
+		mode->visible_pixel, mode->visible_lines, mode->pixel_clock);
+
+	cs5530_set_clock_frequency(io_base, mode->pll_value);
+
+	write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC);
+
+	show_boot_splash_16(mode->visible_pixel, mode->visible_lines,
+		mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000));
+
+	cs5530_activate_mode(gx_base, mode);
+
+	cs5530_activate_video(io_base, mode);
+	write32(gx_base + DC_UNLOCK, 0x00000000);
+}
+
+static struct device_operations vga_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = cs5530_vga_init,
+	.enable           = NULL, /* not required */
+};
+
+static const struct pci_driver vga_pci_driver __pci_driver = {
+	.ops 	= &vga_ops,
+	.vendor = PCI_VENDOR_ID_CYRIX,
+	.device = PCI_DEVICE_ID_CYRIX_5530_VIDEO,
+};
+
+#endif /* #if CONFIG_GX1_VIDEO == 1 */

Modified: trunk/src/southbridge/amd/cs5535/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5535/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5535/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
 driver-y += cs5535.c
-#driver-y += cs5535_pci.c
-#driver-y += cs5535_ide.c
+#driver-y += pci.c
+#driver-y += ide.c
 ramstage-y += chipsetinit.c

Copied: trunk/src/southbridge/amd/cs5535/early_setup.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c)
@@ -0,0 +1,149 @@
+/*
+ *
+ * cs5535_early_setup.c:	Early chipset initialization for CS5535 companion device
+ *
+ *
+ * This file implements the initialization sequence documented in section 4.2 of
+ * AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
+ *
+ */
+
+/**
+ * @brief Setup PCI IDSEL for CS5535
+ *
+ *
+ */
+
+static void cs5535_setup_extmsr(void)
+{
+	msr_t msr;
+
+	/* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
+	msr.hi = msr.lo = 0x00000000;
+#if CS5535_GLINK_PORT_NUM <= 4
+	msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
+#else
+	msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
+#endif
+	wrmsr(0x5000201e, msr);
+}
+
+static void cs5535_setup_idsel(void)
+{
+	/* write IDSEL to the write once register at address 0x0000 */
+	outl(0x1 << (CS5535_DEV_NUM + 10), 0);
+}
+
+static void cs5535_usb_swapsif(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(0x51600005);
+	//USB Serial short detect bit.
+	if (msr.hi & 0x10) {
+		/* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
+		 * SERSHRT error bit */
+		msr.hi &= 0xFFFFFFFB;
+		wrmsr(0x51600005, msr);
+	}
+}
+
+static void cs5535_setup_iobase(void)
+{
+	msr_t msr;
+	/* setup LBAR for SMBus controller */
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
+	/* setup LBAR for GPIO */
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
+	/* setup LBAR for MFGPT */
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
+
+	/* setup LBAR for ACPI */
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
+
+	/* setup LBAR for PM Support */
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
+}
+
+static void cs5535_setup_gpio(void)
+{
+	uint32_t val;
+
+	/* setup GPIO pins 14/15 for SDA/SCL */
+	val = (1<<14 | 1<<15);
+	/* Output Enable */
+	outl(0x3fffc000, 0x6100 + 0x04);
+	//outl(val, 0x6100 + 0x04);
+	/* Output AUX1 */
+	outl(0x3fffc000, 0x6100 + 0x10);
+	//outl(val, 0x6100 + 0x10);
+	/* Input Enable */
+	//outl(0x0f5af0a5, 0x6100 + 0x20);
+	outl(0x3fffc000, 0x6100 + 0x20);
+	//outl(val, 0x6100 + 0x20);
+	/* Input AUX1 */
+	//outl(0x3ffbc004, 0x6100 + 0x34);
+	outl(0x3fffc000, 0x6100 + 0x34);
+	//outl(val, 0x6100 + 0x34);
+}
+
+void cs5535_disable_internal_uart(void)
+{
+}
+
+static void cs5535_setup_cis_mode(void)
+{
+	msr_t msr;
+
+	/* setup CPU interface serial to mode C on both sides */
+	msr = rdmsr(GLPCI_SB_CTRL);
+	msr.lo &= ~0x18;
+	msr.lo |= 0x10;
+	wrmsr(GLPCI_SB_CTRL, msr);
+	//Only do this if we are building for 5535
+	msr.lo = 0x2;
+	msr.hi = 0x0;
+	wrmsr(VIP_GIO_MSR_SEL, msr);
+}
+
+static void dummy(void)
+{
+}
+
+static void cs5535_early_setup(void)
+{
+	msr_t msr;
+
+	cs5535_setup_extmsr();
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	if (msr.lo & (0x3f << 26)) {
+		/* PLL is already set and we are reboot from PLL reset */
+		print_debug("reboot from BIOS reset\n");
+		return;
+	}
+	print_debug("Setup idsel\n");
+	cs5535_setup_idsel();
+	print_debug("Setup iobase\n");
+	cs5535_usb_swapsif();
+	cs5535_setup_iobase();
+	print_debug("Setup gpio\n");
+	cs5535_setup_gpio();
+	print_debug("Setup cis_mode\n");
+	cs5535_setup_cis_mode();
+	print_debug("Setup smbus\n");
+	cs5535_enable_smbus();
+	dummy();
+}

Copied and modified: trunk/src/southbridge/amd/cs5535/early_smbus.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/cs5535/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "cs5535_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x6000
 

Copied: trunk/src/southbridge/amd/cs5535/ide.c (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_ide.c)
@@ -0,0 +1,30 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "cs5535.h"
+
+static void ide_init(struct device *dev)
+{
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
+}
+
+static void ide_enable(struct device *dev)
+{
+	printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.enable           = ide_enable,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops 	= &ide_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_CS5535_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5535/smbus.h (from r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5535/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5535/cs5535_smbus.h)
@@ -0,0 +1,46 @@
+//#include <device/smbus_def.h>
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+
+#define	SMB_SDA		0x00
+#define SMB_STS		0x01
+#define SMB_CTRL_STS	0x02
+#define	SMB_CTRL1	0x03
+#define SMB_ADD		0x04
+#define SMB_CTRL2	0x05
+#define	SMB_CTRL3	0x06
+
+#define SMB_STS_SLVSTP	(0x01 << 7)
+#define SMB_STS_SDAST	(0x01 << 6)
+#define	SMB_STS_BER	(0x01 << 5)
+#define SMB_STS_NEGACK	(0x01 << 4)
+#define	SMB_STS_STASTR	(0x01 << 3)
+#define SMB_STS_NMATCH	(0x01 << 2)
+#define	SMB_STS_MASTER	(0x01 << 1)
+#define SMB_STS_XMIT	(0x01 << 0)
+
+#define	SMB_CSTS_TGSCL	(0x01 << 5)
+#define SMB_CSTS_TSDA	(0x01 << 4)
+#define	SMB_CSTS_GCMTCH	(0x01 << 3)
+#define SMB_CSTS_MATCH	(0x01 << 2)
+#define	SMB_CSTS_BB	(0x01 << 1)
+#define SMB_CSTS_BUSY	(0x01 << 0)
+
+#define	SMB_CTRL1_STASTRE (0x01 << 7)
+#define SMB_CTRL1_NMINTE  (0x01 << 6)
+#define	SMB_CTRL1_GCMEN   (0x01 << 5)
+#define SMB_CTRL1_ACK     (0x01 << 4)
+#define	SMB_CTRL1_RSVD    (0x01 << 3)
+#define SMB_CTRL1_INTEN   (0x01 << 2)
+#define	SMB_CTRL1_STOP    (0x01 << 1)
+#define SMB_CTRL1_START   (0x01 << 0)
+
+#define	SMB_ADD_SAEN	  (0x01 << 7)
+
+#define	SMB_CTRL2_ENABLE  0x01
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0xfbff
+
+#define SMBUS_IO_BASE 0x6000

Modified: trunk/src/southbridge/amd/cs5536/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/cs5536/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/cs5536/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,5 +18,5 @@
 ##
 
 driver-y += cs5536.c
-driver-y += cs5536_ide.c
-driver-y += cs5536_pirq.c
+driver-y += ide.c
+driver-y += pirq.c

Copied: trunk/src/southbridge/amd/cs5536/early_setup.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c)
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * cs5536_early_setup.c:	Early chipset initialization for CS5536 companion device
+ *	This file implements the initialization sequence documented in section 4.2 of
+ *	AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
+ */
+
+/**
+ * @brief Setup PCI IDSEL for CS5536
+ */
+static void cs5536_setup_extmsr(void)
+{
+	msr_t msr;
+
+	/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
+	msr.hi = msr.lo = 0x00000000;
+#if CS5536_GLINK_PORT_NUM <= 4
+	msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
+#else
+	msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
+#endif
+	wrmsr(GLPCI_ExtMSR, msr);
+}
+
+static void cs5536_setup_idsel(void)
+{
+	/* write IDSEL to the write once register at address 0x0000 */
+	outl(0x1 << (CS5536_DEV_NUM + 10), 0);
+}
+
+static void cs5536_usb_swapsif(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
+	//USB Serial short detect bit.
+	if (msr.hi & 0x10) {
+		/* We need to preserve bits 32,33,35 and not clear any BIST
+		 * error, but clear the SERSHRT error bit */
+
+		msr.hi &= 0xFFFFFFFB;
+		wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
+	}
+}
+
+static void cs5536_setup_iobase(void)
+{
+	msr_t msr;
+	/* setup LBAR for SMBus controller */
+	msr.hi = 0x0000f001;
+	msr.lo = SMBUS_IO_BASE;
+	wrmsr(MDD_LBAR_SMB, msr);
+
+	/* setup LBAR for GPIO */
+	msr.hi = 0x0000f001;
+	msr.lo = GPIO_IO_BASE;
+	wrmsr(MDD_LBAR_GPIO, msr);
+
+	/* setup LBAR for MFGPT */
+	msr.hi = 0x0000f001;
+	msr.lo = MFGPT_IO_BASE;
+	wrmsr(MDD_LBAR_MFGPT, msr);
+
+	/* setup LBAR for ACPI */
+	msr.hi = 0x0000f001;
+	msr.lo = ACPI_IO_BASE;
+	wrmsr(MDD_LBAR_ACPI, msr);
+
+	/* setup LBAR for PM Support */
+	msr.hi = 0x0000f001;
+	msr.lo = PMS_IO_BASE;
+	wrmsr(MDD_LBAR_PMS, msr);
+}
+
+static void cs5536_setup_power_button(void)
+{
+#if CONFIG_ENABLE_POWER_BUTTON
+	outl(0x40020000, PMS_IO_BASE + 0x40);
+#endif
+
+	/* setup WORK_AUX/GPIO24, it is the external signal for 5536
+	 * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
+	 * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
+	 * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
+	 */
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+
+}
+
+static void cs5536_setup_gpio(void)
+{
+	uint32_t val;
+
+	/* setup GPIO pins 14/15 for SDA/SCL */
+	val = GPIOL_15_SET | GPIOL_14_SET;
+	/* Output Enable */
+	outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* Output AUX1 */
+	outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Input Enable */
+	outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+	/* Input AUX1 */
+	outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+}
+
+void cs5536_disable_internal_uart(void)
+{
+	msr_t msr;
+	/* The UARTs default to enabled.
+	 * Disable and reset them and configure them later. (SIO init)
+	 */
+	msr = rdmsr(MDD_UART1_CONF);
+	msr.lo = 1;		// reset
+	wrmsr(MDD_UART1_CONF, msr);
+	msr.lo = 0;		// disabled
+	wrmsr(MDD_UART1_CONF, msr);
+
+	msr = rdmsr(MDD_UART2_CONF);
+	msr.lo = 1;		// reset
+	wrmsr(MDD_UART2_CONF, msr);
+	msr.lo = 0;		// disabled
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+static void cs5536_setup_cis_mode(void)
+{
+	msr_t msr;
+
+	/* setup CPU interface serial to mode B to match CPU */
+	msr = rdmsr(GLPCI_SB_CTRL);
+	msr.lo &= ~0x18;
+	msr.lo |= 0x10;
+	wrmsr(GLPCI_SB_CTRL, msr);
+}
+
+/**
+ * Enable the on-chip UART.
+ *
+ * See page 412 of the AMD Geode CS5536 Companion Device data book.
+ */
+static void cs5536_setup_onchipuart1(void)
+{
+	msr_t msr;
+
+	/* Setup early for polling only mode.
+	 * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
+	 *        GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
+	 * 2. Enable UART I/O space in MDD.
+	 *        MSR 0x51400014 bit 18:16
+	 * 3. Enable UART controller.
+	 *        MSR 0x5140003A bit 0, 1
+	 */
+
+	/* GPIO8 - UART1_TX */
+	/* Set: Output Enable (0x4) */
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+
+	/* GPIO9 - UART1_RX */
+	/* Set: Input Enable (0x20) */
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select (0x34) */
+	outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set address to 0x3F8. */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x7 << 16;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks)
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* Enable COM1. */
+	wrmsr(MDD_UART1_CONF, msr);
+}
+
+static void cs5536_setup_onchipuart2(void)
+{
+	msr_t msr;
+
+	/* GPIO4 - UART2_TX */
+	/* Set: Output Enable  (0x4) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* GPIO4 - UART2_RX */
+	/* Set: Input Enable   (0x20) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select  (0x34) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set: GPIO 3 + 3 Pull Up  (0x18) */
+	outl(GPIOL_3_SET | GPIOL_4_SET,
+	     GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
+
+	/* set address to 2F8 */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x5 << 20;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* enable COM2 */
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+void cs5536_setup_onchipuart(int uart)
+{
+	switch (uart) {
+	case 1:
+		cs5536_setup_onchipuart1();
+		break;
+	case 2:
+		cs5536_setup_onchipuart2();
+		break;
+	}
+}
+
+
+/* note: you can't do prints in here in most cases,
+ * and we don't want to hang on serial, so they are
+ * commented out
+ */
+static void cs5536_early_setup(void)
+{
+	msr_t msr;
+
+	cs5536_setup_extmsr();
+	cs5536_setup_cis_mode();
+
+	msr = rdmsr(GLCP_SYS_RSTPLL);
+	if (msr.lo & (0x3f << 26)) {
+		/* PLL is already set and we are reboot from PLL reset */
+		//print_debug("reboot from BIOS reset\n");
+		return;
+	}
+	//print_debug("Setup idsel\n");
+	cs5536_setup_idsel();
+	//print_debug("Setup iobase\n");
+	cs5536_usb_swapsif();
+	cs5536_setup_iobase();
+	//print_debug("Setup gpio\n");
+	cs5536_setup_gpio();
+	//print_debug("Setup smbus\n");
+	cs5536_enable_smbus();
+	//print_debug("Setup power button\n");
+	cs5536_setup_power_button();
+}

Copied: trunk/src/southbridge/amd/cs5536/early_smbus.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c)
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "cs5536.h"
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+#define SMBUS_TIMEOUT (1000)
+
+/* initialization for SMBus Controller */
+static void cs5536_enable_smbus(void)
+{
+
+	/* Set SCL freq and enable SMB controller */
+	/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */
+	outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
+
+	/* Setup SMBus host controller address to 0xEF */
+	outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD);
+
+}
+
+static void smbus_delay(void)
+{
+	/* inb(0x80); */
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+	unsigned long loops = SMBUS_TIMEOUT;
+	unsigned char val;
+
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_STS);
+		if ((val & SMB_STS_SDAST) != 0)
+			break;
+		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+			/*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
+			return SMBUS_ERROR;
+		}
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+/* generate a smbus start condition */
+static int smbus_start_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+
+	/* issue a START condition */
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+	/* check for bus conflict */
+	val = inb(smbus_io_base + SMB_STS);
+	if ((val & SMB_STS_BER) != 0)
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	/* check for SDA status */
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_CTRL1);
+		if ((val & SMB_CTRL1_STOP) == 0) {
+			break;
+		}
+		outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_stop_condition(unsigned smbus_io_base)
+{
+	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+	unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+/*	if (state) */
+	outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+/*	else
+		outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+*/
+	return 0;
+}
+
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
+{
+	unsigned char val;
+
+	/* send the slave address */
+	outb(device, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+		/* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
+		return SMBUS_ERROR;
+	}
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+	unsigned char val;
+
+	/* send the command */
+	outb(command, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static unsigned char smbus_get_result(unsigned smbus_io_base)
+{
+	return inb(smbus_io_base + SMB_SDA);
+}
+
+static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+					unsigned char device,
+					unsigned char address)
+{
+	unsigned char error = 0;
+
+	if ((smbus_check_stop_condition(smbus_io_base))) {
+		error = 1;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 2;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
+		error = 3;
+		goto err;
+	}
+
+	smbus_ack(smbus_io_base, 1);
+
+	if ((smbus_send_command(smbus_io_base, address))) {
+		error = 4;
+		goto err;
+	}
+
+	if ((smbus_start_condition(smbus_io_base))) {
+		error = 5;
+		goto err;
+	}
+
+	if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
+		error = 6;
+		goto err;
+	}
+
+	if ((smbus_stop_condition(smbus_io_base))) {
+		error = 7;
+		goto err;
+	}
+
+	return smbus_get_result(smbus_io_base);
+
+      err:
+	print_debug("SMBUS READ ERROR:");
+	print_debug_hex8(error);
+	print_debug(" device:");
+	print_debug_hex8(device);
+	print_debug("\n");
+	/* stop, clean up the error, and leave */
+	smbus_stop_condition(smbus_io_base);
+	outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
+	outb(0x0, smbus_io_base + SMB_STS);
+	return 0xFF;
+}
+
+static inline int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}

Copied: trunk/src/southbridge/amd/cs5536/ide.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_ide.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "cs5536.h"
+
+#define IDE_CFG	  0x40
+	#define CHANEN  (1L <<  1)
+	#define PWB	(1L << 14)
+	#define CABLE	(1L << 16)
+#define IDE_DTC	  0x48
+#define IDE_CAST  0x4C
+#define IDE_ETC	  0x50
+
+static void ide_init(struct device *dev)
+{
+	uint32_t ide_cfg;
+
+	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
+	/* GPIO and IRQ setup are handled in the main chipset code. */
+
+	// Enable the channel and Post Write Buffer
+	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
+	ide_cfg = pci_read_config32(dev, IDE_CFG);
+	ide_cfg |= CHANEN | PWB;
+	pci_write_config32(dev, IDE_CFG, ide_cfg);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.enable = 0,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE,
+};

Copied: trunk/src/southbridge/amd/cs5536/pirq.c (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/pirq.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_pirq.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+	device_t pdev;
+
+	pdev = dev_find_device(PCI_VENDOR_ID_AMD,
+			       PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+
+	if (pdev) {
+		pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12
+			| pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));
+	}
+}
+#endif

Copied: trunk/src/southbridge/amd/cs5536/smbus2.h (from r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/cs5536/smbus2.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h)
@@ -0,0 +1,317 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
+
+#define	SMB_SDA		0x00
+#define SMB_STS		0x01
+#define SMB_CTRL_STS	0x02
+#define	SMB_CTRL1	0x03
+#define SMB_ADD		0x04
+#define SMB_CTRL2	0x05
+#define	SMB_CTRL3	0x06
+
+#define SMB_STS_SLVSTP	(0x01 << 7)
+#define SMB_STS_SDAST	(0x01 << 6)
+#define	SMB_STS_BER	(0x01 << 5)
+#define SMB_STS_NEGACK	(0x01 << 4)
+#define	SMB_STS_STASTR	(0x01 << 3)
+#define SMB_STS_NMATCH	(0x01 << 2)
+#define	SMB_STS_MASTER	(0x01 << 1)
+#define SMB_STS_XMIT	(0x01 << 0)
+
+#define	SMB_CSTS_TGSCL	(0x01 << 5)
+#define SMB_CSTS_TSDA	(0x01 << 4)
+#define	SMB_CSTS_GCMTCH	(0x01 << 3)
+#define SMB_CSTS_MATCH	(0x01 << 2)
+#define	SMB_CSTS_BB	(0x01 << 1)
+#define SMB_CSTS_BUSY	(0x01 << 0)
+
+#define	SMB_CTRL1_STASTRE (0x01 << 7)
+#define SMB_CTRL1_NMINTE  (0x01 << 6)
+#define	SMB_CTRL1_GCMEN   (0x01 << 5)
+#define SMB_CTRL1_ACK     (0x01 << 4)
+#define	SMB_CTRL1_RSVD    (0x01 << 3)
+#define SMB_CTRL1_INTEN   (0x01 << 2)
+#define	SMB_CTRL1_STOP    (0x01 << 1)
+#define SMB_CTRL1_START   (0x01 << 0)
+
+#define	SMB_ADD_SAEN	  (0x01 << 7)
+
+#define	SMB_CTRL2_ENABLE  0x01
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0xfbff
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+	unsigned long loops = SMBUS_TIMEOUT;
+	unsigned char val;
+
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_STS);
+		if ((val & SMB_STS_SDAST) != 0)
+			break;
+		if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+			printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val);
+			return SMBUS_ERROR;
+		}
+	} while (--loops);
+
+	outb(0, smbus_io_base + SMB_STS);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_write(unsigned smbus_io_base, unsigned char byte)
+{
+
+	outb(byte, smbus_io_base + SMB_SDA);
+	return smbus_wait(smbus_io_base);
+}
+
+/* generate a smbus start condition */
+static int smbus_start_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+
+	/* issue a START condition */
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+	/* check for bus conflict */
+	val = inb(smbus_io_base + SMB_STS);
+	if ((val & SMB_STS_BER) != 0)
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	/* check for SDA status */
+	do {
+		smbus_delay();
+		val = inb(smbus_io_base + SMB_CTRL1);
+		if ((val & SMB_CTRL1_STOP) == 0) {
+			break;
+		}
+	} while (--loops);
+	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Make sure everything is cleared and ready to go */
+
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE),
+	     smbus_io_base + SMB_CTRL1);
+
+	outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR,
+	     smbus_io_base + SMB_STS);
+
+	val = inb(smbus_io_base + SMB_CTRL_STS);
+	outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS);
+}
+
+static int smbus_stop_condition(unsigned smbus_io_base)
+{
+	unsigned char val;
+	val = inb(smbus_io_base + SMB_CTRL1);
+	outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+
+	return 0;
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+	unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+	if (state)
+		outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+	else
+		outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+
+	return 0;
+}
+
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
+{
+	unsigned char val;
+
+	/* send the slave address */
+	outb(device, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+		printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val);
+		return SMBUS_ERROR;
+	}
+	return smbus_wait(smbus_io_base);
+}
+
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+	unsigned char val;
+
+	/* send the command */
+	outb(command, smbus_io_base + SMB_SDA);
+
+	/* check for bus conflict and NACK */
+	val = inb(smbus_io_base + SMB_STS);
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+		return SMBUS_ERROR;
+
+	return smbus_wait(smbus_io_base);
+}
+
+static void _doread(unsigned smbus_io_base, unsigned char device,
+		    unsigned char address, unsigned char *data, int count)
+{
+	int ret;
+	int index = 0;
+	unsigned char val;
+
+	if ((ret = smbus_check_stop_condition(smbus_io_base)))
+		goto err;
+
+	index++;
+
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	index++;		/* 2 */
+	if ((ret = smbus_send_slave_address(smbus_io_base, device)))
+		goto err;
+
+	index++;
+	if ((ret = smbus_send_command(smbus_io_base, address)))
+		goto err;
+
+	index++;
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	/* Clear the ack for multiple byte reads */
+	smbus_ack(smbus_io_base, (count == 1) ? 1 : 0);
+
+	index++;
+	if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01)))
+		goto err;
+
+	while (count) {
+		/* Set the ACK if this is the next to last byte */
+		smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
+
+		/* Set the stop bit if this is the last byte to read */
+
+		if (count == 1)
+			smbus_stop_condition(smbus_io_base);
+
+		val = inb(smbus_io_base + SMB_SDA);
+		*data++ = val;
+
+		if (count > 1) {
+			ret = smbus_wait(smbus_io_base);
+			if (ret)
+				return;
+		}
+
+		count--;
+	}
+
+	return;
+
+      err:
+	printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret);
+}
+
+static inline unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+		unsigned char device, unsigned char address)
+{
+	unsigned char val = 0;
+	_doread(smbus_io_base, device, address, &val, sizeof(val));
+	return val;
+}
+
+static inline unsigned short do_smbus_read_word(unsigned smbus_io_base,
+		 unsigned char device, unsigned char address)
+{
+	unsigned short val = 0;
+	_doread(smbus_io_base, device, address, (unsigned char *)&val,
+		sizeof(val));
+	return val;
+}
+
+static int _dowrite(unsigned smbus_io_base, unsigned char device,
+		    unsigned char address, unsigned char *data, int count)
+{
+
+	int ret;
+
+	if ((ret = smbus_check_stop_condition(smbus_io_base)))
+		goto err;
+
+	if ((ret = smbus_start_condition(smbus_io_base)))
+		goto err;
+
+	if ((ret = smbus_send_slave_address(smbus_io_base, device)))
+		goto err;
+
+	if ((ret = smbus_send_command(smbus_io_base, address)))
+		goto err;
+
+	while (count) {
+		if ((ret = smbus_write(smbus_io_base, *data++)))
+			goto err;
+		count--;
+	}
+
+	smbus_stop_condition(smbus_io_base);
+	return 0;
+
+      err:
+	printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret);
+	return -1;
+}
+
+static inline int do_smbus_write_byte(unsigned smbus_io_base,
+		unsigned char device, unsigned char address, unsigned char data)
+{
+	return _dowrite(smbus_io_base, device, address,
+			(unsigned char *)&data, 1);
+}
+
+static inline int do_smbus_write_word(unsigned smbus_io_base,
+		unsigned char device, unsigned char address, unsigned short data)
+{
+	return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
+			2);
+}

Modified: trunk/src/southbridge/amd/rs690/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/rs690/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs690/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,5 +1,5 @@
 driver-y += rs690.c
-driver-y += rs690_cmn.c
-driver-y += rs690_pcie.c
-driver-y += rs690_ht.c
-driver-y += rs690_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c

Copied: trunk/src/southbridge/amd/rs690/cmn.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/cmn.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_cmn.c)
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include "rs690.h"
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+
+	pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg + 0x4, data);
+
+}
+
+/* extension registers */
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+{
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg;
+	return *((u32 *) addr);
+}
+
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);*/
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg_pos;
+
+	reg = reg_old = *((u32 *) addr);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		*((u32 *) addr) = reg;
+	}
+}
+
+u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+u32 nbpcie_p_read_index(device_t dev, u32 index)
+{
+	return nb_read_index((dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+{
+	nb_write_index((dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+	}
+}
+
+/***********************************************************
+* To access bar3 we need to program PCI MMIO 7 in K8.
+* in_out:
+*	1: enable/enter k8 temp mmio base
+*	0: disable/restore
+***********************************************************/
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
+{
+	/* K8 Function1 is address map */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+
+	if (in_out) {
+		u32 dword, sblk;
+
+		/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* Fill MMIO limit/base pair. */
+		pci_write_config32(k8_f1, 0xbc,
+				   (((pcie_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
+		pci_write_config32(k8_f1, 0xb4,
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
+	} else {
+		pci_write_config32(k8_f1, 0xb8, 0);
+		pci_write_config32(k8_f1, 0xbc, 0);
+		pci_write_config32(k8_f1, 0xb0, 0);
+		pci_write_config32(k8_f1, 0xb4, 0);
+	}
+}
+
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+{
+	switch (port) {
+	case 2:		/* GFX, bit4-5 */
+	case 3:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 2), 0 << (port + 2));
+		break;
+	case 4:		/* GPP, bit20-24 */
+	case 5:
+	case 6:
+	case 7:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 17), 0 << (port + 17));
+		break;
+	}
+}
+
+/********************************************************************************************************
+* Output:
+*	0: no device is present.
+*	1: device is present and is trained.
+********************************************************************************************************/
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 count = 5000;
+	u32 lc_state, reg;
+	int8_t current, res = 0;
+
+	while (count--) {
+		mdelay(40);
+		udelay(200);
+		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
+			     port, lc_state);
+		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
+
+		switch (current) {
+		case 0x00:	/* 0x00-0x04 means no device is present */
+		case 0x01:
+		case 0x02:
+		case 0x03:
+		case 0x04:
+			res = 0;
+			count = 0;
+			break;
+		case 0x07:	/* device is in compliance state (training sequence is doen). Move to train the next device */
+			res = 1;	/* TODO: CIM sets it to 0 */
+			count = 0;
+			break;
+		case 0x10:
+			reg =
+			    pci_ext_read_config32(nb_dev, dev,
+						  PCIE_VC0_RESOURCE_STATUS);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
+			/* check bit1 */
+			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
+				/* set bit8=1, bit0-2=bit4-6 */
+				u32 tmp;
+				reg =
+				    nbpcie_p_read_index(dev,
+							PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg &= 0xfff8;	/* clear bit0-2 */
+				reg += tmp;	/* merge */
+				reg |= 1 << 8;
+				count++;	/* CIM said "keep in loop"?  */
+			} else {
+				res = 1;
+				count = 0;
+			}
+			break;
+		default:	/* reset pcie */
+			res = 0;
+			count = 0;	/* break loop */
+			break;
+		}
+	}
+	return res;
+}
+
+/*
+* Compliant with CIM_33's ATINB_SetToms.
+* Set Top Of Memory below and above 4G.
+*/
+void rs690_set_tom(device_t nb_dev)
+{
+	extern uint64_t uma_memory_base;
+
+	/* set TOM */
+	pci_write_config32(nb_dev, 0x90, uma_memory_base);
+	nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+}
+

Copied: trunk/src/southbridge/amd/rs690/early_setup.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_early_setup.c)
@@ -0,0 +1,484 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#define NBHTIU_INDEX		0xA8
+#define NBMISC_INDEX		0x60
+#define NBMC_INDEX 		0xE8
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+	pci_write_config32(dev, index_reg, index /* | 0x80 */ );
+	pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+static u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+static u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+static u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				 u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				   u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				  u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
+				    u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+				 u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+/*
+* Compliant with CIM_33's ATINB_PrepareInit
+*/
+static void get_cpu_rev(void)
+{
+	u32 eax, ebx, ecx, edx;
+	__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
+			  :"0"(1));
+	printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
+	if (eax <= 0xfff)
+		printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
+	else if (eax <= 0x10fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
+	else if (eax <= 0x20fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
+	else if (eax <= 0x40fff)
+		printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
+	else if (eax == 0x60fb1 || eax == 0x60f81)	/*These two IDS are exception, they are G1. */
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
+	else if (eax <= 0X60FF0)
+		printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
+	else if (eax <= 0x100000)
+		printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
+	else
+		printk(BIOS_INFO, "CPU Rev is K8_10.\n");
+}
+
+static u8 get_nb_rev(device_t nb_dev)
+{
+	u32 reg;
+	reg = pci_read_config32(nb_dev, 0x00);
+	if (0x7911 == (reg >> 16))
+		return 7;
+	reg = pci_read_config8(nb_dev, 0x89);	/* copy from CIM, can't find in doc */
+	if (reg & 0x2)		/* check bit1 */
+		return 7;
+	if (reg & 0x1)		/* check bit0 */
+		return 6;
+	else
+		return 5;
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_HTInit
+* Init HT link speed/width for rs690 -- k8 link
+*****************************************/
+static void rs690_htinit(void)
+{
+	/*
+	 * About HT, it has been done in enumerate_ht_chain().
+	 */
+	device_t k8_f0, rs690_f0;
+	u32 reg;
+	u8 reg8;
+	u8 k8_ht_freq;
+
+	k8_f0 = PCI_DEV(0, 0x18, 0);
+	/************************
+	* get k8's ht freq, in k8's function 0, offset 0x88
+	* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
+	* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
+	* value to this reg, and that value takes effect on the next warm reset or
+	* LDTSTOP_L disconnect sequence.
+	* 0000b = 200Mhz
+	* 0010b = 400Mhz
+	* 0100b = 600Mhz
+	* 0101b = 800Mhz
+	* 0110b = 1Ghz
+	* 1111b = 1Ghz
+	************************/
+	reg = pci_read_config32(k8_f0, 0x88);
+	k8_ht_freq = (reg & 0xf00) >> 8;
+	printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	rs690_f0 = PCI_DEV(0, 0, 0);
+	reg8 = pci_read_config8(rs690_f0, 0x9c);
+	printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+	 */
+	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+		printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		reg8 |= 0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+		printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		reg8 &= ~0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	}
+}
+
+/*******************************************************
+* Optimize k8 with UMA.
+* See BKDG_NPT_0F guide for details.
+* The processor node is addressed by its Node ID on the HT link and can be
+* accessed with a device number in the PCI configuration space on Bus0.
+* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
+* to Device 25, and so on.
+* The processor implements configuration registers in PCI configuration
+* space using the following four headers
+*	Function0: HT technology configuration
+*	Function1: Address map configuration
+*	Function2: DRAM and HT technology Trace mode configuration
+*	Function3: Miscellaneous configuration
+*******************************************************/
+static void k8_optimization(void)
+{
+	device_t k8_f0, k8_f2, k8_f3;
+	msr_t msr;
+
+	printk(BIOS_INFO, "k8_optimization()\n");
+	k8_f0 = PCI_DEV(0, 0x18, 0);
+	k8_f2 = PCI_DEV(0, 0x18, 2);
+	k8_f3 = PCI_DEV(0, 0x18, 3);
+
+	pci_write_config32(k8_f0, 0x90, 0x01700178);	/* CIM NPT_Optimization */
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
+			      1 << 26 | 1 << 27);
+	set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
+	set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15);	/* TODO */
+
+	pci_write_config32(k8_f3, 0x70, 0x51320111);	/* CIM NPT_Optimization */
+	pci_write_config32(k8_f3, 0x74, 0x50304021);
+	pci_write_config32(k8_f3, 0x78, 0x08002A00);
+	if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
+		pci_write_config32(k8_f3, 0x7C, 0x0000211B); /* dual core */
+	else
+		pci_write_config32(k8_f3, 0x7C, 0x0000211C); /* single core */
+	set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
+
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+	set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
+	set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10);
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
+	set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
+
+	msr = rdmsr(0xC001001F);
+	msr.lo &= ~(1 << 9);
+	msr.hi &= ~(1 << 4);
+	wrmsr(0xC001001F, msr);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
+*****************************************/
+static void rs690_por_pcicfg_init(device_t nb_dev)
+{
+	/* enable PCI Memory Access */
+	set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
+	/* Set RCRB Enable */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
+	/* allow decode of 640k-1MB */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
+	/* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
+	/* Power Management Register Enable */
+	set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
+
+	/* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+	 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
+	 * BMMsgEn */
+	set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
+
+	/* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
+	 * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
+	set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
+	/* Reg94h[4:0] = 0x0  P drive strength offset 0
+	 * Reg94h[6:5] = 0x2  P drive strength additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
+
+	/* Reg94h[20:16] = 0x0  N drive strength offset 0
+	 * Reg94h[22:21] = 0x2  N drive strength additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
+
+	/* Reg80h[4:0] = 0x0  Termination offset
+	 * Reg80h[6:5] = 0x2  Termination additive adjust */
+	set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
+
+	/* Reg80h[14] = 0x1   Enable receiver termination control */
+	set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
+
+	/* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
+	 * Reg94h[14] = 0x1  Enable drive strength control */
+	set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
+
+	/* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
+	set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
+
+	/*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
+	 * force this BAR as mem type in rs690_gfx.c */
+	set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
+
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_MCIndex_POR_TABLE
+*****************************************/
+static void rs690_por_mc_index_init(device_t nb_dev)
+{
+	set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
+	set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
+	set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
+	set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
+	set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
+* Compliant with CIM_33's MISC_INIT_TBL
+*****************************************/
+static void rs690_por_misc_index_init(device_t nb_dev)
+{
+	/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
+	 * Block non-snoop DMA request if PMArbDis is set.
+	 * Set BMSetDis */
+	set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
+	set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
+
+	/* NBCFG (NBMISCIND 0x0): NB_CNTL -
+	 *   HIDE_NB_AGP_CAP  ([0], default=1)HIDE
+	 *   HIDE_P2P_AGP_CAP ([1], default=1)HIDE
+	 *   HIDE_NB_GART_BAR ([2], default=1)HIDE
+	 *   AGPMODE30        ([4], default=0)DISABLE
+	 *   AGP30ENCHANCED   ([5], default=0)DISABLE
+	 *   HIDE_AGP_CAP     ([8], default=1)ENABLE */
+	set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506);	/* set bit 10 for MSI */
+
+	/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
+	 *      set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
+	 * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
+	set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
+
+	/* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
+	set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
+
+	/* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
+	set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
+
+	/* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
+	set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
+
+	/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
+	 * Enable access to DEV8
+	 * Enable setPower message for all ports
+	 */
+	set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
+	set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
+	set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
+
+	set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
+	set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
+	/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
+	set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE
+*****************************************/
+static void rs690_por_htiu_index_init(device_t nb_dev)
+{
+	/* 0xBC:
+	* Enables GSM mode for C1e or C3 with pop-up
+	* Prevents AllowLdtStop from being asserted during HT link recovery
+	* Allows FID cycles to be serviced faster. Needed for RS690 A12. No harm in RS690 A11 */
+	set_htiu_enable_bits(nb_dev, 0x05, ~0xffffffff, 0x0BC);
+	/* 0x4203A202:
+	* Enables writes to pass in-progress reads
+	* Enables streaming of CPU writes
+	* Enables extended write buffer for CPU writes
+	* Enables additional response buffers
+	* Enables special reads to pass writes
+	* Enables decoding of C1e/C3 and FID cycles
+	* Enables HTIU-display handshake bypass.
+	* Enables tagging fix */
+	set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x4203A202);
+
+	/* Enables byte-write optimization for IOC requests
+	* Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
+	* Disables upstream system-management delay */
+	set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001);
+
+	/* HTIUNBIND 0x16 [1] = 0x1     Enable crc decoding fix */
+	set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2);
+}
+
+/*****************************************
+* Compliant with CIM_33's ATINB_POR_INIT_JMPDI
+* Configure RS690 registers to power-on default RPR.
+* POR: Power On Reset
+* RPR: Register Programming Requirements
+*****************************************/
+static void rs690_por_init(device_t nb_dev)
+{
+	printk(BIOS_INFO, "rs690_por_init\n");
+	/* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
+	rs690_por_pcicfg_init(nb_dev);
+
+	/* ATINB_MCIND_POR_TABLE */
+	rs690_por_mc_index_init(nb_dev);
+
+	/* ATINB_MISCIND_POR_TABLE */
+	rs690_por_misc_index_init(nb_dev);
+
+	/* ATINB_HTIUNBIND_POR_TABLE */
+	rs690_por_htiu_index_init(nb_dev);
+
+	/* ATINB_CLKCFG_PORT_TABLE */
+	/* rs690 A11 SB Link full swing? */
+}
+
+/* enable CFG access to Dev8, which is the SB P2P Bridge */
+static void enable_rs690_dev8(void)
+{
+	set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
+}
+
+
+
+/*
+* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
+*/
+static void rs690_before_pci_init(void)
+{
+}
+
+/*
+* The calling sequence is same as CIM.
+*/
+static void rs690_early_setup(void)
+{
+	device_t nb_dev = PCI_DEV(0, 0, 0);
+	printk(BIOS_INFO, "rs690_early_setup()\n");
+
+	/*ATINB_PrepareInit */
+	get_cpu_rev();
+	switch (get_nb_rev(nb_dev)) {	/* PCIEMiscInit */
+	case 5:
+		printk(BIOS_INFO, "NB Revision is A11.\n");
+		break;
+	case 6:
+		printk(BIOS_INFO, "NB Revision is A12.\n");
+		break;
+	case 7:
+		printk(BIOS_INFO, "NB Revision is A21.\n");
+		break;
+	}
+
+	k8_optimization();
+	rs690_por_init(nb_dev);
+}

Copied: trunk/src/southbridge/amd/rs690/gfx.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/gfx.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_gfx.c)
@@ -0,0 +1,625 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ *  for rs690 internal graphics device
+ *  device id of internal grphics:
+ *	RS690M/T: 0x791f
+ *    RS690:	   0x791e
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs690.h"
+
+#define CLK_CNTL_INDEX	0x8
+#define CLK_CNTL_DATA	0xC
+
+#ifdef UNUSED_CODE
+static u32 clkind_read(device_t dev, u32 index)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
+	return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
+}
+#endif
+
+static void clkind_write(device_t dev, u32 index, u32 data)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+	/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
+	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
+}
+
+/*
+* pci_dev_read_resources thinks it is a IO type.
+* We have to force it to mem type.
+*/
+static void rs690_gfx_read_resources(device_t dev)
+{
+	printk(BIOS_INFO, "rs690_gfx_read_resources.\n");
+
+	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
+	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
+	   which tells us it is a memory address base.
+	 */
+	pci_write_config32(dev, 0x24, 0x00000000);
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+	compact_resources(dev);
+}
+
+static void internal_gfx_pci_dev_init(struct device *dev)
+{
+	u16 deviceid, vendorid;
+	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
+	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	     deviceid, vendorid);
+
+	pci_dev_init(dev);
+
+	/* clk ind */
+	clkind_write(dev, 0x08, 0x01);
+	clkind_write(dev, 0x0C, 0x22);
+	clkind_write(dev, 0x0F, 0x0);
+	clkind_write(dev, 0x11, 0x0);
+	clkind_write(dev, 0x12, 0x0);
+	clkind_write(dev, 0x14, 0x0);
+	clkind_write(dev, 0x15, 0x0);
+	clkind_write(dev, 0x16, 0x0);
+	clkind_write(dev, 0x17, 0x0);
+	clkind_write(dev, 0x18, 0x0);
+	clkind_write(dev, 0x19, 0x0);
+	clkind_write(dev, 0x1A, 0x0);
+	clkind_write(dev, 0x1B, 0x0);
+	clkind_write(dev, 0x1C, 0x0);
+	clkind_write(dev, 0x1D, 0x0);
+	clkind_write(dev, 0x1E, 0x0);
+	clkind_write(dev, 0x26, 0x0);
+	clkind_write(dev, 0x27, 0x0);
+	clkind_write(dev, 0x28, 0x0);
+	clkind_write(dev, 0x5C, 0x0);
+}
+
+
+/*
+* Set registers in RS690 and CPU to enable the internal GFX.
+* Please refer to CIM source code and BKDG.
+*/
+static void rs690_internal_gfx_enable(device_t dev)
+{
+	u32 l_dword;
+	int i;
+	device_t k8_f0 = 0, k8_f2 = 0;
+	device_t nb_dev = dev_find_slot(0, 0);
+
+	printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
+		    nb_dev);
+
+	/* set APERTURE_SIZE, 128M. */
+	l_dword = pci_read_config32(nb_dev, 0x8c);
+	printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword);
+	l_dword &= 0xffffff8f;
+	pci_write_config32(nb_dev, 0x8c, l_dword);
+
+	/* set TOM */
+	rs690_set_tom(nb_dev);
+
+	/* LPC DMA Deadlock workaround? */
+	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	l_dword = pci_read_config32(k8_f0, 0x68);
+	l_dword &= ~(1 << 22);
+	l_dword |= (1 << 21);
+	pci_write_config32(k8_f0, 0x68, l_dword);
+
+	/* Enable 64bit mode. */
+	set_nbmc_enable_bits(nb_dev, 0x5f, 0, 1 << 9);
+	set_nbmc_enable_bits(nb_dev, 0xb0, 0, 1 << 8);
+
+	/* 64bit Latency. */
+	set_nbmc_enable_bits(nb_dev, 0x5f, 0x7c00, 0x800);
+
+	/* UMA dual channel control register. */
+	nbmc_write_index(nb_dev, 0x86, 0x3d);
+
+	/* check the setting later!! */
+	set_htiu_enable_bits(nb_dev, 0x07, 1 << 7, 0);
+
+	/* UMA mode, powerdown memory PLL. */
+	set_nbmc_enable_bits(nb_dev, 0x74, 0, 1 << 31);
+
+	/* Copy CPU DDR Controller to NB MC. */
+	/* Why K8_MC_REG80 is special? */
+	k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	for (i = 0; i <= (0x80 - 0x40) / 4; i++) {
+		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
+		nbmc_write_index(nb_dev, 0x63 + i, l_dword);
+	}
+
+	/* Set K8 MC for UMA, Family F. */
+	l_dword = pci_read_config32(k8_f2, 0xa0);
+	l_dword |= 0x2c;
+	pci_write_config32(k8_f2, 0xa0, l_dword);
+	l_dword = pci_read_config32(k8_f2, 0x94);
+	l_dword &= 0xf0ffffff;
+	l_dword |= 0x07000000;
+	pci_write_config32(k8_f2, 0x94, l_dword);
+
+	/* set FB size and location. */
+	nbmc_write_index(nb_dev, 0x1b, 0x00);
+	l_dword = nbmc_read_index(nb_dev, 0x1c);
+	l_dword &= 0xffff0;
+	l_dword |= 0x400 << 20;
+	l_dword |= 0x4;
+	nbmc_write_index(nb_dev, 0x1c, l_dword);
+	l_dword = nbmc_read_index(nb_dev, 0x1d);
+	l_dword &= 0xfffff000;
+	l_dword |= 0x0400;
+	nbmc_write_index(nb_dev, 0x1d, l_dword);
+	nbmc_write_index(nb_dev, 0x100, 0x3fff3800);
+
+	/* Program MC table. */
+	set_nbmc_enable_bits(nb_dev, 0x00, 0, 1 << 31);
+	l_dword = nbmc_read_index(nb_dev, 0x91);
+	l_dword |= 0x5;
+	nbmc_write_index(nb_dev, 0x91, l_dword);
+	set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1 << 6);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
+
+	/* TODO: the optimization of voltage and frequency */
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations pcie_ops = {
+	.read_resources = rs690_gfx_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs690_gfx_init, */
+	.scan_bus = 0,
+	.enable = rs690_internal_gfx_enable,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * The dev id of 690G is 791E, while the id of 690M, 690T is 791F.
+ * We should list both of them here.
+ * */
+static const struct pci_driver pcie_driver_690t __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX,
+};
+
+static const struct pci_driver pcie_driver_690 __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690_INT_GFX,
+};
+
+/* step 12 ~ step 14 from rpr */
+static void single_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n");
+
+	/* step 12 training, releases hold training for GFX port 0 (device 2) */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4);
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	result = PcieTrainPort(nb_dev, dev, 2);
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n");
+
+	/* step 13 Power Down Control */
+	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+
+	/* step 13.a Link Training was NOT successful */
+	if (!result) {
+		set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
+		set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
+		if (cfg->gfx_tmds)
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+		else {
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
+			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
+		}
+	} else {		/* step 13.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
+			break;
+		case 8:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
+			break;
+		}
+	}
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n");
+
+	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
+	printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n");
+}
+
+/* step 15 ~ step 18 from rpr */
+static void dual_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs690_config *cfg =
+		    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* step 15: Training for Device 2 */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+	/* Releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	/* PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, 2);
+
+	/* step 16: Power Down Control for Device 2 */
+	/* step 16.a Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port A */
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f);
+	} else {		/* step 16.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
+			break;
+		}
+	}
+
+	/* step 17: Training for Device 3 */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 5, 0 << 5);
+	/* Releases hold training for GFX port 0 (device 3) */
+	PcieReleasePortTraining(nb_dev, dev, 3);
+	/* PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, 3);
+
+	/*step 18: Power Down Control for Device 3 */
+	/* step 18.a Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port B and PLL1 */
+		nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+	} else {		/* step 18.b Link Training was successful */
+
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7070 : 0xe0e0);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3030 : 0xc0c0);
+			break;
+		}
+	}
+}
+
+
+/* For single port GFX configuration Only
+* width:
+* 	000 = x16
+* 	001 = x1
+*	010 = x2
+*	011 = x4
+*	100 = x8
+*	101 = x12 (not supported)
+*	110 = x16
+*/
+static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
+{
+	u32 reg32;
+	device_t sb_dev;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* step 5.9.1.1 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+
+	/* step 5.9.1.2 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+	/* step 5.9.1.3 */
+	set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
+	/* step 5.9.1.4 */
+	set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
+	/* step 5.9.2.4 */
+	if (0 == cfg->gfx_reconfiguration)
+		set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
+
+	/* step 5.9.1.5 */
+	do {
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+	}
+	while (reg32 & 0x100);
+
+	/* step 5.9.1.6 */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	do {
+		reg32 = pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg32 & VC_NEGOTIATION_PENDING);
+
+	/* step 5.9.1.7 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+	if (((reg32 & 0x70) >> 4) != 0x6) {
+		/* the unused lanes should be powered off. */
+	}
+
+	/* step 5.9.1.8 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
+}
+
+/*
+* GFX Core initialization, dev2, dev3
+*/
+void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 reg16;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+		    nb_dev, dev, port);
+
+	/* step 0, REFCLK_SEL, skip A11 revision */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9,
+			       cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9);
+	printk(BIOS_INFO, "rs690_gfx_init step0.\n");
+
+	/* step 1, lane reversal (only need if CMOS option is enabled) */
+	if (cfg->gfx_lane_reversal) {
+		set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+		if (cfg->gfx_dual_slot)
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+	}
+	printk(BIOS_INFO, "rs690_gfx_init step1.\n");
+
+	/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+	/* AMD calls the configuration CrossFire */
+	if (cfg->gfx_dual_slot)
+		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+	printk(BIOS_INFO, "rs690_gfx_init step2.\n");
+
+	/* step 2, TMDS, (only need if CMOS option is enabled) */
+	if (cfg->gfx_tmds) {
+	}
+
+	/* step 3, GFX overclocking, (only need if CMOS option is enabled) */
+	/* skip */
+
+	/* step 4, reset the GFX link */
+	/* step 4.1 asserts both calibration reset and global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
+
+	/* step 4.2 de-asserts calibration reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
+
+	/* step 4.3 wait for at least 200us */
+	udelay(200);
+
+	/* step 4.4 de-asserts global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
+
+	/* step 4.5 asserts both calibration reset and global reset */
+	/* a weird step in RPR, don't do that */
+	/* set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14); */
+
+	/* step 4.6 bring external GFX device out of reset, wait for 1ms */
+	mdelay(1);
+	printk(BIOS_INFO, "rs690_gfx_init step4.\n");
+
+	/* step 5 program PCIE memory mapped configuration space */
+	/* done by enable_pci_bar3() before */
+
+	/* step 6 SBIOS compile flags */
+        if (cfg->gfx_tmds) {
+                /* step 6.2.2 Clock-Muxing Control */
+                /* step 6.2.2.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+
+                /* step 6.2.2.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+
+                /* step 6.2.2.3 */
+                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+
+                /* step 6.2.3 Lane-Muxing Control */
+                /* step 6.2.3.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+
+                /* step 6.2.4 Received Data Control */
+                /* step 6.2.4.1 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+
+                /* step 6.2.4.2 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+
+                /* step 6.2.4.3 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+
+                /* step 6.2.4.4 */
+                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+
+                /* step 6.2.5 PLL Power Down Control */
+                /* step 6.2.5.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+
+                /* step 6.2.6 Driving Strength Control */
+                /* step 6.2.6.1 */
+                set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+
+                /* step 6.2.6.2 */
+                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+        }
+
+        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+
+	/* step 7 compliance state, (only need if CMOS option is enabled) */
+	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+	if (cfg->gfx_compliance) {
+		/* force compliance */
+		set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
+		/* release hold training for device 2. GFX initialization is done. */
+		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
+		printk(BIOS_INFO, "rs690_gfx_init step7.\n");
+		return;
+	}
+
+	/* step 8 common initialization */
+	/* step 8.1 sets RCB timeout to be 25ms */
+	set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16);
+	printk(BIOS_INFO, "rs690_gfx_init step8.1.\n");
+
+	/* step 8.2 disables slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
+	printk(BIOS_INFO, "rs690_gfx_init step8.2.\n");
+
+	/* step 8.3 sets DMA payload size to 64 bytes */
+	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
+	printk(BIOS_INFO, "rs690_gfx_init step8.3.\n");
+
+	/* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still
+	 * time out and go back to Detect Idle.*/
+	set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14);
+	printk(BIOS_INFO, "rs690_gfx_init step8.4.\n");
+
+	/* step 8.5 shortens the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
+	printk(BIOS_INFO, "rs690_gfx_init step8.5.\n");
+
+	/* step 8.6 blocks DMA traffic during C3 state */
+	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+	printk(BIOS_INFO, "rs690_gfx_init step8.6.\n");
+
+	/* step 8.7 Do not gate the electrical idle form the PHY
+	 * step 8.8 Enables the escape from L1L23 */
+	set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30);
+	printk(BIOS_INFO, "rs690_gfx_init step8.8.\n");
+
+	/* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM.
+	 * SLOT_IMPLEMENTED at PCIE_CAP */
+	reg16 = pci_read_config16(dev, 0x5a);
+	reg16 |= 0x100;
+	pci_write_config16(dev, 0x5a, reg16);
+	printk(BIOS_INFO, "rs690_gfx_init step8.9.\n");
+
+	/* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider.
+	 * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */
+	set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31);
+	printk(BIOS_INFO, "rs690_gfx_init step8.10.\n");
+
+	/* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */
+	set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0);
+	printk(BIOS_INFO, "rs690_gfx_init step8.11.\n");
+
+	/* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6);
+	printk(BIOS_INFO, "rs690_gfx_init step8.12.\n");
+
+	/* step 8.13 Sets CMGOOD_OVERRIDE. */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
+	printk(BIOS_INFO, "rs690_gfx_init step8.13.\n");
+
+	/* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */
+	/* skip */
+
+	/* step 10 Optional Features, only needed if CMOS option is enabled. */
+	/* step 10.a: L0s */
+	/* enabling L0s in the RS690 GFX port(s) */
+	set_pcie_enable_bits(nb_dev, 0xF9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xA0, 0xf << 8, 8 << 8);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 |= 1 << 0;
+	/* L0s is intended as a power saving state */
+	/* pci_write_config16(dev, 0x68, reg16); */
+
+	/* enabling L0s in the External GFX Device(s) */
+
+	/* step 10.b: active state power management (ASPM L1) */
+	/* TO DO */
+
+	/* step 10.c: turning off PLL During L1/L23 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3);
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9);
+
+	/* step 10.d: TXCLK clock gating */
+	set_nbmisc_enable_bits(nb_dev, 0x7, 3, 3);
+	set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22);
+	set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4);
+
+	/* step 10.e: LCLK clock gating, done in rs690_config_misc_clk() */
+
+	/* step 11 Poll GPIO to determine whether it is single-port or dual-port configuration.
+	 * While details will be added later in the document, for now assue the single-port configuration. */
+	/* skip */
+
+	/* Single-port/Dual-port configureation. */
+	switch (cfg->gfx_dual_slot) {
+	case 0:
+		single_port_configuration(nb_dev, dev);
+		break;
+	case 1:
+		dual_port_configuration(nb_dev, dev);
+		break;
+	default:
+		printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
+		break;
+	}
+}

Copied: trunk/src/southbridge/amd/rs690/ht.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/ht.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_ht.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "rs690.h"
+
+/* for UMA internal graphics */
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
+{
+	device_t k8_f0;
+	u8 reg;
+
+	k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 21, 1 << 21);
+
+	reg = nbpcie_p_read_index(sb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(sb_dev, 0x10, reg);
+
+	reg = nbpcie_p_read_index(nb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(nb_dev, 0x10, reg);
+
+	/* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
+	 * Set this bit to avoid a deadlock condition. */
+	reg = htiu_read_index(nb_dev, 0x6);
+	reg |= 0x1000000;	/* bit26 */
+	htiu_write_index(nb_dev, 0x6, reg);
+}
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/*
+	 * 1 is APIC enable
+	 * 18 is enable nb to accept A4 interrupt request from SB.
+	 */
+	dword = pci_read_config32(dev, 0x4C);
+	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
+	pci_write_config32(dev, 0x4C, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = pcie_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS690_HT,
+};

Copied: trunk/src/southbridge/amd/rs690/pcie.c (from r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs690/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs690/rs690_pcie.c)
@@ -0,0 +1,401 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs690.h"
+
+/*------------------------------------------------
+* Global variable
+------------------------------------------------*/
+PCIE_CFG AtiPcieCfg = {
+	PCIE_ENABLE_STATIC_DEV_REMAP,	/* Config */
+	0,			/* ResetReleaseDelay */
+	0,			/* Gfx0Width */
+	0,			/* Gfx1Width */
+	0,			/* GfxPayload */
+	0,			/* GppPayload */
+	0,			/* PortDetect, filled by GppSbInit */
+	0,			/* PortHp */
+	0,			/* DbgConfig */
+	0,			/* DbgConfig2 */
+	0,			/* GfxLx */
+	0,			/* GppLx */
+	0,			/* NBSBLx */
+	0,			/* PortSlotInit */
+	0,			/* Gfx0Pwr */
+	0,			/* Gfx1Pwr */
+	0			/* GppPwr */
+};
+
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
+static void ValidatePortEn(device_t nb_dev);
+
+static void ValidatePortEn(device_t nb_dev)
+{
+}
+
+
+/*****************************************************************
+* Compliant with CIM_33's PCIEPowerOffGppPorts
+* Power off unused GPP lines
+*****************************************************************/
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg;
+	u16 state_save;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+	u8 state = cfg->port_enable;
+
+	if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
+		state &= AtiPcieCfg.PortDetect;
+	state = ~state;
+	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
+	state_save = state << 17;
+	state &= !(AtiPcieCfg.PortHp);
+	reg = nbmisc_read_index(nb_dev, 0x0c);
+	reg |= state;
+	nbmisc_write_index(nb_dev, 0x0c, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x08);
+	reg |= state_save;
+	nbmisc_write_index(nb_dev, 0x08, reg);
+
+	if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
+	    && !(AtiPcieCfg.
+		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
+			   PCIE_GFX_COMPLIANCE))) {
+	}
+
+        if (!cfg->gfx_tmds){
+		/* step 3 Power Down Control for Southbridge */
+		reg = nbpcie_p_read_index(dev, 0xa2);
+
+		switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
+		case 1:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+			break;
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+#ifdef UNUSED_CODE
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+}
+#endif
+
+/**********************************************************************
+**********************************************************************/
+static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	/* enables GPP reconfiguration */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg |=
+	    (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
+	     RECONFIG_GPPSB_ATOMIC_RESET);
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x67);
+	reg &= 0xffffff0f;		/* clean */
+	reg |= cfg->gpp_configuration << 4;
+	nbmisc_write_index(nb_dev, 0x67, reg);
+
+	/* read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* delay 1ms */
+	mdelay(1);
+
+	/* waits until SB has trained to L0, poll for bit0-5 = 0x10 */
+	do {
+		reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
+		reg &= 0x3f;	/* remain LSB [5:0] bits */
+	} while (LC_STATE_RECONFIG_GPPSB != reg);
+
+	/* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
+	do {
+		reg =
+		    pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg & VC_NEGOTIATION_PENDING);
+}
+
+/*****************************************************************
+* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
+* Space to a 256MB range within the first 4GB of addressable memory.
+*****************************************************************/
+void enable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
+	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
+
+	pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS);	/* PCIEMiscInit */
+	pci_write_config32(nb_dev, 0x20, 0x00000000);
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
+	ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************************************
+* We should disable bar3 when we want to exit rs690_enable, because bar3 will be
+* remapped in set_resource later.
+*****************************************************************/
+void disable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
+	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEGPPInit
+* nb_dev:
+*	root bridge struct
+* dev:
+*	p2p bridge struct
+* port:
+*	p2p bridge number, 4-8
+*****************************************/
+void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u8 reg8;
+	u16 reg16;
+	device_t sb_dev;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
+
+	/* init GPP core */
+	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
+			     1 << 8);
+	/* PCIE initialization 5.10.2: rpr 2.12*/
+	set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0);	/* no description in datasheet. */
+
+	/* init GPPSB port */
+	/* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/
+	set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16);
+	/* PCIE initialization 5.10.2: rpr 2.4 */
+	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
+	/* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */
+	set_pcie_enable_bits(dev, 0xA0, ~0xffffffbf, (3 << 30) | (3 << 12) | (3 << 4));
+	/* PCIE initialization 5.10.2: rpr 2.13 */
+	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 6);
+
+	/* SLOT_IMPLEMENTED in pcieConfig space */
+	reg8 = pci_read_config8(dev, 0x5b);
+	reg8 |= 1 << 0;
+	pci_write_config8(dev, 0x5b, reg8);
+
+	reg16 = pci_read_config16(dev, 0x5a);
+	reg16 |= 0x100;
+	pci_write_config16(dev, 0x5a, reg16);
+	nbmisc_write_index(nb_dev, 0x34, 0);
+
+	/* check compliance rpr step 2.1*/
+	if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
+		u32 tmp;
+		tmp = nbmisc_read_index(nb_dev, 0x67);
+		tmp |= 1 << 3;
+		nbmisc_write_index(nb_dev, 0x67, tmp);
+	}
+
+	/* step 5: dynamic slave CPL buffer allocation */
+	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11);
+
+	/* step 5a: Training for GPP devices */
+	/* init GPP */
+	switch (port) {
+	case 4:		/* GPP */
+	case 5:
+	case 6:
+	case 7:
+		/* Blocks DMA traffic during C3 state */
+		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+		/* Enabels TLP flushing */
+		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+		/* check port enable */
+		if (cfg->port_enable & (1 << port)) {
+			PcieReleasePortTraining(nb_dev, dev, port);
+			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+				u8 res = PcieTrainPort(nb_dev, dev, port);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
+				if (res) {
+					AtiPcieCfg.PortDetect |= 1 << port;
+				}
+			}
+		}
+		break;
+	case 8:		/* SB */
+		break;
+	}
+	PciePowerOffGppPorts(nb_dev, dev, port);
+
+	/* step 5b: GFX devices in a GPP slot */
+
+	/* step 6a: VCI */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	if (port == 8) {
+		/* The code below between #if and #endif causes a hang on HDA init.
+		 * So we skip it. */
+#if 0
+		/* Clear bits 7:1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1);
+		/* Maps Traffic Class 1-7 to VC1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 0x7f << 1, 0x7f << 1);
+		/* Assigns VC ID to 1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24);
+		/* Enables VC1 */
+		pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31);
+
+		do {
+			reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124);
+			reg16 &= 0x2;
+		} while (reg16); /*bit[1] = 0 means VC1 flow control initialization is successful */
+#endif
+	}
+
+	/* step 6b: L0s for the southbridge link */
+	/* To enalbe L0s in the southbridage*/
+
+	/* step 6c: L0s for the GPP link(s) */
+	/* To eable L0s in the RS690 for the GPP port(s) */
+	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 |= 1 << 0;
+	pci_write_config16(dev, 0x68, reg16);
+
+	/* step 6d: ASPM L1 for the southbridge link */
+	/* To enalbe L1s in the southbridage*/
+
+	/* step 6e: ASPM L1 for GPP link(s) */;
+	set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
+	set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
+	set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);
+	reg16 = pci_read_config16(dev, 0x68);
+	reg16 &= ~0xff;
+	reg16 |= 1 << 1;
+	pci_write_config16(dev, 0x68, reg16);
+
+	/* step 6f: Turning off PLL during L1/L23 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3);
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9);
+
+	/* step 6g: TXCLK clock gating */
+	set_nbmisc_enable_bits(nb_dev, 0x7, 3 << 4, 3 << 4);
+	set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22);
+	set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4);
+
+	/* step 6h: LCLK clock gating, done in rs690_config_misc_clk() */
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEConfigureGPPCore
+*****************************************/
+void config_gpp_core(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs690_config *cfg =
+	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
+
+	reg = nbmisc_read_index(nb_dev, 0x20);
+	if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
+		reg &= 0xfffffffd;	/* set bit1 = 0 */
+	else
+		reg |= 0x2;	/* set bit1 = 1 */
+	nbmisc_write_index(nb_dev, 0x20, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x67);	/* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
+	if (cfg->gpp_configuration != ((reg >> 4) & 0xf))
+		switching_gpp_configurations(nb_dev, sb_dev);
+	ValidatePortEn(nb_dev);
+}
+
+#ifdef UNUSED_CODE
+/*****************************************
+* Compliant with CIM_33's PCIEMiscClkProg
+*****************************************/
+void pcie_config_misc_clk(device_t nb_dev)
+{
+	u32 reg;
+	struct bus pbus; /* fake bus for dev0 fun1 */
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg |= 1 << 0;
+	pci_write_config32(nb_dev, 0x4c, reg);
+
+	if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
+		/* TXCLK Clock Gating */
+		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
+		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
+
+		/* LCLK Clock Gating */
+		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg &= ~(1 << 16);
+		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	}
+
+	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
+		/* TXCLK Clock Gating */
+		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
+		set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
+		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
+
+		/* LCLK Clock Gating */
+		reg =  pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+		reg &= ~(1 << 24);
+		pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+	}
+
+	reg = pci_read_config32(nb_dev, 0x4c);
+	reg &= ~(1 << 0);
+	pci_write_config32(nb_dev, 0x4c, reg);
+}
+#endif

Modified: trunk/src/southbridge/amd/rs780/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/rs780/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs780/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,5 +1,5 @@
 driver-y += rs780.c
-driver-y += rs780_cmn.c
-driver-y += rs780_pcie.c
-driver-y += rs780_ht.c
-driver-y += rs780_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c

Copied: trunk/src/southbridge/amd/rs780/cmn.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/cmn.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_cmn.c)
@@ -0,0 +1,403 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/io.h>
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <boot/coreboot_tables.h>
+#include <delay.h>
+#include <cpu/cpu.h>
+#include "rs780.h"
+
+static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+{
+	pci_write_config32(dev, index_reg, index);
+	return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+{
+	pci_write_config32(dev, index_reg, index);
+	pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+/* extension registers */
+u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+{
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg;
+	return *((u32 *) addr);
+}
+
+void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+
+	/*get BAR3 base address for nbcfg0x1c */
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+	/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+		     dev->path.pci.devfn);*/
+	addr |= dev->bus->secondary << 20 |	/* bus num */
+	    dev->path.pci.devfn << 12 | reg_pos;
+
+	reg = reg_old = *((u32 *) addr);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		*((u32 *) addr) = reg;
+	}
+}
+
+u32 nbmisc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+u32 nbpcie_p_read_index(device_t dev, u32 index)
+{
+	return nb_read_index((dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+{
+	nb_write_index((dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
+}
+
+void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
+}
+
+u32 htiu_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+u32 nbmc_read_index(device_t nb_dev, u32 index)
+{
+	return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+{
+	nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config32(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
+{
+	u8 reg_old, reg;
+	reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		pci_write_config8(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		htiu_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nbmisc_write_index(nb_dev, reg_pos, reg);
+	}
+}
+
+void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+{
+	u32 reg_old, reg;
+	reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+	reg &= ~mask;
+	reg |= val;
+	if (reg != reg_old) {
+		nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+	}
+}
+
+/***********************************************************
+* To access bar3 we need to program PCI MMIO 7 in K8.
+* in_out:
+*	1: enable/enter k8 temp mmio base
+*	0: disable/restore
+***********************************************************/
+void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
+{
+	/* K8 Function1 is address map */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+
+	if (in_out) {
+		u32 dword, sblk;
+
+		/* Get SBLink value (HyperTransport I/O Hub Link ID). */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* Fill MMIO limit/base pair. */
+		pci_write_config32(k8_f1, 0xbc,
+				   (((pcie_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
+		pci_write_config32(k8_f1, 0xb4,
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
+		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
+	} else {
+		pci_write_config32(k8_f1, 0xb8, 0);
+		pci_write_config32(k8_f1, 0xbc, 0);
+		pci_write_config32(k8_f1, 0xb0, 0);
+		pci_write_config32(k8_f1, 0xb4, 0);
+	}
+}
+
+void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+{
+	switch (port) {
+	case 2:		/* GFX, bit4-5 */
+	case 3:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 2), 0 << (port + 2));
+		break;
+	case 4:		/* GPPSB, bit20-24 */
+	case 5:
+	case 6:
+	case 7:
+		set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
+				       1 << (port + 17), 0 << (port + 17));
+		break;
+	case 9:		/* GPP, bit 4,5 of miscind 0x2D */
+	case 10:
+		set_nbmisc_enable_bits(nb_dev, 0x2D,
+				      1 << (port - 5), 0 << (port - 5));
+		break;
+	}
+}
+
+/********************************************************************************************************
+* Output:
+*	0: no device is present.
+*	1: device is present and is trained.
+********************************************************************************************************/
+u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+{
+	u16 count = 5000;
+	u32 lc_state, reg, current_link_width, lane_mask;
+	int8_t current, res = 0;
+	u32 gfx_gpp_sb_sel;
+	void set_pcie_dereset(void);
+	void set_pcie_reset(void);
+
+	switch (port) {
+	case 2 ... 3:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX;
+		break;
+	case 4 ... 7:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB;
+		break;
+	case 9 ... 10:
+		gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
+		break;
+	default:
+		gfx_gpp_sb_sel = -1;
+		return 0;
+	}
+
+	while (count--) {
+		mdelay(40);
+		udelay(200);
+		lc_state = nbpcie_p_read_index(dev, 0xa5);	/* lc_state */
+		printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
+			     port, lc_state);
+		current = lc_state & 0x3f;	/* get LC_CURRENT_STATE, bit0-5 */
+
+		switch (current) {
+		case 0x00:	/* 0x00-0x04 means no device is present */
+		case 0x01:
+		case 0x02:
+		case 0x03:
+		case 0x04:
+			res = 0;
+			count = 0;
+			break;
+		case 0x06:
+			/* read back current link width [6:4]. */
+			current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7;
+			/* 4 means 7:4 and 15:12
+			 * 3 means 7:2 and 15:10
+			 * 2 means 7:1 and 15:9
+			 * egnoring the reversal case
+			 */
+			lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
+			reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
+			reg |= lane_mask << 8 | lane_mask;
+			reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */
+			nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg);
+			printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x",
+				     current_link_width, lane_mask);
+			set_pcie_reset();
+			mdelay(1);
+			set_pcie_dereset();
+			break;
+		case 0x07:	/* device is in compliance state (training sequence is done). Move to train the next device */
+			res = 0;
+			count = 0;
+			break;
+		case 0x10:
+			reg =
+			    pci_ext_read_config32(nb_dev, dev,
+						  PCIE_VC0_RESOURCE_STATUS);
+			printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
+			/* check bit1 */
+			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
+				/* set bit8=1, bit0-2=bit4-6 */
+				u32 tmp;
+				reg =
+				    nbpcie_p_read_index(dev,
+							PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg &= 0xfff8;	/* clear bit0-2 */
+				reg += tmp;	/* merge */
+				reg |= 1 << 8;
+				count++;	/* CIM said "keep in loop"?  */
+			} else {
+				res = 1;
+				count = 0;
+			}
+			break;
+		default:	/* reset pcie */
+			res = 0;
+			count = 0;	/* break loop */
+			break;
+		}
+	}
+	return res;
+}
+
+/*
+* Compliant with CIM_33's ATINB_SetToms.
+* Set Top Of Memory below and above 4G.
+*/
+void rs780_set_tom(device_t nb_dev)
+{
+	extern uint64_t uma_memory_base;
+
+	/* set TOM */
+	pci_write_config32(nb_dev, 0x90, uma_memory_base);
+	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
+}
+
+// extract single bit
+u32 extractbit(u32 data, int bit_number)
+{
+	return (data >> bit_number) & 1;
+}
+
+// extract bit field
+u32 extractbits(u32 source, int lsb, int msb)
+{
+	int field_width = msb - lsb + 1;
+	u32 mask = 0xFFFFFFFF >> (32 - field_width);
+	return (source >> lsb) & mask;
+}
+
+// return AMD cpuid family
+int cpuidFamily(void)
+{
+	u32 baseFamily, extendedFamily, fms;
+	
+	fms = cpuid_eax (1);
+	baseFamily = extractbits (fms, 8, 11);
+	extendedFamily = extractbits (fms, 20, 27);
+	return baseFamily + extendedFamily;
+}
+
+
+// return non-zero for AMD family 0Fh processor found
+int is_family0Fh(void)
+{
+	return cpuidFamily() == 0x0F;
+}
+
+
+// return non-zero for AMD family 10h processor found
+int is_family10h(void)
+{
+	return cpuidFamily() == 0x10;
+}

Copied and modified: trunk/src/southbridge/amd/rs780/early_setup.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/rs780/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -21,7 +21,7 @@
 #define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
 #endif
 
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBHTIU_INDEX		0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
 #define NBMISC_INDEX		0x60

Copied: trunk/src/southbridge/amd/rs780/gfx.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/gfx.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_gfx.c)
@@ -0,0 +1,1340 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ *  for rs780 internal graphics device
+ *  device id of internal grphics:
+ *	RS780:	0x9610
+ *	RS780C:	0x9611
+ *	RS780M:	0x9612
+ *	RS780MC:0x9613
+ *	RS780E: 0x9615
+ *	RS785G: 0x9710 - just works, not much tested
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include <cpu/x86/msr.h>
+#include "rs780.h"
+extern int is_dev3_present(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+extern uint64_t uma_memory_base, uma_memory_size;
+
+/* Trust the original resource allocation. Don't do it again. */
+#undef DONT_TRUST_RESOURCE_ALLOCATION
+//#define DONT_TRUST_RESOURCE_ALLOCATION
+
+#define CLK_CNTL_INDEX	0x8
+#define CLK_CNTL_DATA	0xC
+
+/* The Integrated Info Table. */
+ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
+
+#ifdef UNUSED_CODE
+static u32 clkind_read(device_t dev, u32 index)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
+	return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
+}
+#endif
+
+static void clkind_write(device_t dev, u32 index, u32 data)
+{
+	u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
+	/* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
+
+	*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
+	*(u32*)(gfx_bar2+CLK_CNTL_DATA)  = data;
+}
+
+/*
+* pci_dev_read_resources thinks it is a IO type.
+* We have to force it to mem type.
+*/
+static void rs780_gfx_read_resources(device_t dev)
+{
+	printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
+
+	/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
+	   Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
+	   which tells us it is a memory address base.
+	 */
+	pci_write_config32(dev, 0x24, 0x00000000);
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+	compact_resources(dev);
+}
+
+typedef struct _MMIORANGE
+{
+	u32	Base;
+	u32	Limit;
+	u8	Attribute;
+} MMIORANGE;
+
+MMIORANGE MMIO[8], CreativeMMIO[8];
+
+#define CIM_STATUS u32
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR	0x80000000
+#define CIM_UNSUPPORTED	0x80000001
+#define CIM_DISABLEPORT 0x80000002
+
+#define	MMIO_ATTRIB_NP_ONLY	1
+#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
+#define MMIO_ATTRIB_SKIP_ZERO 1<<2
+
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
+static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
+{
+	int i;
+	for (i=0; i<8; i++) {
+		if (pMMIO[i].Limit == 0)
+				return &pMMIO[i];
+	}
+	return 0;
+}
+
+static void FreeMMIO(MMIORANGE* pMMIO)
+{
+	pMMIO->Base = 0;
+	pMMIO->Limit = 0;
+}
+
+static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
+{
+	int i;
+	MMIORANGE * TempRange;
+	for(i=0; i<8; i++)
+	{
+		if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
+		{
+			TempRange = AllocMMIO(pMMIO);
+			if(TempRange == 0) return 0x80000000;
+			TempRange->Base = Limit;
+			TempRange->Limit = pMMIO[i].Limit;
+			TempRange->Attribute = pMMIO[i].Attribute;
+			pMMIO[i].Limit = Base;
+		}
+	}
+	TempRange = AllocMMIO(pMMIO);
+	if(TempRange == 0) return 0x80000000;
+	TempRange->Base = Base;
+	TempRange->Limit = Limit;
+	TempRange->Attribute = Attribute;
+	return 0;
+}
+
+static u8 FinalizeMMIO(MMIORANGE *pMMIO)
+{
+	int i, j, n = 0;
+	for(i=0; i<8; i++)
+	{
+		if (pMMIO[i].Base == pMMIO[i].Limit)
+		{
+			FreeMMIO(&pMMIO[i]);
+			continue;
+		}
+		for(j=0; j<i; j++)
+		{
+			if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
+			{
+				if (pMMIO[i].Base == pMMIO[j].Limit)
+				{
+					pMMIO[j].Limit = pMMIO[i].Limit;
+					 FreeMMIO(&pMMIO[i]);
+				}
+				if (pMMIO[i].Limit == pMMIO[j].Base)
+				{
+					pMMIO[j].Base = pMMIO[i].Base;
+				   FreeMMIO(&pMMIO[i]);
+				}
+			}
+		}
+	}
+	for (i=0; i<8; i++)
+	{
+		if (pMMIO[i].Limit != 0) n++;
+	}
+	return n;
+}
+
+static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
+{
+	CIM_STATUS Status = CIM_UNSUPPORTED;
+	u8 Bus, Dev, Reg, BusStart, BusEnd;
+	u32	Value;
+	device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+	device_t tempdev;
+	Value = pci_read_config32(dev0x14, 0x18);
+	BusStart = (Value >> 8) & 0xFF;
+	BusEnd = (Value >> 16) & 0xFF;
+	for(Bus = BusStart; Bus <= BusEnd; Bus++)
+	{
+		for(Dev = 0; Dev <= 0x1f; Dev++)
+		{
+			tempdev = dev_find_slot(Bus, Dev << 3);
+			Value = pci_read_config32(tempdev, 0);
+			printk(BIOS_DEBUG, "Dev ID %x \n", Value);
+			if((Value & 0xffff) == 0x1102)
+			{//Creative
+				//Found Creative SB
+			 	u32	MMIOStart = 0xffffffff;
+				u32 MMIOLimit = 0;
+				for(Reg = 0x10; Reg < 0x20; Reg+=4)
+				{
+					u32	BaseA, LimitA;
+					BaseA = pci_read_config32(tempdev, Reg);
+					Value = BaseA;
+					if(!(Value & 0x01))
+					{
+						Value = Value & 0xffffff00;
+						if(Value !=  0)
+						{
+							if(MMIOStart > Value)
+								MMIOStart = Value;
+							LimitA = 0xffffffff;
+							//WritePCI(PciAddress,AccWidthUint32,&LimitA);
+							pci_write_config32(tempdev, Reg, LimitA);
+							//ReadPCI(PciAddress,AccWidthUint32,&LimitA);
+							LimitA = pci_read_config32(tempdev, Reg);
+							LimitA = Value + (~LimitA + 1);
+							//WritePCI(PciAddress,AccWidthUint32,&BaseA);
+							pci_write_config32(tempdev, Reg, BaseA);
+							if (LimitA > MMIOLimit)
+								MMIOLimit = LimitA;
+						}
+					}
+				}
+				printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+				if (MMIOStart < MMIOLimit)
+				{
+					Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
+					if(Status == CIM_ERROR) return Status;
+				}
+			}
+		}
+	}
+	if(Status == CIM_SUCCESS)
+	{
+		//Lets optimize MMIO
+		if(FinalizeMMIO(pMMIO) > 4)
+		{
+			Status = CIM_ERROR;
+		}
+	}
+
+	return Status;
+}
+
+static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
+{
+	int i, j, n = 7;
+	device_t k8_f1;
+
+	k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+	for(i = 0; i < 8; i++)
+	{
+		int k = 0, MmioReg;
+		u32 Base = 0;
+		u32 Limit = 0;
+		for(j = 0; j < 8; j++)
+		{
+			if (Base < pMMIO[j].Base)
+			{
+				Base = pMMIO[j].Base;
+				k = j;
+			}
+		}
+		if(pMMIO[k].Limit != 0)
+		{
+			if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
+			{
+				Base = 0;
+			}
+			else
+			{
+				Base = pMMIO[k].Base | 0x3;
+				Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
+			}
+			FreeMMIO(&pMMIO[k]);
+		}
+		if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
+		MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
+		n--;
+		//RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
+		pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
+
+		//WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
+		pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
+
+		//WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
+		pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
+	}
+}
+#endif
+
+static void internal_gfx_pci_dev_init(struct device *dev)
+{
+	unsigned char * bpointer;
+	volatile u32 * GpuF0MMReg;
+	volatile u32 * pointer;
+	int i;
+	u16 command;
+	u32 value;
+	u16 deviceid, vendorid;
+	device_t nb_dev = dev_find_slot(0, 0);
+	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
+	static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
+	static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
+	static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
+
+	/* We definetely will use this in future. Just leave it here. */
+	/*struct southbridge_amd_rs780_config *cfg =
+	   (struct southbridge_amd_rs780_config *)dev->chip_info;*/
+
+	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
+	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
+	printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+	     deviceid, vendorid);
+
+	command = pci_read_config16(dev, 0x04);
+	command |= 0x7;
+	pci_write_config16(dev, 0x04, command);
+
+	/* Clear vgainfo. */
+	bpointer = (unsigned char *) &vgainfo;
+	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+
+	GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
+
+	/* GFX_InitFBAccess. */
+	value = nbmc_read_index(nb_dev, 0x10);
+	*(GpuF0MMReg + 0x2000/4) = 0x11;
+	*(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
+	*(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
+	*(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
+	*(GpuF0MMReg + 0xF774/4) = 0xffffffff;
+	*(GpuF0MMReg + 0xF770/4) = 0x00000001;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+	*(GpuF0MMReg + 0x200c/4) = 0x00000020;
+	*(GpuF0MMReg + 0x2010/4) = 0x10204810;
+	*(GpuF0MMReg + 0x2010/4) = 0x00204810;
+	*(GpuF0MMReg + 0x2014/4) = 0x10408810;
+	*(GpuF0MMReg + 0x2014/4) = 0x00408810;
+	*(GpuF0MMReg + 0x2414/4) = 0x00000080;
+	*(GpuF0MMReg + 0x2418/4) = 0x84422415;
+	*(GpuF0MMReg + 0x2418/4) = 0x04422415;
+	*(GpuF0MMReg + 0x5490/4) = 0x00000001;
+	*(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
+	/* Force allow LDT_STOP Cool'n'Quiet workaround. */
+	*(GpuF0MMReg + 0x655c/4) |= 1<<4;
+
+	// disable write combining, needed for stability
+	// reference bios does this only for RS780 rev A11
+	// need to figure out why we need it for all revs
+	*(GpuF0MMReg + 0x2000/4) = 0x00000010;
+	*(GpuF0MMReg + 0x2408/4) = 1 << 9;
+	*(GpuF0MMReg + 0x2000/4) = 0x00000011;
+
+	/* GFX_InitFBAccess finished. */
+
+#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
+	/* GFX_StartMC. */
+	set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
+	set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
+	set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
+	set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
+	set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
+	/* GFX_StartMC finished. */
+#else
+	/* for SP mode. */
+	set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
+	set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
+	set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
+	set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
+	set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
+	nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
+	nbmc_write_index(nb_dev, 0xa5, 0x222222df);
+	nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
+	udelay(10);
+	set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
+	udelay(10);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
+	udelay(200);
+	set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
+	udelay(500);
+	set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
+	set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
+	nbmc_write_index(nb_dev, 0xa4, 0x23484576);
+	nbmc_write_index(nb_dev, 0xa5, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa6, 0x00000000);
+	nbmc_write_index(nb_dev, 0xa7, 0x00000000);
+	/* GFX_StartMC finished. */
+
+	/* GFX_SPPowerManagment, don't care for new. */
+	/* Post MC Init table programming. */
+	set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
+
+	/* Do we need Write and Read Calibration? */
+	/* GFX_Init finished. */
+#endif
+
+	/* GFX_InitIntegratedInfo. */
+	/* fill the Integrated Info Table. */
+	vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
+	vgainfo.sHeader.ucTableFormatRevision = 1;
+	vgainfo.sHeader.ucTableContentRevision = 2;
+
+#if (CONFIG_GFXUMA == 0) /* SP mode. */
+	// Side port support is incomplete, do not use it
+	// These parameters must match the motherboard
+	vgainfo.ulBootUpSidePortClock = 667*100;
+	vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
+	vgainfo.ulMinSidePortClock = 333*100;
+#endif
+
+	vgainfo.ulBootUpEngineClock = 500 * 100;	       	// setup option on reference BIOS, 500 is default
+
+	// find the DDR memory frequency
+	if (is_family10h()) {
+		value = pci_read_config32(k8_f2, 0x94);		// read channel 0 DRAM Configuration High Register
+		if (extractbit(value, 14))			// if channel 0 disabled, channel 1 must have memory
+			value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
+	}
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x94);
+		vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
+	}
+
+	/* UMA Channel Number: 1 or 2. */
+	vgainfo.ucUMAChannelNumber = 1;
+	if (is_family0Fh()) {
+		value = pci_read_config32(k8_f2, 0x90);
+	if (extractbit(value, 11))  // 128-bit mode
+		vgainfo.ucUMAChannelNumber = 2;
+	}
+	if (is_family10h()) {
+		u32 dch0 = pci_read_config32(k8_f2, 0x94);
+		u32 dch1 = pci_read_config32(k8_f2, 0x194);
+		if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
+			value = pci_read_config32(k8_f2, 0x110);
+			if (extractbit(value, 4))  // ganged mode
+			vgainfo.ucUMAChannelNumber = 2;
+		}
+	}
+      
+	// processor type
+	if (is_family0Fh())
+		vgainfo.ulCPUCapInfo = 3;
+	if (is_family10h())
+		vgainfo.ulCPUCapInfo = 2;
+
+	/* HT speed */
+	value = pci_read_config8(nb_dev, 0xd1);
+	value = ht_freq_lookup [value] * 100;  // HT link frequency in MHz
+	vgainfo.ulHTLinkFreq = value * 100;    // HT frequency in units of 100 MHz
+	vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+
+	if (value <= 1800)
+		vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
+	else {
+		int sblink, cpuLnkFreqCap, nbLnkFreqCap;
+		value = pci_read_config32(k8_f0, 0x64);
+		sblink = extractbits(value, 8, 10);
+		cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
+		nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
+		if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
+		vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
+	}
+
+	/* HT width. */
+	value = pci_read_config8(nb_dev, 0xcb);
+	vgainfo.usMinDownStreamHTLinkWidth = 
+	vgainfo.usMaxDownStreamHTLinkWidth = 
+	vgainfo.usMinUpStreamHTLinkWidth = 
+	vgainfo.usMaxUpStreamHTLinkWidth =
+	vgainfo.usMinHTLinkWidth =
+	vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
+
+	if (is_family0Fh()) {
+		vgainfo.usUMASyncStartDelay = 322;
+		vgainfo.usUMADataReturnTime = 286;
+	}
+
+	if (is_family10h()) {
+		static u16 t0mult_lookup [] = {10, 50, 200, 2000};
+		int t0time, t0scale;
+		value = pci_read_config32(k8_f0, 0x16c);
+		t0time = extractbits(value, 0, 3);
+		t0scale = extractbits(value, 4, 5);
+		vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
+		vgainfo.usUMASyncStartDelay = 100;
+		if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
+			vgainfo.usUMADataReturnTime = 300;
+			vgainfo.usLinkStatusZeroTime = 6 * 100;   // 6us for GH in HT1 mode
+		}
+		else {
+			int lssel;
+			value = pci_read_config32(nb_dev, 0xac);
+			lssel = extractbits (value, 7, 8);
+			vgainfo.usUMADataReturnTime = 1300;
+			if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
+		}
+	}
+
+	/* Transfer the Table to VBIOS. */
+	pointer = (u32 *)&vgainfo;
+	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
+	{
+#if (CONFIG_GFXUMA == 1)
+		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
+#else
+		*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
+#endif
+		*(GpuF0MMReg+1) = *pointer++;
+	}
+
+	/* GFX_InitLate. */
+	{
+		u32 temp;
+		temp = pci_read_config8(dev, 0x4);
+		//temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
+		temp |= 1<<1|1<<2;
+		pci_write_config8(dev, 0x4, temp);
+
+		// if the GFX debug bar is writable, then it has
+		// been programmed and can be safely enabled now
+		temp = pci_read_config32(nb_dev, 0x8c);
+
+		// if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
+		// then enable gfx debug bar (set gxf_debug_decode_enable)
+		if (temp & 0x202)
+			temp |= (1 << 10);
+		pci_write_config32(nb_dev, 0x8c, temp);
+
+	}
+
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
+	/* NB_SetupMGMMIO. */
+
+	/* clear MMIO and CreativeMMIO. */
+	bpointer = (unsigned char *)MMIO;
+	for(i=0; i<sizeof(MMIO); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+	bpointer = (unsigned char *)CreativeMMIO;
+	for(i=0; i<sizeof(CreativeMMIO); i++)
+	{
+		*bpointer = 0;
+		bpointer++;
+	}
+
+	/* Set MMIO ranges in K8. */
+	/* Set MMIO TOM - 4G. */
+	SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
+	/* Set MMIO for VGA Legacy FB. */
+	SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
+
+	/* Set MMIO for non prefetchable P2P. */
+	temp = pci_read_config32(dev0x14, 0x20);
+	Base32 = (temp & 0x0fff0) << 8;
+	Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+	if(Base32 < Limit32)
+	{
+		Status = GetCreativeMMIO(&CreativeMMIO[0]);
+		if(Status != CIM_ERROR)
+			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+	}
+	/* Set MMIO for prefetchable P2P. */
+	if(Status != CIM_ERROR)
+	{
+		temp = pci_read_config32(dev0x14, 0x24);
+
+		Base32 = (temp & 0x0fff0) <<8;
+		Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
+		if(Base32 < Limit32)
+			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
+	}
+
+	FinalizeMMIO(&MMIO[0]);
+
+	ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
+	ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
+#endif
+
+	pci_dev_init(dev);
+
+	/* clk ind */
+	clkind_write(dev, 0x08, 0x01);
+	clkind_write(dev, 0x0C, 0x22);
+	clkind_write(dev, 0x0F, 0x0);
+	clkind_write(dev, 0x11, 0x0);
+	clkind_write(dev, 0x12, 0x0);
+	clkind_write(dev, 0x14, 0x0);
+	clkind_write(dev, 0x15, 0x0);
+	clkind_write(dev, 0x16, 0x0);
+	clkind_write(dev, 0x17, 0x0);
+	clkind_write(dev, 0x18, 0x0);
+	clkind_write(dev, 0x19, 0x0);
+	clkind_write(dev, 0x1A, 0x0);
+	clkind_write(dev, 0x1B, 0x0);
+	clkind_write(dev, 0x1C, 0x0);
+	clkind_write(dev, 0x1D, 0x0);
+	clkind_write(dev, 0x1E, 0x0);
+	clkind_write(dev, 0x26, 0x0);
+	clkind_write(dev, 0x27, 0x0);
+	clkind_write(dev, 0x28, 0x0);
+	clkind_write(dev, 0x5C, 0x0);
+}
+
+
+/*
+* Set registers in RS780 and CPU to enable the internal GFX.
+* Please refer to CIM source code and BKDG.
+*/
+
+static void rs780_internal_gfx_enable(device_t dev)
+{
+	u32 l_dword;
+	int i;
+	device_t nb_dev = dev_find_slot(0, 0);
+	msr_t sysmem;
+
+#if (CONFIG_GFXUMA == 0)
+	u32 FB_Start, FB_End;
+#endif
+
+	printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
+
+	sysmem = rdmsr(0xc001001a);
+	printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
+
+	/* The system top memory in 780. */
+	pci_write_config32(nb_dev, 0x90, sysmem.lo);
+	htiu_write_index(nb_dev, 0x30, 0);
+	htiu_write_index(nb_dev, 0x31, 0);
+
+	/* Disable external GFX and enable internal GFX. */
+	l_dword = pci_read_config32(nb_dev, 0x8c);
+	l_dword &= ~(1<<0);
+	l_dword |= 1<<1;
+	pci_write_config32(nb_dev, 0x8c, l_dword);
+
+	/* NB_SetDefaultIndexes */
+	pci_write_config32(nb_dev, 0x94, 0x7f);
+	pci_write_config32(nb_dev, 0x60, 0x7f);
+	pci_write_config32(nb_dev, 0xe0, 0);
+
+	/* NB_InitEarlyNB finished. */
+
+	/* LPC DMA Deadlock workaround? */
+	/* GFX_InitCommon*/
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	l_dword = pci_read_config32(k8_f0, 0x68);
+	l_dword &= ~(3 << 21);
+	l_dword |= (1 << 21);
+	pci_write_config32(k8_f0, 0x68, l_dword);
+
+	/* GFX_InitCommon. */
+	nbmc_write_index(nb_dev, 0x23, 0x00c00010);
+	set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
+	set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
+	set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
+
+#if (CONFIG_GFXUMA == 1)
+	/* GFX_InitUMA. */
+	/* Copy CPU DDR Controller to NB MC. */
+	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
+	for (i = 0; i < 12; i++)
+	{
+		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
+		nbmc_write_index(nb_dev, 0x30 + i, l_dword);
+	}
+
+	l_dword = pci_read_config32(k8_f2, 0x80);
+	nbmc_write_index(nb_dev, 0x3c, l_dword);
+	l_dword = pci_read_config32(k8_f2, 0x94);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
+	l_dword = pci_read_config32(k8_f2, 0x90);
+	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
+   if (is_family10h())
+   {
+	   for (i = 0; i < 12; i++)
+	   {
+		   l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
+		   nbmc_write_index(nb_dev, 0x3d + i, l_dword);
+	   }
+
+	   l_dword = pci_read_config32(k8_f2, 0x180);
+	   nbmc_write_index(nb_dev, 0x49, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x194);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
+	   l_dword = pci_read_config32(k8_f2, 0x190);
+	   set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
+
+	   l_dword = pci_read_config32(k8_f2, 0x110);
+	   nbmc_write_index(nb_dev, 0x4a, l_dword);
+	   l_dword = pci_read_config32(k8_f2, 0x114);
+	   nbmc_write_index(nb_dev, 0x4b, l_dword);
+	   l_dword = pci_read_config32(k8_f4, 0x44);
+	   set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
+	   l_dword = pci_read_config32(k8_f1, 0x40);
+	   nbmc_write_index(nb_dev, 0x4c, l_dword);
+	   l_dword = pci_read_config32(k8_f1, 0xf0);
+	   nbmc_write_index(nb_dev, 0x4d, l_dword);
+   }
+
+
+	/* Set UMA in the 780 side. */
+	/* UMA start address, size. */
+	/* The UMA starts at 0xC0000000 of internal RS780 address space
+	    [31:16] addr of last byte | [31:16] addr of first byte
+	*/
+	nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
+	nbmc_write_index(nb_dev, 0x11, uma_memory_base);
+	nbmc_write_index(nb_dev, 0x12, 0);
+	nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
+	/* GFX_InitUMA finished. */
+#else
+	/* GFX_InitSP. */
+	/* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
+
+	/* Enable Async mode. */
+	set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
+	set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
+	/* The last item in AsynchMclkTaskFileIndex. Why? */
+	/* MC_MPLL_CONTROL2. */
+	nbmc_write_index(nb_dev, 0x07, 0x40100028);
+	/* MC_MPLL_DIV_CONTROL. */
+	nbmc_write_index(nb_dev, 0x0b, 0x00000028);
+	/* MC_MPLL_FREQ_CONTROL. */
+	set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
+	/* MC_MPLL_CONTROL3. For PM. */
+	set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
+	/* MPLL_CAL_TRIGGER. */
+	set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
+	udelay(200); /* time is long enough? */
+	set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
+	set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
+	/* MCLK_SRC_USE_MPLL. */
+	set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
+
+	/* Pre Init MC. */
+	nbmc_write_index(nb_dev, 0x01, 0x88108280);
+	set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
+	nbmc_write_index(nb_dev, 0x04, 0x08881018);
+	nbmc_write_index(nb_dev, 0x05, 0x000000bb);
+	nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
+	nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
+	/* MCA_INIT_DLL_PM. */
+	set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
+	nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
+	nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
+	nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
+	nbmc_write_index(nb_dev, 0xb0, 0x88800130);
+	nbmc_write_index(nb_dev, 0xb1, 0x00000040);
+	nbmc_write_index(nb_dev, 0xb4, 0x41247000);
+	nbmc_write_index(nb_dev, 0xb5, 0x00066664);
+	nbmc_write_index(nb_dev, 0xb6, 0x00000022);
+	nbmc_write_index(nb_dev, 0xb7, 0x00000044);
+	nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
+	nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
+	nbmc_write_index(nb_dev, 0xba, 0x55555555);
+	nbmc_write_index(nb_dev, 0xc1, 0x00000000);
+	nbmc_write_index(nb_dev, 0xc2, 0x00000000);
+	nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
+	nbmc_write_index(nb_dev, 0xc4, 0x00066664);
+	nbmc_write_index(nb_dev, 0xc5, 0x00000000);
+	nbmc_write_index(nb_dev, 0xd2, 0x00000022);
+	nbmc_write_index(nb_dev, 0xd3, 0x00000044);
+	nbmc_write_index(nb_dev, 0xd6, 0x00050005);
+	nbmc_write_index(nb_dev, 0xd7, 0x00000000);
+	nbmc_write_index(nb_dev, 0xd8, 0x00700070);
+	nbmc_write_index(nb_dev, 0xd9, 0x00700070);
+	nbmc_write_index(nb_dev, 0xe0, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe1, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe8, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe9, 0x00200020);
+	nbmc_write_index(nb_dev, 0xe0, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe1, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe8, 0x00180018);
+	nbmc_write_index(nb_dev, 0xe9, 0x00180018);
+
+	/* Misc options. */
+	/* Memory Termination. */
+	set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
+	set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
+#if 0
+	/* Controller Termation. */
+	set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
+#endif
+
+	/* OEM Init MC. 667MHz. */
+	nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
+	nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
+	nbmc_write_index(nb_dev, 0xaa, 0x54400520);
+	nbmc_write_index(nb_dev, 0xab, 0x441460ff);
+	nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
+	set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
+	nbmc_write_index(nb_dev, 0xb2, 0x00000303);
+	set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
+	/* Do it later. */
+	/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
+
+	/* Init PM timing. */
+	for(i=0; i<4; i++)
+	{
+		l_dword = nbmc_read_index(nb_dev, 0xa0+i);
+		nbmc_write_index(nb_dev, 0xc8+i, l_dword);
+	}
+	for(i=0; i<4; i++)
+	{
+		l_dword = nbmc_read_index(nb_dev, 0xa8+i);
+		nbmc_write_index(nb_dev, 0xcc+i, l_dword);
+	}
+	l_dword = nbmc_read_index(nb_dev, 0xb1);
+	set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
+
+	/* Init MC FB. */
+	/* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
+	nbmc_write_index(nb_dev, 0x11, 0x40000000);
+	FB_Start = 0xc00 + 0x080;
+	FB_End = 0xc00 + 0x080;
+	nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
+	set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
+	nbmc_write_index(nb_dev, 0x0f, 0);
+	nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
+#endif
+
+	/* GFX_InitSP finished. */
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations pcie_ops = {
+	.read_resources = rs780_gfx_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = internal_gfx_pci_dev_init,	/* The option ROM initializes the device. rs780_gfx_init, */
+	.scan_bus = 0,
+	.enable = rs780_internal_gfx_enable,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * We should list all of them here.
+ * */
+static const struct pci_driver pcie_driver_780 __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
+};
+
+static const struct pci_driver pcie_driver_780c __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780m __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780mc __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
+};
+static const struct pci_driver pcie_driver_780e __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
+};
+static const struct pci_driver pcie_driver_785g __pci_driver = {
+	.ops = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
+};
+
+/* step 12 ~ step 14 from rpr */
+static void single_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
+
+	/* step 12 training, releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, 2);
+	result = PcieTrainPort(nb_dev, dev, 2);
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
+
+	/* step 13 Power Down Control */
+	/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+
+	/* step 13.a Link Training was NOT successful */
+	if (!result) {
+		set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
+		set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
+		if (cfg->gfx_tmds)
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
+		else {
+			nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
+			set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
+		}
+	} else {		/* step 13.b Link Training was successful */
+		set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
+		reg32 = nbpcie_p_read_index(dev, 0x29);
+		width = reg32 & 0xFF;
+		printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
+			break;
+		case 8:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
+
+	/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
+	set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
+	printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
+}
+
+static void dual_port_configuration(device_t nb_dev, device_t dev)
+{
+	u8 result, width;
+	u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
+	struct southbridge_amd_rs780_config *cfg =
+		    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.4.1.2 Dual Port Configuration */
+	set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
+	set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+
+	/* 5.7. Training for Device 2 */
+	/* 5.7.1. Releases hold training for GFX port 0 (device 2) */
+	PcieReleasePortTraining(nb_dev, dev, dev_ind);
+	/* 5.7.2- 5.7.9. PCIE Link Training Sequence */
+	result = PcieTrainPort(nb_dev, dev, dev_ind);
+
+	/* Power Down Control for Device 2 */
+	/* Link Training was NOT successful */
+	if (!result) {
+		/* Powers down all lanes for port A */
+		/* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
+		/* Note: I have to disable the slot where there isnt a device,
+		 * otherwise the system will hang. I dont know why. */
+		set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
+
+	} else {		/* step 16.b Link Training was successful */
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+		width = (reg32 >> 4) & 0x7;
+		printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
+		switch (width) {
+		case 1:
+		case 2:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
+			break;
+		case 4:
+			nbpcie_ind_write_index(nb_dev, 0x65,
+					       cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
+			break;
+		}
+	}
+}
+
+/* For single port GFX configuration Only
+* width:
+* 	000 = x16
+* 	001 = x1
+*	010 = x2
+*	011 = x4
+*	100 = x8
+*	101 = x12 (not supported)
+*	110 = x16
+*/
+static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
+{
+	u32 reg32;
+	device_t sb_dev;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* step 5.9.1.1 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+
+	/* step 5.9.1.2 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
+	/* step 5.9.1.3 */
+	set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
+	/* step 5.9.1.4 */
+	set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
+	/* step 5.9.2.4 */
+	if (0 == cfg->gfx_reconfiguration)
+		set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
+
+	/* step 5.9.1.5 */
+	do {
+		reg32 = nbpcie_p_read_index(dev, 0xa2);
+	}
+	while (reg32 & 0x100);
+
+	/* step 5.9.1.6 */
+	sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
+	do {
+		reg32 = pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg32 & VC_NEGOTIATION_PENDING);
+
+	/* step 5.9.1.7 */
+	reg32 = nbpcie_p_read_index(dev, 0xa2);
+	if (((reg32 & 0x70) >> 4) != 0x6) {
+		/* the unused lanes should be powered off. */
+	}
+
+	/* step 5.9.1.8 */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
+}
+
+/*
+* GFX Core initialization, dev2, dev3
+*/
+void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg32;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+		    nb_dev, dev, port);
+
+	/* GFX Core Initialization */
+	//if (port == 2) return;
+
+	/* step 2, TMDS, (only need if CMOS option is enabled) */
+	if (cfg->gfx_tmds) {
+	}
+
+#if 1				/* external clock mode */
+	/* table 5-22, 5.9.1. REFCLK */
+	/* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
+	 * REFCLK PAD can be driven by an external source. */
+	/* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
+
+	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+	/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+			       1 << 6 | 1 << 8 | 1 << 10);
+	reg32 = nbmisc_read_index(nb_dev, 0x28);
+	printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
+
+	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
+#else				/* internal clock mode */
+	/* table 5-23, 5.9.1. REFCLK */
+	/* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
+	 * REFCLK PAD can be driven by the SB REFCLK. */
+	/* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
+	 * REFCLK from an external source.*/
+	set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
+
+	/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
+	/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
+	/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
+	set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
+			       0);
+	reg32 = nbmisc_read_index(nb_dev, 0x28);
+	printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
+
+	/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
+	set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
+#endif
+
+	/* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
+	/* 5.9.3.1. Increases PLL BW for 6G operation.*/
+	/* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
+	/* skip */
+
+	/* step 5.9.4, reset the GFX link */
+	/* step 5.9.4.1 asserts both calibration reset and global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
+
+	/* step 5.9.4.2 de-asserts calibration reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
+
+	/* step 5.9.4.3 wait for at least 200us */
+	udelay(300);
+
+	/* step 5.9.4.4 de-asserts global reset */
+	set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
+
+	/* 5.9.5 Reset PCIE_GFX Slot */
+	/* It is done in mainboard.c */
+	set_pcie_reset();
+	mdelay(1);
+	set_pcie_dereset();
+
+	/* step 5.9.8 program PCIE memory mapped configuration space */
+	/* done by enable_pci_bar3() before */
+
+	/* step 7 compliance state, (only need if CMOS option is enabled) */
+	/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
+	if (cfg->gfx_compliance) {
+		/* force compliance */
+		set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
+		/* release hold training for device 2. GFX initialization is done. */
+		set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
+		dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
+		printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
+		return;
+	}
+
+	/* 5.9.12 Core Initialization. */
+	/* 5.9.12.1 sets RCB timeout to be 25ms */
+	/* 5.9.12.2. RCB Cpl timeout on link down. */
+	set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
+
+	/* step 5.9.12.3 disables slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
+
+	/* step 5.9.12.4 sets DMA payload size to 64 bytes */
+	set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
+	/* 5.9.12.5. Blocks DMA traffic during C3 state. */
+	set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+
+	/* 5.9.12.6. Disables RC ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
+
+	/* Enabels TLP flushing. */
+	/* Note: It is got from RS690. The system will hang without this action. */
+	set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+	/* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
+	set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
+
+	/* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+	/* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
+	set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
+	printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
+
+	/* 5.9.12.10 Sets the timer in Config state from 20us to */
+	/* 5.9.12.11 De-asserts RX_EN in L0s. */
+	/* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
+	 * recovery parameter when lane is in electrical idle in L0s.*/
+	set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
+
+	/* 5.9.12.13. Turns off offset calibration. */
+	/* 5.9.12.14. Enables Rx Clock gating in CDR */
+	set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
+
+	/* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
+	set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
+
+	/* 5.9.12.16. Lets PI use Electrical Idle from PHY when
+	 * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
+	set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
+
+	/* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+
+	/* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
+	 * acknowledged a request to go to L1. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+
+	/* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
+	set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
+
+	/* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
+	set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
+
+	/* 5.9.12.21. Sets Electrical Idle Threshold. */
+	set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
+
+	/* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
+	 * Only if CMOS Option in section. skip */
+
+	/* 5.9.12.23. Disables GEN2 capability of the device. */
+	set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+
+	/* 5.9.12.24.Disables advertising Upconfigure Support. */
+	set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+
+	/* 5.9.12.25. No comment in RPR. */
+	set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
+
+	/* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
+	 * speed are supported */
+	set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
+
+	/* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
+	if (get_nb_rev(nb_dev) == REV_RS780_A12)			/* A12 */
+		set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
+
+	/* 5.9.12.28 Hides and disables the completion timeout method. */
+	set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
+
+	/* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
+	/* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
+
+	/* 5.9.12.30. Set TX arbitration algorithm to round robin */
+	set_pcie_enable_bits(nb_dev, 0x1C,
+			     1 << 0 | 0x1F << 1 | 0x1F << 6,
+			     1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+	/* Single-port/Dual-port configureation. */
+	switch (cfg->gfx_dual_slot) {
+	case 0:
+		/* step 1, lane reversal (only need if build config option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+		}
+		printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+
+		printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+		if((dev->path.pci.devfn >> 3) == 2) {
+			single_port_configuration(nb_dev, dev);
+		} else {
+			set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+			printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
+		}
+
+		break;
+	case 1:
+		/* step 1, lane reversal (only need if build config option is enabled) */
+		if (cfg->gfx_lane_reversal) {
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+			set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+			set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+		}
+		printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+		/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+		/* AMD calls the configuration CrossFire */
+		set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+		printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+		printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+		dual_port_configuration(nb_dev, dev);
+		break;
+
+	case 2:
+
+		if(is_dev3_present()){
+			/* step 1, lane reversal (only need if CMOS option is enabled) */
+			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+			}
+			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+			/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+			/* AMD calls the configuration CrossFire */
+			set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+			printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+
+			printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+			dual_port_configuration(nb_dev, dev);
+
+		}else{
+			if (cfg->gfx_lane_reversal) {
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
+				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
+			}
+			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+
+			if((dev->path.pci.devfn >> 3) == 2)
+				single_port_configuration(nb_dev, dev);
+			else{
+				set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+				printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
+			    }
+		}
+
+	default:
+		printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
+		break;
+	}
+}

Copied: trunk/src/southbridge/amd/rs780/ht.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/ht.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_ht.c)
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "rs780.h"
+
+/* for UMA internal graphics */
+void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
+{
+	device_t cpu_f0;
+	u8 reg;
+
+	cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21);
+
+	reg = nbpcie_p_read_index(sb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(sb_dev, 0x10, reg);
+
+	reg = nbpcie_p_read_index(nb_dev, 0x10);
+	reg |= 0x100;		/* bit9=1 */
+	nbpcie_p_write_index(nb_dev, 0x10, reg);
+
+	/* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
+	 * Set this bit to avoid a deadlock condition. */
+	reg = htiu_read_index(nb_dev, 0x6);
+	reg |= 0x1000000;	/* bit26 */
+	htiu_write_index(nb_dev, 0x6, reg);
+}
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	u32 dword;
+
+	printk(BIOS_INFO, "pcie_init in rs780_ht.c\n");
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* System error enable */
+	dword |= (1 << 30);	/* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/*
+	 * 1 is APIC enable
+	 * 18 is enable nb to accept A4 interrupt request from SB.
+	 */
+	dword = pci_read_config32(dev, 0x4C);
+	dword |= 1 << 1 | 1 << 18;	/* Clear possible errors */
+	pci_write_config32(dev, 0x4C, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = pcie_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_RS780_HT,
+};

Copied: trunk/src/southbridge/amd/rs780/pcie.c (from r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_pcie.c)
@@ -0,0 +1,392 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <delay.h>
+#include "rs780.h"
+
+/*------------------------------------------------
+* Global variable
+------------------------------------------------*/
+PCIE_CFG AtiPcieCfg = {
+	PCIE_ENABLE_STATIC_DEV_REMAP,	/* Config */
+	0,			/* ResetReleaseDelay */
+	0,			/* Gfx0Width */
+	0,			/* Gfx1Width */
+	0,			/* GfxPayload */
+	0,			/* GppPayload */
+	0,			/* PortDetect, filled by GppSbInit */
+	0,			/* PortHp */
+	0,			/* DbgConfig */
+	0,			/* DbgConfig2 */
+	0,			/* GfxLx */
+	0,			/* GppLx */
+	0,			/* NBSBLx */
+	0,			/* PortSlotInit */
+	0,			/* Gfx0Pwr */
+	0,			/* Gfx1Pwr */
+	0			/* GppPwr */
+};
+
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
+static void ValidatePortEn(device_t nb_dev);
+
+static void ValidatePortEn(device_t nb_dev)
+{
+}
+
+/*****************************************************************
+* Compliant with CIM_33's PCIEPowerOffGppPorts
+* Power off unused GPP lines
+*****************************************************************/
+static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 reg;
+	u16 state_save;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+	u8 state = cfg->port_enable;
+
+	if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
+		state &= AtiPcieCfg.PortDetect;
+	state = ~state;
+	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
+	state_save = state << 17;
+	state &= !(AtiPcieCfg.PortHp);
+	reg = nbmisc_read_index(nb_dev, 0x0c);
+	reg |= state;
+	nbmisc_write_index(nb_dev, 0x0c, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x08);
+	reg |= state_save;
+	nbmisc_write_index(nb_dev, 0x08, reg);
+
+	if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
+	    && !(AtiPcieCfg.
+		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
+			   PCIE_GFX_COMPLIANCE))) {
+	}
+	/* step 3 Power Down Control for Southbridge */
+	reg = nbpcie_p_read_index(dev, 0xa2);
+
+	switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
+	case 1:
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+		break;
+	case 2:
+		nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+		break;
+	default:
+		break;
+	}
+}
+
+/**********************************************************************
+**********************************************************************/
+static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.5.7.1-3 enables GPP reconfiguration */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg |=
+	    (RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
+	     RECONFIG_GPPSB_ATOMIC_RESET);
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* 5.5.7.4a. De-asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg |= 1 << 31;
+	nbmisc_write_index(nb_dev, 0x66, reg);
+	/* 5.5.7.4b. sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x67);
+	reg &= 0xFFFFff0f;		/* clean */
+	reg |= cfg->gppsb_configuration << 4;
+	nbmisc_write_index(nb_dev, 0x67, reg);
+
+#if 1
+	/* NOTE:
+	 * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way,
+	 * a x4 device in port B (dev 4) of Configuration B can only be detected
+	 * as x1, instead of x4. When the port B is being trained, the
+	 * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. We have
+	 * to set the PCIEIND:0x65 as 0xE0E0 and reset the slot. Then the card
+	 * seems to work in x1 mode.
+	 * In the 2nd way below, we do the 5 & 6 before 4c. it conforms the
+	 * CIMx 4.3.0. It conflicts with RPR. But based on the test result I've
+	 * made so far, I haven't found any mistake.
+	 */
+	/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg &= ~(1 << 31);
+	nbmisc_write_index(nb_dev, 0x66, reg);
+
+	/* 5.5.7.5-6. read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+#else
+	/* 5.5.7.5-6. read bit14 and write back its inverst value */
+	reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
+	reg ^= RECONFIG_GPPSB_GPPSB;
+	nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
+
+	/* 5.5.7.4c. Asserts STRAP_BIF_all_valid for PCIE-GPPSB core */
+	reg = nbmisc_read_index(nb_dev, 0x66);
+	reg &= ~(1 << 31);
+	nbmisc_write_index(nb_dev, 0x66, reg);
+#endif
+	/* 5.5.7.7. delay 1ms */
+	mdelay(1);
+
+	/* 5.5.7.8. waits until SB has trained to L0, poll for bit0-5 = 0x10 */
+	do {
+		reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
+		reg &= 0x3f;	/* remain LSB [5:0] bits */
+	} while (LC_STATE_RECONFIG_GPPSB != reg);
+
+	/* 5.5.7.9.ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
+	do {
+		reg =
+		    pci_ext_read_config32(nb_dev, sb_dev,
+					  PCIE_VC0_RESOURCE_STATUS);
+	} while (reg & VC_NEGOTIATION_PENDING);
+}
+
+static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	/* 5.6.2.1. De-asserts STRAP_BIF_all_valid for PCIE-GPP core */
+	reg = nbmisc_read_index(nb_dev, 0x22);
+	reg |= 1 << 14;
+	nbmisc_write_index(nb_dev, 0x22, reg);
+	/* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */
+	reg = nbmisc_read_index(nb_dev, 0x2D);
+	reg &= ~(0xF << 7);		/* clean */
+	reg |= cfg->gpp_configuration << 7;
+	nbmisc_write_index(nb_dev, 0x2D, reg);
+	/* 5.6.2.3. Asserts STRAP_BIF_all_valid for PCIE-GPP core */
+	reg = nbmisc_read_index(nb_dev, 0x22);
+	reg &= ~(1 << 14);
+	nbmisc_write_index(nb_dev, 0x22, reg);
+}
+
+/*****************************************************************
+* The rs780 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
+* Space to a 256MB range within the first 4GB of addressable memory.
+*****************************************************************/
+void enable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
+	set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
+
+	pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS);	/* PCIEMiscInit */
+	pci_write_config32(nb_dev, 0x20, 0x00000000);
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
+	ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************************************
+* We should disable bar3 when we want to exit rs780_enable, because bar3 will be
+* remapped in set_resource later.
+*****************************************************************/
+void disable_pcie_bar3(device_t nb_dev)
+{
+	printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
+	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
+	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3. */
+	set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0);	/* disable bar3 decode */
+	ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEGPPInit
+* nb_dev:
+*	root bridge struct
+* dev:
+*	p2p bridge struct
+* port:
+*	p2p bridge number, 4-10
+*****************************************/
+void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+{
+	u32 gfx_gpp_sb_sel;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+	printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev->path.pci.devfn, dev->path.pci.devfn, port);
+
+	gfx_gpp_sb_sel = port >= 4 && port <= 8 ?
+				PCIE_CORE_INDEX_GPPSB :		/* 4,5,6,7,8 */
+				PCIE_CORE_INDEX_GPP;		/* 9,10 */
+	/* init GPP core */
+	/* 5.10.8.3. Disable slave ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8,
+			     1 << 8);
+	/* 5.10.8.7. PCIE initialization 5.10.2: rpr 2.12*/
+	set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0);	/* no description in datasheet. */
+
+	/* init GPPSB port. rpr 5.10.8 */
+	/* 5.10.8.1-5.10.8.2. Sets RCB timeout to be 100ms/4=25ms by setting bits[18:16] to 3 h4
+	 * and shortens the enumeration timer by setting bit[19] to 1
+	 */
+	set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0x4 << 16 | 1 << 19);
+	/* 5.10.8.4. Sets DMA payload size to 64 bytes. */
+	set_pcie_enable_bits(nb_dev, 0x10 | gfx_gpp_sb_sel, 7 << 10, 4 << 10);
+	/* 5.10.8.6. Disable RC ordering logic */
+	set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 9, 1 << 9);
+	/* 5.10.8.7. Ignores DLLs druing L1 */
+	set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0);
+	/* 5.10.8.8. Prevents LCto go from L0 to Rcv_L0s if L1 is armed. */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+	/* 5.10.8.9. Sets timer in Config state from 20us to 1us.
+	 * 5.10.8.10. De-asserts RX_EN in L0s
+	 * 5.10.8.11. Enables de-assertion of PG2RX_CR_EN to lock clock recovery parameter when .. */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 <<23 | 1 << 19 | 1 << 28);
+	/* 5.10.8.12. Turns off offset calibration */
+	/* 5.10.8.13. Enables Rx  Clock gating in CDR */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 14 | 1 << 26, 1 << 14 | 1 << 26); /* 4,5,6,7 */
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x24, 1 << 29 | 1 << 28, 1 << 29 | 1 << 28); /* 9,10 */
+	/* 5.10.8.14. Sets number of TX Clocks to drain TX Pipe to 3 */
+	set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
+	/* 5.10.8.15. empty */
+	/* 5.10.8.16. P_ELEC_IDLE_MODE */
+	set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 0x3 << 14, 0x2 << 14);
+	/* 5.10.8.17. LC_BLOCK_EL_IDLE_IN_L0 */
+	set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
+	/* 5.10.8.18. LC_DONT_GO_TO_L0S_IFL1_ARMED */
+	set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
+	/* 5.10.8.19. RXP_REALIGN_ON_EACH_TSX_OR_SKP */
+	set_pcie_enable_bits(nb_dev, 0x40 | gfx_gpp_sb_sel, 1 << 28, 0 << 28);
+	/* 5.10.8.20. Bypass lane de-skew logic if in x1 */
+	set_pcie_enable_bits(nb_dev, 0xC2 | gfx_gpp_sb_sel, 1 << 14, 1 << 14);
+	/* 5.10.8.21. sets electrical idle threshold. */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x6A, 3 << 22, 2 << 22);
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x24, 3 << 16, 2 << 16);
+
+	/* 5.10.8.22. Disable GEN2 */
+	/* TODO: should be 2 seperated cases. */
+	set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 5, 0 << 5);
+	set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 31, 0 << 31);
+	set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 5, 0 << 5);
+	/* 5.10.8.23. Disables GEN2 capability of the device. RPR says enable? No! */
+	set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
+	/* 5.10.8.24. Disable advertising upconfigure support. */
+	set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
+	/* 5.10.8.25-26. STRAP_BIF_DSN_EN */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB)
+		set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 19, 0 << 19);
+	else
+		set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 3, 0 << 3);
+	/* 5.10.8.27-28. */
+	set_pcie_enable_bits(nb_dev, 0xC1 | gfx_gpp_sb_sel, 1 << 0 | 1 << 2, 1 << 0 | 0 << 2);
+	/* 5.10.8.29. Uses the bif_core de-emphasis strength by default. */
+	if (gfx_gpp_sb_sel == PCIE_CORE_INDEX_GPPSB) {
+		set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10, 1 << 10);
+		set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 29, 1 << 29);
+	}
+	else {
+		set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 30, 1 << 30);
+	}
+	/* 5.10.8.30. Set TX arbitration algorithm to round robin. */
+	set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel,
+			     1 << 0 | 0x1F << 1 | 0x1F << 6,
+			     1 << 0 | 0x04 << 1 | 0x04 << 6);
+
+	/* check compliance rpr step 2.1*/
+	if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
+		u32 tmp;
+		tmp = nbmisc_read_index(nb_dev, 0x67);
+		tmp |= 1 << 3;
+		nbmisc_write_index(nb_dev, 0x67, tmp);
+	}
+
+	/* step 5: dynamic slave CPL buffer allocation. Disable it, otherwise linux hangs. Why? */
+	/* set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 11, 1 << 11); */
+
+	/* step 5a: Training for GPP devices */
+	/* init GPP */
+	switch (port) {
+	case 4:		/* GPP */
+	case 5:
+	case 6:
+	case 7:
+	case 9:
+	case 10:
+		/* 5.10.8.5. Blocks DMA traffic during C3 state */
+		set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
+		/* Enabels TLP flushing */
+		set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
+
+		/* check port enable */
+		if (cfg->port_enable & (1 << port)) {
+			PcieReleasePortTraining(nb_dev, dev, port);
+			if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
+				u8 res = PcieTrainPort(nb_dev, dev, port);
+				printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
+				if (res) {
+					AtiPcieCfg.PortDetect |= 1 << port;
+				}
+			}
+		}
+		break;
+	case 8:		/* SB */
+		break;
+	}
+	PciePowerOffGppPorts(nb_dev, dev, port);
+}
+
+/*****************************************
+* Compliant with CIM_33's PCIEConfigureGPPCore
+*****************************************/
+void config_gpp_core(device_t nb_dev, device_t sb_dev)
+{
+	u32 reg;
+	struct southbridge_amd_rs780_config *cfg =
+	    (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
+
+	reg = nbmisc_read_index(nb_dev, 0x20);
+	if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
+		reg &= 0xfffffffd;	/* set bit1 = 0 */
+	else
+		reg |= 0x2;	/* set bit1 = 1 */
+	nbmisc_write_index(nb_dev, 0x20, reg);
+
+	reg = nbmisc_read_index(nb_dev, 0x67);	/* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
+	if (cfg->gppsb_configuration != ((reg >> 4) & 0xf))
+		switching_gppsb_configurations(nb_dev, sb_dev);
+	reg = nbmisc_read_index(nb_dev, 0x2D);	/* get STRAP_BIF_LINK_CONFIG_GPP at bit 7-10 */
+	if (cfg->gpp_configuration != ((reg >> 7) & 0xf))
+		switching_gpp_configurations(nb_dev, sb_dev);
+	ValidatePortEn(nb_dev);
+}

Copied: trunk/src/southbridge/amd/rs780/rev.h (from r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/rs780/rev.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/rs780/rs780_rev.h)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __RS780_REV_H__
+#define __RS780_REV_H__
+
+#define	REV_RS780_A11	0
+#define	REV_RS780_A12	1
+#define	REV_RS780_A13	2
+
+#endif	/* __RS780_REV_H__ */

Modified: trunk/src/southbridge/amd/rs780/rs780.h
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780.h	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/rs780/rs780.h	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <device/pci_ids.h>
 #include "chip.h"
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBMISC_INDEX 	0x60
 #define NBHTIU_INDEX 	0x94

Modified: trunk/src/southbridge/amd/sb600/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb600/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb600/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,11 +1,11 @@
 driver-y += sb600.c
-driver-y += sb600_usb.c
-driver-y += sb600_lpc.c
-driver-y += sb600_sm.c
-driver-y += sb600_ide.c
-driver-y += sb600_sata.c
-driver-y += sb600_hda.c
-driver-y += sb600_ac97.c
-driver-y += sb600_pci.c
-ramstage-y += sb600_reset.c
-romstage-y += sb600_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += ac97.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c

Copied: trunk/src/southbridge/amd/sb600/ac97.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_ac97.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ac97audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+/*	.enable           = sb600_enable, */
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ac97audio_driver __pci_driver = {
+	.ops = &ac97audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_ACI,
+};
+
+static struct device_operations ac97modem_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+/*	.enable           = sb600_enable, */
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ac97modem_driver __pci_driver = {
+	.ops = &ac97modem_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_MCI,
+};

Modified: trunk/src/southbridge/amd/sb600/bootblock.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb600/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/amd/sb600/sb600_enable_rom.c"
+#include "southbridge/amd/sb600/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied and modified: trunk/src/southbridge/amd/sb600/early_setup.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -20,7 +20,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */

Copied: trunk/src/southbridge/amd/sb600/enable_rom.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_enable_rom.c)
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/*
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The SB600 power-on default is to map 256K ROM space.
+ *
+ * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
+ */
+static void sb600_enable_rom(void)
+{
+	u8 reg8;
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
+				       PCI_DEVICE_ID_ATI_SB600_LPC), 0);
+
+	/* Decode variable LPC ROM address ranges 1 and 2. */
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= (1 << 3) | (1 << 4);
+	pci_write_config8(dev, 0x48, reg8);
+
+	/* LPC ROM address range 1: */
+	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
+	pci_write_config16(dev, 0x68, 0x000e);
+	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+	pci_write_config16(dev, 0x6a, 0x000f);
+
+	/* LPC ROM address range 2: */
+	/*
+	 * Enable LPC ROM range start at:
+	 * 0xfff8(0000): 512KB
+	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
+	 */
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	/* Enable LPC ROM range end at 0xffff(ffff). */
+	pci_write_config16(dev, 0x6e, 0xffff);
+}

Copied: trunk/src/southbridge/amd/sb600/enable_usbdebug.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/enable_usbdebug.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c)
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "sb600.h"
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+	/* TODO: Allow changing the physical USB port used as Debug Port. */
+}
+
+void sb600_enable_usbdebug(unsigned int port)
+{
+	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+
+	/* Select the requested physical USB port (1-15) as the Debug Port. */
+	set_debug_port(port);
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+}

Copied: trunk/src/southbridge/amd/sb600/hda.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/hda.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_hda.c)
@@ -0,0 +1,331 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "sb600.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 dword;
+	int count;
+
+	/* Write (val & ~mask) to port */
+	val &= mask;
+	dword = read32(port);
+	dword &= ~mask;
+	dword |= val;
+	write32(port, dword);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		dword = read32(port);
+		dword &= mask;
+	} while ((dword != val) && --count);
+
+	/* Timeout occurred */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static u32 codec_detect(u32 base)
+{
+	u32 dword;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Delay for 1 ms since the BKDG does */
+	mdelay(1);
+
+	/* Read in Codec location (BAR + 0xe)[3..0]*/
+	dword = read32(base + 0xe);
+	dword &= 0x0F;
+	if (!dword)
+		goto no_codec;
+
+	return dword;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "No codec!\n");
+	return 0;
+}
+
+static u32 cim_verb_data[] = {
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+/* 1 */
+	0x01571c12,
+	0x01571d10,
+	0x01571e01,
+	0x01571f01,
+/* 2 */
+	0x01671c11,
+	0x01671d60,
+	0x01671e01,
+	0x01671f01,
+/* 3 */
+	0x01771c14,
+	0x01771d20,
+	0x01771e01,
+	0x01771f01,
+/* 4 */
+	0x01871c30,
+	0x01871d90,
+	0x01871ea1,
+	0x01871f01,
+/* 5 */
+	0x01971cf0,
+	0x01971d11,
+	0x01971e11,
+	0x01971f41,
+/* 6 */
+	0x01a71c80,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+/* 7 */
+	0x01b71cf0,
+	0x01b71d11,
+	0x01b71e11,
+	0x01b71f41,
+/* 8 */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+/* 9 */
+	0x01d71cf0,
+	0x01d71d11,
+	0x01d71e11,
+	0x01d71f41,
+/* 10 */
+	0x01e71c50,
+	0x01e71d11,
+	0x01e71e44,
+	0x01e71f01,
+/* 11 */
+	0x01f71c60,
+	0x01f71d61,
+	0x01f71ec4,
+	0x01f71f01,
+};
+
+static u32 find_verb(u32 viddid, u32 ** verb)
+{
+	device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
+	struct southbridge_amd_sb600_config *cfg =
+	    (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
+	printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev));
+	printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid);
+	printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid);
+	if (!cfg)
+		return 0;
+	if (viddid != cfg->hda_viddid)
+		return 0;
+	*verb = (u32 *) cim_verb_data;
+	return sizeof(cim_verb_data) / sizeof(u32);
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 dword=read32(base +  HDA_ICII_REG);
+		if (!(dword & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+static int wait_for_valid(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		u32 dword = read32(base + HDA_ICII_REG);
+		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return 1;
+}
+
+static void codec_init(u32 base, int addr)
+{
+	u32 dword;
+	u32 *verb;
+	u32 verb_size;
+	int i;
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	dword = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, dword);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	dword = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
+	verb_size = find_verb(dword, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "No verb!\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "verb loaded!\n");
+}
+
+static void codecs_init(u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(base, i);
+	}
+}
+
+static void hda_init(struct device *dev)
+{
+	u8 byte;
+	u32 dword;
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	device_t sm_dev;
+
+	/* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
+	pm_iowrite(0x59, 0xB);
+
+	/* Find the SMBus */
+	/* FIXME: Need to find out why the call below crashes. */
+	/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB600_SM, 0);*/
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
+	pci_write_config32(sm_dev, 0xf8, 0x00);
+	pci_write_config8(sm_dev, 0xfc, 0xAA);
+	/* Set INTA - SMBus 0x63 [2..0] */
+	byte = pci_read_config8(sm_dev, 0x63);
+	byte &= ~0x7;
+	byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
+	pci_write_config8(sm_dev, 0x63, byte);
+
+	/* Program the 2C to 0x437b1002 */
+	dword = 0x437b1002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* Read in BAR */
+	/* Is this right? HDA allows for a 64-bit BAR
+	 * but this is only setup for a 32-bit one
+	 */
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations hda_audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	/*.enable           = sb600_enable, */
+	.init = hda_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver hdaaudio_driver __pci_driver = {
+	.ops = &hda_audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_HDA,
+};

Copied: trunk/src/southbridge/amd/sb600/ide.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_ide.c)
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static void ide_init(struct device *dev)
+{
+	/* Enable ide devices so the linux ide driver will work */
+	u32 dword;
+	u8 byte;
+
+	/* RPR10.1 disable MSI */
+	dword = pci_read_config32(dev, 0x70);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x70, dword);
+
+	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
+	byte = pci_read_config8(dev, 0x54);
+	byte |= 0xf;
+	pci_write_config8(dev, 0x54, byte);
+
+	/* Enable I/O Access&& Bus Master */
+	dword = pci_read_config16(dev, 0x4);
+	dword |= 1 << 2;
+	pci_write_config16(dev, 0x4, dword);
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.scan_bus = 0,
+	/* .enable           = sb600_enable, */
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_IDE,
+};

Copied: trunk/src/southbridge/amd/sb600/lpc.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_lpc.c)
@@ -0,0 +1,225 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "sb600.h"
+
+static void lpc_init(device_t dev)
+{
+	u8 byte;
+	u32 dword;
+	device_t sm_dev;
+
+	/* Enable the LPC Controller */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	dword = pci_read_config32(sm_dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(sm_dev, 0x64, dword);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* RPR 7.2 Enable DMA transaction on the LPC bus */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 7.3 Disable the timeout mechanism on LPC */
+	byte = pci_read_config8(dev, 0x48);
+	byte &= ~(1 << 7);
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 7.5 Disable LPC MSI Capability */
+	byte = pci_read_config8(dev, 0x78);
+	byte &= ~(1 << 1);
+	pci_write_config8(dev, 0x78, byte);
+
+}
+
+static void sb600_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+static void sb600_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+					printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		pci_write_config16(dev, 0x64, reg_var[0]);
+		break;
+	}
+}
+
+static void sb600_lpc_enable_resources(device_t dev)
+{
+	pci_dev_enable_resources(dev);
+	sb600_lpc_enable_childrens_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations lpc_ops = {
+	.read_resources = sb600_lpc_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = sb600_lpc_enable_resources,
+	.init = lpc_init,
+	.scan_bus = scan_static_bus,
+	/* .enable           = sb600_enable, */
+	.ops_pci = &lops_pci,
+};
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_LPC,
+};

Copied: trunk/src/southbridge/amd/sb600/pci.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_pci.c)
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb600.h"
+
+static void pci_init(struct device *dev)
+{
+	u32 dword;
+	u16 word;
+	u8 byte;
+
+	/* RPR 4.1 Enables the PCI-bridge subtractive decode */
+	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR4.2 PCI-bridge upstream dual address window */
+	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR 4.3 PCI bus 64-byte DMA read access */
+	/* Enhance the PCI bus DMA performance */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 4;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
+	/* The size of the writes will be set in the Cacheline Register */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 1;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
+	pci_write_config8(dev, 0x0D, 0x40);
+	pci_write_config8(dev, 0x1B, 0x40);
+
+	/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 6;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 4.8 Adjusts the GNT# de-assertion time */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 4.9 Fast Back to Back transactions support */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 2;
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 4.10 Enable Lock Operation */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 3;
+	pci_write_config8(dev, 0x48, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 4.11 Enable additional optional PCI clock */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 8;
+	pci_write_config16(dev, 0x64, word);
+
+	/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
+	byte = pci_read_config8(dev, 0x64);
+	byte &= 0xcf;
+	pci_write_config8(dev, 0x64, byte);
+
+	/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 18);
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.13 Enable One-Prefetch-Channel Mode */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 4.15 Disable PCIB MSI Capability */
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 3);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* rpr4.16 Adjusting CLKRUN# */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 15);
+	pci_write_config32(dev, 0x64, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
+	/* .enable           = sb600_enable, */
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_PCI,
+};

Copied: trunk/src/southbridge/amd/sb600/reset.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_reset.c)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <reset.h>
+
+#include "northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/amd/sb600/sata.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_sata.c)
@@ -0,0 +1,265 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "sb600.h"
+
+static int sata_drive_detect(int portnum, u16 iobar)
+{
+	u8 byte, byte2;
+	int i = 0;
+	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
+		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
+		((byte2 & 0x88) != 0)) {
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
+		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+			/* This will happen at the first iteration of this loop
+			 * if the first SATA port is unpopulated and the
+			 * second SATA port is populated.
+			 */
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
+				"retrying init\n", i * 10);
+			return 1;
+		} else
+			printk(BIOS_SPEW, "drive detection not yet completed, "
+				"waiting...\n");
+		mdelay(10);
+		i++;
+	}
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
+	return 0;
+}
+
+static void sata_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u32 sata_bar5;
+	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+	int i, j;
+
+	struct southbridge_ati_sb600_config *conf;
+	conf = dev->chip_info;
+
+	device_t sm_dev;
+	/* SATA SMBus Disable */
+	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Disable SATA SMBUS */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 1);
+	/* Enable SATA and power saving */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 0);
+	byte |= (1 << 5);
+	pci_write_config8(sm_dev, 0xad, byte);
+	/* Set the interrupt Mapping to INTG# */
+	byte = pci_read_config8(sm_dev, 0xaf);
+	byte = 0x6 << 2;
+	pci_write_config8(sm_dev, 0xaf, byte);
+
+	/* get base address */
+	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
+	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
+	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
+	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
+	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
+
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+
+	/* Program the 2C to 0x43801002 */
+	dword = 0x43801002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* SERR-Enable */
+	word = pci_read_config16(dev, 0x04);
+	word |= (1 << 8);
+	pci_write_config16(dev, 0x04, word);
+
+	/* Dynamic power saving */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Set SATA Operation Mode, Set to IDE mode */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 0);
+	byte |= (1 << 4);
+	pci_write_config8(dev, 0x40, byte);
+
+	dword = 0x01018f00;
+	pci_write_config32(dev, 0x8, dword);
+
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Enable the SATA watchdog counter */
+	byte = pci_read_config8(dev, 0x44);
+	byte |= (1 << 0);
+	pci_write_config8(dev, 0x44, byte);
+
+	/* Program the watchdog counter to 0x10 */
+	byte = 0x10;
+	pci_write_config8(dev, 0x46, byte);
+
+	/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
+	word = 0x2c00;
+	pci_write_config16(dev, 0x86, word);
+
+	/* RPR6.5 Program the Phy Tuning4Ports */
+	dword = 0x00B401D6;
+	pci_write_config32(dev, 0x88, dword);
+	pci_write_config32(dev, 0x8c, dword);
+	pci_write_config32(dev, 0x90, dword);
+	pci_write_config32(dev, 0x94, dword);
+
+	byte = 0xB8;
+	pci_write_config8(dev, 0xA5, byte);
+	pci_write_config8(dev, 0xAD, byte);
+	pci_write_config8(dev, 0xB5, byte);
+	pci_write_config8(dev, 0xBD, byte);
+
+	/* RPR 6.8  */
+	word = pci_read_config16(dev, 0x42);
+	word |= 1 << 7;
+	pci_write_config16(dev, 0x42, word);
+	/* RPR 6.9  */
+	dword = pci_read_config32(dev, 0x40);
+	dword |= 1 << 25;
+	pci_write_config32(dev, 0x40, dword);
+
+	/* Enable the I/O, MM, BusMaster access for SATA */
+	byte = pci_read_config8(dev, 0x4);
+	byte |= 7 << 0;
+	pci_write_config8(dev, 0x4, byte);
+
+	/* RPR6.6 SATA drive detection. */
+	/* Use BAR5+0x128,BAR0 for Primary Slave */
+	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+	/* Use BAR5+0x228,BAR2 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
+
+	for (i = 0; i < 4; i++) {
+		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+		byte &= 0xF;
+
+		if( byte == 0x1 ) {
+			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
+			/* Try to do something about it. */
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
+
+			/* Read in Port-N Serial ATA Control Register */
+			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+
+			/* Set Reset Bit and 1.5g bit */
+			byte |= 0x11;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Clear Reset Bit */
+			byte &= ~0x01;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Reread status */
+			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+			byte &= 0xF;
+		}
+
+		if (byte == 0x3) {
+			for (j = 0; j < 10; j++) {
+				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
+					break;
+			}
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master",
+					(j == 10) ? "not " : "",
+					(j == 10) ? j : j + 1);
+		} else {
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master", i);
+		}
+	}
+
+	/* Below is CIM InitSataLateFar */
+	/* Enable interrupts from the HBA  */
+	byte = read8(sata_bar5 + 0x4);
+	byte |= 1 << 1;
+	write8((sata_bar5 + 0x4), byte);
+
+	/* Clear error status */
+	write32((sata_bar5 + 0x130), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x230), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+
+	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+	/* word = 0x0000; */
+	/* word = pm_ioread(0x28); */
+	/* byte = pm_ioread(0x29); */
+	/* word |= byte<<8; */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
+	/* write32(word, 0x80000000); */
+}
+
+static struct pci_operations lops_pci = {
+	/* .set_subsystem = pci_dev_set_subsystem, */
+};
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	/* .enable           = sb600_enable, */
+	.init = sata_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_SATA,
+};

Copied and modified: trunk/src/southbridge/amd/sb600/sm.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_sm.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_sm.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/sm.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 

Copied and modified: trunk/src/southbridge/amd/sb600/smbus.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb600/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "sb600_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {

Copied: trunk/src/southbridge/amd/sb600/smbus.h (from r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_smbus.h)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SB600_SMBUS_H
+#define SB600_SMBUS_H
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+#define AX_INDXC  0
+#define AX_INDXP  1
+#define AXCFG     2
+#define ABCFG     3
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx(0, (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)	\
+	alink_ax_indx(1, (reg), (mask), (val))
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+
+#endif

Copied: trunk/src/southbridge/amd/sb600/usb.c (from r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb600/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb600/sb600_usb.c)
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <usbdebug.h>
+#include <arch/io.h>
+#include "sb600.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+
+	/* Enable OHCI0-4 and EHCI Controllers */
+	device_t sm_dev;
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	byte = pci_read_config8(sm_dev, 0x68);
+	byte |= 0x3F;
+	pci_write_config8(sm_dev, 0x68, byte);
+
+	/* RPR 5.2 Enables the USB PME Event,Enable USB resume support */
+	byte = pm_ioread(0x61);
+	byte |= 1 << 6;
+	pm_iowrite(0x61, byte);
+	byte = pm_ioread(0x65);
+	byte |= 1 << 2;
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.3 Support USB device wakeup from the S4/S5 state */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 0);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.6 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
+	byte = pm_ioread(0x65);
+	byte |= (1 << 4);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 5.11 Disable OHCI MSI Capability */
+	word = pci_read_config16(dev, 0x40);
+	word |= (0x1F << 8);
+	pci_write_config16(dev, 0x40, word);
+
+	/* RPR 5.8 Disable the OHCI Dynamic Power Saving feature  */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR 5.12 Enable prevention of OHCI accessing the invalid system memory address range */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 15;
+	pci_write_config16(dev, 0x50, word);
+
+	/* RPR 5.15 Disable SMI handshake in between USB and ACPI for USB legacy support. */
+	/* The BIOS should always set this bit to prevent the malfunction on USB legacy keyboard/mouse support */
+	word = pci_read_config16(dev, 0x50);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x50, word);
+}
+
+static void usb_init2(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u32 usb2_bar0;
+	/* dword = pci_read_config32(dev, 0xf8); */
+	/* dword |= 40; */
+	/* pci_write_config32(dev, 0xf8, dword); */
+
+	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+
+	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
+	dword = 0x00020F00;
+	write32(usb2_bar0 + 0xC0, dword);
+
+	/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
+	dword = 0x00200040;
+	write32(usb2_bar0 + 0xA4, dword);
+
+	/* RPR5.9 Disable the EHCI Dynamic Power Saving feature */
+	word = read16(usb2_bar0 + 0xBC);
+	word &= ~(1 << 12);
+	write16(usb2_bar0 + 0xBC, word);
+
+	/* RPR5.10 Disable EHCI MSI support */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR5.13 Disable C3 time enhancement feature */
+	dword = pci_read_config32(dev, 0x50);
+	dword &= ~(1 << 28);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */
+	byte = pci_read_config8(dev, 0x54);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x54, byte);
+}
+
+static void usb_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	/*.enable           = sb600_enable, */
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_0_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_0,
+};
+static const struct pci_driver usb_1_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_1,
+};
+static const struct pci_driver usb_2_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_2,
+};
+static const struct pci_driver usb_3_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_3,
+};
+static const struct pci_driver usb_4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB_4,
+};
+
+static struct device_operations usb_ops2 = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init2,
+	/*.enable           = sb600_enable, */
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_5_driver __pci_driver = {
+	.ops = &usb_ops2,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB600_USB2,
+};
+

Modified: trunk/src/southbridge/amd/sb700/Makefile.inc
==============================================================================
--- trunk/src/southbridge/amd/sb700/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/amd/sb700/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,10 +1,10 @@
 driver-y += sb700.c
-driver-y += sb700_usb.c
-driver-y += sb700_lpc.c
-driver-y += sb700_sm.c
-driver-y += sb700_ide.c
-driver-y += sb700_sata.c
-driver-y += sb700_hda.c
-driver-y += sb700_pci.c
-ramstage-y += sb700_reset.c
-romstage-y += sb700_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c

Copied and modified: trunk/src/southbridge/amd/sb700/early_setup.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_early_setup.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_early_setup.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -23,7 +23,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x6000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */

Copied: trunk/src/southbridge/amd/sb700/enable_usbdebug.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/enable_usbdebug.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c)
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "sb700.h"
+
+#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+
+void set_debug_port(unsigned int port)
+{
+	u32 reg32;
+
+	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 &= ~(0xf << 28);
+	reg32 |= (port << 28);
+	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+	write32(DEBUGPORT_MISC_CONTROL, reg32);
+}
+
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
+void sb700_enable_usbdebug(unsigned int port)
+{
+	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/*
+	* Select the requested physical USB port (1-15) as the Debug Port.
+	* Must be called after the EHCI BAR has been set up (see above).
+	*/
+	set_debug_port(port);
+}

Copied: trunk/src/southbridge/amd/sb700/hda.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/hda.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_hda.c)
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "sb700.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 dword;
+	int count;
+
+	/* Write (val & ~mask) to port */
+	val &= mask;
+	dword = read32(port);
+	dword &= ~mask;
+	dword |= val;
+	write32(port, dword);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		dword = read32(port);
+		dword &= mask;
+	} while ((dword != val) && --count);
+
+	/* Timeout occured */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static u32 codec_detect(u32 base)
+{
+	u32 dword;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Delay for 1 ms since the BKDG does */
+	mdelay(1);
+
+	/* Read in Codec location (BAR + 0xe)[3..0]*/
+	dword = read32(base + 0xe);
+	dword &= 0x0F;
+	if (!dword)
+		goto no_codec;
+
+	return dword;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "No codec!\n");
+	return 0;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 dword=read32(base +  HDA_ICII_REG);
+		if (!(dword & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+static int wait_for_valid(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		u32 dword = read32(base + HDA_ICII_REG);
+		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return 1;
+}
+
+static void codec_init(u32 base, int addr)
+{
+	u32 dword;
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	dword = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, dword);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	dword = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
+}
+
+static void codecs_init(u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(base, i);
+	}
+}
+
+static void hda_init(struct device *dev)
+{
+	u8 byte;
+	u32 dword;
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	device_t sm_dev;
+
+	/* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */
+	byte = pm_ioread(0x59);
+	byte |= 1 << 3;
+	pm_iowrite(0x59, byte);
+
+	/* Find the SMBus */
+	/* FIXME: Need to find out why the call below crashes. */
+	/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB700_SM, 0);*/
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
+	pci_write_config32(sm_dev, 0xf8, 0x00);
+	pci_write_config8(sm_dev, 0xfc, 0xAA);
+	/* Set INTA - SMBus 0x63 [2..0] */
+	byte = pci_read_config8(sm_dev, 0x63);
+	byte &= ~0x7;
+	byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
+	pci_write_config8(sm_dev, 0x63, byte);
+
+	/* Program the 2C to 0x437b1002 */
+	dword = 0x437b1002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* Read in BAR */
+	/* Is this right? HDA allows for a 64-bit BAR
+	 * but this is only setup for a 32-bit one
+	 */
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
+		codecs_init(base, codec_mask);
+	}
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations hda_audio_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = hda_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver hdaaudio_driver __pci_driver = {
+	.ops = &hda_audio_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_HDA,
+};

Copied: trunk/src/southbridge/amd/sb700/ide.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_ide.c)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb700.h"
+
+static void ide_init(struct device *dev)
+{
+	struct southbridge_amd_sb700_config *conf;
+	/* Enable ide devices so the linux ide driver will work */
+	u32 dword;
+	u8 byte;
+
+	conf = dev->chip_info;
+
+	/* RPR9.1 disable MSI */
+	/* TODO: For A14, it should set as 1. I doubt it. */
+	dword = pci_read_config32(dev, 0x70);
+	dword &= ~(1 << 16);
+	pci_write_config32(dev, 0x70, dword);
+
+	/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
+	byte = pci_read_config8(dev, 0x54);
+	byte |= 0xf;
+	pci_write_config8(dev, 0x54, byte);
+
+	/* Enable I/O Access&& Bus Master */
+	dword = pci_read_config16(dev, 0x4);
+	dword |= 1 << 2;
+	pci_write_config16(dev, 0x4, dword);
+
+	/* set ide as primary, if you want to boot from IDE, you'd better set it
+	 * in $vendor/$mainboard/devicetree.cb */
+	 
+	
+	if (conf->boot_switch_sata_ide == 1) {
+		struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+		byte = pci_read_config8(sm_dev, 0xAD);
+		byte |= 1 << 4;
+		pci_write_config8(sm_dev, 0xAD, byte);
+	}
+
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);
+#endif
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_IDE,
+};

Copied: trunk/src/southbridge/amd/sb700/lpc.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_lpc.c)
@@ -0,0 +1,238 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "sb700.h"
+
+static void lpc_init(device_t dev)
+{
+	u8 byte;
+	u32 dword;
+	device_t sm_dev;
+
+	/* Enable the LPC Controller */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	dword = pci_read_config32(sm_dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(sm_dev, 0x64, dword);
+
+	/* Initialize isa dma */
+#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+	printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
+#else
+	isa_dma_init();
+#endif
+
+	/* Enable DMA transaction on the LPC bus */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Disable the timeout mechanism on LPC */
+	byte = pci_read_config8(dev, 0x48);
+	byte &= ~(1 << 7);
+	pci_write_config8(dev, 0x48, byte);
+
+	/* Disable LPC MSI Capability */
+	byte = pci_read_config8(dev, 0x78);
+	byte &= ~(1 << 1);
+	pci_write_config8(dev, 0x78, byte);
+}
+
+static void sb700_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+}
+
+static void sb700_lpc_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	res = find_resource(dev, 0xA0);
+	pci_write_config32(dev, 0xA0, res->base | 1 << 1);
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whose children's resources are to be enabled
+ *
+ */
+static void sb700_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		pci_write_config16(dev, 0x64, reg_var[0]);
+		break;
+	}
+}
+
+static void sb700_lpc_enable_resources(device_t dev)
+{
+	pci_dev_enable_resources(dev);
+	sb700_lpc_enable_childrens_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations lpc_ops = {
+	.read_resources = sb700_lpc_read_resources,
+	.set_resources = sb700_lpc_set_resources,
+	.enable_resources = sb700_lpc_enable_resources,
+	.init = lpc_init,
+	.scan_bus = scan_static_bus,
+	.ops_pci = &lops_pci,
+};
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_LPC,
+};

Copied: trunk/src/southbridge/amd/sb700/pci.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_pci.c)
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "sb700.h"
+
+static void pci_init(struct device *dev)
+{
+	u32 dword;
+	u16 word;
+	u8 byte;
+
+	/* RPR 5.1 Enables the PCI-bridge subtractive decode */
+	/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR5.2 PCI-bridge upstream dual address window */
+	/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR 5.3 PCI bus 64-byte DMA read access */
+	/* Enhance the PCI bus DMA performance */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 4;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */
+	/* The size of the writes will be set in the Cacheline Register */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 1;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
+	pci_write_config8(dev, 0x0D, 0x40);
+	pci_write_config8(dev, 0x1B, 0x40);
+
+	/* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 6;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* RPR 5.8 Adjusts the GNT# de-assertion time */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 12;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 5.9 Fast Back to Back transactions support */
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 1 << 2;
+	/* pci_write_config8(dev, 0x48, byte); */
+
+	/* RPR 5.10 Enable Lock Operation */
+	/* byte = pci_read_config8(dev, 0x48); */
+	byte |= 1 << 3;
+	pci_write_config8(dev, 0x48, byte);
+
+	/* RPR 5.11 Enable additional optional PCI clock */
+	word = pci_read_config16(dev, 0x64);
+	word |= 1 << 8;
+	pci_write_config16(dev, 0x64, word);
+
+	/* RPR 5.12 Enable One-Prefetch-Channel Mode */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= 1 << 20;
+	pci_write_config32(dev, 0x64, dword);
+
+	/* RPR 5.13 Disable PCIB MSI Capability */
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 3);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* rpr5.14 Adjusting CLKRUN# */
+	dword = pci_read_config32(dev, 0x64);
+	dword |= (1 << 15);
+	pci_write_config32(dev, 0x64, dword);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_PCI,
+};

Copied: trunk/src/southbridge/amd/sb700/reset.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_reset.c)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/amd/sb700/sata.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_sata.c)
@@ -0,0 +1,294 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "sb700.h"
+
+static int sata_drive_detect(int portnum, u16 iobar)
+{
+	u8 byte, byte2;
+	int i = 0;
+	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+	while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
+		(byte != (0xA0 + 0x10 * (portnum % 2))) ||
+		((byte2 & 0x88) != 0)) {
+		printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
+		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+			/* This will happen at the first iteration of this loop
+			 * if the first SATA port is unpopulated and the
+			 * second SATA port is poulated.
+			 */
+			printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
+				"retrying init\n", i * 10);
+			return 1;
+		} else
+			printk(BIOS_SPEW, "drive detection not yet completed, "
+				"waiting...\n");
+		mdelay(10);
+		i++;
+	}
+	printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
+	return 0;
+}
+
+	/* This function can be overloaded in mainboard.c */
+
+void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) {
+	/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+	pci_write_config16(dev, 0x86, 0x2c00);
+
+	/* RPR7.6.2 SATA GENI PHY ports setting */
+	pci_write_config32(dev, 0x88, 0x01B48017);
+	pci_write_config32(dev, 0x8c, 0x01B48019);
+	pci_write_config32(dev, 0x90, 0x01B48016);
+	pci_write_config32(dev, 0x94, 0x01B48016);
+	pci_write_config32(dev, 0x98, 0x01B48016);
+	pci_write_config32(dev, 0x9C, 0x01B48016);
+
+	/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+	pci_write_config16(dev, 0xA0, 0xA09A);
+	pci_write_config16(dev, 0xA2, 0xA09F);
+	pci_write_config16(dev, 0xA4, 0xA07A);
+	pci_write_config16(dev, 0xA6, 0xA07A);
+	pci_write_config16(dev, 0xA8, 0xA07A);
+	pci_write_config16(dev, 0xAA, 0xA07A);
+}
+
+static void sata_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+	u32 dword;
+	u8 rev_id;
+	u32 sata_bar5;
+	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+	int i, j;
+
+	struct southbridge_ati_sb700_config *conf;
+	conf = dev->chip_info;
+
+	device_t sm_dev;
+	/* SATA SMBus Disable */
+	/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	/* Disable SATA SMBUS */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 1);
+	/* Enable SATA and power saving */
+	byte = pci_read_config8(sm_dev, 0xad);
+	byte |= (1 << 0);
+	byte |= (1 << 5);
+	pci_write_config8(sm_dev, 0xad, byte);
+
+	/* RPR 7.2 SATA Initialization */
+	/* Set the interrupt Mapping to INTG# */
+	byte = pci_read_config8(sm_dev, 0xaf);
+	byte = 0x6 << 2;
+	pci_write_config8(sm_dev, 0xaf, byte);
+
+	/* get rev_id */
+	rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
+
+	/* get base address */
+	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
+	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
+	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
+	sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
+	sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
+
+	printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+
+	/* disable combined mode */
+	byte = pci_read_config8(sm_dev, 0xAD);
+	byte &= ~(1 << 3);
+	pci_write_config8(sm_dev, 0xAD, byte);
+	/* Program the 2C to 0x43801002 */
+	dword = 0x43801002;
+	pci_write_config32(dev, 0x2c, dword);
+
+	/* SERR-Enable */
+	word = pci_read_config16(dev, 0x04);
+	word |= (1 << 8);
+	pci_write_config16(dev, 0x04, word);
+
+	/* Dynamic power saving */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 2);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Set SATA Operation Mode, Set to IDE mode */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= (1 << 0);
+	byte |= (1 << 4);
+	pci_write_config8(dev, 0x40, byte);
+
+	dword = 0x01018f00;
+	pci_write_config32(dev, 0x8, dword);
+
+	byte = pci_read_config8(dev, 0x40);
+	byte &= ~(1 << 0);
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Enable the SATA watchdog counter */
+	byte = pci_read_config8(dev, 0x44);
+	byte |= (1 << 0);
+	pci_write_config8(dev, 0x44, byte);
+
+	/* Set bit 29 and 24 for A12 */
+	dword = pci_read_config32(dev, 0x40);
+	if (rev_id < 0x14)	/* before A12 */
+		dword |= (1 << 29);
+	else
+		dword &= ~(1 << 29); /* A14 and above */
+	pci_write_config32(dev, 0x40, dword);
+
+	/* set bit 21 for A12 */
+	dword = pci_read_config32(dev, 0x48);
+	if (rev_id < 0x14)	/* before A12 */
+		dword |= 1 << 24 | 1 << 21;
+	else {
+		dword &= ~(1 << 24 | 1 << 21); /* A14 and above */
+		dword &= ~0xFF80; /* 15:7 */
+		dword |= 1 << 15 | 0x7F << 7;
+	}
+	pci_write_config32(dev, 0x48, dword);
+
+	/* Program the watchdog counter to 0x10 */
+	byte = 0x10;
+	pci_write_config8(dev, 0x46, byte);
+	sb700_setup_sata_phys(dev);
+	/* Enable the I/O, MM, BusMaster access for SATA */
+	byte = pci_read_config8(dev, 0x4);
+	byte |= 7 << 0;
+	pci_write_config8(dev, 0x4, byte);
+
+	/* RPR7.7 SATA drive detection. */
+	/* Use BAR5+0x128,BAR0 for Primary Slave */
+	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+	/* Use BAR5+0x228,BAR2 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
+	/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
+	/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
+
+	/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
+
+	for (i = 0; i < 4; i++) {
+		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+		byte &= 0xF;
+		if( byte == 0x1 ) {
+			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
+			/* Try to do something about it. */
+			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
+
+			/* Read in Port-N Serial ATA Control Register */
+			byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+
+			/* Set Reset Bit and 1.5g bit */
+			byte |= 0x11;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Clear Reset Bit */
+			byte &= ~0x01;
+			write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+
+			/* Wait 1ms */
+			mdelay(1);
+
+			/* Reread status */
+			byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+			printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
+			byte &= 0xF;
+		}
+
+		if (byte == 0x3) {
+			for (j = 0; j < 10; j++) {
+				if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
+					break;
+			}
+			printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master",
+					(j == 10) ? "not " : "",
+					(j == 10) ? j : j + 1);
+		} else {
+			printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
+					(i / 2) ? "Secondary" : "Primary",
+					(i % 2 ) ? "Slave" : "Master", i);
+		}
+	}
+
+	/* Below is CIM InitSataLateFar */
+	/* Enable interrupts from the HBA  */
+	byte = read8(sata_bar5 + 0x4);
+	byte |= 1 << 1;
+	write8((sata_bar5 + 0x4), byte);
+
+	/* Clear error status */
+	write32((sata_bar5 + 0x130), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x230), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x330), 0xFFFFFFFF);
+	write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
+
+	/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+	/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+	/* word = 0x0000; */
+	/* word = pm_ioread(0x28); */
+	/* byte = pm_ioread(0x29); */
+	/* word |= byte<<8; */
+	/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
+	/* write32(word, 0x80000000); */
+}
+
+static struct pci_operations lops_pci = {
+	/* .set_subsystem = pci_dev_set_subsystem, */
+};
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = sata_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_SATA,
+};

Copied and modified: trunk/src/southbridge/amd/sb700/sm.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_sm.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_sm.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/sm.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 

Copied and modified: trunk/src/southbridge/amd/sb700/smbus.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.c)
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/amd/sb700/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -20,7 +20,7 @@
 #ifndef _SB700_SMBUS_C_
 #define _SB700_SMBUS_C_
 
-#include "sb700_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {

Copied: trunk/src/southbridge/amd/sb700/smbus.h (from r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_smbus.h)
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SB700_SMBUS_H
+#define SB700_SMBUS_H
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+#define AX_INDXC  0
+#define AX_INDXP  1
+#define AXCFG     2
+#define ABCFG     3
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx(0, (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)	\
+	alink_ax_indx(1, (reg), (mask), (val))
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+
+
+#endif

Copied: trunk/src/southbridge/amd/sb700/usb.c (from r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/amd/sb700/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/amd/sb700/sb700_usb.c)
@@ -0,0 +1,253 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <usbdebug.h>
+#include <arch/io.h>
+#include "sb700.h"
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+	u8 byte;
+	u16 word;
+
+	/* 6.1 Enable OHCI0-4 and EHCI Controllers */
+	device_t sm_dev;
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	byte = pci_read_config8(sm_dev, 0x68);
+	byte |= 0xFF;
+	pci_write_config8(sm_dev, 0x68, byte);
+
+	/* RPR 6.2 Enables the USB PME Event,Enable USB resume support */
+	byte = pm_ioread(0x61);
+	byte |= 1 << 6;
+	pm_iowrite(0x61, byte);
+	byte = pm_ioread(0x65);
+	byte |= 1 << 2;
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.3 Support USB device wakeup from the S4/S5 state */
+	byte = pm_ioread(0x65);
+	byte &= ~(1 << 0);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.5 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
+	byte = pm_ioread(0x65);
+	byte |= (1 << 4);
+	pm_iowrite(0x65, byte);
+
+	/* RPR 6.10 Disable OHCI MSI Capability. */
+	word = pci_read_config16(dev, 0x40);
+	word |= (0x3 << 8);
+	pci_write_config16(dev, 0x40, word);
+}
+
+static void usb_init2(struct device *dev)
+{
+	u32 dword;
+	u32 usb2_bar0;
+	device_t sm_dev;
+	u8 rev;
+
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	rev = get_sb700_revision(sm_dev);
+
+	/* dword = pci_read_config32(dev, 0xf8); */
+	/* dword |= 40; */
+	/* pci_write_config32(dev, 0xf8, dword); */
+
+	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
+	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+
+	/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
+	dword = 0x00020F00;
+	write32(usb2_bar0 + 0xC0, dword);
+
+	/* RPR6.9 Sets In/OUT FIFO threshold for best performance */
+	dword = 0x00400040;
+	write32(usb2_bar0 + 0xA4, dword);
+
+	/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 28);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR 6.12 EHCI Advance PHY Power Savings */
+	/* RPR says it is just for A12. CIMM sets it when it is above A11. */
+	/* But it makes the linux crash, so we skip it */
+	#if 0
+	dword = pci_read_config32(dev, 0x50);
+	dword |= 1 << 31;
+	pci_write_config32(dev, 0x50, dword);
+	#endif
+
+	/* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */
+	/* RPR says it is just for A12. CIMx sets it when it is above A11. */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 20);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* RPR6.15 EHCI Async Park Mode */
+	dword = pci_read_config32(dev, 0x50);
+	dword |= (1 << 23);
+	pci_write_config32(dev, 0x50, dword);
+
+	/* Each step below causes the linux crashes. Leave them here
+	 * for future debugging. */
+#if 0
+	u8 byte;
+	u16 word;
+
+	/* RPR6.16 Disable EHCI MSI support */
+	byte = pci_read_config8(dev, 0x50);
+	byte |= (1 << 6);
+	pci_write_config8(dev, 0x50, byte);
+
+	/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */
+	word = read32(usb2_bar0 + 0xBC);
+	word &= ~(1 << 12);
+	write16(usb2_bar0 + 0xBC, word);
+
+	/* RPR6.19 USB Controller DMA Read Delay Tolerant. */
+	if (rev >= REV_SB700_A14) {
+		byte = pci_read_config8(dev, 0x50);
+		byte |= (1 << 7);
+		pci_write_config8(dev, 0x50, byte);
+	}
+
+	/* RPR6.20 Async Park Mode. */
+	/* RPR recommends not to set these bits. */
+	#if 0
+	dword = pci_read_config32(dev, 0x50);
+	dword |= 1 << 23;
+	if (rev >= REV_SB700_A14) {
+		dword &= ~(1 << 2);
+	}
+	pci_write_config32(dev, 0x50, dword);
+	#endif
+
+	/* RPR6.22 Advance Async Enhancement */
+	/* RPR6.23 USB Periodic Cache Setting */
+	dword = pci_read_config32(dev, 0x50);
+	if (rev == REV_SB700_A12) {
+		dword |= 1 << 28; /* 6.22 */
+		dword |= 1 << 27; /* 6.23 */
+	} else if (rev >= REV_SB700_A14) {
+		dword |= 1 << 3;
+		dword &= ~(1 << 28); /* 6.22 */
+		dword |= 1 << 8;
+		dword &= ~(1 << 27); /* 6.23 */
+	}
+	printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
+#endif
+}
+
+static void usb_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_0_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_0,
+};
+
+static const struct pci_driver usb_1_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
+};
+
+/* the pci id of usb ctrl 0 and 1 are the same. */
+/*
+ * static const struct pci_driver usb_3_driver __pci_driver = {
+ * 	.ops = &usb_ops,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_0,
+ * };
+ * static const struct pci_driver usb_4_driver __pci_driver = {
+ * 	.ops = &usb_ops,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_1,
+ * };
+ */
+
+static const struct pci_driver usb_4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_20_5,
+};
+
+static struct device_operations usb_ops2 = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = usb_set_resources, /* pci_dev_set_resources, */
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init2,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver usb_5_driver __pci_driver = {
+	.ops = &usb_ops2,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_2,
+};
+/*
+ * static const struct pci_driver usb_5_driver __pci_driver = {
+ * 	.ops = &usb_ops2,
+ * 	.vendor = PCI_VENDOR_ID_ATI,
+ * 	.device = PCI_DEVICE_ID_ATI_SB700_USB_19_2,
+ * };
+ */

Modified: trunk/src/southbridge/broadcom/bcm21000/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm21000/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm21000/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += bcm21000_pcie.c
+driver-y += pcie.c

Copied: trunk/src/southbridge/broadcom/bcm21000/pcie.c (from r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm21000/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c)
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for
+ * University of Heidelberg.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void pcie_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	uint32_t dword;
+	uint32_t msicap;
+
+	printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+	/* enable MSI on PCIE: */
+	msicap = pci_read_config32(dev, 0xa0);
+	msicap |= (1<<16); /* enable MSI*/
+	pci_write_config32(dev, 0xa0, msicap);
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = 0,
+};
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pci_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pcie_driver1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0,
+};
+
+static const struct pci_driver pcie_driver2 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1,
+};
+
+static const struct pci_driver pcie_driver3 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2,
+};

Modified: trunk/src/southbridge/broadcom/bcm5780/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5780/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5780/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,3 +1,3 @@
-driver-y += bcm5780_nic.c
-driver-y += bcm5780_pcix.c
-driver-y += bcm5780_pcie.c
+driver-y += nic.c
+driver-y += pcix.c
+driver-y += pcie.c

Copied: trunk/src/southbridge/broadcom/bcm5780/nic.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void nic_init(struct device *dev)
+{
+#if CONFIG_PCI_ROM_RUN == 1
+	pci_dev_init(dev);// it will init option rom
+#endif
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = nic_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_BROADCOM,
+	.device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC,
+};
+
+static const struct pci_driver nic1_driver __pci_driver = {
+        .ops    = &nic_ops,
+        .vendor = PCI_VENDOR_ID_BROADCOM,
+        .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+};

Copied: trunk/src/southbridge/broadcom/bcm5780/pcie.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c)
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void pcie_init(struct device *dev)
+{
+
+	/* Enable pci error detecting */
+	uint32_t dword;
+
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* System error enable */
+	dword |= (1<<30); /* Clear possible errors */
+	pci_write_config32(dev, 0x04, dword);
+
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = 0,
+};
+
+static struct device_operations pcie_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init             = pcie_init,
+        .scan_bus         = pci_scan_bridge,
+        .reset_bus        = pci_bus_reset,
+        .ops_pci          = &lops_pci,
+
+};
+
+static const struct pci_driver pcie_driver __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE,
+};

Copied: trunk/src/southbridge/broadcom/bcm5780/pcix.c (from r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5780/pcix.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c)
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ht_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init             = 0 ,
+        .scan_bus         = pci_scan_bridge,
+        .reset_bus        = pci_bus_reset,
+        .ops_pci          = &lops_pci,
+
+};
+
+static const struct pci_driver ht_driver __pci_driver = {
+	.ops    = &ht_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB,
+};

Modified: trunk/src/southbridge/broadcom/bcm5785/Makefile.inc
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5785/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,7 +1,7 @@
 driver-y += bcm5785.c
-driver-y += bcm5785_usb.c
-driver-y += bcm5785_lpc.c
-driver-y += bcm5785_sb_pci_main.c
-driver-y += bcm5785_ide.c
-driver-y += bcm5785_sata.c
-ramstage-y += bcm5785_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sb_pci_main.c
+driver-y += ide.c
+driver-y += sata.c
+ramstage-y += reset.c

Modified: trunk/src/southbridge/broadcom/bcm5785/bootblock.c
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/broadcom/bcm5785/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_enable_rom.c"
+#include "enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/broadcom/bcm5785/early_setup.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/early_setup.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c)
@@ -0,0 +1,223 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include "bcm5785.h"
+
+static void bcm5785_enable_lpc(void)
+{
+        uint8_t byte;
+        device_t dev;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+        /* LPC Control 0 */
+        byte = pci_read_config8(dev, 0x44);
+        /* Serial 0 */
+        byte |= (1<<6);
+        pci_write_config8(dev, 0x44, byte);
+
+        /* LPC Control 4 */
+        byte = pci_read_config8(dev, 0x48);
+        /* superio port 0x2e/4e enable */
+        byte |=(1<<1)|(1<<0);
+        pci_write_config8(dev, 0x48, byte);
+}
+
+static void bcm5785_enable_wdt_port_cf9(void)
+{
+        device_t dev;
+        uint32_t dword;
+        uint32_t dword_old;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+        dword_old = pci_read_config32(dev, 0x4c);
+        dword = dword_old | (1<<4); //enable Timer Func
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x4c, dword);
+        }
+
+        dword_old = pci_read_config32(dev, 0x6c);
+        dword = dword_old | (1<<9); //unhide Timer Func in pci space
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x6c, dword);
+        }
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+
+        /* enable cf9 */
+        pci_write_config8(dev, 0x40, (1<<2));
+}
+
+unsigned get_sbdn(unsigned bus)
+{
+        device_t dev;
+
+        /* Find the device.
+         * There can only be one bcm5785 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(0x1166, 0x0036),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+#define SB_VFSMAF 0
+
+void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+	//ACPI Decode Enable
+	outb(0x0e, 0xcd6);
+	outb((1<<3), 0xcd7);
+
+	// set port to 0x2060
+	outb(0x67, 0xcd6);
+	outb(0x60, 0xcd7);
+        outb(0x68, 0xcd6);
+        outb(0x20, 0xcd7);
+
+	outb(0x69, 0xcd6);
+	outb(7, 0xcd7);
+
+	outb(0x64, 0xcd6);
+	outb(9, 0xcd7);
+}
+
+void ldtstop_sb(void)
+{
+	outb(1, 0x2060);
+}
+
+
+void hard_reset(void)
+{
+        bcm5785_enable_wdt_port_cf9();
+
+        set_bios_reset();
+
+        /* full reset */
+        outb(0x0a, 0x0cf9);
+        outb(0x0e, 0x0cf9);
+}
+
+void soft_reset(void)
+{
+        bcm5785_enable_wdt_port_cf9();
+
+        set_bios_reset();
+#if 1
+        /* link reset */
+//        outb(0x02, 0x0cf9);
+        outb(0x06, 0x0cf9);
+#endif
+}
+
+static void bcm5785_enable_msg(void)
+{
+        device_t dev;
+        uint32_t dword;
+        uint32_t dword_old;
+        uint8_t byte;
+
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+        byte = pci_read_config8(dev, 0x42);
+        byte = (1<<1); //enable a20
+        pci_write_config8(dev, 0x42, byte);
+
+        dword_old = pci_read_config32(dev, 0x6c);
+        // bit 5: enable A20 Message
+        // bit 4: enable interrupt messages
+        // bit 3: enable reset init message
+        // bit 2: enable keyboard init message
+        // bit 1: enable upsteam messages
+        // bit 0: enable shutdowm message to init generation
+        dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+        if(dword != dword_old ) {
+                pci_write_config32(dev, 0x6c, dword);
+        }
+}
+
+static void bcm5785_early_setup(void)
+{
+        uint8_t byte;
+        uint32_t dword;
+        device_t dev;
+
+//F0
+        // enable device on bcm5785 at first
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+        dword = pci_read_config32(dev, 0x64);
+        dword |=  (1<<15) | (1<<11) | (1<<3); // ioapci enable
+        dword |= (1<<8); // USB enable
+        dword |= /* (1<<27)|*/(1<<14); // IDE enable
+        pci_write_config32(dev, 0x64, dword);
+
+        byte = pci_read_config8(dev, 0x84);
+        byte |= (1<<0); // SATA enable
+        pci_write_config8(dev, 0x84, byte);
+
+// WDT and cf9 for later in coreboot_ram to call hard_reset
+        bcm5785_enable_wdt_port_cf9();
+
+        bcm5785_enable_msg();
+
+
+// IDE related
+	//F0
+        byte = pci_read_config8(dev, 0x4e);
+        byte |= (1<<4); //enable IDE ext regs
+        pci_write_config8(dev, 0x4e, byte);
+
+	//F1
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+        byte = pci_read_config8(dev, 0x48);
+        byte &= ~1; // disable pri channel
+        pci_write_config8(dev, 0x48, byte);
+        pci_write_config8(dev, 0xb0, 0x01);
+        pci_write_config8(dev, 0xb2, 0x02);
+        byte = pci_read_config8(dev, 0x06);
+        byte |= (1<<4); // so b0, b2 can not be changed from now
+        pci_write_config8(dev, 0x06, byte);
+        byte = pci_read_config8(dev, 0x49);
+        byte |= 1; // enable second channel
+        pci_write_config8(dev, 0x49, byte);
+
+	//F2
+        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+        byte = pci_read_config8(dev, 0x40);
+        byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+        pci_write_config8(dev, 0x40, byte);
+
+        pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+
+// USB related
+        pci_write_config8(dev, 0x90, 0x40);
+        pci_write_config8(dev, 0x92, 0x06);
+        pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+        pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+        pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+        pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+        pci_write_config8(dev, 0xb4, 0x40);
+}

Copied and modified: trunk/src/southbridge/broadcom/bcm5785/early_smbus.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/broadcom/bcm5785/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x1000
 

Copied: trunk/src/southbridge/broadcom/bcm5785/enable_rom.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+static void bcm5785_enable_rom(void)
+{
+	u8 byte;
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
+			PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
+
+	/* Set the 4MB enable bits. */
+	byte = pci_read_config8(dev, 0x41);
+	byte |= 0x0e;
+	pci_write_config8(dev, 0x41, byte);
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/ide.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c)
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "bcm5785.h"
+
+static void bcm5785_ide_read_resources(device_t dev)
+{
+        /* Get the normal pci resources of this device */
+        pci_dev_read_resources(dev);
+
+        /* BAR */
+        pci_get_resource(dev, 0x64);
+
+        compact_resources(dev);
+}
+
+static void ide_init(struct device *dev)
+{
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations ide_ops  = {
+	.read_resources   = bcm5785_ide_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+//	.enable           = bcm5785_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE,
+};

Copied: trunk/src/southbridge/broadcom/bcm5785/lpc.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c)
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <bitops.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "bcm5785.h"
+
+static void lpc_init(device_t dev)
+{
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void bcm5785_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+/**
+ * Enable resources for children devices.
+ *
+ * @param dev The device whos children's resources are to be enabled.
+ */
+static void bcm5785_lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	uint32_t reg;
+
+	reg = pci_read_config8(dev, 0x44);
+
+	for (link = dev->link_list; link; link = link->next) {
+                device_t child;
+                for (child = link->children; child; child = child->sibling) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for(res = child->resource_list; res; res = res->next) {
+			                unsigned long base, end; // don't need long long
+					if(!(res->flags & IORESOURCE_IO)) continue;
+		        	        base = res->base;
+                			end = resource_end(res);
+					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
+					switch(base) {
+					case 0x60: //KBC
+					case 0x64:
+						reg |= (1<<29);
+					case 0x3f8: // COM1
+						reg |= (1<<6); 	break;
+					case 0x2f8: // COM2
+						reg |= (1<<7);  break;
+					case 0x378: // Parallal 1
+						reg |= (1<<0); break;
+					case 0x3f0: // FD0
+						reg |= (1<<26); break;
+					case 0x220:  // Aduio 0
+						reg |= (1<<14);	break;
+					case 0x300:  // Midi 0
+						reg |= (1<<18);	break;
+					}
+				}
+			}
+                }
+        }
+	pci_write_config32(dev, 0x44, reg);
+
+
+}
+
+static void bcm5785_lpc_enable_resources(device_t dev)
+{
+        pci_dev_enable_resources(dev);
+        bcm5785_lpc_enable_childrens_resources(dev);
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = bcm5785_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = bcm5785_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+//	.enable           = bcm5785_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
+};

Copied: trunk/src/southbridge/broadcom/bcm5785/reset.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c)
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+        (((BUS) & 0xFFF) << 20) | \
+        (((DEV) & 0x1F) << 15) | \
+        (((FN)  & 0x7) << 12))
+
+typedef unsigned device_t;
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+        unsigned addr;
+        addr = (dev>>4) | where;
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+	set_bios_reset();
+        /* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
+      	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/sata.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c)
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "bcm5785.h"
+
+static void sata_init(struct device *dev)
+{
+	uint8_t byte;
+
+	u32 mmio;
+        struct resource *res;
+        u32 mmio_base;
+	int i;
+
+	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
+		byte = pci_read_config8(dev, 0x78);
+		byte |= (1<<7);
+        	pci_write_config8(dev, 0x78, byte);
+
+	        res = find_resource(dev, 0x24);
+                mmio_base = res->base;
+                mmio_base &= 0xfffffffc;
+
+		write32(mmio_base + 0x10f0, 0x40000001);
+		write32(mmio_base + 0x8c, 0x00ff2007);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x78592009);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x00082004);
+                mdelay( 10 );
+		write32(mmio_base + 0x8c, 0x00002004);
+                mdelay( 10 );
+
+		//init PHY
+
+		printk(BIOS_DEBUG, "init PHY...\n");
+		for(i=0; i<4; i++) {
+			mmio = res->base + 0x100 * i;
+			byte = read8(mmio + 0x40);
+			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
+			if(byte & 0x4) {// bit 2 is set
+				byte = read8(mmio+0x48);
+				write8(mmio + 0x48, byte | 1);
+				write8(mmio + 0x48, byte & (~1));
+	                        byte = read8(mmio + 0x40);
+	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
+			}
+		}
+	}
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+//	.enable           = bcm5785_enable,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver sata0_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA,
+};

Copied and modified: trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c)
==============================================================================
--- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/broadcom/bcm5785/sb_pci_main.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -30,7 +30,7 @@
 #include <arch/io.h>
 #include <device/smbus.h>
 #include "bcm5785.h"
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define NMI_OFF 0
 

Copied: trunk/src/southbridge/broadcom/bcm5785/smbus.h (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h)
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) { // ready now
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while(--loops);
+	return -2; // time out
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f; // mask off reserved bits
+		if ( val & 0x1c) {
+			return -5; // error
+		}
+		if ( val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT); // clear status
+			return 0; //
+		}
+	} while(--loops);
+	return -3; // timeout
+}
+
+static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+{
+	uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        /* read results of transaction */
+        byte = inb(smbus_io_base + SMBHSTCMD);
+
+	return byte;
+}
+
+static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+{
+        uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the command... */
+        outb(val, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        return 0;
+}
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	uint8_t byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2; // not ready
+	}
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3; // Clear [4:2]
+	byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3; // timeout or error
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	return byte;
+}
+
+static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+{
+        uint8_t byte;
+
+        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+                return -2; // not ready
+        }
+
+        /* set the command/address... */
+        outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+        /* set the device I'm talking too */
+        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+
+        /* output value */
+        outb(val, smbus_io_base + SMBHSTDAT0);
+
+        byte = inb(smbus_io_base + SMBHSTCTRL);
+        byte &= 0xe3; // Clear [4:2]
+        byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+        outb(byte, smbus_io_base + SMBHSTCTRL);
+
+        /* poll for transaction completion */
+        if (smbus_wait_until_done(smbus_io_base) < 0) {
+                return -3; // timeout or error
+        }
+
+        return 0;
+}

Copied: trunk/src/southbridge/broadcom/bcm5785/usb.c (from r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/broadcom/bcm5785/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c)
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 AMD
+ * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "bcm5785.h"
+
+static void usb_init(struct device *dev)
+{
+        uint32_t dword;
+
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<2)|(1<<1)|(1<<0);
+	pci_write_config32(dev, 0x04, dword);
+
+	pci_write_config8(dev, 0x41, 0x00); // Serversworks said
+
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+        pci_write_config32(dev, 0x40,
+                ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+        .set_subsystem = lpci_set_subsystem,
+};
+
+static struct device_operations usb_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = usb_init,
+//	.enable           = bcm5785_enable,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb_driver __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB,
+};

Modified: trunk/src/southbridge/intel/esb6300/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/esb6300/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/esb6300/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,12 +1,12 @@
 driver-y += esb6300.c
-driver-y += esb6300_reset.c
-driver-y += esb6300_uhci.c
-driver-y += esb6300_lpc.c
-driver-y += esb6300_ide.c
-driver-y += esb6300_sata.c
-driver-y += esb6300_ehci.c
-driver-y += esb6300_smbus.c
-driver-y += esb6300_pci.c
-driver-y += esb6300_pic.c
-driver-y += esb6300_bridge1c.c
-driver-y += esb6300_ac97.c
+driver-y += reset.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+driver-y += pic.c
+driver-y += bridge1c.c
+driver-y += ac97.c

Copied: trunk/src/southbridge/intel/esb6300/ac97.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ac97.c)
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = ac97_set_subsystem,
+};
+static struct device_operations ac97_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97_audio_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO,
+};
+static const struct pci_driver ac97_modem_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM,
+};

Copied: trunk/src/southbridge/intel/esb6300/bridge1c.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/bridge1c.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c)
@@ -0,0 +1,47 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void bridge1c_init(struct device *dev)
+{
+	/* configuration */
+	pci_write_config8(dev, 0x1b, 0x30);
+//	pci_write_config8(dev, 0x3e, 0x07);
+	pci_write_config8(dev, 0x3e, 0x04);  /* parity ignore */
+	pci_write_config8(dev, 0x6c, 0x0c);  /* undocumented  */
+	pci_write_config8(dev, 0xe0, 0x20);
+
+	/* SRB enable */
+	pci_write_config16(dev, 0xe4, 0x0232);
+
+	/* Burst size */
+	pci_write_config8(dev, 0xf0, 0x02);
+
+	/* prefetch threshold size */
+	pci_write_config16(dev, 0xf8, 0x2121);
+
+	/* primary latency */
+	pci_write_config8(dev, 0x0d, 0x28);
+
+	/* multi transaction timer */
+	pci_write_config8(dev, 0x42, 0x08);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = bridge1c_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
+};
+

Copied and modified: trunk/src/southbridge/intel/esb6300/early_smbus.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/esb6300/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 

Copied: trunk/src/southbridge/intel/esb6300/ehci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ehci.c)
@@ -0,0 +1,50 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ehci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	uint8_t access_cntl;
+	access_cntl = pci_read_config8(dev, 0x80);
+	/* Enable writes to protected registers */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+	/* Restore protection */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &ehci_set_subsystem,
+};
+static struct device_operations ehci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ehci_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
+};

Copied: trunk/src/southbridge/intel/esb6300/ide.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_ide.c)
@@ -0,0 +1,56 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void ide_init(struct device *dev)
+{
+
+	/* Enable ide devices so the linux ide driver will work */
+
+	/* Enable IDE devices */
+        pci_write_config16(dev, 0x40, 0x0a307);
+        pci_write_config16(dev, 0x42, 0x0a307);
+        pci_write_config8(dev, 0x48, 0x05);
+        pci_write_config16(dev, 0x4a, 0x0101);
+        pci_write_config16(dev, 0x54, 0x5055);
+
+#if 0
+	uint16_t word;
+	word = pci_read_config16(dev, 0x40);
+	word |= (1 << 15);
+	pci_write_config16(dev, 0x40, word);
+	word = pci_read_config16(dev, 0x42);
+	word |= (1 << 15);
+	pci_write_config16(dev, 0x42, word);
+#endif
+	printk(BIOS_DEBUG, "IDE Enabled\n");
+}
+
+static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* This value is also visible in uchi[0-2] and smbus functions */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = esb6300_ide_set_subsystem,
+};
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_IDE,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/lpc.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_lpc.c)
@@ -0,0 +1,374 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "esb6300.h"
+
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x58
+
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define SERIRQ_CNTL 0x64
+static void esb6300_enable_serial_irqs(device_t dev)
+{
+	/* set packet length and toggle silent mode bit */
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+}
+
+#define PCI_DMA_CFG 0x90
+static void esb6300_pci_dma_cfg(device_t dev)
+{
+	/* Set PCI DMA CFG to lpc I/F DMA */
+	pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
+}
+
+#define LPC_EN 0xe6
+static void esb6300_enable_lpc(device_t dev)
+{
+        /* lpc i/f enable */
+        pci_write_config8(dev, LPC_EN, 0x0d);
+}
+
+typedef struct southbridge_intel_esb6300_config config_t;
+
+static void set_esb6300_gpio_use_sel(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_use_sel, gpio_use_sel2;
+
+//	gpio_use_sel  = 0x1B003100;
+//	gpio_use_sel2 = 0x03000000;
+	gpio_use_sel  = 0x1BBC31C0;
+	gpio_use_sel2 = 0x03000FE1;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) {
+		case ESB6300_GPIO_USE_AS_NATIVE: val = 0; break;
+		case ESB6300_GPIO_USE_AS_GPIO:   val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_use_sel  &= ~( 1 << i);
+			gpio_use_sel  |= (val << i);
+		} else {
+			gpio_use_sel2 &= ~( 1 << (i - 32));
+			gpio_use_sel2 |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_use_sel,  res->base + 0x00);
+	outl(gpio_use_sel2, res->base + 0x30);
+}
+
+static void set_esb6300_gpio_direction(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_io_sel, gpio_io_sel2;
+
+//	gpio_io_sel  = 0x0000ffff;
+//	gpio_io_sel2 = 0x00000000;
+	gpio_io_sel  = 0x1900ffff;
+	gpio_io_sel2 = 0x00000fe1;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
+		case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
+		case ESB6300_GPIO_SEL_INPUT:  val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_io_sel  &= ~( 1 << i);
+			gpio_io_sel  |= (val << i);
+		} else {
+			gpio_io_sel2 &= ~( 1 << (i - 32));
+			gpio_io_sel2 |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_io_sel,  res->base + 0x04);
+	outl(gpio_io_sel2, res->base + 0x34);
+}
+
+static void set_esb6300_gpio_level(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_lvl, gpio_lvl2;
+	uint32_t gpio_blink;
+
+//	gpio_lvl   = 0x1b3f0000;
+//	gpio_blink = 0x00040000;
+//	gpio_lvl2  = 0x00000fff;
+	gpio_lvl   = 0x19370000;
+	gpio_blink = 0x00000000;
+	gpio_lvl2  = 0x00000fff;
+#if 0
+	int i;
+	for(i = 0; i < 64; i++) {
+		int val, blink;
+		switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) {
+		case ESB6300_GPIO_LVL_LOW:   val = 0; blink = 0; break;
+		case ESB6300_GPIO_LVL_HIGH:  val = 1; blink = 0; break;
+		case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_lvl   &= ~(   1 << i);
+			gpio_blink &= ~(   1 << i);
+			gpio_lvl   |= (  val << i);
+			gpio_blink |= (blink << i);
+		} else {
+			gpio_lvl2  &= ~( 1 << (i - 32));
+			gpio_lvl2  |= (val << (i - 32));
+		}
+	}
+#endif
+	outl(gpio_lvl,   res->base + 0x0c);
+	outl(gpio_blink, res->base + 0x18);
+	outl(gpio_lvl2,  res->base + 0x38);
+}
+
+static void set_esb6300_gpio_inv(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_inv;
+
+	gpio_inv   = 0x00003100;
+#if 0
+	int i;
+	for(i = 0; i < 32; i++) {
+		int val;
+		switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
+		case ESB6300_GPIO_INV_OFF: val = 0; break;
+		case ESB6300_GPIO_INV_ON:  val = 1; break;
+		default:
+			continue;
+		}
+		gpio_inv &= ~( 1 << i);
+		gpio_inv |= (val << i);
+	}
+#endif
+	outl(gpio_inv,   res->base + 0x2c);
+}
+
+static void esb6300_pirq_init(device_t dev)
+{
+	config_t *config;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->pirq_a_d) {
+		pci_write_config32(dev, 0x60, config->pirq_a_d);
+	}
+	if(config->pirq_e_h) {
+		pci_write_config32(dev, 0x68, config->pirq_e_h);
+	}
+}
+
+
+static void esb6300_gpio_init(device_t dev)
+{
+	struct resource *res;
+	config_t *config;
+
+	/* Skip if I don't have any configuration */
+	if (!dev->chip_info) {
+		return;
+	}
+	/* The programmer is responsible for ensuring
+	 * a valid gpio configuration.
+	 */
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+	/* Find the GPIO bar */
+	res = find_resource(dev, GPIO_BAR);
+	if (!res) {
+		return;
+	}
+
+	/* Set the use selects */
+	set_esb6300_gpio_use_sel(dev, res, config);
+
+	/* Set the IO direction */
+	set_esb6300_gpio_direction(dev, res, config);
+
+	/* Setup the input inverters */
+	set_esb6300_gpio_inv(dev, res, config);
+
+	/* Set the value on the GPIO output pins */
+	set_esb6300_gpio_level(dev, res, config);
+
+}
+
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	uint32_t value;
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+	/* sata settings */
+	pci_write_config32(dev, 0x58, 0x00001181);
+
+	/* IO APIC initialization */
+	value = pci_read_config32(dev, 0xd0);
+	value |= (1 << 8)|(1<<7);
+	value |= (6 << 0)|(1<<13)|(1<<11);
+	pci_write_config32(dev, 0xd0, value);
+	setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
+
+	/* disable reset timer */
+	pci_write_config8(dev, 0xd4, 0x02);
+
+	/* cmos ram 2nd 128 */
+	pci_write_config8(dev, 0xd8, 0x04);
+
+	/* comm 2 */
+	pci_write_config8(dev, 0xe0, 0x10);
+
+	/* fwh sellect */
+	pci_write_config32(dev, 0xe8, 0x00112233);
+
+	/* fwh decode */
+	pci_write_config8(dev, 0xf0, 0x0f);
+
+	/* av disable, sata controller */
+	pci_write_config8(dev, 0xf2, 0xc0);
+
+	/* undocumented */
+	pci_write_config8(dev, 0xa0, 0x20);
+	pci_write_config8(dev, 0xad, 0x03);
+	pci_write_config8(dev, 0xbb, 0x09);
+
+	/* apic1 rout */
+	pci_write_config8(dev, 0xf4, 0x40);
+
+	/* undocumented */
+	pci_write_config8(dev, 0xa0, 0x20);
+	pci_write_config8(dev, 0xad, 0x03);
+	pci_write_config8(dev, 0xbb, 0x09);
+
+	esb6300_enable_serial_irqs(dev);
+
+	esb6300_pci_dma_cfg(dev);
+
+	esb6300_enable_lpc(dev);
+
+        get_option(&pwr_on, "power_on_after_fail");
+	byte = pci_read_config8(dev, 0xa4);
+	byte &= 0xfe;
+	if (!pwr_on) {
+		byte |= 1;
+	}
+	pci_write_config8(dev, 0xa4, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
+
+	/* Set up the PIRQ */
+	esb6300_pirq_init(dev);
+
+	/* Set the state of the gpio lines */
+	esb6300_gpio_init(dev);
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void esb6300_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI BAR */
+	res = pci_get_resource(dev, ACPI_BAR);
+
+	/* Add the GPIO BAR */
+	res = pci_get_resource(dev, GPIO_BAR);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void esb6300_lpc_enable_resources(device_t dev)
+{
+	uint8_t acpi_cntl, gpio_cntl;
+
+	/* Enable the normal pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI bar */
+	acpi_cntl = pci_read_config8(dev, 0x44);
+	acpi_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x44, acpi_cntl);
+
+	/* Enable the GPIO bar */
+	gpio_cntl = pci_read_config8(dev, 0x5c);
+	gpio_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x5c, gpio_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = esb6300_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = esb6300_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_LPC,
+};

Copied: trunk/src/southbridge/intel/esb6300/pci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_pci.c)
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void pci_init(struct device *dev)
+{
+
+	uint16_t word;
+
+	/* Clear system errors */
+	word = pci_read_config16(dev, 0x06);
+	word |= 0xf900; /* Clear possible errors */
+	pci_write_config16(dev, 0x06, word);
+
+	word = pci_read_config16(dev, 0x1e);
+	word |= 0xf800; /* Clear possible errors */
+	pci_write_config16(dev, 0x1e, word);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/pic.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/pic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_pic.c)
@@ -0,0 +1,68 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/ioapic.h>
+#include "esb6300.h"
+
+static void pic_init(struct device *dev)
+{
+
+	uint16_t word;
+
+	/* Clear system errors */
+	word = pci_read_config16(dev, 0x06);
+	word |= 0xf900; /* Clear possible errors */
+	pci_write_config16(dev, 0x06, word);
+
+	/* enable interrupt lines */
+	pci_write_config8(dev, 0x3c, 0xff);
+
+	/* Setup the ioapic */
+	clear_ioapic(IO_APIC_ADDR + 0x10000);
+}
+
+static void pic_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Report the pic1 mbar resource */
+	res = new_resource(dev, 0x44);
+	res->base  = IO_APIC_ADDR + 0x10000;
+	res->size  = 256;
+	res->limit = res->base + res->size -1;
+	res->align = 8;
+	res->gran  = 8;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+}
+
+static struct pci_operations lops_pci = {
+	/* Can we set the pci subsystem and device id? */
+	.set_subsystem = 0,
+};
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pic_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = pic_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_APIC1,
+};
+

Copied: trunk/src/southbridge/intel/esb6300/reset.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_reset.c)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9 */
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/intel/esb6300/sata.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_sata.c)
@@ -0,0 +1,75 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void sata_init(struct device *dev)
+{
+	/* Enable sata devices so the linux sata driver will work */
+
+	/* Enable SATA devices */
+
+	printk(BIOS_DEBUG, "SATA init\n");
+        /* SATA configuration */
+        pci_write_config8(dev, 0x04, 0x07);
+        pci_write_config8(dev, 0x09, 0x8f);
+
+        /* Set timmings */
+        pci_write_config16(dev, 0x40, 0x0a307);
+        pci_write_config16(dev, 0x42, 0x0a307);
+
+        /* Sync DMA */
+        pci_write_config16(dev, 0x48, 0x000f);
+        pci_write_config16(dev, 0x4a, 0x1111);
+
+        /* 66 mhz */
+        pci_write_config16(dev, 0x54, 0xf00f);
+
+        /* Combine ide - sata configuration */
+        pci_write_config8(dev, 0x90, 0x0);
+
+        /* port 0 & 1 enable */
+        pci_write_config8(dev, 0x92, 0x33);
+
+        /* initialize SATA  */
+        pci_write_config16(dev, 0xa0, 0x0018);
+        pci_write_config32(dev, 0xa4, 0x00000264);
+        pci_write_config16(dev, 0xa0, 0x0040);
+        pci_write_config32(dev, 0xa4, 0x00220043);
+
+	printk(BIOS_DEBUG, "SATA Enabled\n");
+}
+
+static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* This value is also visible in usb1, usb2 and smbus functions */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = esb6300_sata_set_subsystem,
+};
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+        .ops    = &sata_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA,
+};
+
+static const struct pci_driver sata_driver_nr __pci_driver = {
+        .ops    = &sata_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID,
+};
+

Copied and modified: trunk/src/southbridge/intel/esb6300/smbus.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/esb6300/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "esb6300.h"
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/esb6300/smbus.h (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_smbus.h)
@@ -0,0 +1,101 @@
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#include <delay.h>
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		udelay(100);
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while(byte & 1);
+	return loops?0:-1;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        udelay(100);
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+	return loops?0:-1;
+}
+
+static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        udelay(100);
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte&(1<<7)) == 0);
+	return loops?0:-1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/esb6300/uhci.c (from r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/esb6300/uhci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/esb6300/esb6300_uhci.c)
@@ -0,0 +1,57 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "esb6300.h"
+
+static void uhci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+#if 1
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	/* The subsystem id follows the ide controller */
+	.set_subsystem = 0,
+};
+
+static struct device_operations uhci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = uhci_init,
+	.scan_bus         = 0,
+	.enable           = esb6300_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver usb1_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB1,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_USB2,
+};
+
+/* Note: May or may not need different init than UHCI. */
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
+};
+

Modified: trunk/src/southbridge/intel/i3100/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i3100/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i3100/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,9 +1,9 @@
 driver-y += i3100.c
-driver-y += i3100_uhci.c
-driver-y += i3100_lpc.c
-driver-y += i3100_sata.c
-driver-y += i3100_ehci.c
-driver-y += i3100_smbus.c
-driver-y += i3100_pci.c
-ramstage-y += i3100_reset.c
-ramstage-y += i3100_pciexp_portb.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+ramstage-y += reset.c
+ramstage-y += pciexp_portb.c

Copied: trunk/src/southbridge/intel/i3100/early_lpc.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/early_lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_early_lpc.c)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+static void i3100_enable_superio(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Enable decoding of I/O locations for SuperIO devices */
+	pci_write_config16(dev, 0x80, 0x0010);
+	pci_write_config16(dev, 0x82, 0x340f);
+
+	/* Enable the SERIRQs (start pulse width is 8 clock cycles) */
+	pci_write_config8(dev, 0x64, 0xD2);
+}
+
+static void i3100_halt_tco_timer(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Temporarily enable the ACPI I/O range at 0x4000 */
+	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(0x4068) | (1 << 11), 0x4068);
+
+	/* Disable the ACPI I/O range */
+	pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));
+}

Copied and modified: trunk/src/southbridge/intel/i3100/early_smbus.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i3100/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  *
  */
 
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 

Copied: trunk/src/southbridge/intel/i3100/ehci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_ehci.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void ehci_init(struct device *dev)
+{
+}
+
+static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+	access_cntl = pci_read_config8(dev, 0x80);
+	/* Enable writes to protected registers */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+	/* Restore protection */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &ehci_set_subsystem,
+};
+static struct device_operations ehci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ehci_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_EHCI,
+};
+
+static const struct pci_driver ehci_driver_ep80579 __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_EHCI,
+};

Copied: trunk/src/southbridge/intel/i3100/lpc.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_lpc.c)
@@ -0,0 +1,433 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Linux Networx
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i3100.h"
+
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x48
+#define RCBA 0xf0
+
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+static void i3100_enable_serial_irqs(device_t dev)
+{
+	/* set packet length and toggle silent mode bit */
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+}
+
+typedef struct southbridge_intel_i3100_config config_t;
+
+static void set_i3100_gpio_use_sel(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_use_sel, gpio_use_sel2;
+	int i;
+
+	gpio_use_sel = inl(res->base + 0x00) | 0x0000c603;
+	gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100;
+	for (i = 0; i < 64; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_USE_MASK) {
+		case I3100_GPIO_USE_AS_NATIVE:
+			val = 0;
+			break;
+		case I3100_GPIO_USE_AS_GPIO:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_use_sel &= ~(1 << i);
+			gpio_use_sel |= (val << i);
+		} else {
+			gpio_use_sel2 &= ~(1 << (i - 32));
+			gpio_use_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_use_sel, res->base + 0x00);
+	outl(gpio_use_sel2, res->base + 0x30);
+}
+
+static void set_i3100_gpio_direction(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_io_sel, gpio_io_sel2;
+	int i;
+
+	gpio_io_sel = inl(res->base + 0x04);
+	gpio_io_sel2 = inl(res->base + 0x34);
+	for (i = 0; i < 64; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_SEL_MASK) {
+		case I3100_GPIO_SEL_OUTPUT:
+			val = 0;
+			break;
+		case I3100_GPIO_SEL_INPUT:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_io_sel &= ~(1 << i);
+			gpio_io_sel |= (val << i);
+		} else {
+			gpio_io_sel2 &= ~(1 << (i - 32));
+			gpio_io_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_io_sel, res->base + 0x04);
+	outl(gpio_io_sel2, res->base + 0x34);
+}
+
+static void set_i3100_gpio_level(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_lvl, gpio_lvl2;
+	u32 gpio_blink;
+	int i;
+
+	gpio_lvl = inl(res->base + 0x0c);
+	gpio_blink = inl(res->base + 0x18);
+	gpio_lvl2 = inl(res->base + 0x38);
+	for (i = 0; i < 64; i++) {
+		int val, blink;
+		switch (config->gpio[i] & I3100_GPIO_LVL_MASK) {
+		case I3100_GPIO_LVL_LOW:
+			val = 0;
+			blink = 0;
+			break;
+		case I3100_GPIO_LVL_HIGH:
+			val = 1;
+			blink = 0;
+			break;
+		case I3100_GPIO_LVL_BLINK:
+			val = 1;
+			blink = 1;
+			break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_lvl &= ~(1 << i);
+			gpio_blink &= ~(1 << i);
+			gpio_lvl |= (val << i);
+			gpio_blink |= (blink << i);
+		} else {
+			gpio_lvl2 &= ~(1 << (i - 32));
+			gpio_lvl2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_lvl, res->base + 0x0c);
+	outl(gpio_blink, res->base + 0x18);
+	outl(gpio_lvl2, res->base + 0x38);
+}
+
+static void set_i3100_gpio_inv(
+	device_t dev, struct resource *res, config_t *config)
+{
+	u32 gpio_inv;
+	int i;
+
+	gpio_inv = inl(res->base + 0x2c);
+	for (i = 0; i < 32; i++) {
+		int val;
+		switch (config->gpio[i] & I3100_GPIO_INV_MASK) {
+		case I3100_GPIO_INV_OFF:
+			val = 0;
+			break;
+		case I3100_GPIO_INV_ON:
+			val = 1;
+			break;
+		default:
+			continue;
+		}
+		gpio_inv &= ~(1 << i);
+		gpio_inv |= (val << i);
+	}
+	outl(gpio_inv, res->base + 0x2c);
+}
+
+static void i3100_pirq_init(device_t dev)
+{
+	config_t *config;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->pirq_a_d) {
+		pci_write_config32(dev, 0x60, config->pirq_a_d);
+	}
+	if(config->pirq_e_h) {
+		pci_write_config32(dev, 0x68, config->pirq_e_h);
+	}
+}
+
+static void i3100_power_options(device_t dev) {
+  u8 reg8;
+  u16 reg16;
+  int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+  int nmi_option;
+
+  /* Which state do we want to goto after g3 (power restored)?
+   * 0 == S0 Full On
+   * 1 == S5 Soft Off
+   */
+  get_option(&pwr_on, "power_on_after_fail");
+  reg8 = pci_read_config8(dev, GEN_PMCON_3);
+  reg8 &= 0xfe;
+  if (pwr_on) {
+    reg8 &= ~1;
+  } else {
+    reg8 |= 1;
+  }
+  /* avoid #S4 assertions */
+  reg8 |= (3 << 4);
+  /* minimum asssertion is 1 to 2 RTCCLK */
+  reg8 &= ~(1 << 3);
+  pci_write_config8(dev, GEN_PMCON_3, reg8);
+  printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
+
+  /* Set up NMI on errors. */
+  reg8 = inb(0x61);
+  /* Higher Nibble must be 0 */
+  reg8 &= 0x0f;
+  /* IOCHK# NMI Enable */
+  reg8 &= ~(1 << 3);
+  /* PCI SERR# Enable */
+  // reg8 &= ~(1 << 2);
+  /* PCI SERR# Disable for now */
+  reg8 |= (1 << 2);
+  outb(reg8, 0x61);
+
+  reg8 = inb(0x70);
+  nmi_option = NMI_OFF;
+  get_option(&nmi_option, "nmi");
+  if (nmi_option) {
+    /* Set NMI. */
+    printk(BIOS_INFO, "NMI sources enabled.\n");
+    reg8 &= ~(1 << 7);
+  } else {
+    /* Can't mask NMI from PCI-E and NMI_NOW */
+    printk(BIOS_INFO, "NMI sources disabled.\n");
+    reg8 |= ( 1 << 7);
+  }
+  outb(reg8, 0x70);
+
+  // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+  reg16 = pci_read_config16(dev, GEN_PMCON_1);
+  reg16 &= ~((3 << 0) | (1 << 10));
+  reg16 |= (1 << 3) | (1 << 5);
+  /* CLKRUN_EN */
+  // reg16 |= (1 << 2);
+  pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+  // Set the board's GPI routing.
+  // i82801gx_gpi_routing(dev);
+}
+
+static void i3100_gpio_init(device_t dev)
+{
+	struct resource *res;
+	config_t *config;
+
+	/* Skip if I don't have any configuration */
+	if (!dev->chip_info) {
+		return;
+	}
+	/* The programmer is responsible for ensuring
+	 * a valid gpio configuration.
+	 */
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+	/* Find the GPIO bar */
+	res = find_resource(dev, GPIO_BAR);
+	if (!res) {
+		return;
+	}
+
+	/* Set the use selects */
+	set_i3100_gpio_use_sel(dev, res, config);
+
+	/* Set the IO direction */
+	set_i3100_gpio_direction(dev, res, config);
+
+	/* Setup the input inverters */
+	set_i3100_gpio_inv(dev, res, config);
+
+	/* Set the value on the GPIO output pins */
+	set_i3100_gpio_level(dev, res, config);
+
+}
+
+
+static void lpc_init(struct device *dev)
+{
+	struct resource *res;
+
+	/* Enable IO APIC */
+	res = find_resource(dev, RCBA);
+	if (!res) {
+		return;
+	}
+	*((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0);
+
+	// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+	// (register 0x10/0x11) while the old code used int 1 (register 0x12)
+	// ... Why?
+	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
+
+	/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
+	pci_write_config32(dev, 0xd0, 0x00000000);
+
+	i3100_enable_serial_irqs(dev);
+
+	/* Set up the PIRQ */
+	i3100_pirq_init(dev);
+
+	/* Setup power options */
+	i3100_power_options(dev);
+
+	/* Set the state of the gpio lines */
+	i3100_gpio_init(dev);
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+}
+
+static void i3100_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI BAR */
+	res = pci_get_resource(dev, ACPI_BAR);
+
+	/* Add the GPIO BAR */
+	res = pci_get_resource(dev, GPIO_BAR);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	/* Add resource for RCBA */
+	res = new_resource(dev, RCBA);
+	res->size = 0x4000;
+	res->limit = 0xffffc000;
+	res->align = 14;
+	res->gran = 14;
+	res->flags = IORESOURCE_MEM;
+}
+
+static void i3100_lpc_enable_resources(device_t dev)
+{
+	u8 acpi_cntl, gpio_cntl;
+
+	/* Enable the normal pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI bar */
+	acpi_cntl = pci_read_config8(dev, 0x44);
+	acpi_cntl |= (1 << 7);
+	pci_write_config8(dev, 0x44, acpi_cntl);
+
+	/* Enable the GPIO bar */
+	gpio_cntl = pci_read_config8(dev, 0x4c);
+	gpio_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x4c, gpio_cntl);
+
+	/* Enable the RCBA */
+	pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = i3100_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = i3100_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_LPC,
+};
+
+static const struct pci_driver lpc_driver_ep80579 __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_LPC,
+};

Copied: trunk/src/southbridge/intel/i3100/pci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_pci.c)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void pci_init(struct device *dev)
+{
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCI,
+};
+

Copied: trunk/src/southbridge/intel/i3100/pciexp_portb.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/pciexp_portb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c)
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <reset.h>
+
+#define PCIE_LCTL 0x50
+#define PCIE_LSTS 0x52
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+}
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+	u16 val;
+	u16 ctl;
+	int flag = 0;
+	do {
+		val = pci_read_config16(dev, PCIE_LSTS);
+		printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);
+		if ((val & (1<<10)) && (!flag)) { /* training error */
+			ctl = pci_read_config16(dev, PCIE_LCTL);
+			pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
+			val = pci_read_config16(dev, PCIE_LSTS);
+			printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);
+			flag=1;
+			hard_reset();
+		}
+	} while	(val & (3<<10));
+	return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pcie_init,
+	.scan_bus         = pcie_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver_0 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
+};
+
+static const struct pci_driver pci_driver_1 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
+};
+
+static const struct pci_driver pci_driver_2 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
+};
+
+static const struct pci_driver pci_driver_3 __pci_driver = {
+	.ops    = &pcie_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
+};

Copied: trunk/src/southbridge/intel/i3100/reset.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_reset.c)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	outb(0x06, 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i3100/sata.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_sata.c)
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+typedef struct southbridge_intel_i3100_config config_t;
+
+static void sata_init(struct device *dev)
+{
+        u8 ahci;
+
+	/* Get the chip configuration */
+	ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
+
+	/* Enable SATA devices */
+	printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
+
+	if(ahci) {
+	  /* AHCI mode */
+	  pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
+
+	  /* Enable ports */
+	  pci_write_config8(dev, SATA_PCS, 0x03);
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0F);
+
+	  /* Setup timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x8000);
+	  pci_write_config16(dev, SATA_STIM, 0x8000);
+
+	  /* Synchronous DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0);
+
+	  /* IDE I/O configuration */
+	  pci_write_config32(dev, SATA_IIOC, 0);
+
+	} else {
+	  /* SATA configuration */
+	  pci_write_config8(dev, SATA_CMD, 0x07);
+	  pci_write_config8(dev, SATA_PI, 0x8f);
+
+	  /* Set timings */
+	  pci_write_config16(dev, SATA_PTIM, 0x0a307);
+	  pci_write_config16(dev, SATA_STIM, 0x0a307);
+
+	  /* Sync DMA */
+	  pci_write_config8(dev, SATA_SYNCC, 0x0f);
+	  pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
+
+	  /* Fast ATA */
+	  pci_write_config16(dev, SATA_IIOC, 0x1000);
+
+	  /* Select IDE mode */
+	  pci_write_config8(dev, SATA_MAP, 0x00);
+
+	  /* Enable ports 0-3 */
+	  pci_write_config8(dev, SATA_PCS + 1, 0x0f);
+
+	}
+	printk(BIOS_DEBUG, "SATA Enabled\n");
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_IDE,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_AHCI,
+};
+
+static const struct pci_driver ide_driver_ep80579 __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_IDE,
+};
+
+static const struct pci_driver sata_driver_ep80579 __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,
+};

Copied and modified: trunk/src/southbridge/intel/i3100/smbus.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i3100/i3100_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i3100/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "i3100.h"
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i3100/smbus.h (from r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_smbus.h)
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */
+
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+#define SMBSLVCMD  0x11
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+static void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
+{
+	u8 global_status_register;
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i3100/uhci.c (from r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i3100/uhci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i3100/i3100_uhci.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i3100.h"
+
+static void uhci_init(struct device *dev)
+{
+}
+
+static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &uhci_set_subsystem,
+};
+
+static struct device_operations uhci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = uhci_init,
+	.scan_bus         = 0,
+	.enable           = i3100_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver uhci_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_UHCI,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_3100_UHCI2,
+};
+
+static const struct pci_driver uhci_driver_ep80579 __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_EP80579_UHCI,
+};

Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82371eb/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,13 +19,13 @@
 ##
 
 driver-y +=  i82371eb.c
-driver-y +=  i82371eb_isa.c
-driver-y +=  i82371eb_ide.c
-driver-y +=  i82371eb_usb.c
-driver-y +=  i82371eb_smbus.c
-driver-y +=  i82371eb_reset.c
-driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
+driver-y +=  isa.c
+driver-y +=  ide.c
+driver-y +=  usb.c
+driver-y +=  smbus.c
+driver-y +=  reset.c
+driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
 
-romstage-y += i82371eb_early_pm.c
-romstage-y += i82371eb_early_smbus.c
+romstage-y += early_pm.c
+romstage-y += early_smbus.c

Modified: trunk/src/southbridge/intel/i82371eb/bootblock.c
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/bootblock.c	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82371eb/bootblock.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {

Copied: trunk/src/southbridge/intel/i82371eb/early_pm.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/early_pm.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+void enable_pm(void)
+{
+	device_t dev;
+	u8 reg8;
+	u16 reg16;
+
+	/* Get the SMBus/PM device of the 82371AB/EB/MB. */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
+
+	/* Set the PM I/O base. */
+	pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
+
+	/* Enable access to the PM I/O space. */
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_IO;
+	pci_write_config16(dev, PCI_COMMAND, reg16);
+
+	/* PM I/O Space Enable (PMIOSE). */
+	reg8 = pci_read_config8(dev, PMREGMISC);
+	reg8 |= PMIOSE;
+	pci_write_config8(dev, PMREGMISC, reg8);
+}

Copied and modified: trunk/src/southbridge/intel/i82371eb/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82371eb/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -25,7 +25,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82371eb/enable_rom.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/enable_rom.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c)
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+static void i82371eb_enable_rom(void)
+{
+	u16 reg16;
+	device_t dev;
+
+	/*
+	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
+	 * PCI bus:device.function locations on different boards.
+	 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
+	 * But scanning for the PCI IDs (instead of hardcoding
+	 * bus/device/function numbers) works on all boards.
+	 */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
+
+	/* Enable access to the whole ROM, disable ROM write access. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= LOWER_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE;
+	reg16 |= EXT_BIOS_ENABLE_1MB;
+	reg16 &= ~(WRITE_PROTECT_ENABLE);	/* Disable ROM write access. */
+	pci_write_config16(dev, XBCS, reg16);
+}

Copied: trunk/src/southbridge/intel/i82371eb/fadt.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/fadt.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_fadt.c)
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9 at btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ * Reference: ACPIspec40a, 5.2.9, page 118
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	device_t dev;
+
+	/* Power management controller */
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 42;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = 0; /* unspecified */
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0; /* smi command port */
+	fadt->acpi_enable = 0; /* acpi enable smi command */
+	fadt->acpi_disable = 0; /* acpi disable smi command */
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = DEFAULT_PMBASE;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
+	fadt->pm1b_cnt_blk = 0x0;
+
+	fadt->pm2_cnt_blk = 0;
+	fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
+	fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
+	fadt->gpe1_blk = 0x0;
+	fadt->gpe1_base = 0;
+	fadt->gpe1_blk_len = 0;
+
+	/* *_len define register width in bytes */
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0; /* not supported */
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 4;
+
+	fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
+	fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
+	fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
+	fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
+	fadt->duty_width = 3; /* this width is in bits */
+	fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+	fadt->mon_alrm = 0x0; /* not supported */
+	fadt->century = 0x0; /* not supported */
+	/*
+	 * bit  meaning
+	 * 0    1: We have user-visible legacy devices
+	 * 1    1: 8042
+	 * 2    0: VGA is ok to probe
+	 * 3    1: MSI are not supported
+	 */
+	fadt->iapc_boot_arch = 0xb;
+	/*
+	 * bit  meaning
+	 * 0    WBINVD
+	 *      Processors in new ACPI-compatible systems are required to
+	 *      support this function and indicate this to OSPM by setting
+	 *      this field.
+	 * 1    WBINVD_FLUSH
+	 *      If set, indicates that the hardware flushes all caches on the
+	 *      WBINVD instruction and maintains memory coherency, but does
+	 *      not guarantee the caches are invalidated.
+	 * 2    PROC_C1
+	 *      C1 power state (x86 hlt instruction) is supported on all cpus
+	 * 3    P_LVL2_UP
+	 *      0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
+	 * 4    PWR_BUTTON
+	 *      0: pwr button is fixed feature
+	 *      1: pwr button has control method device if present
+	 * 5    SLP_BUTTON
+	 *      0: sleep button is fixed feature
+	 *      1: sleep button has control method device if present
+	 * 6    FIX_RTC
+	 *      0: RTC wake status supported in fixed register spce
+	 * 7    RTC_S4
+	 *      1: RTC can wake from S4
+	 * 8    TMR_VAL_EXT
+	 *      1: pmtimer is 32bit, 0: pmtimer is 24bit
+	 * 9    DCK_CAP
+	 *      1: system supports docking station
+	 * 10   RESET_REG_SUPPORT
+	 *      1: fadt describes reset register for system reset
+	 * 11   SEALED_CASE
+	 *      1: No expansion possible, sealed case
+	 * 12   HEADLESS
+	 *      1: Video output, keyboard and mouse are not connected
+	 * 13   CPU_SW_SLP
+	 *      1: Special processor instruction needs to be executed
+	 *      after writing SLP_TYP
+	 * 14   PCI_EXP_WAK
+	 *      1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
+	 *      on platforms with pci express support
+	 * 15   USE_PLATFORM_CLOCK
+	 *      1: OS should prefer platform clock over processor internal
+	 *      clock.
+	 * 16   S4_RTC_STS_VALID
+	 * 17   REMOTE_POWER_ON_CAPABLE
+	 *      1: platform correctly supports OSPM leaving GPE wake events
+	 *      armed prior to an S5 transition.
+	 * 18   FORCE_APIC_CLUSTER_MODEL
+	 * 19   FORCE_APIC_PHYSICAL_DESTINATION_MODE
+	 */
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+	fadt->reset_value = 0;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}

Copied: trunk/src/southbridge/intel/i82371eb/ide.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* TODO: Check if this really works for all of the southbridges. */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
+ * enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * Depending on the configuration variable 'ide_legacy_enable' enable or
+ * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O
+ * registers (this is required for e.g. FILO).
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_enable(struct device *dev)
+{
+	u16 reg16;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+	/* Enable/disable the primary IDE interface. */
+	reg16 = pci_read_config16(dev, IDETIM_PRI);
+	reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_PRI, reg16);
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+		     conf->ide0_enable ? "on" : "off");
+
+	/* Enable/disable the secondary IDE interface. */
+	reg16 = pci_read_config16(dev, IDETIM_SEC);
+	reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE);
+	pci_write_config16(dev, IDETIM_SEC, reg16);
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+		     conf->ide1_enable ? "on" : "off");
+
+	/* Enable access to the legacy IDE ports (both primary and secondary),
+	 * and the PCI Bus Master IDE I/O registers.
+	 * Only do this if at least one IDE interface is enabled.
+	 */
+	if (conf->ide0_enable || conf->ide1_enable) {
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 = ONOFF(conf->ide_legacy_enable, reg16,
+			      (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+		printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n",
+			     conf->ide_legacy_enable ? "on" : "off");
+	}
+}
+
+/**
+ * Initialize the Ultra DMA/33 support of the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_drive0_udma33_enable',
+ * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and
+ * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for
+ * the respective IDE controller and drive.
+ *
+ * Only do that if the respective controller is actually enabled, of course.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_udma33(struct device *dev)
+{
+	u8 reg8;
+	struct southbridge_intel_i82371eb_config *conf = dev->chip_info;
+
+	/* Enable/disable UDMA/33 operation (primary IDE interface). */
+	if (conf->ide0_enable) {
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0);
+		reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 0,
+			     conf->ide0_drive0_udma33_enable ? "on" : "off");
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Primary IDE interface", 1,
+			     conf->ide0_drive1_udma33_enable ? "on" : "off");
+	}
+
+	/* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */
+	if (conf->ide1_enable) {
+		reg8 = pci_read_config8(dev, UDMACTL);
+		reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0);
+		reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1);
+		pci_write_config8(dev, UDMACTL, reg8);
+
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 0,
+			     conf->ide1_drive0_udma33_enable ? "on" : "off");
+		printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n",
+			     "Secondary IDE interface", 1,
+			     conf->ide1_drive1_udma33_enable ? "on" : "off");
+	}
+}
+
+/**
+ * IDE init for the Intel 82371FB/SB IDE controller.
+ *
+ * These devices do not support UDMA/33, so don't attempt to enable it.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371fb_sb(struct device *dev)
+{
+	ide_init_enable(dev);
+}
+
+/**
+ * IDE init for the Intel 82371AB/EB/MB IDE controller.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init_i82371ab_eb_mb(struct device *dev)
+{
+	ide_init_enable(dev);
+	ide_init_udma33(dev);
+}
+
+/* Intel 82371FB/SB */
+static const struct device_operations ide_ops_fb_sb = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init_i82371fb_sb,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371AB/EB/MB */
+static const struct device_operations ide_ops_ab_eb_mb = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init_i82371ab_eb_mb,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371XX! */
+};
+
+/* Intel 82371FB (PIIX) */
+static const struct pci_driver ide_driver_fb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371FB_IDE,
+};
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver ide_driver_sb __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_IDE,
+};
+
+/* Intel 82371MX (MPIIX) */
+static const struct pci_driver ide_driver_mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE,
+};
+
+/* Intel 82437MX (part of the 430MX chipset) */
+static const struct pci_driver ide_driver_82437mx __pci_driver = {
+	.ops	= &ide_ops_fb_sb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE,
+};
+
+/* Intel 82371AB/EB/MB */
+static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = {
+	.ops	= &ide_ops_ab_eb_mb,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_IDE,
+};

Copied: trunk/src/southbridge/intel/i82371eb/isa.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/isa.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c)
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/isa-dma.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
+#include "i82371eb.h"
+
+#if CONFIG_IOAPIC
+static void enable_intel_82093aa_ioapic(void)
+{
+	u16 reg16;
+	u32 reg32;
+	u8 ioapic_id = 2;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+	device_t dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
+
+	/* Enable IOAPIC. */
+	reg16 = pci_read_config16(dev, XBCS);
+	reg16 |= (1 << 8); /* APIC Chip Select */
+	pci_write_config16(dev, XBCS, reg16);
+
+	/* Set the IOAPIC ID. */
+	*ioapic_index = 0;
+	*ioapic_data = ioapic_id << 24;
+
+	/* Read back and verify the IOAPIC ID. */
+	*ioapic_index = 0;
+	reg32 = (*ioapic_data >> 24) & 0x0f;
+	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+	if (reg32 != ioapic_id)
+		die("IOAPIC error!\n");
+}
+#endif
+
+static void isa_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Initialize the real time clock (RTC). */
+	rtc_init(0);
+
+	/*
+	 * Enable special cycles, needed for soft poweroff.
+	 */
+	reg32 = pci_read_config16(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_SPECIAL;
+	pci_write_config16(dev, PCI_COMMAND, reg32);
+
+	/*
+	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
+	 * bus, which is a subset of ISA. We select the full ISA bus here.
+	 */
+	reg32 = pci_read_config32(dev, GENCFG);
+	reg32 |= ISA;	/* Select ISA, not EIO. */
+	pci_write_config16(dev, GENCFG, reg32);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+#if CONFIG_IOAPIC
+	/*
+	 * Unlike most other southbridges the 82371EB doesn't have a built-in
+	 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
+	 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
+	 *
+	 * Thus, we can/must only enable the IOAPIC if it actually exists,
+	 * i.e. the respective mainboard does "select IOAPIC".
+	 */
+	enable_intel_82093aa_ioapic();
+#endif
+}
+
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 2);
+	res->base = 0xff800000UL;
+	res->size = 0x00800000UL; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+
+#if CONFIG_IOAPIC
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
+		IORESOURCE_RESERVE;
+#endif
+}
+
+static const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= isa_init,
+	.scan_bus		= scan_static_bus,	/* TODO: Needed? */
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+static const struct pci_driver isa_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_ISA,
+};
+
+static const struct pci_driver isa_SB_driver __pci_driver = {
+	.ops	= &isa_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_ISA,
+};

Copied: trunk/src/southbridge/intel/i82371eb/reset.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_reset.c)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "i82371eb.h"
+
+/**
+ * Initiate a hard reset.
+ */
+void i82371eb_hard_reset(void)
+{
+	outb(SRST | RCPU, RC);
+}

Copied and modified: trunk/src/southbridge/intel/i82371eb/smbus.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82371eb/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -29,7 +29,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 static void pwrmgt_enable(struct device *dev)
 {

Copied: trunk/src/southbridge/intel/i82371eb/smbus.h (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h)
@@ -0,0 +1,115 @@
+#include <device/smbus_def.h>
+#include "i82371eb.h"
+
+#define SMBHST_STATUS 	0x0
+#define SMBHST_CTL    	0x2
+#define SMBHST_CMD  	0x3
+#define SMBHST_ADDR 	0x4
+#define SMBHST_DAT  	0x5
+
+#define SMBUS_TIMEOUT (100*1000*10)
+#define SMBUS_STATUS_MASK 0x1e
+#define SMBUS_ERROR_FLAG (1<<2)
+
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(smbus_io_base + SMBHST_STATUS);
+		if ((val & 0x1) == 0) {
+			break;
+		}
+#if 0
+		if(loops == (SMBUS_TIMEOUT / 2)) {
+			outw(inw(smbus_io_base + SMBHST_STATUS),
+				smbus_io_base + SMBHST_STATUS);
+		}
+#endif
+	} while(--loops);
+	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned short val;
+		smbus_delay();
+
+		val = inb(smbus_io_base + SMBHST_STATUS);
+		// Make sure the command is done
+		if ((val & 0x1) != 0) {
+			continue;
+		}
+		// Don't break out until one of the interrupt
+		// flags is set.
+		if (val & 0xfe) {
+			break;
+		}
+	} while(--loops);
+	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+}
+
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned status_register;
+	unsigned byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+
+	/* setup transaction */
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(0x1e, smbus_io_base + SMBHST_STATUS);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR);
+
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHST_CMD);
+
+	/* clear the data word...*/
+	outb(0, smbus_io_base + SMBHST_DAT);
+
+	/* start a byte read with interrupts disabled */
+	outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	status_register = inw(smbus_io_base + SMBHST_STATUS);
+
+	/* read results of transaction */
+	byte = inw(smbus_io_base + SMBHST_DAT) & 0xff;
+
+	if (status_register & 0x04) {
+#if 0
+ 		print_debug("Read fail ");
+		print_debug_hex16(status_register);
+		print_debug("\n");
+#endif
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/i82371eb/usb.c (from r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82371eb/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82371eb/i82371eb_usb.c)
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the USB (UHCI) controller.
+ *
+ * Depending on the configuration variable 'usb_enable', enable or
+ * disable the USB (UHCI) controller.
+ *
+ * @param dev The device to use.
+ */
+static void usb_init(struct device *dev)
+{
+	/* TODO: No special init needed? */
+}
+
+static const struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */
+};
+
+/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */
+
+/* Intel 82371SB (PIIX3) */
+static const struct pci_driver usb_driver_sb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371SB_USB,
+};
+
+/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */
+/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */
+static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_USB,
+};

Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801ax/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,15 +19,15 @@
 ##
 
 driver-y += i82801ax.c
-driver-y += i82801ax_ac97.c
-driver-y += i82801ax_ide.c
-driver-y += i82801ax_lpc.c
-driver-y += i82801ax_pci.c
-driver-y += i82801ax_smbus.c
-driver-y += i82801ax_usb.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += pci.c
+driver-y += smbus.c
+driver-y += usb.c
 
-ramstage-y += i82801ax_reset.c
-ramstage-y += i82801ax_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-romstage-y += i82801ax_early_smbus.c
+romstage-y += early_smbus.c
 

Copied: trunk/src/southbridge/intel/i82801ax/ac97.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c)
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+static struct device_operations ac97_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
+};

Copied and modified: trunk/src/southbridge/intel/i82801ax/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ax/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82801ax/ide.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c)
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ * Copyright (C) 2005 Digital Design Corporation
+ * (Written by Steven J. Magnani <steve at digidescorp.com> for Digital Design)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+typedef struct southbridge_intel_i82801ax_config config_t;
+
+static void ide_init(struct device *dev)
+{
+	u16 reg16;
+	config_t *conf = dev->chip_info;
+
+	reg16 = pci_read_config16(dev, IDE_TIM_PRI);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide0_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_PRI, reg16);
+
+	reg16 = pci_read_config16(dev, IDE_TIM_SEC);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide1_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_SEC, reg16);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2411,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2421,
+};

Copied: trunk/src/southbridge/intel/i82801ax/lpc.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c)
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2003 SuSE Linux AG
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801ax.h"
+
+#define GPIO_BASE_ADDR	0x00000500 /* GPIO Base Address Register */
+
+#define NMI_OFF 0
+
+typedef struct southbridge_intel_i82801ax_config config_t;
+
+/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ *
+ * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
+ * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
+ * 1 - The PIRQ is not routed to the 8259.
+ */
+
+#define PIRQA 0x03
+#define PIRQB 0x04
+#define PIRQC 0x05
+#define PIRQD 0x06
+
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your devicetree.cb.
+ */
+static void i82801ax_enable_apic(struct device *dev)
+{
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Enable ACPI I/O range decode and ACPI power management. */
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
+	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
+	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	/* TODO: From i82801ca, needed/useful on other ICH? */
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void i82801ax_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+	/* TODO: Explain/#define the real meaning of these magic numbers. */
+}
+
+static void i82801ax_pirq_init(device_t dev)
+{
+	u8 reg8;
+	config_t *config = dev->chip_info;
+
+	reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
+	pci_write_config8(dev, PIRQA_ROUT, reg8);
+
+	reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
+	pci_write_config8(dev, PIRQB_ROUT, reg8);
+
+	reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
+	pci_write_config8(dev, PIRQC_ROUT, reg8);
+
+	reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
+	pci_write_config8(dev, PIRQD_ROUT, reg8);
+}
+
+static void i82801ax_power_options(device_t dev)
+{
+	uint8_t byte;
+	int pwr_on = -1;
+	int nmi_option;
+
+	/* power after power fail */
+	/* FIXME this doesn't work! */
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 */
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
+
+	/* Set up NMI on errors. */
+	byte = inb(0x61);
+	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	byte &= ~(1 << 2);	/* PCI SERR# Enable */
+	outb(byte, 0x61);
+	byte = inb(0x70);
+
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* Set NMI. */
+		outb(byte, 0x70);
+	}
+}
+
+static void gpio_init(device_t dev)
+{
+	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
+}
+
+static void i82801ax_rtc_init(struct device *dev)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~(1 << 1);	/* Preserve the power fail state. */
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	reg32 = pci_read_config32(dev, GEN_STA);
+	rtc_failed |= reg32 & (1 << 2);
+	rtc_init(rtc_failed);
+
+	/* Enable access to the upper 128 byte bank of CMOS RAM. */
+	pci_write_config8(dev, RTC_CONF, 0x04);
+}
+
+static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
+{
+	uint16_t reg16;
+	int i;
+
+	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+	reg16 &= 0x300;
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, reg16);
+}
+
+static void i82801ax_lpc_decode_en(device_t dev)
+{
+	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+	 * We also need to set the value for LPC I/F Enables Register.
+	 */
+	pci_write_config8(dev, COM_DEC, 0x10);
+	pci_write_config16(dev, LPC_EN, 0x300F);
+}
+
+static void lpc_init(struct device *dev)
+{
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	i82801ax_enable_apic(dev);
+
+	i82801ax_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	i82801ax_pirq_init(dev);
+
+	/* Setup power options. */
+	i82801ax_power_options(dev);
+
+	/* Set the state of the GPIO lines. */
+	gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	i82801ax_rtc_init(dev);
+
+	/* Route DMA. */
+	i82801ax_lpc_route_dma(dev, 0xff);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Setup decode ports and LPC I/F enables. */
+	i82801ax_lpc_decode_en(dev);
+}
+
+static void i82801ax_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources		= i82801ax_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_lpc __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2410,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_lpc __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2420,
+};

Copied: trunk/src/southbridge/intel/i82801ax/pci.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c)
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+
+	/* Clear possible errors. */
+	reg16 = pci_read_config16(dev, PCI_STATUS);
+	reg16 |= 0xf900;
+	pci_write_config16(dev, PCI_STATUS, reg16);
+}
+
+static struct device_operations pci_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_pci __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2418,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_pci __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2428,
+};

Copied: trunk/src/southbridge/intel/i82801ax/reset.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm at xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
+}

Copied and modified: trunk/src/southbridge/intel/i82801ax/smbus.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ax/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i82801ax/smbus.h (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h)
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+#include "i82801ax.h"
+
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_io_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40),
+	     smbus_io_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i82801ax/usb.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801ax.h"
+
+static void usb_init(struct device *dev)
+{
+	/* TODO: Any init needed? Some ports have it, others don't. */
+}
+
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801ax_enable,
+};
+
+/* 82801AA (ICH) */
+static const struct pci_driver i82801aa_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AA_USB,
+};
+
+/* 82801AB (ICH0) */
+static const struct pci_driver i82801ab_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801AB_USB,
+};

Copied: trunk/src/southbridge/intel/i82801ax/watchdog.c (from r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ax/watchdog.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 John Dufresne <jon.dufresne at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
+
+void watchdog_off(void)
+{
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH5 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
+}

Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801bx/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -19,16 +19,16 @@
 ##
 
 driver-y += i82801bx.c
-driver-y += i82801bx_ac97.c
-driver-y += i82801bx_ide.c
-driver-y += i82801bx_lpc.c
-driver-y += i82801bx_nic.c
-driver-y += i82801bx_pci.c
-driver-y += i82801bx_smbus.c
-driver-y += i82801bx_usb.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += smbus.c
+driver-y += usb.c
 
-ramstage-y += i82801bx_reset.c
-ramstage-y += i82801bx_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-romstage-y += i82801bx_early_smbus.c
+romstage-y += early_smbus.c
 

Copied: trunk/src/southbridge/intel/i82801bx/ac97.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801bx.h"
+
+static struct device_operations ac97_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
+	.enable			= i82801bx_enable,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_ac97_audio __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801ba_ac97_modem __pci_driver = {
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM,
+};

Copied and modified: trunk/src/southbridge/intel/i82801bx/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801bx/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801bx.h"
-#include "i82801bx_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82801bx/ide.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ * Copyright (C) 2005 Digital Design Corporation
+ * (Written by Steven J. Magnani <steve at digidescorp.com> for Digital Design)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801bx.h"
+
+typedef struct southbridge_intel_i82801bx_config config_t;
+
+static void ide_init(struct device *dev)
+{
+	u16 reg16;
+	config_t *conf = dev->chip_info;
+
+	reg16 = pci_read_config16(dev, IDE_TIM_PRI);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide0_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_PRI, reg16);
+
+	reg16 = pci_read_config16(dev, IDE_TIM_SEC);
+	reg16 &= ~IDE_DECODE_ENABLE;
+	if (!conf || conf->ide1_enable)
+		reg16 |= IDE_DECODE_ENABLE;
+	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+	       conf->ide0_enable ? "on" : "off");
+	pci_write_config16(dev, IDE_TIM_SEC, reg16);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.enable			= i82801bx_enable,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x244b,
+};

Copied: trunk/src/southbridge/intel/i82801bx/lpc.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c)
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2003 SuSE Linux AG
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801bx.h"
+
+#define NMI_OFF 0
+
+typedef struct southbridge_intel_i82801bx_config config_t;
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ *
+ * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
+ * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
+ * 1 - The PIRQ is not routed to the 8259.
+ */
+
+#define PIRQA 0x03
+#define PIRQB 0x04
+#define PIRQC 0x05
+#define PIRQD 0x06
+#define PIRQE 0x07
+#define PIRQF 0x09
+#define PIRQG 0x0A
+#define PIRQH 0x0B
+
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your devicetree.cb.
+*/
+static void i82801bx_enable_apic(struct device *dev)
+{
+	uint32_t reg32;
+	volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR;
+	volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10);
+
+	/* Set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Enable ACPI I/O range decode and ACPI power management. */
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
+	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
+	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	/* TODO: From i82801ca, needed/useful on other ICH? */
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void i82801bx_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+	/* TODO: Explain/#define the real meaning of these magic numbers. */
+}
+
+static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
+{
+	u8 reg8;
+	config_t *config = dev->chip_info;
+
+	reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
+	pci_write_config8(dev, PIRQA_ROUT, reg8);
+
+	reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
+	pci_write_config8(dev, PIRQB_ROUT, reg8);
+
+	reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
+	pci_write_config8(dev, PIRQC_ROUT, reg8);
+
+	reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
+	pci_write_config8(dev, PIRQD_ROUT, reg8);
+
+
+	reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE;
+	pci_write_config8(dev, PIRQE_ROUT, reg8);
+
+	reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF;
+	pci_write_config8(dev, PIRQF_ROUT, reg8);
+
+	reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG;
+	pci_write_config8(dev, PIRQG_ROUT, reg8);
+
+	reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH;
+	pci_write_config8(dev, PIRQH_ROUT, reg8);
+}
+
+static void i82801bx_power_options(device_t dev)
+{
+	uint8_t byte;
+	int pwr_on = -1;
+	int nmi_option;
+
+	/* power after power fail */
+	/* FIXME this doesn't work! */
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 */
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
+
+	/* Set up NMI on errors. */
+	byte = inb(0x61);
+	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	byte &= ~(1 << 2);	/* PCI SERR# Enable */
+	outb(byte, 0x61);
+	byte = inb(0x70);
+
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* Set NMI. */
+		outb(byte, 0x70);
+	}
+}
+
+static void gpio_init(device_t dev)
+{
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
+}
+
+static void i82801bx_rtc_init(struct device *dev)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~(1 << 1);	/* Preserve the power fail state. */
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	reg32 = pci_read_config32(dev, GEN_STS);
+	rtc_failed |= reg32 & (1 << 2);
+	rtc_init(rtc_failed);
+
+	/* Enable access to the upper 128 byte bank of CMOS RAM. */
+	pci_write_config8(dev, RTC_CONF, 0x04);
+}
+
+static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
+{
+	uint16_t reg16;
+	int i;
+
+	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+	reg16 &= 0x300;
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, reg16);
+}
+
+static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
+{
+	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+	 * We also need to set the value for LPC I/F Enables Register.
+	 */
+	pci_write_config8(dev, COM_DEC, 0x10);
+	pci_write_config16(dev, LPC_EN, 0x300F);
+}
+
+static void lpc_init(struct device *dev)
+{
+	uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
+
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	i82801bx_enable_apic(dev);
+
+	i82801bx_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	i82801bx_pirq_init(dev, ich_model);
+
+	/* Setup power options. */
+	i82801bx_power_options(dev);
+
+	/* Set the state of the GPIO lines. */
+	gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	i82801bx_rtc_init(dev);
+
+	/* Route DMA. */
+	i82801bx_lpc_route_dma(dev, 0xff);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Setup decode ports and LPC I/F enables. */
+	i82801bx_lpc_decode_en(dev, ich_model);
+}
+
+static void i82801bx_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources		= i82801bx_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801bx_enable,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_lpc __pci_driver = {
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2440,
+};

Copied: trunk/src/southbridge/intel/i82801bx/nic.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static struct device_operations nic_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
+};

Copied: trunk/src/southbridge/intel/i82801bx/pci.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan Computer
+ * (Written by Yinghai Lu <yinghailu at gmail.com> for Tyan Computer)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801bx.h"
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+
+	/* Clear system errors */
+	reg16 = pci_read_config16(dev, PCI_STATUS);
+	reg16 |= 0xf900;	/* Clear possible errors */
+	pci_write_config16(dev, PCI_STATUS, reg16);
+
+	reg16 = pci_read_config16(dev, SECSTS);
+	reg16 |= 0xf800;	/* Clear possible errors */
+	pci_write_config16(dev, SECSTS, reg16);
+}
+
+static struct device_operations pci_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801misc_pci __pci_driver = {
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x244e,
+};

Copied: trunk/src/southbridge/intel/i82801bx/reset.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c)
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm at xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
+}

Copied and modified: trunk/src/southbridge/intel/i82801bx/smbus.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801bx/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801bx.h"
-#include "i82801bx_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i82801bx/smbus.h (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h)
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_io_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40),
+	     smbus_io_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i82801bx/usb.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c)
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801bx.h"
+
+static void usb_init(struct device *dev)
+{
+	/* TODO: Any init needed? Some ports have it, others don't. */
+}
+
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801bx_enable,
+};
+
+/* 82801BA/BAM (ICH2/ICH2-M) */
+static const struct pci_driver i82801ba_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB1,
+};
+
+static const struct pci_driver i82801ba_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB2,
+};

Copied: trunk/src/southbridge/intel/i82801bx/watchdog.c (from r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801bx/watchdog.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c)
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 John Dufresne <jon.dufresne at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
+
+void watchdog_off(void)
+{
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH5 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
+}

Modified: trunk/src/southbridge/intel/i82801cx/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801cx/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801cx/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,8 +1,8 @@
 driver-y += i82801cx.c
-driver-y += i82801cx_usb.c
-driver-y += i82801cx_lpc.c
-driver-y += i82801cx_ide.c
-driver-y += i82801cx_ac97.c
-#driver-y += i82801cx_nic.c
-driver-y += i82801cx_pci.c
-ramstage-y += i82801cx_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += ac97.c
+#driver-y += nic.c
+driver-y += pci.c
+ramstage-y += reset.c

Copied: trunk/src/southbridge/intel/i82801cx/ac97.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c)
@@ -0,0 +1,41 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801cx.h"
+
+
+static struct device_operations ac97audio_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = i82801cx_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+};
+
+static const struct pci_driver ac97audio_driver __pci_driver = {
+	.ops    = &ac97audio_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO,
+};
+
+
+static struct device_operations ac97modem_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = i82801cx_enable,
+	.init             = 0,
+	.scan_bus         = 0,
+};
+
+static const struct pci_driver ac97modem_driver __pci_driver = {
+	.ops    = &ac97modem_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM,
+};

Copied: trunk/src/southbridge/intel/i82801cx/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c)
@@ -0,0 +1,134 @@
+#include <device/pci_ids.h>
+#include "i82801cx.h"
+
+static void enable_smbus(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
+	print_debug("SMBus controller enabled\n");
+	/* set smbus iobase */
+	pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+	/* Set smbus enable */
+	pci_write_config8(dev, HOSTC, HST_EN);
+	/* Set smbus iospace enable */
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+	/* Disable interrupt generation */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+}
+
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
+// for a description of this function.
+static int smbus_wait_until_active(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		if ((val & 1)) {
+			break;
+		}
+	} while (--loops);
+	return loops ? 0 : -4;
+}
+
+static int smbus_wait_until_ready(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		// !HOST_BUSY?
+		if ((val & 1) == 0) {
+			break;
+		}
+		if(loops == (SMBUS_TIMEOUT / 2)) {
+			// Clear status flags
+			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+				SMBUS_IO_BASE + SMBHSTSTAT);
+		}
+	} while(--loops);
+	return loops?0:-2;
+}
+
+static int smbus_wait_until_done(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		// !HOST_BUSY?
+		if ( (val & 1) == 0) {
+			break;
+		}
+		// BYTE_DONE or SUCCESS or error?
+		if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
+			break;
+		}
+	} while(--loops);
+	return loops?0:-3;
+}
+
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+	unsigned char global_control_register;
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready() < 0) {
+		return -2;
+	}
+
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
+	/* set to read from the specified device  */
+	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+
+	/* start a byte read, with interrupts disabled */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	/* poll for it to start */
+	if (smbus_wait_until_active() < 0) {
+		return -4;
+	}
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done() < 0) {
+		return -3;
+	}
+
+	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
+
+	/* read results of transaction */
+	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+
+	// SUCCESS?
+	if (global_status_register != 2) {
+		return -1;
+	}
+	return byte;
+}

Copied: trunk/src/southbridge/intel/i82801cx/ide.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c)
@@ -0,0 +1,48 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801cx.h"
+
+
+static void ide_init(struct device *dev)
+{
+	/* Enable ide devices so the linux ide driver will work */
+	uint16_t ideTimingConfig;
+	int enable_primary = 1;
+	int enable_secondary = 1;
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	if (enable_primary) {
+		/* Enable first ide interface */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		printk(BIOS_DEBUG, "IDE0 ");
+	}
+	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
+
+    ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
+    ideTimingConfig &= ~IDE_DECODE_ENABLE;
+    if (enable_secondary) {
+		/* Enable secondary ide interface */
+        ideTimingConfig |= IDE_DECODE_ENABLE;
+        printk(BIOS_DEBUG, "IDE1 ");
+	}
+    pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
+}
+
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.enable           = i82801cx_enable,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_IDE,
+};

Copied: trunk/src/southbridge/intel/i82801cx/lpc.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c)
@@ -0,0 +1,245 @@
+/*
+ * (C) 2003 Linux Networx, SuSE Linux AG
+ * (C) 2004 Tyan Computer
+ * (c) 2005 Digital Design Corporation
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801cx.h"
+
+#define NMI_OFF 0
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+
+static void i82801cx_enable_ioapic( struct device *dev)
+{
+	uint32_t dword;
+    volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
+    volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
+
+    dword = pci_read_config32(dev, GEN_CNTL);
+    dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
+    dword |= (1 <<13); /* coprocessor error enable */
+    dword |= (1 << 1); /* delay transaction enable */
+    dword |= (1 << 2); /* DMA collection buf enable */
+    pci_write_config32(dev, GEN_CNTL, dword);
+    printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
+
+    // Must program the APIC's ID before using it
+
+    *ioapic_index = 0;		// Select APIC ID register
+    *ioapic_data = (2<<24);
+
+    // Hang if the ID didn't take (chip not present?)
+    *ioapic_index = 0;
+    dword = *ioapic_data;
+    printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
+    if(dword != (2<<24))
+		die("");
+
+	*ioapic_index = 3;		// Select Boot Configuration register
+	*ioapic_data = 1;		// Use Processor System Bus to deliver interrupts
+}
+
+// This is how interrupts are received from the Super I/O chip
+static void i82801cx_enable_serial_irqs( struct device *dev)
+{
+	// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
+    pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
+}
+
+/**
+ * Route all DMA channels to either PCI or LPC.
+ *
+ * @param dev TODO
+ * @param mask Identifies whether each channel should be used for PCI DMA
+ *             (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
+ *             Channel 4 is not used (reserved).
+ */
+static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
+{
+    uint16_t dmaConfig;
+    int channelIndex;
+
+    dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
+    dmaConfig &= 0x300;				// Preserve reserved bits
+    for(channelIndex = 0; channelIndex < 8; channelIndex++) {
+    	if (channelIndex == 4)
+        	continue;		// Register doesn't support channel 4
+        dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2);
+    }
+    pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
+}
+
+static void i82801cx_rtc_init(struct device *dev)
+{
+    uint32_t dword;
+    int rtc_failed;
+	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
+
+    rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
+    if (rtc_failed) {
+    	// Clear the RTC_BATTERY_DEAD bit, but preserve
+        // the RTC_POWER_FAILED, G3 state, and reserved bits
+		// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
+        pmcon3 &= ~RTC_POWER_FAILED;
+    }
+
+    get_option(&pwr_on, "power_on_after_fail");
+	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+	if (!pwr_on) {
+		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+	}
+	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+	printk(BIOS_INFO, "set power %s after power fail\n",
+				 pwr_on ? "on" : "off");
+
+    // See if the Safe Mode jumper is set
+    dword = pci_read_config32(dev, GEN_STS);
+    rtc_failed |= dword & (1 << 2);
+
+    rtc_init(rtc_failed);
+}
+
+
+static void i82801cx_1f0_misc(struct device *dev)
+{
+	// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
+    pci_write_config16(dev, PCI_COMMAND, 0x014f);
+
+    // Set ACPI base address to 0x1100 (I/O space)
+    pci_write_config32(dev, PMBASE, 0x00001101);
+
+    // Enable ACPI I/O and power management
+    pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+    // Set GPIO base address to 0x1180 (I/O space)
+    pci_write_config32(dev, GPIO_BASE, 0x00001181);
+
+    // Enable GPIO
+    pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+    // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
+    pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
+
+    // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
+    pci_write_config8(dev, PIRQE_ROUT, 0x07);
+
+    // Enable access to the upper 128 byte bank of CMOS RAM
+    pci_write_config8(dev, RTC_CONF, 0x04);
+
+    // Decode 0x3F8-0x3FF (COM1) for COMA port,
+	//		  0x2F8-0x2FF (COM2) for COMB
+    pci_write_config8(dev, COM_DEC, 0x10);
+
+	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+    // Enable COMA, COMB, LPT, floppy;
+	// disable microcontroller, Super I/O, sound, gameport
+    pci_write_config16(dev, LPC_EN, 0x000F);
+}
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	int pwr_on=-1;
+	int nmi_option;
+
+	/* IO APIC initialization */
+	i82801cx_enable_ioapic(dev);
+
+	i82801cx_enable_serial_irqs(dev);
+
+	/* power after power fail */
+	        /* FIXME this doesn't work! */
+        /* Which state do we want to goto after g3 (power restored)?
+         * 0 == S0 Full On
+         * 1 == S5 Soft Off
+         */
+    byte = pci_read_config8(dev, GEN_PMCON_3);
+    if (pwr_on)
+    	byte &= ~1;		// Return to S0 (boot) after power is re-applied
+    else
+    	byte |= 1;		// Return to S5
+    pci_write_config8(dev, GEN_PMCON_3, byte);
+    printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
+
+    /* Set up NMI on errors */
+    byte = inb(0x61);
+    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+    byte &= ~(1 << 2); /* PCI SERR# Enable */
+    outb(byte, 0x61);
+    byte = inb(0x70);
+    nmi_option = NMI_OFF;
+    get_option(&nmi_option, "nmi");
+    if (nmi_option) {
+        byte &= ~(1 << 7); /* set NMI */
+        outb(byte, 0x70);
+    }
+
+	/* Initialize the real time clock */
+	i82801cx_rtc_init(dev);
+
+	i82801cx_lpc_route_dma(dev, 0xff);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	i82801cx_1f0_misc(dev);
+}
+
+static void i82801cx_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = i82801cx_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = 0,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_LPC,
+};

Copied: trunk/src/southbridge/intel/i82801cx/nic.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c)
@@ -0,0 +1,21 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801cx.h"
+
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+};
+
+static const struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_LAN,
+};

Copied: trunk/src/southbridge/intel/i82801cx/pci.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c)
@@ -0,0 +1,30 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801cx.h"
+
+static void pci_init(struct device *dev)
+{
+	// NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
+	/* Enable pci error detecting */
+	uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
+	dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+	pci_write_config32(dev, PCI_COMMAND, dword);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
+};
+

Copied: trunk/src/southbridge/intel/i82801cx/reset.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c)
@@ -0,0 +1,9 @@
+#include <arch/io.h>
+#include "i82801cx.h"
+
+void i82801cx_hard_reset(void)
+{
+        /* Try rebooting through port 0xcf9 */
+        // Hard reset without power cycle
+        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i82801cx/smbus.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c)
@@ -0,0 +1,83 @@
+#include <smbus.h>
+#include <pci.h>
+#include <arch/io.h>
+#include "i82801cx.h"
+
+#define PM_BUS 0
+#define PM_DEVFN PCI_DEVFN(0x1f,3)
+
+void smbus_enable(void)
+{
+	/* iobase addr */
+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE,
+							   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+	/* smbus enable */
+	pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
+	/* iospace enable */
+	pcibios_write_config_word(PM_BUS, PM_DEVFN, PCI_COMMAND, PCI_COMMAND_IO);
+
+    /* Disable interrupt generation */
+    outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+}
+
+static void smbus_wait_until_ready(void)
+{
+	// Loop while HOST_BUSY
+	while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
+		/* nop */
+	}
+}
+
+static void smbus_wait_until_done(void)
+{
+	unsigned char byte;
+
+	// Loop while HOST_BUSY
+	do {
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	}
+	while((byte &1) == 1);
+
+	// Wait for SUCCESS or error or BYTE_DONE
+	while( (byte & ~1) == 0) {
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	}
+}
+
+int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
+{
+	unsigned char host_status_register;
+	unsigned char byte;
+
+	smbus_wait_until_ready();
+
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
+	/* set to read from the specified device  */
+	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
+	/* set the command/address... */
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	smbus_wait_until_done();
+
+	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* read results of transaction */
+	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+
+	*result = byte;
+	return host_status_register != 0x02;		// return true if !SUCCESS
+}

Copied: trunk/src/southbridge/intel/i82801cx/usb.c (from r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801cx/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c)
@@ -0,0 +1,49 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801cx.h"
+
+static void usb_init(struct device *dev)
+{
+
+#if 0
+	uint32_t cmd;
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+		PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
+
+
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+}
+
+static struct device_operations usb_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = usb_init,
+	.scan_bus         = 0,
+	.enable           = i82801cx_enable,
+};
+
+static const struct pci_driver usb_driver_1 __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801CA_USB1,
+};
+static const struct pci_driver usb_driver_2 __pci_driver = {
+        .ops    = &usb_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_82801CA_USB2,
+};
+static const struct pci_driver usb_driver_3 __pci_driver = {
+        .ops    = &usb_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_82801CA_USB3,
+};
+

Modified: trunk/src/southbridge/intel/i82801dx/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801dx/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801dx/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -20,14 +20,14 @@
 ##
 
 driver-y += i82801dx.c
-driver-y += i82801dx_ac97.c
-driver-y += i82801dx_ide.c
-driver-y += i82801dx_lpc.c
-#driver-y += i82801dx_pci.c
-driver-y += i82801dx_usb.c
-driver-y += i82801dx_usb2.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+#driver-y += pci.c
+driver-y += usb.c
+driver-y += usb2.c
 
-ramstage-y += i82801dx_reset.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.c
+ramstage-y += reset.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

Copied: trunk/src/southbridge/intel/i82801dx/ac97.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c)
@@ -0,0 +1,285 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "i82801dx.h"
+
+#define NAMBAR		0x10
+#define   MASTER_VOL	0x02
+#define   PAGING	0x24
+#define   EXT_AUDIO	0x28
+#define   FUNC_SEL	0x66
+#define   INFO_IO	0x68
+#define   CONNECTOR	0x6a
+#define   VENDOR_ID1	0x7c
+#define   VENDOR_ID2	0x7e
+#define   SEC_VENDOR_ID1 0xfc
+#define   SEC_VENDOR_ID2 0xfe
+
+#define NABMBAR		0x14
+#define   GLOB_CNT	0x2c
+#define   GLOB_STA	0x30
+#define   CAS		0x34
+
+#define MMBAR		0x10
+#define   EXT_MODEM_ID1	0x3c
+#define   EXT_MODEM_ID2	0xbc
+
+#define MBAR		0x14
+#define   SEC_CODEC	0x40
+
+
+/* FIXME. This table is probably mainboard specific */
+static u16 ac97_function[16*2][4] = {
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
+};
+
+static u16 nabmbar;
+static u16 nambar;
+
+static int ac97_semaphore(void)
+{
+	int timeout;
+	u8 reg8;
+
+	timeout = 0xffff;
+	do {
+		reg8 = inb(nabmbar + CAS);
+		timeout--;
+	} while ((reg8 & 1) && timeout);
+	if (! timeout) {
+		printk(BIOS_DEBUG, "Timeout!\n");
+	}
+
+	return (!timeout);
+}
+
+static void init_cnr(void)
+{
+	// TODO
+}
+
+static void program_sigid(struct device *dev, u32 id)
+{
+	pci_write_config32(dev, 0x2c, id);
+}
+
+static void ac97_audio_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+	int i;
+
+	printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
+
+	/* top 16 bits are zero, so don't read them */
+	nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
+	nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
+
+	reg16 = inw(nabmbar + GLOB_CNT);
+	reg16 |= (1 << 1); /* Remove AC_RESET# */
+	outw(reg16, nabmbar + GLOB_CNT);
+
+	/* Wait 600ms. Ouch. */
+	udelay(600 * 1000);
+
+	init_cnr();
+
+	/* Detect Primary AC'97 Codec */
+	reg32 = inl(nabmbar + GLOB_STA);
+	if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
+		/* Primary Codec not found */
+		printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
+		return;
+	}
+
+	ac97_semaphore();
+
+	/* Detect if codec is programmable */
+	outw(0x8000, nambar + MASTER_VOL);
+	ac97_semaphore();
+	if (inw(nambar + MASTER_VOL) != 0x8000) {
+		printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
+		return;
+	}
+
+	/* Program Vendor IDs */
+	reg32 = inw(nambar + VENDOR_ID1);
+	reg32 <<= 16;
+	reg32 |= (u16)inw(nambar + VENDOR_ID2);
+
+	program_sigid(dev, reg32);
+
+	/* Is Codec AC'97 2.3 compliant? */
+	reg16 = inw(nambar + EXT_AUDIO);
+	/* [11:10] = 10b -> AC'97 2.3 */
+	if ((reg16 & 0x0c00) != 0x0800) {
+		/* No 2.3 Codec. We're done */
+		return;
+	}
+
+	/* Select Page 1 */
+	reg16 = inw(nambar + PAGING);
+	reg16 &= 0xfff0;
+	reg16 |= 0x0001;
+	outw(reg16, nambar + PAGING);
+
+	for (i = 0x0a * 2; i > 0; i--) {
+		outw(i, nambar + FUNC_SEL);
+
+		/* Function could not be selected. Next one */
+		if (inw(nambar + FUNC_SEL) != i)
+			continue;
+
+		reg16 = inw(nambar + INFO_IO);
+
+		/* Function Information present? */
+		if (!(reg16 & (1 << 0)))
+			continue;
+
+		/* Function Information valid? */
+		if (!(reg16 & (1 << 4)))
+			continue;
+
+		/* Program Buffer Delay [9:5] */
+		reg16 &= 0x03e0;
+		reg16 |= ac97_function[i][0];
+
+		/* Program Gain [15:11] */
+		reg16 |= ac97_function[i][1];
+
+		/* Program Inversion [10] */
+		reg16 |= ac97_function[i][2];
+
+		outw(reg16, nambar + INFO_IO);
+
+		/* Program Connector / Jack Location */
+		reg16 = inw(nambar + CONNECTOR);
+		reg16 &= 0x1fff;
+		reg16 |= ac97_function[i][3];
+		outw(reg16, nambar + CONNECTOR);
+	}
+}
+
+static void ac97_modem_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+	u16 mmbar, mbar;
+
+	mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
+	mbar = pci_read_config16(dev, MBAR) & 0xfffe;
+
+	reg16 = inw(mmbar + EXT_MODEM_ID1);
+	if ((reg16 & 0xc000) != 0xc000 ) {
+		if (reg16 & (1 << 0)) {
+			reg32 = inw(mmbar + VENDOR_ID2);
+			reg32 <<= 16;
+			reg32 |= (u16)inw(mmbar + VENDOR_ID1);
+			program_sigid(dev, reg32);
+			return;
+		}
+	}
+
+	/* Secondary codec? */
+	reg16 = inw(mbar + SEC_CODEC);
+	if ((reg16 & (1 << 9)) == 0)
+		return;
+
+	reg16 = inw(mmbar + EXT_MODEM_ID2);
+	if ((reg16 & 0xc000) == 0x4000) {
+		if (reg16 & (1 << 0)) {
+			reg32 = inw(mmbar + SEC_VENDOR_ID2);
+			reg32 <<= 16;
+			reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
+			program_sigid(dev, reg32);
+			return;
+		}
+	}
+}
+
+static struct device_operations ac97_audio_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = i82801dx_enable,
+	.init             = ac97_audio_init,
+	.scan_bus         = 0,
+};
+
+static struct device_operations ac97_modem_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.enable           = i82801dx_enable,
+	.init             = ac97_modem_init,
+	.scan_bus         = 0,
+};
+
+/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
+static const struct pci_driver i82801db_ac97_audio __pci_driver = {
+	.ops	= &ac97_audio_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
+};
+
+static const struct pci_driver i82801db_ac97_modem __pci_driver = {
+	.ops	= &ac97_modem_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
+};
+
+

Copied: trunk/src/southbridge/intel/i82801dx/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c)
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "i82801dx.h"
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+//#define SMBUS_TIMEOUT (100*1000*10)
+
+static void enable_smbus(void)
+{
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+
+	printk(BIOS_DEBUG, "SMBus controller enabled\n");
+	/* set smbus iobase */
+	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
+	/* Set smbus enable */
+	pci_write_config8(dev, 0x40, 0x01);
+	/* Set smbus iospace enable */
+	pci_write_config16(dev, 0x4, 0x01);
+	/* Disable interrupt generation */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+}
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_active(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		if ((val & 1)) {
+			break;
+		}
+	} while (--loops);
+	return loops ? 0 : -4;
+}
+
+static int smbus_wait_until_ready(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		if ((val & 1) == 0) {
+			break;
+		}
+		if (loops == (SMBUS_TIMEOUT / 2)) {
+			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+			     SMBUS_IO_BASE + SMBHSTSTAT);
+		}
+	} while (--loops);
+	return loops ? 0 : -2;
+}
+
+static int smbus_wait_until_done(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned char val;
+		smbus_delay();
+
+		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		if ((val & 1) == 0) {
+			break;
+		}
+		if ((val & ~((1 << 6) | (1 << 0))) != 0) {
+			break;
+		}
+	} while (--loops);
+	return loops ? 0 : -3;
+}
+
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	/* printk(BIOS_ERR, "smbus_read_byte\n"); */
+	if (smbus_wait_until_ready() < 0) {
+		printk(BIOS_ERR, "SMBUS not ready (%02x)\n", -2);
+		return -2;
+	}
+
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* clear the data byte... */
+	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+
+	/* start a byte read, with interrupts disabled */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
+	/* poll for it to start */
+	if (smbus_wait_until_active() < 0) {
+		printk(BIOS_ERR, "SMBUS not active (%02x)\n", -4);
+		return -4;
+	}
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done() < 0) {
+		printk(BIOS_ERR, "SMBUS not completed (%02x)\n", -3);
+		return -3;
+	}
+
+	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);	/* Ignore the In Use Status... */
+
+	/* read results of transaction */
+	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+
+	if (global_status_register != 2) {
+		//printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address);
+		return -1;
+	}
+	//printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte);
+	return byte;
+}
+
+#if 0
+static void smbus_write_byte(unsigned device, unsigned address,
+			     unsigned char val)
+{
+	if (smbus_wait_until_ready() < 0) {
+		return;
+	}
+
+	/* by LYH */
+	outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
+	/* set the device I'm talking too */
+	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
+
+	/* data to send */
+	outb(val, SMBUS_IO_BASE + SMBHSTDAT);
+
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+
+	/* start the command */
+	outb(0xa, SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	smbus_wait_until_done();
+	return;
+}
+#endif

Copied: trunk/src/southbridge/intel/i82801dx/ide.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c)
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801dx.h"
+
+typedef struct southbridge_intel_i82801dx_config config_t;
+
+static void ide_init(struct device *dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	/* Enable IDE devices so the Linux IDE driver will work. */
+	uint16_t ideTimingConfig;
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	if (!config || config->ide0_enable) {
+		/* Enable primary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
+	} else {
+		printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
+	}
+	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	if (!config || config->ide1_enable) {
+		/* Enable secondary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
+	} else {
+		printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
+	}
+	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ide_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
+};
+
+/* 82801DB */
+static const struct pci_driver i82801db_ide __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x24cb,
+};
+
+/* 82801DBM */
+static const struct pci_driver i82801dbm_ide __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x24ca,
+};

Copied: trunk/src/southbridge/intel/i82801dx/lpc.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c)
@@ -0,0 +1,347 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2004 SuSE Linux AG
+ * Copyright (C) 2004 Tyan Computer
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801dx.h"
+
+#define NMI_OFF 0
+
+typedef struct southbridge_intel_i82801dx_config config_t;
+
+static void i82801dx_enable_ioapic(struct device *dev)
+{
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Enable ACPI I/O and power management. */
+	pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	reg32 |= (3 << 7);	/* Enable IOAPIC */
+	reg32 |= (1 << 13);	/* Coprocessor error enable */
+	reg32 |= (1 << 1);	/* Delayed transaction enable */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void i82801dx_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+}
+
+static void i82801dx_pirq_init(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+	pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+	pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+	pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+	pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+	pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+}
+
+static void i82801dx_power_options(device_t dev)
+{
+	u8 reg8;
+	u16 reg16, pmbase;
+	u32 reg32;
+	const char *state;
+
+	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int nmi_option;
+
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 *
+	 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
+	 */
+	if (get_option(&pwr_on, "power_on_after_fail") < 0)
+		pwr_on = MAINBOARD_POWER_ON;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	reg8 &= 0xfe;
+	switch (pwr_on) {
+		case MAINBOARD_POWER_OFF:
+			reg8 |= 1;
+			state = "off";
+			break;
+		case MAINBOARD_POWER_ON:
+			reg8 &= ~1;
+			state = "on";
+			break;
+		case MAINBOARD_POWER_KEEP:
+			reg8 &= ~1;
+			state = "state keep";
+			break;
+		default:
+			state = "undefined";
+	}
+
+	reg8 &= ~(1 << 3);	/* minimum asssertion is 1 to 2 RTCCLK */
+
+	pci_write_config8(dev, GEN_PMCON_3, reg8);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+	/* Set up NMI on errors. */
+	reg8 = inb(0x61);
+	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
+	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
+	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+	outb(reg8, 0x61);
+
+	reg8 = inb(0x70);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		printk(BIOS_INFO, "NMI sources enabled.\n");
+		reg8 &= ~(1 << 7);	/* Set NMI. */
+	} else {
+		printk(BIOS_INFO, "NMI sources disabled.\n");
+		reg8 |= ( 1 << 7);	/* Disable NMI. */
+	}
+	outb(reg8, 0x70);
+
+	/* Set SMI# rate down and enable CPU_SLP# */
+	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 &= ~(3 << 0);	// SMI# rate 1 minute
+	reg16 |= (1 << 5);	// CPUSLP_EN Desktop only
+	pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+	/* Set up power management block and determine sleep mode */
+	reg32 = inl(pmbase + 0x04); // PM1_CNT
+
+	reg32 &= ~(7 << 10);	// SLP_TYP
+	reg32 |= (1 << 0);	// SCI_EN
+	outl(reg32, pmbase + 0x04);
+}
+
+static void gpio_init(device_t dev)
+{
+	/* This should be done in romstage.c already */
+	pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
+	pci_write_config8(dev, GPIO_CNTL, 0x10);
+}
+
+static void i82801dx_rtc_init(struct device *dev)
+{
+	u8 reg8;
+	u32 reg32;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~(1 << 1);	/* Preserve the power fail state. */
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	reg32 = pci_read_config32(dev, GEN_STS);
+	rtc_failed |= reg32 & (1 << 2);
+	rtc_init(rtc_failed);
+
+	/* Enable access to the upper 128 byte bank of CMOS RAM. */
+	pci_write_config8(dev, RTC_CONF, 0x04);
+}
+
+static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
+{
+	u16 reg16;
+	int i;
+
+	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+	reg16 &= 0x300;
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, reg16);
+}
+
+static void i82801dx_lpc_decode_en(device_t dev)
+{
+	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+	 * We also need to set the value for LPC I/F Enables Register.
+	 */
+	pci_write_config8(dev, COM_DEC, 0x10);
+	pci_write_config16(dev, LPC_EN, 0x300F);
+}
+
+/* ICH4 does not mention HPET in the docs, but
+ * all ICH3 and ICH4 do have HPETs built in.
+ */
+static void enable_hpet(struct device *dev)
+{
+	u32 reg32, hpet, val;
+
+	/* Set HPET base address and enable it */
+	printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR);
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	/*
+	 * Bit 17 is HPET enable bit.
+	 * Bit 16:15 control the HPET base address.
+	 */
+	reg32 &= ~(3 << 15);	/* Clear it */
+
+	hpet = HPET_ADDR >> 12;
+	hpet &= 0x3;
+
+	reg32 |= (hpet << 15);
+	reg32 |= (1 << 17);	/* Enable HPET. */
+	pci_write_config32(dev, GEN_CNTL, reg32);
+
+	/* Check to see whether it took */
+	reg32 = pci_read_config32(dev, GEN_CNTL);
+	val = reg32 >> 15;
+	val &= 0x7;
+
+	if ((val & 0x4) && (hpet == (val & 0x3))) {
+		printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR);
+	} else {
+		printk(BIOS_WARNING, "HPET was not enabled correctly\n");
+		reg32 &= ~(1 << 17);	/* Clear Enable */
+		pci_write_config32(dev, GEN_CNTL, reg32);
+	}
+}
+
+static void lpc_init(struct device *dev)
+{
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	i82801dx_enable_ioapic(dev);
+
+	i82801dx_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	i82801dx_pirq_init(dev);
+
+	/* Setup power options. */
+	i82801dx_power_options(dev);
+
+	/* Set the state of the GPIO lines. */
+	gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	i82801dx_rtc_init(dev);
+
+	/* Route DMA. */
+	i82801dx_lpc_route_dma(dev, 0xff);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Setup decode ports and LPC I/F enables. */
+	i82801dx_lpc_decode_en(dev);
+
+	/* Initialize the High Precision Event Timers */
+	enable_hpet(dev);
+}
+
+static void i82801dx_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources		= i82801dx_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801dx_enable,
+};
+
+/* 82801DB/DBL */
+static const struct pci_driver lpc_driver_db __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
+};
+
+/* 82801DBM */
+static const struct pci_driver lpc_driver_dbm __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
+};

Copied: trunk/src/southbridge/intel/i82801dx/nvs.h (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/nvs.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_nvs.h)
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+typedef struct {
+	/* Miscellaneous */
+	u16	osys; /* 0x00 - Operating System */
+	u8	smif; /* 0x02 - SMI function call ("TRAP") */
+	u8	prm0; /* 0x03 - SMI function call parameter */
+	u8	prm1; /* 0x04 - SMI function call parameter */
+	u8	scif; /* 0x05 - SCI function call (via _L00) */
+	u8	prm2; /* 0x06 - SCI function call parameter */
+	u8	prm3; /* 0x07 - SCI function call parameter */
+	u8	lckf; /* 0x08 - Global Lock function for EC */
+	u8	prm4; /* 0x09 - Lock function parameter */
+	u8	prm5; /* 0x0a - Lock function parameter */
+	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
+	u8	lids; /* 0x0f - LID state (open = 1) */
+	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	u8	dbgs; /* 0x11 - Debug state */
+	u8	linx; /* 0x12 - Linux OS */
+	u8	dckn; /* 0x13 - PCIe docking state */
+	/* Thermal policy */
+	u8	actt; /* 0x14 - active trip point */
+	u8	psvt; /* 0x15 - passive trip point */
+	u8	tc1v; /* 0x16 - passive trip point TC1 */
+	u8	tc2v; /* 0x17 - passive trip point TC2 */
+	u8	tspv; /* 0x18 - passive trip point TSP */
+	u8	crtt; /* 0x19 - critical trip point */
+	u8	dtse; /* 0x1a - Digital Thermal Sensor enable */
+	u8	dts1; /* 0x1b - DT sensor 1 */
+	u8	dts2; /* 0x1c - DT sensor 2 */
+	u8	rsvd2;
+	/* Battery Support */
+	u8	bnum; /* 0x1e - number of batteries */
+	u8	b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
+	u8	b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
+	u8	rsvd3[3];
+	/* Processor Identification */
+	u8	apic; /* 0x28 - APIC enabled */
+	u8	mpen; /* 0x29 - MP capable/enabled */
+	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
+	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
+	u8	ppcm; /* 0x2c - Max. PPC state */
+	u8	rsvd4[5];
+	/* Super I/O & CMOS config */
+	u8	natp; /* 0x32 - SIO type */
+	u8	cmap; /* 0x33 - */
+	u8	cmbp; /* 0x34 - */
+	u8	lptp; /* 0x35 - LPT port */
+	u8	fdcp; /* 0x36 - Floppy Disk Controller */
+	u8	rfdv; /* 0x37 - */
+	u8	hotk; /* 0x38 - Hot Key */
+	u8	rtcf;
+	u8	util;
+	u8	acin;
+	/* Integrated Graphics Device */
+	u8	igds; /* 0x3c - IGD state */
+	u8	tlst; /* 0x3d - Display Toggle List Pointer */
+	u8	cadl; /* 0x3e - currently attached devices */
+	u8	padl; /* 0x3f - previously attached devices */
+	u16	cste; /* 0x40 - current display state */
+	u16	nste; /* 0x42 - next display state */
+	u16	sste; /* 0x44 - set display state */
+	u8	ndid; /* 0x46 - number of device ids */
+	u32	did[5]; /* 0x47 - 5b device id 1..5 */
+	u8	rsvd5[0x9];
+	/* Backlight Control */
+	u8	blcs; /* 0x64 - Backlight Control possible */
+	u8	brtl;
+	u8	odds;
+	u8	rsvd6[0x7];
+	/* Ambient Light Sensors*/
+	u8	alse; /* 0x6e - ALS enable */
+	u8	alaf;
+	u8	llow;
+	u8	lhih;
+	u8	rsvd7[0x6];
+	/* EMA */
+	u8	emae; /* 0x78 - EMA enable */
+	u16	emap;
+	u16	emal;
+	u8	rsvd8[0x5];
+	/* MEF */
+	u8	mefe; /* 0x82 - MEF enable */
+	u8	rsvd9[0x9];
+	/* TPM support */
+	u8	tpmp; /* 0x8c - TPM */
+	u8	tpme;
+	u8	rsvd10[8];
+	/* SATA */
+	u8	gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
+	u8	gtf1[7];
+	u8	gtf2[7];
+	u8	idem;
+	u8	idet;
+	u8	rsvd11[7];
+	/* IGD OpRegion (not implemented yet) */
+	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
+	u8	ibtt;
+	u8	ipat;
+	u8	itvf;
+	u8	itvm;
+	u8	ipsc;
+	u8	iblc;
+	u8	ibia;
+	u8	issc;
+	u8	i409;
+	u8	i509;
+	u8	i609;
+	u8	i709;
+	u8	idmm;
+	u8	idms;
+	u8	if1e;
+	u8	hvco;
+	u32	nxd[8];
+	u8	rsvd12[8];
+	/* Mainboard specific */
+	u8	dock; /* 0xf0 - Docking Status */
+	u8	bten;
+	u8	rsvd13[14];
+} __attribute__((packed)) global_nvs_t;
+

Copied: trunk/src/southbridge/intel/i82801dx/pci.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c)
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801dx.h"
+
+static void pci_init(struct device *dev)
+{
+	/* Enable pci error detecting */
+	uint32_t dword;
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1 << 8);	/* SERR# Enable */
+	dword |= (1 << 6);	/* Parity Error Response */
+	pci_write_config32(dev, 0x04, dword);
+}
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
+};
+
+/* 82801DB */
+static const struct pci_driver pci_driver_db __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_PCI,
+};
+
+/* 82801DBM/DBL */
+static const struct pci_driver pci_driver_dbm __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
+};

Copied: trunk/src/southbridge/intel/i82801dx/reset.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9 */
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i82801dx/smbus.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/smbus.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c)
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "i82801dx.h"
+#include <smbus.h>
+#include <pci.h>
+#include <arch/io.h>
+
+#define PM_BUS 0
+#define PM_DEVFN PCI_DEVFN(0x1f,3)
+
+void smbus_enable(void)
+{
+	unsigned char byte;
+	/* iobase addr */
+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
+	/* smbus enable */
+	pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
+	/* iospace enable */
+	pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
+
+	/* Disable interrupt generation */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+}
+
+void smbus_setup(void)
+{
+	outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
+}
+
+static void smbus_wait_until_ready(void)
+{
+	while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
+		/* nop */
+	}
+}
+
+static void smbus_wait_until_done(void)
+{
+	unsigned char byte;
+	do {
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	}
+	while ((byte & 1) == 1);
+	while ((byte & ~1) == 0) {
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	}
+}
+
+int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
+{
+	unsigned char host_status_register;
+	unsigned char byte;
+
+	smbus_wait_until_ready();
+
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
+	/* set the command/address... */
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* clear the data byte... */
+	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	smbus_wait_until_done();
+
+	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+
+	/* read results of transaction */
+	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+
+	*result = byte;
+	return host_status_register != 0x02;
+}

Copied: trunk/src/southbridge/intel/i82801dx/smi.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/smi.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c)
@@ -0,0 +1,368 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+#include "i82801dx.h"
+
+extern unsigned char _binary_smm_start;
+extern unsigned char _binary_smm_size;
+
+/* I945 */
+#define SMRAM		0x90
+#define   D_OPEN	(1 << 6)
+#define   D_CLS		(1 << 5)
+#define   D_LCK		(1 << 4)
+#define   G_SMRAME	(1 << 3)
+#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = PMBASE_ADDR;
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+	u16 reg16;
+
+	reg16 = inw(pmbase + PM1_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outw(reg16, pmbase + PM1_STS);
+
+	return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + SMI_STS);
+
+	return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + GPE0_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + GPE0_STS);
+
+	return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "GPE0_STS: ");
+	for (i=31; i<= 16; i--) {
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+	}
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear ALT_GP_SMI_STS
+ * @return ALT_GP_SMI_STS register
+ */
+static u16 reset_alt_gp_smi_status(void)
+{
+	u16 reg16;
+
+	reg16 = inl(pmbase + ALT_GP_SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+	return reg16;
+}
+
+static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
+	for (i=15; i<= 0; i--) {
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+	u32 tcobase = pmbase + 0x60;
+	u32 reg32;
+
+	reg32 = inl(tcobase + 0x04);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
+	if (reg32 & (1 << 18))
+		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+	return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief Set the EOS bit
+ */
+static void smi_set_eos(void)
+{
+	u8 reg8;
+
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 |= EOS;
+	outb(reg8, pmbase + SMI_EN);
+}
+
+extern uint8_t smm_relocation_start, smm_relocation_end;
+
+static void smm_relocate(void)
+{
+	u32 smi_en;
+	u16 pm1_en;
+
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
+
+	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+	smi_en = inl(pmbase + SMI_EN);
+	if (smi_en & APMC_EN) {
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
+		return;
+	}
+
+	/* copy the SMM relocation code */
+	memcpy((void *)0x38000, &smm_relocation_start,
+			&smm_relocation_end - &smm_relocation_start);
+
+	printk(BIOS_DEBUG, "\n");
+	dump_smi_status(reset_smi_status());
+	dump_pm1_status(reset_pm1_status());
+	dump_gpe0_status(reset_gpe0_status());
+	dump_alt_gp_smi_status(reset_alt_gp_smi_status());
+	dump_tco_status(reset_tco_status());
+
+	/* Enable SMI generation:
+	 *  - on TCO events
+	 *  - on APMC writes (io 0xb2)
+	 *  - on writes to SLP_EN (sleep states)
+	 *  - on writes to GBL_RLS (bios commands)
+	 * No SMIs:
+	 *  - on microcontroller writes (io 0x62/0x66)
+	 */
+
+	smi_en = 0; /* reset SMI enables */
+
+#if 0
+	smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
+#endif
+	smi_en |= TCO_EN;
+	smi_en |= APMC_EN;
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+	 * periodic SMIs.
+	 */
+	smi_en |= PERIODIC_EN;
+#endif
+	smi_en |= SLP_SMI_EN;
+	smi_en |= BIOS_EN;
+
+	/* The following need to be on for SMIs to happen */
+	smi_en |= EOS | GBL_SMI_EN;
+
+	outl(smi_en, pmbase + SMI_EN);
+
+	pm1_en = 0;
+	pm1_en |= PWRBTN_EN;
+	pm1_en |= GBL_EN;
+	outw(pm1_en, pmbase + PM1_EN);
+
+	/**
+	 * There are several methods of raising a controlled SMI# via
+	 * software, among them:
+	 *  - Writes to io 0xb2 (APMC)
+	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
+	 *
+	 * Using the local apic is a bit more tricky. According to
+	 * AMD Family 11 Processor BKDG no destination shorthand must be
+	 * used.
+	 * The whole SMM initialization is quite a bit hardware specific, so
+	 * I'm not too worried about the better of the methods at the moment
+	 */
+
+	/* raise an SMI interrupt */
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
+	outb(0x00, 0xb2);
+}
+
+static void smm_install(void)
+{
+	/* enable the SMM memory window */
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+				D_OPEN | G_SMRAME | C_BASE_SEG);
+
+	/* copy the real SMM handler */
+	memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size);
+	wbinvd();
+
+	/* close the SMM memory window and enable normal SMM */
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+			G_SMRAME | C_BASE_SEG);
+}
+
+void smm_init(void)
+{
+	/* Put SMM code to 0xa0000 */
+	smm_install();
+
+	/* Put relocation code to 0x38000 and relocate SMBASE */
+	smm_relocate();
+
+	/* We're done. Make sure SMIs can happen! */
+	smi_set_eos();
+}
+
+void smm_lock(void)
+{
+	/* LOCK the SMM memory window and enable normal SMM.
+	 * After running this function, only a full reset can
+	 * make the SMM registers writable again.
+	 */
+	printk(BIOS_DEBUG, "Locking SMM.\n");
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+			D_LCK | G_SMRAME | C_BASE_SEG);
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+	/* The GDT or coreboot table is going to live here. But a long time
+	 * after we relocated the GNVS, so this is not troublesome.
+	 */
+	*(u32 *)0x500 = (u32)gnvs;
+	*(u32 *)0x504 = (u32)tcg;
+	*(u32 *)0x508 = (u32)smi1;
+	outb(0xea, 0xb2);
+}

Copied and modified: trunk/src/southbridge/intel/i82801dx/smihandler.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801dx/smihandler.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -47,7 +47,7 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "i82801dx_nvs.h"
+#include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value

Copied: trunk/src/southbridge/intel/i82801dx/tco_timer.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/tco_timer.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+static void i82801dx_halt_tco_timer(void)
+{
+	/* Set the LPC device statically. */
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Temporarily set ACPI base address (I/O space). */
+	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+	/* Enable ACPI I/O. */
+	pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+	/* Halt the TCO timer, preventing SMI and automatic reboot */
+	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
+	     PMBASE_ADDR + TCOBASE + TCO1_CNT);
+}

Copied: trunk/src/southbridge/intel/i82801dx/usb.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c)
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801dx.h"
+
+static void usb_init(struct device *dev)
+{
+	u32 cmd;
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
+};
+
+/* 82801DB/DBL/DBM USB1 */
+static const struct pci_driver usb_driver_1 __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
+};
+
+/* 82801DB/DBL/DBM USB2 */
+static const struct pci_driver usb_driver_2 __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
+};
+
+/* 82801DB/DBL/DBM USB3 */
+static const struct pci_driver usb_driver_3 __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
+};

Copied: trunk/src/southbridge/intel/i82801dx/usb2.c (from r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801dx/usb2.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c)
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Tyan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801dx.h"
+
+static void usb2_init(struct device *dev)
+{
+	u32 cmd;
+	printk(BIOS_DEBUG, "USB: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static struct device_operations usb2_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = usb2_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
+};
+
+/* 82801DB/DBM USB 2.0 */
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops = &usb2_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,
+};

Modified: trunk/src/southbridge/intel/i82801ex/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801ex/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801ex/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,11 +1,11 @@
 driver-y += i82801ex.c
-driver-y += i82801ex_uhci.c
-driver-y += i82801ex_lpc.c
-driver-y += i82801ex_ide.c
-driver-y += i82801ex_sata.c
-driver-y += i82801ex_ehci.c
-driver-y += i82801ex_smbus.c
-driver-y += i82801ex_pci.c
-driver-y += i82801ex_ac97.c
-ramstage-y += i82801ex_watchdog.c
-ramstage-y += i82801ex_reset.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+driver-y += ac97.c
+ramstage-y += watchdog.c
+ramstage-y += reset.c

Copied: trunk/src/southbridge/intel/i82801ex/ac97.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c)
@@ -0,0 +1,37 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = ac97_set_subsystem,
+};
+static struct device_operations ac97_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = i82801ex_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ac97_audio_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO,
+};
+static const struct pci_driver ac97_modem_driver __pci_driver = {
+	.ops    = &ac97_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM,
+};

Copied and modified: trunk/src/southbridge/intel/i82801ex/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ex/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,4 +1,4 @@
-#include "i82801ex_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 

Copied: trunk/src/southbridge/intel/i82801ex/ehci.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c)
@@ -0,0 +1,50 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void ehci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	uint8_t access_cntl;
+	access_cntl = pci_read_config8(dev, 0x80);
+	/* Enable writes to protected registers */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+	/* Write the subsystem vendor and device id */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+	/* Restore protection */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = &ehci_set_subsystem,
+};
+static struct device_operations ehci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ehci_init,
+	.scan_bus         = 0,
+	.enable           = i82801ex_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ehci_driver __pci_driver = {
+	.ops    = &ehci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_EHCI,
+};

Copied: trunk/src/southbridge/intel/i82801ex/ide.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c)
@@ -0,0 +1,43 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void ide_init(struct device *dev)
+{
+	/* Enable IDE devices and timmings */
+	pci_write_config16(dev, 0x40, 0x0a307); // IDE0
+	pci_write_config16(dev, 0x42, 0x0a307); // IDE1
+	pci_write_config8(dev, 0x48, 0x05);
+	pci_write_config16(dev, 0x4a, 0x0101);
+	pci_write_config16(dev, 0x54, 0x5055);
+	printk(BIOS_DEBUG, "IDE Enabled\n");
+}
+
+static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* This value is also visible in uchi[0-2] and smbus functions */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = i82801ex_ide_set_subsystem,
+};
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ide_init,
+	.scan_bus         = 0,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_IDE,
+};
+

Copied: trunk/src/southbridge/intel/i82801ex/lpc.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c)
@@ -0,0 +1,358 @@
+/*
+ * (C) 2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801ex.h"
+
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x58
+
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define SERIRQ_CNTL 0x64
+static void i82801ex_enable_serial_irqs(device_t dev)
+{
+	/* set packet length and toggle silent mode bit */
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+}
+
+#define PCI_DMA_CFG 0x90
+static void i82801ex_pci_dma_cfg(device_t dev)
+{
+	/* Set PCI DMA CFG to lpc I/F DMA */
+	pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
+}
+
+#define LPC_EN 0xe6
+static void i82801ex_enable_lpc(device_t dev)
+{
+        /* lpc i/f enable */
+        pci_write_config8(dev, LPC_EN, 0x0d);
+}
+
+typedef struct southbridge_intel_i82801ex_config config_t;
+
+static void set_i82801ex_gpio_use_sel(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_use_sel, gpio_use_sel2;
+	int i;
+
+	gpio_use_sel  = 0x1A003180;
+	gpio_use_sel2 = 0x00000007;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
+		case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
+		case ICH5R_GPIO_USE_AS_GPIO:   val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_use_sel  &= ~( 1 << i);
+			gpio_use_sel  |= (val << i);
+		} else {
+			gpio_use_sel2 &= ~( 1 << (i - 32));
+			gpio_use_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_use_sel,  res->base + 0x00);
+	outl(gpio_use_sel2, res->base + 0x30);
+}
+
+static void set_i82801ex_gpio_direction(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_io_sel, gpio_io_sel2;
+	int i;
+
+	gpio_io_sel  = 0x0000ffff;
+	gpio_io_sel2 = 0x00000300;
+	for(i = 0; i < 64; i++) {
+		int val;
+		switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
+		case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
+		case ICH5R_GPIO_SEL_INPUT:  val = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_io_sel  &= ~( 1 << i);
+			gpio_io_sel  |= (val << i);
+		} else {
+			gpio_io_sel2 &= ~( 1 << (i - 32));
+			gpio_io_sel2 |= (val << (i - 32));
+		}
+	}
+	outl(gpio_io_sel,  res->base + 0x04);
+	outl(gpio_io_sel2, res->base + 0x34);
+}
+
+static void set_i82801ex_gpio_level(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_lvl, gpio_lvl2;
+	uint32_t gpio_blink;
+	int i;
+
+	gpio_lvl   = 0x1b3f0000;
+	gpio_blink = 0x00040000;
+	gpio_lvl2  = 0x00030207;
+	for(i = 0; i < 64; i++) {
+		int val, blink;
+		switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
+		case ICH5R_GPIO_LVL_LOW:   val = 0; blink = 0; break;
+		case ICH5R_GPIO_LVL_HIGH:  val = 1; blink = 0; break;
+		case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break;
+		default:
+			continue;
+		}
+		/* The caller is responsible for not playing with unimplemented bits */
+		if (i < 32) {
+			gpio_lvl   &= ~(   1 << i);
+			gpio_blink &= ~(   1 << i);
+			gpio_lvl   |= (  val << i);
+			gpio_blink |= (blink << i);
+		} else {
+			gpio_lvl2  &= ~( 1 << (i - 32));
+			gpio_lvl2  |= (val << (i - 32));
+		}
+	}
+	outl(gpio_lvl,   res->base + 0x0c);
+	outl(gpio_blink, res->base + 0x18);
+	outl(gpio_lvl2,  res->base + 0x38);
+}
+
+static void set_i82801ex_gpio_inv(
+	device_t dev, struct resource *res, config_t *config)
+{
+	uint32_t gpio_inv;
+	int i;
+
+	gpio_inv   = 0x00000000;
+	for(i = 0; i < 32; i++) {
+		int val;
+		switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
+		case ICH5R_GPIO_INV_OFF: val = 0; break;
+		case ICH5R_GPIO_INV_ON:  val = 1; break;
+		default:
+			continue;
+		}
+		gpio_inv &= ~( 1 << i);
+		gpio_inv |= (val << i);
+	}
+	outl(gpio_inv,   res->base + 0x2c);
+}
+
+static void i82801ex_pirq_init(device_t dev)
+{
+	config_t *config;
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+
+	if(config->pirq_a_d) {
+		pci_write_config32(dev, 0x60, config->pirq_a_d);
+	}
+	if(config->pirq_e_h) {
+		pci_write_config32(dev, 0x68, config->pirq_e_h);
+	}
+}
+
+
+static void i82801ex_gpio_init(device_t dev)
+{
+	struct resource *res;
+	config_t *config;
+
+	/* Skip if I don't have any configuration */
+	if (!dev->chip_info) {
+		return;
+	}
+	/* The programmer is responsible for ensuring
+	 * a valid gpio configuration.
+	 */
+
+	/* Get the chip configuration */
+	config = dev->chip_info;
+	/* Find the GPIO bar */
+	res = find_resource(dev, GPIO_BAR);
+	if (!res) {
+		return;
+	}
+
+	/* Set the use selects */
+	set_i82801ex_gpio_use_sel(dev, res, config);
+
+	/* Set the IO direction */
+	set_i82801ex_gpio_direction(dev, res, config);
+
+	/* Setup the input inverters */
+	set_i82801ex_gpio_inv(dev, res, config);
+
+	/* Set the value on the GPIO output pins */
+	set_i82801ex_gpio_level(dev, res, config);
+
+}
+
+static void enable_hpet(struct device *dev)
+{
+	const unsigned long hpet_address = 0xfed00000;
+
+	uint32_t dword;
+	uint32_t code = (0 & 0x3);
+
+	dword = pci_read_config32(dev, GEN_CNTL);
+	dword |= (1 << 17); /* enable hpet */
+
+	/* Bits [16:15]  Memory Address Range
+	 *	    00   FED0_0000h - FED0_03FFh
+	 *	    01   FED0_1000h - FED0_13FFh
+	 *	    10   FED0_2000h - FED0_23FFh
+	 *	    11   FED0_3000h - FED0_33FFh
+	 */
+
+	dword &= ~(3 << 15); /* clear it */
+	dword |= (code<<15);
+	pci_write_config32(dev, GEN_CNTL, dword);
+
+	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
+}
+
+static void lpc_init(struct device *dev)
+{
+	uint8_t byte;
+	uint32_t value;
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+	/* IO APIC initialization */
+	value = pci_read_config32(dev, 0xd0);
+	value |= (1 << 8)|(1<<7)|(1<<1);
+	pci_write_config32(dev, 0xd0, value);
+	value = pci_read_config32(dev, 0xd4);
+	value |= (1<<1);
+	pci_write_config32(dev, 0xd4, value);
+	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
+
+	i82801ex_enable_serial_irqs(dev);
+
+	i82801ex_pci_dma_cfg(dev);
+
+	i82801ex_enable_lpc(dev);
+
+	/* Clear SATA to non raid */
+	pci_write_config8(dev, 0xae, 0x00);
+
+        get_option(&pwr_on, "power_on_after_fail");
+	byte = pci_read_config8(dev, 0xa4);
+	byte &= 0xfe;
+	if (!pwr_on) {
+		byte |= 1;
+	}
+	pci_write_config8(dev, 0xa4, byte);
+	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
+
+	/* Set up the PIRQ */
+	i82801ex_pirq_init(dev);
+
+	/* Set the state of the gpio lines */
+	i82801ex_gpio_init(dev);
+
+	/* Initialize the real time clock */
+	rtc_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	/* Disable IDE (needed when sata is enabled) */
+	pci_write_config8(dev, 0xf2, 0x60);
+
+	enable_hpet(dev);
+}
+
+static void i82801ex_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add the ACPI BAR */
+	res = pci_get_resource(dev, ACPI_BAR);
+
+	/* Add the GPIO BAR */
+	res = pci_get_resource(dev, GPIO_BAR);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void i82801ex_lpc_enable_resources(device_t dev)
+{
+	uint8_t acpi_cntl, gpio_cntl;
+
+	/* Enable the normal pci resources */
+	pci_dev_enable_resources(dev);
+
+	/* Enable the ACPI bar */
+	acpi_cntl = pci_read_config8(dev, 0x44);
+	acpi_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x44, acpi_cntl);
+
+	/* Enable the GPIO bar */
+	gpio_cntl = pci_read_config8(dev, 0x5c);
+	gpio_cntl |= (1 << 4);
+	pci_write_config8(dev, 0x5c, gpio_cntl);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations lpc_ops  = {
+	.read_resources   = i82801ex_lpc_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = i82801ex_lpc_enable_resources,
+	.init             = lpc_init,
+	.scan_bus         = scan_static_bus,
+	.enable           = i82801ex_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_LPC,
+};

Copied: trunk/src/southbridge/intel/i82801ex/pci.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c)
@@ -0,0 +1,45 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void pci_init(struct device *dev)
+{
+	uint16_t word;
+
+	/* Clear system errors */
+	word = pci_read_config16(dev, 0x06);
+	word |= 0xf900; /* Clear possible errors */
+	pci_write_config16(dev, 0x06, word);
+
+#if 0
+	/* System error enable */
+	uint32_t dword;
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* SERR# Enable */
+	dword |= (1<<6); /* Parity Error Response */
+	pci_write_config32(dev, 0x04, dword);
+#endif
+
+	word = pci_read_config16(dev, 0x1e);
+	word |= 0xf800; /* Clear possible errors */
+	pci_write_config16(dev, 0x1e, word);
+}
+
+static struct device_operations pci_ops  = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = pci_init,
+	.scan_bus         = pci_scan_bridge,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops    = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_PCI,
+};
+

Copied: trunk/src/southbridge/intel/i82801ex/reset.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c)
@@ -0,0 +1,8 @@
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+        /* Try rebooting through port 0xcf9 */
+        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i82801ex/sata.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c)
@@ -0,0 +1,60 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void sata_init(struct device *dev)
+{
+  	printk(BIOS_DEBUG, "SATA init\n");
+	/* SATA configuration */
+	pci_write_config8(dev, 0x04, 0x07);
+	pci_write_config8(dev, 0x09, 0x8f);
+
+	/* Set timmings */
+	pci_write_config16(dev, 0x40, 0x0a307);
+	pci_write_config16(dev, 0x42, 0x0a307);
+
+	/* Sync DMA */
+	pci_write_config16(dev, 0x48, 0x000f);
+	pci_write_config16(dev, 0x4a, 0x1111);
+
+	/* 66 mhz */
+	pci_write_config16(dev, 0x54, 0xf00f);
+
+	/* Combine ide - sata configuration */
+	pci_write_config8(dev, 0x90, 0x0);
+
+	/* port 0 & 1 enable */
+	pci_write_config8(dev, 0x92, 0x33);
+
+	/* initialize SATA  */
+	pci_write_config16(dev, 0xa0, 0x0018);
+	pci_write_config32(dev, 0xa4, 0x00000264);
+	pci_write_config16(dev, 0xa0, 0x0040);
+	pci_write_config32(dev, 0xa4, 0x00220043);
+
+}
+
+static struct device_operations sata_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = sata_init,
+	.scan_bus         = 0,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_SATA,
+};
+
+static const struct pci_driver sata_driver_nr __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801EB_SATA,
+};
+

Copied and modified: trunk/src/southbridge/intel/i82801ex/smbus.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801ex/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -6,7 +6,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "i82801ex.h"
-#include "i82801ex_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {

Copied: trunk/src/southbridge/intel/i82801ex/smbus.h (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h)
@@ -0,0 +1,105 @@
+#include <device/smbus_def.h>
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL  0x2
+#define SMBHSTCMD  0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT  0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL  0xf
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+
+static void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while(byte & 1);
+	return loops?0:-1;
+}
+
+static int smbus_wait_until_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        smbus_delay();
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+	return loops?0:-1;
+}
+
+static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+	        smbus_delay();
+	        if (--loops == 0)
+	               break;
+	        byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while((byte&(1<<7)) == 0);
+	return loops?0:-1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/i82801ex/uhci.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/uhci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c)
@@ -0,0 +1,56 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ex.h"
+
+static void uhci_init(struct device *dev)
+{
+	uint32_t cmd;
+
+#if 1
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+	cmd = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND,
+		cmd | PCI_COMMAND_MASTER);
+
+
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+
+}
+
+static struct pci_operations lops_pci = {
+	/* The subsystem id follows the ide controller */
+	.set_subsystem = 0,
+};
+
+static struct device_operations uhci_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = uhci_init,
+	.scan_bus         = 0,
+	.enable           = i82801ex_enable,
+	.ops_pci          = &lops_pci,
+};
+
+static const struct pci_driver uhci_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_USB1,
+};
+
+static const struct pci_driver usb2_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_USB2,
+};
+
+static const struct pci_driver usb3_driver __pci_driver = {
+	.ops    = &uhci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801ER_USB3,
+};
+

Copied: trunk/src/southbridge/intel/i82801ex/watchdog.c (from r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801ex/watchdog.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c)
@@ -0,0 +1,29 @@
+#include <console/console.h>
+#include <watchdog.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+void watchdog_off(void)
+{
+        device_t dev;
+        unsigned long value,base;
+
+	/* turn off the ICH5 watchdog */
+        dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+        /* Enable I/O space */
+        value = pci_read_config16(dev, 0x04);
+        value |= (1 << 10);
+        pci_write_config16(dev, 0x04, value);
+        /* Get TCO base */
+        base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+        /* Disable the watchdog timer */
+        value = inw(base + 0x08);
+        value |= 1 << 11;
+        outw(value, base + 0x08);
+        /* Clear TCO timeout status */
+        outw(0x0008, base + 0x04);
+        outw(0x0002, base + 0x06);
+        printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+}
+

Modified: trunk/src/southbridge/intel/i82801gx/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801gx/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -18,24 +18,24 @@
 ##
 
 driver-y += i82801gx.c
-driver-y += i82801gx_ac97.c
-driver-y += i82801gx_azalia.c
-driver-y += i82801gx_ide.c
-driver-y += i82801gx_lpc.c
-driver-y += i82801gx_nic.c
-driver-y += i82801gx_pci.c
-driver-y += i82801gx_pcie.c
-driver-y += i82801gx_sata.c
-driver-y += i82801gx_smbus.c
-driver-y += i82801gx_usb.c
-driver-y += i82801gx_usb_ehci.c
+driver-y += ac97.c
+driver-y += azalia.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += pcie.c
+driver-y += sata.c
+driver-y += smbus.c
+driver-y += usb.c
+driver-y += usb_ehci.c
 
-ramstage-y += i82801gx_reset.c
-ramstage-y += i82801gx_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
-romstage-y += i82801gx_early_smbus.c
-romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c
+romstage-y += early_smbus.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
 

Copied: trunk/src/southbridge/intel/i82801gx/ac97.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/ac97.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ac97.c)
@@ -0,0 +1,303 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "i82801gx.h"
+
+#define NAMBAR		0x10
+#define   MASTER_VOL	0x02
+#define   PAGING	0x24
+#define   EXT_AUDIO	0x28
+#define   FUNC_SEL	0x66
+#define   INFO_IO	0x68
+#define   CONNECTOR	0x6a
+#define   VENDOR_ID1	0x7c
+#define   VENDOR_ID2	0x7e
+#define   SEC_VENDOR_ID1 0xfc
+#define   SEC_VENDOR_ID2 0xfe
+
+#define NABMBAR		0x14
+#define   GLOB_CNT	0x2c
+#define   GLOB_STA	0x30
+#define   CAS		0x34
+
+#define MMBAR		0x10
+#define   EXT_MODEM_ID1	0x3c
+#define   EXT_MODEM_ID2	0xbc
+
+#define MBAR		0x14
+#define   SEC_CODEC	0x40
+
+
+/* FIXME. This table is probably mainboard specific */
+static u16 ac97_function[16*2][4] = {
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
+	{ (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
+};
+
+static u16 nabmbar;
+static u16 nambar;
+
+static int ac97_semaphore(void)
+{
+	int timeout;
+	u8 reg8;
+
+	timeout = 0xffff;
+	do {
+		reg8 = inb(nabmbar + CAS);
+		timeout--;
+	} while ((reg8 & 1) && timeout);
+	if (! timeout) {
+		printk(BIOS_DEBUG, "Timeout!\n");
+	}
+
+	return (!timeout);
+}
+
+static void init_cnr(void)
+{
+	// TODO
+}
+
+static void program_sigid(struct device *dev, u32 id)
+{
+	pci_write_config32(dev, 0x2c, id);
+}
+
+static void ac97_audio_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+	int i;
+
+	printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
+
+	/* top 16 bits are zero, so don't read them */
+	nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
+	nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
+
+	reg16 = inw(nabmbar + GLOB_CNT);
+	reg16 |= (1 << 1); /* Remove AC_RESET# */
+	outw(reg16, nabmbar + GLOB_CNT);
+
+	/* Wait 600ms. Ouch. */
+	udelay(600 * 1000);
+
+	init_cnr();
+
+	/* Detect Primary AC'97 Codec */
+	reg32 = inl(nabmbar + GLOB_STA);
+	if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
+		/* Primary Codec not found */
+		printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
+		return;
+	}
+
+	ac97_semaphore();
+
+	/* Detect if codec is programmable */
+	outw(0x8000, nambar + MASTER_VOL);
+	ac97_semaphore();
+	if (inw(nambar + MASTER_VOL) != 0x8000) {
+		printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
+		return;
+	}
+
+	/* Program Vendor IDs */
+	reg32 = inw(nambar + VENDOR_ID1);
+	reg32 <<= 16;
+	reg32 |= (u16)inw(nambar + VENDOR_ID2);
+
+	program_sigid(dev, reg32);
+
+	/* Is Codec AC'97 2.3 compliant? */
+	reg16 = inw(nambar + EXT_AUDIO);
+	/* [11:10] = 10b -> AC'97 2.3 */
+	if ((reg16 & 0x0c00) != 0x0800) {
+		/* No 2.3 Codec. We're done */
+		return;
+	}
+
+	/* Select Page 1 */
+	reg16 = inw(nambar + PAGING);
+	reg16 &= 0xfff0;
+	reg16 |= 0x0001;
+	outw(reg16, nambar + PAGING);
+
+	for (i = 0x0a * 2; i > 0; i--) {
+		outw(i, nambar + FUNC_SEL);
+
+		/* Function could not be selected. Next one */
+		if (inw(nambar + FUNC_SEL) != i)
+			continue;
+
+		reg16 = inw(nambar + INFO_IO);
+
+		/* Function Information present? */
+		if (!(reg16 & (1 << 0)))
+			continue;
+
+		/* Function Information valid? */
+		if (!(reg16 & (1 << 4)))
+			continue;
+
+		/* Program Buffer Delay [9:5] */
+		reg16 &= 0x03e0;
+		reg16 |= ac97_function[i][0];
+
+		/* Program Gain [15:11] */
+		reg16 |= ac97_function[i][1];
+
+		/* Program Inversion [10] */
+		reg16 |= ac97_function[i][2];
+
+		outw(reg16, nambar + INFO_IO);
+
+		/* Program Connector / Jack Location */
+		reg16 = inw(nambar + CONNECTOR);
+		reg16 &= 0x1fff;
+		reg16 |= ac97_function[i][3];
+		outw(reg16, nambar + CONNECTOR);
+	}
+}
+
+static void ac97_modem_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+	u16 mmbar, mbar;
+
+	mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
+	mbar = pci_read_config16(dev, MBAR) & 0xfffe;
+
+	reg16 = inw(mmbar + EXT_MODEM_ID1);
+	if ((reg16 & 0xc000) != 0xc000 ) {
+		if (reg16 & (1 << 0)) {
+			reg32 = inw(mmbar + VENDOR_ID2);
+			reg32 <<= 16;
+			reg32 |= (u16)inw(mmbar + VENDOR_ID1);
+			program_sigid(dev, reg32);
+			return;
+		}
+	}
+
+	/* Secondary codec? */
+	reg16 = inw(mbar + SEC_CODEC);
+	if ((reg16 & (1 << 9)) == 0)
+		return;
+
+	reg16 = inw(mmbar + EXT_MODEM_ID2);
+	if ((reg16 & 0xc000) == 0x4000) {
+		if (reg16 & (1 << 0)) {
+			reg32 = inw(mmbar + SEC_VENDOR_ID2);
+			reg32 <<= 16;
+			reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
+			program_sigid(dev, reg32);
+			return;
+		}
+	}
+}
+
+static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations ac97_pci_ops = {
+	.set_subsystem    = ac97_set_subsystem,
+};
+
+static struct device_operations ac97_audio_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ac97_audio_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &ac97_pci_ops,
+};
+
+static struct device_operations ac97_modem_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ac97_modem_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &ac97_pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+/* Note: 82801GU (ICH7-U) doesn't have AC97 audio. */
+static const struct pci_driver i82801gx_ac97_audio __pci_driver = {
+	.ops	= &ac97_audio_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27de,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+/* Note: 82801GU (ICH7-U) doesn't have AC97 modem. */
+static const struct pci_driver i82801gx_ac97_modem __pci_driver = {
+	.ops	= &ac97_modem_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27dd,
+};

Copied: trunk/src/southbridge/intel/i82801gx/acpi/ac97.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/ac97.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel i82801G AC'97 Audio and Modem */
+
+// Intel AC'97 Audio 0:1e.2
+
+Device (AUD0)
+{
+	Name (_ADR, 0x001e0002)
+}
+
+// Intel AC'97 Modem 0:1e.3
+
+Device (MODM)
+{
+	Name (_ADR, 0x001e0003)
+
+	Name (_PRW, Package(){ 5, 4 })
+}
+
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/audio.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/audio.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel i82801G HDA */
+
+// Intel High Definition Audio (Azalia) 0:1b.0
+
+Device (HDEF)
+{
+	Name (_ADR, 0x001b0000)
+
+	// Power Resources for Wake
+	Name (_PRW, Package(){
+		5,  // Bit 5 of GPE
+		4   // Can wake from S4 state.
+	})
+}
+

Modified: trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl	Wed Dec  8 06:42:47 2010	(r6149)
@@ -159,30 +159,30 @@
 }
 
 // 0:1b.0 High Definition Audio (Azalia)
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/audio.asl"
 
 // PCI Express Ports
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pcie.asl"
 
 // USB
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/usb.asl"
 
 // PCI Bridge
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pci.asl"
 
 // AC97 Audio and Modem
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/ac97.asl"
 
 // LPC Bridge
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/lpc.asl"
 
 // PATA
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pata.asl"
 
 // SATA
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/sata.asl"
 
 // SMBus
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/smbus.asl"
 
 

Copied: trunk/src/southbridge/intel/i82801gx/acpi/irqlinks.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/irqlinks.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl)
@@ -0,0 +1,493 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LNKA)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 1)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTA)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTA
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTA, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 2)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTB)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTB
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTB, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 3)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTC)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTC
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTC, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 4)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTD)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTD
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTD, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 5)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTE)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTE
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTE, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 6)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTF)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTF
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTF, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 7)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTG)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTG
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTG, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 8)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTH)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTH
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTH, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+

Copied and modified: trunk/src/southbridge/intel/i82801gx/acpi/lpc.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl)
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801gx/acpi/lpc.asl	Wed Dec  8 06:42:47 2010	(r6149)
@@ -51,7 +51,7 @@
 		RCBA,	18,
 	}
 
-	#include "../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl"
+	#include "../../../southbridge/intel/i82801gx/acpi/irqlinks.asl"
 
 	#include "acpi/ec.asl"
 

Copied: trunk/src/southbridge/intel/i82801gx/acpi/pata.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/pata.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl)
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel PATA Controller 0:1f.1
+
+Device (PATA)
+{
+	Name (_ADR, 0x001f0001)
+
+	Device (PRID)
+	{
+		Name (_ADR, 0)
+
+		// Get Timing Mode
+		Method (_GTM)
+		{
+			Name(PBUF, Buffer(20) {
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00 })
+
+			CreateDwordField (PBUF,  0, PIO0)
+			CreateDwordField (PBUF,  4, DMA0)
+			CreateDwordField (PBUF,  8, PIO1)
+			CreateDwordField (PBUF, 12, DMA1)
+			CreateDwordField (PBUF, 16, FLAG)
+
+			// TODO fill return structure
+
+			Return (PBUF)
+		}
+
+		// Set Timing Mode
+		Method (_STM, 3)
+		{
+			CreateDwordField (Arg0,  0, PIO0)
+			CreateDwordField (Arg0,  4, DMA0)
+			CreateDwordField (Arg0,  8, PIO1)
+			CreateDwordField (Arg0, 12, DMA1)
+			CreateDwordField (Arg0, 16, FLAG)
+
+			// TODO: Do the deed
+		}
+
+		Device (DSK0)
+		{
+			Name (_ADR, 0)
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+		Device (DSK1)
+		{
+			Name (_ADR, 1)
+
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+	}
+}
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/pci.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/pci.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl)
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel PCI to PCI bridge 0:1e.0
+
+Device (PCIB)
+{
+	Name (_ADR, 0x001e0000)
+
+	Device (SLT1)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_PRW, Package(){ 11, 4 })
+	}
+
+	Device (SLT2)
+	{
+		Name (_ADR, 0x00010000)
+		Name (_PRW, Package(){ 11, 4 })
+	}
+
+	Device (SLT3)
+	{
+		Name (_ADR, 0x00020000)
+		Name (_PRW, Package(){ 11, 4 })
+	}
+
+	Device (SLT6)
+	{
+		Name (_ADR, 0x00050000)
+		Name (_PRW, Package(){ 11, 4 })
+	}
+
+	Device (LANC)
+	{
+		Name (_ADR, 0x00080000)
+		Name (_PRW, Package(){ 11, 3 })
+	}
+
+	Device (LANR)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_PRW, Package(){ 11, 3 })
+	}
+
+	// TODO: How many slots, where?
+
+	// PCI Interrupt Routing.
+	// If PICM is set, interrupts are routed over the i8259, otherwise
+	// over the IOAPIC. (Really? If they're above 15 they need to be routed
+	// fixed over the IOAPIC?)
+
+	Method (_PRT)
+	{
+		#include "acpi/ich7_pci_irqs.asl"
+	}
+
+}
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/pcie.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/pcie.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl)
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel i82801G PCIe support */
+
+// PCI Express Ports
+
+Device (RP01)
+{
+	NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 16 },
+				Package() { 0x0000ffff, 1, 0, 17 },
+				Package() { 0x0000ffff, 2, 0, 18 },
+				Package() { 0x0000ffff, 3, 0, 19 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP02)
+{
+	NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 17 },
+				Package() { 0x0000ffff, 1, 0, 18 },
+				Package() { 0x0000ffff, 2, 0, 19 },
+				Package() { 0x0000ffff, 3, 0, 16 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+			})
+
+		}
+
+	}
+}
+
+
+Device (RP03)
+{
+	NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 18 },
+				Package() { 0x0000ffff, 1, 0, 19 },
+				Package() { 0x0000ffff, 2, 0, 16 },
+				Package() { 0x0000ffff, 3, 0, 17 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
+			})
+
+		}
+
+	}
+}
+
+
+Device (RP04)
+{
+	NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 19 },
+				Package() { 0x0000ffff, 1, 0, 16 },
+				Package() { 0x0000ffff, 2, 0, 17 },
+				Package() { 0x0000ffff, 3, 0, 18 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }
+			})
+
+		}
+
+	}
+}
+
+
+Device (RP05)
+{
+	NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 16 },
+				Package() { 0x0000ffff, 1, 0, 17 },
+				Package() { 0x0000ffff, 2, 0, 18 },
+				Package() { 0x0000ffff, 3, 0, 19 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+			})
+
+		}
+
+	}
+}
+
+
+Device (RP06)
+{
+	NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 17 },
+				Package() { 0x0000ffff, 1, 0, 18 },
+				Package() { 0x0000ffff, 2, 0, 19 },
+				Package() { 0x0000ffff, 3, 0, 16 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+			})
+
+		}
+
+	}
+}
+
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/sata.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/sata.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl)
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SATA Controller 0:1f.2
+
+// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
+// pluggable
+
+Device (SATA)
+{
+	Name (_ADR, 0x001f0002)
+
+	Device (PRID)
+	{
+		Name (_ADR, 0)
+
+		// Get Timing Mode
+		Method (_GTM)
+		{
+			Name(PBUF, Buffer(20) {
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00 })
+
+			CreateDwordField (PBUF,  0, PIO0)
+			CreateDwordField (PBUF,  4, DMA0)
+			CreateDwordField (PBUF,  8, PIO1)
+			CreateDwordField (PBUF, 12, DMA1)
+			CreateDwordField (PBUF, 16, FLAG)
+
+			// TODO fill return structure
+
+			Return (PBUF)
+		}
+
+		// Set Timing Mode
+		Method (_STM, 3)
+		{
+			CreateDwordField (Arg0,  0, PIO0)
+			CreateDwordField (Arg0,  4, DMA0)
+			CreateDwordField (Arg0,  8, PIO1)
+			CreateDwordField (Arg0, 12, DMA1)
+			CreateDwordField (Arg0, 16, FLAG)
+
+			// TODO: Do the deed
+		}
+
+		Device (DSK0)
+		{
+			Name (_ADR, 0)
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+		Device (DSK1)
+		{
+			Name (_ADR, 1)
+
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+	}
+}
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/smbus.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/smbus.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl)
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SMBus Controller 0:1f.3
+
+Device (SBUS)
+{
+	Name (_ADR, 0x001f0003)
+
+	OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
+	Field(SMBP, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x40),
+		,	2,
+		I2CE,	1
+	}
+
+	OperationRegion (SMBI, SystemIO, 0x400, 0x20)
+	Field (SMBI, ByteAcc, NoLock, Preserve)
+	{
+		HSTS,	8,	// Host Status
+		,	8,
+		HCNT,	8,	// Host Control
+		HCMD,	8,	// Host Command
+		TXSA,	8,	// Transmit Slave Address
+		DAT0,	8,	// Host Data 0
+		DAT1,	8,	// Host Data 1
+		HBDB,	8,	// Host Block Data Byte
+		PECK,	8,	// Packet Error Check
+		RXSA,	8,	// Receive Slave Address
+		RXDA,	16,	// Receive Slave Data
+		AUXS,	8,	// Auxiliary Status
+		AUXC,	8,	// Auxiliary Control
+		SLPC,	8,	// SMLink Pin Control
+		SBPC,	8,	// SMBus Pin Control
+		SSTS,	8,	// Slave Status
+		SCMD,	8,	// Slave Command
+		NADR,	8,	// Notify Device Address
+		NDLB,	8,	// Notify Data Low Byte
+		NDLH,	8,	// Notify Data High Byte
+	}
+
+#ifdef ENABLE_SMBUS_METHODS
+	// Kill all SMBus communication
+	Method (KILL, 0, Serialized)
+	{
+		Or (HCNT, 0x02, HCNT)	// Send Kill
+		Or (HSTS, 0xff, HSTS)	// Clean Status
+	}
+
+	// Check if last operation completed
+	// return	Failure = 0, Success = 1
+	Method (CMPL, 0, Serialized)
+	{
+		Store (4000, Local0)		// Timeout 200ms in 50us steps
+		While (Local0) {
+			If (And(HSTS, 0x02)) {	// Completion Status?
+				Return (1)	// Operation Completed
+			} Else {
+				Stall (50)
+				Decrement (Local0)
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			}
+		}
+
+		Return (0)		//  Failure
+	}
+
+
+	// Wait for SMBus to become ready
+	Method (SRDY, 0, Serialized)
+	{
+		Store (200, Local0)	// Timeout 200ms
+		While (Local0) {
+			If (And(HSTS, 0x40)) {		// IN_USE?
+				Sleep(1)		// Wait 1ms
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					Return (1)
+				}
+			} Else {
+				Store (0, Local0)	// We're ready
+			}
+		}
+
+		Store (4000, Local0)	// Timeout 200ms (50us * 4000)
+		While (Local0) {
+			If (And (HSTS, 0x01)) {		// Host Busy?
+				Stall(50)		// Wait 50us
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			} Else {
+				Return (0)		// Success
+			}
+		}
+
+		Return (1)		// Failure
+	}
+
+	// SMBus Send Byte
+	// Arg0:	Address
+	// Arg1:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SSXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Data Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Receive Byte
+	// Arg0:	Address
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+
+		Store (0x44, HCNT)	// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+
+
+	// SMBus Write Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Arg2:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SWRB, 3, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Command
+		Store (Arg2, DAT0)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Read Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRDB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)			// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+		Store (Arg1, HCMD)		// Command
+
+		Store (0x48, HCNT)		// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+#endif
+}
+

Copied: trunk/src/southbridge/intel/i82801gx/acpi/usb.asl (from r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/acpi/usb.asl	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl)
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel i82801G USB support */
+
+// USB Controller 0:1d.0
+
+Device (USB1)
+{
+	Name(_ADR, 0x001d0000)
+
+	OperationRegion(U01P, PCI_Config, 0, 256)
+	Field(U01P, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0xc4),
+		U1WE, 2		// USB Wake Enable
+	}
+
+	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
+
+	Method (_PSW, 1)	// Power State Wake method
+	{
+		// USB Controller can wake OS from Sleep State
+		If (Arg0) {
+			Store (3, U1WE)
+		} Else {
+			Store (0, U1WE)
+		}
+	}
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+}
+
+
+// USB Controller 0:1d.1
+
+Device (USB2)
+{
+	Name(_ADR, 0x001d0001)
+
+	OperationRegion(U02P, PCI_Config, 0, 256)
+	Field(U02P, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0xc4),
+		U2WE, 2		// USB Wake Enable
+	}
+
+	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
+
+	Method (_PSW, 1)	// Power State Wake method
+	{
+		// USB Controller can wake OS from Sleep State
+		If (Arg0) {
+			Store (3, U2WE)
+		} Else {
+			Store (0, U2WE)
+		}
+	}
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+}
+
+
+// USB Controller 0:1d.2
+
+Device (USB3)
+{
+	Name(_ADR, 0x001d0002)
+
+	OperationRegion(U03P, PCI_Config, 0, 256)
+	Field(U03P, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0xc4),
+		U3WE, 2		// USB Wake Enable
+	}
+
+	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
+
+	Method (_PSW, 1)	// Power State Wake method
+	{
+		// USB Controller can wake OS from Sleep State
+		If (Arg0) {
+			Store (3, U3WE)
+		} Else {
+			Store (0, U3WE)
+		}
+	}
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+}
+
+
+// USB Controller 0:1d.3
+
+Device (USB4)
+{
+	Name(_ADR, 0x001d0003)
+
+	OperationRegion(U04P, PCI_Config, 0, 256)
+	Field(U04P, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0xc4),
+		U4WE, 2		// USB Wake Enable
+	}
+
+	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
+
+	Method (_PSW, 1)	// Power State Wake method
+	{
+		// USB Controller can wake OS from Sleep State
+		If (Arg0) {
+			Store (3, U4WE)
+		} Else {
+			Store (0, U4WE)
+		}
+	}
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+}
+
+
+// EHCI Controller 0:1d.7
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0007)
+
+	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+	Device (HUB7)
+	{
+		Name (_ADR, 0x00000000)
+
+		// How many are there?
+		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+	}
+}
+
+

Copied: trunk/src/southbridge/intel/i82801gx/azalia.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/azalia.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c)
@@ -0,0 +1,347 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "i82801gx.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+typedef struct southbridge_intel_i82801gx_config config_t;
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 reg32;
+	int count;
+
+	/* Write (val & mask) to port */
+	val &= mask;
+	reg32 = read32(port);
+	reg32 &= ~mask;
+	reg32 |= val;
+	write32(port, reg32);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		reg32 = read32(port);
+		reg32 &= mask;
+	} while ((reg32 != val) && --count);
+
+	/* Timeout occurred */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static int codec_detect(u32 base)
+{
+	u32 reg32;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Read in Codec location (BAR + 0xe)[2..0]*/
+	reg32 = read32(base + 0xe);
+	reg32 &= 0x0f;
+	if (!reg32)
+		goto no_codec;
+
+	return reg32;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
+	return 0;
+}
+
+const u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
+
+static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
+{
+	int idx=0;
+
+	while (idx < (cim_verb_data_size / sizeof(u32))) {
+		u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+		if (cim_verb_data[idx] != viddid) {
+			idx += verb_size + 3; // skip verb + header
+			continue;
+		}
+		*verb = &cim_verb_data[idx+3];
+		return verb_size;
+	}
+
+	/* Not all codecs need to load another verb */
+	return 0;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 reg32 = read32(base +  HDA_ICII_REG);
+		if (!(reg32 & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+
+static int wait_for_valid(u32 base)
+{
+	u32 reg32;
+
+	/* Send the verb to the codec */
+	reg32 = read32(base + 0x68);
+	reg32 |= (1 << 0) | (1 << 1);
+	write32(base + 0x68, reg32);
+
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		reg32 = read32(base + HDA_ICII_REG);
+		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+static void codec_init(struct device *dev, u32 base, int addr)
+{
+	u32 reg32;
+	const u32 *verb;
+	u32 verb_size;
+	int i;
+
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	reg32 = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, reg32);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	reg32 = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
+	verb_size = find_verb(dev, reg32, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
+
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
+}
+
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(dev, base, i);
+	}
+}
+
+static void azalia_init(struct device *dev)
+{
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	u8 reg8;
+	u32 reg32;
+
+#if CONFIG_MMCONF_SUPPORT
+	// ESD
+	reg32 = pci_mmio_read_config32(dev, 0x134);
+	reg32 &= 0xff00ffff;
+	reg32 |= (2 << 16);
+	pci_mmio_write_config32(dev, 0x134, reg32);
+
+	// Link1 description
+	reg32 = pci_mmio_read_config32(dev, 0x140);
+	reg32 &= 0xff00ffff;
+	reg32 |= (2 << 16);
+	pci_mmio_write_config32(dev, 0x140, reg32);
+
+	// Port VC0 Resource Control Register
+	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 &= 0xffffff00;
+	reg32 |= 1;
+	pci_mmio_write_config32(dev, 0x114, reg32);
+
+	// VCi traffic class
+	reg8 = pci_mmio_read_config8(dev, 0x44);
+	reg8 |= (7 << 0); // TC7
+	pci_mmio_write_config8(dev, 0x44, reg8);
+
+	// VCi Resource Control
+	reg32 = pci_mmio_read_config32(dev, 0x120);
+	reg32 |= (1 << 31);
+	reg32 |= (1 << 24); // VCi ID
+	reg32 |= (0x80 << 0); // VCi map
+	pci_mmio_write_config32(dev, 0x120, reg32);
+#else
+#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
+#endif
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	pci_write_config8(dev, 0x3c, 0x0a); // unused?
+
+	// TODO Actually check if we're AC97 or HDA instead of hardcoding this
+	// here, in devicetree.cb and/or romstage.c.
+	reg8 = pci_read_config8(dev, 0x40);
+	reg8 |= (1 << 3); // Clear Clock Detect Bit
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 |= (1 << 2); // Enable clock detection
+	pci_write_config8(dev, 0x40, reg8);
+	mdelay(1);
+	reg8 = pci_read_config8(dev, 0x40);
+	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
+
+	//
+	reg8 = pci_read_config8(dev, 0x40); // Audio Control
+	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+	pci_write_config8(dev, 0x40, reg8);
+
+	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
+	reg8 &= ~(1 << 7); // Docking not supported
+	pci_write_config8(dev, 0x4d, reg8);
+#if 0
+	/* Set routing pin */
+	pci_write_config32(dev, 0xf8, 0x0);
+	pci_write_config8(dev, 0xfc, 0xAA);
+
+	/* Set INTA */
+	pci_write_config8(dev, 0x63, 0x0);
+
+	/* Enable azalia, disable ac97 */
+	// pm_iowrite(0x59, 0xB);
+#endif
+
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	// NOTE this will break as soon as the Azalia get's a bar above
+	// 4G. Is there anything we can do about it?
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
+		codecs_init(dev, base, codec_mask);
+	}
+}
+
+static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations azalia_pci_ops = {
+	.set_subsystem    = azalia_set_subsystem,
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= azalia_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &azalia_pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_azalia __pci_driver = {
+	.ops	= &azalia_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27d8,
+};
+

Copied and modified: trunk/src/southbridge/intel/i82801gx/early_smbus.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801gx/early_smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801gx.h"
-#include "i82801gx_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {

Copied: trunk/src/southbridge/intel/i82801gx/ide.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/ide.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_ide.c)
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+
+typedef struct southbridge_intel_i82801gx_config config_t;
+
+static void ide_init(struct device *dev)
+{
+	u16 ideTimingConfig;
+	u32 reg32;
+	u32 enable_primary, enable_secondary;
+
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
+	if (config == NULL) {
+		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
+		// Trying to set somewhat safe defaults instead of bailing out.
+		enable_primary = enable_secondary = 1;
+	} else {
+		enable_primary = config->ide_enable_primary;
+		enable_secondary = config->ide_enable_secondary;
+	}
+
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+
+	/* Native Capable, but not enabled. */
+	pci_write_config8(dev, 0x09, 0x8a);
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	ideTimingConfig |= IDE_SITRE;
+	if (enable_primary) {
+		/* Enable primary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		ideTimingConfig |= (2 << 12); // ISP = 3 clocks
+		ideTimingConfig |= (3 << 8); // RCT = 1 clock
+		ideTimingConfig |= (1 << 1); // IE0
+		ideTimingConfig |= (1 << 0); // TIME0
+		printk(BIOS_DEBUG, "IDE0 ");
+	}
+	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	ideTimingConfig |= IDE_SITRE;
+	if (enable_secondary) {
+		/* Enable secondary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		ideTimingConfig |= (2 << 12); // ISP = 3 clocks
+		ideTimingConfig |= (3 << 8); // RCT = 1 clock
+		ideTimingConfig |= (1 << 1); // IE0
+		ideTimingConfig |= (1 << 0); // TIME0
+		printk(BIOS_DEBUG, "IDE1 ");
+	}
+	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
+
+	/* Set IDE I/O Configuration */
+	reg32 = 0;
+	/* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
+	if (enable_primary)
+		reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
+	if (enable_secondary)
+		reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
+	pci_write_config32(dev, IDE_CONFIG, reg32);
+
+	/* Set Interrupt Line */
+	/* Interrupt Pin is set by D31IP.PIP */
+	pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
+
+	printk(BIOS_DEBUG, "\n");
+}
+
+static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations ide_pci_ops = {
+	.set_subsystem    = ide_set_subsystem,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &ide_pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gx_ide __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27df,
+};

Copied: trunk/src/southbridge/intel/i82801gx/lpc.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/lpc.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c)
@@ -0,0 +1,536 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include "i82801gx.h"
+
+#define NMI_OFF	0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT	0
+#define TEST_SMM_FLASH_LOCKDOWN		0
+
+typedef struct southbridge_intel_i82801gx_config config_t;
+
+static void i82801gx_enable_apic(struct device *dev)
+{
+	int i;
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Enable ACPI I/O and power management.
+	 * Set SCI IRQ to IRQ9
+	 */
+	pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
+	for (i=0; i<3; i++) {
+		*ioapic_index = i;
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
+		reg32 = *ioapic_data;
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
+	}
+
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void i82801gx_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit for one frame. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+}
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+static void i82801gx_pirq_init(device_t dev)
+{
+	device_t irq_dev;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+	pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+	pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+	pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+	pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+	pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+	/* Eric Biederman once said we should let the OS do this.
+	 * I am not so sure anymore he was right.
+	 */
+
+	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+		u8 int_pin=0, int_line=0;
+
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+			continue;
+
+		int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+		switch (int_pin) {
+		case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+		case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+		case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+		case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+		}
+
+		if (!int_line)
+			continue;
+
+		pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+	}
+}
+
+static void i82801gx_gpi_routing(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+	u32 reg32 = 0;
+
+	/* An array would be much nicer here, or some
+	 * other method of doing this.
+	 */
+	reg32 |= (config->gpi0_routing & 0x03) << 0;
+	reg32 |= (config->gpi1_routing & 0x03) << 2;
+	reg32 |= (config->gpi2_routing & 0x03) << 4;
+	reg32 |= (config->gpi3_routing & 0x03) << 6;
+	reg32 |= (config->gpi4_routing & 0x03) << 8;
+	reg32 |= (config->gpi5_routing & 0x03) << 10;
+	reg32 |= (config->gpi6_routing & 0x03) << 12;
+	reg32 |= (config->gpi7_routing & 0x03) << 14;
+	reg32 |= (config->gpi8_routing & 0x03) << 16;
+	reg32 |= (config->gpi9_routing & 0x03) << 18;
+	reg32 |= (config->gpi10_routing & 0x03) << 20;
+	reg32 |= (config->gpi11_routing & 0x03) << 22;
+	reg32 |= (config->gpi12_routing & 0x03) << 24;
+	reg32 |= (config->gpi13_routing & 0x03) << 26;
+	reg32 |= (config->gpi14_routing & 0x03) << 28;
+	reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+	pci_write_config32(dev, 0xb8, reg32);
+}
+
+extern u8 acpi_slp_type;
+
+static void i82801gx_power_options(device_t dev)
+{
+	u8 reg8;
+	u16 reg16, pmbase;
+	u32 reg32;
+	const char *state;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int nmi_option;
+
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 *
+	 * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
+	 */
+	if (get_option(&pwr_on, "power_on_after_fail") < 0)
+		pwr_on = MAINBOARD_POWER_ON;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	reg8 &= 0xfe;
+	switch (pwr_on) {
+	case MAINBOARD_POWER_OFF:
+		reg8 |= 1;
+		state = "off";
+		break;
+	case MAINBOARD_POWER_ON:
+		reg8 &= ~1;
+		state = "on";
+		break;
+	case MAINBOARD_POWER_KEEP:
+		reg8 &= ~1;
+		state = "state keep";
+		break;
+	default:
+		state = "undefined";
+	}
+
+	reg8 |= (3 << 4);	/* avoid #S4 assertions */
+	reg8 &= ~(1 << 3);	/* minimum asssertion is 1 to 2 RTCCLK */
+
+	pci_write_config8(dev, GEN_PMCON_3, reg8);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+	/* Set up NMI on errors. */
+	reg8 = inb(0x61);
+	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
+	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
+	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+	outb(reg8, 0x61);
+
+	reg8 = inb(0x70);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		printk(BIOS_INFO, "NMI sources enabled.\n");
+		reg8 &= ~(1 << 7);	/* Set NMI. */
+	} else {
+		printk(BIOS_INFO, "NMI sources disabled.\n");
+		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
+	}
+	outb(reg8, 0x70);
+
+	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 &= ~(3 << 0);	// SMI# rate 1 minute
+	reg16 |= (1 << 2);	// CLKRUN_EN - Mobile/Ultra only
+	reg16 |= (1 << 3);	// Speedstep Enable - Mobile/Ultra only
+	reg16 |= (1 << 5);	// CPUSLP_EN Desktop only
+	// another laptop wants this?
+	// reg16 &= ~(1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
+	reg16 |= (1 << 10);	// BIOS_PCI_EXP_EN - Desktop/Mobile only
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+	 * periodic SMIs.
+	 */
+	reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
+	pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	// Set the board's GPI routing.
+	i82801gx_gpi_routing(dev);
+
+	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+	outl(config->gpe0_en, pmbase + GPE0_EN);
+	outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+	/* Set up power management block and determine sleep mode */
+	reg32 = inl(pmbase + 0x04); // PM1_CNT
+
+	reg32 &= ~(7 << 10);	// SLP_TYP
+	reg32 |= (1 << 1);	// enable C3->C0 transition on bus master
+	reg32 |= (1 << 0);	// SCI_EN
+	outl(reg32, pmbase + 0x04);
+}
+
+static void i82801gx_configure_cstates(device_t dev)
+{
+	u8 reg8;
+
+	reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
+	reg8 |= (1 << 4) | (1 << 3) | (1 << 2);	// Enable Popup & Popdown
+	pci_write_config8(dev, 0xa9, reg8);
+
+	// Set Deeper Sleep configuration to recommended values
+	reg8 = pci_read_config8(dev, 0xaa);
+	reg8 &= 0xf0;
+	reg8 |= (2 << 2);	// Deeper Sleep to Stop CPU: 34-40us
+	reg8 |= (2 << 0);	// Deeper Sleep to Sleep: 15us
+	pci_write_config8(dev, 0xaa, reg8);
+}
+
+static void i82801gx_rtc_init(struct device *dev)
+{
+	u8 reg8;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~RTC_BATTERY_DEAD;
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
+
+	rtc_init(rtc_failed);
+}
+
+static void enable_hpet(void)
+{
+	u32 reg32;
+
+	/* Move HPET to default address 0xfed00000 and enable it */
+	reg32 = RCBA32(HPTC);
+	reg32 |= (1 << 7); // HPET Address Enable
+	reg32 &= ~(3 << 0);
+	RCBA32(HPTC) = reg32;
+}
+
+static void enable_clock_gating(void)
+{
+	u32 reg32;
+
+	/* Enable Clock Gating for most devices */
+	reg32 = RCBA32(CG);
+	reg32 |= (1 << 31);	// LPC clock gating
+	reg32 |= (1 << 30);	// PATA clock gating
+	// SATA clock gating
+	reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+	reg32 |= (1 << 23);	// AC97 clock gating
+	reg32 |= (1 << 19);	// USB EHCI clock gating
+	reg32 |= (1 << 3) | (1 << 1);	// DMI clock gating
+	reg32 |= (1 << 2);	// PCIe clock gating;
+	reg32 &= ~(1 << 20); // No static clock gating for USB
+	reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
+	RCBA32(CG) = reg32;
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void i82801gx_lock_smm(struct device *dev)
+{
+	void smm_lock(void);
+#if TEST_SMM_FLASH_LOCKDOWN
+	u8 reg8;
+#endif
+
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+	outb(0xe1, 0xb2); // Enable ACPI mode
+	printk(BIOS_DEBUG, "done.\n");
+#else
+	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+	outb(0x1e, 0xb2); // Disable ACPI mode
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+	/* Don't allow evil boot loaders, kernels, or
+	 * userspace applications to deceive us:
+	 */
+	smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+	/* Now try this: */
+	printk(BIOS_DEBUG, "Locking BIOS to RO... ");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	reg8 &= ~(1 << 0);			/* clear BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+	reg8 |= (1 << 1);			/* set BLE */
+	pci_write_config8(dev, 0xdc, reg8);
+	printk(BIOS_DEBUG, "ok.\n");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+
+	printk(BIOS_DEBUG, "Writing:\n");
+	*(volatile u8 *)0xfff00000 = 0x00;
+	printk(BIOS_DEBUG, "Testing:\n");
+	reg8 |= (1 << 0);			/* set BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	printk(BIOS_DEBUG, "Done.\n");
+#endif
+}
+#endif
+
+#define SPIBASE 0x3020
+static void i82801gx_spi_init(void)
+{
+	u16 spicontrol;
+
+	spicontrol = RCBA16(SPIBASE + 2);
+	spicontrol &= ~(1 << 0); // SPI Access Request
+	RCBA16(SPIBASE + 2) = spicontrol;
+}
+
+static void i82801gx_fixups(struct device *dev)
+{
+	/* This needs to happen after PCI enumeration */
+	RCBA32(0x1d40) |= 1;
+
+	/* USB Transient Disconnect Detect:
+	 * Prevent a SE0 condition on the USB ports from being
+	 * interpreted by the UHCI controller as a disconnect
+	 */
+	pci_write_config8(dev, 0xad, 0x3);
+}
+
+static void lpc_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
+
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	i82801gx_enable_apic(dev);
+
+	i82801gx_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	i82801gx_pirq_init(dev);
+
+	/* Setup power options. */
+	i82801gx_power_options(dev);
+
+	/* Configure Cx state registers */
+	i82801gx_configure_cstates(dev);
+
+	/* Set the state of the GPIO lines. */
+	//gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	i82801gx_rtc_init(dev);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers, if present. */
+	enable_hpet();
+
+	/* Initialize Clock Gating */
+	enable_clock_gating();
+
+	setup_i8259();
+
+	/* The OS should do this? */
+	/* Interrupt 9 should be level triggered (SCI) */
+	i8259_configure_irq_trigger(9, 1);
+
+#if CONFIG_HAVE_SMI_HANDLER
+	i82801gx_lock_smm(dev);
+#endif
+
+	i82801gx_spi_init();
+
+	i82801gx_fixups(dev);
+}
+
+static void i82801gx_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= i82801gx_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &pci_ops,
+};
+
+/* 82801GH (ICH7 DH) */
+static const struct pci_driver ich7_dh_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27b0,
+};
+
+/* 82801GB/GR (ICH7/ICH7R) */
+static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27b8,
+};
+
+/* 82801GBM/GU (ICH7-M/ICH7-U) */
+static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27b9,
+};
+
+/* 82801GHM (ICH7-M DH) */
+static const struct pci_driver ich7m_dh_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27bd,
+};

Copied: trunk/src/southbridge/intel/i82801gx/nic.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/nic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nic.c)
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This code should work for all ICH* southbridges with a NIC. */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void nic_init(struct device *dev)
+{
+	/* Nothing yet */
+}
+
+static struct device_operations nic_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= nic_init,
+	.scan_bus		= 0,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+/* Note: 82801GU (ICH7-U) doesn't have a NIC. */
+/* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used. */
+static const struct pci_driver i82801gx_nic __pci_driver = {
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27dc,
+};

Copied: trunk/src/southbridge/intel/i82801gx/nvs.h (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/nvs.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_nvs.h)
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+typedef struct {
+	/* Miscellaneous */
+	u16	osys; /* 0x00 - Operating System */
+	u8	smif; /* 0x02 - SMI function call ("TRAP") */
+	u8	prm0; /* 0x03 - SMI function call parameter */
+	u8	prm1; /* 0x04 - SMI function call parameter */
+	u8	scif; /* 0x05 - SCI function call (via _L00) */
+	u8	prm2; /* 0x06 - SCI function call parameter */
+	u8	prm3; /* 0x07 - SCI function call parameter */
+	u8	lckf; /* 0x08 - Global Lock function for EC */
+	u8	prm4; /* 0x09 - Lock function parameter */
+	u8	prm5; /* 0x0a - Lock function parameter */
+	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
+	u8	lids; /* 0x0f - LID state (open = 1) */
+	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	u8	dbgs; /* 0x11 - Debug state */
+	u8	linx; /* 0x12 - Linux OS */
+	u8	dckn; /* 0x13 - PCIe docking state */
+	/* Thermal policy */
+	u8	actt; /* 0x14 - active trip point */
+	u8	psvt; /* 0x15 - passive trip point */
+	u8	tc1v; /* 0x16 - passive trip point TC1 */
+	u8	tc2v; /* 0x17 - passive trip point TC2 */
+	u8	tspv; /* 0x18 - passive trip point TSP */
+	u8	crtt; /* 0x19 - critical trip point */
+	u8	dtse; /* 0x1a - Digital Thermal Sensor enable */
+	u8	dts1; /* 0x1b - DT sensor 1 */
+	u8	dts2; /* 0x1c - DT sensor 2 */
+	u8	rsvd2;
+	/* Battery Support */
+	u8	bnum; /* 0x1e - number of batteries */
+	u8	b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
+	u8	b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
+	u8	rsvd3[3];
+	/* Processor Identification */
+	u8	apic; /* 0x28 - APIC enabled */
+	u8	mpen; /* 0x29 - MP capable/enabled */
+	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
+	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
+	u8	ppcm; /* 0x2c - Max. PPC state */
+	u8	rsvd4[5];
+	/* Super I/O & CMOS config */
+	u8	natp; /* 0x32 - SIO type */
+	u8	cmap; /* 0x33 - */
+	u8	cmbp; /* 0x34 - */
+	u8	lptp; /* 0x35 - LPT port */
+	u8	fdcp; /* 0x36 - Floppy Disk Controller */
+	u8	rfdv; /* 0x37 - */
+	u8	hotk; /* 0x38 - Hot Key */
+	u8	rtcf;
+	u8	util;
+	u8	acin;
+	/* Integrated Graphics Device */
+	u8	igds; /* 0x3c - IGD state */
+	u8	tlst; /* 0x3d - Display Toggle List Pointer */
+	u8	cadl; /* 0x3e - currently attached devices */
+	u8	padl; /* 0x3f - previously attached devices */
+	u16	cste; /* 0x40 - current display state */
+	u16	nste; /* 0x42 - next display state */
+	u16	sste; /* 0x44 - set display state */
+	u8	ndid; /* 0x46 - number of device ids */
+	u32	did[5]; /* 0x47 - 5b device id 1..5 */
+	u8	rsvd5[0x9];
+	/* Backlight Control */
+	u8	blcs; /* 0x64 - Backlight Control possible */
+	u8	brtl;
+	u8	odds;
+	u8	rsvd6[0x7];
+	/* Ambient Light Sensors*/
+	u8	alse; /* 0x6e - ALS enable */
+	u8	alaf;
+	u8	llow;
+	u8	lhih;
+	u8	rsvd7[0x6];
+	/* EMA */
+	u8	emae; /* 0x78 - EMA enable */
+	u16	emap;
+	u16	emal;
+	u8	rsvd8[0x5];
+	/* MEF */
+	u8	mefe; /* 0x82 - MEF enable */
+	u8	rsvd9[0x9];
+	/* TPM support */
+	u8	tpmp; /* 0x8c - TPM */
+	u8	tpme;
+	u8	rsvd10[8];
+	/* SATA */
+	u8	gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
+	u8	gtf1[7];
+	u8	gtf2[7];
+	u8	idem;
+	u8	idet;
+	u8	rsvd11[7];
+	/* IGD OpRegion (not implemented yet) */
+	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
+	u8	ibtt;
+	u8	ipat;
+	u8	itvf;
+	u8	itvm;
+	u8	ipsc;
+	u8	iblc;
+	u8	ibia;
+	u8	issc;
+	u8	i409;
+	u8	i509;
+	u8	i609;
+	u8	i709;
+	u8	idmm;
+	u8	idms;
+	u8	if1e;
+	u8	hvco;
+	u32	nxd[8];
+	u8	rsvd12[8];
+	/* Mainboard specific */
+	u8	dock; /* 0xf0 - Docking Status */
+	u8	bten;
+	u8	rsvd13[14];
+} __attribute__((packed)) global_nvs_t;
+

Copied: trunk/src/southbridge/intel/i82801gx/pci.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/pci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c)
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+	u8 reg8;
+
+	/* Enable Bus Master */
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MASTER;
+	pci_write_config16(dev, PCI_COMMAND, reg16);
+
+	/* This device has no interrupt */
+	pci_write_config8(dev, INTR, 0xff);
+
+	/* disable parity error response and SERR */
+	reg16 = pci_read_config16(dev, BCTRL);
+	reg16 &= ~(1 << 0);
+	reg16 &= ~(1 << 1);
+	pci_write_config16(dev, BCTRL, reg16);
+
+	/* Master Latency Count must be set to 0x04! */
+	reg8 = pci_read_config8(dev, SMLT);
+	reg8 &= 0x07;
+	reg8 |= (0x04 << 3);
+	pci_write_config8(dev, SMLT, reg8);
+
+	/* Will this improve throughput of bus masters? */
+	pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+	/* Clear errors in status registers */
+	reg16 = pci_read_config16(dev, PSTS);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, PSTS, reg16);
+
+	reg16 = pci_read_config16(dev, SECSTS);
+	// reg16 |= 0xf900;
+	pci_write_config16(dev, SECSTS, reg16);
+}
+
+#undef PCI_BRIDGE_UPDATE_COMMAND
+static void ich_pci_dev_enable_resources(struct device *dev)
+{
+	const struct pci_operations *ops;
+	uint16_t command;
+
+	/* Set the subsystem vendor and device id for mainboard devices */
+	ops = ops_pci(dev);
+	if (dev->on_mainboard && ops && ops->set_subsystem) {
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+			dev_path(dev),
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+		ops->set_subsystem(dev,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+	}
+
+	command = pci_read_config16(dev, PCI_COMMAND);
+	command |= dev->command;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+	/* If we write to PCI_COMMAND, on some systems
+	 * this will cause the ROM and APICs not being visible
+	 * anymore.
+	 */
+	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
+	pci_write_config16(dev, PCI_COMMAND, command);
+#else
+	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+static void ich_pci_bus_enable_resources(struct device *dev)
+{
+	uint16_t ctrl;
+	/* enable IO in command register if there is VGA card
+	 * connected with (even it does not claim IO resource)
+	 */
+	if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
+		dev->command |= PCI_COMMAND_IO;
+	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+	ctrl |= dev->link_list->bridge_ctrl;
+	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+	/* This is the reason we need our own pci_bus_enable_resources */
+	ich_pci_dev_enable_resources(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* NOTE: This is not the default position! */
+	if (!vendor || !device) {
+		pci_write_config32(dev, 0x54,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, 0x54,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= ich_pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+	.ops_pci		= &pci_ops,
+};
+
+/* Desktop */
+/* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
+static const struct pci_driver i82801g_pci __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x244e,
+};
+
+/* Mobile / Ultra Mobile */
+/* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
+static const struct pci_driver i82801gmu_pci __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2448,
+};

Copied: trunk/src/southbridge/intel/i82801gx/pcie.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/pcie.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c)
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
+
+	/* Enable Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Set Cache Line Size to 0x10 */
+	// This has no effect but the OS might expect it
+	pci_write_config8(dev, 0x0c, 0x10);
+
+	reg16 = pci_read_config16(dev, 0x3e);
+	reg16 &= ~(1 << 0); /* disable parity error response */
+	// reg16 &= ~(1 << 1); /* disable SERR */
+	reg16 |= (1 << 2); /* ISA enable */
+	pci_write_config16(dev, 0x3e, reg16);
+
+	/* Enable IO xAPIC on this PCIe port */
+	reg32 = pci_read_config32(dev, 0xd8);
+	reg32 |= (1 << 7);
+	pci_write_config32(dev, 0xd8, reg32);
+
+	/* Enable Backbone Clock Gating */
+	reg32 = pci_read_config32(dev, 0xe1);
+	reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
+	pci_write_config32(dev, 0xe1, reg32);
+
+#if CONFIG_MMCONF_SUPPORT
+	/* Set VC0 transaction class */
+	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 &= 0xffffff00;
+	reg32 |= 1;
+	pci_mmio_write_config32(dev, 0x114, reg32);
+
+	/* Mask completion timeouts */
+	reg32 = pci_mmio_read_config32(dev, 0x148);
+	reg32 |= (1 << 14);
+	pci_mmio_write_config32(dev, 0x148, reg32);
+#else
+#error "MMIO needed for ICH7 PCIe"
+#endif
+	/* Enable common clock configuration */
+	// Are there cases when we don't want that?
+	reg16 = pci_read_config16(dev, 0x50);
+	reg16 |= (1 << 6);
+	pci_write_config16(dev, 0x50, reg16);
+
+#ifdef EVEN_MORE_DEBUG
+	reg32 = pci_read_config32(dev, 0x20);
+	printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x24);
+	printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x28);
+	printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x2c);
+	printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
+#endif
+
+	/* Clear errors in status registers */
+	reg16 = pci_read_config16(dev, 0x06);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, 0x06, reg16);
+
+	reg16 = pci_read_config16(dev, 0x1e);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, 0x1e, reg16);
+}
+
+static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* NOTE: This is not the default position! */
+	if (!vendor || !device) {
+		pci_write_config32(dev, 0x94,
+				pci_read_config32(dev, 0));
+	} else {
+		pci_write_config32(dev, 0x94,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+	.ops_pci		= &pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port1 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27d0,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port2 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27d2,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port3 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27d4,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port4 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27d6,
+};
+
+/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port5 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27e0,
+};
+
+/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
+static const struct pci_driver i82801gx_pcie_port6 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27e2,
+};

Copied: trunk/src/southbridge/intel/i82801gx/reset.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/reset.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c)
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void soft_reset(void)
+{
+        outb(0x04, 0xcf9);
+}
+
+#if 0
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
+}
+#endif
+
+void hard_reset(void)
+{
+        outb(0x02, 0xcf9);
+        outb(0x06, 0xcf9);
+}

Copied: trunk/src/southbridge/intel/i82801gx/sata.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/sata.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_sata.c)
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+
+typedef struct southbridge_intel_i82801gx_config config_t;
+
+static void sata_init(struct device *dev)
+{
+	u32 reg32;
+	u16 reg16;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
+
+	if (config == NULL) {
+		printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
+		return;
+	}
+
+	/* SATA configuration */
+
+	/* Enable BARs */
+	pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+	if (config->ide_legacy_combined) {
+		printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		pci_write_config8(dev, 0x09, 0x80);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Combine IDE - SATA configuration */
+		pci_write_config8(dev, 0x90, 0x02);
+
+		/* Port 0 & 1 enable */
+		pci_write_config8(dev, 0x92, 0x0f);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94, 0x5a000180);
+	} else if(config->sata_ahci) {
+		printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
+		/* Allow both Legacy and Native mode */
+		pci_write_config8(dev, 0x09, 0x8f);
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0x0a);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Set Sata Controller Mode. */
+		pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
+
+		/* Port 0 & 1 enable */
+		pci_write_config8(dev, 0x92, 0x0f);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94, 0x1a000180);
+	} else {
+		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
+		/* Set Sata Controller Mode. No Mapping(?) */
+		pci_write_config8(dev, 0x90, 0x00);
+
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		/* Native mode capable on both primary and secondary (0xa)
+		 * or'ed with enabled (0x50) = 0xf
+		 */
+		pci_write_config8(dev, 0x09, 0x8f);
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0xff);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_SITRE | IDE_ISP_3_CLOCKS |
+				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Port 0 & 1 enable XXX */
+		pci_write_config8(dev, 0x92, 0x15);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94, 0x1a000180);
+	}
+
+	/* All configurations need this SATA initialization sequence */
+	pci_write_config8(dev, 0xa0, 0x40);
+	pci_write_config8(dev, 0xa6, 0x22);
+	pci_write_config8(dev, 0xa0, 0x78);
+	pci_write_config8(dev, 0xa6, 0x22);
+	pci_write_config8(dev, 0xa0, 0x88);
+	reg32 = pci_read_config32(dev, 0xa4);
+	reg32 &= 0xc0c0c0c0;
+	reg32 |= 0x1b1b1212;
+	pci_write_config32(dev, 0xa4, reg32);
+	pci_write_config8(dev, 0xa0, 0x8c);
+	reg32 = pci_read_config32(dev, 0xa4);
+	reg32 &= 0xc0c0ff00;
+	reg32 |= 0x121200aa;
+	pci_write_config32(dev, 0xa4, reg32);
+	pci_write_config8(dev, 0xa0, 0x00);
+
+	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+
+	/* Sata Initialization Register */
+	reg32 = pci_read_config32(dev, 0x94);
+	reg32 |= (1 << 30); // due to some bug
+	pci_write_config32(dev, 0x94, reg32);
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations sata_pci_ops = {
+	.set_subsystem    = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &sata_pci_ops,
+};
+
+/* Desktop Non-AHCI and Non-RAID Mode */
+/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c0,
+};
+
+/* Mobile Non-AHCI and Non-RAID Mode */
+/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c4,
+};
+
+
+/* NOTE: Any of the below are not properly supported yet. */
+
+/* Desktop AHCI Mode */
+/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c1,
+};
+
+/* Desktop RAID mode */
+/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c3,
+};
+
+/* Mobile AHCI Mode */
+/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
+static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c5,
+};
+
+/* ICH7M DH Raid Mode */
+/* 82801GHM (ICH7-M DH) */
+static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c6,
+};

Copied and modified: trunk/src/southbridge/intel/i82801gx/smbus.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801gx/smbus.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -27,7 +27,7 @@
 #include <device/pci_ops.h>
 #include <arch/io.h>
 #include "i82801gx.h"
-#include "i82801gx_smbus.h"
+#include "smbus.h"
 
 #define SMB_BASE 0x20
 static void smbus_init(struct device *dev)

Copied: trunk/src/southbridge/intel/i82801gx/smbus.h (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/smbus.h	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h)
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+#include "i82801gx.h"
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	byte = inb(smbus_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+

Copied: trunk/src/southbridge/intel/i82801gx/smi.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/smi.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c)
@@ -0,0 +1,368 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+#include "i82801gx.h"
+
+extern unsigned char _binary_smm_start;
+extern unsigned char _binary_smm_size;
+
+/* I945 */
+#define SMRAM		0x9d
+#define   D_OPEN	(1 << 6)
+#define   D_CLS		(1 << 5)
+#define   D_LCK		(1 << 4)
+#define   G_SMRAME	(1 << 3)
+#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = DEFAULT_PMBASE;
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+	u16 reg16;
+
+	reg16 = inw(pmbase + PM1_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outw(reg16, pmbase + PM1_STS);
+
+	return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + SMI_STS);
+
+	return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + GPE0_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + GPE0_STS);
+
+	return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "GPE0_STS: ");
+	for (i=31; i<= 16; i--) {
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+	}
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear ALT_GP_SMI_STS
+ * @return ALT_GP_SMI_STS register
+ */
+static u16 reset_alt_gp_smi_status(void)
+{
+	u16 reg16;
+
+	reg16 = inl(pmbase + ALT_GP_SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+	return reg16;
+}
+
+static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
+	for (i=15; i<= 0; i--) {
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+	u32 tcobase = pmbase + 0x60;
+	u32 reg32;
+
+	reg32 = inl(tcobase + 0x04);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
+	if (reg32 & (1 << 18))
+		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+	return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief Set the EOS bit
+ */
+static void smi_set_eos(void)
+{
+	u8 reg8;
+
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 |= EOS;
+	outb(reg8, pmbase + SMI_EN);
+}
+
+extern uint8_t smm_relocation_start, smm_relocation_end;
+
+static void smm_relocate(void)
+{
+	u32 smi_en;
+	u16 pm1_en;
+
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
+
+	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+	smi_en = inl(pmbase + SMI_EN);
+	if (smi_en & APMC_EN) {
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
+		return;
+	}
+
+	/* copy the SMM relocation code */
+	memcpy((void *)0x38000, &smm_relocation_start,
+			&smm_relocation_end - &smm_relocation_start);
+
+	printk(BIOS_DEBUG, "\n");
+	dump_smi_status(reset_smi_status());
+	dump_pm1_status(reset_pm1_status());
+	dump_gpe0_status(reset_gpe0_status());
+	dump_alt_gp_smi_status(reset_alt_gp_smi_status());
+	dump_tco_status(reset_tco_status());
+
+	/* Enable SMI generation:
+	 *  - on TCO events
+	 *  - on APMC writes (io 0xb2)
+	 *  - on writes to SLP_EN (sleep states)
+	 *  - on writes to GBL_RLS (bios commands)
+	 * No SMIs:
+	 *  - on microcontroller writes (io 0x62/0x66)
+	 */
+
+	smi_en = 0; /* reset SMI enables */
+
+#if 0
+	smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
+#endif
+	smi_en |= TCO_EN;
+	smi_en |= APMC_EN;
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+	 * periodic SMIs.
+	 */
+	smi_en |= PERIODIC_EN;
+#endif
+	smi_en |= SLP_SMI_EN;
+	smi_en |= BIOS_EN;
+
+	/* The following need to be on for SMIs to happen */
+	smi_en |= EOS | GBL_SMI_EN;
+
+	outl(smi_en, pmbase + SMI_EN);
+
+	pm1_en = 0;
+	pm1_en |= PWRBTN_EN;
+	pm1_en |= GBL_EN;
+	outw(pm1_en, pmbase + PM1_EN);
+
+	/**
+	 * There are several methods of raising a controlled SMI# via
+	 * software, among them:
+	 *  - Writes to io 0xb2 (APMC)
+	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
+	 *
+	 * Using the local apic is a bit more tricky. According to
+	 * AMD Family 11 Processor BKDG no destination shorthand must be
+	 * used.
+	 * The whole SMM initialization is quite a bit hardware specific, so
+	 * I'm not too worried about the better of the methods at the moment
+	 */
+
+	/* raise an SMI interrupt */
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
+	outb(0x00, 0xb2);
+}
+
+static void smm_install(void)
+{
+	/* enable the SMM memory window */
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+				D_OPEN | G_SMRAME | C_BASE_SEG);
+
+	/* copy the real SMM handler */
+	memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size);
+	wbinvd();
+
+	/* close the SMM memory window and enable normal SMM */
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+			G_SMRAME | C_BASE_SEG);
+}
+
+void smm_init(void)
+{
+	/* Put SMM code to 0xa0000 */
+	smm_install();
+
+	/* Put relocation code to 0x38000 and relocate SMBASE */
+	smm_relocate();
+
+	/* We're done. Make sure SMIs can happen! */
+	smi_set_eos();
+}
+
+void smm_lock(void)
+{
+	/* LOCK the SMM memory window and enable normal SMM.
+	 * After running this function, only a full reset can
+	 * make the SMM registers writable again.
+	 */
+	printk(BIOS_DEBUG, "Locking SMM.\n");
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+			D_LCK | G_SMRAME | C_BASE_SEG);
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+	/* The GDT or coreboot table is going to live here. But a long time
+	 * after we relocated the GNVS, so this is not troublesome.
+	 */
+	*(u32 *)0x500 = (u32)gnvs;
+	*(u32 *)0x504 = (u32)tcg;
+	*(u32 *)0x508 = (u32)smi1;
+	outb(0xea, 0xb2);
+}

Copied and modified: trunk/src/southbridge/intel/i82801gx/smihandler.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c)
==============================================================================
--- trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c	Tue Dec  7 20:34:01 2010	(r6148, copy source)
+++ trunk/src/southbridge/intel/i82801gx/smihandler.c	Wed Dec  8 06:42:47 2010	(r6149)
@@ -44,7 +44,7 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "i82801gx_nvs.h"
+#include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value

Copied: trunk/src/southbridge/intel/i82801gx/usb.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/usb.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c)
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+
+static void usb_init(struct device *dev)
+{
+	u32 reg32;
+	u8 reg8;
+
+	/* USB Specification says the device must be Bus Master */
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	// Erratum
+	pci_write_config8(dev, 0xca, 0x00);
+
+	// Yes. Another Erratum
+	reg8 = pci_read_config8(dev, 0xca);
+	reg8 |= (1 << 0);
+	pci_write_config8(dev, 0xca, reg8);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations usb_pci_ops = {
+	.set_subsystem    = usb_set_subsystem,
+};
+
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &usb_pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c8,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c9,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27ca,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27cb,
+};

Copied: trunk/src/southbridge/intel/i82801gx/usb_debug.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/usb_debug.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c)
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "i82801gx.h"
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
+}
+
+void i82801gx_enable_usbdebug(unsigned int port)
+{
+	u32 dbgctl;
+	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/* Force ownership of the Debug Port to the EHCI controller. */
+	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
+	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
+	dbgctl |= (1 << 30);
+	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
+}

Copied: trunk/src/southbridge/intel/i82801gx/usb_ehci.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/usb_ehci.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c)
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void usb_ehci_init(struct device *dev)
+{
+	struct resource *res;
+	u32 base;
+	u32 reg32;
+	u8 reg8;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	reg32 |= PCI_COMMAND_SERR;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	reg32 = pci_read_config32(dev, 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(dev, 0xdc, reg32);
+
+	reg32 = pci_read_config32(dev, 0xfc);
+	reg32 &= ~(3 << 2);
+	reg32 |= (2 << 2) | (1 << 29) | (1 << 17);
+	pci_write_config32(dev, 0xfc, reg32);
+
+	/* Clear any pending port changes */
+	res = find_resource(dev, 0x10);
+	base = res->base;
+	reg32 = read32(base + 0x24) | (1 << 2);
+	write32(base + 0x24, reg32);
+
+	/* workaround */
+	reg8 = pci_read_config8(dev, 0x84);
+	reg8 |= (1 << 4);
+	pci_write_config8(dev, 0x84, reg8);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+
+	access_cntl = pci_read_config8(dev, 0x80);
+
+	/* Enable writes to protected registers. */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+
+	/* Restore protection. */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static void usb_ehci_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 usb_debug;
+
+	usb_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(usb_debug);
+	if (!res) return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+}
+
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= &usb_ehci_set_subsystem,
+};
+
+static struct device_operations usb_ehci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= usb_ehci_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_ehci_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &lops_pci,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gx_usb_ehci __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27cc,
+};

Copied: trunk/src/southbridge/intel/i82801gx/watchdog.c (from r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82801gx/watchdog.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+void watchdog_off(void)
+{
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH7 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk(BIOS_DEBUG, "ICH7 watchdog disabled\n");
+}

Modified: trunk/src/southbridge/intel/i82870/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/i82870/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/i82870/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1,3 +1,3 @@
-driver-y += p64h2_ioapic.c
-driver-y += p64h2_pcibridge.c
-#driver-y += p64h2_pci_parity.c
+driver-y += ioapic.c
+driver-y += pcibridge.c
+#driver-y += pci_parity.c

Copied: trunk/src/southbridge/intel/i82870/ioapic.c (from r6148, trunk/src/southbridge/intel/i82870/p64h2_ioapic.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82870/ioapic.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82870/p64h2_ioapic.c)
@@ -0,0 +1,98 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include <assert.h>
+#include "82870.h"
+
+static int num_p64h2_ioapics = 0;
+
+static void p64h2_ioapic_enable(device_t dev)
+{
+    /* We have to enable MEM and Bus Master for IOAPIC */
+    uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+
+
+    pci_write_config16(dev, PCI_COMMAND, command);
+}
+
+/**
+ * Configure one of the IOAPICs in a P64H2.
+ *
+ * Note that a PCI bus scan will detect both IOAPICs, so this function
+ * will be called twice for each P64H2 in the system.
+ *
+ * @param dev PCI bus/device/function of P64H2 IOAPIC.
+ *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
+ */
+static void p64h2_ioapic_init(device_t dev)
+{
+    uint32_t memoryBase;
+    int apic_index, apic_id;
+
+    volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
+    volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
+
+    apic_index = num_p64h2_ioapics;
+    num_p64h2_ioapics++;
+
+    // A note on IOAPIC addresses:
+    //  0 and 1 are used for the local APICs of the dual virtual
+    //  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
+    //  6 and 7 are used for the local APICs of the dual virtual
+    //  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+    //  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
+
+    // Map APIC index into APIC ID
+    // IDs 3, 4, 5, and 8+ are available (see above note)
+
+    if (apic_index < 3)
+        apic_id = apic_index + 3;
+    else
+        apic_id = apic_index + 5;
+
+    ASSERT(apic_id < 16);       // ID is only 4 bits
+
+    // Read the MBAR address for setting up the IOAPIC in memory space
+    // NOTE: this address was assigned during enumeration of the bus
+
+    memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+    pIndexRegister  = (volatile uint32_t*) memoryBase;
+    pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+
+    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
+                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+                 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+
+    apic_id <<= 24;             // Convert ID to bitmask
+
+    *pIndexRegister = 0;        // Select APIC ID register
+    *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
+
+    if ((*pWindowRegister & (0xF<<24)) != apic_id)
+        die("p64h2_ioapic_init failed");
+
+    *pIndexRegister  = 3;   // Select Boot Configuration register
+    *pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
+
+    if (!(*pWindowRegister & 1))
+        die("p64h2_ioapic_init failed");
+}
+
+static struct device_operations ioapic_ops = {
+        .read_resources   = pci_dev_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init     = p64h2_ioapic_init,
+        .scan_bus = 0,
+        .enable   = p64h2_ioapic_enable,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+        .ops    = &ioapic_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+
+};

Copied: trunk/src/southbridge/intel/i82870/pci_parity.c (from r6148, trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82870/pci_parity.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82870/p64h2_pci_parity.c)
@@ -0,0 +1,25 @@
+#include <pci.h>
+#include <arch/io.h>
+#include <printk.h>
+#
+
+void p64h2_pci_parity_enable(void)
+{
+        uint8_t reg;
+
+        /* 2SERREN - SERR enable for PCI bridge secondary device  */
+        /* 2PEREN  - Parity error for PCI bridge secondary device  */
+        pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
+        reg |= ((1 << 1) + (1 << 0));
+        pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+
+        /* 2SERREN - SERR enable for PCI bridge secondary device  */
+        /* 2PEREN  - Parity error for PCI bridge secondary device  */
+        pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
+        reg |= ((1 << 1) + (1 << 0));
+        pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+
+        return;
+}
+
+

Copied: trunk/src/southbridge/intel/i82870/pcibridge.c (from r6148, trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/i82870/pcibridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/i82870/p64h2_pcibridge.c)
@@ -0,0 +1,39 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/mc146818rtc.h>
+#include "82870.h"
+
+static void p64h2_pcix_init(device_t dev)
+{
+	u32 dword;
+	u8 byte;
+
+	/* The purpose of changes to HCCR, ACNF, and MTT is to speed
+	 * up the PCI bus for cards having high speed transfers.
+	 */
+	dword = 0xc2040002;
+	pci_write_config32(dev, HCCR, dword);
+	dword = 0x0000c3bf;
+	pci_write_config32(dev, ACNF, dword);
+	byte = 0x08;
+	pci_write_config8(dev, MTT, byte);
+
+}
+static struct device_operations pcix_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_bus_enable_resources,
+        .init             = p64h2_pcix_init,
+        .scan_bus         = pci_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = PCI_DEVICE_ID_INTEL_82870_1F0,
+};
+

Modified: trunk/src/southbridge/intel/pxhd/Makefile.inc
==============================================================================
--- trunk/src/southbridge/intel/pxhd/Makefile.inc	Tue Dec  7 20:34:01 2010	(r6148)
+++ trunk/src/southbridge/intel/pxhd/Makefile.inc	Wed Dec  8 06:42:47 2010	(r6149)
@@ -1 +1 @@
-driver-y += pxhd_bridge.c
+driver-y += bridge.c

Copied: trunk/src/southbridge/intel/pxhd/bridge.c (from r6148, trunk/src/southbridge/intel/pxhd/pxhd_bridge.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/southbridge/intel/pxhd/bridge.c	Wed Dec  8 06:42:47 2010	(r6149, copy of r6148, trunk/src/southbridge/intel/pxhd/pxhd_bridge.c)
@@ -0,0 +1,212 @@
+/*
+ * (C) 2003-2004 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pcix.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
+#include <delay.h>
+#include "pxhd.h"
+
+static void pxhd_enable(device_t dev)
+{
+	device_t bridge;
+	uint16_t value;
+	if ((dev->path.pci.devfn & 1) == 0) {
+		/* Can we enable/disable the bridges? */
+	  	return;
+	}
+	bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
+	if (!bridge) {
+		printk(BIOS_ERR, "Cannot find bridge for ioapic: %s\n",
+			   dev_path(dev));
+		return;
+	}
+	value = pci_read_config16(bridge, 0x40);
+	value &= ~(1 << 13);
+	if (!dev->enabled) {
+		value |= (1 << 13);
+	}
+	pci_write_config16(bridge, 0x40, value);
+}
+
+
+#define NMI_OFF 0
+
+static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
+{
+	int bus_100Mhz = 0;
+
+	dev->link_list->dev = dev;
+
+	get_option(&bus_100Mhz, "pxhd_bus_speed_100");
+	if(bus_100Mhz) {
+		uint16_t word;
+
+		printk(BIOS_DEBUG, "setting pxhd bus to 100 Mhz\n");
+		/* set to pcix 100 mhz */
+		word = pci_read_config16(dev, 0x40);
+		word &= ~(3 << 14);
+		word |= (1 << 14);
+		word &= ~(3 << 9);
+		word |= (2 << 9);
+		pci_write_config16(dev, 0x40, word);
+
+		/* reset the bus to make the new frequencies effective */
+		pci_bus_reset(dev->link_list);
+	}
+	return pcix_scan_bridge(dev, max);
+}
+static void pcix_init(device_t dev)
+{
+	/* Bridge control ISA enable */
+	pci_write_config8(dev, 0x3e, 0x07);
+
+	// FIXME Please review lots of dead code here.
+#if 0
+	int nmi_option;
+	uint32_t dword;
+	uint16_t word;
+	uint8_t byte;
+
+	/* Enable memory write and invalidate ??? */
+	byte = pci_read_config8(dev, 0x04);
+        byte |= 0x10;
+        pci_write_config8(dev, 0x04, byte);
+
+	/* Set drive strength */
+	word = pci_read_config16(dev, 0xe0);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe0, word);
+	word = pci_read_config16(dev, 0xe4);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe4, word);
+
+	/* Set impedance */
+	word = pci_read_config16(dev, 0xe8);
+        word = 0x0404;
+        pci_write_config16(dev, 0xe8, word);
+
+	/* Set discard unrequested prefetch data */
+	word = pci_read_config16(dev, 0x4c);
+        word |= 1;
+        pci_write_config16(dev, 0x4c, word);
+
+	/* Set split transaction limits */
+	word = pci_read_config16(dev, 0xa8);
+        pci_write_config16(dev, 0xaa, word);
+	word = pci_read_config16(dev, 0xac);
+        pci_write_config16(dev, 0xae, word);
+
+	/* Set up error reporting, enable all */
+	/* system error enable */
+	dword = pci_read_config32(dev, 0x04);
+        dword |= (1<<8);
+        pci_write_config32(dev, 0x04, dword);
+
+	/* system and error parity enable */
+	dword = pci_read_config32(dev, 0x3c);
+        dword |= (3<<16);
+        pci_write_config32(dev, 0x3c, dword);
+
+	/* NMI enable */
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if(nmi_option) {
+		dword = pci_read_config32(dev, 0x44);
+        	dword |= (1<<0);
+        	pci_write_config32(dev, 0x44, dword);
+	}
+
+	/* Set up CRC flood enable */
+	dword = pci_read_config32(dev, 0xc0);
+	if(dword) {  /* do device A only */
+		dword = pci_read_config32(dev, 0xc4);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc4, dword);
+		dword = pci_read_config32(dev, 0xc8);
+		dword |= (1<<1);
+		pci_write_config32(dev, 0xc8, dword);
+	}
+
+	return;
+#endif
+}
+
+static struct device_operations pcix_ops  = {
+        .read_resources   = pci_bus_read_resources,
+        .set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+        .init             = pcix_init,
+        .scan_bus         = pxhd_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver pcix_driver __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = 0x0329,
+};
+
+static const struct pci_driver pcix_driver2 __pci_driver = {
+        .ops    = &pcix_ops,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = 0x032a,
+};
+
+static void ioapic_init(device_t dev)
+{
+	uint32_t value, ioapic_base;
+	/* Enable bus mastering so IOAPICs work */
+	value = pci_read_config16(dev, PCI_COMMAND);
+	value |= PCI_COMMAND_MASTER;
+	pci_write_config16(dev, PCI_COMMAND, value);
+
+	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+	setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
+}
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations intel_ops_pci = {
+	.set_subsystem = intel_set_subsystem,
+};
+
+static struct device_operations ioapic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ioapic_init,
+	.scan_bus         = 0,
+	.enable           = pxhd_enable,
+	.ops_pci          = &intel_ops_pci,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device =