[coreboot] [PATCH] Set the register based on the ROMSIZE

[Bao, Zheng]

Set the register based on the ROMSIZE.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>

Index: src/southbridge/amd/sb600/Kconfig
===================================================================
--- src/southbridge/amd/sb600/Kconfig	(revision 6159)
+++ src/southbridge/amd/sb600/Kconfig	(working copy)
@@ -23,6 +23,11 @@
 	select HAVE_USBDEBUG
 	select TINY_BOOTBLOCK
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb600/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB600
+
 config EHCI_BAR
 	hex
 	default 0xfef00000 if SOUTHBRIDGE_AMD_SB600
Index: src/southbridge/amd/sb600/bootblock.c
===================================================================
--- src/southbridge/amd/sb600/bootblock.c	(revision 6159)
+++ src/southbridge/amd/sb600/bootblock.c	(working copy)
@@ -59,7 +59,15 @@
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
 	 */
+	#if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
+	pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_1024
+	pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
+	pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
 	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	#endif
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
Index: src/southbridge/amd/sb700/Kconfig
===================================================================
--- src/southbridge/amd/sb700/Kconfig	(revision 6159)
+++ src/southbridge/amd/sb700/Kconfig	(working copy)
@@ -23,6 +23,11 @@
 	select HAVE_USBDEBUG
 	select TINY_BOOTBLOCK
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/sb700/bootblock.c"
+	depends on SOUTHBRIDGE_AMD_SB700
+
 config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	bool
 	default n
Index: src/southbridge/amd/sb700/bootblock.c
===================================================================
--- src/southbridge/amd/sb700/bootblock.c	(revision 6159)
+++ src/southbridge/amd/sb700/bootblock.c	(working copy)
@@ -28,7 +28,7 @@
  * Hardware should enable LPC ROM by pin straps. This function does not
  * handle the theoretically possible PCI ROM, FWH, or SPI ROM
configurations.
  *
- * The SB700 power-on default is to map 256K ROM space.
+ * The SB700 power-on default is to map 512K ROM space.
  *
  * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00,
  *          PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page
14.
@@ -57,8 +57,18 @@
 	 * Enable LPC ROM range start at:
 	 * 0xfff8(0000): 512KB
 	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
 	 */
+	#if CONFIG_COREBOOT_ROMSIZE_KB_512 ||
CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128
+	pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_1024
 	pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
+	pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */
+	#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
+	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	#endif
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_write_config16(dev, 0x6e, 0xffff);
 }
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