[coreboot] [PATCH] Set the register based on the ROMSIZE

[Bao, Zheng]

My opinion is,
Use the calculation, and put the truth table in the comment, if it has
nothing to do with ROMCC.

Zheng

> -----Original Message-----
> From: coreboot-bounces+zheng.bao=amd.com at coreboot.org
[mailto:coreboot-
> bounces+zheng.bao=amd.com at coreboot.org] On Behalf Of Patrick Georgi
> Sent: Friday, December 10, 2010 8:58 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE
> 
> Am 10.12.2010 13:29, schrieb Bao, Zheng:
> >> How about
> >> pci_write_config16(dev, 0x6c,
> >> 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6));
> >> instead?
> > I am not sure.
> > I think we need to leave the workload to compiler, instead of to the
> > machine running the coreboot and to the people.
> Hmm.. The main problem might be that romcc is probably not capable of
> resolving max(a,b) at compile time. Other than that, this is a rather
> primitive compile time optimization.
> 
> Other than that, it's more a style question: lots of #ifdef/#elif
> statements or a comparably opaque calculation as in the proposal?
> 
> 
> Patrick
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot