[coreboot] [PATCH] Implement DIMM loading for DDR on K8
stepan at coreboot.org
Sat Dec 11 23:11:08 CET 2010
* Rudolf Marek <r.marek at assembler.cz> [101211 22:37]:
> Attached patch implements the memory speed reductions (and 2T/1T
> clock logic) for DDR1 memory (939 sockets). The details can be found
> in BKDG chapter 184.108.40.206.
> The patch looks at certain DDR configurations (dual rank/single
> rank) and lowers the clocks to 2T or frequency as guide suggest. It
> sets the DualDIMMen bit which I believe should be set for non-dual
> channel configs.
> Dual DIMM Enable (DualDimmEn)—Bit 9. When this bit is set, the A
> copy of the memory address bus is enabled, regardless of the MC0_EN
> (Function 2, Offset 94h) value, and the B copy of the memory bus is
> disabled if 939 package with 128-bit bus is not used. This bit
> should be set if unbuffered DIMMs are used, and two DIMM sockets are
> connected to the A copy of the memory address bus, as in SODIMM or
> 939 package configurations. See “Register Differences in Revisions
> of the AMD AthlonTM 64.
> The patch does not implement support for three dimm configurations
> supported from revE.
> On the other hand it should improve greatly memory stability across
> the 939 platform.
> Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
Wow, nice finding. Assuming it's abuild tested and tested on real
Acked-by: Stefan Reinauer <stepan at coreboot.org>
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