[coreboot] [PATCH]: Disable ExtINT in ioapic.c

Bao, Zheng Zheng.Bao at amd.com
Tue Feb 2 04:25:29 CET 2010

If ExtINT is enabled, my board will hang when linux boots.
Checking if this processor honours the WP bit even in supervisor
SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
Console: colour dummy device 80x25
console [ttyS0] enabled
spurious APIC interrupt on CPU#0, should never happen.
Fast TSC calibration using PIT
Detected 2100.411 MHz processor.
Calibrating delay loop (skipped), value calculated using timer
frequency.. 4200.82 BogoMIPS
Mount-cache hash table entries: 512
Initializing cgroup subsys ns
Initializing cgroup subsys cpuacct
Initializing cgroup subsys freezer
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
mce: CPU supports 5 MCE banks
using C1E aware idle routine
Performance Events: AMD PMU driver.
... version:                0
... bit width:              48
... generic registers:      4
... value mask:             0000ffffffffffff
... max period:             00007fffffffffff
... fixed-purpose events:   0
... event mask:             000000000000000f
Checking 'hlt' instruction...
end of log.

I believe the ExtINT don't have to be enable in BIOS stage. It will be
when the kernel boots. Plus, it is the way my proprietary BIOS does.

It is tested on dbm690t.

Signed-off-by: Zheng Bao <zheng.bao at amd.com>

Index: src/arch/i386/smp/ioapic.c
--- src/arch/i386/smp/ioapic.c	(revision 5073)
+++ src/arch/i386/smp/ioapic.c	(working copy)
@@ -110,7 +110,7 @@
 	/* Enable Virtual Wire Mode */
+	low = DISABLED;
 	high = bsp_lapicid << (56 - 32);
 	io_apic_write(ioapic_base, 0x10, low);
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