[coreboot] ASUS P2B-LS support
Keith Hui
buurin at gmail.com
Mon Feb 22 05:49:15 CET 2010
Greetings.
I just tried the CVS coreboot v2 on my Asus P2B-LS motherboard. It's also
partially working as it is similar to the already partially supported P2B-F
and P3B-F, which is encouraging. There are two other boards in this series,
the P2B-L and P2B-S. They share the same circuit board with -LS and only
omit the SCSI or LAN (respectively), so I'll concentrate my effort on LS.
Let's begin with my results:
CPU = OK
L1 and L2 cache = untested
On-board SCSI = partial (3)
On-board LAN = untested
PS/2 keyboard still doesn't work.
AGP graphics card = works. Text console activated, I can see the SeaBIOS
banner and text from the SCSI BIOS. On this run the card is a ATI 3D Rage
IIc.
Serial port 1 definitely works - see attached for a log
Have not tried reboot, reset button does NOT work
I am interested in helping completing support for this board. I have a POST
card, a chip programmer, numerous types of PCI and AGP video cards and CPUs,
which should cover a lot of grounds. (1) First I want to get RAM working,
then try L2 cache, CAR if possible, keyboard/mouse, and ACPI.
I have some x86 assembly programming experience although I have not done
much assembly coding for years, I should still be able to understand
datasheets.
Before I dig right in, I want to ask what is the current state of the art
for the P2B series.
>From what I read no one actively worked on these boards for the past couple
years. Our boards currently need romcc, but has anyone tried doing
cache-as-RAM on these P6 CPUs?
Also to find out how the vendor initialized RAM, some analysis efforts were
made on it to determine how. Will this prevent me from actually submitting a
patch should I succeed? If so, can I instead post the how, and let some
others code it from what I would write here?
I was able to get a irq routing table using coreboot's own tools.
I already made change to my working copy to add code for "slot 1 CPUs"
(duplicated from slot 2), added P2B-LS to Kconfig with aforementioned,
dumped, irq routing table and related code with correct "slot 1" reference.
The log above is created after these modifications are done. I also added
microcode updates for family 6B1 and 6B4 CPUs but it appears coreboot isn't
catching it. I run a 6B4 Tualatin on my daily desktop. My test system
currently has an overclocked 6B1.
For starters, below is what I know.
On top of what a P2B carries, P2B-LS has two extra devices:
SCSI is on PCI 0:6.0, id 0x9005:0x001f
LAN is on PCI 0:7.0, id 0x8086:0x1229
In vendor BIOS the power management base port is set to 0xe400, SMBus base
port is 0xe800
I dumped the ACPI tables from vendor bios, haven't a chance to run it
through iasl yet.
I have seen code for doing ECC tests on memory (isn't a priority; I have no
ECC memory)
The RAM enable sequence is already very close to vendor's sequence.
PIIX4 General purpose input #21 and #13 are used
PIIX4 Gen Purp output #28 and #27 used
I/O writes to port 0xe1 is used in vendor BIOS for delays
Cheers
Keith
(1) My stash contains:
Two P2B-LS motherboards, one rev 1.04 "dot" with updated clock chip, one rev
1.03 with updated clock and voltage chip retrofitted by yours truly. Both
have been modified slightly (2) and have vendor BIOS 1014 beta 3.
One P3B-F motherboard
A POST card
A "Willem PCB3B" chip programmer
Pentium III 450 and 600MHz in slot 1
Pentium III 1000EB in S370
Tualatin Celeron 1000A
Tualatin Celeron 1400 in both stepping 6B1 and 6B4
A stick of 64MB EDO DIMM
Various styles of PC100 and PC133 SDRAM, a couple with 7ns time good for
140MHz, two with 6ns time claimed to be good for 150MHz
(2) http://tipperlinne.com/p2bmod These mods are done in 2003 with another
enthusiast. The objective is to have this board support every Slot 1 and
Socket 370 CPUs from Klamath to Tualatin, with the right S370 adapter. I
then went on to fit PC99 color-coded connectors on both my boards.
(3) I used SeaBIOS as payload and inserted the SCSI BIOS straight from
vendor BIOS. It gets called, seems normal, but waits indefinitely for a
keypress to enter its config screen. At this point POST card reads FE.
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lb: [0x0000000000100000, 0x0000000000124000)
Post relocation: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x00 000000000086c6
using LZMA
[ 0x00000000000ef000, 0000000000100000, 0x0000000000100000) <- 00000000fffc8bb0
dest 000ef000, end 00100000, bouncebuffer 3fa8000
Loaded segments
Jumping to boot code at fdf8b
POST: 0xfe
entry = 0x000fdf8b
lb_start = 0x00100000
lb_size = 0x00024000
adjust = 0x03ecc000
buffer = 0x03fa8000
elf_boot_notes = 0x00110080
adjusted_boot_notes = 0x03fdc080
Start bios (version pre-0.5.2-20100219_203152-htcore)
Found mainboard ASUS P2B-LS
Found CBFS header at 0xfffeffe0
Ram Size=0x03ff0000 (0x0000000000000000 high)
CPU Mhz=1330
Found 1 cpu(s) max supported 1 cpu(s)
Copying PIR from 0x03ff0400 to 0x000f8c20
SMBIOS ptr=0x000f8c00 table=0x03fefef0
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga console
Starting SeaBIOS (version pre-0.5.2-20100219_203152-htcore)
WARNING - Timeout at i8042_flush:68!
Found 1 lpt ports
Found 2 serial ports
ATA controller 0 at 1f0/3f4/2440 (irq 14 dev 21)
ATA controller 1 at 170/374/2448 (irq 15 dev 21)
ata0-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
Scan for option roms
Running option rom at c800:0003
pmm call arg1=0
pmm call arg1=0
pnp call arg1=60
pnp call arg1=61
coreboot-4.0 Sun Feb 21 21:44:01 EST 2010 starting...
SMBus controller enabled
Northbridge prior to SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00
70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
Set register 0x50 to 0x0c
Set register 0x51 to 0x80
Set register 0x52 to 0x00
Set register 0x53 to 0xff
Set register 0x57 to 0x08
Set register 0x59 to 0x00
Set register 0x5a to 0x00
Set register 0x5b to 0x00
Set register 0x5c to 0x00
Set register 0x5d to 0x00
Set register 0x5e to 0x00
Set register 0x5f to 0x00
Set register 0x60 to 0x00
Set register 0x61 to 0x00
Set register 0x62 to 0x00
Set register 0x63 to 0x00
Set register 0x64 to 0x00
Set register 0x65 to 0x00
Set register 0x66 to 0x00
Set register 0x67 to 0x00
Set register 0x68 to 0x00
Set register 0x74 to 0x00
Set register 0x75 to 0x00
Set register 0x76 to 0x00
Set register 0x77 to 0x00
Set register 0x78 to 0x00
Set register 0x79 to 0xff
Set register 0x7a to 0x00
RAM Enable 1: Apply NOP
RAM Enable 2: Precharge all
RAM Enable 3: CBR
RAM Enable 4: Mode register set
RAM Enable 5: Normal operation
RAM Enable 6: Enable refresh
Enabling refresh (DRAMC = 0x09) for DIMM 00
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 90 71 06 00 10 22 03 00 00 06 00 40 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 0c 80 00 ff 00 00 00 09 03 30 33 33 33 33 33 33
60: 08 08 08 08 08 08 08 08 00 03 00 00 00 00 00 00
70: 00 1f 02 38 01 00 10 00 23 01 10 38 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00
a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00
Copying coreboot to RAM.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0 Sun Feb 21 21:44:01 EST 2010 booting...
POST: 0x40
Calibrating delay loop...
end 8fc71eb3, start 434ea2d1
32-bit delta 1223
calibrate_tsc 32-bit result is 1223
clocks_per_usec: 1223
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PNP: 03f0.0: enabled 1, 3 resources
PNP: 03f0.1: enabled 1, 2 resources
PNP: 03f0.2: enabled 1, 2 resources
PNP: 03f0.3: enabled 1, 2 resources
PNP: 03f0.5: enabled 1, 4 resources
PNP: 03f0.7: enabled 1, 0 resources
PNP: 03f0.8: enabled 1, 0 resources
PNP: 03f0.a: enabled 1, 0 resources
PCI: 00:04.1: enabled 1, 0 resources
PCI: 00:04.2: enabled 1, 0 resources
PCI: 00:04.3: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:07.0: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PNP: 03f0.0: enabled 1, 3 resources
PNP: 03f0.1: enabled 1, 2 resources
PNP: 03f0.2: enabled 1, 2 resources
PNP: 03f0.3: enabled 1, 2 resources
PNP: 03f0.5: enabled 1, 4 resources
PNP: 03f0.7: enabled 1, 0 resources
PNP: 03f0.8: enabled 1, 0 resources
PNP: 03f0.a: enabled 1, 0 resources
PCI: 00:04.1: enabled 1, 0 resources
PCI: 00:04.2: enabled 1, 0 resources
PCI: 00:04.3: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 0 resources
PCI: 00:07.0: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:02.0, bad id 0xffffffff
PCI: 00:03.0, bad id 0xffffffff
PCI: 00:04.0 [8086/7110] bus ops
PCI: 00:04.0 [8086/7110] enabled
PCI: 00:04.1 [8086/7111] ops
PCI: 00:04.1 [8086/7111] enabled
PCI: 00:04.2 [8086/7112] ops
PCI: 00:04.2 [8086/7112] enabled
PCI: 00:04.3 [8086/7113] bus ops
PCI: 00:04.3 [8086/7113] enabled
PCI: 00:04.4, bad id 0xffffffff
PCI: 00:04.5, bad id 0xffffffff
PCI: 00:04.6, bad id 0xffffffff
PCI: 00:04.7, bad id 0xffffffff
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0 [9005/001f] enabled
PCI: 00:07.0 [8086/1229] enabled
PCI: 00:08.0, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
PCI: 00:11.0, bad id 0xffffffff
PCI: 00:12.0, bad id 0xffffffff
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0, bad id 0xffffffff
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0, bad id 0xffffffff
POST: 0x25
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
POST: 0x24
malloc Enter, size 1092, free_mem_ptr 00120000
malloc 00120000
PCI: 01:00.0 [1002/475a] enabled
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:04.0
malloc Enter, size 1092, free_mem_ptr 00120444
malloc 00120444
PNP: 03f0.0 enabled
PNP: 03f0.1 enabled
PNP: 03f0.2 enabled
PNP: 03f0.3 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PNP: 03f0.a enabled
PNP: 03f0.6 enabled
scan_static_bus for PCI: 00:04.0 done
scan_static_bus for PCI: 00:04.3
scan_static_bus for PCI: 00:04.3 done
PCI: pci_scan_bus returning with max=001
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 01:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PNP: 03f0.8 missing read_resources
PCI: 00:04.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
PCI: 00:01.0 links 1 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0 links 0 child on link 0 NULL
PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 1200 index 10
PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0
PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2
PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 03f0.0 links 0 child on link 0 NULL
PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 03f0.1 links 0 child on link 0 NULL
PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 03f0.2 links 0 child on link 0 NULL
PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.3 links 0 child on link 0 NULL
PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.5 links 0 child on link 0 NULL
PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 03f0.7 links 0 child on link 0 NULL
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.8 links 0 child on link 0 NULL
PNP: 03f0.a links 0 child on link 0 NULL
PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.6 links 0 child on link 0 NULL
PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PCI: 00:04.1 links 0 child on link 0 NULL
PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:04.2 links 0 child on link 0 NULL
PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:04.3 links 0 child on link 0 NULL
PCI: 00:06.0 links 0 child on link 0 NULL
PCI: 00:06.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 00:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 14
PCI: 00:06.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:07.0 links 0 child on link 0 NULL
PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 1200 index 10
PCI: 00:07.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
PCI: 00:07.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 2200 index 30
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:06.0 10 * [0x1000 - 0x10ff] io
PCI: 00:04.2 20 * [0x1400 - 0x141f] io
PCI: 00:07.0 14 * [0x1420 - 0x143f] io
PCI: 00:04.1 20 * [0x1440 - 0x144f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1450 size: 1450 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0xffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 1000000 size: 1000000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem
PCI: 01:00.0 18 * [0x20000 - 0x20fff] mem
PCI: 00:01.0 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 24 * [0x10000000 - 0x10ffffff] prefmem
PCI: 00:01.0 20 * [0x11000000 - 0x110fffff] mem
PCI: 00:07.0 18 * [0x11100000 - 0x111fffff] mem
PCI: 00:07.0 30 * [0x11200000 - 0x112fffff] mem
PCI: 00:06.0 30 * [0x11300000 - 0x1131ffff] mem
PCI: 00:06.0 14 * [0x11320000 - 0x11320fff] mem
PCI: 00:07.0 10 * [0x11321000 - 0x11321fff] prefmem
PCI_DOMAIN: 0000 compute_resources_mem: base: 11322000 size: 11322000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:04.0
constrain_resources: PNP: 03f0.0
constrain_resources: PNP: 03f0.1
constrain_resources: PNP: 03f0.2
constrain_resources: PNP: 03f0.3
constrain_resources: PNP: 03f0.5
constrain_resources: PNP: 03f0.7
constrain_resources: PNP: 03f0.8
constrain_resources: PNP: 03f0.a
constrain_resources: PNP: 03f0.6
constrain_resources: PCI: 00:04.1
constrain_resources: PCI: 00:04.2
constrain_resources: PCI: 00:04.3
constrain_resources: PCI: 00:06.0
constrain_resources: PCI: 00:07.0
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1450 align:12 gran:0 limit:ffff
Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io
Assigned: PCI: 00:06.0 10 * [0x2000 - 0x20ff] io
Assigned: PCI: 00:04.2 20 * [0x2400 - 0x241f] io
Assigned: PCI: 00:07.0 14 * [0x2420 - 0x243f] io
Assigned: PCI: 00:04.1 20 * [0x2440 - 0x244f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2450 size: 1450 align: 12 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:00.0 14 * [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:11322000 align:28 gran:0 limit:febfffff
Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:01.0 24 * [0xf0000000 - 0xf0ffffff] prefmem
Assigned: PCI: 00:01.0 20 * [0xf1000000 - 0xf10fffff] mem
Assigned: PCI: 00:07.0 18 * [0xf1100000 - 0xf11fffff] mem
Assigned: PCI: 00:07.0 30 * [0xf1200000 - 0xf12fffff] mem
Assigned: PCI: 00:06.0 30 * [0xf1300000 - 0xf131ffff] mem
Assigned: PCI: 00:06.0 14 * [0xf1320000 - 0xf1320fff] mem
Assigned: PCI: 00:07.0 10 * [0xf1321000 - 0xf1321fff] prefmem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f1322000 size: 11322000 align: 28 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:f0000000 size:1000000 align:24 gran:20 limit:febfffff
Assigned: PCI: 01:00.0 10 * [0xf0000000 - 0xf0ffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: f1000000 size: 1000000 align: 24 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:f1000000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf101ffff] mem
Assigned: PCI: 01:00.0 18 * [0xf1020000 - 0xf1020fff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: f1021000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 64 MB
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f1000000 - 0x00f10fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 prefmem
PCI: 01:00.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x00f1020000 - 0x00f1020fff] size 0x00001000 gran 0x0c mem
PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f101ffff] size 0x00020000 gran 0x11 romem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned
PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned
ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned
ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned
ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x0000002440 - 0x000000244f] size 0x00000010 gran 0x04 io
PCI: 00:04.2 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io
PCI: 00:06.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:06.0 14 <- [0x00f1320000 - 0x00f1320fff] size 0x00001000 gran 0x0c mem64
PCI: 00:06.0 30 <- [0x00f1300000 - 0x00f131ffff] size 0x00020000 gran 0x11 romem
PCI: 00:07.0 10 <- [0x00f1321000 - 0x00f1321fff] size 0x00001000 gran 0x0c prefmem
PCI: 00:07.0 14 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io
PCI: 00:07.0 18 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 mem
PCI: 00:07.0 30 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 romem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 1000 size 1450 align 12 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base e0000000 size 11322000 align 28 gran 0 limit febfffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
PCI_DOMAIN: 0000 resource base c0000 size 3f40000 align 0 gran 0 limit 0 flags e0004200 index b
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10
PCI: 00:01.0 links 1 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:01.0 resource base f0000000 size 1000000 align 24 gran 20 limit febfffff flags 60081202 index 24
PCI: 00:01.0 resource base f1000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
PCI: 01:00.0 links 0 child on link 0 NULL
PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit febfffff flags 60001200 index 10
PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
PCI: 01:00.0 resource base f1020000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 18
PCI: 01:00.0 resource base f1000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0
PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2
PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 03f0.0 links 0 child on link 0 NULL
PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
PNP: 03f0.1 links 0 child on link 0 NULL
PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 03f0.2 links 0 child on link 0 NULL
PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.3 links 0 child on link 0 NULL
PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.5 links 0 child on link 0 NULL
PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 03f0.7 links 0 child on link 0 NULL
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.8 links 0 child on link 0 NULL
PNP: 03f0.a links 0 child on link 0 NULL
PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 03f0.6 links 0 child on link 0 NULL
PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PCI: 00:04.1 links 0 child on link 0 NULL
PCI: 00:04.1 resource base 2440 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 00:04.2 links 0 child on link 0 NULL
PCI: 00:04.2 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
PCI: 00:04.3 links 0 child on link 0 NULL
PCI: 00:06.0 links 0 child on link 0 NULL
PCI: 00:06.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
PCI: 00:06.0 resource base f1320000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 14
PCI: 00:06.0 resource base f1300000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
PCI: 00:07.0 links 0 child on link 0 NULL
PCI: 00:07.0 resource base f1321000 size 1000 align 12 gran 12 limit febfffff flags 60001200 index 10
PCI: 00:07.0 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000100 index 14
PCI: 00:07.0 resource base f1100000 size 100000 align 20 gran 20 limit febfffff flags 60000200 index 18
PCI: 00:07.0 resource base f1200000 size 100000 align 20 gran 20 limit febfffff flags 60002200 index 30
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 008b
PCI: 00:01.0 cmd <- 07
PCI: 01:00.0 cmd <- 83
PCI: 00:04.0 cmd <- 07
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 cmd <- 01
PCI: 00:06.0 subsystem <- 00/00
PCI: 00:06.0 cmd <- 03
PCI: 00:07.0 subsystem <- 00/00
PCI: 00:07.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Intel device 6b1
CPU: family 06, model 0b, stepping 01
POST: 0x60
Enabling cache
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base: 0MB, range: 64MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
POST: 0x6a
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
microcode_info: sig = 0x000006b1 pf=0x00000010 rev = 0x00000000
microcode updated to revision: 00000000 from revision 00000000
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
CPU #0 initialized
PCI: 00:00.0 init
Northbridge Init
PCI: 00:04.0 init
RTC Init
PNP: 03f0.0 init
PNP: 03f0.1 init
PNP: 03f0.2 init
PNP: 03f0.3 init
PNP: 03f0.5 init
Keyboard init...
Couldn't cleanup the keyboard controller buffers
Status (0x64): 0xff, Buffer (0x60): 0xff
PNP: 03f0.7 init
PNP: 03f0.a init
PCI: 00:04.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:04.2 init
PCI: 00:06.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fffc0000 + 38 + 8af4 + align -> fffc8b40
Check fallback/payload
CBFS: follow chain: fffc8b40 + 38 + 86fe + align -> fffd1280
Check pci9005,001f.rom
CBFS: File pci9005,001f.rom is of type 63000000 instead oftype 30
On card, rom address for PCI: 00:06.0 = f1300000
PCI Expansion ROM, signature 0xffff, INIT size 0x1fe00, data ptr 0xffff
Incorrect Expansion ROM Header Signature ffff
PCI: 00:07.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fffc0000 + 38 + 8af4 + align -> fffc8b40
Check fallback/payload
CBFS: follow chain: fffc8b40 + 38 + 86fe + align -> fffd1280
Check pci9005,001f.rom
CBFS: follow chain: fffd1280 + 38 + b000 + align -> fffdc2c0
Check
CBFS: follow chain: fffdc2c0 + 28 + 13cf8 + align -> ffff0000
CBFS: Could not find file pci8086,1229.rom
On card, rom address for PCI: 00:07.0 = f1200000
PCI Expansion ROM, signature 0x0202, INIT size 0x0400, data ptr 0x0202
Incorrect Expansion ROM Header Signature 0202
PCI: 01:00.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fffc0000 + 38 + 8af4 + align -> fffc8b40
Check fallback/payload
CBFS: follow chain: fffc8b40 + 38 + 86fe + align -> fffd1280
Check pci9005,001f.rom
CBFS: follow chain: fffd1280 + 38 + b000 + align -> fffdc2c0
Check
CBFS: follow chain: fffdc2c0 + 28 + 13cf8 + align -> ffff0000
CBFS: Could not find file pci1002,475a.rom
On card, rom address for PCI: 01:00.0 = f1000000
PCI Expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x0158
PCI ROM Image, Vendor 1002, Device 475a,
PCI ROM Image, Class Code 030000, Code Type 00
copying VGA ROM Image from f1000000 to 0xc0000, 0x8000 bytes
Real mode stub @00000600: 422 bytes
Calling Option ROM...
oprom: INT# 0x1a
oprom: eax: 0000b109 ebx: 00000100 ecx: 00000100 edx: 00120000
oprom: ebp: 0011ff40 esp: 00000fd6 edi: 0000002e esi: 00001900
oprom: ip: 0184 cs: c000 flags: 00000046
0xb109: bus 1 devfn 0x0 reg 0x2e val 0x84
oprom: INT# 0x1a
oprom: eax: 0000b109 ebx: 00000100 ecx: 00000084 edx: 00120000
oprom: ebp: 0011ff40 esp: 00000fd6 edi: 00000014 esi: 00001900
oprom: ip: 01e6 cs: c000 flags: 00000046
0xb109: bus 1 devfn 0x0 reg 0x14 val 0x1001
oprom: INT# 0x1a
oprom: eax: 0000b108 ebx: 00000100 ecx: 0000efff edx: 001210a0
oprom: ebp: 0011ff40 esp: 00000fd6 edi: 00000004 esi: 00001900
oprom: ip: 0219 cs: c000 flags: 00000006
0xb108: bus 1 devfn 0x0 reg 0x4 val 0x83
oprom: INT# 0x1a
oprom: eax: 0000b10b ebx: 00000100 ecx: 00000087 edx: 001210a0
oprom: ebp: 0011ff40 esp: 00000fd6 edi: 00000004 esi: 00001900
oprom: ip: 0221 cs: c000 flags: 00000086
0xb10b: bus 1 devfn 0x0 reg 0x4 val 0x87
oprom: INT# 0x1a
oprom: eax: 0000b10a ebx: 00000100 ecx: 00000087 edx: 001210a0
oprom: ebp: 0011ff40 esp: 00000fd6 edi: 00000018 esi: 00001900
oprom: ip: 0229 cs: c000 flags: 00000086
0xb10a: bus 1 devfn 0x0 reg 0x18 val 0xf1020000
oprom: INT# 0x42
oprom: eax: 00000007 ebx: 00001004 ecx: 00000000 edx: 001203c2
oprom: ebp: 00110000 esp: 00000fda edi: 0000ffff esi: 00000000
oprom: ip: 3e3d cs: c000 flags: 00000006
Unsupported software interrupt #0x42
error!
... Option ROM returned.
PNP: 03f0.6 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 1 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 00:04.0: enabled 1, 3 resources
PNP: 03f0.0: enabled 1, 3 resources
PNP: 03f0.1: enabled 1, 3 resources
PNP: 03f0.2: enabled 1, 2 resources
PNP: 03f0.3: enabled 1, 2 resources
PNP: 03f0.5: enabled 1, 4 resources
PNP: 03f0.7: enabled 1, 3 resources
PNP: 03f0.8: enabled 1, 0 resources
PNP: 03f0.a: enabled 1, 1 resources
PCI: 00:04.1: enabled 1, 1 resources
PCI: 00:04.2: enabled 1, 1 resources
PCI: 00:04.3: enabled 1, 0 resources
PCI: 00:06.0: enabled 1, 3 resources
PCI: 00:07.0: enabled 1, 4 resources
PCI: 01:00.0: enabled 1, 4 resources
PNP: 03f0.6: enabled 1, 2 resources
POST: 0x89
Initializing CBMEM area to 0x3ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 03ff0200...ok
High Tables Base is 3ff0000.
POST: 0x9a
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x03ff0400... done.
PIRQ table: 160 bytes.
POST: 0x9d
Multiboot Information structure has been written.
POST: 0x9d
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum e7df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x03ff1400
rom_table_end = 0x03ff1400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x03ff1400 to 0x04000000
Adding high table area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-0000000003feffff: RAM
3. 0000000003ff0000-0000000003ffffff: CONFIGURATION TABLES
Wrote coreboot table at: 03ff1400 - 03ff158c checksum 90bd
coreboot table: 396 bytes.
POST: 0x9e
0. FREE SPACE 03ff3400 0000cc00
1. GDT 03ff0200 00000200
2. IRQ TABLE 03ff0400 00001000
3. COREBOOT 03ff1400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fffc0000 + 38 + 8af4 + align -> fffc8b40
Check fallback/payload
Got a payload
Loading segment from rom address 0xfffc8b78
data (compression=1)
malloc Enter, size 36, free_mem_ptr 00120888
malloc 00120888
New segment dstaddr 0xef000 memsize 0x11000 srcaddr 0xfffc8bb0 filesize 0x86c6
(cleaned up) New segment addr 0xef000 size 0x11000 offset 0xfffc8bb0 filesize 0x86c6
Loading segment from rom address 0xfffc8b94
Entry Point 0x000fdf8b
Loading Segment: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x00000000000086c6
lb: [0x0000000000100000, 0x0000000000124000)
Post relocation: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x00000000000086c6
using LZMA
[ 0x00000000000ef000, 0000000000100000, 0x0000000000100000) <- 00000000fffc8bb0
dest 000ef000, end 00100000, bouncebuffer 3fa8000
Loaded segments
Jumping to boot code at fdf8b
POST: 0xfe
entry = 0x000fdf8b
lb_start = 0x00100000
lb_size = 0x00024000
adjust = 0x03ecc000
buffer = 0x03fa8000
elf_boot_notes = 0x00110080
adjusted_boot_notes = 0x03fdc080
Start bios (version pre-0.5.2-20100219_203152-htcore)
Found mainboard ASUS P2B-LS
Found CBFS header at 0xfffeffe0
Ram Size=0x03ff0000 (0x0000000000000000 high)
CPU Mhz=1330
Found 1 cpu(s) max supported 1 cpu(s)
Copying PIR from 0x03ff0400 to 0x000f8c20
SMBIOS ptr=0x000f8c00 table=0x03fefef0
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga console
Starting SeaBIOS (version pre-0.5.2-20100219_203152-htcore)
WARNING - Timeout at i8042_flush:68!
Found 1 lpt ports
Found 2 serial ports
ATA controller 0 at 1f0/3f4/2440 (irq 14 dev 21)
ATA controller 1 at 170/374/2448 (irq 15 dev 21)
ata0-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
Scan for option roms
Running option rom at c800:0003
pmm call arg1=0
pmm call arg1=0
pnp call arg1=60
pnp call arg1=61
More information about the coreboot
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