[coreboot] Future coreboot phases?

[Rudolf Marek]

> How is S3 resume handled?

I describe the AMD64 port. There is a function which you can get sleepstate from 
a chipset. If you are resuming, most of the boot code flow is same. However 
there are following expecptions:

1) the coreboot RAM stage area is backuped to a cbmem store. It is done because 
we don't have relocable ram stage.

2) The memory is taken out of the selfrefresh instead of "init command", so most 
of the memory setup is same. The DQS values are stored in chipset S3 "NVRAM" 
during first boot, and used later when resume to fill them in. It could be done 
via simple backup of all mem cntrl regs but it is not done so.

3) The boot continues normally until the build of the memory tables. No tables 
are build but the wakeup vector is taken from ACPI tables and with a realmode 
trampoline (currently partly overwriting first 1K of mem) the CPU is taken to 
the realmode OS wakup entrypoint.

Thats it. Maybe it is more clear now.

Rudolf