From knuku at gap.upv.es Thu Jul 1 10:25:57 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Thu, 01 Jul 2010 10:25:57 +0200 Subject: [coreboot] HTX (FPGA) device needs more time for initialization but HOW? Message-ID: <4C2C5115.9050903@gap.upv.es> Hi, my version of coreboot (on Supermicro H8QME-2+) is working just fabulous but now I have a little issue. I have a HTX board with a FPGA on it which needs to boot with coreboot on the motherboard. The problem is that it fails to boot most of the time because it doesn't had time to initialize itself properly. I know that because at HT non coherent device initialization it marks bit 1(InitComplete) in the link type register of the device as 0. What I tried to do is to hard_reset() every time it fails but with no luck. I did that because after a power cycle the card seems to have enough time to initialize and the boot process completes successfully. I read in the maillist (http://www.mail-archive.com/coreboot at coreboot.org/msg01089.html) of a similar problem but with no solution published at the end :(. So is there any way how I could delay the whole initialization process to give the card more time? Thanks in advanced, Knut Kujat. From mylesgw at gmail.com Thu Jul 1 16:41:55 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 1 Jul 2010 08:41:55 -0600 Subject: [coreboot] HTX (FPGA) device needs more time for initialization butHOW? In-Reply-To: <4C2C5115.9050903@gap.upv.es> References: <4C2C5115.9050903@gap.upv.es> Message-ID: <2655AF51E6B94FD098BC251FC0E802F0@chimp> > my version of coreboot (on Supermicro H8QME-2+) is working just fabulous > but now I have a little issue. I have a HTX board with a FPGA on it > which needs to boot with coreboot on the motherboard. The problem is > that it fails to boot most of the time because it doesn't had time to > initialize itself properly. I know that because at HT non coherent > device initialization it marks bit 1(InitComplete) in the link type > register of the device as 0. What I tried to do is to hard_reset() every > time it fails but with no luck. I did that because after a power cycle > the card seems to have enough time to initialize and the boot process > completes successfully. Doing a hard reset works for me here. I'm surprised that power cycling the machine works. That doesn't work for me. I always figured that it was because on a warm hard reset the power and clocks were already stable. > So is there any way how I could delay the whole initialization process > to give the card more time? By the time software gets control, it's too late. The HT links are already initialized. >From your FPGA, you should be able to delay it if your clock is stable and you can have CAD driven high and CTL driven low. Initialization shouldn't start until you raise CTL. Thanks, Myles From knuku at gap.upv.es Thu Jul 1 16:59:54 2010 From: knuku at gap.upv.es (Knut Kujat) Date: Thu, 01 Jul 2010 16:59:54 +0200 Subject: [coreboot] HTX (FPGA) device needs more time for initialization butHOW? In-Reply-To: <2655AF51E6B94FD098BC251FC0E802F0@chimp> References: <4C2C5115.9050903@gap.upv.es> <2655AF51E6B94FD098BC251FC0E802F0@chimp> Message-ID: <4C2CAD6A.6040506@gap.upv.es> Myles Watson escribi?: >> my version of coreboot (on Supermicro H8QME-2+) is working just fabulous >> but now I have a little issue. I have a HTX board with a FPGA on it >> which needs to boot with coreboot on the motherboard. The problem is >> that it fails to boot most of the time because it doesn't had time to >> initialize itself properly. I know that because at HT non coherent >> device initialization it marks bit 1(InitComplete) in the link type >> register of the device as 0. What I tried to do is to hard_reset() every >> time it fails but with no luck. I did that because after a power cycle >> the card seems to have enough time to initialize and the boot process >> completes successfully. >> > > Doing a hard reset works for me here. I'm surprised that power cycling the > machine works. That doesn't work for me. I always figured that it was > because on a warm hard reset the power and clocks were already stable. > By power cycling I mean one of those where you plug the cable in again and the board becomes alive immediately without any need of pushing the power button. After cycling you need to push the button it fails also. > >> So is there any way how I could delay the whole initialization process >> to give the card more time? >> > > By the time software gets control, it's too late. The HT links are already > initialized. > That was kind of I thought it would work without being completely sure. But now my question is if it is possible to reset the initialization by software and try to delay it then? > From your FPGA, you should be able to delay it if your clock is stable and > you can have CAD driven high and CTL driven low. Initialization shouldn't > start until you raise CTL. > Don't know much about that FPGA because I'm not working on/with it. But the main idea is to modify coreboot to not to modify the FPGA. > Thanks, > Myles > > > > Kind regards, Knut Kujat. From mylesgw at gmail.com Thu Jul 1 17:13:30 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 1 Jul 2010 09:13:30 -0600 Subject: [coreboot] HTX (FPGA) device needs more time for initialization butHOW? In-Reply-To: <4C2CAD6A.6040506@gap.upv.es> References: <4C2C5115.9050903@gap.upv.es> <2655AF51E6B94FD098BC251FC0E802F0@chimp> <4C2CAD6A.6040506@gap.upv.es> Message-ID: > -----Original Message----- > From: Knut Kujat [mailto:knuku at gap.upv.es] > Sent: Thursday, July 01, 2010 9:00 AM > To: Myles Watson > Cc: 'coreboot' > Subject: Re: [coreboot] HTX (FPGA) device needs more time for > initialization butHOW? > > Myles Watson escribi?: > >> my version of coreboot (on Supermicro H8QME-2+) is working just > fabulous > >> but now I have a little issue. I have a HTX board with a FPGA on it > >> which needs to boot with coreboot on the motherboard. The problem is > >> that it fails to boot most of the time because it doesn't had time to > >> initialize itself properly. I know that because at HT non coherent > >> device initialization it marks bit 1(InitComplete) in the link type > >> register of the device as 0. What I tried to do is to hard_reset() > every > >> time it fails but with no luck. I did that because after a power cycle > >> the card seems to have enough time to initialize and the boot process > >> completes successfully. > >> > > > > Doing a hard reset works for me here. I'm surprised that power cycling > the > > machine works. That doesn't work for me. I always figured that it was > > because on a warm hard reset the power and clocks were already stable. > > > By power cycling I mean one of those where you plug the cable in again > and the board becomes alive immediately without any need of pushing the > power button. After cycling you need to push the button it fails also. That's surprising. Maybe it has something to do with the configuration of the power button? > Don't know much about that FPGA because I'm not working on/with it. But > the main idea is to modify coreboot to not to modify the FPGA. Even if you don't modify it, knowing why it's failing from the FPGA's perspective might be helpful. Good luck, Myles From grantwu00 at yahoo.com.tw Fri Jul 2 00:17:22 2010 From: grantwu00 at yahoo.com.tw (=?big5?B?R3JhbnQgp2Sp+q+n?=) Date: Fri, 2 Jul 2010 06:17:22 +0800 (CST) Subject: [coreboot] Coreboot RS780 problem Message-ID: <876847.45785.qm@web72807.mail.tp2.yahoo.com> Hi all, Coreboot just added support for RS780 chipset. My mainboard is AM2+RS780+SB700. In Coreboot, I use "make menuconfig" command to choose motherboard. I can only choose "AMD + Tilapia" project. However, it is AM3+RS780+SB700. So how can I replace the cpu code to AM2 in coreboot? BR Grant -------------- next part -------------- An HTML attachment was scrubbed... URL: From marcj303 at gmail.com Fri Jul 2 00:50:56 2010 From: marcj303 at gmail.com (Marc Jones) Date: Thu, 1 Jul 2010 16:50:56 -0600 Subject: [coreboot] Coreboot RS780 problem In-Reply-To: <876847.45785.qm@web72807.mail.tp2.yahoo.com> References: <876847.45785.qm@web72807.mail.tp2.yahoo.com> Message-ID: 2010/7/1 Grant ??? : > Hi all, > > Coreboot just added support for RS780 chipset. > > My mainboard is AM2+RS780+SB700. > In Coreboot, I use "make menuconfig" command to choose motherboard. > I can only choose "AMD + Tilapia" project. > However, it is AM3+RS780+SB700. > > So how can I replace the cpu code to AM2 in coreboot? Hi Grant, Look at the AMD Mahogany_fam10 platform too. You can change the CPU socket in the mainboard Kconfig. Marc -- http://se-eng.com From Maximilian.Thuermer at ziti.uni-heidelberg.de Fri Jul 2 10:25:13 2010 From: Maximilian.Thuermer at ziti.uni-heidelberg.de (Maximilian Thuermer) Date: Fri, 02 Jul 2010 10:25:13 +0200 Subject: [coreboot] HTX (FPGA) device needs more time for, initialization but HOW? Message-ID: <4C2DA269.5070904@ziti.uni-heidelberg.de> Hi Knut, this is a problem I ran into multiple times since I've been working with FPGA based HTX boards now and it appears to me there is - as always - no general way to fix that issue. It all depends greatly on the mobo setup. Hard reset isnt always behaving as you would expect. An HT link reinitialization only takes place if either pwrkok goes down (the cold reset case), or ldtstop forces the link into idle state (which most Opterons out there dont seem to support yet). Additionally, almost every mainboard vendor ignores the fact that powerok and reset_n on every HT link is defined as bidirectional. I am working with a Tyan S2912 with fam10 cpus, and its MCP55 seems to control abovementioned signals unidirectionally. If this should be the case with your board, too, there are two possible ways to fix your issue. If you have the southbridge documentation and it truly controls all HT sideband signals, implement your own, real hard reset. Another thing that works on some boards (e.g. on Tyan) is pressing and holding the reset button before pressing the power button and letting it go sometimes afterwards. This holds the southbridge in init state and leaves your card all the time you need to have it program itself. Good luck and best regards, Maximilian Thuermer From sc at drccomputer.com Fri Jul 2 23:30:19 2010 From: sc at drccomputer.com (Steve Casselman) Date: Fri, 2 Jul 2010 14:30:19 -0700 (PDT) Subject: [coreboot] HTX (FPGA) device needs more time for, initialization but HOW? In-Reply-To: <4C2DA269.5070904@ziti.uni-heidelberg.de> References: <4C2DA269.5070904@ziti.uni-heidelberg.de> Message-ID: <393705.23546.qm@web504.biz.mail.mud.yahoo.com> All Opterons support ldtstop (disconnect protocol). According to the spec in x86 systems only the southbridge drives ldtstop. Steve ________________________________ From: Maximilian Thuermer To: coreboot at coreboot.org; knuku at gap.upv.es Sent: Fri, July 2, 2010 1:25:13 AM Subject: [coreboot] HTX (FPGA) device needs more time for, initialization but HOW? Hi Knut, this is a problem I ran into multiple times since I've been working with FPGA based HTX boards now and it appears to me there is - as always - no general way to fix that issue. It all depends greatly on the mobo setup. Hard reset isnt always behaving as you would expect. An HT link reinitialization only takes place if either pwrkok goes down (the cold reset case), or ldtstop forces the link into idle state (which most Opterons out there dont seem to support yet). Additionally, almost every mainboard vendor ignores the fact that powerok and reset_n on every HT link is defined as bidirectional. I am working with a Tyan S2912 with fam10 cpus, and its MCP55 seems to control abovementioned signals unidirectionally. If this should be the case with your board, too, there are two possible ways to fix your issue. If you have the southbridge documentation and it truly controls all HT sideband signals, implement your own, real hard reset. Another thing that works on some boards (e.g. on Tyan) is pressing and holding the reset button before pressing the power button and letting it go sometimes afterwards. This holds the southbridge in init state and leaves your card all the time you need to have it program itself. Good luck and best regards, Maximilian Thuermer -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From qjmiao at gmail.com Sat Jul 3 07:30:38 2010 From: qjmiao at gmail.com (QJ Miao) Date: Sat, 3 Jul 2010 13:30:38 +0800 Subject: [coreboot] About undocumented i945gm+ich7m registers Message-ID: Hi, When reading coreboot i945gm+ich7m code, I found many configured registers are not existed in intel published datasheets. Where I can get these register definitions? and these registers must be initialized? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Sat Jul 3 10:47:18 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 03 Jul 2010 10:47:18 +0200 Subject: [coreboot] About undocumented i945gm+ich7m registers In-Reply-To: References: Message-ID: <4C2EF916.9060605@gmx.net> Hi, On 03.07.2010 07:30, QJ Miao wrote: > When reading coreboot i945gm+ich7m code, I found many configured registers > are not existed in intel published datasheets. > > Where I can get these register definitions? > You have to get a restricted secret NDA from Intel. Maybe you also need to reverse engineer some code. > and these registers must be initialized? > I think so, yes. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Mon Jul 5 16:00:01 2010 From: svn at coreboot.org (coreboot tracker) Date: Mon, 05 Jul 2010 16:00:01 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From dcelta at gmail.com Mon Jul 5 23:02:16 2010 From: dcelta at gmail.com (Daniel J. Celta) Date: Mon, 5 Jul 2010 16:02:16 -0500 Subject: [coreboot] H8DME-2 Message-ID: Has anyone updated this Supermicro server Board BIOS for the H8DME-2...... I have installed FC10, (i was able to complete this installation by turning of the RAID configuration in the BIOS), and now I am having trouble when trying to upgrade the Operating system to FC13. I suspect, if I update the BIOS, I currently have the version of the BIOS that came pre-installed with the server, I may be able to upgrade to FC13. One thing I like to mention, when running "make menuconfig" I was not sure of the ROM Chip size, and used the largest available setting 4MB. - How can I check the proper setting for this parameter???? So now, I have created the coreboot.rom, and think I am ready to run "flashrom"....... - Is there anything else I need to check before I pull the trigger??? - Has anyone had any problems I should be aware of???? Thanks Daniel -------------- next part -------------- An HTML attachment was scrubbed... URL: From gregg.drwho8 at gmail.com Tue Jul 6 00:51:45 2010 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Mon, 5 Jul 2010 18:51:45 -0400 Subject: [coreboot] H8DME-2 In-Reply-To: References: Message-ID: On Mon, Jul 5, 2010 at 5:02 PM, Daniel J. Celta wrote: > Has anyone updated this Supermicro server Board BIOS for the H8DME-2...... > > I have installed FC10, (i was able to complete this installation by turning > of the RAID configuration in the BIOS), and now I am having trouble when > trying to upgrade the Operating system to FC13. > > > I suspect, if I update the BIOS, I currently have the version of the BIOS > that came pre-installed with the server, I may be able to upgrade to FC13. > > One thing I like to mention, when running "make menuconfig" I was not sure > of the ROM Chip size, and used the largest available setting 4MB. > > - How can I check the proper setting for this parameter???? > > > > So now, I have created the coreboot.rom, and think I am ready to run > "flashrom"....... > > - Is there anything else I need to check before I pull the trigger??? > > - Has anyone had any problems I should be aware of???? > > > Thanks > > Daniel > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hello! I confess I'm not familiar with that board. Why don't you post the exact same things that the Wiki asks for? That way the rest of us, even those of us who do know it, can advise you? I do however believe you're on the right path. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From anders at jenbo.dk Tue Jul 6 02:12:00 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Tue, 06 Jul 2010 02:12:00 +0200 Subject: [coreboot] =?utf-8?q?Re__H8DME-2?= Message-ID: Run flashrom with no parameters and it should tell you what Rom chip you have. Before you pull the trigger you should make sure that you have a way to recover the original BIOS (with out the use of the computer you are doing this to). Mvh Anders ----- Reply message ----- Fra: "Daniel J. Celta" Dato: man., jul. 5, 2010 23:02 Emne: [coreboot] H8DME-2 Til: -------------- next part -------------- An HTML attachment was scrubbed... URL: From dcelta at gmail.com Tue Jul 6 03:58:28 2010 From: dcelta at gmail.com (Daniel J. Celta) Date: Mon, 5 Jul 2010 20:58:28 -0500 Subject: [coreboot] H8DME-2 In-Reply-To: References: Message-ID: Greg, Could you point me to the right "Wiki" page, so I can provide what you are referring to. I am thinking machine and motherboard specs, but I want to make sure I am looking at the same page you are. Thanks On Mon, Jul 5, 2010 at 5:51 PM, Gregg Levine wrote: > On Mon, Jul 5, 2010 at 5:02 PM, Daniel J. Celta wrote: > > Has anyone updated this Supermicro server Board BIOS for the > H8DME-2...... > > > > I have installed FC10, (i was able to complete this installation by > turning > > of the RAID configuration in the BIOS), and now I am having trouble when > > trying to upgrade the Operating system to FC13. > > > > > > I suspect, if I update the BIOS, I currently have the version of the BIOS > > that came pre-installed with the server, I may be able to upgrade to > FC13. > > > > One thing I like to mention, when running "make menuconfig" I was not > sure > > of the ROM Chip size, and used the largest available setting 4MB. > > > > - How can I check the proper setting for this parameter???? > > > > > > > > So now, I have created the coreboot.rom, and think I am ready to run > > "flashrom"....... > > > > - Is there anything else I need to check before I pull the trigger??? > > > > - Has anyone had any problems I should be aware of???? > > > > > > Thanks > > > > Daniel > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > Hello! > I confess I'm not familiar with that board. Why don't you post the > exact same things that the Wiki asks for? That way the rest of us, > even those of us who do know it, can advise you? I do however believe > you're on the right path. > > > ----- > Gregg C Levine gregg.drwho8 at gmail.com > "This signature fought the Time Wars, time and again." > -------------- next part -------------- An HTML attachment was scrubbed... URL: From gregg.drwho8 at gmail.com Tue Jul 6 04:06:30 2010 From: gregg.drwho8 at gmail.com (Gregg Levine) Date: Mon, 5 Jul 2010 22:06:30 -0400 Subject: [coreboot] H8DME-2 In-Reply-To: References: Message-ID: On Mon, Jul 5, 2010 at 9:58 PM, Daniel J. Celta wrote: > Greg, > Could you point me to the right "Wiki" page, so I can provide what you are > referring to. > I am thinking machine and motherboard specs, but I want to make sure I am > looking at the same page you are. > Thanks > > On Mon, Jul 5, 2010 at 5:51 PM, Gregg Levine wrote: >> >> On Mon, Jul 5, 2010 at 5:02 PM, Daniel J. Celta wrote: >> > Has anyone updated this Supermicro server Board BIOS for the >> > H8DME-2...... >> > >> > I have installed FC10, (i was able to complete this installation by >> > turning >> > of the RAID configuration in the BIOS), and now I am having trouble when >> > trying to upgrade the Operating system to FC13. >> > >> > >> > I suspect, if I update the BIOS, I currently have the version of the >> > BIOS >> > that came pre-installed with the server, I may be able to upgrade to >> > FC13. >> > >> > One thing I like to mention, when running "make menuconfig" I was not >> > sure >> > of the ROM Chip size, and used the largest available setting 4MB. >> > >> > - How can I check the proper setting for this parameter???? >> > >> > >> > >> > So now, I have created the coreboot.rom, and think I am ready to run >> > "flashrom"....... >> > >> > - Is there anything else I need to check before I pull the trigger??? >> > >> > - Has anyone had any problems I should be aware of???? >> > >> > >> > Thanks >> > >> > Daniel >> > >> > -- >> > coreboot mailing list: coreboot at coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> >> Hello! >> I confess I'm not familiar with that board. Why don't you post the >> exact same things that the Wiki asks for? That way the rest of us, >> even those of us who do know it, can advise you? I do however believe >> you're on the right path. >> >> >> ----- >> Gregg C Levine gregg.drwho8 at gmail.com >> "This signature fought the Time Wars, time and again." > > Hello! I found it listed here: http://www.coreboot.org/Supported_Motherboards It's on the entries marked as servers, and of course via the vendor's entered name. Third one down from there. ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From dcelta at gmail.com Tue Jul 6 04:17:27 2010 From: dcelta at gmail.com (Daniel J. Celta) Date: Mon, 5 Jul 2010 21:17:27 -0500 Subject: [coreboot] H8DME-2 In-Reply-To: References: Message-ID: Ok I see now what you were referring to. All, The details about the board below: Vendor: Supermicro MainBoard: H8DME-2 NorthVBridge: AMD K8 SouthBridge: NVIDIA MCP55 Super I/O: Winbond? W83627EHG CPU: AMD Opteron Thanks Supermicro H8DME-2 AMD K8 NVIDIA MCP55 Winbond? W83627EHG AMD Opteron? Socket F On Mon, Jul 5, 2010 at 9:06 PM, Gregg Levine wrote: > On Mon, Jul 5, 2010 at 9:58 PM, Daniel J. Celta wrote: > > Greg, > > Could you point me to the right "Wiki" page, so I can provide what you > are > > referring to. > > I am thinking machine and motherboard specs, but I want to make sure I am > > looking at the same page you are. > > Thanks > > > > On Mon, Jul 5, 2010 at 5:51 PM, Gregg Levine > wrote: > >> > >> On Mon, Jul 5, 2010 at 5:02 PM, Daniel J. Celta > wrote: > >> > Has anyone updated this Supermicro server Board BIOS for the > >> > H8DME-2...... > >> > > >> > I have installed FC10, (i was able to complete this installation by > >> > turning > >> > of the RAID configuration in the BIOS), and now I am having trouble > when > >> > trying to upgrade the Operating system to FC13. > >> > > >> > > >> > I suspect, if I update the BIOS, I currently have the version of the > >> > BIOS > >> > that came pre-installed with the server, I may be able to upgrade to > >> > FC13. > >> > > >> > One thing I like to mention, when running "make menuconfig" I was not > >> > sure > >> > of the ROM Chip size, and used the largest available setting 4MB. > >> > > >> > - How can I check the proper setting for this parameter???? > >> > > >> > > >> > > >> > So now, I have created the coreboot.rom, and think I am ready to run > >> > "flashrom"....... > >> > > >> > - Is there anything else I need to check before I pull the trigger??? > >> > > >> > - Has anyone had any problems I should be aware of???? > >> > > >> > > >> > Thanks > >> > > >> > Daniel > >> > > >> > -- > >> > coreboot mailing list: coreboot at coreboot.org > >> > http://www.coreboot.org/mailman/listinfo/coreboot > >> > > >> > >> Hello! > >> I confess I'm not familiar with that board. Why don't you post the > >> exact same things that the Wiki asks for? That way the rest of us, > >> even those of us who do know it, can advise you? I do however believe > >> you're on the right path. > >> > >> > >> ----- > >> Gregg C Levine gregg.drwho8 at gmail.com > >> "This signature fought the Time Wars, time and again." > > > > > > Hello! > I found it listed here: > http://www.coreboot.org/Supported_Motherboards > > It's on the entries marked as servers, and of course via the vendor's > entered name. Third one down from there. > ----- > Gregg C Levine gregg.drwho8 at gmail.com > "This signature fought the Time Wars, time and again." > -------------- next part -------------- An HTML attachment was scrubbed... URL: From dcelta at gmail.com Tue Jul 6 03:59:57 2010 From: dcelta at gmail.com (Daniel J. Celta) Date: Mon, 5 Jul 2010 20:59:57 -0500 Subject: [coreboot] Fwd: Re H8DME-2 In-Reply-To: References: <4c3274ed.454cdf0a.0a1b.ffffaff7SMTPIN_ADDED@mx.google.com> Message-ID: Ok I was able to determine the ROM chip of the server..... Thank you very much... Now, I did save the original BIOS information using "flashrom -r " But, not sure I know how to rebuild back the BIOS from this file in case needed. Do you have any suggestions???? Thanks On Mon, Jul 5, 2010 at 7:12 PM, anders at jenbo.dk wrote: > Run flashrom with no parameters and it should tell you what Rom chip you > have. > > Before you pull the trigger you should make sure that you have a way to > recover the original BIOS (with out the use of the computer you are doing > this to). > > Mvh Anders > > ----- Reply message ----- > Fra: "Daniel J. Celta" > Dato: man., jul. 5, 2010 23:02 > Emne: [coreboot] H8DME-2 > Til: > > Has anyone updated this Supermicro server Board BIOS for the H8DME-2...... > > I have installed FC10, (i was able to complete this installation by turning > of the RAID configuration in the BIOS), and now I am having trouble when > trying to upgrade the Operating system to FC13. > > > I suspect, if I update the BIOS, I currently have the version of the BIOS > that came pre-installed with the server, I may be able to upgrade to FC13. > > One thing I like to mention, when running "make menuconfig" I was not sure > of the ROM Chip size, and used the largest available setting 4MB. > > - How can I check the proper setting for this parameter???? > > > > So now, I have created the coreboot.rom, and think I am ready to run > "flashrom"....... > > - Is there anything else I need to check before I pull the trigger??? > > - Has anyone had any problems I should be aware of???? > > > Thanks > > Daniel > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From dcelta at gmail.com Tue Jul 6 04:33:05 2010 From: dcelta at gmail.com (Daniel J. Celta) Date: Mon, 5 Jul 2010 21:33:05 -0500 Subject: [coreboot] Re H8DME-2 In-Reply-To: <1278381578.4719.7.camel@anders-desktop> References: <4c3274ed.454cdf0a.0a1b.ffffaff7SMTPIN_ADDED@mx.google.com> <1278381578.4719.7.camel@anders-desktop> Message-ID: Anders, Thanks you, I can see how to flash as long as I can boot the machine, otherwise I am in trouble. I wiould have no means to get to that chip and flash it back with the original BIOS........ :( Is there a way to test if the LinuxBIOS would work, without locking myself out....... ???? Has anyone done this on this board????? Thanks On Mon, Jul 5, 2010 at 8:59 PM, Anders Jenbo wrote: > You can flash the original image in the same way as you are going to do > with the coreboot image. flashrom -w imagename.rom > > But if you board fails to boot then you will need to have access to some > thing else that can flash that chip, one option is another motherboard > that uses the same type of chip, or a rom flasher for the type of chip > you have. This requires that the chip is socketed, so that you can > remove it from the board as you write back the old image. > > Another option is to use what is known as a tophat, it will allow you to > install a second flash rom on top of the once that is soldered on to the > board (this only works with plcc32 chips as fare as i know). > > -Anders > > man, 05 07 2010 kl. 20:53 -0500, skrev Daniel J. Celta: > > Ok I was able to determine the ROM chip of the server..... Thank you > > very much... > > > > Now, I did save the original BIOS information using "flashrom -r > > " > > > > But, not sure I know how to rebuild back the BIOS from this file in > > case needed. > > > > Do you have any suggestions???? > > > > Thanks > > > > On Mon, Jul 5, 2010 at 7:12 PM, anders at jenbo.dk > > wrote: > > Run flashrom with no parameters and it should tell you what > > Rom chip you have. > > > > Before you pull the trigger you should make sure that you have > > a way to recover the original BIOS (with out the use of the > > computer you are doing this to). > > > > Mvh Anders > > > > ----- Reply message ----- > > Fra: "Daniel J. Celta" > > Dato: man., jul. 5, 2010 23:02 > > Emne: [coreboot] H8DME-2 > > Til: > > > > > > Has anyone updated this Supermicro server Board BIOS for the > > H8DME-2...... > > > > I have installed FC10, (i was able to complete this > > installation by turning of the RAID configuration in the > > BIOS), and now I am having trouble when trying to upgrade the > > Operating system to FC13. > > > > > > I suspect, if I update the BIOS, I currently have the version > > of the BIOS that came pre-installed with the server, I may be > > able to upgrade to FC13. > > > > One thing I like to mention, when running "make menuconfig" I > > was not sure of the ROM Chip size, and used the largest > > available setting 4MB. > > > > - How can I check the proper setting for this parameter???? > > > > > > > > So now, I have created the coreboot.rom, and think I am ready > > to run "flashrom"....... > > > > - Is there anything else I need to check before I pull the > > trigger??? > > > > - Has anyone had any problems I should be aware of???? > > > > > > Thanks > > > > Daniel > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From masoudf at t2data.se Tue Jul 6 10:47:27 2010 From: masoudf at t2data.se (Masoud Fatollahy) Date: Tue, 06 Jul 2010 10:47:27 +0200 Subject: [coreboot] minimum linuxbios Message-ID: Hi, I am working to make a minimal linuxbios without any payload or linux kernel, I just want to see a nice hello word string on the serial port and nothing else. is it possible to make such a bios? also to setup only the necessary HW registers and memory to see the printout message. how should i do this? thanks, /Masoud -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Tue Jul 6 12:01:35 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 6 Jul 2010 12:01:35 +0200 Subject: [coreboot] minimum linuxbios In-Reply-To: References: Message-ID: <20100706100135.16554.qmail@stuge.se> Hej Masoud, Masoud Fatollahy wrote: > I am working to make a minimal linuxbios Note that LinuxBIOS is not really used anymore. The project changed it's name to coreboot. > without any payload or linux kernel, ..and *if* LinuxBIOS *is* used, then it refers to coreboot+Linux kernel as payload. That said, if you want to control what happens with the system after coreboot, then you need a payload. > I just want to see a nice hello word string on the serial port and > nothing else. Then you need to disable all debugging in coreboot, it will otherwise send a bunch of messages over the serial port. And you will also need to make a minimal payload using libpayload. It will look like: #include /* reservation: you may need other headers */ int main() { printf("Hello, world!\n"); while(1); } That is then compiled with lpgcc -o hello.elf hello.c and you'll use hello.elf as payload. It's very simple. > is it possible to make such a bios? also to setup only the > necessary HW registers and memory to see the printout message. coreboot does complete init of the components in the system which it knows about from compile time, and which it finds during system enumeration at run time. My guess is that your concern is boot speed rather than lines of code actually used. On smaller systems coreboot typically runs in a few hundred milliseconds. If that's not enough, then yes, you'll have some work to do in order to minimize the code being executed. > how should i do this? Get a supported hardware and start experimenting. You can do some testing with QEMU also. //Peter From mark.marshall at csr.com Tue Jul 6 11:53:17 2010 From: mark.marshall at csr.com (Mark Marshall) Date: Tue, 06 Jul 2010 10:53:17 +0100 Subject: [coreboot] minimum linuxbios In-Reply-To: References: Message-ID: <4C32FD0D.6020001@csr.com> Masoud Fatollahy wrote: > > Hi, > > I am working to make a minimal linuxbios without any payload or linux > kernel, I just want to see a nice hello word string on the serial port > and nothing else. is it possible to make such a bios? also to setup only > the necessary HW registers and memory to see the printout message. > > how should i do this? Look at SerialICE: http://www.serialice.com/News/News.html This is a mini monitor that runs over the serial port. The coreboot developers use it to step through a BIOS image, but it contains just enough to get the serial port working. Memory is not initialized, so everything is done with registers. MarkM From peter at stuge.se Tue Jul 6 12:33:10 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 6 Jul 2010 12:33:10 +0200 Subject: [coreboot] Re H8DME-2 In-Reply-To: References: <4c3274ed.454cdf0a.0a1b.ffffaff7SMTPIN_ADDED@mx.google.com> <1278381578.4719.7.camel@anders-desktop> Message-ID: <20100706103310.22228.qmail@stuge.se> Daniel, Daniel J. Celta wrote: > I wiould have no means to get to that chip and flash it back with > the original BIOS........ :( > > Is there a way to test if the LinuxBIOS would work, without locking > myself out....... ???? As you know, coreboot replaces your factory BIOS. So there is no way to boot your system if coreboot does not work on the first try. This will not likely happen. :) Make sure that you have some way to recover. Use a second mainboard to flash your chip, or better yet buy a few spare flash chips and program them with your factory BIOS while developing coreboot. > Has anyone done this on this board????? The process is identical for all boards. //Peter From anders at jenbo.dk Tue Jul 6 15:47:04 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Tue, 06 Jul 2010 15:47:04 +0200 Subject: [coreboot] =?utf-8?q?minimum_linuxbios?= Message-ID: You could remove RAM and probably also CPU from the system then, and you wouldn't need to start the south or north bridge, just the super io. Just find the first debug message after serial init and change it to what you want to output. Mvh Anders ----- Reply message ----- Fra: "Masoud Fatollahy" Dato: tir., jul. 6, 2010 10:47 Emne: [coreboot] minimum linuxbios Til: -------------- next part -------------- An HTML attachment was scrubbed... URL: From joe.korty at ccur.com Tue Jul 6 15:49:59 2010 From: joe.korty at ccur.com (Joe Korty) Date: Tue, 6 Jul 2010 09:49:59 -0400 Subject: [coreboot] my coreboot experiences with the H8DME-2 [Was: H8DME-2] In-Reply-To: References: Message-ID: <20100706134959.GA12051@tsunami.ccur.com> On Mon, Jul 05, 2010 at 05:02:16PM -0400, Daniel J. Celta wrote: > Has anyone updated this Supermicro server Board BIOS > for the H8DME-2...... > > I have installed FC10, (i was able to complete this > installation by turning of the RAID configuration in the > BIOS), and now I am having trouble when trying to upgrade > the Operating system to FC13. > > I suspect, if I update the BIOS, I currently have the > version of the BIOS that came pre-installed with the > server, I may be able to upgrade to FC13. > > One thing I like to mention, when running "make > menuconfig" I was not sure of the ROM Chip size, and used > the largest available setting 4MB. > > - How can I check the proper setting for this parameter???? > > So now, I have created the coreboot.rom, and think I am > ready to run "flashrom"....... > > - Is there anything else I need to check before I pull the trigger??? > - Has anyone had any problems I should be aware of???? > > Thanks > Daniel Hi Daniel, My first (and so far only) experience in installing coreboot was with the H8DME-2. http://www.mindspring.com/~jakorty/coreboot.html is a step-by-step writeup of my experiences. This page was written up quite recently (May), so, unlike most coreboot documentation found on the web, nothing in it should yet be obsolete. Regards, Joe From r.ozgur.doruk at gmail.com Tue Jul 6 15:50:21 2010 From: r.ozgur.doruk at gmail.com (r. ozgur doruk) Date: Tue, 6 Jul 2010 16:50:21 +0300 Subject: [coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets Message-ID: Hello, I have Pentium4 laptop motherboard of which BIOS chip is soldered out by some guys and it doesn't read newly programmed bios chip (a SST49lf080a) as far as I understand since it even does not beep. And no harddisk signal, no video and so on. In order to diagnose I have written a VHDL code (citing Andy Green's Milksop experiment) and then program my code on a Xilinx CPLD and connect it to the LPC debug board connector on the motherboard which has the signals LAD0 - 3, LRST, LFRAME, LCLK. The job of my VHDL code is to convert the LPC protocol to a parallel address and data combination so that I can at least trace what the motherboard responds. When I do that, if I give a long sync to the motherboard after the first address is received by the PLD I understand that the motherboard starts to fetch the flash codes from the adress 0xFFFFFFD0. In fact this conforms to the script written by the current coreboot developer as the SIS 966 has a firmware trap in the memory region starting from 0xFFFFFFD0. When I operate the system giving a ready sync after each address reception to the PLD the system runs until showing 0xFFFFFFDF and the value stays in the CPLD address output busses. The same thing is observed when the board is operated without the CPU in its socket. I operate the mainboard without the CPU using a small hack connecting one of the VID pins to the ground, thermal diode output to the vcc core, sckocc to the ground and thermtrip to the vcc core. By that board thinks that CPU is connected. The interesting thing is that, when I measure the powergood and the reset inputs to the processor (by plugging the wires to the wholes as no processor is there). After the PLD address output is 0xFFFFFFDF both RESET and POWERGOOD inputs become active so I think that the southbridge/northbridge mechanism is alive. I also measured all of the processor socket holes one by one and found no problematic conditions on the socket contacts. The processor is heating up when operated without the heat sink and I also noticed that thermtrip mechanism is also working as it shutdown after a high value of temperature. Because of that I think that the processor is defective but again I can not be sure about that because of this firmware trap feature of the chipsets I mention. So are those firmware traps in the SIS chipsets are effective on the boot process of the processor? Or any other reasons? Can I hear about your ideas? Thanks for all considerations Ozgur -------------- next part -------------- An HTML attachment was scrubbed... URL: From joe at settoplinux.org Tue Jul 6 16:34:12 2010 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 06 Jul 2010 10:34:12 -0400 Subject: [coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets In-Reply-To: References: Message-ID: On Tue, 6 Jul 2010 16:50:21 +0300, "r. ozgur doruk" wrote: > Hello, > > I have Pentium4 laptop motherboard of which BIOS chip is soldered out by > some guys and it doesn't read newly programmed bios chip (a SST49lf080a) as > far as I understand since it even does not beep. And no harddisk signal, no > video and so on. In order to diagnose I have written a VHDL code (citing > Andy Green's Milksop experiment) and then program my code on a Xilinx CPLD > and connect it to the LPC debug board connector on the motherboard which > has > the signals LAD0 - 3, LRST, LFRAME, LCLK. The job of my VHDL code is to > convert the LPC protocol to a parallel address and data combination so that > I can at least trace what the motherboard responds. When I do that, if I > give a long sync to the motherboard after the first address is received by > the PLD I understand that the motherboard starts to fetch the flash codes > from the adress 0xFFFFFFD0. In fact this conforms to the script written by > the current coreboot developer as the SIS 966 has a firmware trap in the > memory region starting from 0xFFFFFFD0. When I operate the system giving a > ready sync after each address reception to the PLD the system runs until > showing 0xFFFFFFDF and the value stays in the CPLD address output busses. > The same thing is observed when the board is operated without the CPU in > its > socket. > > I operate the mainboard without the CPU using a small hack connecting one > of > the VID pins to the ground, thermal diode output to the vcc core, sckocc to > the ground and thermtrip to the vcc core. By that board thinks that CPU is > connected. > > The interesting thing is that, when I measure the powergood and the reset > inputs to the processor (by plugging the wires to the wholes as no > processor > is there). After the PLD address output is 0xFFFFFFDF both RESET and > POWERGOOD inputs become active so I think that the southbridge/northbridge > mechanism is alive. I also measured all of the processor socket holes one > by > one and found no problematic conditions on the socket contacts. > > The processor is heating up when operated without the heat sink and I also > noticed that thermtrip mechanism is also working as it shutdown after a > high > value of temperature. Because of that I think that the processor is > defective but again I can not be sure about that because of this firmware > trap feature of the chipsets I mention. So are those firmware traps in the > SIS chipsets are effective on the boot process of the processor? Or any > other reasons? > > Can I hear about your ideas? > > Thanks for all considerations > Very cool idea. I think SerialICE debugging may be alot easier, give you better results, and alot more information. http://www.serialice.com -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From r.marek at assembler.cz Tue Jul 6 16:53:50 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 06 Jul 2010 16:53:50 +0200 Subject: [coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets In-Reply-To: References: Message-ID: <4C33437E.2040800@assembler.cz> Hi, >I can not be sure about that because of >this firmware trap feature of the chipsets I mention. So are those > firmware traps in the SIS chipsets are effective on the boot process of > the processor? Or any other reasons? I think they are independent of CPU itself. It usually configures some registers in chipsets for default values, like SB-NB bus. If you cannot see any fetches except those, the CPU is not running or is unable to talk to the flash (defective route). The thermtrip is sw independent so does not play role here. Thanks Rudolf From caibaiyin.pku at gmail.com Tue Jul 6 17:48:58 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Tue, 6 Jul 2010 23:48:58 +0800 Subject: [coreboot] payload bayou can not be compiled. Message-ID: /home/work/coreboot-work/payloads/bayou/build/libpayload/bin/lpgcc -Wall -Werror -Os -DCONFIG_BUILTIN_LAR -DCONFIG_LZMA -DCONFIG_NRV2B -I/home/work/coreboot-work/payloads/bayou/build/libpayload/include -c -o main.o main.c basename: missing operand Try `basename --help' for more information. In file included from main.c:20: hi all, i am trying to use bayou as an payload. but i find it can not be build. the error message seems like: > bayou.h:60: error: field ?stat? has incomplete type > cc1: warnings being treated as errors > bayou.h:85: error: ?struct LAR? declared inside parameter list > bayou.h:85: error: its scope is only this definition or declaration, which > is probably not what you want > main.c: In function ?main?: > main.c:34: error: implicit declaration of function ?openlar? > main.c:34: error: assignment makes pointer from integer without a cast > main.c:41: error: passing argument 1 of ?get_configuration? from > incompatible pointer type > bayou.h:85: note: expected ?struct LAR *? but argument is of type ?struct > LAR *? > make: *** [main.o] Error 1 > any suggestions ? -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Tue Jul 6 17:46:21 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 6 Jul 2010 23:46:21 +0800 Subject: [coreboot] gigabyte dual bios programming Message-ID: hi all, Since i am trying to do my 780 mass porting, i faced a problem about Gigabyte dual bios mainboard. my SF100 programmer can not detect the spi chip unless i removed it from the mainboard, but i can not use this method to test my coreboot code for i would program the chip lots of time. Is there any idea about this? it's pretty strange about these dual bios things. Any suggestion will be welcome for me. -- Wang Qing Pei MSN:wangqingpei at hotmail.com Gmail:wangqingpei at gmail.com Phone:86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From bari at onelabs.com Tue Jul 6 18:30:59 2010 From: bari at onelabs.com (bari) Date: Tue, 06 Jul 2010 11:30:59 -0500 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: Message-ID: <4C335A43.9000104@onelabs.com> Qing Pei, Try the flashrom patch here: http://www.flashrom.org/pipermail/flashrom/2010-April/002905.html -Bari Qing Pei Wang wrote: > hi all, > Since i am trying to do my 780 mass porting, i faced a problem about > Gigabyte dual bios mainboard. my SF100 programmer can not > detect the spi chip unless i removed it from the mainboard, but i can > not use this method to test my coreboot code for i would program > the chip lots of time. > Is there any idea about this? it's pretty strange about these dual bios > things. > Any suggestion will be welcome for me. > > -- > Wang Qing Pei > MSN:wangqingpei at hotmail.com > Gmail:wangqingpei at gmail.com > Phone:86+13426369984 > From peter at stuge.se Tue Jul 6 19:30:34 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 6 Jul 2010 19:30:34 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: Message-ID: <20100706173034.24990.qmail@stuge.se> Hi, Qing Pei Wang wrote: > i faced a problem about Gigabyte dual bios mainboard. my SF100 > programmer can not detect the spi chip unless i removed it from > the mainboard, .. > Is there any idea about this? it's pretty strange about these dual > bios things. > Any suggestion will be welcome for me. Please see http://www.mail-archive.com/coreboot at coreboot.org/msg23613.html http://www.mail-archive.com/linuxbios at linuxbios.org/msg05929.html And there's info about this as implemented on the GA-M57SLI-S4 board on http://stuge.se/m57sli/ Do you have two flash chips populated, or only a single one? //Peter From njacobs8 at hetnet.nl Tue Jul 6 20:27:12 2010 From: njacobs8 at hetnet.nl (Nils) Date: Tue, 6 Jul 2010 20:27:12 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR Message-ID: <201007062027.12484.njacobs8@hetnet.nl> Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. From svn at coreboot.org Tue Jul 6 22:36:36 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 22:36:36 +0200 Subject: [coreboot] [commit] r5652 - in trunk/src: mainboard/msi/ms7135 mainboard/sunw/ultra40 mainboard/tyan/s2892 mainboard/tyan/s2895 northbridge/amd/amdk8 southbridge/nvidia/ck804 Message-ID: Author: myles Date: Tue Jul 6 22:36:36 2010 New Revision: 5652 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5652 Log: A bug fix: Fix the ctrl_devport_conf_clear to clear the enable bit. A simplification: Dynamically enable ck804s that are found instead of relying on #defines. Removing an Opteron changes the number of ck804s that are present. Simple changes to make it easier to compare the factory BIOS with Coreboot when using SerialICE for boards with the Nvidia ck804 chipset: If the mask is zero, don't read the value, just write the new value over it. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -45,7 +45,6 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" /* Used by ck804_early_setup(). */ -#define CK804_NUM 1 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -79,7 +79,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 2 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -60,7 +60,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Jul 6 22:36:36 2010 (r5652) @@ -73,7 +73,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 2 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -90,7 +89,6 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jul 6 22:36:36 2010 (r5652) @@ -15,7 +15,8 @@ #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); + if (register_values[i+1]) + reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); @@ -60,7 +61,8 @@ unsigned long reg; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); + if (register_values[i+2]) + reg = pci_read_config32(dev, where); reg &= register_values[i+2]; reg |= register_values[i+3]; pci_write_config32(dev, where, reg); @@ -71,7 +73,8 @@ unsigned where; unsigned reg; where = register_values[i+1] + offset_io_base; - reg = inb(where); + if (register_values[i+2]) + reg = inb(where); reg &= register_values[i+2]; reg |= register_values[i+3]; outb(reg, where); @@ -82,7 +85,8 @@ unsigned where; unsigned long reg; where = register_values[i+1] + offset_io_base; - reg = inl(where); + if (register_values[i+2]) + reg = inl(where); reg &= register_values[i+2]; reg |= register_values[i+3]; outl(reg, where); Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Jun 29 23:26:17 2010 (r5651) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Jul 6 22:36:36 2010 (r5652) @@ -102,8 +102,8 @@ unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff01), 0, }; int j; @@ -211,9 +211,10 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif -#if CK804_NUM > 1 + }; + + static const unsigned int ctrl_conf_multiple[] = { RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), -#endif }; static const unsigned int ctrl_conf_slave[] = { @@ -284,7 +285,12 @@ if (busn[j] == 0) { setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(busn[0], CK804_DEVN_BASE, 0), io_base[0]); + PCI_DEV(0, CK804_DEVN_BASE, 0), io_base[0]); + if (ck804_num > 1) + setup_resource_map_x_offset(ctrl_conf_multiple, + ARRAY_SIZE(ctrl_conf_multiple), + PCI_DEV(0, CK804_DEVN_BASE, 0), 0); + continue; } From mylesgw at gmail.com Tue Jul 6 22:47:07 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 6 Jul 2010 14:47:07 -0600 Subject: [coreboot] SerialICE-based patch for s2895 Message-ID: These two patches make the SerialICE output match a lot better. I'm not sure which part is the magic one, but my board works better on a reset now. I may get around to cleaning it up so that only things that matter get changed, but it isn't likely to happen very soon. I'm not suggesting that this should be applied, but I'd like to save anyone else who needs to do this some work. If I were to apply it, I'd force most of the extra stuff into the CK804_MB_SETUP, or something similar, since I've only tested this on s2895. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: addr_change.diff Type: text/x-patch Size: 1877 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: match_factory.diff Type: text/x-patch Size: 17324 bytes Desc: not available URL: From svn at coreboot.org Tue Jul 6 23:05:05 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 23:05:05 +0200 Subject: [coreboot] [commit] r5653 - in trunk: src src/arch/i386/boot src/arch/i386/init src/cpu/amd/dualcore src/cpu/amd/model_10xxx src/cpu/amd/model_fxx src/cpu/amd/quadcore src/include/pc80 src/mainboard/a-trend/a... Message-ID: Author: myles Date: Tue Jul 6 23:05:04 2010 New Revision: 5653 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5653 Log: Re-integrate "USE_OPTION_TABLE" code. Signed-off-by: Edwin Beasant Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/Kconfig trunk/src/arch/i386/boot/coreboot_table.c trunk/src/arch/i386/init/bootblock_normal.c trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/pc80/mc146818rtc.h trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/advantech/pcm-5820/Kconfig trunk/src/mainboard/amd/db800/Kconfig trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/Kconfig trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/Kconfig trunk/src/mainboard/amd/pistachio/Kconfig trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/rumba/Kconfig trunk/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/Kconfig trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/Kconfig trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/Kconfig trunk/src/mainboard/asi/mb_5blgp/Kconfig trunk/src/mainboard/asi/mb_5blmp/Kconfig trunk/src/mainboard/asrock/939a785gmh/Kconfig trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/Kconfig trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/mew-am/Kconfig trunk/src/mainboard/asus/mew-vm/Kconfig trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-f/Kconfig trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/mainboard/axus/tc320/Kconfig trunk/src/mainboard/azza/pt-6ibd/Kconfig trunk/src/mainboard/bcom/winnet100/Kconfig trunk/src/mainboard/bcom/winnetp680/Kconfig trunk/src/mainboard/biostar/m6tba/Kconfig trunk/src/mainboard/broadcom/blast/Kconfig trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/src/mainboard/dell/s1850/Kconfig trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/Kconfig trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/Kconfig trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/Kconfig trunk/src/mainboard/eaglelion/5bcm/Kconfig trunk/src/mainboard/ecs/p6iwp-fe/Kconfig trunk/src/mainboard/emulation/qemu-x86/Kconfig trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/getac/p470/Kconfig trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/Kconfig trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig trunk/src/mainboard/ibase/mb899/Kconfig trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/ibm/e325/Kconfig trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/Kconfig trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig trunk/src/mainboard/intel/d810e2cb/Kconfig trunk/src/mainboard/intel/d945gclf/Kconfig trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/Kconfig trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/Kconfig trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/Kconfig trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/Kconfig trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/Kconfig trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/Kconfig trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/Kconfig trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/Kconfig trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/Kconfig trunk/src/mainboard/kontron/986lcd-m/Kconfig trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/Kconfig trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/frontrunner/Kconfig trunk/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/src/mainboard/mitac/6513wu/Kconfig trunk/src/mainboard/msi/ms6119/Kconfig trunk/src/mainboard/msi/ms6147/Kconfig trunk/src/mainboard/msi/ms6156/Kconfig trunk/src/mainboard/msi/ms6178/Kconfig trunk/src/mainboard/msi/ms7135/Kconfig trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/Kconfig trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/Kconfig trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nec/powermate2000/Kconfig trunk/src/mainboard/newisys/khepri/Kconfig trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/olpc/btest/Kconfig trunk/src/mainboard/olpc/rev_a/Kconfig trunk/src/mainboard/pcengines/alix1c/Kconfig trunk/src/mainboard/rca/rm4100/Kconfig trunk/src/mainboard/roda/rk886ex/Kconfig trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/src/mainboard/sunw/ultra40/Kconfig trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/Kconfig trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/Kconfig trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technexion/tim5690/Kconfig trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/Kconfig trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/technologic/ts5300/Kconfig trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/Kconfig trunk/src/mainboard/thomson/ip1000/Kconfig trunk/src/mainboard/traverse/geos/Kconfig trunk/src/mainboard/tyan/s1846/Kconfig trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/Kconfig trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/Kconfig trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/Kconfig trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/Kconfig trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/Kconfig trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/Kconfig trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/Kconfig trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/Kconfig trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/Kconfig trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/Kconfig trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/Kconfig trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/Kconfig trunk/src/mainboard/via/epia-m/Kconfig trunk/src/mainboard/via/epia-m700/Kconfig trunk/src/mainboard/via/epia-n/Kconfig trunk/src/mainboard/via/epia/Kconfig trunk/src/mainboard/via/pc2500e/Kconfig trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/Kconfig trunk/src/mainboard/winent/pl6064/Kconfig trunk/src/mainboard/wyse/s50/Kconfig trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/intel/i945/raminit.c trunk/src/pc80/Makefile.inc trunk/src/pc80/mc146818rtc.c trunk/src/pc80/mc146818rtc_early.c trunk/src/pc80/serial.c trunk/util/options/build_opt_tbl.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -83,6 +83,7 @@ config USE_OPTION_TABLE bool "Use CMOS for configuration values" default n + depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values. @@ -189,13 +190,17 @@ bool default n +config USE_OPTION_TABLE + bool + default n + config HAVE_OPTION_TABLE bool - default y + default n help This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. - It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig. + It defaults to 'n' but can be selected in mainboard/*/Kconfig. config PIRQ_ROUTE bool Modified: trunk/src/arch/i386/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/i386/boot/coreboot_table.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/arch/i386/boot/coreboot_table.c Tue Jul 6 23:05:04 2010 (r5653) @@ -29,7 +29,7 @@ #include #include #include -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_USE_OPTION_TABLE == 1) #include #endif @@ -188,7 +188,7 @@ return mainboard; } -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_USE_OPTION_TABLE == 1) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; @@ -535,7 +535,7 @@ rom_table_end &= ~0xffff; printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_USE_OPTION_TABLE == 1) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ Modified: trunk/src/arch/i386/init/bootblock_normal.c ============================================================================== --- trunk/src/arch/i386/init/bootblock_normal.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/arch/i386/init/bootblock_normal.c Tue Jul 6 23:05:04 2010 (r5653) @@ -2,7 +2,7 @@ #include #include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" +#include static void main(unsigned long bist) { Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/cpu/amd/dualcore/dualcore.c Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ #endif #include "cpu/amd/dualcore/dualcore_id.c" +#include static inline unsigned get_core_num_in_bsp(unsigned nodeid) { @@ -56,8 +57,7 @@ unsigned nodes; unsigned nodeid; - if (CONFIG_HAVE_OPTION_TABLE && - read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0)) { return; // disable multi_core } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Jul 6 23:05:04 2010 (r5653) @@ -109,13 +109,12 @@ /* get_nodes define in ht_wrapper.c */ nodes = get_nodes(); - disable_siblings = !CONFIG_LOGICAL_CPUS; - -#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 - if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core + if (!CONFIG_LOGICAL_CPUS || + read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; + } else { + disable_siblings = 0; } -#endif /* Assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */ Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Tue Jul 6 23:05:04 2010 (r5653) @@ -36,13 +36,12 @@ /* get_nodes define in in_coherent_ht.c */ nodes = get_nodes(); - disable_siblings = !CONFIG_LOGICAL_CPUS; - -#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 - if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core + if (!CONFIG_LOGICAL_CPUS || + read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; + } else { + disable_siblings = 0; } -#endif /* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */ nb_cfg_54 = read_nb_cfg_54(); Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/cpu/amd/quadcore/quadcore.c Tue Jul 6 23:05:04 2010 (r5653) @@ -18,7 +18,7 @@ */ #include -#include +#include #include #ifndef SET_NB_CFG_54 Modified: trunk/src/include/pc80/mc146818rtc.h ============================================================================== --- trunk/src/include/pc80/mc146818rtc.h Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/include/pc80/mc146818rtc.h Tue Jul 6 23:05:04 2010 (r5653) @@ -85,15 +85,48 @@ * LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined * in option_table.h */ +#if CONFIG_HAVE_OPTION_TABLE +#include +#endif + +#ifndef UTIL_BUILD_OPTION_TABLE +#include +static inline unsigned char cmos_read(unsigned char addr) +{ + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + return inb(RTC_BASE_PORT + offs + 1); +} -#if !defined(ASSEMBLY) && !defined(__PRE_RAM__) +static inline void cmos_write(unsigned char val, unsigned char addr) +{ + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + outb(val, RTC_BASE_PORT + offs + 1); +} +#endif + +#if !defined(__ROMCC__) void rtc_init(int invalid); -#if CONFIG_USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE int get_option(void *dest, const char *name); +unsigned read_option(unsigned start, unsigned size, unsigned def); #else static inline int get_option(void *dest __attribute__((unused)), const char *name __attribute__((unused))) { return -2; } +static inline unsigned read_option(unsigned start, unsigned size, unsigned def) + { return def; } #endif +#else +#include #endif #endif /* PC80_MC146818RTC_H */ Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "ATC-6220" depends on BOARD_A_TREND_ATC_6220 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_A_TREND_ATC_6220 - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/a-trend/atc-6240/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/a-trend/atc-6240/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "ATC-6240" depends on BOARD_A_TREND_ATC_6240 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_A_TREND_ATC_6240 - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "BE6-II V2.0" depends on BOARD_ABIT_BE6_II_V2_0 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ABIT_BE6_II_V2_0 - config IRQ_SLOT_COUNT int default 9 Modified: trunk/src/mainboard/advantech/pcm-5820/Kconfig ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/advantech/pcm-5820/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "PCM-5820" depends on BOARD_ADVANTECH_PCM_5820 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ADVANTECH_PCM_5820 - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/amd/db800/Kconfig ============================================================================== --- trunk/src/mainboard/amd/db800/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/db800/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "DB800" depends on BOARD_AMD_DB800 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_AMD_DB800 - config IRQ_SLOT_COUNT int default 4 Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -11,6 +11,7 @@ select GENERATE_ACPI_TABLES select GENERATE_MP_TABLE select GENERATE_PIRQ_TABLE + select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -40,8 +40,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/amd/mahogany/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/mahogany/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -11,6 +11,7 @@ select GENERATE_ACPI_TABLES select GENERATE_MP_TABLE select GENERATE_PIRQ_TABLE + select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/mahogany/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -40,8 +40,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_ITE_IT8718F select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -45,7 +45,6 @@ #include #include #include -#include "option_table.h" #include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/amd/norwich/Kconfig ============================================================================== --- trunk/src/mainboard/amd/norwich/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/norwich/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -21,11 +21,6 @@ default "Norwich" depends on BOARD_AMD_NORWICH -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_AMD_NORWICH - config IRQ_SLOT_COUNT int default 6 Modified: trunk/src/mainboard/amd/pistachio/Kconfig ============================================================================== --- trunk/src/mainboard/amd/pistachio/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/pistachio/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_SB600 select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/pistachio/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -34,8 +34,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/amd/rumba/Kconfig ============================================================================== --- trunk/src/mainboard/amd/rumba/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/rumba/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -38,11 +38,6 @@ default "Rumba" depends on BOARD_AMD_RUMBA -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_AMD_RUMBA - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -18,8 +18,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "./arch/i386/lib/printk_init.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,8 +26,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -45,7 +45,6 @@ #include #include #include -#include "option_table.h" #include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_ITE_IT8718F select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -45,7 +45,6 @@ #include #include #include -#include "option_table.h" #include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/arima/hdama/Kconfig ============================================================================== --- trunk/src/mainboard/arima/hdama/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/arima/hdama/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87360 select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/arima/hdama/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/artecgroup/dbe61/Kconfig ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/artecgroup/dbe61/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -21,11 +21,6 @@ default "DBE61" depends on BOARD_ARTECGROUP_DBE61 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ARTECGROUP_DBE61 - config IRQ_SLOT_COUNT int default 3 Modified: trunk/src/mainboard/asi/mb_5blgp/Kconfig ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asi/mb_5blgp/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "MB-5BLGP" depends on BOARD_ASI_MB_5BLGP -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASI_MB_5BLGP - config IRQ_SLOT_COUNT int default 3 Modified: trunk/src/mainboard/asi/mb_5blmp/Kconfig ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asi/mb_5blmp/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "MB-5BLMP" depends on BOARD_ASI_MB_5BLMP -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASI_MB_5BLMP - config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -13,6 +13,7 @@ select GENERATE_MP_TABLE select GENERATE_PIRQ_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -41,8 +41,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/asus/a8n_e/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8n_e/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/a8n_e/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_ITE_IT8712F select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -38,8 +38,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -10,6 +10,7 @@ select SUPERIO_WINBOND_W83627EHG select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -44,8 +44,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -49,8 +49,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/asus/mew-am/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-am/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/mew-am/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -41,11 +41,6 @@ default "MEW-AM" depends on BOARD_ASUS_MEW_AM -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_MEW_AM - config IRQ_SLOT_COUNT int default 8 Modified: trunk/src/mainboard/asus/mew-vm/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-vm/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/mew-vm/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -25,6 +25,7 @@ select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 select ROMCC + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -42,11 +42,6 @@ default "P2B-D" depends on BOARD_ASUS_P2B_D -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P2B_D - config IRQ_SLOT_COUNT int default 6 Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -42,11 +42,6 @@ default "P2B-DS" depends on BOARD_ASUS_P2B_DS -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P2B_DS - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/asus/p2b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-f/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p2b-f/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "P2B-F" depends on BOARD_ASUS_P2B_F -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P2B_F - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "P2B-LS" depends on BOARD_ASUS_P2B_LS -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P2B_LS - config IRQ_SLOT_COUNT int default 8 Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p2b/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "P2B" depends on BOARD_ASUS_P2B -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P2B - config IRQ_SLOT_COUNT int default 6 Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "P3B-F" depends on BOARD_ASUS_P3B_F -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ASUS_P3B_F - config IRQ_SLOT_COUNT int default 8 Modified: trunk/src/mainboard/axus/tc320/Kconfig ============================================================================== --- trunk/src/mainboard/axus/tc320/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/axus/tc320/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "TC320" depends on BOARD_AXUS_TC320 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_AXUS_TC320 - # Soldered NIC, internal USB, no real PCI slots. config IRQ_SLOT_COUNT int Modified: trunk/src/mainboard/azza/pt-6ibd/Kconfig ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/azza/pt-6ibd/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "PT-6IBD" depends on BOARD_AZZA_PT_6IBD -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_AZZA_PT_6IBD - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/bcom/winnet100/Kconfig ============================================================================== --- trunk/src/mainboard/bcom/winnet100/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/bcom/winnet100/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "WinNET100" depends on BOARD_BCOM_WINNET100 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_BCOM_WINNET100 - # Soldered NIC, internal USB, no real PCI slots. config IRQ_SLOT_COUNT int Modified: trunk/src/mainboard/bcom/winnetp680/Kconfig ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/bcom/winnetp680/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/biostar/m6tba/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/m6tba/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/biostar/m6tba/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "M6TBA" depends on BOARD_BIOSTAR_M6TBA -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_BIOSTAR_M6TBA - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/broadcom/blast/Kconfig ============================================================================== --- trunk/src/mainboard/broadcom/blast/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/broadcom/blast/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/broadcom/blast/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -11,8 +11,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "Deskpro EN SFF P600" depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600 - config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/dell/s1850/Kconfig ============================================================================== --- trunk/src/mainboard/dell/s1850/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/dell/s1850/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_NSC_PC8374 select ROMCC select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/dell/s1850/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -4,10 +4,9 @@ #include #include #include -//#include "option_table.h" #include #include "pc80/udelay_io.c" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" Modified: trunk/src/mainboard/digitallogic/msm586seg/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/digitallogic/msm586seg/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -3,6 +3,7 @@ select ARCH_X86 select CPU_AMD_SC520 select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE select BOARD_ROMSIZE_KB_512 select ROMCC Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -4,7 +4,7 @@ #include #include #include -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/digitallogic/msm800sev/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/digitallogic/msm800sev/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "MSM800SEV" depends on BOARD_DIGITALLOGIC_MSM800SEV -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_DIGITALLOGIC_MSM800SEV - config IRQ_SLOT_COUNT int default 9 Modified: trunk/src/mainboard/eaglelion/5bcm/Kconfig ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/eaglelion/5bcm/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "5BCM" depends on BOARD_EAGLELION_5BCM -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_EAGLELION_5BCM - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/ecs/p6iwp-fe/Kconfig ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -42,11 +42,6 @@ default "P6IWP-FE" depends on BOARD_ECS_P6IWP_FE -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_ECS_P6IWP_FE - config IRQ_SLOT_COUNT int default 10 Modified: trunk/src/mainboard/emulation/qemu-x86/Kconfig ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/emulation/qemu-x86/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -3,6 +3,7 @@ select ARCH_X86 select SOUTHBRIDGE_INTEL_I82371EB select ROMCC + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select WARNINGS_ARE_ERRORS Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "pc80/udelay_io.c" #include "lib/delay.c" Modified: trunk/src/mainboard/getac/p470/Kconfig ============================================================================== --- trunk/src/mainboard/getac/p470/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/getac/p470/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -31,6 +31,7 @@ select GENERATE_ACPI_TABLES select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select HAVE_ACPI_RESUME select HAVE_ACPI_SLIC Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -31,8 +31,7 @@ #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "GA-6BXC" depends on BOARD_GIGABYTE_GA_6BXC -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_GIGABYTE_GA_6BXC - config IRQ_SLOT_COUNT int default 6 Modified: trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -41,11 +41,6 @@ default "GA-6BXE" depends on BOARD_GIGABYTE_GA_6BXE -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_GIGABYTE_GA_6BXE - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_SIS_SIS966 select SUPERIO_ITE_IT8716F select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -41,8 +41,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "lib/uart8250.c" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -50,8 +50,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #if CONFIG_USBDEBUG Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_ITE_IT8716F select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -39,8 +39,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "lib/uart8250.c" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -48,8 +48,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #if CONFIG_USBDEBUG Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/hp/dl145_g3/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -54,8 +54,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -44,11 +44,6 @@ default "e-Vectra P2706T" depends on BOARD_HP_E_VECTRA_P2706T -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_HP_E_VECTRA_P2706T - config IRQ_SLOT_COUNT int default 3 Modified: trunk/src/mainboard/ibase/mb899/Kconfig ============================================================================== --- trunk/src/mainboard/ibase/mb899/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibase/mb899/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -11,6 +11,7 @@ select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -34,8 +34,7 @@ #include "superio/winbond/w83627ehg/w83627ehg.h" -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/ibm/e325/Kconfig ============================================================================== --- trunk/src/mainboard/ibm/e325/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibm/e325/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87366 + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibm/e325/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/ibm/e326/Kconfig ============================================================================== --- trunk/src/mainboard/ibm/e326/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibm/e326/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_NSC_PC87366 + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/ibm/e326/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -21,11 +21,6 @@ default "PCISA-LX-800-R10" depends on BOARD_IEI_PCISA_LX_800_R10 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_IEI_PCISA_LX_800_R10 - config IRQ_SLOT_COUNT int default 9 Modified: trunk/src/mainboard/intel/d810e2cb/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/d810e2cb/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "D810E2CB" depends on BOARD_INTEL_D810E2CB -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_INTEL_D810E2CB - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/intel/d945gclf/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d945gclf/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/d945gclf/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -29,6 +29,7 @@ select GENERATE_ACPI_TABLES select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -33,8 +33,7 @@ #include "superio/smsc/lpc47m15x/lpc47m15x.h" -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/intel/eagleheights/Kconfig ============================================================================== --- trunk/src/mainboard/intel/eagleheights/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/eagleheights/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select BOARD_HAS_FADT Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -29,8 +29,7 @@ #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/intel/jarrell/Kconfig ============================================================================== --- trunk/src/mainboard/intel/jarrell/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/jarrell/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/jarrell/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/intel/mtarvon/Kconfig ============================================================================== --- trunk/src/mainboard/intel/mtarvon/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/mtarvon/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "3100 devkit (Mt. Arvon)" depends on BOARD_INTEL_MTARVON -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_INTEL_MTARVON - config IRQ_SLOT_COUNT int default 1 Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,7 +26,7 @@ #include #include #include -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" Modified: trunk/src/mainboard/intel/truxton/Kconfig ============================================================================== --- trunk/src/mainboard/intel/truxton/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/truxton/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -23,11 +23,6 @@ default "Truxton" depends on BOARD_INTEL_TRUXTON -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_INTEL_TRUXTON - config IRQ_SLOT_COUNT int default 1 Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/truxton/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,7 +26,7 @@ #include #include #include -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/udelay_io.c" #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/intel/xe7501devkit/Kconfig ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/xe7501devkit/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -12,7 +12,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC - select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -6,8 +6,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8_htx/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,8 +26,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8s2/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,8 +26,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/iwill/dk8x/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8x/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8x/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627THF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -26,8 +26,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/jetway/j7f24/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/j7f24/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/jetway/j7f24/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_FINTEK_F71805F + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/kontron/986lcd-m/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -10,6 +10,7 @@ select GENERATE_ACPI_TABLES select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select HAVE_ACPI_RESUME select HAVE_MAINBOARD_RESOURCES Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -42,8 +42,7 @@ #include "superio/winbond/w83627thg/w83627thg.h" -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/kontron/kt690/Kconfig ============================================================================== --- trunk/src/mainboard/kontron/kt690/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/kontron/kt690/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_SB600 select SUPERIO_WINBOND_W83627DHG select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/kontron/kt690/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -41,8 +41,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/lippert/frontrunner/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/lippert/frontrunner/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -19,11 +19,6 @@ default "Cool Frontrunner" depends on BOARD_LIPPERT_FRONTRUNNER -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_LIPPERT_FRONTRUNNER - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/lippert/roadrunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "Cool RoadRunner-LX" depends on BOARD_LIPPERT_ROADRUNNER_LX -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_LIPPERT_ROADRUNNER_LX - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/lippert/spacerunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "Cool SpaceRunner-LX" depends on BOARD_LIPPERT_SPACERUNNER_LX -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_LIPPERT_SPACERUNNER_LX - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/mitac/6513wu/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/6513wu/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/mitac/6513wu/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -41,11 +41,6 @@ default "6513WU" depends on BOARD_MITAC_6513WU -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_MITAC_6513WU - config IRQ_SLOT_COUNT int default 8 Modified: trunk/src/mainboard/msi/ms6119/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6119/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms6119/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "MS-6119" depends on BOARD_MSI_MS_6119 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_MSI_MS_6119 - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/msi/ms6147/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6147/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms6147/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "MS-6147" depends on BOARD_MSI_MS_6147 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_MSI_MS_6147 - config IRQ_SLOT_COUNT int default 8 Modified: trunk/src/mainboard/msi/ms6156/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6156/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms6156/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "MS-6156" depends on BOARD_MSI_MS_6156 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_MSI_MS_6156 - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/msi/ms6178/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6178/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms6178/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "MS-6178" depends on BOARD_MSI_MS_6178 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_MSI_MS_6178 - config IRQ_SLOT_COUNT int default 4 Modified: trunk/src/mainboard/msi/ms7135/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7135/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms7135/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SUPERIO_WINBOND_W83627THF select HAVE_BUS_CONFIG select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_DCACHE_RAM Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -38,8 +38,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms7260/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -36,8 +36,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "console/console.c" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -52,8 +52,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #if CONFIG_USBDEBUG Modified: trunk/src/mainboard/msi/ms9185/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9185/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9185/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9185/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -47,8 +47,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/msi/ms9282/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9282/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9282/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9282/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -42,8 +42,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -49,11 +49,6 @@ default 0 depends on BOARD_MSI_MS9652_FAM10 -config HAVE_OPTION_TABLE - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - config MAX_CPUS int default 8 Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -43,7 +43,6 @@ #include #include #include -#include "option_table.h" #include #if CONFIG_USBDEBUG #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" Modified: trunk/src/mainboard/nec/powermate2000/Kconfig ============================================================================== --- trunk/src/mainboard/nec/powermate2000/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/nec/powermate2000/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -41,11 +41,6 @@ default "PowerMate 2000" depends on BOARD_NEC_POWERMATE_2000 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_NEC_POWERMATE_2000 - config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/newisys/khepri/Kconfig ============================================================================== --- trunk/src/mainboard/newisys/khepri/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/newisys/khepri/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/newisys/khepri/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -12,8 +12,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/nokia/ip530/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -42,11 +42,6 @@ default "IP530" depends on BOARD_NOKIA_IP530 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_NOKIA_IP530 - config IRQ_SLOT_COUNT int default 22 Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -39,8 +39,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "lib/uart8250.c" Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -48,8 +48,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #if CONFIG_USBDEBUG Modified: trunk/src/mainboard/olpc/btest/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/btest/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/olpc/btest/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -19,11 +19,6 @@ default "btest" depends on BOARD_OLPC_BTEST -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_OLPC_BTEST - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/olpc/rev_a/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/rev_a/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/olpc/rev_a/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -19,11 +19,6 @@ default "rev_a" depends on BOARD_OLPC_REV_A -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_OLPC_REV_A - config IRQ_SLOT_COUNT int default 2 Modified: trunk/src/mainboard/pcengines/alix1c/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/pcengines/alix1c/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "ALIX.1C" depends on BOARD_PCENGINES_ALIX1C -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_PCENGINES_ALIX1C - config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/rca/rm4100/Kconfig ============================================================================== --- trunk/src/mainboard/rca/rm4100/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/rca/rm4100/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -26,11 +26,6 @@ default "RM4100" depends on BOARD_RCA_RM4100 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_RCA_RM4100 - config DCACHE_RAM_BASE hex default 0xffdf8000 Modified: trunk/src/mainboard/roda/rk886ex/Kconfig ============================================================================== --- trunk/src/mainboard/roda/rk886ex/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/roda/rk886ex/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_SMSC_LPC47N227 select SUPERIO_RENESAS_M3885X select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select MMCONF_SUPPORT Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -35,8 +35,7 @@ #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "SY-6BA+ III" depends on BOARD_SOYO_SY_6BA_PLUS_III -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_SOYO_SY_6BA_PLUS_III - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/sunw/ultra40/Kconfig ============================================================================== --- trunk/src/mainboard/sunw/ultra40/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/sunw/ultra40/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_SMSC_LPC47M10X + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -14,8 +14,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -39,8 +39,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "console/console.c" Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -43,8 +43,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -39,8 +39,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "console/console.c" Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -46,8 +46,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -41,7 +41,6 @@ #include #include #include -#include "option_table.h" #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -41,7 +41,6 @@ #include #include #include -#include "option_table.h" #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/supermicro/x6dai_g/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dai_g/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhe_g/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_WATCHDOG_ON_BOOT Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_WATCHDOG_ON_BOOT Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -5,8 +5,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/technexion/tim5690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim5690/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technexion/tim5690/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_ITE_IT8712F select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -40,8 +40,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/technexion/tim8690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim8690/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technexion/tim8690/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_ITE_IT8712F select BOARD_HAS_FADT select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -40,8 +40,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include Modified: trunk/src/mainboard/technologic/ts5300/Kconfig ============================================================================== --- trunk/src/mainboard/technologic/ts5300/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technologic/ts5300/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -3,6 +3,7 @@ select ARCH_X86 select CPU_AMD_SC520 select ROMCC + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_128 Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -10,7 +10,7 @@ #include #include #include -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/televideo/tc7020/Kconfig ============================================================================== --- trunk/src/mainboard/televideo/tc7020/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/televideo/tc7020/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -40,11 +40,6 @@ default "TC7020" depends on BOARD_TELEVIDEO_TC7020 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_TELEVIDEO_TC7020 - config IRQ_SLOT_COUNT int default 3 Modified: trunk/src/mainboard/thomson/ip1000/Kconfig ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/thomson/ip1000/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -26,11 +26,6 @@ default "IP1000" depends on BOARD_THOMSON_IP1000 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_THOMSON_IP1000 - config DCACHE_RAM_BASE hex default 0xffdf8000 Modified: trunk/src/mainboard/traverse/geos/Kconfig ============================================================================== --- trunk/src/mainboard/traverse/geos/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/traverse/geos/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -21,11 +21,6 @@ default "Geos" depends on BOARD_TRAVERSE_GEOS -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_TRAVERSE_GEOS - config IRQ_SLOT_COUNT int default 6 Modified: trunk/src/mainboard/tyan/s1846/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s1846/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s1846/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -38,7 +38,3 @@ default "S1846" depends on BOARD_TYAN_S1846 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_TYAN_S1846 Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2735/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -6,8 +6,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2850/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2850/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2850/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2850/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2875/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2875/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2875/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2875/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2880/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2880/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2880/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2880/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2881/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2881/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2881/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2881/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -11,8 +11,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2882/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2882/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2882/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2882/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2885/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2885/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2885/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2885/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -6,8 +6,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2891/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2891/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2891/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -12,8 +12,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2892/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2892/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2892/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -9,6 +9,7 @@ select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_HARD_RESET + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -11,8 +11,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s2895/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2895/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2895/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -8,6 +8,7 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_SMSC_LPC47B397 select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -13,8 +13,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2912/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -39,8 +39,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include "pc80/serial.c" #include "console/console.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -48,8 +48,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #if CONFIG_USBDEBUG Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -43,7 +43,6 @@ #include #include #include -#include "option_table.h" #include #if CONFIG_USBDEBUG #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" Modified: trunk/src/mainboard/tyan/s4880/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s4880/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s4880/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s4880/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -7,8 +7,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/tyan/s4882/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s4882/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s4882/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/tyan/s4882/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -6,8 +6,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" Modified: trunk/src/mainboard/via/epia-cn/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-cn/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/epia-cn/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_VIA_VT1211 + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/via/epia-m/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/epia-m/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -7,6 +7,7 @@ select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_VIA_VT1211 select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/via/epia-m700/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m700/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/epia-m700/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_VIA_VX800 select SUPERIO_WINBOND_W83697HF select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/via/epia-n/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-n/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/epia-n/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select EPIA_VT8237R_INIT Modified: trunk/src/mainboard/via/epia/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/epia/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_VIA_VT8601 select SOUTHBRIDGE_VIA_VT8231 select SUPERIO_WINBOND_W83627HF + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select ROMCC Modified: trunk/src/mainboard/via/pc2500e/Kconfig ============================================================================== --- trunk/src/mainboard/via/pc2500e/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/pc2500e/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_ITE_IT8716F + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/pc2500e/romstage.c Tue Jul 6 23:05:04 2010 (r5653) @@ -25,8 +25,7 @@ #include #include #include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" +#include #include #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" Modified: trunk/src/mainboard/via/vt8454c/Kconfig ============================================================================== --- trunk/src/mainboard/via/vt8454c/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/via/vt8454c/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -5,6 +5,7 @@ select NORTHBRIDGE_VIA_CX700 select SUPERIO_VIA_VT1211 select BOARD_HAS_FADT + select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE # select MMCONF_SUPPORT Modified: trunk/src/mainboard/winent/pl6064/Kconfig ============================================================================== --- trunk/src/mainboard/winent/pl6064/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/winent/pl6064/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -22,11 +22,6 @@ default "PL6064" depends on BOARD_WINENT_PL6064 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_WINENT_PL6064 - config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/s50/Kconfig Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/mainboard/wyse/s50/Kconfig Tue Jul 6 23:05:04 2010 (r5653) @@ -39,11 +39,6 @@ default "s50" depends on BOARD_WYSE_S50 -config HAVE_OPTION_TABLE - bool - default n - depends on BOARD_WYSE_S50 - config IRQ_SLOT_COUNT int default 3 Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Tue Jul 6 23:05:04 2010 (r5653) @@ -68,6 +68,7 @@ #include #include #include "arch/romcc_io.h" +#include #include "amdk8.h" @@ -1594,8 +1595,7 @@ #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!CONFIG_HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/northbridge/amd/amdk8/raminit.c Tue Jul 6 23:05:04 2010 (r5653) @@ -549,8 +549,7 @@ if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (CONFIG_HAVE_OPTION_TABLE && - read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); @@ -1102,8 +1101,7 @@ { unsigned long tom_k, base_k; - if ((!CONFIG_HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { printk(BIOS_DEBUG, "Interleaving disabled\n"); @@ -1406,7 +1404,7 @@ min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { + if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/northbridge/intel/i945/raminit.c Tue Jul 6 23:05:04 2010 (r5653) @@ -19,6 +19,7 @@ #include #include +#include #include #include "raminit.h" #include "i945.h" @@ -2671,7 +2672,7 @@ values[3] |= (reg32 >> (24 - 4)) & 0xf0; /* coreboot only uses bytes 0 - 127 for its CMOS values so far - * so we grad bytes 128 - 131 to save the receive enable values + * so we grab bytes 128 - 131 to save the receive enable values */ for (i=0; i<4; i++) Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/pc80/Makefile.inc Tue Jul 6 23:05:04 2010 (r5653) @@ -3,7 +3,7 @@ obj-y += i8259.o obj-$(CONFIG_UDELAY_IO) += udelay_io.o obj-y += keyboard.o - +initobj-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.o initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o subdirs-y += vga Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/pc80/mc146818rtc.c Tue Jul 6 23:05:04 2010 (r5653) @@ -1,11 +1,7 @@ #include -#include #include #include #include -#if CONFIG_HAVE_OPTION_TABLE -#include -#endif /* control registers - Moto names */ @@ -76,29 +72,7 @@ # define RTC_VRT 0x80 /* valid RAM and time */ /**********************************************************************/ -static inline unsigned char cmos_read(unsigned char addr) -{ - int offs = 0; - if (addr >= 128) { - offs = 2; - addr -= 128; - } - outb(addr, RTC_BASE_PORT + offs + 0); - return inb(RTC_BASE_PORT + offs + 1); -} - -static inline void cmos_write(unsigned char val, unsigned char addr) -{ - int offs = 0; - if (addr >= 128) { - offs = 2; - addr -= 128; - } - outb(addr, RTC_BASE_PORT + offs + 0); - outb(val, RTC_BASE_PORT + offs + 1); -} - -#if CONFIG_HAVE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) { int i; @@ -138,14 +112,14 @@ void rtc_init(int invalid) { -#if CONFIG_HAVE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE unsigned char x; int cmos_invalid, checksum_invalid; #endif printk(BIOS_DEBUG, "RTC Init\n"); -#if CONFIG_HAVE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE /* See if there has been a CMOS power problem. */ x = cmos_read(RTC_VALID); cmos_invalid = !(x & RTC_VRT); @@ -186,7 +160,7 @@ /* Setup the frequency it operates at */ cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); -#if CONFIG_HAVE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE /* See if there is a LB CMOS checksum error */ checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END,LB_CKS_LOC); @@ -203,7 +177,7 @@ } -#if CONFIG_USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE /* This routine returns the value of the requested bits input bit = bit count from the beginning of the cmos image length = number of bits to include in the value Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/pc80/mc146818rtc_early.c Tue Jul 6 23:05:04 2010 (r5653) @@ -1,8 +1,5 @@ #include #include -#if CONFIG_HAVE_OPTION_TABLE -#include -#endif #ifndef CONFIG_MAX_REBOOT_CNT #error "CONFIG_MAX_REBOOT_CNT not defined" @@ -11,28 +8,6 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif -static unsigned char cmos_read(unsigned char addr) -{ - int offs = 0; - if (addr >= 128) { - offs = 2; - addr -= 128; - } - outb(addr, RTC_BASE_PORT + offs + 0); - return inb(RTC_BASE_PORT + offs + 1); -} - -static void cmos_write(unsigned char val, unsigned char addr) -{ - int offs = 0; - if (addr >= 128) { - offs = 2; - addr -= 128; - } - outb(addr, RTC_BASE_PORT + offs + 0); - outb(val, RTC_BASE_PORT + offs + 1); -} - static int cmos_error(void) { unsigned char reg_d; @@ -43,7 +18,7 @@ static int cmos_chksum_valid(void) { -#if CONFIG_HAVE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE unsigned char addr; unsigned long sum, old_sum; sum = 0; @@ -114,9 +89,9 @@ return (byte & (1<<1)); } -static inline unsigned read_option(unsigned start, unsigned size, unsigned def) +unsigned read_option(unsigned start, unsigned size, unsigned def) { -#if CONFIG_USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE unsigned byte; byte = cmos_read(start/8); return (byte >> (start & 7U)) & ((1U << size) - 1U); Modified: trunk/src/pc80/serial.c ============================================================================== --- trunk/src/pc80/serial.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/src/pc80/serial.c Tue Jul 6 23:05:04 2010 (r5653) @@ -1,5 +1,6 @@ #include /* Prototypes */ #include +#include "pc80/mc146818rtc.h" /* Base Address */ #ifndef CONFIG_TTYS0_BASE @@ -80,7 +81,7 @@ outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -#if CONFIG_USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); @@ -101,7 +102,7 @@ extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); void uart_init(void) { -#if CONFIG_USE_OPTION_TABLE == 1 +#if CONFIG_USE_OPTION_TABLE static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); Modified: trunk/util/options/build_opt_tbl.c ============================================================================== --- trunk/util/options/build_opt_tbl.c Tue Jul 6 22:36:36 2010 (r5652) +++ trunk/util/options/build_opt_tbl.c Tue Jul 6 23:05:04 2010 (r5653) @@ -25,6 +25,7 @@ #include #include #include +#define UTIL_BUILD_OPTION_TABLE #include "../../src/include/pc80/mc146818rtc.h" #include "../../src/include/boot/coreboot_tables.h" From mylesgw at gmail.com Tue Jul 6 23:05:42 2010 From: mylesgw at gmail.com (Myles Watson) Date: Tue, 6 Jul 2010 15:05:42 -0600 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> Message-ID: On Wed, Jun 30, 2010 at 11:52 AM, Edwin Beasant wrote: > Seems best of all worlds to me :-) > Can we get an ack and a commit? Rev 5653. Thanks, Myles From svn at coreboot.org Tue Jul 6 23:20:53 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 23:20:53 +0200 Subject: [coreboot] build service results for r5653 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5653 to the coreboot repository. This caused the following changes: Change Log: Re-integrate "USE_OPTION_TABLE" code. Signed-off-by: Edwin Beasant Signed-off-by: Myles Watson Acked-by: Myles Watson Build Log: Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5653&device=ms9652_fam10&vendor=msi&num=2 If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Tue Jul 6 23:37:39 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 23:37:39 +0200 Subject: [coreboot] [commit] r5654 - trunk/src/mainboard/msi/ms9652_fam10 Message-ID: Author: myles Date: Tue Jul 6 23:37:39 2010 New Revision: 5654 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5654 Log: Select HAVE_OPTION_TABLE for msi/ms9652_fam10. It fixes the build and doesn't change the behavior, since it is disabled by default. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Jul 6 23:05:04 2010 (r5653) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Jul 6 23:37:39 2010 (r5654) @@ -10,6 +10,7 @@ select HAVE_MP_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_OPTION_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select ENABLE_APIC_EXT_ID From svn at coreboot.org Tue Jul 6 23:40:13 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 23:40:13 +0200 Subject: [coreboot] [commit] r5655 - trunk/src/northbridge/amd/amdk8 Message-ID: Author: myles Date: Tue Jul 6 23:40:11 2010 New Revision: 5655 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5655 Log: Eliminate a couple of warnings from setup_resourcemap.c Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jul 6 23:37:39 2010 (r5654) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Tue Jul 6 23:40:11 2010 (r5655) @@ -9,7 +9,7 @@ for(i = 0; i < max; i += 3) { device_t dev; unsigned where; - unsigned long reg; + unsigned long reg = 0; #if RES_DEBUG prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]); #endif @@ -58,7 +58,7 @@ { device_t dev; unsigned where; - unsigned long reg; + unsigned long reg = 0; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff; if (register_values[i+2]) @@ -71,7 +71,7 @@ case RES_PORT_IO_8: // io 8 { unsigned where; - unsigned reg; + unsigned reg = 0; where = register_values[i+1] + offset_io_base; if (register_values[i+2]) reg = inb(where); @@ -83,7 +83,7 @@ case RES_PORT_IO_32: //io32 { unsigned where; - unsigned long reg; + unsigned long reg = 0; where = register_values[i+1] + offset_io_base; if (register_values[i+2]) reg = inl(where); @@ -116,80 +116,10 @@ #endif } -#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) -static void setup_resource_map_x(const unsigned int *register_values, int max) +static inline void setup_resource_map_x(const unsigned int *register_values, int max) { - int i; - -#if RES_DEBUG - printk(BIOS_DEBUG, "setting up resource map ex....\n"); -#endif - - for(i = 0; i < max; i += 4) { -#if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", - i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); -#endif - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - device_t dev; - unsigned where; - unsigned long reg; - dev = register_values[i+1] & ~0xfff; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - unsigned where; - unsigned reg; - where = register_values[i+1]; - reg = inb(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - } - break; - case RES_PORT_IO_32: //io32 - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = inl(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - } - break; -#if 0 - case RES_MEM_IO: //mem - { - unsigned where; - unsigned long reg; - where = register_values[i+1]; - reg = read32(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - write32( where, reg); - } - break; -#endif - - } // switch - - - } - -#if RES_DEBUG - printk(BIOS_DEBUG, "done.\n"); -#endif + setup_resource_map_x_offset(register_values, max, 0, 0); } -#endif #if 0 static void setup_io_resource_map(const unsigned int *register_values, int max) From svn at coreboot.org Tue Jul 6 23:51:36 2010 From: svn at coreboot.org (repository service) Date: Tue, 06 Jul 2010 23:51:36 +0200 Subject: [coreboot] build service results for r5654 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5654 to the coreboot repository. This caused the following changes: Change Log: Select HAVE_OPTION_TABLE for msi/ms9652_fam10. It fixes the build and doesn't change the behavior, since it is disabled by default. Signed-off-by: Myles Watson Acked-by: Myles Watson Build Log: Compilation of msi:ms9652_fam10 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From wangqingpei at gmail.com Wed Jul 7 02:05:49 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Wed, 7 Jul 2010 08:05:49 +0800 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <20100706173034.24990.qmail@stuge.se> References: <20100706173034.24990.qmail@stuge.se> Message-ID: hi peter, there used to have too bios chips, but i remove the B_BIOS, just leave the M_BIOS which means the main bios . I am pretty interested with your method. Is that useful for the other Gigabyte mainboards like my 785GMT-UD2H On Wed, Jul 7, 2010 at 1:30 AM, Peter Stuge wrote: > Hi, > > Qing Pei Wang wrote: > > i faced a problem about Gigabyte dual bios mainboard. my SF100 > > programmer can not detect the spi chip unless i removed it from > > the mainboard, > .. > > Is there any idea about this? it's pretty strange about these dual > > bios things. > > Any suggestion will be welcome for me. > > Please see > http://www.mail-archive.com/coreboot at coreboot.org/msg23613.html > http://www.mail-archive.com/linuxbios at linuxbios.org/msg05929.html > > And there's info about this as implemented on the GA-M57SLI-S4 board > on http://stuge.se/m57sli/ > > Do you have two flash chips populated, or only a single one? > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- Wang Qing Pei MSN:wangqingpei at hotmail.com Gmail:wangqingpei at gmail.com Phone:86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Wed Jul 7 02:40:56 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Wed, 7 Jul 2010 08:40:56 +0800 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: <20100706173034.24990.qmail@stuge.se> Message-ID: i saw teh method from http://stuge.se/m57sli/ . i have some questions: 1. U9: Populate flash chip. 2. R509: Remove. (I can not find the from your pic m57sli_soic_detail_labels.jpg ) 3. R89,R130: Populate 0402 100k resistors. how can i know which register i should move for my own board? On Wed, Jul 7, 2010 at 8:05 AM, Qing Pei Wang wrote: > hi peter, > there used to have too bios chips, but i remove the B_BIOS, just leave the > M_BIOS which means the main bios . > I am pretty interested with your method. Is that useful for the other > Gigabyte mainboards like my 785GMT-UD2H > > > On Wed, Jul 7, 2010 at 1:30 AM, Peter Stuge wrote: > >> Hi, >> >> Qing Pei Wang wrote: >> > i faced a problem about Gigabyte dual bios mainboard. my SF100 >> > programmer can not detect the spi chip unless i removed it from >> > the mainboard, >> .. >> > Is there any idea about this? it's pretty strange about these dual >> > bios things. >> > Any suggestion will be welcome for me. >> >> Please see >> http://www.mail-archive.com/coreboot at coreboot.org/msg23613.html >> http://www.mail-archive.com/linuxbios at linuxbios.org/msg05929.html >> >> And there's info about this as implemented on the GA-M57SLI-S4 board >> on http://stuge.se/m57sli/ >> >> Do you have two flash chips populated, or only a single one? >> >> >> //Peter >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > Wang Qing Pei > MSN:wangqingpei at hotmail.com > Gmail:wangqingpei at gmail.com > Phone:86+13426369984 > -- Wang Qing Pei MSN:wangqingpei at hotmail.com Gmail:wangqingpei at gmail.com Phone:86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From bari at onelabs.com Wed Jul 7 04:33:14 2010 From: bari at onelabs.com (bari) Date: Tue, 06 Jul 2010 21:33:14 -0500 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: <20100706173034.24990.qmail@stuge.se> Message-ID: <4C33E76A.6030603@onelabs.com> The Gigabyte 785GMT-UD2H has a fully functional dual SPI flash bios circuit. Peter's circuit is for boards that leave out one SPI flash device and you if wish to use a toggle switch to choose between the SPI flash device you wish to boot from. The Gigabyte 785GMT-UD2H has everything already soldered in place. You just need to use the patch for ITE it8720/18 dual bios that Vadim Girlin wrote, or something very similar. It worked for him on his Gigabyte GA-MA770-UD3 AMD 770 (RX780 / SB700) with ITE IT8718/20. -Bari Qing Pei Wang wrote: > i saw teh method from http://stuge.se/m57sli/ . > i have some questions: > > 1. U9: Populate flash chip. > 2. R509: Remove. (I can not find the from your pic m57sli_soic_detail_labels.jpg ) > > 3. R89,R130: Populate 0402 100k resistors. > > how can i know which register i should move for my own board? > On Wed, Jul 7, 2010 at 8:05 AM, Qing Pei Wang > wrote: > > hi peter, > there used to have too bios chips, but i remove the B_BIOS, just > leave the M_BIOS which means the main bios . > I am pretty interested with your method. Is that useful for the > other Gigabyte mainboards like my 785GMT-UD2H > > > On Wed, Jul 7, 2010 at 1:30 AM, Peter Stuge > wrote: > > Hi, > > Qing Pei Wang wrote: > > i faced a problem about Gigabyte dual bios mainboard. my SF100 > > programmer can not detect the spi chip unless i removed it from > > the mainboard, > .. > > Is there any idea about this? it's pretty strange about these > dual > > bios things. > > Any suggestion will be welcome for me. > > Please see > http://www.mail-archive.com/coreboot at coreboot.org/msg23613.html > http://www.mail-archive.com/linuxbios at linuxbios.org/msg05929.html > > And there's info about this as implemented on the GA-M57SLI-S4 board > on http://stuge.se/m57sli/ > > Do you have two flash chips populated, or only a single one? > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > > -- > Wang Qing Pei > MSN:wangqingpei at hotmail.com > Gmail:wangqingpei at gmail.com > Phone:86+13426369984 > > > > > -- > Wang Qing Pei > MSN:wangqingpei at hotmail.com > Gmail:wangqingpei at gmail.com > Phone:86+13426369984 > From hagigatali at gmail.com Wed Jul 7 06:42:42 2010 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 7 Jul 2010 09:12:42 +0430 Subject: [coreboot] 3 questions about coreboot Message-ID: My chipset is Intel Core2Due/945/ICH7. I have 3 questions. First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS. Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)? I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller? Second question: What is the code flow of Coreboot? Where does it start? and how it contines? Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Wed Jul 7 11:46:41 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 11:46:41 +0200 Subject: [coreboot] 3 questions about coreboot In-Reply-To: References: Message-ID: <4C344D01.8010200@coresystems.de> On 7/7/10 6:42 AM, ali hagigat wrote: > My chipset is Intel Core2Due/945/ICH7. > > I have 3 questions. > > First question: > I wonder how PCI memory read cycles can read an instruction from > F000:FFF0 right after reset which is the first instruction of BIOS. x86 CPUs are designed like that. Go read the Intel?64 and IA-32 Architectures Software Developer's Manuals: http://www.intel.com/products/processor/manuals/ > Does Coreboot writes into PCI configuration space of Device 31 of > ICH7-south bridge(LPC controller)? before initializing the > configuration space of Device 0 of 82945(which is memory controller)? What do you mean by "initializing the configuration space of Device 0 of 82945" ? Generally, a lot of work happens before RAM is initialized. Go read the source code for further details. > I mean the hardware immediately accesses BIOS chip after reset but at > some point all memory read/write cycles are claimed by 945 and memory > controller? No, that assumption is not true. > Second question: > What is the code flow of Coreboot? Where does > it start? and how it contines? It starts with the reset vector, which is in the "bootblock". That bootblock loads further modules. > Third question: > Inside src/mainboard/kontron/986lcd- > m/acpi we have some asl files. > What language they have been written in? Like superio.asl The language is called ACPI Control Message Source Language (short: ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and http://acpica.org/documentation/ Stefan From hagigatali at gmail.com Wed Jul 7 12:44:46 2010 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 7 Jul 2010 15:14:46 +0430 Subject: [coreboot] 3 questions about coreboot In-Reply-To: <4C344D01.8010200@coresystems.de> References: <4C344D01.8010200@coresystems.de> Message-ID: Stefan, BIOS chip is not connected to CPU directly after reset!! It is connected to the south bridge and it is on the PCI bus. When CPU gets ready to read from F000:FFF0, this request travels to BIOS chip. > I mean the hardware immediately accesses BIOS chip after reset but at > > some point all memory read/write cycles are claimed by 945 and memory > > controller? > > No, that assumption is not true. > If not so what happens? CPU does not have address/data buses directly attached to the BIOS chip. Thank you to answer the questions. On Wed, Jul 7, 2010 at 2:16 PM, Stefan Reinauer < stefan.reinauer at coresystems.de> wrote: > On 7/7/10 6:42 AM, ali hagigat wrote: > > My chipset is Intel Core2Due/945/ICH7. > > > > I have 3 questions. > > > > First question: > > I wonder how PCI memory read cycles can read an instruction from > > F000:FFF0 right after reset which is the first instruction of BIOS. > x86 CPUs are designed like that. Go read the Intel?64 and IA-32 > Architectures Software Developer's Manuals: > http://www.intel.com/products/processor/manuals/ > > > Does Coreboot writes into PCI configuration space of Device 31 of > > ICH7-south bridge(LPC controller)? before initializing the > > configuration space of Device 0 of 82945(which is memory controller)? > What do you mean by "initializing the configuration space of Device 0 of > 82945" ? > > Generally, a lot of work happens before RAM is initialized. Go read the > source code for further details. > > > I mean the hardware immediately accesses BIOS chip after reset but at > > some point all memory read/write cycles are claimed by 945 and memory > > controller? > No, that assumption is not true. > > > Second question: > > What is the code flow of Coreboot? Where does > > it start? and how it contines? > It starts with the reset vector, which is in the "bootblock". That > bootblock loads further modules. > > > > Third question: > > Inside src/mainboard/kontron/986lcd- > > m/acpi we have some asl files. > > What language they have been written in? Like superio.asl > > The language is called ACPI Control Message Source Language (short: > ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and > http://acpica.org/documentation/ > > > Stefan > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Wed Jul 7 13:19:15 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 13:19:15 +0200 Subject: [coreboot] 3 questions about coreboot In-Reply-To: References: <4C344D01.8010200@coresystems.de> Message-ID: <4C3462B3.2030001@coresystems.de> On 7/7/10 12:44 PM, ali hagigat wrote: > Stefan, > > BIOS chip is not connected to CPU directly after reset!! It's never connected directly, anyways, but through some kind of bridge. Usually the southbridge. > > I mean the hardware immediately accesses BIOS chip after reset > but at > > some point all memory read/write cycles are claimed by 945 and > memory > > controller? > > No, that assumption is not true. > > > If not so what happens? CPU does not have address/data buses directly > attached to the BIOS chip. The address cycles are claimed by whatever components live in any given address space. Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Wed Jul 7 13:23:54 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 13:23:54 +0200 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> Message-ID: <4C3463CA.1070402@coresystems.de> On 7/6/10 11:05 PM, Myles Watson wrote: > On Wed, Jun 30, 2010 at 11:52 AM, Edwin Beasant > wrote: >> Seems best of all worlds to me :-) >> Can we get an ack and a commit? > Rev 5653. > > Thanks, > Myles > Not sure why there were no errors, but: 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No such file or directory -------------- next part -------------- An HTML attachment was scrubbed... URL: From hagigatali at gmail.com Wed Jul 7 13:04:36 2010 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 7 Jul 2010 15:34:36 +0430 Subject: [coreboot] Position Independent Code Message-ID: Is Coreboot source code is a position independent code? I mean, will it be executed from any arbitrary location of the main memory? Can it be revoked and correctly executed by a bootloader like Grub if I make a binary image of it and make necessary changes to be read by Grub? -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Wed Jul 7 13:41:52 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 13:41:52 +0200 Subject: [coreboot] Position Independent Code In-Reply-To: References: Message-ID: <4C346800.9010706@coresystems.de> On 7/7/10 1:04 PM, ali hagigat wrote: > Is Coreboot source code is a position independent code? I mean, will > it be executed from any arbitrary location of the main memory? Most of it, no. > > Can it be revoked and correctly executed by a bootloader like Grub if > I make a binary image of it and make necessary changes to be read by Grub? It does not make sense to load coreboot from grub. You'd rather load Grub from coreboot. Stefan From anders at jenbo.dk Wed Jul 7 15:47:16 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Wed, 07 Jul 2010 15:47:16 +0200 Subject: [coreboot] =?utf-8?q?Position_Independent_Code?= Message-ID: If you want to do this to test out an image before flashing it, I think that you will run in to some issues since a lot of the stuff that coreboot performs will already have been done and so could fail or misbehave. Mvh Anders ----- Reply message ----- Fra: "Stefan Reinauer" Dato: ons., jul. 7, 2010 13:41 Emne: [coreboot] Position Independent Code Til: On 7/7/10 1:04 PM, ali hagigat wrote: > Is Coreboot source code is a position independent code? I mean, will > it be executed from any arbitrary location of the main memory? Most of it, no. > > Can it be revoked and correctly executed by a bootloader like Grub if > I make a binary image of it and make necessary changes to be read by Grub? It does not make sense to load coreboot from grub. You'd rather load Grub from coreboot. Stefan -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From stepan at coresystems.de Wed Jul 7 15:54:18 2010 From: stepan at coresystems.de (Stefan Reinauer) Date: Wed, 7 Jul 2010 15:54:18 +0200 Subject: [coreboot] Position Independent Code Message-ID: <20100707135418.GA10048@coresystems.de> * anders at jenbo.dk [100707 15:47]: > If you want to do this to test out an image before flashing it, I think that > you will run in to some issues since a lot of the stuff that coreboot performs > will already have been done and so could fail or misbehave. Yes. Testing a BIOS image in GRUB will not give you any reliable results. If you want to test payloads or some such, look at simnow or qemu. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From mylesgw at gmail.com Wed Jul 7 16:24:14 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 7 Jul 2010 08:24:14 -0600 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: <4C3463CA.1070402@coresystems.de> References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> <4C3463CA.1070402@coresystems.de> Message-ID: > Rev 5653. > > Thanks, > Myles > > Not sure why there were no errors, but: > > 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No > such file or directory That's odd. I don't see that warning. Does it have to do with parallel compilation and insufficient dependency checking? Which boards have the warning? Thanks, Myles From mylesgw at gmail.com Wed Jul 7 16:56:49 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 7 Jul 2010 08:56:49 -0600 Subject: [coreboot] [PATCH] warnings Message-ID: Kill a few more warnings. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: warnings.diff Type: text/x-diff Size: 6732 bytes Desc: not available URL: From stefan.reinauer at coresystems.de Wed Jul 7 17:03:31 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 17:03:31 +0200 Subject: [coreboot] [PATCH] warnings In-Reply-To: References: Message-ID: <4C349743.6010606@coresystems.de> On 7/7/10 4:56 PM, Myles Watson wrote: > Kill a few more warnings. > > Signed-off-by: Myles Watson > > Thanks, > Myles > Acked-by: Stefan Reinauer -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Wed Jul 7 17:09:10 2010 From: svn at coreboot.org (repository service) Date: Wed, 07 Jul 2010 17:09:10 +0200 Subject: [coreboot] [commit] r5656 - in trunk/src: mainboard/intel/d810e2cb mainboard/kontron/986lcd-m northbridge/intel/i82810 southbridge/intel/i82801bx Message-ID: Author: myles Date: Wed Jul 7 17:09:09 2010 New Revision: 5656 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5656 Log: Kill a few more warnings. Signed-off-by: Myles Watson Acked-by: Stefan Reinauer Modified: trunk/src/mainboard/intel/d810e2cb/Kconfig trunk/src/mainboard/kontron/986lcd-m/mptable.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Modified: trunk/src/mainboard/intel/d810e2cb/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/Kconfig Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/mainboard/intel/d810e2cb/Kconfig Wed Jul 7 17:09:09 2010 (r5656) @@ -25,6 +25,8 @@ select SOUTHBRIDGE_INTEL_I82801BX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE + select HAVE_HARD_RESET + select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES Modified: trunk/src/mainboard/kontron/986lcd-m/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mptable.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/mainboard/kontron/986lcd-m/mptable.c Wed Jul 7 17:09:09 2010 (r5656) @@ -32,7 +32,6 @@ static const char productid[12] = "986LCD-M "; struct mp_config_table *mc; struct device *riser = NULL, *firewire = NULL; - int i; int firewire_bus = 0, riser_bus = 0, isa_bus; int ioapic_id; Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/northbridge/intel/i82810/raminit.c Wed Jul 7 17:09:09 2010 (r5656) @@ -365,7 +365,7 @@ static void sdram_set_registers(void) { u8 reg8; - u16 reg16, did; + u16 did; did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Jul 7 17:09:09 2010 (r5656) @@ -65,17 +65,3 @@ { return do_smbus_read_byte(device, address); } - -static void smbus_write_byte(unsigned device, unsigned address, - unsigned char val) -{ - print_err("Unimplemented smbus_write_byte() called\n"); - return; -} - -static inline int smbus_write_block(unsigned device, unsigned length, - unsigned cmd, unsigned data1, - unsigned data2) -{ - return do_smbus_write_block(device, length, cmd, data1, data2); -} Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Jul 7 17:09:09 2010 (r5656) @@ -72,7 +72,7 @@ * specific IRQ values in your mainboards Config.lb. */ -void i82801bx_enable_apic(struct device *dev) +static void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -106,7 +106,7 @@ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } -void i82801bx_enable_serial_irqs(struct device *dev) +static void i82801bx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -211,7 +211,7 @@ pci_write_config8(dev, GPIO_CNTL, 0x10); } -void i82801bx_rtc_init(struct device *dev) +static void i82801bx_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -231,7 +231,7 @@ pci_write_config8(dev, RTC_CONF, 0x04); } -void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c Wed Jul 7 17:09:09 2010 (r5656) @@ -19,6 +19,7 @@ */ #include +#include void hard_reset(void) { Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Jul 7 17:09:09 2010 (r5656) @@ -110,74 +110,3 @@ return byte; } -/* This function is neither used nor tested by me (Corey Osgood), the author -(Yinghai) probably tested/used it on i82801er */ -static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ -#warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\n"); -#if 0 - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - unsigned char stat; - int i; - - /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return -2; - } - - /* Setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for (stat = 0; (stat & 0x40) == 0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* Clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* Set the command address */ - outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - - /* Set the block length */ - outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Try sending out the first byte of data here */ - byte = (data1 >> (0)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - /* Issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for (i = 0; i < length; i++) { - - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { - return -3; - } - - /* Load the next byte */ - if (i > 3) - byte = (data2 >> (i % 4)) & 0x0ff; - else - byte = (data1 >> (i)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - - /* Clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -#endif -} Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Wed Jul 7 17:09:09 2010 (r5656) @@ -22,6 +22,7 @@ #include #include #include +#include /* TODO: I'm fairly sure the same functionality is provided elsewhere. */ From mylesgw at gmail.com Wed Jul 7 17:10:38 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 7 Jul 2010 09:10:38 -0600 Subject: [coreboot] [PATCH] warnings In-Reply-To: <4C349743.6010606@coresystems.de> References: <4C349743.6010606@coresystems.de> Message-ID: > > Kill a few more warnings. > > > > Signed-off-by: Myles Watson > > > > Thanks, > > Myles > > > Acked-by: Stefan Reinauer Rev 5656. Thanks, Myles From stefan.reinauer at coresystems.de Wed Jul 7 17:46:24 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Wed, 07 Jul 2010 17:46:24 +0200 Subject: [coreboot] [PATCH] warnings -> errors Message-ID: <4C34A150.7040308@coresystems.de> Hi, I suggest applying the following patch to encourage folks to get their warnings fixed and cleaned up. Stefan -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: coreboot-warnings.diff URL: From caibaiyin.pku at gmail.com Wed Jul 7 17:27:10 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Wed, 7 Jul 2010 23:27:10 +0800 Subject: [coreboot] mconf of libpayload Message-ID: hi, as what you mentioned yesterday, i tried to make to use Makefile to load the libpayload kconfig instead of using "source" command. I can successfully load libpayload's config by modifying some code of the /util/kconfig/Makefile but the only problem left now is that i can not make them saved in separate files. There is a env variable "KCONFIG_CONFIG" which is used to indicate the file to save the configuration. i can make it work in the main frame of Makefile by "export KCONFIG_CONFIG=lib.config" but it can not work while i put this command under the rules. which looks like > memuconfig: > $(Q)export KCONFIG_CONFIG=.config > libpayload: > $(Q)export KCONFIG_CONFIG=lib.config > in this case i can not change this variable. Is there any suggestion about this? i cc this mail to the coreboot list, there may some one known this problem. -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Wed Jul 7 19:25:34 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 7 Jul 2010 19:25:34 +0200 Subject: [coreboot] 3 questions about coreboot In-Reply-To: References: <4C344D01.8010200@coresystems.de> Message-ID: <20100707172534.7831.qmail@stuge.se> ali hagigat wrote: > BIOS chip is not connected to CPU directly after reset!! See http://stuge.se/pc2010.png for a sketch of the components in a contemporary PC. The boot flash is very far away from the CPU. > When CPU gets ready to read from F000:FFF0, this request travels to > BIOS chip. Yes. It works because all components along the way are hardwired to decode accesses to the flash chip when they come out of reset. //Peter From svn at coreboot.org Wed Jul 7 19:51:42 2010 From: svn at coreboot.org (repository service) Date: Wed, 07 Jul 2010 19:51:42 +0200 Subject: [coreboot] [commit] r5657 - trunk/src/northbridge/via/vx800 Message-ID: Author: stepan Date: Wed Jul 7 19:51:41 2010 New Revision: 5657 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5657 Log: fix some warnings. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/northbridge/via/vx800/pci_rawops.h trunk/src/northbridge/via/vx800/vx800.h trunk/src/northbridge/via/vx800/vx800_early_serial.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c Modified: trunk/src/northbridge/via/vx800/pci_rawops.h ============================================================================== --- trunk/src/northbridge/via/vx800/pci_rawops.h Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/pci_rawops.h Wed Jul 7 19:51:41 2010 (r5657) @@ -43,30 +43,6 @@ pci_write_config8(dev, where, data); } -static void pci_modify_config16(device_t dev, unsigned where, u16 orval, u16 mask) -{ - u16 data = pci_read_config16(dev, where); - data &= (~mask); - data |= orval; - pci_write_config16(dev, where, data); -} - -static void pci_modify_config32(device_t dev, unsigned where, u32 orval, u32 mask) -{ - u32 data = pci_read_config32(dev, where); - data &= (~mask); - data |= orval; - pci_write_config32(dev, where, data); -} - -static void io_modify_config8(u16 where, u8 orval, u8 mask) -{ - u8 data = inb(where); - data &= (~mask); - data |= orval; - outb(data, where); -} - static void via_pci_inittable(u8 chipversion, const struct VIA_PCI_REG_INIT_TABLE *initdata) { Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800.h Wed Jul 7 19:51:41 2010 (r5657) @@ -26,6 +26,17 @@ { } #endif + +#ifdef __PRE_RAM__ +/* vx800_early_smbus.c */ +struct mem_controller; +void enable_smbus(void); +void smbus_fixup(const struct mem_controller *mem_ctrl); + +/* vx800_early_serial.c */ +void enable_vx800_serial(void); +#endif + //#define REV_B0 0x10 #define REV_B1 0x11 //#define REV_B2 0x12 Modified: trunk/src/northbridge/via/vx800/vx800_early_serial.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_serial.c Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800_early_serial.c Wed Jul 7 19:51:41 2010 (r5657) @@ -27,12 +27,6 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vx800_writesuper(uint8_t reg, uint8_t val) -{ - outb(reg, SIO_BASE); - outb(val, SIO_DATA); -} - static void vx800_writepnpaddr(uint8_t val) { outb(val, 0x2e); @@ -59,7 +53,7 @@ mainboard */ -static void enable_vx800_serial(void) +void enable_vx800_serial(void) { outb(6, 0x80); outb(0x03, 0x22); Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Jul 7 19:51:41 2010 (r5657) @@ -19,6 +19,7 @@ #include #include "vx800.h" + #define SMBUS_IO_BASE 0x0500 //from award bios #define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here @@ -137,14 +138,11 @@ return val; } -static void enable_smbus(void) +void enable_smbus(void) { device_t dev; - dev = - pci_locate_device(PCI_ID - (PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), - 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) { /* This won't display text if enable_smbus() is before serial init */ @@ -183,7 +181,7 @@ * * @param mem_ctrl The memory controller and SMBus addresses. */ -static void smbus_fixup(const struct mem_controller *mem_ctrl) +void smbus_fixup(const struct mem_controller *mem_ctrl) { int i, ram_slots, current_slot = 0; u8 result = 0; From marcj303 at gmail.com Wed Jul 7 20:11:28 2010 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 7 Jul 2010 12:11:28 -0600 Subject: [coreboot] mconf of libpayload In-Reply-To: References: Message-ID: Hi Bai Yin, I don't think that the export at that level won't work since rules are executed in a new shell. Maybe just copy the resulting .config file after the kconfig. Marc On Wed, Jul 7, 2010 at 9:27 AM, baiyin cai wrote: > hi, > ? as what you mentioned yesterday, i tried to make to use Makefile to load > the libpayload kconfig instead of using > "source" command. > I can successfully load libpayload's config by modifying some code of the > /util/kconfig/Makefile > but the only problem left now is that i can not make them saved in separate > files. > There is a env variable "KCONFIG_CONFIG" which is used to indicate the file > to save the configuration. > i can make it work in the main frame of Makefile by > "export KCONFIG_CONFIG=lib.config" > but it can not work while i put this command under the rules. which looks > like >> >> memuconfig: >> ? ? ? $(Q)export KCONFIG_CONFIG=.config >> >> libpayload: >> ? ? ? $(Q)export KCONFIG_CONFIG=lib.config > > > ? in this case i can not change this variable. Is there any suggestion about > this? > i cc this mail to the coreboot list, there may some one known this problem. > -- http://se-eng.com From r.ozgur.doruk at gmail.com Wed Jul 7 19:37:29 2010 From: r.ozgur.doruk at gmail.com (r. ozgur doruk) Date: Wed, 7 Jul 2010 20:37:29 +0300 Subject: [coreboot] SIS645DX and SIS962 Message-ID: Hi folks, does anyone have the datasheets and related technical documents of SIS645DX and SIS962 chipset. Or at least the technical documents concerning the chipset SIS761 and SIS966 which are the member of the chipsets supported by coreboot. Thanx for all, Ozgur -------------- next part -------------- An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Wed Jul 7 20:28:14 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 7 Jul 2010 12:28:14 -0600 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> <4C3463CA.1070402@coresystems.de> Message-ID: On Wed, Jul 7, 2010 at 8:24 AM, Myles Watson wrote: >> Rev 5653. >> >> Thanks, >> Myles >> >> Not sure why there were no errors, but: >> >> ? ? ? 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No >> such file or directory > > That's odd. ?I don't see that warning. ?Does it have to do with > parallel compilation and insufficient dependency checking? ?Which > boards have the warning? http://qa.coreboot.org/log_buildbrd.php?revision=5657&device=dbm690t&vendor=amd&num=2 option_table.h doesn't get generated until way down the list (after the warnings) It looks like the first board that needs this: HOSTCC coreboot-builds/sharedutils/options/build_opt_tbl And the rest of the build doesn't wait for it. Thanks, Myles From joe at settoplinux.org Wed Jul 7 23:34:37 2010 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 07 Jul 2010 17:34:37 -0400 Subject: [coreboot] [PATCH] warnings In-Reply-To: References: <4C349743.6010606@coresystems.de> Message-ID: <4C34F2ED.1020502@settoplinux.org> On 07/07/2010 11:10 AM, Myles Watson wrote: >>> Kill a few more warnings. >>> >>> Signed-off-by: Myles Watson >>> >>> Thanks, >>> Myles >>> >> Acked-by: Stefan Reinauer > Rev 5656. > Ah, thanks Myles, I actually had alot of those changes already in my ICH2 Overhaul coming soon. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Wed Jul 7 23:59:07 2010 From: svn at coreboot.org (repository service) Date: Wed, 07 Jul 2010 23:59:07 +0200 Subject: [coreboot] [commit] r5658 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdk8 southbridge/amd/rs780 southbridge/amd/sb600 southbridge/amd/sb700 Message-ID: Author: stepan Date: Wed Jul 7 23:59:06 2010 New Revision: 5658 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5658 Log: fix some more warnings Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/include/cpu/amd/multicore.h trunk/src/northbridge/amd/amdk8/amdk8.h trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/amd/rs780/rs780_gfx.c trunk/src/southbridge/amd/sb600/sb600_smbus.c trunk/src/southbridge/amd/sb600/sb600_smbus.h trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/amd/sb700/sb700_smbus.c trunk/src/southbridge/amd/sb700/sb700_smbus.h Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -244,7 +244,7 @@ } } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -178,12 +178,12 @@ } } -static void wait_all_aps_started(u32 bsp_apicid) +void wait_all_aps_started(u32 bsp_apicid) { for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0); } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658) @@ -38,6 +38,9 @@ struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); +#else +void wait_all_other_cores_started(u32 bsp_apicid); +void wait_all_aps_started(u32 bsp_apicid); #endif #endif /* CPU_AMD_QUADCORE_H */ Modified: trunk/src/northbridge/amd/amdk8/amdk8.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 23:59:06 2010 (r5658) @@ -8,8 +8,9 @@ #include "amdk8_pre_f.h" #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); #endif #endif /* AMDK8_H */ Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 23:59:06 2010 (r5658) @@ -1,6 +1,6 @@ #ifndef AMDK8_F_H - #define AMDK8_F_H + /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 Modified: trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 23:59:06 2010 (r5658) @@ -1,5 +1,4 @@ #ifndef AMDK8_PRE_F_H - #define AMDK8_PRE_F_H /* Definitions of various K8 registers */ Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 23:59:06 2010 (r5658) @@ -206,12 +206,12 @@ print_spew(" done.\n"); } +#if CONFIG_MAX_PHYSICAL_CPUS > 1 static void fill_row(u8 node, u8 row, u32 value) { pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); } -#if CONFIG_MAX_PHYSICAL_CPUS > 1 static u8 link_to_register(int ldt) { /* @@ -447,28 +447,33 @@ } #if CROSS_BAR_47_56 -static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { +static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) +{ uint32_t val; val = get_row(source, dest); val -= link_connection(source, kickout)<<16; fill_row(source, dest, val); } -static void opt_broadcast_rt_group(const u8 *conn, int num) { +static void opt_broadcast_rt_group(const u8 *conn, int num) +{ int i; for(i=0; i 2 -static int optimize_connection_group(const u8 *opt_conn, int num) { +static int optimize_connection_group(const u8 *opt_conn, int num) +{ int needs_reset = 0; int i; for(i=0; i> 22; wrmsr(TOP_MEM, msr); } +#endif static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { @@ -1802,6 +1804,7 @@ } +#if CONFIG_MEM_TRAIN_SEQ == 1 static unsigned get_htic_bit(unsigned i, unsigned bit) { uint32_t dword; @@ -1816,6 +1819,7 @@ if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(unsigned val) { Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658) @@ -1,6 +1,8 @@ +#include "amdk8.h" + #define RES_DEBUG 0 -static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) { int i; #if RES_DEBUG Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 23:59:06 2010 (r5658) @@ -96,33 +96,33 @@ MMIORANGE MMIO[8], CreativeMMIO[8]; +#define CIM_STATUS u32 +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 +#define CIM_DISABLEPORT 0x80000002 + +#define MMIO_ATTRIB_NP_ONLY 1 +#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 +#define MMIO_ATTRIB_SKIP_ZERO 1<<2 + +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) - { + for (i=0; i<8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } return 0; } + static void FreeMMIO(MMIORANGE* pMMIO) { pMMIO->Base = 0; pMMIO->Limit = 0; } -#define CIM_STATUS u32 -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 -#define CIM_DISABLEPORT 0x80000002 - -#define MMIO_ATTRIB_NP_ONLY 1 -#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 -#define MMIO_ATTRIB_SKIP_ZERO 1<<2 - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; @@ -584,7 +584,6 @@ { u32 l_dword; int i; - device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; @@ -617,7 +616,7 @@ /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -632,7 +631,7 @@ #if (CONFIG_GFXUMA == 1) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -60,7 +60,7 @@ return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -87,8 +87,7 @@ return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, - u8 val) +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 23:59:06 2010 (r5658) @@ -20,8 +20,6 @@ #ifndef SB600_SMBUS_H #define SB600_SMBUS_H -//#include - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 @@ -58,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 23:59:06 2010 (r5658) @@ -49,4 +49,9 @@ void sb700_enable(device_t dev); +#ifdef __PRE_RAM__ +void sb700_lpc_port80(void); +void sb700_pci_port80(void); +#endif + #endif /* SB700_H */ Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 23:59:06 2010 (r5658) @@ -231,7 +231,7 @@ outb(0x06, 0x0cf9); } -static void sb700_pci_port80(void) +void sb700_pci_port80(void) { u8 byte; device_t dev; @@ -276,7 +276,7 @@ pci_write_config8(dev, 0x4A, byte); } -static void sb700_lpc_port80(void) +void sb700_lpc_port80(void) { u8 byte; device_t dev; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -63,7 +63,7 @@ return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -90,7 +90,7 @@ return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 23:59:06 2010 (r5658) @@ -56,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); From stefan.reinauer at coresystems.de Thu Jul 8 00:02:13 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 08 Jul 2010 00:02:13 +0200 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> <4C3463CA.1070402@coresystems.de> Message-ID: <4C34F965.8060907@coresystems.de> On 7/7/10 8:28 PM, Myles Watson wrote: > On Wed, Jul 7, 2010 at 8:24 AM, Myles Watson wrote: >>> Rev 5653. >>> >>> Thanks, >>> Myles >>> >>> Not sure why there were no errors, but: >>> >>> 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No >>> such file or directory >> That's odd. I don't see that warning. Does it have to do with >> parallel compilation and insufficient dependency checking? Which >> boards have the warning? > http://qa.coreboot.org/log_buildbrd.php?revision=5657&device=dbm690t&vendor=amd&num=2 > > option_table.h doesn't get generated until way down the list (after > the warnings) It looks like the first board that needs this: > > HOSTCC coreboot-builds/sharedutils/options/build_opt_tbl > > And the rest of the build doesn't wait for it. This sure looks like a race... question is, what do we do about it? Force an early build of option_table.h outside of the normal dependency system? Why does gcc only print a warning instead of an error here? Are those #includes not needed at all? Stefan From mylesgw at gmail.com Thu Jul 8 00:17:29 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 7 Jul 2010 16:17:29 -0600 Subject: [coreboot] PATCH: Fix CMOS Tables support for all boards. In-Reply-To: <4C34F965.8060907@coresystems.de> References: <95EC52016CC5DE4896FD95FA7323A4DB153016C742@mr-burns.exchange.virtensys.com> <354E6168-76AB-4342-8FE5-62119BF67FB5@virtensys.com> <4C3463CA.1070402@coresystems.de> <4C34F965.8060907@coresystems.de> Message-ID: On Wed, Jul 7, 2010 at 4:02 PM, Stefan Reinauer wrote: > ?On 7/7/10 8:28 PM, Myles Watson wrote: >> On Wed, Jul 7, 2010 at 8:24 AM, Myles Watson wrote: >>>> Rev 5653. >>>> >>>> Thanks, >>>> Myles >>>> >>>> Not sure why there were no errors, but: >>>> >>>> ? ? ? 9 src/include/pc80/mc146818rtc.h:89:26: warning: option_table.h: No >>>> such file or directory >>> That's odd. ?I don't see that warning. ?Does it have to do with >>> parallel compilation and insufficient dependency checking? ?Which >>> boards have the warning? >> http://qa.coreboot.org/log_buildbrd.php?revision=5657&device=dbm690t&vendor=amd&num=2 >> >> option_table.h doesn't get generated until way down the list (after >> the warnings) ?It looks like the first board that needs this: >> >> ?HOSTCC ? ? coreboot-builds/sharedutils/options/build_opt_tbl >> >> And the rest of the build doesn't wait for it. > > This sure looks like a race... question is, what do we do about it? > Force an early build of option_table.h outside of the normal dependency > system? I don't know what the best fix is. The problem is the building of the tool, so abuild could just build the tool before building any boards. We could also create option_table.h as part of the configure process. > Why does gcc only print a warning instead of an error here? Are those > #includes not needed at all? USE_OPTION_TABLE defaults to false. HAVE_OPTION_TABLE triggers the #include so that the options get defined. If you select USE_OPTION_TABLE and create the race condition, gcc will error out. Steps to exercise the race condition for the curious: rm -rf build make oldconfig make -j4 Thanks, Myles From svn at coreboot.org Thu Jul 8 02:37:23 2010 From: svn at coreboot.org (repository service) Date: Thu, 08 Jul 2010 02:37:23 +0200 Subject: [coreboot] [commit] r5659 - in trunk/src: cpu/amd/dualcore cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore include/cpu/amd northbridge/amd/amdfam10 northbridge/amd/amdmct/mct northbridge/amd/amdmct/wra... Message-ID: Author: stepan Date: Thu Jul 8 02:37:23 2010 New Revision: 5659 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5659 Log: get rid of even more fam10 and k8 warnings. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Deleted: trunk/src/northbridge/amd/amdmct/mct/mct_fd.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/include/cpu/amd/multicore.h trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c trunk/src/northbridge/amd/amdfam10/setup_resource_map.c trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c trunk/src/southbridge/amd/amd8111/amd8111.h trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -14,7 +14,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -252,12 +252,11 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { /* Called by the BSP to indicate AP can stop */ - /* FIXME Do APs use this? - Looks like wait_till_sysinfo_in_ram is used instead. */ + /* FIXME Do APs use this? */ // allow aps to stop use 6 bits for state lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); @@ -395,15 +394,11 @@ } #endif - /* AP is ready, Wait for the BSP to get memory configured */ - /* FIXME: many cores spinning on node0 pci register seems to be bad. - * Why do we need to wait? These APs are just going to go sit in a hlt. - */ - //wait_till_sysinfo_in_ram(); - + /* AP is ready, configure MTRRs and go to sleep */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); + printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid); @@ -912,6 +907,7 @@ printk(BIOS_DEBUG, " done\n"); } +#ifdef UNUSED_CODE static void cpuInitializeMCA(void) { /* Clears Machine Check Architecture (MCA) registers, which power on @@ -939,6 +935,7 @@ } } } +#endif /** * finalize_node_setup() Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -191,7 +191,7 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { // allow aps to stop Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -32,7 +32,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static u32 get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,10 +67,12 @@ return id; } +#ifdef UNUSED_CODE static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } +#endif static struct node_core_id get_node_core_id_x(void) { Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/include/cpu/amd/multicore.h Thu Jul 8 02:37:23 2010 (r5659) @@ -41,6 +41,8 @@ #else void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); #endif +u32 get_initial_apicid(void); #endif /* CPU_AMD_QUADCORE_H */ Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Jul 8 02:37:23 2010 (r5659) @@ -1169,8 +1169,16 @@ #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); + +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x(const u32 *register_values, u32 max); #endif #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Jul 8 02:37:23 2010 (r5659) @@ -111,8 +111,6 @@ //#include "../amdmct/mct/mctardk5.c" #endif -#include "../amdmct/mct/mct_fd.c" - #endif /* DDR2 */ int mctRead_SPD(u32 smaddr, u32 reg) Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Thu Jul 8 02:37:23 2010 (r5659) @@ -28,7 +28,7 @@ pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); } - +#ifdef UNUSED_CODE static u32 get_htic_bit(u8 i, u8 bit) { u32 dword; @@ -47,6 +47,7 @@ if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(u32 val) { Modified: trunk/src/northbridge/amd/amdfam10/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Thu Jul 8 02:37:23 2010 (r5659) @@ -41,9 +41,7 @@ } -static void setup_resource_map_offset(const u32 *register_values, - u32 max, u32 offset_pci_dev, - u32 offset_io_base) +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; // print_debug("setting up resource map offset...."); @@ -66,8 +64,7 @@ #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 -static void setup_resource_map_x_offset(const u32 *register_values, u32 max, - u32 offset_pci_dev, u32 offset_io_base) +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; @@ -133,7 +130,8 @@ print_debug("done.\n"); #endif } -static void setup_resource_map_x(const u32 *register_values, u32 max) + +void setup_resource_map_x(const u32 *register_values, u32 max) { u32 i; Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Thu Jul 8 02:37:23 2010 (r5659) @@ -538,7 +538,6 @@ void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -unsigned amd_FD_support(void); void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -375,7 +375,7 @@ *enabled = 0; } - +#ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { u32 tmp; @@ -387,6 +387,7 @@ } return 0; } +#endif void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Thu Jul 8 02:37:23 2010 (r5659) @@ -70,13 +70,12 @@ return MaxValue; } - - +#ifdef UNUSED_CODE static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) { return (val_1p & 0xff) + ((val_2p & 0xff)<<8); } - +#endif u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -337,6 +337,7 @@ static void coreDelay (void); +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -398,6 +399,7 @@ coreDelay(); } +#endif static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Modified: trunk/src/southbridge/amd/amd8111/amd8111.h ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111.h Thu Jul 8 02:37:23 2010 (r5659) @@ -5,4 +5,8 @@ void amd8111_enable(device_t dev); +#ifdef __PRE_RAM__ +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + #endif /* AMD8111_H */ Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Thu Jul 8 02:37:23 2010 (r5659) @@ -1,3 +1,4 @@ +#include "amd8111.h" #include /* by yhlu 2005.10 */ @@ -45,7 +46,7 @@ outb(0x0e, 0x0cf9); // make sure cf9 is enabled } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { device_t dev; From fengyuning1984 at gmail.com Thu Jul 8 07:28:36 2010 From: fengyuning1984 at gmail.com (FENG Yu Ning) Date: Thu, 8 Jul 2010 13:28:36 +0800 Subject: [coreboot] 3 questions about coreboot In-Reply-To: <20100707172534.7831.qmail@stuge.se> References: <4C344D01.8010200@coresystems.de> <20100707172534.7831.qmail@stuge.se> Message-ID: Peter Stuge wrote: > See http://stuge.se/pc2010.png for a sketch of the components in a > contemporary PC. Great drawing, Peter. ali, I would like to add some detail. The picture mentioned by Peter show an architecture that is closer to the AMD ones, in which memory controller is integrated into the CPU. The 945 architecture has memory controller in the northbridge. The bridge chips have logic deciding if the coming address access should be responsed by it, or should be routed to somewhere else. As in 945, when an address comes from CPU, the northbridge decides whether the address access means a memory access, a configuration to the chip itself, or to other devices that connects to it. In the case of first instruction address, the northbridge will pass that request to southbridge. Read the chipset manual for more information. Some effort is is needed to extract what you want from the text. By the way, since my knowledge is still of the single core age and I know little about architectures other than Intel x86, my explanation may not be accurate. I think someone in the list will correct me if that was the case. yn From svn at coreboot.org Thu Jul 8 18:41:05 2010 From: svn at coreboot.org (repository service) Date: Thu, 08 Jul 2010 18:41:05 +0200 Subject: [coreboot] [commit] r5660 - in trunk/src: . cpu/amd/car cpu/amd/dualcore cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore include/cpu/amd mainboard/asus/m2v-mx_se mainboard/gigabyte/ga_2761gxdk mainboar... Message-ID: Author: stepan Date: Thu Jul 8 18:41:05 2010 New Revision: 5660 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5660 Log: Fix all warnings in the tree (does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer Signed-off-by: Myles Watson Acked-by: Stefan Reinauer Modified: trunk/src/Kconfig trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/include/cpu/amd/multicore.h trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c trunk/src/northbridge/amd/amdfam10/amdfam10_pci.c trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdfam10/reset_test.c trunk/src/northbridge/amd/amdk8/amdk8.h trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit.h trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c trunk/src/northbridge/intel/i3100/i3100.h trunk/src/northbridge/intel/i3100/reset_test.c trunk/src/southbridge/broadcom/bcm5785/bcm5785.h trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c trunk/src/southbridge/sis/sis966/sis966_early_smbus.c trunk/src/southbridge/sis/sis966/sis966_smbus.h trunk/src/southbridge/via/k8t890/k8t890_early_car.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/Kconfig Thu Jul 8 18:41:05 2010 (r5660) @@ -722,7 +722,7 @@ config WARNINGS_ARE_ERRORS bool - default n + default y config ID_SECTION_OFFSET hex Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Jul 8 18:41:05 2010 (r5660) @@ -37,16 +37,16 @@ #include #include /* - XMM map: - xmm1: cpu family - xmm2: fam10 comparison value - xmm3: backup ebx -*/ + * XMM map: + * xmm1: cpu family + * xmm2: fam10 comparison value + * xmm3: backup ebx + */ /* Save the BIST result */ movl %eax, %ebp - /*for normal part %ebx already contain cpu_init_detected from fallback call */ + /* for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: post_code(0xa0) @@ -113,7 +113,8 @@ CAR_FAM10_out: /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - Re-enable it in after RAM is initialized and before CAR is disabled */ + * Re-enable it in after RAM is initialized and before CAR is disabled + */ movl $0xc001102a, %ecx rdmsr bts $15, %eax Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c Thu Jul 8 18:41:05 2010 (r5660) @@ -47,7 +47,7 @@ return (cpuid_ecx(0x80000008) & 0xff); } -static inline struct node_core_id get_node_core_id_x(void) +struct node_core_id get_node_core_id_x(void) { return get_node_core_id(read_nb_cfg_54()); // for pre_e0() nb_cfg_54 always be 0 Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Jul 8 18:41:05 2010 (r5660) @@ -417,7 +417,7 @@ return htic; } -static void wait_all_core0_started(void) +void wait_all_core0_started(void) { /* When core0 is started, it will distingush_cpu_resets * So wait for that to finish */ Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Jul 8 18:41:05 2010 (r5660) @@ -326,7 +326,7 @@ return htic; } -static void wait_all_core0_started(void) +void wait_all_core0_started(void) { /* When core0 is started, it will distingush_cpu_resets * So wait for that to finish */ Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c Thu Jul 8 18:41:05 2010 (r5660) @@ -74,7 +74,7 @@ } #endif -static struct node_core_id get_node_core_id_x(void) +struct node_core_id get_node_core_id_x(void) { return get_node_core_id(read_nb_cfg_54()); } Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/include/cpu/amd/multicore.h Thu Jul 8 18:41:05 2010 (r5660) @@ -32,6 +32,7 @@ #if defined(__GNUC__) // it can be used to get unitid and coreid it running only struct node_core_id get_node_core_id(u32 nb_cfg_54); +struct node_core_id get_node_core_id_x(void); #endif #if !defined(__PRE_RAM__) @@ -39,6 +40,7 @@ u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); #else +void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Jul 8 18:41:05 2010 (r5660) @@ -57,7 +57,6 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "northbridge/amd/amdk8/early_ht.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Jul 8 18:41:05 2010 (r5660) @@ -123,9 +123,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include "southbridge/sis/sis966/sis966_early_setup_ss.h" -#include "southbridge/sis/sis966/sis966_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Jul 8 18:41:05 2010 (r5660) @@ -30,10 +30,11 @@ //used by raminit #define QRANK_DIMM_SUPPORT 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 +// used by init_cpus and fidvid (disabled until someone tests this) +// #define SET_FIDVID 1 +#define SET_FIDVID 0 +// if we want to wait for core1 done before DQS training, set it to 0 +// #define SET_FIDVID_CORE0_ONLY 1 #include #include @@ -121,7 +122,8 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" +// Disabled until it's actually used: +// #include "cpu/amd/model_fxx/fidvid.c" #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Jul 8 18:41:05 2010 (r5660) @@ -1179,6 +1179,14 @@ offset_pci_dev, u32 offset_io_base); void setup_resource_map_x(const u32 *register_values, u32 max); + +/* reset_test.c */ +u32 cpu_init_detected(u8 nodeid); +u32 bios_reset_detected(void); +u32 cold_reset_detected(void); +u32 other_reset_detected(void); +u32 get_sblk(void); +u8 get_sbbusn(u8 sblk); #endif #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Thu Jul 8 18:41:05 2010 (r5660) @@ -61,6 +61,7 @@ return d; } +#if CONFIG_AMDMCT == 0 static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; @@ -117,8 +118,9 @@ pci_write_config32(dev, 0x124, d.mask>>8); } +#endif - +#if CONFIG_AMDMCT == 0 static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; @@ -152,7 +154,6 @@ return sel_m; } -#if CONFIG_AMDMCT == 0 #ifdef UNUSED_CODE static void set_DctSelHiEn(u32 i, u32 val) { @@ -234,6 +235,7 @@ return one_DCT; } + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 // See that other copy in northbridge.c static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) @@ -574,7 +576,7 @@ } #endif - +#ifdef UNUSED_CODE static void re_set_all_config_map_reg(u32 nodes, u32 segbit, sys_info_conf_t *sysinfo) { @@ -616,7 +618,7 @@ } } - +#endif static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) { @@ -660,7 +662,7 @@ } - +#ifdef UNUSED_CODE static void set_BusSegmentEn(u32 node, u32 segbit) { #if CONFIG_PCI_BUS_SEGN_BITS @@ -679,6 +681,7 @@ pci_write_config32(dev, 0x68, dword); #endif } +#endif #if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_pci.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_pci.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_pci.c Thu Jul 8 18:41:05 2010 (r5660) @@ -32,6 +32,7 @@ return dword; } +#ifdef UNUSED_CODE static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data) { @@ -40,6 +41,7 @@ pci_write_config32(dev, index_reg + 0x4, data); } +#endif static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) { @@ -55,6 +57,7 @@ return dword; } +#ifdef UNUSED_CODE static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data) { @@ -69,5 +72,6 @@ } #endif +#endif Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Jul 8 18:41:05 2010 (r5660) @@ -17,12 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ static void print_tx(const char *strval, u32 val) { #if CONFIG_DEBUG_RAM_SETUP printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } +#endif static void print_t(const char *strval) { Modified: trunk/src/northbridge/amd/amdfam10/reset_test.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/reset_test.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdfam10/reset_test.c Thu Jul 8 18:41:05 2010 (r5660) @@ -29,7 +29,7 @@ /* mmconf is not ready */ /* io_ext is not ready */ -static u32 cpu_init_detected(u8 nodeid) +u32 cpu_init_detected(u8 nodeid) { u32 htic; device_t dev; @@ -40,7 +40,7 @@ return !!(htic & HTIC_INIT_Detect); } -static u32 bios_reset_detected(void) +u32 bios_reset_detected(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -48,7 +48,7 @@ return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } -static u32 cold_reset_detected(void) +u32 cold_reset_detected(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -56,7 +56,7 @@ return !(htic & HTIC_ColdR_Detect); } -static u32 other_reset_detected(void) // other warm reset not started by BIOS +u32 other_reset_detected(void) // other warm reset not started by BIOS { u32 htic; htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); @@ -154,7 +154,7 @@ return 0; } -static u32 get_sblk(void) +u32 get_sblk(void) { u32 reg; /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ @@ -163,7 +163,7 @@ } -static u8 get_sbbusn(u8 sblk) +u8 get_sbbusn(u8 sblk) { return node_link_to_bus(0, sblk); } Modified: trunk/src/northbridge/amd/amdk8/amdk8.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdk8/amdk8.h Thu Jul 8 18:41:05 2010 (r5660) @@ -11,6 +11,7 @@ #ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif #endif /* AMDK8_H */ Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Thu Jul 8 18:41:05 2010 (r5660) @@ -576,7 +576,7 @@ return reset_needed; } -#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) +#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) { uint32_t dword; Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdk8/raminit.c Thu Jul 8 18:41:05 2010 (r5660) @@ -19,7 +19,7 @@ #define QRANK_DIMM_SUPPORT 0 #endif -static void setup_resource_map(const unsigned int *register_values, int max) +void setup_resource_map(const unsigned int *register_values, int max) { int i; // printk(BIOS_DEBUG, "setting up resource map...."); @@ -2346,7 +2346,7 @@ { } -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { int i; Modified: trunk/src/northbridge/amd/amdk8/raminit.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdk8/raminit.h Thu Jul 8 18:41:05 2010 (r5660) @@ -13,6 +13,7 @@ struct sys_info; void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); +void setup_resource_map(const unsigned int *register_values, int max); #if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Jul 8 18:41:05 2010 (r5660) @@ -74,7 +74,7 @@ */ -static void setup_resource_map(const unsigned int *register_values, int max) +void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { @@ -3206,7 +3206,7 @@ } -static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr) { int i; Modified: trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c Thu Jul 8 18:41:05 2010 (r5660) @@ -22,7 +22,9 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); +#ifdef UNUSED_CODE static u32 GetScrubAddr_D(u32 Node); +#endif static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); @@ -249,7 +251,7 @@ } } - +#ifdef UNUSED_CODE static u32 GetScrubAddr_D(u32 Node) { /* Get the current 40-bit Scrub ADDR address, scaled to 32-bits, @@ -280,7 +282,7 @@ return val; /* ScrubAddr[39:8] */ } - +#endif static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Jul 8 18:41:05 2010 (r5660) @@ -313,7 +313,8 @@ } } - +#ifdef UNUSED_CODE +/* Callback not required */ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) { u8 skip = 0; @@ -323,7 +324,7 @@ return skip; } - +#endif static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 DQSDelay, Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Jul 8 18:41:05 2010 (r5660) @@ -19,6 +19,7 @@ /* Call-backs */ #include + static u16 mctGet_NVbits(u8 index) { u16 val = 0; @@ -411,6 +412,7 @@ #endif } +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val) { if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) { @@ -420,6 +422,7 @@ } return val; } +#endif static void mctHookAfterAnyTraining(void) { @@ -430,8 +433,9 @@ return mctGetLogicalCPUID(node); } +#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */ static u8 mctSetNodeBoundary_D(void) { return 0; } - +#endif Modified: trunk/src/northbridge/intel/i3100/i3100.h ============================================================================== --- trunk/src/northbridge/intel/i3100/i3100.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/intel/i3100/i3100.h Thu Jul 8 18:41:05 2010 (r5660) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __I3100_H__ +#define __I3100_H__ + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -60,3 +63,10 @@ /* DRC */ #define DRC_NOECC_MODE (0 << 20) #define DRC_72BIT_ECC (1 << 20) + + +#ifdef __GNUC__ +int bios_reset_detected(void); +#endif + +#endif Modified: trunk/src/northbridge/intel/i3100/reset_test.c ============================================================================== --- trunk/src/northbridge/intel/i3100/reset_test.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/northbridge/intel/i3100/reset_test.c Thu Jul 8 18:41:05 2010 (r5660) @@ -6,7 +6,7 @@ /* To see if I have already booted I check to see if memory * has been enabled. */ -static int bios_reset_detected(void) +int bios_reset_detected(void) { uint32_t dword; Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785.h ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785.h Thu Jul 8 18:41:05 2010 (r5660) @@ -3,6 +3,13 @@ #include "chip.h" +#ifndef __PRE_RAM__ void bcm5785_enable(device_t dev); +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + +void ldtstop_sb(void); +unsigned get_sbdn(unsigned bus); #endif /* BCM5785_H */ Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Thu Jul 8 18:41:05 2010 (r5660) @@ -4,6 +4,7 @@ */ #include +#include "bcm5785.h" #include "bcm5785_enable_rom.c" static void bcm5785_enable_lpc(void) @@ -53,12 +54,12 @@ pci_write_config8(dev, 0x40, (1<<2)); } -static unsigned get_sbdn(unsigned bus) +unsigned get_sbdn(unsigned bus) { device_t dev; /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. + * There can only be one bcm5785 on a hypertransport chain/bus. */ dev = pci_locate_device_on_bus( PCI_ID(0x1166, 0x0036), @@ -70,7 +71,7 @@ #define SB_VFSMAF 0 -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { //ACPI Decode Enable outb(0x0e, 0xcd6); @@ -89,7 +90,7 @@ outb(9, 0xcd7); } -static void ldtstop_sb(void) +void ldtstop_sb(void) { outb(1, 0x2060); } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Thu Jul 8 18:41:05 2010 (r5660) @@ -113,8 +113,6 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { - unsigned char global_control_register; - unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Thu Jul 8 18:41:05 2010 (r5660) @@ -51,6 +51,7 @@ return loops ? 0 : -1; } +#ifdef UNUNSED_CODE static int smbus_wait_until_blk_done(void) { unsigned loops = SMBUS_TIMEOUT; @@ -63,6 +64,7 @@ } while ((byte & (1 << 7)) == 0); return loops ? 0 : -1; } +#endif static int do_smbus_read_byte(unsigned device, unsigned address) { @@ -110,3 +112,69 @@ return byte; } +#ifdef UNUNSED_CODE +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ + unsigned char byte; + unsigned char stat; + int i; + + print_err("Untested smbus_write_block called\n"); + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\n"); + return 0; +} +#endif Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Thu Jul 8 18:41:05 2010 (r5660) @@ -24,6 +24,9 @@ #include "chip.h" +#ifndef __PRE_RAM__ void mcp55_enable(device_t dev); - +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif #endif /* MCP55_H */ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c Thu Jul 8 18:41:05 2010 (r5660) @@ -20,6 +20,7 @@ */ #include +#include "mcp55.h" static unsigned get_sbdn(unsigned bus) { @@ -52,7 +53,7 @@ outb(0x0e, 0x0cf9); } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { /* default value for mcp55 is good */ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ Modified: trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/sis/sis966/sis966_early_setup_car.c Thu Jul 8 18:41:05 2010 (r5660) @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) +void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl; uint32_t pll_ctrl; Modified: trunk/src/southbridge/sis/sis966/sis966_early_smbus.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_early_smbus.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/sis/sis966/sis966_early_smbus.c Thu Jul 8 18:41:05 2010 (r5660) @@ -23,6 +23,174 @@ #define SMBUS0_IO_BASE 0x8D0 +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; + } + outb(val,smbus_io_base + SMBHSTSTAT); + } while(--loops); + return -2; +} + +int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(smbus_io_base + 0x00); + if ( (val & 0xff) != 0x02) { + return 0; + } + } while(--loops); + return -3; +} + +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + unsigned char global_status_register; + unsigned char byte; + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} + +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + +static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + outb(0xff, smbus_io_base + 0x00); + smbus_delay(); + outb(0x20, smbus_io_base + 0x03); + smbus_delay(); + + outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); + smbus_delay(); + outb(address & 0xff, smbus_io_base + 0x05); + smbus_delay(); + outb(0x12, smbus_io_base + 0x03); + smbus_delay(); + +int i,j; +for(i=0;i<0x1000;i++) +{ + if (inb(smbus_io_base + 0x00) != 0x08) + { smbus_delay(); + for(j=0;j<0xFFFF;j++); + } +}; + + global_status_register = inb(smbus_io_base + 0x00); + byte = inb(smbus_io_base + 0x08); + + if (global_status_register != 0x08) { // lose check, otherwise it should be 0 + print_debug("Fail");print_debug("\r\t"); + return -1; + } + print_debug("Success");print_debug("\r\t"); + return byte; +} + + +static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + + + static const uint8_t SiS_LPC_init[34][3]={ {0x04, 0xF8, 0x07}, //Reg 0x04 {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash @@ -564,11 +732,11 @@ printk(BIOS_DEBUG, "enable_smbus <--------\n"); } -static int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } Modified: trunk/src/southbridge/sis/sis966/sis966_smbus.h ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_smbus.h Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/sis/sis966/sis966_smbus.h Thu Jul 8 18:41:05 2010 (r5660) @@ -37,166 +37,10 @@ */ #define SMBUS_TIMEOUT (100*1000*10) -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { - return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); - return -2; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(smbus_io_base + 0x00); - if ( (val & 0xff) != 0x02) { - return 0; - } - } while(--loops); - return -3; -} -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - outb(0xff, smbus_io_base + 0x00); - smbus_delay(); - outb(0x20, smbus_io_base + 0x03); - smbus_delay(); - - outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); - smbus_delay(); - outb(address & 0xff, smbus_io_base + 0x05); - smbus_delay(); - outb(0x12, smbus_io_base + 0x03); - smbus_delay(); - -int i,j; -for(i=0;i<0x1000;i++) -{ - if (inb(smbus_io_base + 0x00) != 0x08) - { smbus_delay(); - for(j=0;j<0xFFFF;j++); - } -}; - - global_status_register = inb(smbus_io_base + 0x00); - byte = inb(smbus_io_base + 0x08); - - if (global_status_register != 0x08) { // lose check, otherwise it should be 0 - print_debug("Fail");print_debug("\r\t"); - return -1; - } - print_debug("Success");print_debug("\r\t"); - return byte; -} - - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} +int smbus_wait_until_ready(unsigned smbus_io_base); +int smbus_wait_until_done(unsigned smbus_io_base); +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device); +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val); +int smbus_read_byte(unsigned device, unsigned address); +int smbus_write_byte(unsigned device, unsigned address, unsigned char val); Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_early_car.c Thu Jul 8 02:37:23 2010 (r5659) +++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c Thu Jul 8 18:41:05 2010 (r5660) @@ -113,7 +113,7 @@ return 1; } -static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); @@ -134,7 +134,7 @@ return nvram_pos; } -static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { switch (size) { case 1: From svn at coreboot.org Thu Jul 8 19:00:25 2010 From: svn at coreboot.org (repository service) Date: Thu, 08 Jul 2010 19:00:25 +0200 Subject: [coreboot] build service results for r5660 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5660 to the coreboot repository. This caused the following changes: Change Log: Fix all warnings in the tree (does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer Signed-off-by: Myles Watson Acked-by: Stefan Reinauer Build Log: Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5660&device=dbm690t&vendor=amd&num=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From svn at coreboot.org Thu Jul 8 19:20:07 2010 From: svn at coreboot.org (repository service) Date: Thu, 08 Jul 2010 19:20:07 +0200 Subject: [coreboot] [commit] r5661 - trunk/src/mainboard/amd/dbm690t Message-ID: Author: myles Date: Thu Jul 8 19:20:07 2010 New Revision: 5661 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5661 Log: Ugly temporary fix until we figure out how to deal with the race condition. Justification: - dbm690t isn't actively developed (no new warnings will be introduced) - having this board fail clutters the mailing list Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/mainboard/amd/dbm690t/Kconfig Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Thu Jul 8 18:41:05 2010 (r5660) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Thu Jul 8 19:20:07 2010 (r5661) @@ -30,6 +30,13 @@ default n depends on BOARD_AMD_DBM690T +# This is a temporary fix, and should be removed when the race condition for +# building option_table.h is fixed. +config WARNINGS_ARE_ERRORS + bool + default n + depends on BOARD_AMD_DBM690T + config DCACHE_RAM_BASE hex default 0xc8000 From svn at coreboot.org Thu Jul 8 19:38:15 2010 From: svn at coreboot.org (repository service) Date: Thu, 08 Jul 2010 19:38:15 +0200 Subject: [coreboot] build service results for r5661 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5661 to the coreboot repository. This caused the following changes: Change Log: Ugly temporary fix until we figure out how to deal with the race condition. Justification: - dbm690t isn't actively developed (no new warnings will be introduced) - having this board fail clutters the mailing list Signed-off-by: Myles Watson Acked-by: Myles Watson Build Log: Compilation of amd:dbm690t has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From mylesgw at gmail.com Thu Jul 8 19:50:11 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 8 Jul 2010 11:50:11 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback Message-ID: BOOTBLOCK_NORMAL allows the user to use CMOS values to select which image to boot. This patch: - makes BOOTBLOCK_NORMAL depend on USE_OPTION_TABLE - makes compilation of bootblock.inc depend on OPTION_TABLE_H - removes broken includes Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: normal.diff Type: text/x-diff Size: 1655 bytes Desc: not available URL: From patrick at georgi-clan.de Thu Jul 8 19:56:38 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Thu, 08 Jul 2010 19:56:38 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: Message-ID: <4C361156.4090304@georgi-clan.de> Am 08.07.2010 19:50, schrieb Myles Watson: > BOOTBLOCK_NORMAL allows the user to use CMOS values to select which > image to boot. This patch: > > - makes BOOTBLOCK_NORMAL depend on USE_OPTION_TABLE This would prevent the "old" scheme of building a fallback image (which is built first) with BOOTBLOCK_NORMAL and _no_ USE_OPTION_TABLE (so it uses the hardcoded defaults) and a normal image with USE_OPTION_TABLE. > - makes compilation of bootblock.inc depend on OPTION_TABLE_H How does this interact with BOOTBLOCK_SIMPLE builds without USE_OPTION_TABLE? Patrick From mylesgw at gmail.com Thu Jul 8 20:09:01 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 8 Jul 2010 12:09:01 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C361156.4090304@georgi-clan.de> References: <4C361156.4090304@georgi-clan.de> Message-ID: On Thu, Jul 8, 2010 at 11:56 AM, Patrick Georgi wrote: > Am 08.07.2010 19:50, schrieb Myles Watson: >> BOOTBLOCK_NORMAL allows the user to use CMOS values to select which >> image to boot. ?This patch: >> >> - makes BOOTBLOCK_NORMAL depend on USE_OPTION_TABLE > This would prevent the "old" scheme of building a fallback image (which > is built first) with BOOTBLOCK_NORMAL and _no_ USE_OPTION_TABLE (so it > uses the hardcoded defaults) and a normal image with USE_OPTION_TABLE. So I probably went too far. I should have made it depend on HAVE_OPTION_TABLE. >> - makes compilation of bootblock.inc depend on OPTION_TABLE_H > How does this interact with BOOTBLOCK_SIMPLE builds without > USE_OPTION_TABLE? It shouldn't make a difference. OPTION_TABLE_H is empty if there isn't one. Thanks, Myles From mylesgw at gmail.com Thu Jul 8 20:11:43 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 8 Jul 2010 12:11:43 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: <4C361156.4090304@georgi-clan.de> Message-ID: On Thu, Jul 8, 2010 at 12:09 PM, Myles Watson wrote: > On Thu, Jul 8, 2010 at 11:56 AM, Patrick Georgi wrote: >> Am 08.07.2010 19:50, schrieb Myles Watson: >>> BOOTBLOCK_NORMAL allows the user to use CMOS values to select which >>> image to boot. ?This patch: >>> >>> - makes BOOTBLOCK_NORMAL depend on USE_OPTION_TABLE >> This would prevent the "old" scheme of building a fallback image (which >> is built first) with BOOTBLOCK_NORMAL and _no_ USE_OPTION_TABLE (so it >> uses the hardcoded defaults) and a normal image with USE_OPTION_TABLE. > So I probably went too far. ?I should have made it depend on HAVE_OPTION_TABLE. I admit I've never used it. I just tried to build it to see if there were any warnings, and it wouldn't build. Maybe it would be better if you fixed it the right way. Thanks, Myles From hagigatali at gmail.com Fri Jul 9 09:07:51 2010 From: hagigatali at gmail.com (ali hagigat) Date: Thu, 8 Jul 2010 23:07:51 -0800 Subject: [coreboot] 3 questions about coreboot In-Reply-To: References: <4C344D01.8010200@coresystems.de> <20100707172534.7831.qmail@stuge.se> Message-ID: Ok, thank you all for the replies, links and diagrams. But there are still some ambiguities in memory read/write after reset which is done by BIOS chip and then the memory controller !! Immediately after reset all memory read/write cycles are claimed by BIOS chip ultimately. The first question is that: Is memory controller enabled after reset before writing to its configuration space? If it is enabled, how it does not claim for memory addresses after reset? If it is not enabled and we enable the memory controller by writing to its configuration registers how we introduce the memory address range used by BIOS chip here? Because the memory controller should not claim the memory address range of the BIOS chip. I had a general look at the configuration registers of the memory controller, there is no register or registers to set this range of address!! Besides there is no enable bit or something similar!! These questions are repeated for BIOS chip and the PCI device connected to it. Do we have to write to their configuration registers to specify a specific range of address? Otherwise both memory controller and the PCI device connected to the BIOS chip will claim for that address!! Because they are being situated at the same PCI bus. On 7/7/10, FENG Yu Ning wrote: > Peter Stuge wrote: >> See http://stuge.se/pc2010.png for a sketch of the components in a >> contemporary PC. > > Great drawing, Peter. > > ali, I would like to add some detail. > > The picture mentioned by Peter show an architecture that is closer to > the AMD ones, in which memory controller is integrated into the CPU. > > The 945 architecture has memory controller in the northbridge. > > The bridge chips have logic deciding if the coming address access > should be responsed by it, or should be routed to somewhere else. > As in 945, when an address comes from CPU, the northbridge > decides whether the address access means a memory access, > a configuration to the chip itself, or to other devices that connects > to it. In the case of first instruction address, the northbridge will > pass that request to southbridge. > > Read the chipset manual for more information. Some effort is > is needed to extract what you want from the text. > > By the way, since my knowledge is still of the single core age > and I know little about architectures other than Intel x86, my > explanation may not be accurate. I think someone in the list > will correct me if that was the case. > > yn > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From stefan.reinauer at coresystems.de Fri Jul 9 11:02:02 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 09 Jul 2010 11:02:02 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: <4C361156.4090304@georgi-clan.de> Message-ID: <4C36E58A.7070308@coresystems.de> On 7/8/10 8:09 PM, Myles Watson wrote: > On Thu, Jul 8, 2010 at 11:56 AM, Patrick Georgi wrote: >> Am 08.07.2010 19:50, schrieb Myles Watson: >>> BOOTBLOCK_NORMAL allows the user to use CMOS values to select which >>> image to boot. This patch: >>> >>> - makes BOOTBLOCK_NORMAL depend on USE_OPTION_TABLE >> This would prevent the "old" scheme of building a fallback image (which >> is built first) with BOOTBLOCK_NORMAL and _no_ USE_OPTION_TABLE (so it >> uses the hardcoded defaults) and a normal image with USE_OPTION_TABLE. > So I probably went too far. I should have made it depend on HAVE_OPTION_TABLE. Even though the normal/fallback mechanism uses CMOS, it does not require an option table. Are there advantages in changing this? Stefan From peter at stuge.se Fri Jul 9 15:10:14 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 9 Jul 2010 15:10:14 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C36E58A.7070308@coresystems.de> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> Message-ID: <20100709131014.1347.qmail@stuge.se> Stefan Reinauer wrote: > Even though the normal/fallback mechanism uses CMOS, it does not > require an option table. > Are there advantages in changing this? One advantage would be that any use of NVRAM always implies having an option table, which I think makes sense. Somewhere it needs to be specified what bit(s) the mechanism uses, better in an option table than hardcoded IMO. //Peter From mylesgw at gmail.com Fri Jul 9 15:36:16 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 07:36:16 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <20100709131014.1347.qmail@stuge.se> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> Message-ID: On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: > Stefan Reinauer wrote: >> Even though the normal/fallback mechanism uses CMOS, it does not >> require an option table. >> Are there advantages in changing this? > > One advantage would be that any use of NVRAM always implies having an > option table, which I think makes sense. Somewhere it needs to be > specified what bit(s) the mechanism uses, better in an option table > than hardcoded IMO. That was my thought. It should be obvious when we're using/corrupting values, to minimize surprises. Thanks, Myles From svn at coreboot.org Fri Jul 9 16:24:23 2010 From: svn at coreboot.org (repository service) Date: Fri, 09 Jul 2010 16:24:23 +0200 Subject: [coreboot] [commit] r5662 - trunk/src/arch/i386/init Message-ID: Author: myles Date: Fri Jul 9 16:24:23 2010 New Revision: 5662 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5662 Log: Trivial fix to make CONFIG_BOOTBLOCK_NORMAL switch compile again. Signed-off-by: Myles Watson Acked-by: Myles Watson Modified: trunk/src/arch/i386/init/bootblock_normal.c Modified: trunk/src/arch/i386/init/bootblock_normal.c ============================================================================== --- trunk/src/arch/i386/init/bootblock_normal.c Thu Jul 8 19:20:07 2010 (r5661) +++ trunk/src/arch/i386/init/bootblock_normal.c Fri Jul 9 16:24:23 2010 (r5662) @@ -1,7 +1,4 @@ #include - -#include -#include "arch/romcc_io.h" #include static void main(unsigned long bist) From stefan.reinauer at coresystems.de Fri Jul 9 17:55:21 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 09 Jul 2010 17:55:21 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> Message-ID: <4C374669.6040608@coresystems.de> On 7/9/10 3:36 PM, Myles Watson wrote: > On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: >> Stefan Reinauer wrote: >>> Even though the normal/fallback mechanism uses CMOS, it does not >>> require an option table. >>> Are there advantages in changing this? >> One advantage would be that any use of NVRAM always implies having an >> option table, which I think makes sense. Somewhere it needs to be >> specified what bit(s) the mechanism uses, better in an option table >> than hardcoded IMO. > That was my thought. It should be obvious when we're using/corrupting > values, to minimize surprises. the normal/fallback selection and the cmos settings are living in completely distinct spaces. normal/fallback is not covered by the checksum. So I don't think this applies here. At least not until we create this necessity. I think we want to be able to use CMOS options without normal / fallback and the other way round, so we need to be careful. Stefan From mylesgw at gmail.com Fri Jul 9 18:01:15 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 10:01:15 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C374669.6040608@coresystems.de> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> Message-ID: On Fri, Jul 9, 2010 at 9:55 AM, Stefan Reinauer wrote: > ?On 7/9/10 3:36 PM, Myles Watson wrote: >> On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: >>> Stefan Reinauer wrote: >>>> Even though the normal/fallback mechanism uses CMOS, it does not >>>> require an option table. >>>> Are there advantages in changing this? >>> One advantage would be that any use of NVRAM always implies having an >>> option table, which I think makes sense. Somewhere it needs to be >>> specified what bit(s) the mechanism uses, better in an option table >>> than hardcoded IMO. >> That was my thought. ?It should be obvious when we're using/corrupting >> values, to minimize surprises. > > the normal/fallback selection and the cmos settings are living in > completely distinct spaces. normal/fallback is not covered by the > checksum. Yes. It could still corrupt values used by the factory BIOS if you're trying to have them coexist. For testing, it can be nice to not have to do BIOS setup every time you boot the factory BIOS. > So I don't think this applies here. At least not until we > create this necessity. I think we want to be able to use CMOS options > without normal / fallback and the other way round, so we need to be careful. No problem. It compiles now, so I'm happy. Thanks, Myles From r.marek at assembler.cz Fri Jul 9 18:09:56 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 09 Jul 2010 18:09:56 +0200 Subject: [coreboot] [RFC] Network console for coreboot In-Reply-To: <4C228991.4040101@assembler.cz> References: <4C02BDA2.1030101@assembler.cz> <4C06CFD7.3010604@assembler.cz> <4C20790D.5030901@assembler.cz> <4C228991.4040101@assembler.cz> Message-ID: <4C3749D4.1080805@assembler.cz> Anyone can ack / test please? KTHXBYE Rudolf From Cristi.Magherusan at net.utcluj.ro Fri Jul 9 18:27:25 2010 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Fri, 09 Jul 2010 19:27:25 +0300 Subject: [coreboot] [RFC] Network console for coreboot In-Reply-To: <4C3749D4.1080805@assembler.cz> References: <4C02BDA2.1030101@assembler.cz> <4C06CFD7.3010604@assembler.cz> <4C20790D.5030901@assembler.cz> <4C228991.4040101@assembler.cz> <4C3749D4.1080805@assembler.cz> Message-ID: <1278692845.25117.5.camel@ufo> On Fri, 2010-07-09 at 18:09 +0200, Rudolf Marek wrote: > Anyone can ack / test please? > > KTHXBYE > > Rudolf > > Tested with my m2v-mx-se and TX is confirmed to work. Still, when using the qemu target it fails to compile, so I think we should also test it using abuild to see how many boards really compile with it enabled. Having these said, this great piece of engineering is Acked-by: Cristian Magherusan-Stanciu Regards, Cristi -- Cristi M?gheru?an, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From stefan.reinauer at coresystems.de Fri Jul 9 18:29:23 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 09 Jul 2010 18:29:23 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> Message-ID: <4C374E63.70001@coresystems.de> On 7/9/10 6:01 PM, Myles Watson wrote: > On Fri, Jul 9, 2010 at 9:55 AM, Stefan Reinauer > wrote: >> On 7/9/10 3:36 PM, Myles Watson wrote: >>> On Fri, Jul 9, 2010 at 7:10 AM, Peter Stuge wrote: >>>> Stefan Reinauer wrote: >>>>> Even though the normal/fallback mechanism uses CMOS, it does not >>>>> require an option table. >>>>> Are there advantages in changing this? >>>> One advantage would be that any use of NVRAM always implies having an >>>> option table, which I think makes sense. Somewhere it needs to be >>>> specified what bit(s) the mechanism uses, better in an option table >>>> than hardcoded IMO. >>> That was my thought. It should be obvious when we're using/corrupting >>> values, to minimize surprises. >> the normal/fallback selection and the cmos settings are living in >> completely distinct spaces. normal/fallback is not covered by the >> checksum. > Yes. It could still corrupt values used by the factory BIOS if you're > trying to have them coexist. For testing, it can be nice to not have > to do BIOS setup every time you boot the factory BIOS. 0. Maybe we should hard code the Normal / Fallback ("BOOT_BYTE") into the cmos.layout parser tool so anyone who tries to use that byte gets a decent error. 1. Should Fallback always ignore CMOS? I think it would make more sense if Normal and Fallback were the same and both would write a decent set of CMOS defaults in the case of a bad checksum. 2. Ok, so what should happen when bad settings are detected? 2.1 Go back to fallback (the same path like when the normal rom image is corrupted)? 2.1.1 leave BOOT_BYTE alone ...? 2.1.2 dump a set of cmos default values 2.2 Stay in Normal 2.2.1 leave BOOT_BYTE alone ...? 2.2.2 dump a set of cmos default values 3. Do we want an extra "checksum" for BOOT_BYTE? Stefan From mylesgw at gmail.com Fri Jul 9 18:46:59 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 10:46:59 -0600 Subject: [coreboot] [RFC] Network console for coreboot In-Reply-To: <1278692845.25117.5.camel@ufo> References: <4C02BDA2.1030101@assembler.cz> <4C06CFD7.3010604@assembler.cz> <4C20790D.5030901@assembler.cz> <4C228991.4040101@assembler.cz> <4C3749D4.1080805@assembler.cz> <1278692845.25117.5.camel@ufo> Message-ID: Before you commit, I have some suggestions: I don't think it should default to yes. +config CONSOLE_NE2K + bool "Network console over NE2000 compatible Ethernet adapter" + default y + help A little trivial white space cleanup before you commit. Warning: trailing whitespace in lines 70,104,110,113,240,243,244,246,255,257,330,342,344,418,420 of src/lib/ne2k.c Now that warnings are errors, it's time to add the timeout. +#warning "Add timeout" Thanks, Myles From mylesgw at gmail.com Fri Jul 9 19:02:33 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 11:02:33 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C374E63.70001@coresystems.de> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> <4C374E63.70001@coresystems.de> Message-ID: <9DC57C28DBF44B1B8DA1837529C2509B@chimp> > 0. Maybe we should hard code the Normal / Fallback ("BOOT_BYTE") into > the cmos.layout parser tool so anyone who tries to use that byte gets a > decent error. It seems more flexible to use the value from cmos.layout unless there isn't one, then hard code it. But I agree we don't want it to be part of the checksum. > 1. Should Fallback always ignore CMOS? I think it would make more sense > if Normal and Fallback were the same and both would write a decent set > of CMOS defaults in the case of a bad checksum. Agreed. The way we build each image separately now, you could have a different set of defaults for Normal and Fallback. > 2. Ok, so what should happen when bad settings are detected? > 2.1 Go back to fallback (the same path like when the normal rom image is > corrupted)? > 2.1.1 leave BOOT_BYTE alone ...? > 2.1.2 dump a set of cmos default values > 2.2 Stay in Normal > 2.2.1 leave BOOT_BYTE alone ...? > 2.2.2 dump a set of cmos default values Stay in Normal, set boot count to maximum, set CMOS to default. Then if it fails, fallback is tried next. I guess it would be nice to have fallback set CMOS to its default values if it gets selected because the boot count was too high. Booting fallback with normal's defaults doesn't seem wise. > 3. Do we want an extra "checksum" for BOOT_BYTE? Might be good. One byte seems cheap. Thanks, Myles From stefan.reinauer at coresystems.de Fri Jul 9 19:34:46 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 09 Jul 2010 19:34:46 +0200 Subject: [coreboot] [patch] libpayload standard headers Message-ID: <4C375DB6.8020205@coresystems.de> See patch -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: libpayload-stdhdrs.diff URL: From Cristi.Magherusan at net.utcluj.ro Fri Jul 9 19:55:23 2010 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Fri, 09 Jul 2010 20:55:23 +0300 Subject: [coreboot] [patch] trivial -Werror compilation fix for Asus M2V-MX-SE Message-ID: <1278698123.25117.12.camel@ufo> See attached patch: Signed-off-by: Cristi M -- Cristi M?gheru?an, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-trivial-Werror-compilation-fix-for-Asus-M2V-MX-SE.patch Type: text/x-patch Size: 852 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From svn at coreboot.org Fri Jul 9 20:06:23 2010 From: svn at coreboot.org (repository service) Date: Fri, 09 Jul 2010 20:06:23 +0200 Subject: [coreboot] [commit] r5663 - trunk/src/northbridge/amd/amdk8 Message-ID: Author: myles Date: Fri Jul 9 20:06:23 2010 New Revision: 5663 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5663 Log: Trivial -Werror fix. Signed-off-by: Cristi M Acked-by: Myles Watson Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Fri Jul 9 16:24:23 2010 (r5662) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Fri Jul 9 20:06:23 2010 (r5663) @@ -2410,7 +2410,7 @@ uint32_t reg; if ((val < TT_MIN) || (val > TT_MAX)) { - printk(BIOS_ERR, str); + printk(BIOS_ERR, "%s", str); die(" Unknown\n"); } From patrick at georgi-clan.de Fri Jul 9 20:10:39 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 09 Jul 2010 20:10:39 +0200 Subject: [coreboot] [patch] libpayload standard headers In-Reply-To: <4C375DB6.8020205@coresystems.de> References: <4C375DB6.8020205@coresystems.de> Message-ID: <4C37661F.7010808@georgi-clan.de> Am 09.07.2010 19:34, schrieb Stefan Reinauer: > See patch > Acked-by: Patrick Georgi From mylesgw at gmail.com Fri Jul 9 20:06:50 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 12:06:50 -0600 Subject: [coreboot] [patch] trivial -Werror compilation fix for Asus M2V-MX-SE In-Reply-To: <1278698123.25117.12.camel@ufo> References: <1278698123.25117.12.camel@ufo> Message-ID: On Fri, Jul 9, 2010 at 11:55 AM, Cristi Magherusan wrote: > > See attached patch: > > Signed-off-by: Cristi M Rev 5663. Thanks, Myles From peter at stuge.se Fri Jul 9 20:35:59 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 9 Jul 2010 20:35:59 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C374E63.70001@coresystems.de> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> <4C374E63.70001@coresystems.de> Message-ID: <20100709183559.18967.qmail@stuge.se> Stefan Reinauer wrote: > 1. Should Fallback always ignore CMOS? I think it would make more sense > if Normal and Fallback were the same and both would write a decent set > of CMOS defaults in the case of a bad checksum. NAK if this means that testing coreboot and later booting factory BIOS again will throw an error and lose/change the NVRAM contents. //Peter From stefan.reinauer at coresystems.de Fri Jul 9 20:50:13 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Fri, 09 Jul 2010 20:50:13 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <20100709183559.18967.qmail@stuge.se> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> <4C374E63.70001@coresystems.de> <20100709183559.18967.qmail@stuge.se> Message-ID: <4C376F65.1030504@coresystems.de> On 7/9/10 8:35 PM, Peter Stuge wrote: > Stefan Reinauer wrote: >> 1. Should Fallback always ignore CMOS? I think it would make more sense >> if Normal and Fallback were the same and both would write a decent set >> of CMOS defaults in the case of a bad checksum. > NAK if this means that testing coreboot and later booting factory > BIOS again will throw an error and lose/change the NVRAM contents. > I don't understand your concern. That's always the case in one way or another, unless you disable CMOS settings in coreboot completely. Are you saying that coreboot should not corrupt factory bios settings even if that is required to have settings in coreboot? It sounds if you need intelligence in that area, you're gonna get it with tools like nvramtool rather than generally cutting coreboot's feature set. In my scenarios a machine is never running vendor bioses again after coreboot is able to boot (that's the whole purpose of coreboot) Stefan From svn at coreboot.org Fri Jul 9 20:52:18 2010 From: svn at coreboot.org (repository service) Date: Fri, 09 Jul 2010 20:52:18 +0200 Subject: [coreboot] [commit] r5664 - in trunk/payloads/libpayload: curses include Message-ID: Author: stepan Date: Fri Jul 9 20:52:17 2010 New Revision: 5664 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5664 Log: become more standard with libpayload headers. PATH_MAX belongs in limits.h, tiny curses can use standard includes now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi Added: trunk/payloads/libpayload/include/limits.h Modified: trunk/payloads/libpayload/curses/local.h trunk/payloads/libpayload/include/curses.priv.h trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/include/stdio.h Modified: trunk/payloads/libpayload/curses/local.h ============================================================================== --- trunk/payloads/libpayload/curses/local.h Fri Jul 9 20:06:23 2010 (r5663) +++ trunk/payloads/libpayload/curses/local.h Fri Jul 9 20:52:17 2010 (r5664) @@ -46,6 +46,8 @@ #define NCURSES_NO_PADDING 0 #define USE_HARD_TABS 0 #define HAVE_FCNTL_H 0 +#define HAVE_LIMITS_H 1 +#define HAVE_UNISTD_H 1 #define USE_XMC_SUPPORT 0 #define NCURSES_EXPANDED 0 #define HAVE_GETCWD 0 Modified: trunk/payloads/libpayload/include/curses.priv.h ============================================================================== --- trunk/payloads/libpayload/include/curses.priv.h Fri Jul 9 20:06:23 2010 (r5663) +++ trunk/payloads/libpayload/include/curses.priv.h Fri Jul 9 20:52:17 2010 (r5664) @@ -46,9 +46,6 @@ #ifndef _CURSES_PRIV_H #define _CURSES_PRIV_H 1 -//// XXX -extern void *memset(void *s, int c, size_t len); - //// #include #ifdef __cplusplus @@ -63,38 +60,28 @@ #define MODULE_ID(id) /*nothing*/ #endif -//// #include -//// #include -//// #include -//// -//// #if HAVE_UNISTD_H -//// #include -//// #endif -//// +#include +#include +#include + +#if HAVE_UNISTD_H +#include +#endif + //// #if HAVE_SYS_BSDTYPES_H //// #include /* needed for ISC */ //// #endif -//// -//// #if HAVE_LIMITS_H -//// # include + +#if HAVE_LIMITS_H +# include //// #elif HAVE_SYS_PARAM_H //// # include -//// #endif +#endif //// //// #include -//// #include -//// -//// #include +#include -#ifndef PATH_MAX -# if defined(_POSIX_PATH_MAX) -# define PATH_MAX _POSIX_PATH_MAX -# elif defined(MAXPATHLEN) -# define PATH_MAX MAXPATHLEN -# else -# define PATH_MAX 255 /* the Posix minimum path-size */ -# endif -#endif +#include #if DECL_ERRNO extern int errno; Modified: trunk/payloads/libpayload/include/libpayload.h ============================================================================== --- trunk/payloads/libpayload/include/libpayload.h Fri Jul 9 20:06:23 2010 (r5663) +++ trunk/payloads/libpayload/include/libpayload.h Fri Jul 9 20:52:17 2010 (r5664) @@ -342,10 +342,6 @@ struct LFILE *lfopen(struct LAR *lar, const char *filename); int lfread(void *ptr, size_t size, size_t nmemb, struct LFILE *stream); -#define SEEK_SET 0 /**< The seek offset is absolute. */ -#define SEEK_CUR 1 /**< The seek offset is against the current position. */ -#define SEEK_END 2 /**< The seek offset is against the end of the file. */ - int lfseek(struct LFILE *stream, long offset, int whence); int lfclose(struct LFILE *file); /** @} */ Added: trunk/payloads/libpayload/include/limits.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/payloads/libpayload/include/limits.h Fri Jul 9 20:52:17 2010 (r5664) @@ -0,0 +1,43 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2010 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _LIMITS_H +#define _LIMITS_H + +#ifndef PATH_MAX +# if defined(_POSIX_PATH_MAX) +# define PATH_MAX _POSIX_PATH_MAX +# elif defined(MAXPATHLEN) +# define PATH_MAX MAXPATHLEN +# else +# define PATH_MAX 255 /* the Posix minimum path-size */ +# endif +#endif + +#endif Modified: trunk/payloads/libpayload/include/stdio.h ============================================================================== --- trunk/payloads/libpayload/include/stdio.h Fri Jul 9 20:06:23 2010 (r5663) +++ trunk/payloads/libpayload/include/stdio.h Fri Jul 9 20:52:17 2010 (r5664) @@ -43,4 +43,9 @@ void perror(const char *s); +#define SEEK_SET 0 /**< The seek offset is absolute. */ +#define SEEK_CUR 1 /**< The seek offset is against the current position. */ +#define SEEK_END 2 /**< The seek offset is against the end of the file. */ + + #endif From peter at stuge.se Fri Jul 9 21:11:22 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 9 Jul 2010 21:11:22 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <4C376F65.1030504@coresystems.de> References: <4C361156.4090304@georgi-clan.de> <4C36E58A.7070308@coresystems.de> <20100709131014.1347.qmail@stuge.se> <4C374669.6040608@coresystems.de> <4C374E63.70001@coresystems.de> <20100709183559.18967.qmail@stuge.se> <4C376F65.1030504@coresystems.de> Message-ID: <20100709191122.24834.qmail@stuge.se> Stefan Reinauer wrote: > >> if Normal and Fallback were the same and both would write a > >> decent set of CMOS defaults in the case of a bad checksum. > > NAK if this means that testing coreboot and later booting factory > > BIOS again will throw an error and lose/change the NVRAM contents. > > I don't understand your concern. .. > In my scenarios a machine is never running vendor bioses again > after coreboot is able to boot (that's the whole purpose of coreboot) And that's the good scenario that we all know and love. But remember that there are other scenarios up until that point. I think it's really bad for coreboot to trample NVRAM contents since it hurts the impression of coreboot when someone is evaluating coreboot for the very first time. > That's always the case in one way or another, unless you disable > CMOS settings in coreboot completely. This is another way to express what I think is important; a way to disable NVRAM options that guarantees that coreboot will never write to NVRAM. > Are you saying that coreboot should not corrupt factory bios settings > even if that is required to have settings in coreboot? It sounds if you > need intelligence in that area, you're gonna get it with tools like > nvramtool rather than generally cutting coreboot's feature set. I'm after a more sophisticated feature set in coreboot, I don't want to cut it down in any way. I totally understand that coreboot in some areas makes convenient assumptions that hold for some scenarios but breaks in others, and it may not be entirely trivial to support those "new" scenarios. //Peter From mylesgw at gmail.com Fri Jul 9 21:48:09 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 13:48:09 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <20100709191122.24834.qmail@stuge.se> References: <4C361156.4090304@georgi-clan.de><4C36E58A.7070308@coresystems.de><20100709131014.1347.qmail@stuge.se><4C374669.6040608@coresystems.de><4C374E63.70001@coresystems.de><20100709183559.18967.qmail@stuge.se><4C376F65.1030504@coresystems.de> <20100709191122.24834.qmail@stuge.se> Message-ID: > This is another way to express what I think is important; a way to > disable NVRAM options that guarantees that coreboot will never write > to NVRAM. It's implemented: Don't use fallback/normal & set USE_OPTION_TABLE to false. Thanks, Myles From peter at stuge.se Fri Jul 9 22:30:13 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 9 Jul 2010 22:30:13 +0200 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: References: <20100709191122.24834.qmail@stuge.se> Message-ID: <20100709203013.4112.qmail@stuge.se> Myles Watson wrote: > > This is another way to express what I think is important; a way to > > disable NVRAM options that guarantees that coreboot will never write > > to NVRAM. > > It's implemented: Don't use fallback/normal & set USE_OPTION_TABLE to > false. Fantastic. I probably knew this already, sorry for forgetting. It would be nice to never mention fallback anywhere unless there is also a normal, but that's another issue. If USE_OPTION_TABLE is set during config then I think it's fine to overwrite any invalid NVRAM contents. //Peter From mylesgw at gmail.com Fri Jul 9 22:47:51 2010 From: mylesgw at gmail.com (Myles Watson) Date: Fri, 9 Jul 2010 14:47:51 -0600 Subject: [coreboot] [PATCH] fix normal vs. fallback In-Reply-To: <20100709203013.4112.qmail@stuge.se> References: <20100709191122.24834.qmail@stuge.se> <20100709203013.4112.qmail@stuge.se> Message-ID: > > It's implemented: Don't use fallback/normal & set USE_OPTION_TABLE to > > false. > > Fantastic. I probably knew this already, sorry for forgetting. No problem. > It > would be nice to never mention fallback anywhere unless there is > also a normal, but that's another issue. Yes. It's always seemed to me like we should always have a normal image, and let fallback be optional. I think you can change that via Kconfig, but I haven't played with it. > If USE_OPTION_TABLE is set during config then I think it's fine to > overwrite any invalid NVRAM contents. Great. That's how it's supposed to work. Thanks, Myles From borg.db at gmail.com Sat Jul 10 01:16:35 2010 From: borg.db at gmail.com (David Borg) Date: Sat, 10 Jul 2010 01:16:35 +0200 Subject: [coreboot] Mobo Support In-Reply-To: <20100607042002.12353.qmail@stuge.se> References: <48372.1275871911@jenbo.dk> <20100607042002.12353.qmail@stuge.se> Message-ID: Hey Anders, I can help out with coding and testing support for the GA-6VX7-4X. Do you have a patch with the code you have done already, so we don't duplicate efforts? I've got datasheets for the north and south bridges, so it shouldn't be too difficult to include support for this board. Let me know how I can help. Thanks, David From anders at jenbo.dk Sat Jul 10 02:16:30 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sat, 10 Jul 2010 02:16:30 +0200 Subject: [coreboot] Mobo Support In-Reply-To: References: <48372.1275871911@jenbo.dk><20100607042002.12353.qmail@stuge.se> Message-ID: Hi Grate, I'll send so the patch in a day or two. At the moment it sets up most of the config before ram init, the SMBus code is about half done. -Anders -------------------------------------------------- From: "David Borg" Sent: Saturday, July 10, 2010 1:16 AM To: Cc: Subject: Re: [coreboot] Mobo Support > Hey Anders, > I can help out with coding and testing support for the GA-6VX7-4X. Do > you have a patch with the code you have done already, so we don't > duplicate efforts? I've got datasheets for the north and south > bridges, so it shouldn't be too difficult to include support for this > board. Let me know how I can help. > > Thanks, > David > From takuo at akibsystems.com Mon Jul 12 10:47:20 2010 From: takuo at akibsystems.com (Takuo Fukunaga) Date: Mon, 12 Jul 2010 16:47:20 +0800 Subject: [coreboot] Necessary information for supporting chipsets Message-ID: <4C3AD698.3060606@akibsystems.com> Hi, my apologies in advance for the newbie question. I would just like to know what information is necessary to support recent Intel chipsets such as Nehalem chipsets. Datasheets for these chipsets are available on Intel's web site and I think that is enough. Are there any information, for example, setup sequence, which isn't described in those datasheets? Best Regards, Takuo From stefan.reinauer at coresystems.de Mon Jul 12 12:32:35 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Mon, 12 Jul 2010 12:32:35 +0200 Subject: [coreboot] Necessary information for supporting chipsets In-Reply-To: <4C3AD698.3060606@akibsystems.com> References: <4C3AD698.3060606@akibsystems.com> Message-ID: <4C3AEF43.50902@coresystems.de> On 7/12/10 10:47 AM, Takuo Fukunaga wrote: > Hi, my apologies in advance for the newbie question. > > I would just like to know what information is necessary to > support recent Intel chipsets such as Nehalem chipsets. > > Datasheets for these chipsets are available on Intel's > web site and I think that is enough. > > Are there any information, for example, setup sequence, > which isn't described in those datasheets? You will need a CNDA and a Restricted Secret NDA with Intel in order to get the necessary information to port coreboot to Nehalem. Be sure to have any such agreements checked by a lawyer so that you know that you are allowed to write (and publish) coreboot support for those systems. Stefan From svn at coreboot.org Mon Jul 12 16:00:02 2010 From: svn at coreboot.org (coreboot tracker) Date: Mon, 12 Jul 2010 16:00:02 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From grantwu00 at yahoo.com.tw Tue Jul 13 00:34:56 2010 From: grantwu00 at yahoo.com.tw (=?big5?B?R3JhbnQgp2Sp+q+n?=) Date: Tue, 13 Jul 2010 06:34:56 +0800 (CST) Subject: [coreboot] "FILO setup OS" problem In-Reply-To: References: <876847.45785.qm@web72807.mail.tp2.yahoo.com> Message-ID: <999361.76327.qm@web74202.mail.tp2.yahoo.com> Hi All, My project is AMD K8+RS780+SB700. Now my coreboot BIOS can boot into FILO.(SATA1: HDD, SATA3: CDROM) GEEXBOX setup CD is in CDROM. So I key in: kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom installator But I cannot setup GEEXBOX(Message : File not found) I change "hdc" to hda,hdb, hdc, hdd, hde, and the results are the same. Can anyone tell me what's wrong? Grant -------------- next part -------------- An HTML attachment was scrubbed... URL: From marcj303 at gmail.com Tue Jul 13 07:45:11 2010 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 12 Jul 2010 23:45:11 -0600 Subject: [coreboot] "FILO setup OS" problem In-Reply-To: <999361.76327.qm@web74202.mail.tp2.yahoo.com> References: <876847.45785.qm@web72807.mail.tp2.yahoo.com> <999361.76327.qm@web74202.mail.tp2.yahoo.com> Message-ID: 2010/7/12 Grant ??? : > Hi All, > > My project is AMD K8+RS780+SB700. > > Now my coreboot BIOS can boot into FILO.(SATA1: HDD, SATA3: CDROM) > > GEEXBOX setup CD is in CDROM. > > So I key in: > kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom > installator > But I cannot setup GEEXBOX(Message : File not found) > > I change "hdc" to hda,hdb, hdc, hdd, hde, and the results are the same. > Can anyone tell me what's wrong? > > Grant Hi Grant, I assume that you are using a liveCD. I don't think that will work with filo. I have never tried. Either setup the harddrive with your image on another machine or try booting the Seabios payload. Marc -- http://se-eng.com From wangqingpei at gmail.com Tue Jul 13 07:56:58 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 13 Jul 2010 13:56:58 +0800 Subject: [coreboot] "FILO setup OS" problem In-Reply-To: <999361.76327.qm@web74202.mail.tp2.yahoo.com> References: <876847.45785.qm@web72807.mail.tp2.yahoo.com> <999361.76327.qm@web74202.mail.tp2.yahoo.com> Message-ID: hi Grant, have you enable the ISO9660 filesystem config with filo? please enable all of the debug level, post the log. That would make us more clear about what's the problem 2010/7/13 Grant ??? > Hi All, > > My project is AMD K8+RS780+SB700. > > Now my coreboot BIOS can boot into FILO.(SATA1: HDD, SATA3: CDROM) > > GEEXBOX setup CD is in CDROM. > > So I key in: > kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom > installator > But I cannot setup GEEXBOX(Message : File not found) > > I change "hdc" to hda,hdb, hdc, hdd, hde, and the results are the same. > Can anyone tell me what's wrong? > > Grant > > > > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Tue Jul 13 11:13:16 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 13 Jul 2010 17:13:16 +0800 Subject: [coreboot] gigabyte dual bios programming Message-ID: hi Vadim, i am trying to flashing the gigabyte dual bios at this moment, have you ever tried to boot coreboot from the main bios? i flashed the main bios, but the board always did the checksum failed, the restore the bios to the legacy bios. Have you ever tried that? if flash the backup chip, how to make it boot first? -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From caibaiyin.pku at gmail.com Tue Jul 13 16:51:17 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Tue, 13 Jul 2010 22:51:17 +0800 Subject: [coreboot] filo kconfig patch of libpayload Message-ID: hi all, the patch did the following things: 1) load libpayload kconfig while configuring filo. 2) build libpayload before filo building. it can be used by : $MAKE LIBCONFIG_PATH=/path/to/libpayload" Any suggestion will be welcome. thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: filo-libpayload.patch Type: text/x-patch Size: 7447 bytes Desc: not available URL: From patrick at georgi-clan.de Tue Jul 13 23:01:45 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Tue, 13 Jul 2010 23:01:45 +0200 Subject: [coreboot] filo kconfig patch of libpayload In-Reply-To: References: Message-ID: <4C3CD439.1090205@georgi-clan.de> Am 13.07.2010 16:51, schrieb baiyin cai: > 1) load libpayload kconfig while configuring filo. > 2) build libpayload before filo building. > it can be used by : $MAKE LIBCONFIG_PATH=/path/to/libpayload" > Any suggestion will be welcome. thanks Marc asked me to take a closer look, as I worked a lot on coreboot related Makefiles in the past (though not on these) and he mentioned that you plan to use that work for more libpayload-based payload. If that is the case, consider pushing the complex and libpayload specific parts into the libpayload tree, and then use "include" to load it from the payloads' Makefiles. But that can (and should) be done in a separate patch, to avoid that you lose your work to mistakes. > +ifneq ($(strip $(HAVE_FILO_CONFIG)),) > +ifneq ($(strip $(HAVE_LIB_CONFIG)),) > xconfig: prepare $(objk)/qconf > + $(Q)printf "Libpayload config for FILO.\n" > + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" > + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) > + $(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in > + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) > + $(Q)printf "Libpayload config done.\n" > + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) > $(Q)$(objk)/qconf $(Kconfig) > +else > +xconfig: prepare $(objk)/qconf > + $(Q)printf "Lost libpayload config file.\n" > + $(Q)rm -f $(FILO_CONFIG) What's the intended behaviour if HAVE_LIB_CONFIG is not set? Maybe it's better to just $(error ... ) before doing all these nested ifs and elses? That would spare you the various copies below. > -ifeq ($(strip $(HAVE_LIBPAYLOAD)),) > -all: > - @printf "\nError: libpayload is not installed!\nexpected: $(LIBPAYLOAD).\n" > +ifneq ($(strip $(HAVE_LIBPAYLOAD)),) > +libpayload: > + @printf "Found Libpayload $(LIBPAYLOAD).\n" > else > -all: prepare $(obj)/version.h $(TARGET) > +libpayload: $(src)/$(LIB_CONFIG) libpayload should be marked as a "phony" target, I think. Alternatively, libpayload's install target could be changed to install a certain file last, and then you could rely on its presence to determine if there's a complete installation. Also be careful with the actions of the libpayload target: libpayload is referenced from multiple places, so if you're doing parallel builds (make -j), make is free to execute this rule parallely multiple times (not that this makes sense, but it can do so, and it does, sometimes). Whatever you do here must be stable against races in such situations. Apart from these little issues, I think your patch is a real improvement for simplifying the build of a complete image. Thank you! With the above taken into account, this is Acked-by: Patrick Georgi Patrick From grantwu00 at yahoo.com.tw Wed Jul 14 00:11:34 2010 From: grantwu00 at yahoo.com.tw (=?big5?B?R3JhbnQgp2Sp+q+n?=) Date: Wed, 14 Jul 2010 06:11:34 +0800 (CST) Subject: [coreboot] "FILO setup OS" problem In-Reply-To: References: <876847.45785.qm@web72807.mail.tp2.yahoo.com> <999361.76327.qm@web74202.mail.tp2.yahoo.com> Message-ID: <606081.37382.qm@web74210.mail.tp2.yahoo.com> Hi, Now I change FILO to Seabios. Setuping Linux is OK. Thanks, Grant ________________________________ ???? Marc Jones ???? Grant ??? ???? coreboot at coreboot.org ????? 2010/7/13 (?) 1:45:11 PM ???? Re: [coreboot] "FILO setup OS" problem 2010/7/12 Grant ??? : > Hi All, > > My project is AMD K8+RS780+SB700. > > Now my coreboot BIOS can boot into FILO.(SATA1: HDD, SATA3: CDROM) > > GEEXBOX setup CD is in CDROM. > > So I key in: > kernel hdc:/GEEXBOX/boot/vmlinuz root=/dev/ram0 rw init=linuxrc boot=cdrom > installator > But I cannot setup GEEXBOX(Message : File not found) > > I change "hdc" to hda,hdb, hdc, hdd, hde, and the results are the same. > Can anyone tell me what's wrong? > > Grant Hi Grant, I assume that you are using a liveCD. I don't think that will work with filo. I have never tried. Either setup the harddrive with your image on another machine or try booting the Seabios payload. Marc -- http://se-eng.com -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Wed Jul 14 01:57:28 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 14 Jul 2010 01:57:28 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: Message-ID: <20100713235728.30668.qmail@stuge.se> Qing Pei Wang wrote: > i flashed the main bios, but the board always did the checksum > failed, I believe this happens because coreboot does not perform the special handshake before the patented timer expires. > the restore the bios to the legacy bios. > Have you ever tried that? if flash the backup chip, how to make it > boot first? I think it should work if you flash both flash chips with coreboot. Then it will try to start from the first one, expire the timer, then start from the second one. //Peter From Amit.Maoz at nuvoton.com Wed Jul 14 08:34:25 2010 From: Amit.Maoz at nuvoton.com (Amit.Maoz at nuvoton.com) Date: Wed, 14 Jul 2010 09:34:25 +0300 Subject: [coreboot] Add support for nuvoton WPCE775x/NPCE781x devices Message-ID: <8F2A7B0931C16B4C99DDA3B283A4363013FDF643@ntilml01.nuvoton.com> This patch was created by: dhendrix at google.com. Amit Maoz Advanced PC Division Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel Phone : +972-9-9702266 Fax : +972-9-9702001 Email : Amit.Maoz at nuvoton.com =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. 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Name: nuvoton.diff Type: application/octet-stream Size: 5584 bytes Desc: nuvoton.diff URL: From wangqingpei at gmail.com Wed Jul 14 09:45:15 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Wed, 14 Jul 2010 15:45:15 +0800 Subject: [coreboot] Jetway PA78VM5 Support Message-ID: add support of Jetway PA78VM5 and F71863FG super I/O support. Signed-off-by: Wang Qing Pei -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: f71863fg.patch Type: text/x-patch Size: 9820 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: pa78vm5.patch Type: text/x-patch Size: 156120 bytes Desc: not available URL: From eswierk at aristanetworks.com Wed Jul 14 08:44:35 2010 From: eswierk at aristanetworks.com (Ed Swierk) Date: Tue, 13 Jul 2010 23:44:35 -0700 Subject: [coreboot] cbfs for safe flashing Message-ID: Hi folks, I'm using Coreboot to implement an old-school Linux-as-bootloader for a prototype board, which has an 8-MByte SPI flash attached to an AMD SB800 southbridge. I'd like to take advantage of that nice roomy flash, as well as the normal/fallback capabilities of Coreboot and the layout and partial-rewrite features of flashrom, to provide a safe firmware upgrade path for end users. Ideally I'd divide up the flash so that the normal Coreboot+payload are separate from the fallback Coreboot+payload and bootblock. The end user would only rewrite the normal Coreboot+payload. If the rewrite fails leaving the normal area of the flash completely scrambled, the board would still boot using the fallback Coreboot+payload. And for extra credit, I'd try to put the critical fallback bits in an area of the flash that can be turned read-only once it's programmed at the factory. Following the flashrom layout format, here's how I imagine partitioning the flash: 00000000:003fffff normal+payload 00400000:ffffffff fallback+payload+bootblock Following Patrick's helpful recipe (http://www.coreboot.org/pipermail/coreboot/2010-February/055944.html) I figured out how to build a rom image with a cbfs containing normal and fallback files. Unfortunately the build system insists on placing each new file at the beginning of the free space; I didn't see any obvious way to convince cbfstool to leave a gap after normal+payload and place the fallback files at 00400000. I hacked around this by creating a dummy pad file and adding it before the fallback files. Is there a better way to do this? The next issue I encountered is that when I test my scheme by erasing the 00000000:003fffff region, Coreboot takes approximately forever to locate the fallback files. In cbfs, information about each file is stored in a header along with the file itself. To locate a file, Coreboot starts at the first file's header and hops from one to the next until it finds a matching filename. If instead of a header it finds gibberish, it doesn't throw up its hands in despair; rather, it goes into PRESS PLAY ON TAPE mode, scanning along until it either finds a header signature or hits the end of the rom. At this early stage of the boot process, caches and other such niceties aren't enabled; on my board, each iteration in the walkcbfs loop causes ~75 SPI reads, yielding a scan rate of ~175kB/sec. Placing the fallback files before the normal ones doesn't help, because the bootblock needs to discover that the normal files are AWOL before deciding to use the fallback. Increasing the cbfs file alignment from the default of 64 bytes is more promising, allowing the scan to take much bigger hops. I tried bumping it up to 4096 bytes and ran into several bugs in cbfstool and walkcbfs, which assume that the bootblock region is larger than the alignment in deciding when to terminate the scan. While I'm sure these issues can be fixed, the whole flash-as-tape thing bothers me. In my scheme, I've decided ahead of time where the files are supposed to reside. A file's header is either there or it isn't; there's no point wasting time scanning the entire flash in the vain hope that the file is actually present, just in an unexpected location. I'm thinking of extending the cbfs format to allow more than one top-level header in the bootblock. In my scheme, there would be two: one pointing to the first normal file, and another pointing to the first fallback file. Searching for a file would involve scanning each series of files linked from the headers in the bootblock, and would simply terminate if no matching filename were found in any of them. This implies changing cbfstool and any code in Coreboot that touches cbfs. Before I jump off the deep end, is there an easier or better way to achieve this? --Ed From avg at icyb.net.ua Wed Jul 14 14:20:11 2010 From: avg at icyb.net.ua (Andriy Gapon) Date: Wed, 14 Jul 2010 15:20:11 +0300 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <20100713235728.30668.qmail@stuge.se> References: <20100713235728.30668.qmail@stuge.se> Message-ID: <4C3DAB7B.6040007@icyb.net.ua> In this context I would really appreciate "unabridged" version of ITE IT8718F-S specification. If someone could "somehow" share it, it would be terrific. -- Andriy Gapon From mylesgw at gmail.com Wed Jul 14 14:47:33 2010 From: mylesgw at gmail.com (Myles Watson) Date: Wed, 14 Jul 2010 06:47:33 -0600 Subject: [coreboot] cbfs for safe flashing In-Reply-To: References: Message-ID: <59F85874A9654D22806F45AD5AE1D69A@chimp> > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of Ed Swierk > Sent: Wednesday, July 14, 2010 12:45 AM > To: Coreboot > Subject: [coreboot] cbfs for safe flashing > > Hi folks, > > I'm using Coreboot to implement an old-school Linux-as-bootloader for > a prototype board, which has an 8-MByte SPI flash attached to an AMD > SB800 southbridge. I'd like to take advantage of that nice roomy > flash, as well as the normal/fallback capabilities of Coreboot and the > layout and partial-rewrite features of flashrom, to provide a safe > firmware upgrade path for end users. > > Ideally I'd divide up the flash so that the normal Coreboot+payload > are separate from the fallback Coreboot+payload and bootblock. The end > user would only rewrite the normal Coreboot+payload. If the rewrite > fails leaving the normal area of the flash completely scrambled, the > board would still boot using the fallback Coreboot+payload. And for > extra credit, I'd try to put the critical fallback bits in an area of > the flash that can be turned read-only once it's programmed at the > factory. > > Following the flashrom layout format, here's how I imagine > partitioning the flash: > > 00000000:003fffff normal+payload > 00400000:ffffffff fallback+payload+bootblock Wouldn't you want three areas? I'd think you'd want another for just the bootblock. > > Following Patrick's helpful recipe > (http://www.coreboot.org/pipermail/coreboot/2010-February/055944.html) > I figured out how to build a rom image with a cbfs containing normal > and fallback files. Unfortunately the build system insists on placing > each new file at the beginning of the free space; I didn't see any > obvious way to convince cbfstool to leave a gap after normal+payload > and place the fallback files at 00400000. I hacked around this by > creating a dummy pad file and adding it before the fallback files. Is > there a better way to do this? It seems like there used to be a way to specify an address, which would force CBFS to add the empty space for you. > I'm thinking of extending the cbfs format to allow more than one > top-level header in the bootblock. In my scheme, there would be two: > one pointing to the first normal file, and another pointing to the > first fallback file. Searching for a file would involve scanning each > series of files linked from the headers in the bootblock, and would > simply terminate if no matching filename were found in any of them. > > This implies changing cbfstool and any code in Coreboot that touches > cbfs. Before I jump off the deep end, is there an easier or better way > to achieve this? Instead of erasing one image to test it, you could add blank images with the same name. That would allow you to test the case of a bad flash. The case where CBFS is corrupted shouldn't happen too often, and when it does it is only inconvenient to have it take a long time to boot. The fact that it recovers will make up for that :) Thanks, Myles From wangqingpei at gmail.com Wed Jul 14 17:22:50 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Wed, 14 Jul 2010 23:22:50 +0800 Subject: [coreboot] Jetway PA78VM5 Support In-Reply-To: References: Message-ID: sorry, the last patch is based on r5444 i update the patch which based on the recently svn version Signed-off-by: Wang Qing Pei On Wed, Jul 14, 2010 at 3:45 PM, Qing Pei Wang wrote: > add support of Jetway PA78VM5 and F71863FG super I/O support. > Signed-off-by: Wang Qing Pei > > -- > Wang Qing Pei > Phone: 86+13426369984 > -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PA78VM5.patch Type: text/x-patch Size: 165408 bytes Desc: not available URL: From peter at stuge.se Wed Jul 14 22:25:06 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 14 Jul 2010 22:25:06 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <4C3DAB7B.6040007@icyb.net.ua> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> Message-ID: <20100714202506.7146.qmail@stuge.se> Andriy Gapon wrote: > In this context I would really appreciate "unabridged" version of > ITE IT8718F-S specification. Maybe you already know this, but I would not expect the superio to be involved very much in the dualbios mechanism - at most an IO pin would be used for the handshake with the patented timer. //Peter From gregg.drwho8 at gmail.com Wed Jul 14 22:27:58 2010 From: gregg.drwho8 at gmail.com (Gregg C Levine) Date: Wed, 14 Jul 2010 16:27:58 -0400 Subject: [coreboot] Uncommitted GPIOs Message-ID: <4c3e1dcc.5c4ee50a.6ca6.0e22@mx.google.com> Hello! Would anyone be able to confirm this line of reasoning? For anything based on the X86 design styles, only the GEODE families have these uncommitted GPIO points that are documented. But do the Intel designed chipsets contain undocumented GPIO points? ----- Gregg C Levine gregg.drwho8 at gmail.com "This signature fought the Time Wars, time and again." From peter at stuge.se Wed Jul 14 23:00:24 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 14 Jul 2010 23:00:24 +0200 Subject: [coreboot] Uncommitted GPIOs In-Reply-To: <4c3e1dcc.5c4ee50a.6ca6.0e22@mx.google.com> References: <4c3e1dcc.5c4ee50a.6ca6.0e22@mx.google.com> Message-ID: <20100714210024.12566.qmail@stuge.se> Gregg C Levine wrote: > Would anyone be able to confirm this line of reasoning? For anything > based on the X86 design styles, only the GEODE families have these > uncommitted GPIO points that are documented. I think there's more to the story. > But do the Intel designed chipsets contain undocumented GPIO > points? Yes, and many if not all superio chips have documented GPIO pins. //Peter From joe at settoplinux.org Wed Jul 14 23:06:24 2010 From: joe at settoplinux.org (Joseph Smith) Date: Wed, 14 Jul 2010 17:06:24 -0400 Subject: [coreboot] Uncommitted GPIOs In-Reply-To: <20100714210024.12566.qmail@stuge.se> References: <4c3e1dcc.5c4ee50a.6ca6.0e22@mx.google.com> <20100714210024.12566.qmail@stuge.se> Message-ID: <4C3E26D0.20401@settoplinux.org> On 07/14/2010 05:00 PM, Peter Stuge wrote: > Gregg C Levine wrote: >> Would anyone be able to confirm this line of reasoning? For anything >> based on the X86 design styles, only the GEODE families have these >> uncommitted GPIO points that are documented. > > I think there's more to the story. > > >> But do the Intel designed chipsets contain undocumented GPIO >> points? > > Yes, and many if not all superio chips have documented GPIO pins. > Intel northbridges have GPIO lines in the integrated graphics display (IGD). Not usually documented in datasheets. Intel southbridges also have GPIO lines. And every SuperIO has many GPIO lines. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From caibaiyin.pku at gmail.com Thu Jul 15 01:26:22 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Thu, 15 Jul 2010 07:26:22 +0800 Subject: [coreboot] filo kconfig patch of libpayload In-Reply-To: <4C3CD439.1090205@georgi-clan.de> References: <4C3CD439.1090205@georgi-clan.de> Message-ID: hi patrick, thanks for your kindly suggestions. That's will be much helpful for me. I would take that into consideration. Signed-off-by: Cai Bai Yin 2010/7/14 Patrick Georgi > Am 13.07.2010 16:51, schrieb baiyin cai: > > 1) load libpayload kconfig while configuring filo. > > 2) build libpayload before filo building. > > it can be used by : $MAKE LIBCONFIG_PATH=/path/to/libpayload" > > Any suggestion will be welcome. thanks > Marc asked me to take a closer look, as I worked a lot on coreboot > related Makefiles in the past (though not on these) and he mentioned > that you plan to use that work for more libpayload-based payload. > > If that is the case, consider pushing the complex and libpayload > specific parts into the libpayload tree, and then use "include" to load > it from the payloads' Makefiles. > > But that can (and should) be done in a separate patch, to avoid that you > lose your work to mistakes. > > > +ifneq ($(strip $(HAVE_FILO_CONFIG)),) > > +ifneq ($(strip $(HAVE_LIB_CONFIG)),) > > xconfig: prepare $(objk)/qconf > > + $(Q)printf "Libpayload config for FILO.\n" > > + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" > > + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) > > + $(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in > > + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) > > + $(Q)printf "Libpayload config done.\n" > > + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) > > $(Q)$(objk)/qconf $(Kconfig) > > +else > > +xconfig: prepare $(objk)/qconf > > + $(Q)printf "Lost libpayload config file.\n" > > + $(Q)rm -f $(FILO_CONFIG) > What's the intended behaviour if HAVE_LIB_CONFIG is not set? > Maybe it's better to just $(error ... ) before doing all these nested > ifs and elses? That would spare you the various copies below. > > > -ifeq ($(strip $(HAVE_LIBPAYLOAD)),) > > -all: > > - @printf "\nError: libpayload is not installed!\nexpected: > $(LIBPAYLOAD).\n" > > +ifneq ($(strip $(HAVE_LIBPAYLOAD)),) > > +libpayload: > > + @printf "Found Libpayload $(LIBPAYLOAD).\n" > > else > > -all: prepare $(obj)/version.h $(TARGET) > > +libpayload: $(src)/$(LIB_CONFIG) > libpayload should be marked as a "phony" target, I think. > Alternatively, libpayload's install target could be changed to install a > certain file last, and then you could rely on its presence to determine > if there's a complete installation. > > Also be careful with the actions of the libpayload target: libpayload is > referenced from multiple places, so if you're doing parallel builds > (make -j), make is free to execute this rule parallely multiple times > (not that this makes sense, but it can do so, and it does, sometimes). > Whatever you do here must be stable against races in such situations. > > > Apart from these little issues, I think your patch is a real improvement > for simplifying the build of a complete image. Thank you! > > With the above taken into account, this is > Acked-by: Patrick Georgi > > Patrick > -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Thu Jul 15 10:01:57 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Thu, 15 Jul 2010 16:01:57 +0800 Subject: [coreboot] [PATCH]Jetway PA78VM5 Message-ID: hi all, in order to make the code much clear, i update the patch which sent yesterday to make all messages fit for "PA78VM5". Signed-off-by Wang Qing Pei -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PA78VM5.patch Type: text/x-patch Size: 165407 bytes Desc: not available URL: From avg at icyb.net.ua Thu Jul 15 10:52:41 2010 From: avg at icyb.net.ua (Andriy Gapon) Date: Thu, 15 Jul 2010 11:52:41 +0300 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <20100714202506.7146.qmail@stuge.se> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> Message-ID: <4C3ECC59.9060505@icyb.net.ua> on 14/07/2010 23:25 Peter Stuge said the following: > Andriy Gapon wrote: >> In this context I would really appreciate "unabridged" version of >> ITE IT8718F-S specification. > > Maybe you already know this, but I would not expect the superio to be > involved very much in the dualbios mechanism - at most an IO pin > would be used for the handshake with the patented timer. Still I would like to get the spec. It may also depend on a particular motherboard, chip, etc. Perhaps the "patented timer" is implemented in Super I/O. At least, we see that some undocumented Super I/O register(s) are used to switch between the flash chips and some other related things. -- Andriy Gapon From peter at stuge.se Thu Jul 15 16:29:16 2010 From: peter at stuge.se (Peter Stuge) Date: Thu, 15 Jul 2010 16:29:16 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <4C3ECC59.9060505@icyb.net.ua> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> Message-ID: <20100715142916.10804.qmail@stuge.se> Andriy Gapon wrote: > > Maybe you already know this, but I would not expect the superio to be > > involved very much in the dualbios mechanism - at most an IO pin > > would be used for the handshake with the patented timer. > > Still I would like to get the spec. Yes, fair enough. :) > It may also depend on a particular motherboard, chip, etc. Perhaps > the "patented timer" is implemented in Super I/O. I doubt this since Gigabyte owns the patent for the dual bios invention, and ITE is unrelated to Gigabyte. The dual bios invention might *use* a timer within the superio though - that's possible. > At least, we see that some undocumented Super I/O register(s) are > used to switch between the flash chips and some other related > things. IO pins and timer on the superio could certainly be used. //Peter From svn at coreboot.org Thu Jul 15 17:59:07 2010 From: svn at coreboot.org (repository service) Date: Thu, 15 Jul 2010 17:59:07 +0200 Subject: [coreboot] [commit] r5665 - trunk/util/sconfig Message-ID: Author: oxygene Date: Thu Jul 15 17:59:07 2010 New Revision: 5665 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5665 Log: Trivial: Improve error reporting of sconfig slightly by reporting the line number. Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/util/sconfig/main.c Modified: trunk/util/sconfig/main.c ============================================================================== --- trunk/util/sconfig/main.c Fri Jul 9 20:52:17 2010 (r5664) +++ trunk/util/sconfig/main.c Thu Jul 15 17:59:07 2010 (r5665) @@ -21,6 +21,8 @@ #include "sconfig.h" #include "sconfig.tab.h" +extern int linenum; + struct device *head, *lastdev; struct header headers; @@ -87,7 +89,7 @@ void yyerror (char const *str) { - fprintf (stderr, "%s\n", str); + fprintf (stderr, "line %d: %s\n", linenum, str); } void postprocess_devtree(void) { From c-d.hailfinger.devel.2006 at gmx.net Thu Jul 15 20:09:53 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 15 Jul 2010 20:09:53 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <20100715142916.10804.qmail@stuge.se> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> <20100715142916.10804.qmail@stuge.se> Message-ID: <4C3F4EF1.7030709@gmx.net> Hi, On 15.07.2010 16:29, Peter Stuge wrote: > Andriy Gapon wrote: > >>> Maybe you already know this, but I would not expect the superio to be >>> involved very much in the dualbios mechanism - at most an IO pin >>> would be used for the handshake with the patented timer. >>> >> Still I would like to get the spec. >> > > Yes, fair enough. :) > > > >> It may also depend on a particular motherboard, chip, etc. Perhaps >> the "patented timer" is implemented in Super I/O. >> > > I doubt this since Gigabyte owns the patent for the dual bios > invention, and ITE is unrelated to Gigabyte. The dual bios invention > might *use* a timer within the superio though - that's possible. > > > >> At least, we see that some undocumented Super I/O register(s) are >> used to switch between the flash chips and some other related >> things. >> > > IO pins and timer on the superio could certainly be used. > Did you know that SB700 (and later) has its own Dual BIOS mechanism? If there is interest, I can help with implementing support for that feature in flashrom. Regards, Carl-Daniel -- http://www.hailfinger.org/ From caibaiyin.pku at gmail.com Fri Jul 16 04:42:12 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Fri, 16 Jul 2010 10:42:12 +0800 Subject: [coreboot] filo xcompile patch Message-ID: this patch is used for filo xcompile fix. Signed-off-by: Cai Bai Yin -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: filo-xcompile.patch Type: text/x-patch Size: 531 bytes Desc: not available URL: From borg.db at gmail.com Fri Jul 16 07:12:39 2010 From: borg.db at gmail.com (David Borg) Date: Fri, 16 Jul 2010 07:12:39 +0200 Subject: [coreboot] Mobo Support In-Reply-To: <1279143483.5128.0.camel@anders-laptop> References: <48372.1275871911@jenbo.dk> <20100607042002.12353.qmail@stuge.se> <1279143483.5128.0.camel@anders-laptop> Message-ID: Thanks a lot! I'll start working on it as soon as I have some time. Regards, David On 14 July 2010 23:38, Anders Jenbo wrote: > Here is the patch > > l?r, 10 07 2010 kl. 01:16 +0200, skrev David Borg: >> Hey Anders, >> I can help out with coding and testing support for the GA-6VX7-4X. Do >> you have a patch with the code you have done already, so we don't >> duplicate efforts? I've got datasheets for the north and south >> bridges, so it shouldn't be too difficult to include support for this >> board. Let me know how I can help. >> >> Thanks, >> David > > -- David Borg From avg at icyb.net.ua Fri Jul 16 09:17:56 2010 From: avg at icyb.net.ua (Andriy Gapon) Date: Fri, 16 Jul 2010 10:17:56 +0300 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <4C3F4EF1.7030709@gmx.net> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> <20100715142916.10804.qmail@stuge.se> <4C3F4EF1.7030709@gmx.net> Message-ID: <4C4007A4.2090807@icyb.net.ua> on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following: > > Did you know that SB700 (and later) has its own Dual BIOS mechanism? If > there is interest, I can help with implementing support for that feature > in flashrom. Does that mechanism require that flash chips are wired to the south bridge (handled by its SPI controller)? Or is it a more generic mechanism? -- Andriy Gapon From corey.osgood at gmail.com Fri Jul 16 12:02:32 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Fri, 16 Jul 2010 06:02:32 -0400 Subject: [coreboot] What have I missed? Message-ID: It's been a while since I've read the list, and I've got a new project going on and I'm trying to get back up to speed. I see there's now a v4, currently checking it out but it looks a lot like the v2 code with the v3 build system, is that about right? If so, sorry I wasn't around to help out with the merge. What's the current state of CAR on non-AMD64 CPUs, is the C7 implementation working reliably now? Does it work on Nano? How about Atom? Anything else I should know about before diving in? Thanks, Corey From JasonZhao at viatech.com.cn Fri Jul 16 12:25:56 2010 From: JasonZhao at viatech.com.cn (JasonZhao at viatech.com.cn) Date: Fri, 16 Jul 2010 18:25:56 +0800 Subject: [coreboot] Emacs package to highlight variable/function-call in C code Message-ID: <5B96C97B1988A4419C8FED50FF66A29B57BF6B@exchbj02.viatech.com.bj> Hi all, I am still alive! This time I come back to share an Emacs package(I write it) I think some of you would like, it can highlight almost every thing in C code. Attachment includes the screen-shot of this package, you can check it before you decide to install the package or not. TO INSTALL this package 1. enable semantic firstly You need enable cedet/semantic(emacs23.2 has include this) before use the zjl-hl.el: (when (and (fboundp 'semantic-mode) (not (locate-library "semantic-ctxt"))) ; can't found offical cedet (setq semantic-default-submodes '(global-semantic-idle-scheduler-mode global-semanticdb-minor-mode global-semantic-idle-summary-mode global-semantic-mru-bookmark-mode)) (semantic-mode 1) (require 'semantic/ctxt) 2. Download zjl-hl.el and region-list-edit.el from http://www.emacswiki.org/emacs/JianliZhao 3. Add these two lines to your dot emacs. ===========888============= (require 'zjl-hl) (zjl-hl-enable-global-all-modes);(zjl-hl-disable-global-all) ===========888============= By default, zjl-hl.el works on both C and emacs-lisp, you can also enable/disable one of them by this config: (require 'zjl-hl) ;;(zjl-hl-enable-global-all-modes) (zjl-hl-enable-global 'c-mode);; (zjl-hl-disable-global 'c-mode) (zjl-hl-enable-global 'emacs-lisp-mode);; (zjl-hl-disable-global 'emacs-lisp-mode) -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: zjl-hl.png Type: image/png Size: 64046 bytes Desc: zjl-hl.png URL: From joe at settoplinux.org Fri Jul 16 13:05:24 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 16 Jul 2010 07:05:24 -0400 Subject: [coreboot] =?utf-8?q?What_have_I_missed=3F?= In-Reply-To: References: Message-ID: <6f4a69bd66132d10f3d1979ced837575@imap.1and1.com> On Fri, 16 Jul 2010 06:02:32 -0400, Corey Osgood wrote: > It's been a while since I've read the list, and I've got a new project > going on and I'm trying to get back up to speed. I see there's now a > v4, currently checking it out but it looks a lot like the v2 code with > the v3 build system, is that about right? If so, sorry I wasn't around > to help out with the merge. What's the current state of CAR on > non-AMD64 CPUs, is the C7 implementation working reliably now? Does it > work on Nano? How about Atom? Anything else I should know about before > diving in? > Welcome back Corey :-) Good to hear from you. We now have CAR running on the Intel CPU's. Not all of the 440bx's and Socket 370's have been converted yet. I am currectly working on the 370's. We have a pending patch for CAR on Geode GX2. Yes v3 is kind of abandone, and we jumped to v4. v4 has same basic structure as v2 but we are now using Kconfig for our build system, don't get me wrong though... alot has changed sinse v2 so dive in:-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Fri Jul 16 14:41:47 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 16 Jul 2010 08:41:47 -0400 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <201007062027.12484.njacobs8@hetnet.nl> References: <201007062027.12484.njacobs8@hetnet.nl> Message-ID: <7789189772300c48365ef062f885e862@imap.1and1.com> On Tue, 6 Jul 2010 20:27:12 +0200, Nils wrote: > Ping!? > Could anybody tell me how to proceed? > Peter:did i gave the wrong answers? :) > > Thanks,Nils. > Nils, I really would hate to see your great work go to the way side. It has been a few revisions since your original patch. As long as you can send a working/tested updated patch to the list: Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From avg at icyb.net.ua Fri Jul 16 15:34:38 2010 From: avg at icyb.net.ua (Andriy Gapon) Date: Fri, 16 Jul 2010 16:34:38 +0300 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> <20100715142916.10804.qmail@stuge.se> <4C3F4EF1.7030709@gmx.net> <4C4007A4.2090807@icyb.net.ua> Message-ID: <4C405FEE.9090704@icyb.net.ua> on 16/07/2010 16:29 Qing Pei Wang said the following: > i think the spi chips are wired to both south bridge and super I/O. On my mobo they are definitely wired to Super I/O only. That doesn't preclude, of course, Super I/O being wired to SB :-) -- Andriy Gapon From wangqingpei at gmail.com Fri Jul 16 15:29:44 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Fri, 16 Jul 2010 21:29:44 +0800 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <4C4007A4.2090807@icyb.net.ua> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> <20100715142916.10804.qmail@stuge.se> <4C3F4EF1.7030709@gmx.net> <4C4007A4.2090807@icyb.net.ua> Message-ID: i think the spi chips are wired to both south bridge and super I/O. carl: i do not think that SB700 has this mechanism, it must be the time circuit of this patent. i find that before booting bios, there is several seconds delay after powering up. On Fri, Jul 16, 2010 at 3:17 PM, Andriy Gapon wrote: > on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following: > > > > Did you know that SB700 (and later) has its own Dual BIOS mechanism? If > > there is interest, I can help with implementing support for that feature > > in flashrom. > > Does that mechanism require that flash chips are wired to the south bridge > (handled by its SPI controller)? Or is it a more generic mechanism? > > -- > Andriy Gapon > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From njacobs8 at hetnet.nl Fri Jul 16 21:35:58 2010 From: njacobs8 at hetnet.nl (Nils) Date: Fri, 16 Jul 2010 21:35:58 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <7789189772300c48365ef062f885e862@imap.1and1.com> References: <201007062027.12484.njacobs8@hetnet.nl> <7789189772300c48365ef062f885e862@imap.1and1.com> Message-ID: <201007162135.59312.njacobs8@hetnet.nl> Hi Joseph, Op vrijdag 16 juli 2010 14:41:47 schreef u: > On Tue, 6 Jul 2010 20:27:12 +0200, Nils wrote: > > Ping!? > > Could anybody tell me how to proceed? > > Peter:did i gave the wrong answers? :) > > > > Thanks,Nils. > > Nils, > I really would hate to see your great work go to the way side. > It has been a few revisions since your original patch. > As long as you can send a working/tested updated patch to the list: > > Acked-by: Joseph Smith Thanks for the heads up! At the moment i have no time to update/test the patch, maybe in a few days. I will delete the unused code if til then nobody speaks up/ objects. And add the new line in Makefile.inc . Maybe until then Peter finds some time to give some professional advice. Thanks again for the ack. Nils. P.s. How is your paraflasher project doing? Do you have some programming results already? From svn at coreboot.org Fri Jul 16 22:02:09 2010 From: svn at coreboot.org (repository service) Date: Fri, 16 Jul 2010 22:02:09 +0200 Subject: [coreboot] [commit] r5666 - in trunk/src: arch/i386/lib console include include/console lib Message-ID: Author: ruik Date: Fri Jul 16 22:02:09 2010 New Revision: 5666 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5666 Log: Add support for the console over Ethernet (through PCI NE2000). Signed-off-by: Rudolf Marek Acked-by: Cristian Magherusan-Stanciu Added: trunk/src/console/ne2k_console.c trunk/src/include/console/ne2k.h trunk/src/lib/ne2k.c trunk/src/lib/ns8390.h Modified: trunk/src/arch/i386/lib/printk_init.c trunk/src/console/Kconfig trunk/src/console/Makefile.inc trunk/src/console/console.c trunk/src/include/console/console.h trunk/src/include/ip_checksum.h trunk/src/lib/Makefile.inc Modified: trunk/src/arch/i386/lib/printk_init.c ============================================================================== --- trunk/src/arch/i386/lib/printk_init.c Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/arch/i386/lib/printk_init.c Fri Jul 16 22:02:09 2010 (r5666) @@ -21,8 +21,17 @@ #include #include +#if CONFIG_CONSOLE_NE2K +#include +#endif + static void console_tx_byte(unsigned char byte) { +#if CONFIG_CONSOLE_NE2K +#ifdef __PRE_RAM__ + ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +#endif if (byte == '\n') uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r'); @@ -41,6 +50,8 @@ va_start(args, fmt); i = vtxprintf(console_tx_byte, fmt, args); va_end(args); - +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif return i; } Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/console/Kconfig Fri Jul 16 22:02:09 2010 (r5666) @@ -1,5 +1,4 @@ menu "Console options" - # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 bool "Serial port console output" @@ -130,6 +129,49 @@ help If not selected, the last adapter found will be used. +config CONSOLE_NE2K + bool "Network console over NE2000 compatible Ethernet adapter" + default n + help + Send coreboot debug output to a Ethernet console, it works + same way as Linux netconsole, packets are received to UDP + port 6666 on IP/MAC specified with options bellow. + Use following netcat command: nc -u -l -p 6666 + +config CONSOLE_NE2K_DST_MAC + depends on CONSOLE_NE2K + string "Destination MAC address of remote system" + default "00:13:d4:76:a2:ac" + help + Type in either MAC address of logging system or MAC address + of the router. + +config CONSOLE_NE2K_DST_IP + depends on CONSOLE_NE2K + string "Destination IP of logging system" + default "10.0.1.27" + help + This is IP adress of the system running for example + netcat command to dump the packets. + +config CONSOLE_NE2K_SRC_IP + depends on CONSOLE_NE2K + string "IP adress of Coreboot system" + default "10.0.1.253" + help + This is the IP of the Coreboot system + +config CONSOLE_NE2K_IO_PORT + depends on CONSOLE_NE2K + hex "NE2000 adapter fixed IO port address" + default 0xe00 + help + This is the IO port address for the IO port + on the card, please select some non-conflicting region, + 32 bytes of IO spaces will be used (and align on 32 bytes + boundary, qemu needs broader align) + + choice prompt "Maximum console log level" default MAXIMUM_CONSOLE_LOGLEVEL_8 Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/console/Makefile.inc Fri Jul 16 22:02:09 2010 (r5666) @@ -15,6 +15,7 @@ driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o +driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.o $(obj)/console/console.o : $(obj)/build.h $(obj)/console/console.initobj.o : $(obj)/build.h Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/console/console.c Fri Jul 16 22:02:09 2010 (r5666) @@ -7,11 +7,14 @@ #include #include +#if CONFIG_CONSOLE_NE2K +#include +#endif + #ifndef __PRE_RAM__ #include #include - /* initialize the console */ void console_init(void) { @@ -99,6 +102,10 @@ void console_init(void) { + +#if CONFIG_CONSOLE_NE2K + ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION Added: trunk/src/console/ne2k_console.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/console/ne2k_console.c Fri Jul 16 22:02:09 2010 (r5666) @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +static void ne2k_tx_byte(unsigned char data) +{ + ne2k_append_data(&data, 1, CONFIG_CONSOLE_NE2K_IO_PORT); +} + +static void ne2k_tx_flush(void) +{ + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +} + +static const struct console_driver ne2k_console __console = { + .tx_byte = ne2k_tx_byte, + .tx_flush = ne2k_tx_flush, +}; Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/include/console/console.h Fri Jul 16 22:02:09 2010 (r5666) @@ -131,10 +131,17 @@ #include +#if CONFIG_CONSOLE_NE2K +#include "lib/ne2k.c" +#endif + /* __ROMCC__ */ static void __console_tx_byte(unsigned char byte) { uart_tx_byte(byte); +#if CONFIG_CONSOLE_NE2K + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } static void __console_tx_nibble(unsigned nibble) @@ -151,6 +158,10 @@ { if (console_loglevel >= loglevel) { uart_tx_byte(byte); +#if CONFIG_CONSOLE_NE2K + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } } @@ -160,6 +171,9 @@ __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } static void __console_tx_hex16(int loglevel, unsigned short value) @@ -170,6 +184,9 @@ __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } static void __console_tx_hex32(int loglevel, unsigned int value) @@ -184,6 +201,9 @@ __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } static void __console_tx_string(int loglevel, const char *str) @@ -195,6 +215,9 @@ __console_tx_byte('\r'); __console_tx_byte(ch); } +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif } } Added: trunk/src/include/console/ne2k.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/console/ne2k.h Fri Jul 16 22:02:09 2010 (r5666) @@ -0,0 +1,27 @@ +#ifndef _NE2K_H__ +#define _NE2K_H__ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ROMCC__ +void ne2k_append_data(unsigned char *d, int len, unsigned int base); +int ne2k_init(unsigned int eth_nic_base); +void ne2k_transmit(unsigned int eth_nic_base); +#endif +#endif /* _NE2K_H */ Modified: trunk/src/include/ip_checksum.h ============================================================================== --- trunk/src/include/ip_checksum.h Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/include/ip_checksum.h Fri Jul 16 22:02:09 2010 (r5666) @@ -1,7 +1,8 @@ #ifndef IP_CHECKSUM_H #define IP_CHECKSUM_H +#ifndef __ROMCC__ unsigned long compute_ip_checksum(void *addr, unsigned long length); unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new); - +#endif #endif /* IP_CHECKSUM_H */ Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Thu Jul 15 17:59:07 2010 (r5665) +++ trunk/src/lib/Makefile.inc Fri Jul 16 22:02:09 2010 (r5666) @@ -22,6 +22,9 @@ initobj-y += cbfs.o initobj-y += lzma.o #initobj-y += lzmadecode.o +initobj-$(CONFIG_CONSOLE_NE2K) += ne2k.o +initobj-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.o +driver-$(CONFIG_CONSOLE_NE2K) += ne2k.o obj-$(CONFIG_USBDEBUG) += usbdebug.o Added: trunk/src/lib/ne2k.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/lib/ne2k.c Fri Jul 16 22:02:09 2010 (r5666) @@ -0,0 +1,462 @@ +/* +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: May/94 + + This code is based heavily on David Greenman's if_ed.c driver + + Copyright (C) 1993-1994, David Greenman, Martin Renters. + This software may be used, modified, copied, distributed, and sold, in + both source and binary form provided that the above copyright and these + terms are retained. Under no circumstances are the authors responsible for + the proper functioning of this software, nor do the authors assume any + responsibility for damages incurred with its use. + +Multicast support added by Timothy Legge (timlegge at users.sourceforge.net) 09/28/2003 +Relocation support added by Ken Yap (ken_yap at users.sourceforge.net) 28/12/02 +3c503 support added by Bill Paul (wpaul at ctr.columbia.edu) on 11/15/94 +SMC8416 support added by Bill Paul (wpaul at ctr.columbia.edu) on 12/25/94 +3c503 PIO support added by Jim Hague (jim.hague at acm.org) on 2/17/98 +RX overrun by Klaus Espenlaub (espenlaub at informatik.uni-ulm.de) on 3/10/99 + parts taken from the Linux 8390 driver (by Donald Becker and Paul Gortmaker) +SMC8416 PIO support added by Andrew Bettison (andrewb at zip.com.au) on 4/3/02 + based on the Linux 8390 driver (by Donald Becker and Paul Gortmaker) + +(C) Rudolf Marek Simplify for RTL8029, Add coreboot glue logic + +*/ + +#define ETH_ALEN 6 /* Size of Ethernet address */ +#define ETH_HLEN 14 /* Size of ethernet header */ +#define ETH_ZLEN 60 /* Minimum packet */ +#define ETH_FRAME_LEN 1514 /* Maximum packet */ +#define ETH_DATA_ALIGN 2 /* Amount needed to align the data after an ethernet header */ +#define ETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN) + +#include "ns8390.h" +#include +#include +#include +//#include + +#define MEM_SIZE MEM_32768 +#define TX_START 64 +#define RX_START (64 + D8390_TXBUF_SIZE) + +static unsigned int get_count(unsigned int eth_nic_base) +{ + unsigned int ret; + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, + eth_nic_base + D8390_P0_COMMAND); + + ret = inb(eth_nic_base + 8 + 0) | (inb(eth_nic_base + 8 + 1) << 8); + + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, + eth_nic_base + D8390_P0_COMMAND); + return ret; +} + +static void set_count(unsigned int eth_nic_base, unsigned int what) +{ + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, + eth_nic_base + D8390_P0_COMMAND); + + outb(what & 0xff,eth_nic_base + 8); + outb((what >> 8) & 0xff,eth_nic_base + 8 + 1); + + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, + eth_nic_base + D8390_P0_COMMAND); +} + +static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt, + unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + while (cnt--) { + outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + } + /* + #warning "Add timeout" + */ + /* wait for operation finish */ + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) + ; +} + +void ne2k_append_data(unsigned char *d, int len, unsigned int base) +{ + eth_pio_write(d, (TX_START << 8) + 42 + get_count(base), len, base); + set_count(base, get_count(base)+len); +} + +#ifdef __ROMCC__ + +void eth_pio_write_byte(int data, unsigned short dst, unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(1, eth_nic_base + D8390_P0_RBCR0); + outb(0, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(data, eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) + ; +} + +void ne2k_append_data_byte(int d, unsigned int base) +{ + eth_pio_write_byte(d, (TX_START << 8) + 42 + get_count(base), base); + set_count(base, get_count(base)+1); +} + +static unsigned char eth_pio_read_byte(unsigned int src, + unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(0, eth_nic_base + D8390_P0_RBCR0); + outb(1, eth_nic_base + D8390_P0_RBCR1); + outb(src, eth_nic_base + D8390_P0_RSAR0); + outb(src >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + return inb(eth_nic_base + NE_ASIC_OFFSET + NE_DATA); +} + + +/* varition of compute_ip_checksum which works on SRAM */ +unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned short length, + unsigned int eth_nic_base) +{ + unsigned long sum; + unsigned long i; + /* In the most straight forward way possible, + * compute an ip style checksum. + */ + sum = 0; + for(i = 0; i < length; i++) { + unsigned long v; + v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base); + if (i & 1) { + v <<= 8; + } + /* Add the new value */ + sum += v; + /* Wrap around the carry */ + if (sum > 0xFFFF) { + sum = (sum + (sum >> 16)) & 0xFFFF; + } + } + return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff; +} + + +static void str2ip_load(const char *str, unsigned short offset, unsigned int eth_nic_base) +#else +static void str2ip(const char *str, unsigned char *ip) +#endif +{ + unsigned char c, i = 0; + int acc = 0; + + do { + c = str[i]; + if ((c >= '0') && (c <= '9')) { + acc *= 10; + acc += (c - '0'); + } else { +#ifdef __ROMCC__ + eth_pio_write_byte(acc, (TX_START << 8)+offset, eth_nic_base); + offset++; +#else + *ip++ = acc; +#endif + acc = 0; + } + i++; + } while (c != '\0'); +} + +#ifdef __ROMCC__ +static void str2mac_load(const char *str, unsigned short offset, unsigned int eth_nic_base) +#else +static void str2mac(const char *str, unsigned char *mac) +#endif +{ + unsigned char c, i = 0; + int acc = 0; + + do { + + c = str[i]; + if ((c >= '0') && (c <= '9')) { + acc *= 16; + acc += (c - '0'); + } else if ((c >= 'a') && (c <= 'f')) { + acc *= 16; + acc += ((c - 'a') + 10) ; + } else if ((c >= 'A') && (c <= 'F')) { + acc *= 16; + acc += ((c - 'A') + 10) ; + } else { +#ifdef __ROMCC__ + eth_pio_write_byte(acc, ((TX_START << 8)+offset), eth_nic_base); + offset++; +#else + *mac++ = acc; +#endif + acc = 0; + } + + i++; + } while (c != '\0'); +} + + +#ifndef __ROMCC__ +static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) { + unsigned short chksum; + unsigned char hdr[] = { +#else +static const unsigned char hdr[] = { +#endif + /* + * ETHERNET HDR + */ + + // destination macaddr + 0x02, 0x00, 0x00, 0x00, 0x00, 0x01, + /* source mac */ + 0x02, 0x00, 0x00, 0xC0, 0xFF, 0xEE, + /* ethtype (IP) */ + 0x08, 0x00, + /* + * IP HDR + */ + 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, + /* TTL, proto (UDP), chksum_hi, chksum_lo, IP0, IP1, IP2, IP3, */ + 0x40, 0x11, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1, + /* IP0, IP1, IP2, IP3 */ + 0xff, 0xff, 0xff, 0xff, + /* + * UDP HDR + */ + /* SRC PORT DST PORT (2bytes each), ulen, uchksum (must be zero or correct */ + 0x1a, 0x0b, 0x1a, 0x0a, 0x00, 0x9, 0x00, 0x00, + }; + +#ifndef __ROMCC__ + str2mac(CONFIG_CONSOLE_NE2K_DST_MAC, &hdr[0]); + str2ip(CONFIG_CONSOLE_NE2K_DST_IP, &hdr[30]); + str2ip(CONFIG_CONSOLE_NE2K_SRC_IP, &hdr[26]); + + /* zero checksum */ + hdr[24] = 0; + hdr[25] = 0; + + /* update IP packet len */ + hdr[16] = ((28 + pktlen) >> 8) & 0xff; + hdr[17] = (28 + pktlen) & 0xff; + + /* update UDP len */ + hdr[38] = (8 + pktlen) >> 8; + hdr[39] = 8 + pktlen; + + chksum = compute_ip_checksum(&hdr[14], 20); + + hdr[25] = chksum >> 8; + hdr[24] = chksum; + eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); +} + + +#else + +/* ROMCC madness */ +static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) +{ + unsigned short chksum; + + eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); + + str2mac_load(CONFIG_CONSOLE_NE2K_DST_MAC, 0, eth_nic_base); + + str2ip_load(CONFIG_CONSOLE_NE2K_DST_IP, 30, eth_nic_base); + str2ip_load(CONFIG_CONSOLE_NE2K_SRC_IP, 26, eth_nic_base); + /* zero checksum */ + eth_pio_write_byte(0, (TX_START << 8)+24, eth_nic_base); + eth_pio_write_byte(0, (TX_START << 8)+25, eth_nic_base); + + /* update IP packet len */ + eth_pio_write_byte(((28 + pktlen) >> 8) & 0xff, (TX_START << 8)+16, eth_nic_base); + eth_pio_write_byte( (28 + pktlen) & 0xff, (TX_START << 8)+17, eth_nic_base); + + /* update UDP len */ + eth_pio_write_byte((8 + pktlen) >> 8, (TX_START << 8)+38, eth_nic_base); + eth_pio_write_byte( 8 + pktlen, (TX_START << 8)+39, eth_nic_base); + + chksum = compute_ip_checksum_from_sram(14, 20, eth_nic_base); + + eth_pio_write_byte(chksum, (TX_START << 8)+24, eth_nic_base); + eth_pio_write_byte(chksum >> 8, (TX_START << 8)+25, eth_nic_base); +} + +#endif + +void ne2k_transmit(unsigned int eth_nic_base) { + unsigned int pktsize; + unsigned int len = get_count(eth_nic_base); + + // so place whole header inside chip buffer + ns8390_tx_header(eth_nic_base, len); + + // commit sending now + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + outb(TX_START, eth_nic_base + D8390_P0_TPSR); + + pktsize = 42 + len; + if (pktsize < 64) + pktsize = 64; + + outb(pktsize, eth_nic_base + D8390_P0_TBCR0); + outb(pktsize >> 8, eth_nic_base + D8390_P0_TBCR1); + + outb(D8390_ISR_PTX, eth_nic_base + D8390_P0_ISR); + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + /* wait for operation finish */ + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_PTX) != D8390_ISR_PTX) ; + + set_count(eth_nic_base, 0); +} + +#ifdef __PRE_RAM__ + +#include + +static void ns8390_reset(unsigned int eth_nic_base) +{ + int i; + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STP, eth_nic_base + D8390_P0_COMMAND); + + outb(0x48, eth_nic_base + D8390_P0_DCR); + outb(0, eth_nic_base + D8390_P0_RBCR0); + outb(0, eth_nic_base + D8390_P0_RBCR1); + outb(0x20, eth_nic_base + D8390_P0_RCR); + outb(2, eth_nic_base + D8390_P0_TCR); + outb(TX_START, eth_nic_base + D8390_P0_TPSR); + outb(RX_START, eth_nic_base + D8390_P0_PSTART); + outb(MEM_SIZE, eth_nic_base + D8390_P0_PSTOP); + outb(MEM_SIZE - 1, eth_nic_base + D8390_P0_BOUND); + outb(0xFF, eth_nic_base + D8390_P0_ISR); + outb(0, eth_nic_base + D8390_P0_IMR); + + outb(D8390_COMMAND_PS1 | + D8390_COMMAND_RD2 | D8390_COMMAND_STP, + eth_nic_base + D8390_P0_COMMAND); + + for (i = 0; i < ETH_ALEN; i++) + outb(0x0C, eth_nic_base + D8390_P1_PAR0 + i); + + for (i = 0; i < ETH_ALEN; i++) + outb(0xFF, eth_nic_base + D8390_P1_MAR0 + i); + + outb(RX_START, eth_nic_base + D8390_P1_CURR); + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_RD2 | D8390_COMMAND_STA, + eth_nic_base + D8390_P0_COMMAND); + outb(0xFF, eth_nic_base + D8390_P0_ISR); + outb(0, eth_nic_base + D8390_P0_TCR); + outb(4, eth_nic_base + D8390_P0_RCR); + set_count(eth_nic_base, 0); +} + + +int ne2k_init(unsigned int eth_nic_base) { + + device_t dev; + unsigned char c; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(0x10ec, + 0x8029), 0); + + if (dev == PCI_DEV_INVALID) + return 0; + + pci_write_config32(dev, 0x10, eth_nic_base | 1 ); + pci_write_config8(dev, 0x4, 0x1); + + c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); + outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); + + (void) inb(0x84); + + outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); + + outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); + outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); + + ns8390_reset(eth_nic_base); + return 1; +} + +#else + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static void read_resources(struct device *dev) +{ + struct resource *res; + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = CONFIG_CONSOLE_NE2K_IO_PORT; + res->size = 32; + res->align = 5; + res->gran = 5; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + return; +} + + +static struct device_operations si_sata_ops = { + .read_resources = read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +static const struct pci_driver si_sata_driver __pci_driver = { + .ops = &si_sata_ops, + .vendor = 0x10ec, + .device = 0x8029, +}; + +#endif Added: trunk/src/lib/ns8390.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/lib/ns8390.h Fri Jul 16 22:02:09 2010 (r5666) @@ -0,0 +1,110 @@ +/************************************************************************** +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: Jun/94 + +**************************************************************************/ + +//FILE_LICENCE ( BSD2 ); + +#define VENDOR_NONE 0 +#define VENDOR_WD 1 +#define VENDOR_NOVELL 2 +#define VENDOR_3COM 3 + +#define FLAG_PIO 0x01 +#define FLAG_16BIT 0x02 +#define FLAG_790 0x04 + +#define MEM_8192 32 +#define MEM_16384 64 +#define MEM_32768 128 + +#define ISA_MAX_ADDR 0x400 + +/************************************************************************** +NE1000/2000 definitions +**************************************************************************/ +#define NE_ASIC_OFFSET 0x10 +#define NE_RESET 0x0F /* Used to reset card */ +#define NE_DATA 0x00 /* Used to read/write NIC mem */ + +#define COMPEX_RL2000_TRIES 200 + +/************************************************************************** +8390 Register Definitions +**************************************************************************/ +#define D8390_P0_COMMAND 0x00 +#define D8390_P0_PSTART 0x01 +#define D8390_P0_PSTOP 0x02 +#define D8390_P0_BOUND 0x03 +#define D8390_P0_TSR 0x04 +#define D8390_P0_TPSR 0x04 +#define D8390_P0_TBCR0 0x05 +#define D8390_P0_TBCR1 0x06 +#define D8390_P0_ISR 0x07 +#define D8390_P0_RSAR0 0x08 +#define D8390_P0_RSAR1 0x09 +#define D8390_P0_RBCR0 0x0A +#define D8390_P0_RBCR1 0x0B +#define D8390_P0_RSR 0x0C +#define D8390_P0_RCR 0x0C +#define D8390_P0_TCR 0x0D +#define D8390_P0_DCR 0x0E +#define D8390_P0_IMR 0x0F +#define D8390_P1_COMMAND 0x00 +#define D8390_P1_PAR0 0x01 +#define D8390_P1_PAR1 0x02 +#define D8390_P1_PAR2 0x03 +#define D8390_P1_PAR3 0x04 +#define D8390_P1_PAR4 0x05 +#define D8390_P1_PAR5 0x06 +#define D8390_P1_CURR 0x07 +#define D8390_P1_MAR0 0x08 + +#define D8390_COMMAND_PS0 0x0 /* Page 0 select */ +#define D8390_COMMAND_PS1 0x40 /* Page 1 select */ +#define D8390_COMMAND_PS2 0x80 /* Page 2 select */ +#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */ +#define D8390_COMMAND_RD1 0x10 +#define D8390_COMMAND_RD0 0x08 +#define D8390_COMMAND_TXP 0x04 /* transmit packet */ +#define D8390_COMMAND_STA 0x02 /* start */ +#define D8390_COMMAND_STP 0x01 /* stop */ + +#define D8390_RCR_MON 0x20 /* monitor mode */ + +#define D8390_DCR_FT1 0x40 +#define D8390_DCR_LS 0x08 /* Loopback select */ +#define D8390_DCR_WTS 0x01 /* Word transfer select */ + +#define D8390_ISR_PRX 0x01 /* successful recv */ +#define D8390_ISR_PTX 0x02 /* successful xmit */ +#define D8390_ISR_RXE 0x04 /* receive error */ +#define D8390_ISR_TXE 0x08 /* transmit error */ +#define D8390_ISR_OVW 0x10 /* Overflow */ +#define D8390_ISR_CNT 0x20 /* Counter overflow */ +#define D8390_ISR_RDC 0x40 /* Remote DMA complete */ +#define D8390_ISR_RST 0x80 /* reset */ + +#define D8390_RSTAT_PRX 0x01 /* successful recv */ +#define D8390_RSTAT_CRC 0x02 /* CRC error */ +#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */ +#define D8390_RSTAT_OVER 0x08 /* FIFO overrun */ + +#define D8390_TXBUF_SIZE 6 +#define D8390_RXBUF_END 32 +#define D8390_PAGE_SIZE 256 + +struct ringbuffer { + unsigned char status; + unsigned char next; + unsigned short len; +}; +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ + From r.marek at assembler.cz Fri Jul 16 22:04:04 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Fri, 16 Jul 2010 22:04:04 +0200 Subject: [coreboot] [RFC] Network console for coreboot In-Reply-To: References: <4C02BDA2.1030101@assembler.cz> <4C06CFD7.3010604@assembler.cz> <4C20790D.5030901@assembler.cz> <4C228991.4040101@assembler.cz> <4C3749D4.1080805@assembler.cz> <1278692845.25117.5.camel@ufo> Message-ID: <4C40BB34.60601@assembler.cz> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Thanks for the hints, I fixed that, Its there as 5666. If someone wants a RTL8029 cards please let me know. I will have like 20 of them. It could work on Soyo board too, however with Qemu the ROMCC runs out of regs. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkxAuzQACgkQ3J9wPJqZRNWd+gCgt/hjFb06uyOmL4Xhr8Aj8NDn opMAoItYgtdg+5e9MsAksaTBXrUxSqJG =YIaQ -----END PGP SIGNATURE----- From joe at settoplinux.org Sat Jul 17 01:00:15 2010 From: joe at settoplinux.org (Joseph Smith) Date: Fri, 16 Jul 2010 19:00:15 -0400 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <201007162135.59312.njacobs8@hetnet.nl> References: <201007062027.12484.njacobs8@hetnet.nl> <7789189772300c48365ef062f885e862@imap.1and1.com> <201007162135.59312.njacobs8@hetnet.nl> Message-ID: <4C40E47F.1040803@settoplinux.org> On 07/16/2010 03:35 PM, Nils wrote: > Hi Joseph, > > Op vrijdag 16 juli 2010 14:41:47 schreef u: >> On Tue, 6 Jul 2010 20:27:12 +0200, Nils wrote: >>> Ping!? >>> Could anybody tell me how to proceed? >>> Peter:did i gave the wrong answers? :) >>> >>> Thanks,Nils. >> >> Nils, >> I really would hate to see your great work go to the way side. >> It has been a few revisions since your original patch. >> As long as you can send a working/tested updated patch to the list: >> >> Acked-by: Joseph Smith > > Thanks for the heads up! > At the moment i have no time to update/test the patch, maybe in a few days. > I will delete the unused code if til then nobody speaks up/ objects. > And add the new line in Makefile.inc . > Maybe until then Peter finds some time to give some professional advice. > Thanks again for the ack. > No problem, I have a few GX2's myself that have coreboot writen on them but way to many other things going on now to study code vs datasheets to get familiar with the GX2. Like I said I would hate for you code to go to the way side. > > P.s. How is your paraflasher project doing? Do you have some programming > results already? No programming yet; still working on hardware design, I decided to make my own pcb's for it, something I have wanted to do for a long time. I have designed it with the gEDA tools (gschem, gsch2pcb, and PCB) which I have come to Love. Anyways the final harware should be kick ass. I have the programming for it in my head, just nothing on paper yet. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From njacobs8 at hetnet.nl Sat Jul 17 11:08:06 2010 From: njacobs8 at hetnet.nl (Nils) Date: Sat, 17 Jul 2010 11:08:06 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <4C40E47F.1040803@settoplinux.org> References: <201007062027.12484.njacobs8@hetnet.nl> <201007162135.59312.njacobs8@hetnet.nl> <4C40E47F.1040803@settoplinux.org> Message-ID: <201007171108.06952.njacobs8@hetnet.nl> Op zaterdag 17 juli 2010 01:00:15 schreef u: > > P.s. How is your paraflasher project doing? Do you have some programming > > results already? > > No programming yet; still working on hardware design, I decided to make > my own pcb's for it, something I have wanted to do for a long time. I > have designed it with the gEDA tools (gschem, gsch2pcb, and PCB) which I > have come to Love. Anyways the final harware should be kick ass. I have > the programming for it in my head, just nothing on paper yet. Nice! The last time i designed a pcb myself was ~20 years ago. It was a special and very expensive to buy type 1MB SIMM to expand my Philips 386 pc to 2MB! That were times. Nowadays i make my circuits mostly on breadboard. Nils. Ps:I hear that nowadays you can order PCB`s real cheap in china. But i didn`t use it for my simple designs yet as i found the shipping cost for 1 PCB to high. From peter at stuge.se Sat Jul 17 18:09:48 2010 From: peter at stuge.se (Peter Stuge) Date: Sat, 17 Jul 2010 18:09:48 +0200 Subject: [coreboot] gigabyte dual bios programming In-Reply-To: <4C3F4EF1.7030709@gmx.net> References: <20100713235728.30668.qmail@stuge.se> <4C3DAB7B.6040007@icyb.net.ua> <20100714202506.7146.qmail@stuge.se> <4C3ECC59.9060505@icyb.net.ua> <20100715142916.10804.qmail@stuge.se> <4C3F4EF1.7030709@gmx.net> Message-ID: <20100717160948.5701.qmail@stuge.se> Carl-Daniel Hailfinger wrote: > Did you know that SB700 (and later) has its own Dual BIOS mechanism? I did not. Do you know more details? //Peter From peter at stuge.se Sat Jul 17 18:53:08 2010 From: peter at stuge.se (Peter Stuge) Date: Sat, 17 Jul 2010 18:53:08 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <201007171108.06952.njacobs8@hetnet.nl> References: <201007062027.12484.njacobs8@hetnet.nl> <201007162135.59312.njacobs8@hetnet.nl> <4C40E47F.1040803@settoplinux.org> <201007171108.06952.njacobs8@hetnet.nl> Message-ID: <20100717165308.11449.qmail@stuge.se> Nils wrote: > Ps:I hear that nowadays you can order PCB`s real cheap in china. > But i didn`t use it for my simple designs yet as i found the > shipping cost for 1 PCB to high. There is certainly a market for small quantity PCBs. Competition has driven cost down. If you can wait for long(ish) delivery times then you can certainly order from China. Look for some local PCB houses, that offer cheap slow service. Here in Sweden I know a couple of alternatives ranging from ~3 week delivery Made in China to next-day delivery Made in my city. :) For low quantity stuff I've used the Olimex prototype PCB service a couple of times, and while it is not quite as nice as production PCBs I think it is still much better value for money than messing with chemicals in the kitchen. I also understand that Olimex have improved their processes a lot since my last orders. Their basic cost is ~30 USD for 160x100 mm of 2-layer PCB area IIRC. You can panel that however you want and they'll cut it up for you. http://olimex.com/pcb/ //Peter From ebiederm at xmission.com Sat Jul 17 22:23:09 2010 From: ebiederm at xmission.com (Eric W. Biederman) Date: Sat, 17 Jul 2010 13:23:09 -0700 Subject: [coreboot] 3 questions about coreboot In-Reply-To: (ali hagigat's message of "Thu\, 8 Jul 2010 23\:07\:51 -0800") References: <4C344D01.8010200@coresystems.de> <20100707172534.7831.qmail@stuge.se> Message-ID: ali hagigat writes: > Ok, thank you all for the replies, links and diagrams. But there are > still some ambiguities in memory read/write after reset which is done > by BIOS chip and then the memory controller !! > > Immediately after reset all memory read/write cycles are claimed by > BIOS chip ultimately. The first question is that: Is memory controller > enabled after reset before writing to its configuration space? If it > is enabled, how it does not claim for memory addresses after reset? > > If it is not enabled and we enable the memory controller by writing to > its configuration registers how we introduce the memory address range > used by BIOS chip here? Because the memory controller should not claim > the memory address range of the BIOS chip. > I had a general look at the configuration registers of the memory > controller, there is no register or registers to set this range of > address!! Besides there is no enable bit or something similar!! > > These questions are repeated for BIOS chip and the PCI device > connected to it. Do we have to write to their configuration registers > to specify a specific range of address? Otherwise both memory > controller and the PCI device connected to the BIOS chip will claim > for that address!! Because they are being situated at the same PCI > bus. If you really want to understand this I recommend picking a board that has a good coreboot port and getting the manuals of all of the parts and following the code through. Making things work in coreboot tends to be like attaching the mains to the breaker box, turn the power on at the breaker, and the flipping the light switch all to turn on a little light. It is very rarely as simple as going to the destination devices and looking at it. Eric From corey.osgood at gmail.com Sun Jul 18 11:54:08 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 18 Jul 2010 05:54:08 -0400 Subject: [coreboot] SPI in-system programming Message-ID: I need a way that I can test images without actually being in the same location as the board I'll be testing them on. What would you guys recommend for programming an SPI chip with it still on the motherboard? There is no ISP header, and the flash chip is socketed, the board will be a Zotac Atom/NM10 ITX board. I've seen programmers that explain how to isolate the signals so their programmer can be used to do it, but does it require a special programmer, or is it something that could be done with a $20 ebay programmer and a little wire? And can the board be operated with the programmer still attached? I'm getting a lot of conflicting info, hoping someone can clarify this. If this doesn't work out, how can I flip back and forth between a pair of SPI chips? Thanks, Corey From hagigatali at gmail.com Sun Jul 18 14:25:00 2010 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 18 Jul 2010 16:55:00 +0430 Subject: [coreboot] romcc.c Message-ID: What util/romcc/romcc.c does? It is over 25000 lines of code! -------------- next part -------------- An HTML attachment was scrubbed... URL: From nitr0 at seti.kr.ua Sun Jul 18 14:28:01 2010 From: nitr0 at seti.kr.ua (Andrew) Date: Sun, 18 Jul 2010 15:28:01 +0300 Subject: [coreboot] romcc.c In-Reply-To: References: Message-ID: <4C42F351.7060601@seti.kr.ua> 18.07.2010 15:25, ali hagigat ?????: > What util/romcc/romcc.c does? > It is over 25000 lines of code! > You tried to read romcc.1 ? :) From hagigatali at gmail.com Sun Jul 18 14:29:51 2010 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 18 Jul 2010 16:59:51 +0430 Subject: [coreboot] util files Message-ID: Can any one mention a short comment for each directory inside util/ directory like abuild, amdtools, cbfstool, ....., xcompile. What each tool does and what is its main functionality? I will be much appreciated. -------------- next part -------------- An HTML attachment was scrubbed... URL: From corey.osgood at gmail.com Sun Jul 18 15:09:03 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 18 Jul 2010 09:09:03 -0400 Subject: [coreboot] util files In-Reply-To: References: Message-ID: Please check the coreboot wiki, most of those utilities should have entries or are mentioned there. Some of them also have README files inside, which explain their purpose. If neither of those applies, then most likely it's either an obsolete tool, or something that was written for one specific board and then forgotten about. Any questions let us know ;) -Corey On Sun, Jul 18, 2010 at 8:29 AM, ali hagigat wrote: > Can any one mention a short comment for each directory inside util/ > directory like abuild, amdtools, cbfstool, ....., xcompile. > What each tool does and what is its main functionality? > > I will be much appreciated. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From r.marek at assembler.cz Sun Jul 18 15:33:14 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 18 Jul 2010 15:33:14 +0200 Subject: [coreboot] romcc.c In-Reply-To: References: Message-ID: <4C43029A.9040406@assembler.cz> Please ask smart questions, stupid questions will be ignored. Try to read this to get what I mean http://catb.org/esr/faqs/smart-questions.html Especially a section before you ask. Thanks, Rudolf From c-d.hailfinger.devel.2006 at gmx.net Sun Jul 18 18:20:54 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sun, 18 Jul 2010 18:20:54 +0200 Subject: [coreboot] SPI in-system programming In-Reply-To: References: Message-ID: <4C4329E6.9080307@gmx.net> Hi Corey, [adding flashrom at flashrom.org to CC] On 18.07.2010 11:54, Corey Osgood wrote: > I need a way that I can test images without actually being in the same > location as the board I'll be testing them on. What would you guys > recommend for programming an SPI chip with it still on the > motherboard? flashrom. > There is no ISP header, and the flash chip is socketed, > the board will be a Zotac Atom/NM10 ITX board. You could stack two SPI chips easily, and switch the CS# pin. > I've seen programmers > that explain how to isolate the signals so their programmer can be > used to do it, but does it require a special programmer, or is it > something that could be done with a $20 ebay programmer and a little > wire? And can the board be operated with the programmer still > attached? I'm getting a lot of conflicting info, hoping someone can > clarify this. > If you want to reflash with an external programmer, it gets complicated really fast. Reflashing a chip which is connected to a running system is extremely risky, and you may fry your board. One way around that is to hook some buffer in between, but you'd need one which is fast enough for 33 MHz operation (and you want a safety margin to not disturb communication, so shooting for one with a delay around 10 ns is a good idea), and then electrically disconnect the flash chip from the board while flashing. Maybe flashing a chip in a powered down system with an external programmer works, but you can't be sure if the external programmer has enough power to feed 3.3V to the whole board (if the flash chip is connected there) and you may see undesirable side effects as well. > If this doesn't work out, how can I flip back and forth between a pair > of SPI chips? > Switching the CS# pin should do the trick. Regards, Carl-Daniel -- http://www.hailfinger.org/ From flashrom at mkarcher.dialup.fu-berlin.de Sun Jul 18 18:30:56 2010 From: flashrom at mkarcher.dialup.fu-berlin.de (Michael Karcher) Date: Sun, 18 Jul 2010 18:30:56 +0200 Subject: [coreboot] [flashrom] SPI in-system programming In-Reply-To: <4C4329E6.9080307@gmx.net> References: <4C4329E6.9080307@gmx.net> Message-ID: <1279470656.6151.237.camel@aquila> Am Sonntag, den 18.07.2010, 18:20 +0200 schrieb Carl-Daniel Hailfinger: > > There is no ISP header, and the flash chip is socketed, > > the board will be a Zotac Atom/NM10 ITX board. > You could stack two SPI chips easily, and switch the CS# pin. Don't forget to switch the inactive chip to a pull-up. Regards, Michael Karcher From r.marek at assembler.cz Sun Jul 18 19:11:13 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Sun, 18 Jul 2010 19:11:13 +0200 Subject: [coreboot] SPI in-system programming In-Reply-To: <4C4329E6.9080307@gmx.net> References: <4C4329E6.9080307@gmx.net> Message-ID: <4C4335B1.8050906@assembler.cz> Hi, I guess you need to have some driver to disconnect the bus from chipset. And maybe some diode not to power on whole MB while doing ISP when MB is off Check this: www.dediprog.com/chipset/via8237s.pdf Maybe you will need tri state buffer? Thanks, Rudolf From juhe at iki.fi Sun Jul 18 20:22:13 2010 From: juhe at iki.fi (Juhana Helovuo) Date: Sun, 18 Jul 2010 21:22:13 +0300 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: <3C92B942FD2F45A78D16F334E642629B@chimp> References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> Message-ID: <1279477333.9331.32.camel@bart> On Thu, 2010-06-17 at 07:31 -0600, Myles Watson wrote: > > Yes, here it is attached. It is copied and modified from AMD Tilapia > > mainboard, because that seemed to be a close relative. > Thanks. > > > Meanwhile, I added call to it8712f_kill_watchdog() , like Rudolf Marek > > suggested. That changed the behavior so that the machine no longer > > reboots in the middle of iterating through PCI busses and devices, but > > instead it seems to go on iterating infinitely, or presumably until > > malloc runs out of memory. > OK Hello again, Infinitely looping PCI scan in pci_device.c was resolved: I added the following lines to the beginning of pci_scan_bus: // Maximum sane devfn is 0xFF if (max_devfn > 0xff) { printk(BIOS_DEBUG, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n"); max_devfn=0xff; } And then the relevant part of the log is: PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 It seems that the scan loop was not infinite after all, but just tried to enumerate devices from 0 to 0xffffffff, which seemed like inifinity. I could not find out who calls pci_scan_bus, nor where does the too large upper limit come from. Now the boot process goes through bus probing and starts enabling devices. This goes on until it is time to enable to LPC controller, which I suppose is the bridge to the IT8712F Super I/O -chip. At that point the boot process freezes, or at least there is no more serial output. I added some debug printouts as follows: [src/southbridge/amd/sb700/sb700_lpc.c] static void lpc_init(device_t dev) { u8 byte; u32 dword; device_t sm_dev; printk(BIOS_DEBUG, "sb700 entering lpc_init\n"); /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); /* Initialize isa dma */ printk(BIOS_DEBUG, "sb700 initializing isa dma\n"); isa_dma_init(); printk(BIOS_DEBUG, "sb700 isa dma initialized\n"); /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); printk(BIOS_DEBUG, "sb700 DMA enabled on LPC bus\n"); /* Disable the timeout mechanism on LPC */ byte = pci_read_config8(dev, 0x48); byte &= ~(1 << 7); pci_write_config8(dev, 0x48, byte); printk(BIOS_DEBUG, "sb700 LPC Timeout disabled\n"); /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); printk(BIOS_DEBUG, "sb700 exiting lpc_init\n"); } And the resulting end of boot log is: [...cut...] PCI: 00:14.1 init Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 14769 + align -> fff147c0 Check fallback/coreboot_ram CBFS: follow chain: fff147c0 + 38 + ddc2 + align -> fff225c0 Check fallback/payload CBFS: follow chain: fff225c0 + 38 + 22483 + align -> fff44a80 Check CBFS: follow chain: fff44a80 + 28 + bb286 + align -> fffffd40 CBFS: Could not find file pci1002,439c.rom PCI: 00:14.2 init base = 0xd4200000 codec_mask = 05 2(th) codec viddid: ffffffff 0(th) codec viddid: ffffffff PCI: 00:14.3 init sb700 entering lpc_init sb700 initializing isa dma [log ends here] PCI tree with the factory BIOS is: # lspci -tvnn -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] +-01.0-[0000:01]--+-05.0 ATI Technologies Inc Device [1002:9710] | \-05.1 ATI Technologies Inc Device [1002:970f] +-0a.0-[0000:02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [IDE mode] [1002:4390] +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] +-14.4-[0000:03]-- +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] So it seems that something goes wrong inside isa_dma_init(); Now I am not sure what I could try next. As the LPC is needed for Super I/O access, it seems like it cannot be just left out, and configuring the LPC controller to "off" will also kill the serial port. Any suggestions? Best regards, Juhana Helovuo From ebiederm at xmission.com Sun Jul 18 21:19:33 2010 From: ebiederm at xmission.com (Eric W. Biederman) Date: Sun, 18 Jul 2010 12:19:33 -0700 Subject: [coreboot] romcc.c In-Reply-To: (ali hagigat's message of "Sun\, 18 Jul 2010 16\:55\:00 +0430") References: Message-ID: ali hagigat writes: > What util/romcc/romcc.c does? > It is over 25000 lines of code! It is a C compiler. At 25000 lines of code it pretty small for a C compiler ;) Eric From corey.osgood at gmail.com Sun Jul 18 21:41:33 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Sun, 18 Jul 2010 15:41:33 -0400 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: <1279477333.9331.32.camel@bart> References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> <1279477333.9331.32.camel@bart> Message-ID: The file that you're looking for is src/pc80/isa-dma.c. I suspect that isa dma init isn't actually shutting the system down, just resetting whatever COM you're getting serial output from. Either comment out that dma port, or try re-initializing the serial console after doing isa_dma_init(). -Corey On Sun, Jul 18, 2010 at 2:22 PM, Juhana Helovuo wrote: > On Thu, 2010-06-17 at 07:31 -0600, Myles Watson wrote: >> > Yes, here it is attached. It is copied and modified from AMD Tilapia >> > mainboard, because that seemed to be a close relative. >> Thanks. >> >> > Meanwhile, I added call to it8712f_kill_watchdog() , like Rudolf Marek >> > suggested. That changed the behavior so that the machine no longer >> > reboots in the middle of iterating through PCI busses and devices, but >> > instead it seems to go on iterating infinitely, or presumably until >> > malloc runs out of memory. >> OK > > Hello again, > > Infinitely looping PCI scan in pci_device.c was resolved: > > I added the following lines to the beginning of pci_scan_bus: > > ? ? ? ?// Maximum sane devfn is 0xFF > ? ? ? ?if (max_devfn > 0xff) { > ? ? ? ? ?printk(BIOS_DEBUG, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n"); > ? ? ? ? ?max_devfn=0xff; > ? ? ? ?} > > And then the relevant part of the log is: > > PCI: pci_scan_bus for bus 00 > PCI: pci_scan_bus limits devfn 0 - devfn ffffffff > PCI: pci_scan_bus upper limit too big. Using 0xff. > POST: 0x24 > > It seems that the scan loop was not infinite after all, but just tried > to enumerate devices from 0 to 0xffffffff, which seemed like inifinity. > I could not find out who calls pci_scan_bus, nor where does the too > large upper limit come from. > > > Now the boot process goes through bus probing and starts enabling > devices. This goes on until it is time to enable to LPC controller, > which I suppose is the bridge to the IT8712F Super I/O -chip. At that > point the boot process freezes, or at least there is no more serial > output. I added some debug printouts as follows: > > [src/southbridge/amd/sb700/sb700_lpc.c] > > static void lpc_init(device_t dev) > { > ? ? ? ?u8 byte; > ? ? ? ?u32 dword; > ? ? ? ?device_t sm_dev; > > ? ? ? ?printk(BIOS_DEBUG, "sb700 entering lpc_init\n"); > ? ? ? ?/* Enable the LPC Controller */ > ? ? ? ?sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); > ? ? ? ?dword = pci_read_config32(sm_dev, 0x64); > ? ? ? ?dword |= 1 << 20; > ? ? ? ?pci_write_config32(sm_dev, 0x64, dword); > > ? ? ? ?/* Initialize isa dma */ > ? ? ? ?printk(BIOS_DEBUG, "sb700 initializing isa dma\n"); > ? ? ? ?isa_dma_init(); > ? ? ? ?printk(BIOS_DEBUG, "sb700 isa dma initialized\n"); > > ? ? ? ?/* Enable DMA transaction on the LPC bus */ > ? ? ? ?byte = pci_read_config8(dev, 0x40); > ? ? ? ?byte |= (1 << 2); > ? ? ? ?pci_write_config8(dev, 0x40, byte); > ? ? ? ?printk(BIOS_DEBUG, "sb700 DMA enabled on LPC bus\n"); > > ? ? ? ?/* Disable the timeout mechanism on LPC */ > ? ? ? ?byte = pci_read_config8(dev, 0x48); > ? ? ? ?byte &= ~(1 << 7); > ? ? ? ?pci_write_config8(dev, 0x48, byte); > ? ? ? ?printk(BIOS_DEBUG, "sb700 LPC Timeout disabled\n"); > > ? ? ? ?/* Disable LPC MSI Capability */ > ? ? ? ?byte = pci_read_config8(dev, 0x78); > ? ? ? ?byte &= ~(1 << 1); > ? ? ? ?pci_write_config8(dev, 0x78, byte); > ? ? ? ?printk(BIOS_DEBUG, "sb700 exiting lpc_init\n"); > } > > And the resulting end of boot log is: > > [...cut...] > PCI: 00:14.1 init > Check CBFS header at fffffd2e > magic is 4f524243 > Found CBFS header at fffffd2e > Check fallback/romstage > CBFS: follow chain: fff00000 + 38 + 14769 + align -> fff147c0 > Check fallback/coreboot_ram > CBFS: follow chain: fff147c0 + 38 + ddc2 + align -> fff225c0 > Check fallback/payload > CBFS: follow chain: fff225c0 + 38 + 22483 + align -> fff44a80 > Check > CBFS: follow chain: fff44a80 + 28 + bb286 + align -> fffffd40 > CBFS: ?Could not find file pci1002,439c.rom > PCI: 00:14.2 init > base = 0xd4200000 > codec_mask = 05 > 2(th) codec viddid: ffffffff > 0(th) codec viddid: ffffffff > PCI: 00:14.3 init > sb700 entering lpc_init > sb700 initializing isa dma > [log ends here] > > PCI tree with the factory BIOS is: > > # lspci -tvnn > -[0000:00]-+-00.0 ?Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] > ? ? ? ? ? +-01.0-[0000:01]--+-05.0 ?ATI Technologies Inc Device [1002:9710] > ? ? ? ? ? | ? ? ? ? ? ? ? ? \-05.1 ?ATI Technologies Inc Device [1002:970f] > ? ? ? ? ? +-0a.0-[0000:02]----00.0 ?Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > ? ? ? ? ? +-11.0 ?ATI Technologies Inc SB700/SB800 SATA Controller [IDE mode] [1002:4390] > ? ? ? ? ? +-12.0 ?ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > ? ? ? ? ? +-12.1 ?ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > ? ? ? ? ? +-12.2 ?ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > ? ? ? ? ? +-13.0 ?ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > ? ? ? ? ? +-13.1 ?ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > ? ? ? ? ? +-13.2 ?ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > ? ? ? ? ? +-14.0 ?ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > ? ? ? ? ? +-14.1 ?ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] > ? ? ? ? ? +-14.2 ?ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > ? ? ? ? ? +-14.3 ?ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] > ? ? ? ? ? +-14.4-[0000:03]-- > ? ? ? ? ? +-14.5 ?ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] > ? ? ? ? ? +-18.0 ?Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] > ? ? ? ? ? +-18.1 ?Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] > ? ? ? ? ? +-18.2 ?Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] > ? ? ? ? ? +-18.3 ?Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] > ? ? ? ? ? \-18.4 ?Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] > > > So it seems that something goes wrong inside isa_dma_init(); > > Now I am not sure what I could try next. As the LPC is needed for Super > I/O access, it seems like it cannot be just left out, and configuring > the LPC controller to "off" will also kill the serial port. > > Any suggestions? > > Best regards, > Juhana Helovuo > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From corey.osgood at gmail.com Mon Jul 19 11:20:37 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 19 Jul 2010 05:20:37 -0400 Subject: [coreboot] SPI in-system programming In-Reply-To: <4C4335B1.8050906@assembler.cz> References: <4C4329E6.9080307@gmx.net> <4C4335B1.8050906@assembler.cz> Message-ID: On Sun, Jul 18, 2010 at 1:11 PM, Rudolf Marek wrote: > Hi, > > I guess you need to have some driver to disconnect the bus from chipset. > And maybe some diode not to power on whole MB while doing ISP when MB is off > Check this: > > www.dediprog.com/chipset/via8237s.pdf > > Maybe you will need tri state buffer? I've seen that, along with the intel version: http://www.dediprog.com/chipset/In%20System%20Programming%20Solution%20for%20IA%20Reference%20and%20Validation%20Boards.pdf But they rely on an SPI header and the reference design, neither of which I'll have. I was hoping someone had some solution for hooking a programmer directly to a board, but with switching chips so easy I can't imagine why they'd bother. -Corey From corey.osgood at gmail.com Mon Jul 19 11:17:05 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 19 Jul 2010 05:17:05 -0400 Subject: [coreboot] [flashrom] SPI in-system programming In-Reply-To: <1279470656.6151.237.camel@aquila> References: <4C4329E6.9080307@gmx.net> <1279470656.6151.237.camel@aquila> Message-ID: On Sun, Jul 18, 2010 at 12:30 PM, Michael Karcher wrote: > Am Sonntag, den 18.07.2010, 18:20 +0200 schrieb Carl-Daniel Hailfinger: >> > There is no ISP header, and the flash chip is socketed, >> > the board will be a Zotac Atom/NM10 ITX board. >> You could stack two SPI chips easily, and switch the CS# pin. > > Don't forget to switch the inactive chip to a pull-up. > Thanks for the info, didn't realize it was quite that simple, looks like that's the route I'll be going. -Corey From caibaiyin.pku at gmail.com Mon Jul 19 12:42:29 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Mon, 19 Jul 2010 18:42:29 +0800 Subject: [coreboot] SPI in-system programming In-Reply-To: References: <4C4329E6.9080307@gmx.net> <4C4335B1.8050906@assembler.cz> Message-ID: SF100 can fit your requirement with testclip SO8, you can see the details from: http://www.dediprog.com/SPI-flash-in-circuit-programming/ISP-Testclip-SO8 2010/7/19 Corey Osgood > On Sun, Jul 18, 2010 at 1:11 PM, Rudolf Marek > wrote: > > Hi, > > > > I guess you need to have some driver to disconnect the bus from chipset. > > And maybe some diode not to power on whole MB while doing ISP when MB is > off > > Check this: > > > > www.dediprog.com/chipset/via8237s.pdf > > > > Maybe you will need tri state buffer? > > I've seen that, along with the intel version: > > > http://www.dediprog.com/chipset/In%20System%20Programming%20Solution%20for%20IA%20Reference%20and%20Validation%20Boards.pdf > > But they rely on an SPI header and the reference design, neither of > which I'll have. I was hoping someone had some solution for hooking a > programmer directly to a board, but with switching chips so easy I > can't imagine why they'd bother. > > -Corey > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Mon Jul 19 12:54:43 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Mon, 19 Jul 2010 18:54:43 +0800 Subject: [coreboot] GIGABYTE GA785GMT-UD2H coreboot porting problems Message-ID: hi, i am trying to port coreboot to 785/710 mainboard which is gigabyte ga785gmt-ud2h. the problem now is it reboots while decompress cbfs by executing "memcpy". i would like to doubt that ddr3 is not configured correctly. the log is attached. any suggestion is welcome. thanks -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 FIDVID on BSP, APIC_id: 00 BSP fid = 10500 common_fid = 10500 FID Change Node:00, F3xD4: c8810f25 End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode fill_mem_ctrl() raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=2 DIMMPresence: DIMMPresent=2 DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=2 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=1 DIMMPresence: MAload[1]=8 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 2 AutoCycTiming: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 1 SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 80 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: a0092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 8010000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 80 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 3fffff BottomIO: e00000 Node: 00 base: 03 limit: 3fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:400000 CPUMemTyping: Bottom32bIO:400000 CPUMemTyping: Bottom40bIO:0 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1000 TrainRcvrEn: ErrStatus 80 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 FIDVID on BSP, APIC_id: 00 BSP fid = 10500 common_fid = 10500 FID Change Node:00, F3xD4: c8810f25 End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode fill_mem_ctrl() raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=2 DIMMPresence: DIMMPresent=2 DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=2 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=1 DIMMPresence: MAload[1]=8 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 2 AutoCycTiming: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 1 SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 80 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: a0092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 8010000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 80 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 3fffff BottomIO: e00000 Node: 00 base: 03 limit: 3fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:400000 CPUMemTyping: Bottom32bIO:400000 CPUMemTyping: Bottom40bIO:0 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1000 TrainRcvrEn: ErrStatus 80 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1000 InterleaveNodes_D: ErrStatus 80 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 80 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 17191 + align -> fff17200 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000 CBFS: got here src=fff17254,dest=200000,len=30000 coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 FIDVID on BSP, APIC_id: 00 BSP fid = 10500 common_fid = 10500 FID Change Node:00, F3xD4: c8810f25 End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03000714 F3xDC: 0000522c core0 started: start_other_cores() init node: 00 cores: 00 started ap apicid: rs780_early_setup() get_cpu_rev EAX=0x100f63. CPU Rev is K8_10. fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840 End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode fill_mem_ctrl() raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=2 DIMMPresence: DIMMPresent=2 DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=2 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=1 DIMMPresence: MAload[1]=8 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 2 AutoCycTiming: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 1 SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 80 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: a0092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 8010000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 80 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 3fffff BottomIO: e00000 Node: 00 base: 03 limit: 3fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:400000 CPUMemTyping: Bottom32bIO:400000 CPUMemTyping: Bottom40bIO:0 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1000 TrainRcvrEn: ErrStatus 80 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1000 InterleaveNodes_D: ErrStatus 80 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 80 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 17191 + align -> fff17200 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000 CBFS: got here src=fff17254,dest=200000,len=30000 coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting... BSP Family_Model: 00100f63 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success From svn at coreboot.org Mon Jul 19 16:00:01 2010 From: svn at coreboot.org (coreboot tracker) Date: Mon, 19 Jul 2010 16:00:01 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From svn at coreboot.org Mon Jul 19 19:56:39 2010 From: svn at coreboot.org (repository service) Date: Mon, 19 Jul 2010 19:56:39 +0200 Subject: [coreboot] [FILO] r134 - trunk/filo/util/xcompile Message-ID: Author: mjones Date: Mon Jul 19 19:56:38 2010 New Revision: 134 URL: http://tracker.coreboot.org/trac/filo/changeset/134 Log: This patch fixes xcompile for filo located in coreboot/payloads. This goes with the follow-on patch to put filo and libpayload in the same place. Signed-off-by: Cai Bai Yin Acked-by: Marc Jones Modified: trunk/filo/util/xcompile/xcompile Modified: trunk/filo/util/xcompile/xcompile ============================================================================== --- trunk/filo/util/xcompile/xcompile Thu Jun 3 19:36:15 2010 (r133) +++ trunk/filo/util/xcompile/xcompile Mon Jul 19 19:56:38 2010 (r134) @@ -41,7 +41,7 @@ # This should be a loop over all supported architectures TARCH=i386 TWIDTH=32 -for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do +for gccprefixes in `pwd`/../../util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi From marcj303 at gmail.com Mon Jul 19 19:57:26 2010 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 19 Jul 2010 11:57:26 -0600 Subject: [coreboot] filo xcompile patch In-Reply-To: References: Message-ID: On Thu, Jul 15, 2010 at 8:42 PM, baiyin cai wrote: > this patch is used for filo xcompile fix. > > Signed-off-by: Cai Bai Yin Acked-by: Marc Jones r134 -- http://se-eng.com From svn at coreboot.org Mon Jul 19 20:33:46 2010 From: svn at coreboot.org (repository service) Date: Mon, 19 Jul 2010 20:33:46 +0200 Subject: [coreboot] [FILO] r135 - in trunk/filo: . util/kconfig Message-ID: Author: mjones Date: Mon Jul 19 20:33:46 2010 New Revision: 135 URL: http://tracker.coreboot.org/trac/filo/changeset/135 Log: This patch builds libpayload for filo from filo. There are two steps: 1) load libpayload kconfig while configuring filo. 2) build libpayload before filo building. it can be used by : $MAKE LIBCONFIG_PATH=/path/to/libpayload" The filo copy of libpayload is kept locally in the build directory for the next rebuild. Signed-off-by: Cai Bai Yin Acked-by: Patrick Georgi Acked-by: Marc Jones Modified: trunk/filo/Makefile trunk/filo/util/kconfig/Makefile Modified: trunk/filo/Makefile ============================================================================== --- trunk/filo/Makefile Mon Jul 19 19:56:38 2010 (r134) +++ trunk/filo/Makefile Mon Jul 19 20:33:46 2010 (r135) @@ -24,6 +24,7 @@ export srck := $(src)/util/kconfig export obj := $(src)/build export objk := $(src)/build/util/kconfig +export LIBCONFIG_PATH := $(src)/../libpayload export KERNELVERSION := $(PROGRAM_VERSION) export KCONFIG_AUTOHEADER := $(obj)/config.h @@ -102,19 +103,29 @@ TARGET = $(obj)/filo.elf +HAVE_LIBCONFIG := $(wildcard $(LIBCONFIG_PATH)) + +all: prepare $(obj)/version.h $(TARGET) + + HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD)) -ifeq ($(strip $(HAVE_LIBPAYLOAD)),) -all: - @printf "\nError: libpayload is not installed!\nexpected: $(LIBPAYLOAD).\n" +ifneq ($(strip $(HAVE_LIBPAYLOAD)),) +libpayload: + @printf "Found Libpayload $(LIBPAYLOAD).\n" else -all: prepare $(obj)/version.h $(TARGET) +libpayload: $(src)/$(LIB_CONFIG) + $(Q)printf "building libpayload.\n" + $(Q)make -C $(LIBCONFIG_PATH) distclean + $(Q)cp lib.config $(LIBCONFIG_PATH)/.config + $(Q)make -C $(LIBCONFIG_PATH) oldconfig + $(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(src)/build install endif -$(obj)/filo: $(src)/.config $(OBJS) +$(obj)/filo: $(src)/.config $(OBJS) libpayload $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC) -$(TARGET): $(obj)/filo +$(TARGET): $(obj)/filo libpayload $(Q)cp $(obj)/filo $@ $(Q)$(NM) $(obj)/filo | sort > $(obj)/filo.map $(Q)printf " STRIP $(subst $(shell pwd)/,,$(@))\n" @@ -122,7 +133,7 @@ include util/kconfig/Makefile -$(obj)/%.o: $(src)/%.c +$(obj)/%.o: $(src)/%.c libpayload $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $< @@ -148,7 +159,7 @@ distclean: clean $(Q)rm -rf build - $(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* + $(Q)rm -f .config lib.config .config.old ..config.tmp .kconfig.d .tmpconfig* FORCE: Modified: trunk/filo/util/kconfig/Makefile ============================================================================== --- trunk/filo/util/kconfig/Makefile Mon Jul 19 19:56:38 2010 (r134) +++ trunk/filo/util/kconfig/Makefile Mon Jul 19 20:33:46 2010 (r135) @@ -12,23 +12,161 @@ Kconfig := Config.in +FILO_CONFIG := $(src)/.config +LIB_CONFIG := $(src)/lib.config +HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG)) +HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG)) + +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) xconfig: prepare $(objk)/qconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) $(Q)$(objk)/qconf $(Kconfig) +else +xconfig: prepare $(objk)/qconf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else +xconfig: prepare $(objk)/qconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/qconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)$(objk)/qconf $(Kconfig) +endif +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) +gconfig: prepare $(objk)/gconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) + $(Q)$(objk)/gconf $(Kconfig) +else +gconfig: prepare $(objk)/gconf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else gconfig: prepare $(objk)/gconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/gconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" $(Q)$(objk)/gconf $(Kconfig) +endif +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) +menuconfig: prepare $(objk)/mconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) + $(Q)$(objk)/mconf $(Kconfig) +else +menuconfig: prepare $(objk)/mconf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else menuconfig: prepare $(objk)/mconf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/mconf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" $(Q)$(objk)/mconf $(Kconfig) +endif +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) config: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) $(Q)$(objk)/conf $(Kconfig) +else +config: prepare $(objk)/conf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else +config: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/conf $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)$(objk)/conf $(Kconfig) +endif +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) +oldconfig: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) + $(Q)$(objk)/conf -o $(Kconfig) +else oldconfig: prepare $(objk)/conf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else +oldconfig: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/conf -o $(LIBCONFIG_PATH)/Config.in + $(Q)mv .config $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" $(Q)$(objk)/conf -o $(Kconfig) +endif +ifneq ($(strip $(HAVE_FILO_CONFIG)),) +ifneq ($(strip $(HAVE_LIB_CONFIG)),) silentoldconfig: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)mv $(FILO_CONFIG) $(FILO_CONFIG)."temp" + $(Q)mv $(LIB_CONFIG) $(FILO_CONFIG) + $(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in + $(Q)mv $(FILO_CONFIG) $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)mv $(FILO_CONFIG)."temp" $(FILO_CONFIG) $(Q)$(objk)/conf -s $(Kconfig) +else +silentoldconfig: prepare $(objk)/conf + $(Q)printf "Lost libpayload config file.\n" + $(Q)rm -f $(FILO_CONFIG) +endif +else +silentoldconfig: prepare $(objk)/conf + $(Q)printf "Libpayload config for FILO.\n" + $(Q)$(objk)/conf -s $(LIBCONFIG_PATH)/Config.in + $(Q)mv .config $(LIB_CONFIG) + $(Q)printf "Libpayload config done.\n" + $(Q)$(objk)/conf -s $(Kconfig) + +endif # --- UNUSED, ignore ---------------------------------------------------------- # Create new linux.pot file From marcj303 at gmail.com Mon Jul 19 20:33:58 2010 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 19 Jul 2010 12:33:58 -0600 Subject: [coreboot] filo kconfig patch of libpayload In-Reply-To: References: <4C3CD439.1090205@georgi-clan.de> Message-ID: On Wed, Jul 14, 2010 at 5:26 PM, baiyin cai wrote: > hi patrick, > ?? thanks for your kindly suggestions. That's will be much helpful for me. I > would take > that into consideration. > > Signed-off-by: Cai Bai Yin >>Acked-by: Patrick Georgi Acked-by: Marc Jones r135 -- http://se-eng.com From marcj303 at gmail.com Mon Jul 19 23:19:25 2010 From: marcj303 at gmail.com (Marc Jones) Date: Mon, 19 Jul 2010 15:19:25 -0600 Subject: [coreboot] [PATCH]Jetway PA78VM5 In-Reply-To: References: Message-ID: On Thu, Jul 15, 2010 at 2:01 AM, Qing Pei Wang wrote: > hi all, > ?? in order to make the code much clear, i update the patch which sent > yesterday to make all messages fit for "PA78VM5". > > Signed-off-by Wang Qing Pei > Qing Pei, Can you break up this patch into smaller parts, fintek sio and mainboard? That would make it easier to review. Also, Can you give a summary of what the code supports. What works and what doesn't. What about internal graphics, pci e slots etc? Here are a few items to look at: Do you need the mb_sysconf.h file? I don't think that the 8132 and 8111 stuff is needed on your platform. In devicetree.cb, You don't need multiple 18.0 devices. romstage.c +//used by incoherent_ht +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 0 Are these used? I think that they may be outdated. Maybe make a patch for all fam10 platforms? +//#include "northbridge/amd/amdht/ht_wrapper.c" +//#include "northbridge/amd/amdfam10/raminit_amdmct.c" +//#include "cpu/amd/model_10xxx/fidvid.c" +//#include "spd_addr.h" Remove these old includes that are commented out. Remove spd_addr.h file since it isn't used. chip.h +// int fixup_scsi; +// int fixup_vga; Remove these old lines. I don't think that they are used for anything in 780/700. Marc -- http://se-eng.com From hagigatali at gmail.com Tue Jul 20 13:14:17 2010 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 20 Jul 2010 15:44:17 +0430 Subject: [coreboot] compiling coreboot Message-ID: If i execute only this command at the root folder of Coreboot source tree : make Will the project be compiled with GCC of the system or GCC of the system will be patched and changed or it will be compiled exactly with regular GCC of the linux operating system? Besides will be the object files in elf format and when they are linked? Is there any possibility for other formats? -------------- next part -------------- An HTML attachment was scrubbed... URL: From r.marek at assembler.cz Tue Jul 20 15:52:16 2010 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 20 Jul 2010 15:52:16 +0200 Subject: [coreboot] compiling coreboot In-Reply-To: References: Message-ID: <4C45AA10.8000805@assembler.cz> You did not read my last email didn't you? Do you think we are an expert system to ask? Do you think we have time to waste with you? Of course not, if are not able to get this, go away and find some other people to bother. No, thanks, Rudolf Dne 20.7.2010 13:14, ali hagigat napsal(a): > If i execute only this command at the root folder of Coreboot source tree : > make > > Will the project be compiled with GCC of the system or GCC of the system > will be patched and changed or it will be compiled exactly with regular > GCC of the linux operating system? > > Besides will be the object files in elf format and when they are linked? > Is there any possibility for other formats? > From hagigatali at gmail.com Tue Jul 20 13:01:12 2010 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 20 Jul 2010 15:31:12 +0430 Subject: [coreboot] .sv folder of coreboot Message-ID: There is a .svn folder with some files and folders. How they are created? -------------- next part -------------- An HTML attachment was scrubbed... URL: From anders at jenbo.dk Tue Jul 20 16:47:15 2010 From: anders at jenbo.dk (=?utf-8?B?YW5kZXJzQGplbmJvLmRr?=) Date: Tue, 20 Jul 2010 16:47:15 +0200 Subject: [coreboot] =?utf-8?q?compiling_coreboot?= Message-ID: All your questions are answered on the wiki, in the make file or in the docs. Go read them. Mvh Anders ----- Reply message ----- Fra: "Rudolf Marek" Dato: tir., jul. 20, 2010 15:52 Emne: [coreboot] compiling coreboot Til: "ali hagigat" Cc: You did not read my last email didn't you? Do you think we are an expert system to ask? Do you think we have time to waste with you? Of course not, if are not able to get this, go away and find some other people to bother. No, thanks, Rudolf Dne 20.7.2010 13:14, ali hagigat napsal(a): > If i execute only this command at the root folder of Coreboot source tree : > make > > Will the project be compiled with GCC of the system or GCC of the system > will be patched and changed or it will be compiled exactly with regular > GCC of the linux operating system? > > Besides will be the object files in elf format and when they are linked? > Is there any possibility for other formats? > -- coreboot mailing list: coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From chertovs at gmail.com Tue Jul 20 17:17:01 2010 From: chertovs at gmail.com (Vitaly Chertovskih) Date: Tue, 20 Jul 2010 19:17:01 +0400 Subject: [coreboot] Roda RK886EX troubles Message-ID: Hi! I'm experiencing some troubles in installing coreboot on Roda RK886EX. Please, help me. Is there some manual about installation coreboot on Roda? I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS image (I download it from coreboot.org), and including VGA onboard rom, grabbed from /dev/mem as described in howtos on coreboot.org. But, after flashing using flashrom, nothing happens. Screen blinks once, and nothing happens at all. I include my .config file, maybe it helps... Please, help me. What am I doing wrong? -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: .config Type: application/octet-stream Size: 7708 bytes Desc: not available URL: From wangqingpei at gmail.com Tue Jul 20 17:47:07 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 20 Jul 2010 23:47:07 +0800 Subject: [coreboot] [PATCH]Jetway PA78VM5 In-Reply-To: References: Message-ID: hi marc, thanks a lot for your kindly review. i update the patch followed by your suggestion. there are some issues with all of the fam10 problems. patch will be send later. On Tue, Jul 20, 2010 at 5:19 AM, Marc Jones wrote: > On Thu, Jul 15, 2010 at 2:01 AM, Qing Pei Wang > wrote: > > hi all, > > in order to make the code much clear, i update the patch which sent > > yesterday to make all messages fit for "PA78VM5". > > > > Signed-off-by Wang Qing Pei > > > > > Qing Pei, > > Can you break up this patch into smaller parts, fintek sio and > mainboard? That would make it easier to review. > > Also, Can you give a summary of what the code supports. What works and > what doesn't. What about internal graphics, pci e slots etc? > > > Here are a few items to look at: > > Do you need the mb_sysconf.h file? I don't think that the 8132 and > 8111 stuff is needed on your platform. > > In devicetree.cb, You don't need multiple 18.0 devices. > > romstage.c > +//used by incoherent_ht > +#define FAM10_SCAN_PCI_BUS 0 > +#define FAM10_ALLOCATE_IO_RANGE 0 > > Are these used? I think that they may be outdated. Maybe make a patch > for all fam10 platforms? > > +//#include "northbridge/amd/amdht/ht_wrapper.c" > +//#include "northbridge/amd/amdfam10/raminit_amdmct.c" > +//#include "cpu/amd/model_10xxx/fidvid.c" > +//#include "spd_addr.h" > > Remove these old includes that are commented out. > > Remove spd_addr.h file since it isn't used. > > chip.h > +// int fixup_scsi; > +// int fixup_vga; > > Remove these old lines. I don't think that they are used for anything > in 780/700. > > Marc > > > -- > http://se-eng.com > -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: f71863fg.patch Type: text/x-patch Size: 9820 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PA78VM5.patch Type: text/x-patch Size: 146859 bytes Desc: not available URL: From anders at jenbo.dk Tue Jul 20 20:56:03 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Tue, 20 Jul 2010 18:56:03 -0000 Subject: [coreboot] Roda RK886EX troubles In-Reply-To: References: Message-ID: Try connecting a com cable and see if there is any output. Mvh Anders Den 20/07/2010 kl. 17.17 skrev Vitaly Chertovskih : > Hi! > > I'm experiencing some troubles in installing coreboot on Roda RK886EX. > Please, help me. > > Is there some manual about installation coreboot on Roda? > > I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS > image (I download it from coreboot.org), and including VGA onboard > rom, grabbed from /dev/mem as described in howtos on coreboot.org. > But, after flashing using flashrom, nothing happens. Screen blinks > once, and nothing happens at all. > > I include my .config file, maybe it helps... > > Please, help me. What am I doing wrong? > <.config> > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -------------- next part -------------- An HTML attachment was scrubbed... URL: From stefan.reinauer at coresystems.de Wed Jul 21 06:15:36 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Tue, 20 Jul 2010 21:15:36 -0700 Subject: [coreboot] Roda RK886EX troubles In-Reply-To: References: Message-ID: <4C467468.6080400@coresystems.de> On 7/20/10 8:17 AM, Vitaly Chertovskih wrote: > Hi! > > I'm experiencing some troubles in installing coreboot on Roda RK886EX. > Please, help me. > > Is there some manual about installation coreboot on Roda? > > I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS > image (I download it from coreboot.org ), and > including VGA onboard rom, grabbed from /dev/mem as described in > howtos on coreboot.org . But, after flashing > using flashrom, nothing happens. Screen blinks once, and nothing > happens at all. > > I include my .config file, maybe it helps... > > Please, help me. What am I doing wrong? Can you please send a serial console log along? Stefan -------------- next part -------------- An HTML attachment was scrubbed... URL: From svn at coreboot.org Wed Jul 21 08:52:51 2010 From: svn at coreboot.org (coreboot) Date: Wed, 21 Jul 2010 06:52:51 -0000 Subject: [coreboot] #167: Support for new ION2 (Intel NM10 chipset) Message-ID: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> #167: Support for new ION2 (Intel NM10 chipset) --------------------------------------+------------------------------------- Reporter: niklas.lonn@? | Owner: stepan@? Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: NM10,ION2,Intel,Asus Dependencies: | Patch Status: there is no patch --------------------------------------+------------------------------------- I have read that the ION platform is not supported because nVidia doesn't release the datasheets in public, however, a new ION2 platform is availabl, having an Intel NM10 north/south-bridge combo with open datashet at: http://www.intel.com/products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm The motherboard of my interest is this one (Probably many others too): http://www.asus.com/product.aspx?P_ID=iIZKMXSj0jZKiebE&templete=2 -- Ticket URL: coreboot From anders at jenbo.dk Wed Jul 21 11:18:02 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Wed, 21 Jul 2010 11:18:02 +0200 Subject: [coreboot] #167: Support for new ION2 (Intel NM10 chipset) In-Reply-To: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> References: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> Message-ID: It looks to m? like it is only a grafic card ?n that board. If that is the case then yes you should be able to port the board to corboot using the intel docs. But you will still need the nvidia x.org driver in the end. Mvh Anders Den 21/07/2010 kl. 08.52 skrev "coreboot" : > #167: Support for new ION2 (Intel NM10 chipset) > -------------------------------------- > +------------------------------------- > Reporter: niklas.lonn@? | Owner: stepan@? > Type: defect | Status: new > Priority: major | Milestone: > Component: coreboot | Keywords: > NM10,ION2,Intel,Asus > Dependencies: | Patch Status: there is no > patch > -------------------------------------- > +------------------------------------- > I have read that the ION platform is not supported because nVidia > doesn't > release the datasheets in public, however, a new ION2 platform is > availabl, having an Intel NM10 north/south-bridge combo with open > datashet > at: > http://www.intel.com/products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm > > The motherboard of my interest is this one (Probably many others too): > http://www.asus.com/product.aspx?P_ID=iIZKMXSj0jZKiebE&templete=2 > > -- > Ticket URL: > coreboot > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From hagigatali at gmail.com Wed Jul 21 12:16:06 2010 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 21 Jul 2010 14:46:06 +0430 Subject: [coreboot] compiling coreboot In-Reply-To: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> Message-ID: The reason some of you do not like to answer is not lack of time. It is because you do not want other people know about the details of the project, to disappoint people or make their progress slow. I do not ask trivial questions and far from the real knowledge necessary for the project. I ask the questions which hurts you guys because it targets your core knowledge you do not want to talk about. The same behaviour is seen in Linux Kernel mailing list... Knowledge expands by discussing the darkest areas of the matter not to keep it secrete in my opinion. Hey, Rudolf, you wrote 6 lines attacking me instead of write one line to answer my questions. What is the reason for it you think? Rudolf, answering my questions take you not more than a few minutes of your time and it is not a waste of time. Answering technical questions are not a waste of time, never, as it is a kind of practice and helps people keep their knowledge updated or refreshed. I did not ask you about economics, politics and the subjects unrelated to computer science, how can i waste your time? It is something you can benefit from if you think about it unless you have other reasons (that I am aware of!!) I asked some questions to understand the overall framework of the work without going into the details. I knew about the wiki site of Coreboot before, how could i register at this mailing list while I found it by Coreboot site!!? Go read wiki or the source code are the solutions I knew myself, i have the source and the Internet connection... On Tue, Jul 20, 2010 at 7:17 PM, anders at jenbo.dk wrote: > All your questions are answered on the wiki, in the make file or in the > docs. Go read them. > > Mvh Anders > > ----- Reply message ----- > Fra: "Rudolf Marek" > Dato: tir., jul. 20, 2010 15:52 > Emne: [coreboot] compiling coreboot > Til: "ali hagigat" > Cc: > > > You did not read my last email didn't you? Do you think we are an expert > system > to ask? Do you think we have time to waste with you? Of course not, if are > not > able to get this, go away and find some other people to bother. > > No, thanks, > Rudolf > > Dne 20.7.2010 13:14, ali hagigat napsal(a): > > If i execute only this command at the root folder of Coreboot source tree > : > > make > > > > Will the project be compiled with GCC of the system or GCC of the system > > will be patched and changed or it will be compiled exactly with regular > > GCC of the linux operating system? > > > > Besides will be the object files in elf format and when they are linked? > > Is there any possibility for other formats? > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Jul 21 13:26:38 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 21 Jul 2010 13:26:38 +0200 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> Message-ID: <4C46D96E.4080407@gmx.net> Hi, let me explain a few things. On 21.07.2010 12:16, ali hagigat wrote: > The reason some of you do not like to answer is not lack of time. It is > because you do not want other people know about the details of the project, > We will tell you about the details of our project if you are friendly and if you read the documentation. > Rudolf, answering my questions take you not more than a few minutes of your > time and it is not a waste of time. Answering technical questions are not a > waste of time, never, as it is a kind of practice and helps people keep > their knowledge updated or refreshed. I did not ask you about economics, > politics and the subjects unrelated to computer science, how can i waste > your time? It is something you can benefit from if you think about it unless > you have other reasons (that I am aware of!!) > We do not benefit from explaining things to you. You have shown an unwillingness to learn independently, so the project does not benefit from explaining things to you either. BUT... if you pay some of us _enough_ money, they will treat you as a customer and explain things to you even if you are unwilling to do any work yourself. Even if you promised to help us with developing coreboot, we would not benefit until the amount of development done by you saves other developers more time than they lose explaining things to you. We do not know you, and we have no way to make sure if you really intend to help or if you're just trolling. Your behaviour so far is pretty close to trolling. > I asked some questions to understand the overall framework of the work > without going into the details. I knew about the wiki site of Coreboot > before, how could i register at this mailing list while I found it by > Coreboot site!!? > Apparently you found the wiki, but you're unwilling or unable to read and understand the main contents, and focused on the mailing list instructions instead. > Go read wiki or the source code are the solutions I knew myself, i have the > source and the Internet connection... > And why don't you do that? You have three choices: 1. Be friendly. Read the source/documentation. We'll explain the rest. 2. Pay someone to explain this in private. 3. Leave. Regards, Carl-Daniel From corey.osgood at gmail.com Wed Jul 21 13:38:56 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Wed, 21 Jul 2010 07:38:56 -0400 Subject: [coreboot] #167: Support for new ION2 (Intel NM10 chipset) In-Reply-To: References: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> Message-ID: This is my current project, Intel Atom D410/510 cpu and NM10 southbridge support. There's 2 different IONs, one is a full chipset, the other is just a graphics chip. Supporting the graphics chip/card isn't very difficult, just load the vendor bios, it's the chipset that we can't do without any docs. niklas, do you own the Asus board you linked to? -Corey On Wed, Jul 21, 2010 at 5:18 AM, Anders Jenbo wrote: > It looks to m? like it is only a grafic card ?n that board. If that is the > case then yes you should be able to port the board to corboot using the > intel docs. But you will still need the nvidia x.org driver in the end. > > Mvh Anders > > Den 21/07/2010 kl. 08.52 skrev "coreboot" : > >> #167: Support for new ION2 (Intel NM10 chipset) >> >> --------------------------------------+------------------------------------- >> ? Reporter: ?niklas.lonn@? ? ? ? ? ?| ? ? ? ? ?Owner: ?stepan@? >> ? ? ? Type: ?defect ? ? ? ? ? ? ? ? | ? ? ? ? Status: ?new >> ? Priority: ?major ? ? ? ? ? ? ? ? ?| ? ? ?Milestone: >> ?Component: ?coreboot ? ? ? ? ? ? ? | ? ? ? Keywords: >> ?NM10,ION2,Intel,Asus >> Dependencies: ? ? ? ? ? ? ? ? ? ? ? ? | ? Patch Status: ?there is no patch >> >> --------------------------------------+------------------------------------- >> I have read that the ION platform is not supported because nVidia doesn't >> release the datasheets in public, however, a new ION2 platform is >> availabl, having an Intel NM10 north/south-bridge combo with open datashet >> at: >> >> http://www.intel.com/products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm >> >> The motherboard of my interest is this one (Probably many others too): >> http://www.asus.com/product.aspx?P_ID=iIZKMXSj0jZKiebE&templete=2 >> >> -- >> Ticket URL: >> coreboot >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From hagigatali at gmail.com Wed Jul 21 14:06:59 2010 From: hagigatali at gmail.com (ali hagigat) Date: Wed, 21 Jul 2010 16:36:59 +0430 Subject: [coreboot] compiling coreboot In-Reply-To: <4C46D96E.4080407@gmx.net> References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: My first impression from the BIOS open source project was an effort to expand knowledge not to earn money!! If any one wants to earn money he will find a technical job, will get involved in deadlines of the project, will tolerate the pressure and stress of a challenging and rewarding work. I thought we were here to help each other to understand the details of the science and technology involved and become ready to invent something new or to become ready for the projects in the market. Though spending money for this case seems contrary to the first purposes of the project but money might be paid to responsible and eligible technical people. Who you recommend and where are those? I am ready to develop code for Coreboot but my knowledge is not enough and I suspect the knowledge of many users of this mailing list to be enough for it!! On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006 at gmx.net> wrote: > Hi, > > let me explain a few things. > > On 21.07.2010 12:16, ali hagigat wrote: > > The reason some of you do not like to answer is not lack of time. It is > > because you do not want other people know about the details of the > project, > > > > We will tell you about the details of our project if you are friendly > and if you read the documentation. > > > > Rudolf, answering my questions take you not more than a few minutes of > your > > time and it is not a waste of time. Answering technical questions are not > a > > waste of time, never, as it is a kind of practice and helps people keep > > their knowledge updated or refreshed. I did not ask you about economics, > > politics and the subjects unrelated to computer science, how can i waste > > your time? It is something you can benefit from if you think about it > unless > > you have other reasons (that I am aware of!!) > > > > We do not benefit from explaining things to you. > You have shown an unwillingness to learn independently, so the project > does not benefit from explaining things to you either. > BUT... if you pay some of us _enough_ money, they will treat you as a > customer and explain things to you even if you are unwilling to do any > work yourself. > > Even if you promised to help us with developing coreboot, we would not > benefit until the amount of development done by you saves other > developers more time than they lose explaining things to you. We do not > know you, and we have no way to make sure if you really intend to help > or if you're just trolling. Your behaviour so far is pretty close to > trolling. > > > > I asked some questions to understand the overall framework of the work > > without going into the details. I knew about the wiki site of Coreboot > > before, how could i register at this mailing list while I found it by > > Coreboot site!!? > > > > Apparently you found the wiki, but you're unwilling or unable to read > and understand the main contents, and focused on the mailing list > instructions instead. > > > > Go read wiki or the source code are the solutions I knew myself, i have > the > > source and the Internet connection... > > > > And why don't you do that? > > You have three choices: > 1. Be friendly. Read the source/documentation. We'll explain the rest. > 2. Pay someone to explain this in private. > 3. Leave. > > > Regards, > Carl-Daniel > -------------- next part -------------- An HTML attachment was scrubbed... URL: From corey.osgood at gmail.com Wed Jul 21 14:19:18 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Wed, 21 Jul 2010 08:19:18 -0400 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat wrote: > My first impression from the BIOS open source project was an effort to > expand knowledge not to earn money!! > > If any one wants to earn money he will find a technical job, will get > involved in deadlines of the project, will tolerate the pressure and stress > of a challenging and rewarding work. > > I thought we were here to help each other to understand the details of the > science and technology involved and become ready to invent something new or > to become ready for the projects in the market. > > Though spending money for this case seems contrary to the first purposes of > the project but money might be paid to responsible and eligible technical > people. Who you recommend and where are those? > > I am ready to develop code for Coreboot but my knowledge is not enough and I > suspect the knowledge of many users of this mailing list to be enough for > it!! Look dude, I'm getting tired of this nonsense. All the info you need is in the wiki and the documentation. How do I know? coreboot is one of the few projects I've gotten involved in. I'm not a professional developer, not even a great programmer. I don't build CPUs for a living, hell I don't even pretend to fully comprehend how everything works. Yet when I started with this project, I found all the info I needed to get started. And I've worked my way through to port a couple 440bx boards, the i810 chipset, and the cn700 chipset (albiet that one was left a little incomplete due to the untimely death of my cn700 board). If you're not willing to make the effort to find *basic* info, why the heck should we waste our time spoon feeding it to you? Because if you're not willing to make that little effort, you're probably not going to put in the effort to actually write the code, make it work, and contribute it back to the project. So, to reiterate carl-daniel's points: 1. Put forth the effort yourself to learn about the project 2. Pay someone to make it worth their while to spend their time educating you, rather then working on projects of their own, or 3. GTFO! -Corey > > On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger > wrote: >> >> Hi, >> >> let me explain a few things. >> >> On 21.07.2010 12:16, ali hagigat wrote: >> > The reason some of you do not like to answer is not lack of time. It is >> > because you do not want other people know about the details of the >> > project, >> > >> >> We will tell you about the details of our project if you are friendly >> and if you read the documentation. >> >> >> > Rudolf, answering my questions take you not more than a few minutes of >> > your >> > time and it is not a waste of time. Answering technical questions are >> > not a >> > waste of time, never, as it is a kind of practice and helps people keep >> > their knowledge updated or refreshed. I did not ask you about economics, >> > politics and the subjects unrelated to computer science, how can i waste >> > your time? It is something you can benefit from if you think about it >> > unless >> > you have other reasons (that I am aware of!!) >> > >> >> We do not benefit from explaining things to you. >> You have shown an unwillingness to learn independently, so the project >> does not benefit from explaining things to you either. >> BUT... if you pay some of us _enough_ money, they will treat you as a >> customer and explain things to you even if you are unwilling to do any >> work yourself. >> >> Even if you promised to help us with developing coreboot, we would not >> benefit until the amount of development done by you saves other >> developers more time than they lose explaining things to you. We do not >> know you, and we have no way to make sure if you really intend to help >> or if you're just trolling. Your behaviour so far is pretty close to >> trolling. >> >> >> > I asked some questions to understand the overall framework of the work >> > without going into the details. I knew about the wiki site of Coreboot >> > before, how could i register at this mailing list while I found it by >> > Coreboot site!!? >> > >> >> Apparently you found the wiki, but you're unwilling or unable to read >> and understand the main contents, and focused on the mailing list >> instructions instead. >> >> >> > Go read wiki or the source code are the solutions I knew myself, i have >> > the >> > source and the Internet connection... >> > >> >> And why don't you do that? >> >> You have three choices: >> 1. Be friendly. Read the source/documentation. We'll explain the rest. >> 2. Pay someone to explain this in private. >> 3. Leave. >> >> >> Regards, >> Carl-Daniel > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From corey.osgood at gmail.com Wed Jul 21 15:23:00 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Wed, 21 Jul 2010 09:23:00 -0400 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: I think I just need to clarify a couple things: On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood wrote: > On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat wrote: >> My first impression from the BIOS open source project was an effort to >> expand knowledge not to earn money!! There are lots of reasons open-source projects thrive. Most of them involve money. Why are you working with coreboot? Is it (just a guess) because you're developing a product to sell? >> >> If any one wants to earn money he will find a technical job, will get >> involved in deadlines of the project, will tolerate the pressure and stress >> of a challenging and rewarding work. Yeah, paying people to teach? What a ridiculous idea! >> >> I thought we were here to help each other to understand the details of the >> science and technology involved and become ready to invent something new or >> to become ready for the projects in the market. And if you come on here with a *technical* issue, e.g. need a hand initiating an HT link, memory controller, ide device, kernel errors, etc, then the people on here will bend over backwards to help you out. On the other hand, documentation exists for a reason, because we don't have time to explain every line of code to every person who comes along. >> >> Though spending money for this case seems contrary to the first purposes of >> the project but money might be paid to responsible and eligible technical >> people. Who you recommend and where are those? http://www.coreboot.org/Products http://www.google.com/search?q=coreboot+professional+development >> >> I am ready to develop code for Coreboot but my knowledge is not enough and I >> suspect the knowledge of many users of this mailing list to be enough for >> it!! I really don't think that's the case. Read the mailing list archives, how many questions do you see like yours? Alright, because I'm just plain too damn nice to leave it at this, if you're still interested, what board/chipset are you working on? I'll get you pointed in the right direction. I'm not going to explain how every piece of coreboot works, but you really don't need to know to write a working port. -Corey > > Look dude, I'm getting tired of this nonsense. All the info you need > is in the wiki and the documentation. How do I know? coreboot is one > of the few projects I've gotten involved in. I'm not a professional > developer, not even a great programmer. I don't build CPUs for a > living, hell I don't even pretend to fully comprehend how everything > works. Yet when I started with this project, I found all the info I > needed to get started. And I've worked my way through to port a couple > 440bx boards, the i810 chipset, and the cn700 chipset (albiet that one > was left a little incomplete due to the untimely death of my cn700 > board). If you're not willing to make the effort to find *basic* info, > why the heck should we waste our time spoon feeding it to you? Because > if you're not willing to make that little effort, you're probably not > going to put in the effort to actually write the code, make it work, > and contribute it back to the project. > > So, to reiterate carl-daniel's points: > 1. Put forth the effort yourself to learn about the project > 2. Pay someone to make it worth their while to spend their time > educating you, rather then working on projects of their own, or > 3. GTFO! > > -Corey > >> >> On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger >> wrote: >>> >>> Hi, >>> >>> let me explain a few things. >>> >>> On 21.07.2010 12:16, ali hagigat wrote: >>> > The reason some of you do not like to answer is not lack of time. It is >>> > because you do not want other people know about the details of the >>> > project, >>> > >>> >>> We will tell you about the details of our project if you are friendly >>> and if you read the documentation. >>> >>> >>> > Rudolf, answering my questions take you not more than a few minutes of >>> > your >>> > time and it is not a waste of time. Answering technical questions are >>> > not a >>> > waste of time, never, as it is a kind of practice and helps people keep >>> > their knowledge updated or refreshed. I did not ask you about economics, >>> > politics and the subjects unrelated to computer science, how can i waste >>> > your time? It is something you can benefit from if you think about it >>> > unless >>> > you have other reasons (that I am aware of!!) >>> > >>> >>> We do not benefit from explaining things to you. >>> You have shown an unwillingness to learn independently, so the project >>> does not benefit from explaining things to you either. >>> BUT... if you pay some of us _enough_ money, they will treat you as a >>> customer and explain things to you even if you are unwilling to do any >>> work yourself. >>> >>> Even if you promised to help us with developing coreboot, we would not >>> benefit until the amount of development done by you saves other >>> developers more time than they lose explaining things to you. We do not >>> know you, and we have no way to make sure if you really intend to help >>> or if you're just trolling. Your behaviour so far is pretty close to >>> trolling. >>> >>> >>> > I asked some questions to understand the overall framework of the work >>> > without going into the details. I knew about the wiki site of Coreboot >>> > before, how could i register at this mailing list while I found it by >>> > Coreboot site!!? >>> > >>> >>> Apparently you found the wiki, but you're unwilling or unable to read >>> and understand the main contents, and focused on the mailing list >>> instructions instead. >>> >>> >>> > Go read wiki or the source code are the solutions I knew myself, i have >>> > the >>> > source and the Internet connection... >>> > >>> >>> And why don't you do that? >>> >>> You have three choices: >>> 1. Be friendly. Read the source/documentation. We'll explain the rest. >>> 2. Pay someone to explain this in private. >>> 3. Leave. >>> >>> >>> Regards, >>> Carl-Daniel >> >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > From coreboot at miradou.com Wed Jul 21 16:44:09 2010 From: coreboot at miradou.com (CybFr) Date: Wed, 21 Jul 2010 16:44:09 +0200 Subject: [coreboot] [offlist] coreboot on Dell c600 In-Reply-To: References: <553651f8.5e039b2d.4c10d967.8ef4b@o2.pl> <201006301943.29777.coreboot@miradou.com> Message-ID: <201007211644.09643.coreboot@miradou.com> Le Wednesday 30 June 2010 20:49:21 Joseph Smith, vous avez ?crit : > On Wed, 30 Jun 2010 19:43:29 +0200, CybFr wrote: > > Le Wednesday 30 June 2010 13:19:48 Joseph Smith, vous avez ?crit : > >> On Wed, 30 Jun 2010 09:30:20 +0200, CybFr wrote: > >> > Hello, > >> > > >> > I tried to port coreboot to c610 but stopped at desoldering flash > > > > step... > > > >> > So I > >> > have a board, it boots with dell bios (I tried yesterday) and I can > > > > give > > > >> it > >> > >> > to > >> > the cause (I have another c610 on wich I will love to run coreboot). > >> > > >> > Any ideas to minimize send costs ?? (I'm in France) > >> > >> Hello, > >> I would love to port the C610. I am particularly interested because I > > > > would > > > >> love to see AGP support for the Intel 830M, plus of course coreboot > > > > running > > > >> on a laptop :-) > >> > >> Let me know if this works for you, I am located in the US. > > > > OK, if you give me a post address, I can send it to you tomorrow. > > Ok, Great :-) > > Joseph Smith > 168 Pleasant St. > Franklin, NH 03235 > USA Sorry , I'm a bit late but the parcell is at the post office and should arrived in two weeks. Let me know when you get it. Sincerely, -- Fran?ois-R?gis From rminnich at gmail.com Wed Jul 21 17:27:52 2010 From: rminnich at gmail.com (ron minnich) Date: Wed, 21 Jul 2010 08:27:52 -0700 Subject: [coreboot] It finally happened. Message-ID: We predicted this possibility about 10 years ago, and have been warning about it almost continuously since then, but could not get people to listen. http://www.newscientist.com/blogs/shortsharpscience/2010/07/pc-giant-warns-of-hardware-tro.html I wonder if they'll start listening now? ron From bari at onelabs.com Wed Jul 21 19:20:33 2010 From: bari at onelabs.com (bari) Date: Wed, 21 Jul 2010 12:20:33 -0500 Subject: [coreboot] It finally happened. In-Reply-To: References: Message-ID: <4C472C61.3000409@onelabs.com> ron minnich wrote: > We predicted this possibility about 10 years ago, and have been > warning about it almost continuously since then, but could not get > people to listen. > > http://www.newscientist.com/blogs/shortsharpscience/2010/07/pc-giant-warns-of-hardware-tro.html > > I wonder if they'll start listening now? > > ron > They sort of have: "Implementation of embedded open source linux system designed (but not limited) torun on Raritan's OPMA card or in an User Mode linux session on any x86 host." http://sourceforge.net/projects/raritan-oss/ All it takes is the operator of the flash programmer to be malicious or anyone else that handles the flash devices. -Bari From peter at stuge.se Wed Jul 21 19:49:50 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 21 Jul 2010 19:49:50 +0200 Subject: [coreboot] It finally happened. In-Reply-To: References: Message-ID: <20100721174950.21220.qmail@stuge.se> ron minnich wrote: > I wonder if they'll start listening now? "not least because firmware should have been subject to high physical and computer security procedures" Hah! Yeah right. //Peter From Amit.Maoz at nuvoton.com Wed Jul 21 09:00:19 2010 From: Amit.Maoz at nuvoton.com (Amit.Maoz at nuvoton.com) Date: Wed, 21 Jul 2010 10:00:19 +0300 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) Message-ID: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> This is the same patch as before (2010/07/14) just with an updated copyright notice. Amit Maoz Advanced PC Division Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel Phone : +972-9-9702266 Fax : +972-9-9702001 Email : Amit.Maoz at nuvoton.com Index: nuvoton.c =================================================================== --- nuvoton.c (revision 0) +++ nuvoton.c (revision 0) @@ -0,0 +1,106 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks for Nuvoton Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 /* Super I/O ID (SID) / family */ +#define DEVICE_REV_REG 0x27 /* Super I/O revision ID (SRID) */ + +static const struct superio_registers reg_table[] = { + {0xfc, "WPCE775x / NPCE781x", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, + 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, + {0x03, "CIR Port (CIRP)", /* where supported */ + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x04, "Mobile System Wake-Up Control Config (MSWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x05, "Mouse config (KBC)", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x03,0x04,0x04,EOT}}, + {0x06, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x03,0x04,0x04,EOT}}, + {0x0f, "Shared memory (SHM)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,MISC,0x07,RSVD, + RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x11, "Power management I/F Channel 1 (PM1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x03,0x04,0x04,EOT}}, + {0x12, "Power management I/F Channel 2 (PM2)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,0x04,0x04,EOT}}, + {0x15, "Enhanced Wake On CIR (EWOC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x17, "Power Management I/F Channel 3 (PM3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x03,0x04,0x04,EOT}}, + {0x1a, "Serial Port with Fast Infrared Port (FIR)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {EOT}}}, + {EOT} +}; + +void probe_idregs_nuvoton(uint16_t port) +{ + uint8_t sid, srid; + uint8_t chip_id = 0, chip_rev = 0; + + probing_for("Nuvoton", "(sid=0xfc) ", port); + + sid = regval(port, DEVICE_ID_REG); + srid = regval(port, DEVICE_REV_REG); + + if (sid == 0xfc) { /* WPCE775xL family */ + /* + * bits 7-5: Chip ID + * bits 4-0: Chip revision + */ + chip_id = srid >> 5; + chip_rev = srid & 0x1f; + } + + if (superio_unknown(reg_table, sid)) { + if (verbose) + printf(NOTFOUND "sid=0x%02x, id=0x%02x, rev=0x%02x\n", + sid, chip_id, chip_rev); + return; + } + + printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, sid), chip_id, chip_rev, port); + chip_found = 1; + + dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); +} + +void print_nuvoton_chips(void) +{ + print_vendor_chips("Nuvoton", reg_table); +} Index: superiotool.h =================================================================== --- superiotool.h (revision 4892) +++ superiotool.h (working copy) @@ -133,6 +133,10 @@ void probe_idregs_nsc(uint16_t port); void print_nsc_chips(void); +/* nuvoton.c */ +void probe_idregs_nuvoton(uint16_t port); +void print_nuvoton_chips(void); + /* smsc.c */ void probe_idregs_smsc(uint16_t port); void print_smsc_chips(void); @@ -151,6 +155,9 @@ /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, + /* I/O pairs on Nuvoton EC chips can be configured by firmware in + * addition to the following hardware strapping options. */ + {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, }; @@ -163,6 +170,7 @@ {print_fintek_chips}, {print_ite_chips}, {print_nsc_chips}, + {print_nuvoton_chips}, {print_smsc_chips}, {print_winbond_chips}, }; Index: Makefile =================================================================== --- Makefile (revision 4892) +++ Makefile (working copy) @@ -32,7 +32,7 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. -------------- next part -------------- An HTML attachment was scrubbed... URL: From greg at creativec.com Wed Jul 21 22:04:55 2010 From: greg at creativec.com (Greg Scantlen) Date: Wed, 21 Jul 2010 14:04:55 -0600 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: References: Message-ID: <4C4752E7.1050005@creativec.com> Hello Zheng Bao, I'm Greg at Creative Consultants in Albuquerque, NM. We build clusters, mainly for LANL.I'm hoping to bid on a RFQ that involves coreboot for some custom cluster nodes. I've been benchmarking a supermicro *H8QGi-F* motherboard with (4)x 6128 CPUs and (16)x 4GB ECC UnBuff DDR****. Would this be a good candidate for core boot? I'm just starting reading the Howto on coreboot now. I do have experience with flashing BIOS - is that technique sufficient or should I have special equipment to get started? Thanks for your guidance in advance. Greg -------------- next part -------------- An HTML attachment was scrubbed... URL: From bari at onelabs.com Wed Jul 21 23:15:59 2010 From: bari at onelabs.com (bari) Date: Wed, 21 Jul 2010 16:15:59 -0500 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: <4C4752E7.1050005@creativec.com> References: <4C4752E7.1050005@creativec.com> Message-ID: <4C47638F.3060902@onelabs.com> Greg Scantlen wrote: > Hello Zheng Bao, > > I'm Greg at Creative Consultants in Albuquerque, NM. We build clusters, > mainly for LANL.I'm hoping to bid on a RFQ that involves coreboot for > some custom cluster nodes. I've been benchmarking a supermicro *H8QGi-F* > motherboard with (4)x 6128 CPUs and (16)x 4GB ECC UnBuff DDR****. Would > this be a good candidate for core boot? I'm just starting reading the > Howto on coreboot now. I do have experience with flashing BIOS - is that > technique sufficient or should I have special equipment to get started? > Thanks for your guidance in advance. > > Greg > The last I heard the 5650 was working with coreboot. The 5690 is still a work-in-progress. Zheng Bao should know the latest. -Bari From njacobs8 at hetnet.nl Wed Jul 21 23:20:54 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 21 Jul 2010 23:20:54 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR Message-ID: <201007212320.54287.njacobs8@hetnet.nl> This patch converts the Geode GX2 boards to CAR. It reduces the boot time with ~35 seconds in "Stage: loading fallback/coreboot_ram". After the conversion GCC gave a lot of build warnings in the old ROMCC code (especially in the southbridge CS5535 code used by the Lippert Frontrunner board) which i had to fix. It is ABUILD tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith V2: Add newline at end of file src/cpu/amd/model_gx2/Makefile.inc.(thanks to Peter for spotting this) Remove unused code in src/southbridge/amd/cs5535/ . Thanks,nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: 5666_gx2_car.patch Type: text/x-patch Size: 38805 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Wed Jul 21 23:49:35 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Wed, 21 Jul 2010 23:49:35 +0200 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: <4C4752E7.1050005@creativec.com> References: <4C4752E7.1050005@creativec.com> Message-ID: <4C476B6F.9010107@gmx.net> Hi Greg, On 21.07.2010 22:04, Greg Scantlen wrote: > We build clusters, mainly for LANL.I'm hoping to bid on a RFQ that > involves coreboot for some custom cluster nodes. I've been > benchmarking a supermicro *H8QGi-F* motherboard with (4)x 6128 CPUs > and (16)x 4GB ECC UnBuff DDR****.Would this be a good candidate for > core boot? AFAICS it looks like a good candidate, but you'll have to do a bit of development work. If you're lucky, you can get this done in a few days. The good news is that the chipset looks supportable (may even be supported already in part), and the board has a serial port which will help you tremendously for debugging. IPMI may be a bit of a challenge because some IPMI controllers screw up booting of any custom firmware unless you know how to silence those IPMI controllers. > I'm just starting reading the Howto on coreboot now. I do have > experience with flashing BIOS - is that technique sufficient or should > I have special equipment to get started? Thanks for your guidance in > advance. If you want to do any serious development, I recommend to make sure the BIOS flash chip is socketed (solder a socket on the board if not), or at least check for a SPI recovery connector. You absolutely want a fast SPI flash programmer or ROM emulator which works under the operating system you're using for coreboot development (which will probably be Linux). Make sure to compare prices (and consider the option to run the programmer software in VMware if you can't get a Linux version). You will likely reflash the chip a few hundred times during development, and you want flashing to be fast and reliable. Oh, and make sure the flash chip you're using has fast programming time (vendors usually ship cheap flash, not fast flash, and your time is worth a lot more than a few cents for a faster chip). A nullmodem cable for the serial port will be crucial for debugging, and a POST card is recommended as well. I usually recommend to get your feet wet with a desktop board that is already supported and cheap, and to move on to the real target only after that board runs fine. That way, you get a feeling for working with coreboot, and you know what to expect. One of the supported AMD 780 boards might be a really good starting point. Side note: I'd be really happy if you could test flashrom on those boards and submit test reports to flashrom at flashrom.org. Regards, Carl-Daniel -- http://www.hailfinger.org/ From grantwu927 at kimo.com Thu Jul 22 00:57:38 2010 From: grantwu927 at kimo.com (Grant) Date: Thu, 22 Jul 2010 06:57:38 +0800 (CST) Subject: [coreboot] Coreboot NB RS780 Routing Message-ID: <193902.43191.qm@web74009.mail.tp2.yahoo.com> Hi all, ? In my AMD RS780 project, two Marvel Lan chips connect to PCIE GPP port 0&1. One wireless lan chip connects to PCIE GPP port 2. ? In AMI BIOS, I see Bus 0 Dev4&5&6. But in coreboot, I see BUS 0 DEV 9&a. ? Is that normal? ? BR Grant -------------- next part -------------- An HTML attachment was scrubbed... URL: From mail at baerlin.eu Thu Jul 22 02:43:32 2010 From: mail at baerlin.eu (=?iso-8859-1?b?Qmr2cm4=?= Busse) Date: Thu, 22 Jul 2010 02:43:32 +0200 Subject: [coreboot] blogs.coreboot.org suggestion Message-ID: <20100722024332.10311bt5s7eduzhw@mail.baerlin.eu> Hi List, since it is fairly common to have a subdomain 'planet' for blog aggregators in the foss world, i suggest making blogs.coreboot.org also available under planet.coreboot org. compare: planet.gentoo.org planet.freedesktop.org planet.debian.org Thanks, Bj?rn Busse ---------------------------------------------------------------- This message was sent using IMP, the Internet Messaging Program. From Zheng.Bao at amd.com Thu Jul 22 03:55:55 2010 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 22 Jul 2010 09:55:55 +0800 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: <4C47638F.3060902@onelabs.com> References: <4C4752E7.1050005@creativec.com> <4C47638F.3060902@onelabs.com> Message-ID: The releasing of 5650 is in the progress. It is about 1 month to go. If you can not wait, please contact AMD to get the code. Zheng > -----Original Message----- > From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] > On Behalf Of bari > Sent: Thursday, July 22, 2010 5:16 AM > To: Greg Scantlen > Cc: coreboot at coreboot.org > Subject: Re: [coreboot] [patch] DDR3 support of AMD Family 10 > > Greg Scantlen wrote: > > Hello Zheng Bao, > > > > I'm Greg at Creative Consultants in Albuquerque, NM. We build clusters, > > mainly for LANL.I'm hoping to bid on a RFQ that involves coreboot for > > some custom cluster nodes. I've been benchmarking a supermicro *H8QGi-F* > > motherboard with (4)x 6128 CPUs and (16)x 4GB ECC UnBuff DDR****. Would > > this be a good candidate for core boot? I'm just starting reading the > > Howto on coreboot now. I do have experience with flashing BIOS - is that > > technique sufficient or should I have special equipment to get started? > > Thanks for your guidance in advance. > > > > Greg > > > > The last I heard the 5650 was working with coreboot. The 5690 is still a > work-in-progress. Zheng Bao should know the latest. > > -Bari > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From Zheng.Bao at amd.com Thu Jul 22 04:50:13 2010 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Thu, 22 Jul 2010 10:50:13 +0800 Subject: [coreboot] Coreboot NB RS780 Routing In-Reply-To: <193902.43191.qm@web74009.mail.tp2.yahoo.com> References: <193902.43191.qm@web74009.mail.tp2.yahoo.com> Message-ID: Check the devicetree.cb. set the correct configuration of gppsb_configuration and gpp_configuration. Set the needed port as device pci x.0 on end # xxxxx and Please uncomment the PciePowerOffGppPorts() in rs780_pcie.c to see what we can see. I assume the PCIE GPP you mentioned is GPPSB, which covers the dev 4,5,6,7. The Gpp covers dev 9,a. Zheng ________________________________ From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Grant Sent: Thursday, July 22, 2010 6:58 AM To: coreboot at coreboot.org Subject: [coreboot] Coreboot NB RS780 Routing Hi all, In my AMD RS780 project, two Marvel Lan chips connect to PCIE GPP port 0&1. One wireless lan chip connects to PCIE GPP port 2. In AMI BIOS, I see Bus 0 Dev4&5&6. But in coreboot, I see BUS 0 DEV 9&a. Is that normal? BR Grant -------------- next part -------------- An HTML attachment was scrubbed... URL: From wangqingpei at gmail.com Thu Jul 22 08:23:37 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Thu, 22 Jul 2010 14:23:37 +0800 Subject: [coreboot] mainboard pcie/gfx reset problems Message-ID: hi all Is there any method to find out which GPIO PIN of SB700 is used as PCIe and GFX slot reset? -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rminnich at gmail.com Thu Jul 22 08:35:48 2010 From: rminnich at gmail.com (ron minnich) Date: Thu, 22 Jul 2010 06:35:48 +0000 Subject: [coreboot] mainboard pcie/gfx reset problems In-Reply-To: References: Message-ID: On Thu, Jul 22, 2010 at 6:23 AM, Qing Pei Wang wrote: > hi all > ??? Is there any method to find out which GPIO PIN of SB700 is used as PCIe > and GFX slot reset? There is the usual method of finding the IObase of the SB700 GPIOs, then just complementing each one in turn until you see the reset activated. Doesn't take long. I demonstrated such a process for the Dell s1850 about a year ago while search for a Flash write enable. I can't find the message at present however. ron From rminnich at gmail.com Thu Jul 22 08:29:55 2010 From: rminnich at gmail.com (ron minnich) Date: Thu, 22 Jul 2010 06:29:55 +0000 Subject: [coreboot] Del firmware malware Message-ID: Wow, top hit on google. But I'm confused. http://www.infoworld.com/t/malware/dells-response-motherboard-malware-causes-confusion-176?page=0,1 "The W32.Spybot worm was discovered in flash storage on the motherboard during Dell testing. The malware does not reside in the firmware." Er, um, the firmware is in Flash I thought. OK, there's more than one Flash part I assume. OK, what's that mean? In the Flash in the case the Flash file system used by EFI? Why is there flash storage on the motherboard? As you can guess, getting some information out of Dell or the journalists is essentially impossible. I like this one: "Systems running non-Microsoft Windows operating systems cannot be affected.". Which won't stop IT departments everywhere from continuing to mandate Windows :-) (yes, I realize I'm being unfair :-) This one is even stranger: "Remaining systems can only be exposed if the customer chooses to run an update to either Unified Server Configurator (USC) or 32-bit Diagnostics."" Eh? Why would that expose remaining systems? And why would this worm be run anyway? In other words, why is a worm on a Flash part on the mainboard being run? What other software is in that part that is also being run that we don't know about? This is very curious. ron From chertovs at gmail.com Thu Jul 22 08:47:32 2010 From: chertovs at gmail.com (Vitaly Chertovskih) Date: Thu, 22 Jul 2010 10:47:32 +0400 Subject: [coreboot] Roda RK886EX troubles In-Reply-To: References: Message-ID: >>On 7/20/10 8:17 AM, Vitaly Chertovskih wrote: >> Hi! >> >> I'm experiencing some troubles in installing coreboot on Roda RK886EX. >> Please, help me. > >> Is there some manual about installation coreboot on Roda? >> >> I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS >> image (I download it from coreboot.org ), and >> including VGA onboard rom, grabbed from /dev/mem as described in >> howtos on coreboot.org . But, after flashing >> using flashrom, nothing happens. Screen blinks once, and nothing >> happens at all. >> >> I include my .config file, maybe it helps... >> >> Please, help me. What am I doing wrong? >Can you please send a serial console log along? >Stefan Attaching serial port log. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- coreboot-4.0-r5666 ??? ??? 20 20:12:26 MSD 2010 starting... Mobile Intel(R) 82945GM/GME Express Chipset (G)MCH capable of up to FSB 800 MHz (G)MCH capable of up to DDR2-667 Setting up static southbridge registers... GPIOS... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Waiting for MCHBAR to come up...ok PM1_CNT: 00001c00 SMBus controller enabled. Setting up RAM controller. This mainboard supports Dual Channel Operation. DDR II Channel 0 Socket 0: x8DDS DDR II Channel 1 Socket 0: N/A Memory will be driven at 400MHz with CAS=3 clocks tRAS = 9 cycles tRP = 3 cycles tRCD = 3 cycles Refresh: 7.8us tWR = 3 cycles DIMM 0 side 0 = 1024 MB DIMM 0 side 1 = 1024 MB tRFC = 26 cycles Setting Graphics Frequency... FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz Setting Memory Frequency... CLKCFG=0x00010023, ok (unchanged) Setting mode of operation for memory channels...Single Channel 0 only. Programming Clock Crossing...MEM=400 FSB=667... ok Setting RAM size... C0DRB = 0x40404020 C1DRB = 0x00000000 TOLUD = 0x0080 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0000 DIMM0 has 8 banks. one dimm per channel config.. Initializing System Memory IO... Programming Dual Channel RCOMP Table Index: 19 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 jedec enable sequence: bank 1 bankaddr from bank size of rank 0 receive_enable_autoconfig() for channel 0 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x3 set_receive_enable() medium=0x1, coarse=0x3 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x3 add_quarter_clock() mediumcoarse=0d fine=b0 set_receive_enable() medium=0x3, coarse=0x3 find_preamble() set_receive_enable() medium=0x3, coarse=0x2 set_receive_enable() medium=0x3, coarse=0x1 add_quarter_clock() mediumcoarse=07 fine=30 normalize() set_receive_enable() medium=0x0, coarse=0x2 RAM initialization finished. Setting up Egress Port RCRB Loading port arbitration table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait for VC1 negotiation ...done.. Internal graphics: enabled Waiting for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: 0000 Disabling PCI Express x16 Link Wait for link to enter detect state... ok Setting up Root Complex Topology Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (376832 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r5666 ??? ??? 20 20:12:26 MSD 2010 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:03.1: enabled 1 PCI: 00:03.2: enabled 1 PCI: 00:03.3: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 0 PNP: 00ff.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 1 PCI: 00:1c.2: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 1 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 1 PCI: 00:1d.7: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:03.1: enabled 1 PCI: 00:03.2: enabled 1 PCI: 00:03.3: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 0 PNP: 00ff.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 Display I/O: 0x32 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/27ac] enabled malloc Enter, size 68, free_mem_ptr 00158000 malloc 00158000 PCI: 00:02.0 [8086/27ae] enabled malloc Enter, size 68, free_mem_ptr 00158044 malloc 00158044 PCI: 00:02.1 [8086/27a6] ops PCI: 00:02.1 [8086/27a6] enabled PCI: Static device PCI: 00:1b.0 not found, disabling it. PCI: 00:1c.0 [8086/27d0] bus ops PCI: 00:1c.0 [8086/27d0] enabled PCI: Static device PCI: 00:1c.1 not found, disabling it. PCI: Static device PCI: 00:1c.2 not found, disabling it. malloc Enter, size 68, free_mem_ptr 00158088 malloc 00158088 PCI: 00:1c.3 [8086/27d6] bus ops PCI: 00:1c.3 [8086/27d6] enabled PCI: 00:1d.0 [8086/27c8] ops PCI: 00:1d.0 [8086/27c8] enabled PCI: 00:1d.1 [8086/27c9] ops PCI: 00:1d.1 [8086/27c9] enabled PCI: 00:1d.2 [8086/27ca] ops PCI: 00:1d.2 [8086/27ca] enabled PCI: 00:1d.3 [8086/27cb] ops PCI: 00:1d.3 [8086/27cb] enabled PCI: 00:1d.7 [8086/27cc] ops PCI: 00:1d.7 [8086/27cc] enabled PCI: 00:1e.0 [8086/2448] bus ops PCI: 00:1e.0 [8086/2448] enabled malloc Enter, size 68, free_mem_ptr 001580cc malloc 001580cc PCI: 00:1e.2 [8086/27de] ops PCI: 00:1e.2 [8086/27de] enabled PCI: 00:1f.0 [8086/27bd] bus ops PCI: 00:1f.0 [8086/27bd] enabled PCI: 00:1f.2 [8086/27c4] ops PCI: 00:1f.2 [8086/27c4] enabled PCI: 00:1f.3 [8086/27da] bus ops PCI: 00:1f.3 [8086/27da] enabled do_pci_scan_bridge for PCI: 00:1c.0 malloc Enter, size 24, free_mem_ptr 00158110 malloc 00158110 PCI: pci_scan_bus for bus 01 PCI: Using configuration type 1 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:1c.3 malloc Enter, size 24, free_mem_ptr 00158128 malloc 00158128 PCI: pci_scan_bus for bus 02 malloc Enter, size 68, free_mem_ptr 00158140 malloc 00158140 PCI: 02:00.0 [10ec/8168] ops PCI: 02:00.0 [10ec/8168] enabled PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 03 PCI: Static device PCI: 03:03.0 not found, disabling it. PCI: Static device PCI: 03:03.1 not found, disabling it. PCI: Static device PCI: 03:03.2 not found, disabling it. PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:1f.0 malloc Enter, size 2560, free_mem_ptr 00158184 malloc 00158184 PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 disabled malloc Enter, size 68, free_mem_ptr 00158b84 malloc 00158b84 PNP: 00ff.1 enabled PNP: 00ff.0 enabled scan_static_bus for PCI: 00:1f.0 done scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done PCI: pci_scan_bus returning with max=003 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1c.3 read_resources bus 2 link: 0 PCI: 00:1c.3 read_resources bus 2 link: 0 done PCI: 00:1e.0 read_resources bus 3 link: 0 PCI: 00:1e.0 read_resources bus 3 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PNP: 00ff.1 missing read_resources PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 PCI: 00:1b.0 PCI: 00:1c.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.3 child on link 0 PCI: 02:00.0 PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:1d.0 PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1d.1 PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1d.2 PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1d.3 PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1d.7 PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1e.0 child on link 0 PCI: 03:03.0 PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:03.0 PCI: 03:03.1 PCI: 03:03.2 PCI: 03:03.3 PCI: 00:1e.2 PCI: 00:1e.2 resource base 0 size 200 align 9 gran 9 limit ffffffff flags 200 index 18 PCI: 00:1e.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 1c PCI: 00:1f.0 child on link 0 PNP: 002e.1 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 00ff.1 PNP: 00ff.0 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 02:00.0 10 * [0x0 - 0xff] io PCI: 00:1c.3 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.3 1c * [0x0 - 0xfff] io PCI: 00:1d.0 20 * [0x1000 - 0x101f] io PCI: 00:1d.1 20 * [0x1020 - 0x103f] io PCI: 00:1d.2 20 * [0x1040 - 0x105f] io PCI: 00:1d.3 20 * [0x1060 - 0x107f] io PCI: 00:1f.3 20 * [0x1080 - 0x109f] io PCI: 00:1f.2 20 * [0x10a0 - 0x10af] io PCI: 00:02.0 14 * [0x10b0 - 0x10b7] io PCI: 00:1f.2 10 * [0x10b8 - 0x10bf] io PCI: 00:1f.2 18 * [0x10c0 - 0x10c7] io PCI: 00:1f.2 14 * [0x10c8 - 0x10cb] io PCI: 00:1f.2 1c * [0x10cc - 0x10cf] io PCI_DOMAIN: 0000 compute_resources_io: base: 10d0 size: 10d0 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 30 * [0x0 - 0x1ffff] mem PCI: 02:00.0 18 * [0x20000 - 0x20fff] mem PCI: 00:1c.3 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:1c.3 20 * [0x10000000 - 0x100fffff] mem PCI: 00:02.0 10 * [0x10100000 - 0x1017ffff] mem PCI: 00:02.1 10 * [0x10180000 - 0x101fffff] mem PCI: 00:02.0 1c * [0x10200000 - 0x1023ffff] mem PCI: 00:1d.7 10 * [0x10240000 - 0x102403ff] mem PCI: 00:1f.2 24 * [0x10240400 - 0x102407ff] mem PCI: 00:1e.2 18 * [0x10240800 - 0x102409ff] mem PCI: 00:1e.2 1c * [0x10240a00 - 0x10240aff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 10240b00 size: 10240b00 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:1c.0 constrain_resources: PCI: 00:1c.3 constrain_resources: PCI: 02:00.0 constrain_resources: PCI: 00:1d.0 constrain_resources: PCI: 00:1d.1 constrain_resources: PCI: 00:1d.2 constrain_resources: PCI: 00:1d.3 constrain_resources: PCI: 00:1d.7 constrain_resources: PCI: 00:1e.0 constrain_resources: PCI: 00:1e.2 constrain_resources: PCI: 00:1f.0 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 00ff.1 constrain_resources: PNP: 00ff.0 constrain_resources: PCI: 00:1f.2 constrain_resources: PCI: 00:1f.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10d0 align:12 gran:0 limit:ffff Assigned: PCI: 00:1c.3 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:1d.0 20 * [0x2000 - 0x201f] io Assigned: PCI: 00:1d.1 20 * [0x2020 - 0x203f] io Assigned: PCI: 00:1d.2 20 * [0x2040 - 0x205f] io Assigned: PCI: 00:1d.3 20 * [0x2060 - 0x207f] io Assigned: PCI: 00:1f.3 20 * [0x2080 - 0x209f] io Assigned: PCI: 00:1f.2 20 * [0x20a0 - 0x20af] io Assigned: PCI: 00:02.0 14 * [0x20b0 - 0x20b7] io Assigned: PCI: 00:1f.2 10 * [0x20b8 - 0x20bf] io Assigned: PCI: 00:1f.2 18 * [0x20c0 - 0x20c7] io Assigned: PCI: 00:1f.2 14 * [0x20c8 - 0x20cb] io Assigned: PCI: 00:1f.2 1c * [0x20cc - 0x20cf] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20d0 size: 10d0 align: 12 gran: 0 done PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:1c.3 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 02:00.0 10 * [0x1000 - 0x10ff] io PCI: 00:1c.3 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10240b00 align:28 gran:0 limit:febfffff Assigned: PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:1c.3 20 * [0xf0000000 - 0xf00fffff] mem Assigned: PCI: 00:02.0 10 * [0xf0100000 - 0xf017ffff] mem Assigned: PCI: 00:02.1 10 * [0xf0180000 - 0xf01fffff] mem Assigned: PCI: 00:02.0 1c * [0xf0200000 - 0xf023ffff] mem Assigned: PCI: 00:1d.7 10 * [0xf0240000 - 0xf02403ff] mem Assigned: PCI: 00:1f.2 24 * [0xf0240400 - 0xf02407ff] mem Assigned: PCI: 00:1e.2 18 * [0xf0240800 - 0xf02409ff] mem Assigned: PCI: 00:1e.2 1c * [0xf0240a00 - 0xf0240aff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0240b00 size: 10240b00 align: 28 gran: 0 done PCI: 00:1c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:1c.3 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1c.3 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:1c.3 allocate_resources_mem: base:f0000000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 02:00.0 30 * [0xf0000000 - 0xf001ffff] mem Assigned: PCI: 02:00.0 18 * [0xf0020000 - 0xf0020fff] mem PCI: 00:1c.3 allocate_resources_mem: next_base: f0021000 size: 100000 align: 20 gran: 20 done PCI: 00:1e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:1e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 pci_tolm: 0xe0000000 Base of stolen memory: 0x7f800000 Top of Low Used DRAM: 0x80000000 IGD decoded, subtracting 8M UMA Available memory: 2088960K (2040M) PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00f0100000 - 0x00f017ffff] size 0x00080000 gran 0x13 mem PCI: 00:02.0 14 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:02.0 1c <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.1 10 <- [0x00f0180000 - 0x00f01fffff] size 0x00080000 gran 0x13 mem PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:1c.3 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:1c.3 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1c.3 20 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:1c.3 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 02:00.0 18 <- [0x00f0020000 - 0x00f0020fff] size 0x00001000 gran 0x0c mem64 PCI: 02:00.0 30 <- [0x00f0000000 - 0x00f001ffff] size 0x00020000 gran 0x11 romem PCI: 00:1c.3 assign_resources, bus 2 link: 0 PCI: 00:1d.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:1d.1 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io PCI: 00:1d.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io PCI: 00:1d.3 20 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io PCI: 00:1d.7 10 <- [0x00f0240000 - 0x00f02403ff] size 0x00000400 gran 0x0a mem PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:1e.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:1e.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:1e.0 assign_resources, bus 3 link: 0 PCI: 00:1e.0 assign_resources, bus 3 link: 0 PCI: 00:1e.2 18 <- [0x00f0240800 - 0x00f02409ff] size 0x00000200 gran 0x09 mem PCI: 00:1e.2 1c <- [0x00f0240a00 - 0x00f0240aff] size 0x00000100 gran 0x08 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.2 10 <- [0x00000020b8 - 0x00000020bf] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x00000020c8 - 0x00000020cb] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x00000020c0 - 0x00000020c7] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x00000020cc - 0x00000020cf] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x00000020a0 - 0x00000020af] size 0x00000010 gran 0x04 io PCI: 00:1f.2 24 <- [0x00f0240400 - 0x00f02407ff] size 0x00000400 gran 0x0a mem PCI: 00:1f.3 20 <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 10d0 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10240b00 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI_DOMAIN: 0000 resource base c0000 size 7f740000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 PCI: 00:02.0 PCI: 00:02.0 resource base f0100000 size 80000 align 19 gran 19 limit febfffff flags 60000200 index 10 PCI: 00:02.0 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 18 PCI: 00:02.0 resource base f0200000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 1c PCI: 00:02.1 PCI: 00:02.1 resource base f0180000 size 80000 align 19 gran 19 limit febfffff flags 60000200 index 10 PCI: 00:1b.0 PCI: 00:1c.0 PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:1c.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.3 child on link 0 PCI: 02:00.0 PCI: 00:1c.3 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1c.3 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:1c.3 resource base f0000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 02:00.0 resource base f0020000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18 PCI: 02:00.0 resource base f0000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 00:1d.0 PCI: 00:1d.0 resource base 2000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1d.1 PCI: 00:1d.1 resource base 2020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1d.2 PCI: 00:1d.2 resource base 2040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1d.3 PCI: 00:1d.3 resource base 2060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1d.7 PCI: 00:1d.7 resource base f0240000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 10 PCI: 00:1e.0 child on link 0 PCI: 03:03.0 PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:1e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:03.0 PCI: 03:03.1 PCI: 03:03.2 PCI: 03:03.3 PCI: 00:1e.2 PCI: 00:1e.2 resource base f0240800 size 200 align 9 gran 9 limit febfffff flags 60000200 index 18 PCI: 00:1e.2 resource base f0240a00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 1c PCI: 00:1f.0 child on link 0 PNP: 002e.1 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 00ff.1 PNP: 00ff.0 PCI: 00:1f.2 PCI: 00:1f.2 resource base 20b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:1f.2 resource base 20c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:1f.2 resource base 20c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:1f.2 resource base 20cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:1f.2 resource base 20a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:1f.2 resource base f0240400 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 2080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 4352/6886 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 cmd <- 03 PCI: 00:02.1 cmd <- 02 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 4352/6886 PCI: 00:1c.0 cmd <- 100 PCI: 00:1c.3 bridge ctrl <- 0003 PCI: 00:1c.3 cmd <- 07 PCI: 00:1d.0 subsystem <- 4352/6886 PCI: 00:1d.0 cmd <- 01 PCI: 00:1d.1 subsystem <- 4352/6886 PCI: 00:1d.1 cmd <- 01 PCI: 00:1d.2 subsystem <- 4352/6886 PCI: 00:1d.2 cmd <- 01 PCI: 00:1d.3 subsystem <- 4352/6886 PCI: 00:1d.3 cmd <- 01 PCI: 00:1d.7 subsystem <- 4352/6886 PCI: 00:1d.7 cmd <- 102 PCI: 00:1e.0 bridge ctrl <- 0043 PCI: 00:1e.0 subsystem <- 4352/6886 PCI: 00:1e.0 cmd <- 100 (NOT WRITTEN!) PCI: 00:1e.2 cmd <- 02 PCI: 00:1f.0 subsystem <- 4352/6886 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 4352/6886 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 subsystem <- 4352/6886 PCI: 00:1f.3 cmd <- 101 PCI: 02:00.0 cmd <- 03 done. Initializing devices... APIC_CLUSTER: 0 init malloc Enter, size 91, free_mem_ptr 00158bc8 malloc 00158bc8 start_eip=0x0000d000, offset=0x00100000, code_size=0x0000005b Initializing SMM handler... ... pmbase = 0x0500 SMI_STS: PM1 PM1_STS: WAK PWRBTN BM TMROF GPE0_STS: PME ALT_GP_SMI_STS: TCO_STS: ... raise SMI# Initializing CPU #0 CPU: vendor Intel device 6f2 CPU: family 06, model 0f, stepping 02 Enabling cache microcode_info: sig = 0x000006f2 pf=0x00000020 rev = 0x00000000 microcode updated to revision: 00000057 from revision 00000000 CPU: Intel(R) Core(TM)2 CPU T5500 @ 1.66GHz. Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 1024MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 1536MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 1792MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 1920MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 5, base: 1984MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Running out of variable MTRRs! Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU: 0 2 siblings malloc Enter, size 68, free_mem_ptr 00158c23 malloc 00158c24 CPU: 0 has sibling 1 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU #0 initialized Waiting for 1 CPUS to stop Initializing CPU #1 CPU: vendor Intel device 6f2 CPU: family 06, model 0f, stepping 02 Enabling cache microcode_info: sig = 0x000006f2 pf=0x00000020 rev = 0x00000000 microcode updated to revision: 00000057 from revision 00000000 CPU: Intel(R) Core(TM)2 CPU T5500 @ 1.66GHz. Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 1024MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 1536MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 1792MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 1920MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 5, base: 1984MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Running out of variable MTRRs! Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x01 done. CPU: 1 2 siblings CPU #1 initialized CPU 1 going down... All AP CPUs stopped PCI: 00:00.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + 19847 + align -> fff19880 Check fallback/payload CBFS: follow chain: fff19880 + 38 + 13c38 + align -> fff2d500 Check pci8086,27ae.rom CBFS: follow chain: fff2d500 + 38 + 8000 + align -> fff35540 Check CBFS: follow chain: fff35540 + 28 + baa78 + align -> ffff0000 CBFS: Could not find file pci8086,27ac.rom PCI: 00:02.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff00000 + 38 + 19847 + align -> fff19880 Check fallback/payload CBFS: follow chain: fff19880 + 38 + 13c38 + align -> fff2d500 Check pci8086,27ae.rom In cbfs, rom address for PCI: 00:02.0 = fff2d538 PCI Expansion ROM, signature 0xaa55, INIT size 0xea00, data ptr 0x0040 PCI ROM Image, Vendor 8086, Device 27ae, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff2d538 to 0xc0000, 0xea00 bytes Real mode stub @00000600: 606 bytes Calling Option ROM... oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 00000ff6 edi: 00000000 esi: 00000000 oprom: ip: e4d1 cs: c000 flags: 00000046 Oops, exception 6 while executing option rom oprom: INT# 0x6 oprom: eax: 00000010 ebx: 0000ffff ecx: 00000000 edx: 0000ffff oprom: ebp: 00157ee0 esp: 0000 From peter at stuge.se Thu Jul 22 08:56:15 2010 From: peter at stuge.se (Peter Stuge) Date: Thu, 22 Jul 2010 08:56:15 +0200 Subject: [coreboot] blogs.coreboot.org suggestion In-Reply-To: <20100722024332.10311bt5s7eduzhw@mail.baerlin.eu> References: <20100722024332.10311bt5s7eduzhw@mail.baerlin.eu> Message-ID: <20100722065615.19338.qmail@stuge.se> Bj?rn Busse wrote: > making blogs.coreboot.org also available under planet.coreboot org Good point. +1 Maybe with a redirect from one to the other? //Peter From ziltro at ziltro.com Thu Jul 22 12:58:58 2010 From: ziltro at ziltro.com (Andrew Morgan) Date: Thu, 22 Jul 2010 11:58:58 +0100 Subject: [coreboot] Del firmware malware In-Reply-To: References: Message-ID: <4C482472.3010003@ziltro.com> It sounds very much like it could be a system similar to HP's iLO. I don't know any details, but it seems this is another computer in the server which is always running as long as the server is connected to the mains. It has another network card and IP address and you can connect to it with a web browser and turn the power supply on/off, provide boot media over the network/internet, and use it a bit like VNC, remote screen keyboard and mouse for installing an operating system remotely. Some of these features are paid for extras where you have to enter a serial number to use them on your own server! Something like this obviously has to have pretty good access to the main computer. Even if the Dell computer 'code on flash on the motherboard which we're not going to call firmware' isn't anything like iLO, this is another place for firmware based viruses to hide. -- Andrew. From c-d.hailfinger.devel.2006 at gmx.net Thu Jul 22 15:13:48 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 22 Jul 2010 15:13:48 +0200 Subject: [coreboot] Del firmware malware In-Reply-To: References: Message-ID: <4C48440C.7080609@gmx.net> On 22.07.2010 08:29, ron minnich wrote: > Wow, top hit on google. But I'm confused. > > http://www.infoworld.com/t/malware/dells-response-motherboard-malware-causes-confusion-176?page=0,1 > > "The W32.Spybot worm was discovered in flash storage on the > motherboard during Dell testing. The malware does not reside in the > firmware." > > Er, um, the firmware is in Flash I thought. OK, there's more than one > Flash part I assume. > Yes. Admittedly the press doesn't know enough to get a clear picture across. > OK, what's that mean? In the Flash in the case the Flash file system > used by EFI? Why is there flash storage on the motherboard? As you can > guess, getting some information out of Dell or the journalists is > essentially impossible. > Board manufacturers noticed that NOR flash (for BIOS) is way too expensive and you can get 128 MB NAND flash for the price of 1 MB NOR flash (rough numbers). So they use small NOR flash which hosts the firmware and a small NAND controller driver. Once firmware has run, the NAND controller driver (which lives in NOR flash) is used to load a payload (e.g. Splashtop/whatever) from NAND. That NAND flash is essentially a USB flash drive soldered onboard, and it often is attached directly without USB. Admittedly the explanation above is an educated guess. It could easily be worse. > I like this one: "Systems running non-Microsoft Windows operating > systems cannot be affected.". Which won't stop IT departments > everywhere from continuing to mandate Windows :-) (yes, I realize I'm > being unfair :-) > > This one is even stranger: "Remaining systems can only be exposed if > the customer chooses to run an update to either Unified Server > Configurator (USC) or 32-bit Diagnostics."" > > Eh? Why would that expose remaining systems? And why would this worm > be run anyway? In other words, why is a worm on a Flash part on the > mainboard being run? What other software is in that part that is also > being run that we don't know about? This is very curious. > This is Dell. The company which blocks all attempts to reflash from userspace. You run a BIOS/whatever update by loading the image in memory, rebooting and waiting for the BIOS to use that image to reflash itself. Now if the in-BIOS (or in-NAND-flash) updater executes code in NAND flash which is infected with malware, you are royally screwed. Basically the only way to kill the malware (by updating the flash chip) is to execute the malware and hope for the best. I'd like to summarize the situation with a soundbite for the press: "You're infected with HIV. Please take medication which will trigger a full AIDS outbreak because that medication has a chance to heal you." Regards, Carl-Daniel -- http://www.hailfinger.org/ From joe at settoplinux.org Thu Jul 22 15:56:48 2010 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 22 Jul 2010 09:56:48 -0400 Subject: [coreboot] Roda RK886EX troubles In-Reply-To: References: Message-ID: <4C484E20.7050702@settoplinux.org> On 07/22/2010 02:47 AM, Vitaly Chertovskih wrote: > >>On 7/20/10 8:17 AM, Vitaly Chertovskih wrote: > >> Hi! > >> > >> I'm experiencing some troubles in installing coreboot on Roda RK886EX. > >> Please, help me. > > > >> Is there some manual about installation coreboot on Roda? > >> > >> I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS > >> image (I download it from coreboot.org > >), and > >> including VGA onboard rom, grabbed from /dev/mem as described in > >> howtos on coreboot.org >. But, after flashing > >> using flashrom, nothing happens. Screen blinks once, and nothing > >> happens at all. > >> > >> I include my .config file, maybe it helps... > >> > >> Please, help me. What am I doing wrong? > > >Can you please send a serial console log along? > > >Stefan > Attaching serial port log. > Thanks! > At first glance, it looks like there is something wrong with your mtrr setup. Maybe something weird about memory region allocations. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Thu Jul 22 16:00:32 2010 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 22 Jul 2010 10:00:32 -0400 Subject: [coreboot] CentraLUG meeting, 2 August Message-ID: <4C484F00.9070600@settoplinux.org> Brief summary about the presentation: 1. I plan on speaking a litle about myself, and how I got involved in coreboot (elaborate on above). 2. Give a brief history on coreboot and how it started. 3. Go over some of the features of coreboot. 4. Go over some of the great tools that have sprouted off of the coreboot tree. 5. Talk about how the code process flows and how you(audiance) can start to develop coreboot. 6. Open for Question and Answer time. -------------------------------------- Do you guys think there is anything else I should touch on? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From peter at stuge.se Thu Jul 22 16:12:49 2010 From: peter at stuge.se (Peter Stuge) Date: Thu, 22 Jul 2010 16:12:49 +0200 Subject: [coreboot] Roda RK886EX troubles In-Reply-To: References: Message-ID: <20100722141249.22505.qmail@stuge.se> Vitaly Chertovskih wrote: > Attaching serial port log. Thank you. There's a problem when coreboot tries to execute the VGA ROM. You mentioned that the ROM was extracted from /dev/mem. It would be even better if you could extract the VGA ROM from a BIOS image on disk, instead of from the running system. Another approach would be to disable execute of the option ROM in coreboot. This is not something coreboot can do well. If you need an option ROM (such as a VGA ROM) then it's better to use SeaBIOS because you then get a complete BIOS environment in the system, and option ROMs want that very much. //Peter From phenon at gmx.com Thu Jul 22 16:02:28 2010 From: phenon at gmx.com (phenon at gmx.com) Date: Thu, 22 Jul 2010 10:02:28 -0400 Subject: [coreboot] ASUS K8V-MX Message-ID: <20100722141105.83200@gmx.com> Hello everyone... I have an ASUS K8V-MX that I'd like to test coreboot on. It has VIA's K8M800 / VT8237R as the chipset duo, and an Athlon 64 3000+ 2GHz 754 CPU (ADA3000AIK4BX). The board link: http://www.asus.com/product.aspx?P_ID=dJ2XP7zr8tzeYbLp Is it doable? I'm a first timer with coreboot... Cheers :) From dhendrix at google.com Thu Jul 22 22:30:15 2010 From: dhendrix at google.com (David Hendricks) Date: Thu, 22 Jul 2010 13:30:15 -0700 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> Message-ID: Thanks for sending the patch out, Amit! Since I wrote this particular patch, I'll go ahead and do the sign-off on it: Signed-off by: David Hendricks (dhendrix at google.com) On Wed, Jul 21, 2010 at 12:00 AM, wrote: > This is the same patch as before (2010/07/14) just with an updated > copyright notice. > > > > Amit Maoz > Advanced PC Division > Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel > Phone : +972-9-9702266 > Fax : +972-9-9702001 > Email : Amit.Maoz at nuvoton.com > > > > > > Index: nuvoton.c > > =================================================================== > > --- nuvoton.c (revision 0) > > +++ nuvoton.c (revision 0) > > @@ -0,0 +1,106 @@ > > +/* > > + * This file is part of the superiotool project. > > + * > > + * Copyright (C) 2010 Google Inc. > > + * Written by David Hendricks for Nuvoton > Technology Corp. > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > > + */ > > + > > +#include "superiotool.h" > > + > > +#define DEVICE_ID_REG 0x20 /* Super I/O ID > (SID) / family */ > > +#define DEVICE_REV_REG 0x27 /* Super I/O > revision ID (SRID) */ > > + > > +static const struct superio_registers reg_table[] = { > > + {0xfc, "WPCE775x / NPCE781x", { > > + {NOLDN, NULL, > > + > {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, > > + > 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, > > + > {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, > > + > 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, > > + {0x03, "CIR Port (CIRP)", /* where supported */ > > + > {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, > > + > {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, > > + {0x04, "Mobile System Wake-Up Control Config > (MSWC)", > > + > {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, > > + {0x05, "Mouse config (KBC)", > > + {0x30,0x70,0x71,0x74,0x75,EOT}, > > + {0x00,0x0c,0x03,0x04,0x04,EOT}}, > > + {0x06, "Keyboard config (KBC)", > > + > {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x60,0x00,0x64,0x01,0x03,0x04,0x04,EOT}}, > > + {0x0f, "Shared memory (SHM)", > > + > {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, > > + > 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, > > + > {0x00,0x00,0x00,0x00,0x00,0x04,0x04,MISC,0x07,RSVD, > > + > RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, > > + {0x11, "Power management I/F Channel 1 (PM1)", > > + > {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x62,0x00,0x66,0x01,0x03,0x04,0x04,EOT}}, > > + {0x12, "Power management I/F Channel 2 (PM2)", > > + > {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,0x04,0x04,EOT}}, > > + {0x15, "Enhanced Wake On CIR (EWOC)", > > + > {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, > > + {0x17, "Power Management I/F Channel 3 (PM3)", > > + > {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, > > + > {0x00,0x00,0x6a,0x00,0x6e,0x01,0x03,0x04,0x04,EOT}}, > > + {0x1a, "Serial Port with Fast Infrared Port > (FIR)", > > + > {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, > > + > {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, > > + {EOT}}}, > > + {EOT} > > +}; > > + > > +void probe_idregs_nuvoton(uint16_t port) > > +{ > > + uint8_t sid, srid; > > + uint8_t chip_id = 0, chip_rev = 0; > > + > > + probing_for("Nuvoton", "(sid=0xfc) ", port); > > + > > + sid = regval(port, DEVICE_ID_REG); > > + srid = regval(port, DEVICE_REV_REG); > > + > > + if (sid == 0xfc) { /* WPCE775xL family */ > > + /* > > + * bits 7-5: Chip ID > > + * bits 4-0: Chip revision > > + */ > > + chip_id = srid >> 5; > > + chip_rev = srid & 0x1f; > > + } > > + > > + if (superio_unknown(reg_table, sid)) { > > + if (verbose) > > + printf(NOTFOUND "sid=0x%02x, > id=0x%02x, rev=0x%02x\n", > > + sid, chip_id, chip_rev); > > + return; > > + } > > + > > + printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", > > + get_superio_name(reg_table, sid), chip_id, > chip_rev, port); > > + chip_found = 1; > > + > > + dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); > > +} > > + > > +void print_nuvoton_chips(void) > > +{ > > + print_vendor_chips("Nuvoton", reg_table); > > +} > > Index: superiotool.h > > =================================================================== > > --- superiotool.h (revision 4892) > > +++ superiotool.h (working copy) > > @@ -133,6 +133,10 @@ > > void probe_idregs_nsc(uint16_t port); > > void print_nsc_chips(void); > > > > +/* nuvoton.c */ > > +void probe_idregs_nuvoton(uint16_t port); > > +void print_nuvoton_chips(void); > > + > > /* smsc.c */ > > void probe_idregs_smsc(uint16_t port); > > void print_smsc_chips(void); > > @@ -151,6 +155,9 @@ > > /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be > valid. */ > > {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, > > {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, > > + /* I/O pairs on Nuvoton EC chips can be configured by firmware > in > > + * addition to the following hardware strapping options. */ > > + {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, > > {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, > 0x370, EOT}}, > > {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, > 0x250, EOT}}, > > }; > > @@ -163,6 +170,7 @@ > > {print_fintek_chips}, > > {print_ite_chips}, > > {print_nsc_chips}, > > + {print_nuvoton_chips}, > > {print_smsc_chips}, > > {print_winbond_chips}, > > }; > > Index: Makefile > > =================================================================== > > --- Makefile (revision 4892) > > +++ Makefile (working copy) > > @@ -32,7 +32,7 @@ > > CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ > > -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) > > > > -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o > > +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o > > > > OS_ARCH = $(shell uname) > > ifeq ($(OS_ARCH), Darwin) > > > =========================================================================================== > The privileged confidential information contained in this email is intended > for use only by the addressees as indicated by the original sender of this > email. If you are not the addressee indicated in this email or are not > responsible for delivery of the email to such a person, please kindly reply > to the sender indicating this fact and delete all copies of it from your > computer and network server immediately. Your cooperation is highly > appreciated. It is advised that any unauthorized use of confidential > information of Nuvoton is strictly prohibited; and any information in this > email irrelevant to the official business of Nuvoton shall be deemed as > neither given nor endorsed by Nuvoton. > > > =========================================================================================== > The privileged confidential information contained in this email is intended > for use only by the addressees as indicated by the original sender of this > email. If you are not the addressee indicated in this email or are not > responsible for delivery of the email to such a person, please kindly reply > to the sender indicating this fact and delete all copies of it from your > computer and network server immediately. Your cooperation is highly > appreciated. It is advised that any unauthorized use of confidential > information of Nuvoton is strictly prohibited; and any information in this > email irrelevant to the official business of Nuvoton shall be deemed as > neither given nor endorsed by Nuvoton. > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL: From dhendrix at google.com Thu Jul 22 23:55:15 2010 From: dhendrix at google.com (David Hendricks) Date: Thu, 22 Jul 2010 14:55:15 -0700 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> Message-ID: Carl-Daniel pointed out some whitespace issues with the patch. I ran it thru the "indent -kr -i8" filter and fixed up the register table entries, so the attached patch should address concerns about whitespace. On Thu, Jul 22, 2010 at 1:30 PM, David Hendricks wrote: > Thanks for sending the patch out, Amit! > > Since I wrote this particular patch, I'll go ahead and do the sign-off on > it: > Signed-off by: David Hendricks (dhendrix at google.com) > > On Wed, Jul 21, 2010 at 12:00 AM, wrote: > >> This is the same patch as before (2010/07/14) just with an updated >> copyright notice. >> >> >> >> Amit Maoz >> Advanced PC Division >> Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel >> Phone : +972-9-9702266 >> Fax : +972-9-9702001 >> Email : Amit.Maoz at nuvoton.com >> >> >> >> >> >> Index: nuvoton.c >> >> =================================================================== >> >> --- nuvoton.c (revision 0) >> >> +++ nuvoton.c (revision 0) >> >> @@ -0,0 +1,106 @@ >> >> +/* >> >> + * This file is part of the superiotool project. >> >> + * >> >> + * Copyright (C) 2010 Google Inc. >> >> + * Written by David Hendricks for Nuvoton >> Technology Corp. >> >> + * >> >> + * This program is free software; you can redistribute it and/or modify >> >> + * it under the terms of the GNU General Public License as published by >> >> + * the Free Software Foundation; either version 2 of the License, or >> >> + * (at your option) any later version. >> >> + * >> >> + * This program is distributed in the hope that it will be useful, >> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> >> + * GNU General Public License for more details. >> >> + * >> >> + * You should have received a copy of the GNU General Public License >> >> + * along with this program; if not, write to the Free Software >> >> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 >> USA >> >> + */ >> >> + >> >> +#include "superiotool.h" >> >> + >> >> +#define DEVICE_ID_REG 0x20 /* Super I/O ID >> (SID) / family */ >> >> +#define DEVICE_REV_REG 0x27 /* Super I/O >> revision ID (SRID) */ >> >> + >> >> +static const struct superio_registers reg_table[] = { >> >> + {0xfc, "WPCE775x / NPCE781x", { >> >> + {NOLDN, NULL, >> >> + >> {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, >> >> + >> 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, >> >> + >> {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, >> >> + >> 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, >> >> + {0x03, "CIR Port (CIRP)", /* where supported */ >> >> + >> {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, >> >> + >> {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, >> >> + {0x04, "Mobile System Wake-Up Control Config >> (MSWC)", >> >> + >> {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, >> >> + {0x05, "Mouse config (KBC)", >> >> + {0x30,0x70,0x71,0x74,0x75,EOT}, >> >> + {0x00,0x0c,0x03,0x04,0x04,EOT}}, >> >> + {0x06, "Keyboard config (KBC)", >> >> + >> {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x60,0x00,0x64,0x01,0x03,0x04,0x04,EOT}}, >> >> + {0x0f, "Shared memory (SHM)", >> >> + >> {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, >> >> + >> 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, >> >> + >> {0x00,0x00,0x00,0x00,0x00,0x04,0x04,MISC,0x07,RSVD, >> >> + >> RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, >> >> + {0x11, "Power management I/F Channel 1 (PM1)", >> >> + >> {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x62,0x00,0x66,0x01,0x03,0x04,0x04,EOT}}, >> >> + {0x12, "Power management I/F Channel 2 (PM2)", >> >> + >> {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,0x04,0x04,EOT}}, >> >> + {0x15, "Enhanced Wake On CIR (EWOC)", >> >> + >> {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, >> >> + {0x17, "Power Management I/F Channel 3 (PM3)", >> >> + >> {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, >> >> + >> {0x00,0x00,0x6a,0x00,0x6e,0x01,0x03,0x04,0x04,EOT}}, >> >> + {0x1a, "Serial Port with Fast Infrared Port >> (FIR)", >> >> + >> {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, >> >> + >> {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, >> >> + {EOT}}}, >> >> + {EOT} >> >> +}; >> >> + >> >> +void probe_idregs_nuvoton(uint16_t port) >> >> +{ >> >> + uint8_t sid, srid; >> >> + uint8_t chip_id = 0, chip_rev = 0; >> >> + >> >> + probing_for("Nuvoton", "(sid=0xfc) ", port); >> >> + >> >> + sid = regval(port, DEVICE_ID_REG); >> >> + srid = regval(port, DEVICE_REV_REG); >> >> + >> >> + if (sid == 0xfc) { /* WPCE775xL family */ >> >> + /* >> >> + * bits 7-5: Chip ID >> >> + * bits 4-0: Chip revision >> >> + */ >> >> + chip_id = srid >> 5; >> >> + chip_rev = srid & 0x1f; >> >> + } >> >> + >> >> + if (superio_unknown(reg_table, sid)) { >> >> + if (verbose) >> >> + printf(NOTFOUND "sid=0x%02x, >> id=0x%02x, rev=0x%02x\n", >> >> + sid, chip_id, chip_rev); >> >> + return; >> >> + } >> >> + >> >> + printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", >> >> + get_superio_name(reg_table, sid), >> chip_id, chip_rev, port); >> >> + chip_found = 1; >> >> + >> >> + dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); >> >> +} >> >> + >> >> +void print_nuvoton_chips(void) >> >> +{ >> >> + print_vendor_chips("Nuvoton", reg_table); >> >> +} >> >> Index: superiotool.h >> >> =================================================================== >> >> --- superiotool.h (revision 4892) >> >> +++ superiotool.h (working copy) >> >> @@ -133,6 +133,10 @@ >> >> void probe_idregs_nsc(uint16_t port); >> >> void print_nsc_chips(void); >> >> >> >> +/* nuvoton.c */ >> >> +void probe_idregs_nuvoton(uint16_t port); >> >> +void print_nuvoton_chips(void); >> >> + >> >> /* smsc.c */ >> >> void probe_idregs_smsc(uint16_t port); >> >> void print_smsc_chips(void); >> >> @@ -151,6 +155,9 @@ >> >> /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be >> valid. */ >> >> {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, >> >> {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, >> >> + /* I/O pairs on Nuvoton EC chips can be configured by firmware >> in >> >> + * addition to the following hardware strapping options. */ >> >> + {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, >> >> {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, >> 0x370, EOT}}, >> >> {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, >> 0x370, 0x250, EOT}}, >> >> }; >> >> @@ -163,6 +170,7 @@ >> >> {print_fintek_chips}, >> >> {print_ite_chips}, >> >> {print_nsc_chips}, >> >> + {print_nuvoton_chips}, >> >> {print_smsc_chips}, >> >> {print_winbond_chips}, >> >> }; >> >> Index: Makefile >> >> =================================================================== >> >> --- Makefile (revision 4892) >> >> +++ Makefile (working copy) >> >> @@ -32,7 +32,7 @@ >> >> CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing >> \ >> >> -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) >> >> >> >> -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o >> >> +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o >> winbond.o >> >> >> >> OS_ARCH = $(shell uname) >> >> ifeq ($(OS_ARCH), Darwin) >> >> >> =========================================================================================== >> The privileged confidential information contained in this email is >> intended for use only by the addressees as indicated by the original sender >> of this email. If you are not the addressee indicated in this email or are >> not responsible for delivery of the email to such a person, please kindly >> reply to the sender indicating this fact and delete all copies of it from >> your computer and network server immediately. Your cooperation is highly >> appreciated. It is advised that any unauthorized use of confidential >> information of Nuvoton is strictly prohibited; and any information in this >> email irrelevant to the official business of Nuvoton shall be deemed as >> neither given nor endorsed by Nuvoton. >> >> >> =========================================================================================== >> The privileged confidential information contained in this email is >> intended for use only by the addressees as indicated by the original sender >> of this email. If you are not the addressee indicated in this email or are >> not responsible for delivery of the email to such a person, please kindly >> reply to the sender indicating this fact and delete all copies of it from >> your computer and network server immediately. Your cooperation is highly >> appreciated. It is advised that any unauthorized use of confidential >> information of Nuvoton is strictly prohibited; and any information in this >> email irrelevant to the official business of Nuvoton shall be deemed as >> neither given nor endorsed by Nuvoton. >> >> -- >> >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: nuvoton_fixed_whitespace.patch Type: text/x-patch Size: 5654 bytes Desc: not available URL: From c-d.hailfinger.devel.2006 at gmx.net Thu Jul 22 23:57:42 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Thu, 22 Jul 2010 23:57:42 +0200 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> Message-ID: <4C48BED6.8000300@gmx.net> Hi Amit, hi David, thanks a lot for the patch! It will certainly help us a lot. Having superiotool support for WPCE775x/NPCE781x will finally allow us to debug the issues we were seeing with WPCE775L on flash access. On 22.07.2010 22:30, David Hendricks wrote: > Thanks for sending the patch out, Amit! > > Since I wrote this particular patch, I'll go ahead and do the sign-off on > it: > Signed-off by: David Hendricks (dhendrix at google.com) > > On Wed, Jul 21, 2010 at 12:00 AM, wrote: > > >> This is the same patch as before (2010/07/14) just with an updated >> copyright notice. >> The patch seems to have been damaged in transmit (whitespace corruption). It looks good from a first glance, but I can't test it in its current state. David, could you resend it (if in doubt, attach it to the mail to avoid corruption)? I'll do an in-depth review and commit it. Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Jul 23 00:56:45 2010 From: svn at coreboot.org (repository service) Date: Fri, 23 Jul 2010 00:56:45 +0200 Subject: [coreboot] [commit] r5667 - trunk/util/superiotool Message-ID: Author: hailfinger Date: Fri Jul 23 00:56:44 2010 New Revision: 5667 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5667 Log: Superiotool support for Nuvoton WPCE775x/NPCE781x. Signed-off-by: David Hendricks Acked-by: Carl-Daniel Hailfinger Added: trunk/util/superiotool/nuvoton.c Modified: trunk/util/superiotool/Makefile trunk/util/superiotool/superiotool.h Modified: trunk/util/superiotool/Makefile ============================================================================== --- trunk/util/superiotool/Makefile Fri Jul 16 22:02:09 2010 (r5666) +++ trunk/util/superiotool/Makefile Fri Jul 23 00:56:44 2010 (r5667) @@ -32,7 +32,7 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) Added: trunk/util/superiotool/nuvoton.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/superiotool/nuvoton.c Fri Jul 23 00:56:44 2010 (r5667) @@ -0,0 +1,107 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks for Nuvoton Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 /* Super I/O ID (SID) / family */ +#define DEVICE_REV_REG 0x27 /* Super I/O revision ID (SRID) */ + +static const struct superio_registers reg_table[] = { + {0xfc, "WPCE775x / NPCE781x", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, + 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, + {0x03, "CIR Port (CIRP)", /* where supported */ + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x04, "Mobile System Wake-Up Control Config (MSWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x05, "Mouse config (KBC)", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x03,0x04,0x04,EOT}}, + {0x06, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x03,0x04,0x04,EOT}}, + {0x0f, "Shared memory (SHM)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,MISC,0x07,RSVD, + RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x11, "Power management I/F Channel 1 (PM1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x03,0x04,0x04,EOT}}, + {0x12, "Power management I/F Channel 2 (PM2)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,0x04,0x04,EOT}}, + {0x15, "Enhanced Wake On CIR (EWOC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x17, "Power Management I/F Channel 3 (PM3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x03,0x04,0x04,EOT}}, + {0x1a, "Serial Port with Fast Infrared Port (FIR)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {EOT}}}, + {EOT} +}; + +void probe_idregs_nuvoton(uint16_t port) +{ + uint8_t sid, srid; + uint8_t chip_id = 0, chip_rev = 0; + + probing_for("Nuvoton", "(sid=0xfc) ", port); + + sid = regval(port, DEVICE_ID_REG); + srid = regval(port, DEVICE_REV_REG); + + if (sid == 0xfc) { /* WPCE775xL family */ + /* + * bits 7-5: Chip ID + * bits 4-0: Chip revision + */ + chip_id = srid >> 5; + chip_rev = srid & 0x1f; + } + + if (superio_unknown(reg_table, sid)) { + if (verbose) + printf(NOTFOUND + "sid=0x%02x, id=0x%02x, rev=0x%02x\n", sid, + chip_id, chip_rev); + return; + } + + printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, sid), chip_id, chip_rev, port); + chip_found = 1; + + dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); +} + +void print_nuvoton_chips(void) +{ + print_vendor_chips("Nuvoton", reg_table); +} Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Fri Jul 16 22:02:09 2010 (r5666) +++ trunk/util/superiotool/superiotool.h Fri Jul 23 00:56:44 2010 (r5667) @@ -143,6 +143,10 @@ void probe_idregs_nsc(uint16_t port); void print_nsc_chips(void); +/* nuvoton.c */ +void probe_idregs_nuvoton(uint16_t port); +void print_nuvoton_chips(void); + /* smsc.c */ void probe_idregs_smsc(uint16_t port); void print_smsc_chips(void); @@ -167,6 +171,9 @@ /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, + /* I/O pairs on Nuvoton EC chips can be configured by firmware in + * addition to the following hardware strapping options. */ + {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, #ifdef PCI_SUPPORT @@ -182,6 +189,7 @@ {print_fintek_chips}, {print_ite_chips}, {print_nsc_chips}, + {print_nuvoton_chips}, {print_smsc_chips}, {print_winbond_chips}, #ifdef PCI_SUPPORT From c-d.hailfinger.devel.2006 at gmx.net Fri Jul 23 01:03:27 2010 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Fri, 23 Jul 2010 01:03:27 +0200 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> Message-ID: <4C48CE3F.9050805@gmx.net> On 22.07.2010 23:55, David Hendricks wrote: > On Thu, Jul 22, 2010 at 1:30 PM, David Hendricks wrote > >> On Wed, Jul 21, 2010 at 12:00 AM, wrote: >>> This is the same patch as before (2010/07/14) just with an updated >>> copyright notice. >> >> Thanks for sending the patch out, Amit! >> >> Since I wrote this particular patch, I'll go ahead and do the sign-off >> on it: >> Signed-off-by: David Hendricks > the attached patch should address concerns about whitespace. > Thanks, looks good. Acked-by: Carl-Daniel Hailfinger and committed in r5667. If you want to check out the tree, please use svn co svn://coreboot.org/coreboot/trunk/util/superiotool Regards, Carl-Daniel -- http://www.hailfinger.org/ From svn at coreboot.org Fri Jul 23 01:11:34 2010 From: svn at coreboot.org (coreboot) Date: Thu, 22 Jul 2010 23:11:34 -0000 Subject: [coreboot] #134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC bus () In-Reply-To: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org> References: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org> Message-ID: <094.e535a2f50b8ff3b5cb33ac10640e68eb@coreboot.org> #134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC bus () --------------------------------------------------------------+------------- Reporter: Timo Juhani Lindfors | Owner: somebody Type: defect | Status: reopened Priority: minor | Milestone: Component: flashrom (please use trac on flashrom.org) | Resolution: Keywords: aspire laptop wpce775l ec embedded controller | Dependencies: Patch Status: there is no patch | --------------------------------------------------------------+------------- Changes (by hailfinger): * status: closed => reopened * resolution: wontfix => Comment: Could you please try to run superiotool again? The latest revision (r5667) has support for your EC and should work (unless the laptop manufacturer reconfigured the EC to listen on another address). Besides that, flashrom (0.9.2 or later) should detect that it is running on a laptop and abort immediately before anything bad can happen. We plan to whitelist some laptops eventually, but for now we're going the safe route. If flashrom does not detect your laptop as laptop, please file a new bug at http://www.flashrom.org/trac/flashrom/newticket I have reopened this ticket for now to keep it active until we know if superiotool works for you. -- Ticket URL: coreboot From greg at creativec.com Thu Jul 22 19:49:21 2010 From: greg at creativec.com (Greg Scantlen) Date: Thu, 22 Jul 2010 13:49:21 -0400 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: <4C4752E7.1050005@creativec.com> References: <4C4752E7.1050005@creativec.com> Message-ID: Hi Dale, Do you want to see the Statement of Work, Instruction for this Quote. If Creative were to get the award, I would need your (or someone's) help with setting up the serial console server, and online power management for PDUs. The timelines are rediculus, it could only be done by somewith a lot of experience. We're getting lot's of help from FlashRom.org, and CoreBoot.org already. I'm only interested in the H8QGi-G (or maybe H8DGU) motherboards. Greg On Wed, Jul 21, 2010 at 4:04 PM, Greg Scantlen wrote: > Hello Zheng Bao, > > I'm Greg at Creative Consultants in Albuquerque, NM. We build clusters, > mainly for LANL.I'm hoping to bid on a RFQ that involves coreboot for some > custom cluster nodes. I've been benchmarking a supermicro *H8QGi-Fmotherboard with (4)x 6128 CPUs and (16)x 4GB ECC UnBuff DDR > ***. Would this be a good candidate for core boot? I'm just starting > reading the Howto on coreboot now. I do have experience with flashing BIOS - > is that technique sufficient or should I have special equipment to get > started? Thanks for your guidance in advance. > > Greg > -------------- next part -------------- An HTML attachment was scrubbed... URL: From Zheng.Bao at amd.com Fri Jul 23 05:34:54 2010 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Fri, 23 Jul 2010 11:34:54 +0800 Subject: [coreboot] why "No irq handler for vector (irq -1)" Message-ID: I am porting coreboot to a new board. The processor is family 10 C32. The chipset is close to rs780. It seems to be quite close to ok. But the linux reports "No irq handler for vector (irq -1)". I am wondering whether IOAPIC or LAPIC will cause that problem. Or any other suggestion? Zheng ----------------------- Booting 'hda1:/boot/2.6.34-sb800 ro root=UUID=7f2a5ca6-6e6d-4fcd-a6cf-80c595592 6d3 console=ttyS0,115200 pci=nomsi initrd=hda1:/boot/initrd-2.6.34-sb800-bao' Found Linux version 2.6.34-sb800-bao (baozheng at localhost.localdomain) #8 SMP Fr i Jun 18 18:06:37 CST 2010 bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.34-sb800-bao (baozheng at localhost.localdomain) (gcc version 4.3 .2 20081007 (Red Hat 4.3.2-6) (GCC) ) #8 SMP Fri Jun 18 18:06:37 CST 2010 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 0000000000001000 type 16 [ 0.000000] BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) [ 0.000000] BIOS-e820: 00000000000c0000 - 0000000030000000 (usable) [ 0.000000] BIOS-e820: 0000000030000000 - 0000000040000000 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection cannot be enabled: non-PAE kernel! [ 0.000000] DMI not present or invalid. [ 0.000000] last_pfn = 0x30000 max_arch_pfn = 0x100000 [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] found SMP MP-table at [c00f0400] f0400 [ 0.000000] init_memory_mapping: 0000000000000000-0000000030000000 [ 0.000000] RAMDISK: 2fb50000 - 2fe9c000 [ 0.000000] ACPI Error: A valid RSDP was not found (20100121/tbxfroot-219) [ 0.000000] 0MB HIGHMEM available. [ 0.000000] 768MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 30000000 [ 0.000000] low ram: 0 - 30000000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000001 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x00030000 [ 0.000000] HighMem empty [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000001 -> 0x000000a0 [ 0.000000] 0: 0x00000100 -> 0x00030000 [ 0.000000] Using APIC driver default [ 0.000000] Intel MultiProcessor Specification v1.4 [ 0.000000] Virtual Wire compatibility mode. [ 0.000000] MPTABLE: OEM ID: COREBOOT [ 0.000000] MPTABLE: Product ID: PENSE [ 0.000000] MPTABLE: APIC at: 0xFEE00000 [ 0.000000] Processor #0 (Bootup-CPU) [ 0.000000] Processor #1 [ 0.000000] Processor #2 [ 0.000000] Processor #3 [ 0.000000] Processor #4 [ 0.000000] Processor #5 [ 0.000000] Processor #8 [ 0.000000] Processor #9 [ 0.000000] Processor #10 [ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 8 reached. Processor 8/0xa ignored. [ 0.000000] Processor #11 [ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 8 reached. Processor 9/0xb ignored. [ 0.000000] Processor #12 [ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 8 reached. Processor 10/0xc ignored. [ 0.000000] Processor #13 [ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 8 reached. Processor 11/0xd ignored. [ 0.000000] I/O APIC #33 Version 17 at 0xF0000000. [ 0.000000] Processors: 8 [ 0.000000] 12 Processors exceeds NR_CPUS limit of 8 [ 0.000000] SMP: Allowing 8 CPUs, 0 hotplug CPUs [ 0.000000] Allocating PCI resources starting at 40000000 (gap: 40000000:c0000000) [ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 13 pages/cpu @c2000000 s32724 r0 d20524 u524288 [ 0.000000] pcpu-alloc: s32724 r0 d20524 u524288 alloc=1*4194304 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 194975 [ 0.000000] Kernel command line: ro root=UUID=7f2a5ca6-6e6d-4fcd-a6cf-80c5955926d3 console=t tyS0,115200 pci=nomsi [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Enabling fast FPU save and restore... done. [ 0.000000] Enabling unmasked SIMD FPU exception support... done. [ 0.000000] Initializing CPU#0 [ 0.000000] Subtract (42 early reservations) [ 0.000000] #1 [0000001000 - 0000002000] EX TRAMPOLINE [ 0.000000] #2 [0001000000 - 00016253d0] TEXT DATA BSS [ 0.000000] #3 [002fb50000 - 002fe9c000] RAMDISK [ 0.000000] #4 [0001626000 - 000162c000] BRK [ 0.000000] #5 [000009f000 - 00000f0400] BIOS reserved [ 0.000000] #6 [00000f0400 - 00000f0410] MP-table mpf [ 0.000000] #7 [00000f0664 - 0000100000] BIOS reserved [ 0.000000] #8 [00000f0410 - 00000f0664] MP-table mpc [ 0.000000] #9 [0000002000 - 0000003000] TRAMPOLINE [ 0.000000] #10 [0000003000 - 0000007000] ACPI WAKEUP [ 0.000000] #11 [000162c000 - 000162d000] BOOTMEM [ 0.000000] #12 [000162d000 - 0001c2d000] BOOTMEM [ 0.000000] #13 [0001625400 - 0001625404] BOOTMEM [ 0.000000] #14 [0001625440 - 0001625500] BOOTMEM [ 0.000000] #15 [0001625500 - 0001625548] BOOTMEM [ 0.000000] #16 [0001c2d000 - 0001c30000] BOOTMEM [ 0.000000] #17 [0001625580 - 00016255a7] BOOTMEM [ 0.000000] #18 [00016255c0 - 0001625630] BOOTMEM [ 0.000000] #19 [0001625640 - 0001625680] BOOTMEM [ 0.000000] #20 [0001625680 - 00016256c0] BOOTMEM [ 0.000000] #21 [00016256c0 - 0001625700] BOOTMEM [ 0.000000] #22 [0001625700 - 0001625740] BOOTMEM [ 0.000000] #23 [0001625740 - 0001625791] BOOTMEM [ 0.000000] #24 [00016257c0 - 0001625811] BOOTMEM [ 0.000000] #25 [0002000000 - 000200d000] BOOTMEM [ 0.000000] #26 [0002080000 - 000208d000] BOOTMEM [ 0.000000] #27 [0002100000 - 000210d000] BOOTMEM [ 0.000000] #28 [0002180000 - 000218d000] BOOTMEM [ 0.000000] #29 [0002200000 - 000220d000] BOOTMEM [ 0.000000] #30 [0002280000 - 000228d000] BOOTMEM [ 0.000000] #31 [0002300000 - 000230d000] BOOTMEM [ 0.000000] #32 [0002380000 - 000238d000] BOOTMEM [ 0.000000] #33 [0001625840 - 0001625844] BOOTMEM [ 0.000000] #34 [0001625880 - 0001625884] BOOTMEM [ 0.000000] #35 [00016258c0 - 00016258e0] BOOTMEM [ 0.000000] #36 [0001625900 - 0001625920] BOOTMEM [ 0.000000] #37 [0001625940 - 00016259d8] BOOTMEM [ 0.000000] #38 [0001625a00 - 0001625a38] BOOTMEM [ 0.000000] #39 [0001c30000 - 0001c34000] BOOTMEM [ 0.000000] #40 [0001c34000 - 0001cb4000] BOOTMEM [ 0.000000] #41 [0001cb4000 - 0001cf4000] BOOTMEM [ 0.000000] Initializing HighMem for node 0 (00000000:00000000) [ 0.000000] Memory: 768960k/786432k available (3339k kernel code, 17084k reserved, 1887k dat a, 372k init, 0k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfff1e000 - 0xfffff000 ( 900 kB) [ 0.000000] pkmap : 0xff800000 - 0xffc00000 (4096 kB) [ 0.000000] vmalloc : 0xf0800000 - 0xff7fe000 ( 239 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) [ 0.000000] .init : 0xc151b000 - 0xc1578000 ( 372 kB) [ 0.000000] .data : 0xc1342d7a - 0xc151abe8 (1887 kB) [ 0.000000] .text : 0xc1000000 - 0xc1342d7a (3339 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] NR_IRQS:512 [ 0.000000] Console: colour dummy device 80x25 [ 0.000000] console [ttyS0] enabled [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 2200.073 MHz processor. [ 0.003014] Calibrating delay loop (skipped), value calculated using timer frequency.. 4400. 14 BogoMIPS (lpj=2200073) [ 0.005050] Security Framework initialized [ 0.006050] Mount-cache hash table entries: 512 [ 0.007365] Initializing cgroup subsys ns [ 0.008010] Initializing cgroup subsys cpuacct [ 0.010014] Initializing cgroup subsys freezer [ 0.011043] CPU: Physical Processor ID: 0 [ 0.012006] CPU: Processor Core ID: 0 [ 0.013012] mce: CPU supports 6 MCE banks [ 0.014033] using C1E aware idle routine [ 0.015022] Performance Events: AMD PMU driver. [ 0.017016] ... version: 0 [ 0.018006] ... bit width: 48 [ 0.019004] ... generic registers: 4 [ 0.020004] ... value mask: 0000ffffffffffff [ 0.021004] ... max period: 00007fffffffffff [ 0.022004] ... fixed-purpose events: 0 [ 0.023004] ... event mask: 000000000000000f [ 0.024022] Checking 'hlt' instruction... OK. [ 0.030588] Enabling APIC mode: Flat. Using 1 I/O APICs [ 0.032338] ..TIMER: vector=0x30 apic1=0 pin1=0 apic2=0 pin2=0 [ 0.032999] ..MP-BIOS bug: 8254 timer not connected to IO-APIC [ 0.032999] ...trying to set up timer (IRQ0) through the 8259A ... [ 0.032999] ..... (found apic 0 pin 0) ... [ 0.043281] ....... works. [ 0.044004] CPU0: AMD Thermal Test Kit stepping 01 [ 0.149446] Booting Node 0, Processors #1 [ 0.003999] Initializing CPU#1 [ 0.003999] do_IRQ: 1.55 No irq handler for vector (irq -1) [ 0.223153] #2 [ 0.003999] Initializing CPU#2 [ 0.003999] do_IRQ: 2.55 No irq handler for vector (irq -1) [ 0.297156] #3 [ 0.003999] Initializing CPU#3 [ 0.003999] do_IRQ: 3.55 No irq handler for vector (irq -1) [ 0.371154] #4 [ 0.003999] Initializing CPU#4 [ 0.003999] do_IRQ: 4.55 No irq handler for vector (irq -1) [ 0.445158] #5 [ 0.003999] Initializing CPU#5 [ 0.003999] do_IRQ: 5.55 No irq handler for vector (irq -1) [ 0.519159] #6 [ 0.003999] Initializing CPU#6 [ 0.003999] do_IRQ: 6.55 No irq handler for vector (irq -1) [ 0.593166] #7 Ok. [ 0.003999] Initializing CPU#7 [ 0.003999] do_IRQ: 7.55 No irq handler for vector (irq -1) [ 0.667034] Brought up 8 CPUs [ 0.668010] Total of 8 processors activated (35200.21 BogoMIPS). [ 0.671260] khelper used greatest stack depth: 7176 bytes left [ 0.673208] NET: Registered protocol family 16 [ 0.683087] TOM: 0000000040000000 aka 1024M [ 0.684028] TOM2: 0000000000000000 aka 0M [ 0.686364] PCI: Using configuration type 1 for base access [ 0.687003] PCI: Using configuration type 1 for extended access [ 0.721065] bio: create slab at 0 [ 0.723094] ACPI: Interpreter disabled. [ 0.724095] vgaarb: loaded [ 0.726079] SCSI subsystem initialized [ 0.729037] usbcore: registered new interface driver usbfs [ 0.730078] usbcore: registered new interface driver hub [ 0.731081] usbcore: registered new device driver usb [ 0.734047] Advanced Linux Sound Architecture Driver Version 1.0.22.1. [ 0.735008] PCI: Probing PCI hardware [ 0.738214] pci 0000:00:14.4: PCI bridge to [bus 01-01] (subtractive decode) [ 0.742085] vgaarb: device added: PCI:0000:01:06.0,decodes=io+mem,owns=io+mem,locks=none [ 0.744095] PCI: Discovered primary peer bus 10 [IRQ] [ 0.746157] cfg80211: Calling CRDA to update world regulatory domain [ 0.747085] NetLabel: Initializing [ 0.748005] NetLabel: domain hash size = 128 [ 0.749002] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.750032] NetLabel: unlabeled traffic allowed by default [ 0.752077] Switching to clocksource tsc [ 0.758546] pnp: PnP ACPI: disabled [ 0.765008] pci 0000:00:14.1: BAR 4: assigned [io 0x2030-0x203f] [ 0.771119] pci 0000:00:14.1: BAR 4: set to [io 0x2030-0x203f] (PCI address [0x2030-0x203f] [ 0.779554] pci 0000:00:14.4: PCI bridge to [bus 01-01] [ 0.784785] pci 0000:00:14.4: bridge window [io 0x1000-0x1fff] [ 0.790891] pci 0000:00:14.4: bridge window [mem 0xe0000000-0xe00fffff] [ 0.797682] pci 0000:00:14.4: bridge window [mem 0xe8000000-0xefffffff pref] [ 0.805118] NET: Registered protocol family 2 [ 0.809681] IP route cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.817548] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.827236] TCP bind hash table entries: 65536 (order: 7, 524288 bytes) [ 0.834995] TCP: Hash tables configured (established 131072 bind 65536) [ 0.841609] TCP reno registered [ 0.844765] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 0.850721] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 0.857377] NET: Registered protocol family 1 [ 0.862028] Trying to unpack rootfs image as initramfs... [ 1.131241] Freeing initrd memory: 3376k freed [ 1.142297] platform rtc_cmos: registered platform RTC device (no PNP device found) [ 1.204111] HugeTLB registered 4 MB page size, pre-allocated 0 pages [ 1.222322] VFS: Disk quotas dquot_6.5.2 [ 1.226556] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 1.235737] msgmni has been set to 1508 [ 1.240845] cryptomgr_test used greatest stack depth: 7168 bytes left [ 1.242144] alg: No test for stdrng (krng) [ 1.251400] cryptomgr_test used greatest stack depth: 6888 bytes left [ 1.251816] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 1.251826] io scheduler noop registered [ 1.251830] io scheduler deadline registered [ 1.252119] io scheduler cfq registered (default) [ 1.252901] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 1.284116] ------------[ cut here ]------------ [ 1.288761] WARNING: at fs/proc/generic.c:825 remove_proc_entry+0xa5/0x1a7() [ 1.295811] name 'fan' [ 1.298183] Modules linked in: [ 1.301277] Pid: 1, comm: swapper Not tainted 2.6.34-sb800-bao #8 [ 1.307374] Call Trace: [ 1.309846] [] ? remove_proc_entry+0xa5/0x1a7 [ 1.315170] [] warn_slowpath_common+0x60/0x90 [ 1.320490] [] warn_slowpath_fmt+0x24/0x27 [ 1.325551] [] remove_proc_entry+0xa5/0x1a7 [ 1.330703] [] ? acpi_button_init+0x0/0x4a [ 1.335763] [] ? proc_mkdir_mode+0x2f/0x43 [ 1.340823] [] ? acpi_fan_init+0x0/0x2c [ 1.345621] [] acpi_fan_init+0x23/0x2c [ 1.350330] [] do_one_initcall+0x4c/0x131 [ 1.355306] [] kernel_init+0x127/0x1a8 [ 1.360017] [] ? kernel_init+0x0/0x1a8 [ 1.364729] [] kernel_thread_helper+0x6/0x10 [ 1.369982] ---[ end trace a7919e7f17c0a725 ]--- [ 1.390836] Linux agpgart interface v0.103 [ 1.395749] [drm] Initialized drm 1.1.0 20060810 [ 1.400376] [drm:i915_init] *ERROR* drm/i915 can't work without intel_agp module! [ 1.407861] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled ??[ 1.658895] do_IRQ: 1.55 No irq handler for vector (irq -1) [ 1.658906] do_IRQ: 2.55 No irq handler for vector (irq -1) [ 1.658918] do_IRQ: 7.55 No irq handler for vector (irq -1) [ 1.659095] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.691713] brd: module loaded [ 1.699045] loop: module loaded [ 1.702199] Uniform Multi-Platform E-IDE driver [ 1.707240] ide-gd driver 1.18 [ 1.711848] ahci 0000:00:11.0: PCI->APIC IRQ transform: INT A -> IRQ 22 [ 1.718909] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl IDE mode [ 1.726913] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pmp pio slum part ccc [ 1.736741] scsi0 : ahci [ 1.739967] scsi1 : ahci [ 1.743131] scsi2 : ahci [ 1.746230] scsi3 : ahci [ 1.749227] ata1: SATA max UDMA/133 abar m1024 at 0xe0100000 port 0xe0100100 irq 22 [ 1.756626] ata2: SATA max UDMA/133 abar m1024 at 0xe0100000 port 0xe0100180 irq 22 [ 1.764023] ata3: SATA max UDMA/133 abar m1024 at 0xe0100000 port 0xe0100200 irq 22 [ 1.771417] ata4: SATA max UDMA/133 abar m1024 at 0xe0100000 port 0xe0100280 irq 22 [ 1.781034] Fixed MDIO Bus: probed [ 1.784481] console [netcon0] enabled [ 1.788150] netconsole: network logging started [ 1.793749] PNP: No PS/2 controller found. Probing ports directly. [ 2.052190] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 2.057650] mice: PS/2 mouse device common for all mice [ 2.063953] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 [ 2.070358] rtc0: alarms up to one day, 114 bytes nvram [ 2.076948] cpuidle: using governor ladder [ 2.081052] cpuidle: using governor menu [ 2.083879] ata2: SATA link down (SStatus 0 SControl 300) [ 2.083970] ata3: SATA link down (SStatus 0 SControl 300) [ 2.084112] ata4: SATA link down (SStatus 0 SControl 300) [ 2.107588] usbcore: registered new interface driver hiddev [ 2.113369] usbcore: registered new interface driver usbhid [ 2.118947] usbhid: USB HID core driver [ 2.126816] ALSA device list: [ 2.129795] No soundcards found. [ 2.133248] Netfilter messages via NETLINK v0.30. [ 2.138020] nf_conntrack version 0.5.0 (12067 buckets, 48268 max) [ 2.145034] ctnetlink v0.93: registering with nfnetlink. [ 2.151573] ip_tables: (C) 2000-2006 Netfilter Core Team [ 2.157034] TCP cubic registered [ 2.160277] NET: Registered protocol family 17 [ 2.164754] Using IPI No-Shortcut mode [ 2.236807] ata1: softreset failed (device not ready) [ 2.241870] ata1: applying SB600 PMP SRST workaround and retrying [ 2.400799] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 7.406122] ata1.00: qc timeout (cmd 0xec) [ 7.410238] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4) [ 7.874051] ata1: softreset failed (device not ready) [ 7.879108] ata1: applying SB600 PMP SRST workaround and retrying [ 8.038043] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 18.042696] ata1.00: qc timeout (cmd 0xec) [ 18.046809] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4) [ 18.052903] ata1: limiting SATA link speed to 1.5 Gbps [ 18.515635] ata1: softreset failed (device not ready) [ 18.520692] ata1: applying SB600 PMP SRST workaround and retrying [ 18.679630] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 310) [ 48.681630] ata1.00: qc timeout (cmd 0xec) [ 48.685742] ata1.00: failed to IDENTIFY (I/O error, err_mask=0x4) [ 49.149568] ata1: softreset failed (device not ready) [ 49.154627] ata1: applying SB600 PMP SRST workaround and retrying [ 49.313563] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 310) [ 49.330696] Freeing unused kernel memory: 372k freed [ 49.336697] Write protecting the kernel text: 3340k [ 49.341710] Write protecting the kernel read-only data: 1564k Mounting proc fi[ 49.355181] do_IRQ: 16 callbacks suppressed lesystem [ 49.356169] do_IRQ: 2.55 No irq handler for vector (irq -1) [ 49.360767] do_IRQ: 6.55 No irq handler for vector (irq -1) [ 49.360780] do_IRQ: 4.55 No irq handler for vector (irq -1) [ 49.355482] do_IRQ: 1.55 No irq handler for vector (irq -1) Mounting sysfs f[ 49.372768] do_IRQ: 3.55 No irq handler for vector (irq -1) [ 49.372778] do_IRQ: 4.55 No irq handler for vector (irq -1) ilesystem [ 49.372789] do_IRQ: 5.55 No irq handler for vector (irq -1) [ 49.372800] do_IRQ: 6.55 No irq handler for vector (irq -1) [ 49.372813] do_IRQ: 7.55 No irq handler for vector (irq -1) [ 49.372824] do_IRQ: 1.55 No irq handler for vector (irq -1) Creating /dev [ 49.692854] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver Creating initial device nodes [ 49.706978] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 49.713356] modprobe used greatest stack depth: 6828 bytes left [ 49.726499] uhci_hcd: USB Universal Host Controller Interface driver From bari at onelabs.com Fri Jul 23 06:55:09 2010 From: bari at onelabs.com (bari) Date: Thu, 22 Jul 2010 23:55:09 -0500 Subject: [coreboot] [patch] DDR3 support of AMD Family 10 In-Reply-To: References: <4C4752E7.1050005@creativec.com> Message-ID: <4C4920AD.8000309@onelabs.com> Greg Scantlen wrote: > Hi Dale, > > Do you want to see the Statement of Work, Instruction for this Quote. If > Creative were to get the award, I would need your (or someone's) help > with setting up the serial console server, and online power management > for PDUs. The timelines are rediculus, it could only be done by somewith > a lot of experience. We're getting lot's of help from FlashRom.org, and > CoreBoot.org already. I'm only interested in the H8QGi-G (or maybe > H8DGU) motherboards. Greg, "The sr5650 is in the progress. It is about 1 month to go." as Zheng Bao mentioned. It's going to take a few more months to get coreboot up on sr5670 or sr5690. They definitely will get coreboot support since there are funded projects for new coreboot mainboard designs using the sr5690 for HPC applications. Some boards will support multiple sr5690's and 8/12 core 6100 series G34 sockets along with drip free water cooled chassis and sub microsecond latency >2.5Gb/s network interconnects. -Bari From svn at coreboot.org Fri Jul 23 12:17:17 2010 From: svn at coreboot.org (coreboot) Date: Fri, 23 Jul 2010 10:17:17 -0000 Subject: [coreboot] #134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC bus () In-Reply-To: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org> References: <079.4f83eff2e689d10d548530ef42e0e66a@coreboot.org> Message-ID: <094.545bd4f8e0ef3e5189d7fb62cb11b6a4@coreboot.org> #134: flashrom crashes systems with WPC876x/WPCE775x embedded controller on LPC bus () --------------------------------------------------------------+------------- Reporter: Timo Juhani Lindfors | Owner: somebody Type: defect | Status: reopened Priority: minor | Milestone: Component: flashrom (please use trac on flashrom.org) | Resolution: Keywords: aspire laptop wpce775l ec embedded controller | Dependencies: Patch Status: there is no patch | --------------------------------------------------------------+------------- Comment (by Timo Juhani Lindfors ): Hmm, should tracker.coreboot.org sent me email about all these comments? I can't find any of them from my procmail.log. -- Ticket URL: coreboot From peter at stuge.se Fri Jul 23 14:49:40 2010 From: peter at stuge.se (Peter Stuge) Date: Fri, 23 Jul 2010 14:49:40 +0200 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: <4C48CE3F.9050805@gmx.net> <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> <4C48CE3F.9050805@gmx.net> <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> Message-ID: <20100723124940.5387.qmail@stuge.se> Hi Amit, David, list, Amit.Maoz at nuvoton.com wrote: > This is the same patch as before (2010/07/14) just with an updated > copyright notice. Thank you for the contribution from Nuvoton, Amit! I'm sorry about this belated feedback, but better late than never.. Like Carl-Daniel I am very happy that this work was committed, and I would like to point out a few things to keep in mind, should you wish to contribute further to the project. It's important that the copyright notice is correct, thank you for fixing this! Another thing that is also important is the Signed-off-by: which in this case came from David who created the patch. Please have a look at http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for the details about Signed-off-by. The point of the notice is to demonstrate that whoever sent us this patch really was allowed to, and really intended to, publish this code under the license used for coreboot. If one person is sending a patch that was developed by another person, this becomes particularly important. The patch should then have Signed-off-by: from both the person who wrote it, and the person who is sending it. Another thing that could be considered related to this is the email footer in your email, Amit. I know that you did not add it, but it is still somewhat problematic when sending patches to an open source project: > The privileged confidential information contained in this email is > intended for use only by the addressees as indicated by the > original sender of this email. The email footer strongly and directly contradicts a Signed-off-by:. A Signed-off-by: with your name says that you can release this patch under the open source license that coreboot uses, but the email footer says that this email is privileged and confidential. > If you are not the addressee indicated in this email or are not > responsible for delivery of the email to such a person, please > kindly reply to the sender indicating this fact and delete all > copies of it from your computer and network server immediately. > Your cooperation is highly appreciated. It is advised that any > unauthorized use of confidential information of Nuvoton is strictly > prohibited; and any information in this email irrelevant to the > official business of Nuvoton shall be deemed as neither given nor > endorsed by Nuvoton. We all know what little good these email footers do, but at the very least I think it would be wise to not introduce this contradiction for contributions to the project. It would be very good if you could make sure to send any patches in the future without such an email footer. David Hendricks wrote: > Thanks for sending the patch out, Amit! > > Since I wrote this particular patch, I'll go ahead and do the sign-off on > it: > Signed-off by: David Hendricks (dhendrix at google.com) Good stuff. Like Carl-Daniel I'm happy to see it go in! Thanks for sending the Signed-off-by: - otherwise the patch might not have been taken care of. Carl-Daniel Hailfinger wrote: > Acked-by: Carl-Daniel Hailfinger > and committed in r5667. Thanks to Carl-Daniel for ack and commit! I would've done it today otherwise. :) //Peter From anders at jenbo.dk Fri Jul 23 17:02:28 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Fri, 23 Jul 2010 17:02:28 +0200 Subject: [coreboot] LinuxBios P6IWP-Fe In-Reply-To: References: <1279838733.1808.18.camel@anders-desktop> Message-ID: The bios is only 256KB, but it is written as bit (8 bits per byte). Not being tied to Linux is actually a good thing as it gives more flexibility an we still have the possibility to have all the benefits of having Linux in there. I'm not sure what you are saying in the last part of you email, but if you plan to port more boards to coreboot that's grate :) What is your native language? If you could include both the original and translated text I might be better able to understand you. Mvh Anders Den 23/07/2010 kl. 15.02 skrev Alan Grossi : > Good Day Friend. Yes I will try and send the results. > > Too bad the Coreboot is no longer tied to Linux, but I want to study in depth and yes he still have bios. > > Was looking in my bios I found some scraps that I believe to work in ECS_P6IWP-Fe, bios 2MB. > > I really appreciate it if you send me a picture compiled. I'm still studying how to build the mine, but I do not see that long, I just risking. > > Thanks for everything. Sorry for any inconvenience. I have a vast collection of motherboards at home, or els with the test and then you step Coreboot results. So we can add even more to the list of cards supported. > > I'm not very good with English, so I'm using Google translator. Sorry the inconsistencies in the text. > > _______________________________________________________________________________________________________________________________________ > > > Subject: Re: LinuxBios P6IWP-Fe > > From: anders at jenbo.dk > > To: alan_roberto_grossi at hotmail.com > > Date: Fri, 23 Jul 2010 00:45:33 +0200 > > > > Hi i ported this board 45 dayes ago :) > > Here is the current status of the board > > http://www.coreboot.org/ECS_P6IWP-Fe > > If you test any thing make sure to send your result here so that we can > > update the table. > > > > LinuxBIOS is now know as Coreboot, this is because it is nolonger tied > > in to Linux (you still can do that if you want to). > > > > The rom flash chip on the board is fairly small, so putting a full linux > > on it might not be posible. But you can still run coreboot, with either > > FILO, GRUB or SeaBIOS as a payload and have one of them start up your > > installed linux. > > > > I can send you a compiled image tomorrow, if you like. > > > > To compile one your self: > > > > 1: make sure that you have all the tools mentioned here: > > http://www.coreboot.org/Development_Guidelines#Required_Toolchain > > (you can stop when you get to "Coding Guidelines") > > > > 2: follow this guide. > > http://www.coreboot.org/Build_HOWTO > > pick SeaBIOS as your payload, it's a safe bet for starters. > > > > Before you flash your motherboard you should consider getting a second > > flashrom-chip that you can safely flash, this way if things doesn't work > > you can get your motherboard back to life by placing back the original > > flashrom-chip. > > The chip you will need is an Intel 82802AB, it can be found on some > > other mother boards, i don't know if it is still possible to order it. > > It will look some thing like this: > > http://flashrom.org/File:Plcc32_in_socket.jpg > > > > -Anders > > > > tor, 22 07 2010 kl. 16:27 +0300, skrev Alan Grossi: > > > Good Day Friend. > > > > > > My name is ALAN GROSSI, I'm a fan of Linux. > > > > > > I have the Motherboard P6IWP-Fe and now I'm getting to know the Linux > > > BIOS project. > > > > > > I would like your help to configure and use this motherboard. > > > > > > Perhaps a bios ready. > > > > > > Sorry for the inconvenience. > > > > > > Thanks already. > > > > > > > > > > > > > > > > > > ______________________________________________________________________ > > > O INTERNET EXPLORER 8 AJUDA VOC? A FICAR LONGE DOS V?RUS. DESCUBRA > > > COMO. > > > > > > LEVE SEU MESSENGER PARA ONDE VOC? ESTIVER PELO SEU CELULAR. CLIQUE E VEJA COMO FAZER. -------------- next part -------------- An HTML attachment was scrubbed... URL: From Cristi.Magherusan at net.utcluj.ro Sat Jul 24 00:49:26 2010 From: Cristi.Magherusan at net.utcluj.ro (Cristi Magherusan) Date: Sat, 24 Jul 2010 01:49:26 +0300 Subject: [coreboot] [patch](trivial) Fix qemu target compilation with netconsole enabled Message-ID: <1279925366.11979.4.camel@ufo> Hi, See attached trivial patch. This fix might apply to other boards that only have -mcpu=i386 set in ROMCCFLAGS. Still, some won't work because of too large binaries that won't fit the ROM size when enabling the netconsole. Signed-off-by: Cristi Magherusan Regards, Cristi -- Cristi M?gheru?an, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Fix-for-qemu-target-compilation-with-the-RTL8029AS-n.patch Type: text/x-patch Size: 1020 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From vitplister at gmail.com Sat Jul 24 02:15:45 2010 From: vitplister at gmail.com (Mattias Mattsson) Date: Sat, 24 Jul 2010 02:15:45 +0200 Subject: [coreboot] [PATCH] Add id for ITE IT8707F Message-ID: <20100724001545.GA7185@vargen> Adds id for ITE IT8707F to superiotool. Signed-off-by: Mattias Mattsson Index: superiotool/ite.c =================================================================== --- superiotool/ite.c (revision 5667) +++ superiotool/ite.c (working copy) @@ -307,6 +307,8 @@ {0x8706, "IT8706R", { /* TODO: Not yet in sensors-detect */ /* This is a "Special General Purpose I/O chip". */ {EOT}}}, + {0x8707, "IT8707F", { + {EOT}}}, {0x8708, "IT8708F", { {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, From hagigatali at gmail.com Sat Jul 24 07:12:38 2010 From: hagigatali at gmail.com (ali hagigat) Date: Sat, 24 Jul 2010 09:42:38 +0430 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: <4C484F00.9070600@settoplinux.org> References: <4C484F00.9070600@settoplinux.org> Message-ID: You can talk about the Makefile too. How Coreboot is built in a typical scenario and by what tools. On Thu, Jul 22, 2010 at 6:30 PM, Joseph Smith wrote: > > > Brief summary about the presentation: > > 1. I plan on speaking a litle about myself, and how I got involved in > coreboot (elaborate on above). > > 2. Give a brief history on coreboot and how it started. > > 3. Go over some of the features of coreboot. > > 4. Go over some of the great tools that have sprouted off of the > coreboot tree. > > 5. Talk about how the code process flows and how you(audiance) can start > to develop coreboot. > > 6. Open for Question and Answer time. > > -------------------------------------- > > Do you guys think there is anything else I should touch on? > > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: From hagigatali at gmail.com Sat Jul 24 08:03:11 2010 From: hagigatali at gmail.com (ali hagigat) Date: Sat, 24 Jul 2010 10:33:11 +0430 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: My motherboard will be Kontron, 986LCD-M/mITX. I have not yet received it but very soon will have it. I am studying the technical info but answering my questions boosts my progress. I am not planing to make a product for sale and trying to expand my knowledge about BIOS and PC. I have a good time to spend for this project but seems to have to learn many new things first and deal with some PDFs every day. On Wed, Jul 21, 2010 at 5:53 PM, Corey Osgood wrote: > I think I just need to clarify a couple things: > > On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood > wrote: > > On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat > wrote: > >> My first impression from the BIOS open source project was an effort to > >> expand knowledge not to earn money!! > > There are lots of reasons open-source projects thrive. Most of them > involve money. Why are you working with coreboot? Is it (just a guess) > because you're developing a product to sell? > > >> > >> If any one wants to earn money he will find a technical job, will get > >> involved in deadlines of the project, will tolerate the pressure and > stress > >> of a challenging and rewarding work. > > Yeah, paying people to teach? What a ridiculous idea! > > >> > >> I thought we were here to help each other to understand the details of > the > >> science and technology involved and become ready to invent something new > or > >> to become ready for the projects in the market. > > And if you come on here with a *technical* issue, e.g. need a hand > initiating an HT link, memory controller, ide device, kernel errors, > etc, then the people on here will bend over backwards to help you out. > On the other hand, documentation exists for a reason, because we don't > have time to explain every line of code to every person who comes > along. > > >> > >> Though spending money for this case seems contrary to the first purposes > of > >> the project but money might be paid to responsible and eligible > technical > >> people. Who you recommend and where are those? > > http://www.coreboot.org/Products > http://www.google.com/search?q=coreboot+professional+development > > >> > >> I am ready to develop code for Coreboot but my knowledge is not enough > and I > >> suspect the knowledge of many users of this mailing list to be enough > for > >> it!! > > I really don't think that's the case. Read the mailing list archives, > how many questions do you see like yours? > > Alright, because I'm just plain too damn nice to leave it at this, if > you're still interested, what board/chipset are you working on? I'll > get you pointed in the right direction. I'm not going to explain how > every piece of coreboot works, but you really don't need to know to > write a working port. > > -Corey > > > > > Look dude, I'm getting tired of this nonsense. All the info you need > > is in the wiki and the documentation. How do I know? coreboot is one > > of the few projects I've gotten involved in. I'm not a professional > > developer, not even a great programmer. I don't build CPUs for a > > living, hell I don't even pretend to fully comprehend how everything > > works. Yet when I started with this project, I found all the info I > > needed to get started. And I've worked my way through to port a couple > > 440bx boards, the i810 chipset, and the cn700 chipset (albiet that one > > was left a little incomplete due to the untimely death of my cn700 > > board). If you're not willing to make the effort to find *basic* info, > > why the heck should we waste our time spoon feeding it to you? Because > > if you're not willing to make that little effort, you're probably not > > going to put in the effort to actually write the code, make it work, > > and contribute it back to the project. > > > > So, to reiterate carl-daniel's points: > > 1. Put forth the effort yourself to learn about the project > > 2. Pay someone to make it worth their while to spend their time > > educating you, rather then working on projects of their own, or > > 3. GTFO! > > > > -Corey > > > >> > >> On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger > >> wrote: > >>> > >>> Hi, > >>> > >>> let me explain a few things. > >>> > >>> On 21.07.2010 12:16, ali hagigat wrote: > >>> > The reason some of you do not like to answer is not lack of time. It > is > >>> > because you do not want other people know about the details of the > >>> > project, > >>> > > >>> > >>> We will tell you about the details of our project if you are friendly > >>> and if you read the documentation. > >>> > >>> > >>> > Rudolf, answering my questions take you not more than a few minutes > of > >>> > your > >>> > time and it is not a waste of time. Answering technical questions are > >>> > not a > >>> > waste of time, never, as it is a kind of practice and helps people > keep > >>> > their knowledge updated or refreshed. I did not ask you about > economics, > >>> > politics and the subjects unrelated to computer science, how can i > waste > >>> > your time? It is something you can benefit from if you think about it > >>> > unless > >>> > you have other reasons (that I am aware of!!) > >>> > > >>> > >>> We do not benefit from explaining things to you. > >>> You have shown an unwillingness to learn independently, so the project > >>> does not benefit from explaining things to you either. > >>> BUT... if you pay some of us _enough_ money, they will treat you as a > >>> customer and explain things to you even if you are unwilling to do any > >>> work yourself. > >>> > >>> Even if you promised to help us with developing coreboot, we would not > >>> benefit until the amount of development done by you saves other > >>> developers more time than they lose explaining things to you. We do not > >>> know you, and we have no way to make sure if you really intend to help > >>> or if you're just trolling. Your behaviour so far is pretty close to > >>> trolling. > >>> > >>> > >>> > I asked some questions to understand the overall framework of the > work > >>> > without going into the details. I knew about the wiki site of > Coreboot > >>> > before, how could i register at this mailing list while I found it by > >>> > Coreboot site!!? > >>> > > >>> > >>> Apparently you found the wiki, but you're unwilling or unable to read > >>> and understand the main contents, and focused on the mailing list > >>> instructions instead. > >>> > >>> > >>> > Go read wiki or the source code are the solutions I knew myself, i > have > >>> > the > >>> > source and the Internet connection... > >>> > > >>> > >>> And why don't you do that? > >>> > >>> You have three choices: > >>> 1. Be friendly. Read the source/documentation. We'll explain the rest. > >>> 2. Pay someone to explain this in private. > >>> 3. Leave. > >>> > >>> > >>> Regards, > >>> Carl-Daniel > >> > >> > >> -- > >> coreboot mailing list: coreboot at coreboot.org > >> http://www.coreboot.org/mailman/listinfo/coreboot > >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From mbertens at xs4all.nl Sat Jul 24 12:29:29 2010 From: mbertens at xs4all.nl (Marc Bertens) Date: Sat, 24 Jul 2010 12:29:29 +0200 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: <1279967369.18810.16.camel@enzo-matrix> Hi Ali, I read the main log from you and the replies you have received. You try to do what most of us takes us a couple of months. I'm involved with the coreboot project from a couple of months now and working on a piece of custom hardware (Nokia IP530). And still i don't know all the ins and outs of the project. But i read a lot of specification documentation to understand how hardware and firmware should work. For this i Google a lot, and if i can't find it i will ask a "Smart Question". To me it seems that you are not willing to read documentation thats out there. Besides reading documentation, it's necessary to read the source code of the project. So therefor dealing with PDFs all day is the starting point of any project. After which you start with reading the code of the project that you first need. So you project is underway and your learing on the job. I have only one thing to say further at this time: R.T.F.M, you can Google this or follow this link: http://en.wikipedia.org/wiki/RTFM I wish you good luck with de development of coreboot. Marc PS: A discussion to get it your way, will not work, there comes a time that people start ignoring you, and that cannot be your purpose i hope. Op zaterdag 24-07-2010 om 10:33 uur [tijdzone +0430], schreef ali hagigat: > My motherboard will be Kontron, 986LCD-M/mITX. > > I have not yet received it but very soon will have it. I am studying > the technical info but answering my questions boosts my progress. > > I am not planing to make a product for sale and trying to expand my > knowledge about BIOS and PC. I have a good time to spend for this > project but seems to have to learn many new things first and deal with > some PDFs every day. > > > On Wed, Jul 21, 2010 at 5:53 PM, Corey Osgood > wrote: > I think I just need to clarify a couple things: > > On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood > wrote: > > On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat > wrote: > >> My first impression from the BIOS open source project was > an effort to > >> expand knowledge not to earn money!! > > > There are lots of reasons open-source projects thrive. Most of > them > involve money. Why are you working with coreboot? Is it (just > a guess) > because you're developing a product to sell? > > >> > >> If any one wants to earn money he will find a technical > job, will get > >> involved in deadlines of the project, will tolerate the > pressure and stress > >> of a challenging and rewarding work. > > > Yeah, paying people to teach? What a ridiculous idea! > > >> > >> I thought we were here to help each other to understand the > details of the > >> science and technology involved and become ready to invent > something new or > >> to become ready for the projects in the market. > > > And if you come on here with a *technical* issue, e.g. need a > hand > initiating an HT link, memory controller, ide device, kernel > errors, > etc, then the people on here will bend over backwards to help > you out. > On the other hand, documentation exists for a reason, because > we don't > have time to explain every line of code to every person who > comes > along. > > >> > >> Though spending money for this case seems contrary to the > first purposes of > >> the project but money might be paid to responsible and > eligible technical > >> people. Who you recommend and where are those? > > > http://www.coreboot.org/Products > http://www.google.com/search?q=coreboot+professional > +development > > >> > >> I am ready to develop code for Coreboot but my knowledge is > not enough and I > >> suspect the knowledge of many users of this mailing list to > be enough for > >> it!! > > > I really don't think that's the case. Read the mailing list > archives, > how many questions do you see like yours? > > Alright, because I'm just plain too damn nice to leave it at > this, if > you're still interested, what board/chipset are you working > on? I'll > get you pointed in the right direction. I'm not going to > explain how > every piece of coreboot works, but you really don't need to > know to > write a working port. > > -Corey > > > > > > Look dude, I'm getting tired of this nonsense. All the info > you need > > is in the wiki and the documentation. How do I know? > coreboot is one > > of the few projects I've gotten involved in. I'm not a > professional > > developer, not even a great programmer. I don't build CPUs > for a > > living, hell I don't even pretend to fully comprehend how > everything > > works. Yet when I started with this project, I found all the > info I > > needed to get started. And I've worked my way through to > port a couple > > 440bx boards, the i810 chipset, and the cn700 chipset > (albiet that one > > was left a little incomplete due to the untimely death of my > cn700 > > board). If you're not willing to make the effort to find > *basic* info, > > why the heck should we waste our time spoon feeding it to > you? Because > > if you're not willing to make that little effort, you're > probably not > > going to put in the effort to actually write the code, make > it work, > > and contribute it back to the project. > > > > So, to reiterate carl-daniel's points: > > 1. Put forth the effort yourself to learn about the project > > 2. Pay someone to make it worth their while to spend their > time > > educating you, rather then working on projects of their own, > or > > 3. GTFO! > > > > -Corey > > > >> > >> On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger > >> wrote: > >>> > >>> Hi, > >>> > >>> let me explain a few things. > >>> > >>> On 21.07.2010 12:16, ali hagigat wrote: > >>> > The reason some of you do not like to answer is not lack > of time. It is > >>> > because you do not want other people know about the > details of the > >>> > project, > >>> > > >>> > >>> We will tell you about the details of our project if you > are friendly > >>> and if you read the documentation. > >>> > >>> > >>> > Rudolf, answering my questions take you not more than a > few minutes of > >>> > your > >>> > time and it is not a waste of time. Answering technical > questions are > >>> > not a > >>> > waste of time, never, as it is a kind of practice and > helps people keep > >>> > their knowledge updated or refreshed. I did not ask you > about economics, > >>> > politics and the subjects unrelated to computer science, > how can i waste > >>> > your time? It is something you can benefit from if you > think about it > >>> > unless > >>> > you have other reasons (that I am aware of!!) > >>> > > >>> > >>> We do not benefit from explaining things to you. > >>> You have shown an unwillingness to learn independently, so > the project > >>> does not benefit from explaining things to you either. > >>> BUT... if you pay some of us _enough_ money, they will > treat you as a > >>> customer and explain things to you even if you are > unwilling to do any > >>> work yourself. > >>> > >>> Even if you promised to help us with developing coreboot, > we would not > >>> benefit until the amount of development done by you saves > other > >>> developers more time than they lose explaining things to > you. We do not > >>> know you, and we have no way to make sure if you really > intend to help > >>> or if you're just trolling. Your behaviour so far is > pretty close to > >>> trolling. > >>> > >>> > >>> > I asked some questions to understand the overall > framework of the work > >>> > without going into the details. I knew about the wiki > site of Coreboot > >>> > before, how could i register at this mailing list while > I found it by > >>> > Coreboot site!!? > >>> > > >>> > >>> Apparently you found the wiki, but you're unwilling or > unable to read > >>> and understand the main contents, and focused on the > mailing list > >>> instructions instead. > >>> > >>> > >>> > Go read wiki or the source code are the solutions I knew > myself, i have > >>> > the > >>> > source and the Internet connection... > >>> > > >>> > >>> And why don't you do that? > >>> > >>> You have three choices: > >>> 1. Be friendly. Read the source/documentation. We'll > explain the rest. > >>> 2. Pay someone to explain this in private. > >>> 3. Leave. > >>> > >>> > >>> Regards, > >>> Carl-Daniel > >> > >> > >> -- > >> coreboot mailing list: coreboot at coreboot.org > >> http://www.coreboot.org/mailman/listinfo/coreboot > >> > > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From anders at jenbo.dk Sat Jul 24 13:35:38 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sat, 24 Jul 2010 13:35:38 +0200 Subject: [coreboot] LinuxBios P6IWP-Fe In-Reply-To: References: , <1279838733.1808.18.camel@anders-desktop> Message-ID: <9D84E3E20A19460FB1268F8A3397FAFE@AndersPc> Here is a prebuild rom for 512KB rom chips (it was what was in my board from the beginning). Make sure you have anothere chip with the original bios on it incase some thing goes wrong or i made a mistake when i build the image. -Anders From: Alan Grossi Sent: Friday, July 23, 2010 3:02 PM To: anders at jenbo.dk Subject: Re: LinuxBios P6IWP-Fe Good Day Friend. Yes I will try and send the results. Too bad the Coreboot is no longer tied to Linux, but I want to study in depth and yes he still have bios. Was looking in my bios I found some scraps that I believe to work in ECS_P6IWP-Fe, bios 2MB. I really appreciate it if you send me a picture compiled. I'm still studying how to build the mine, but I do not see that long, I just risking. Thanks for everything. Sorry for any inconvenience. I have a vast collection of motherboards at home, or els with the test and then you step Coreboot results. So we can add even more to the list of cards supported. I'm not very good with English, so I'm using Google translator. Sorry the inconsistencies in the text. _______________________________________________________________________________________________________________________________________ > Subject: Re: LinuxBios P6IWP-Fe > From: anders at jenbo.dk > To: alan_roberto_grossi at hotmail.com > Date: Fri, 23 Jul 2010 00:45:33 +0200 > > Hi i ported this board 45 dayes ago :) > Here is the current status of the board > http://www.coreboot.org/ECS_P6IWP-Fe > If you test any thing make sure to send your result here so that we can > update the table. > > LinuxBIOS is now know as Coreboot, this is because it is nolonger tied > in to Linux (you still can do that if you want to). > > The rom flash chip on the board is fairly small, so putting a full linux > on it might not be posible. But you can still run coreboot, with either > FILO, GRUB or SeaBIOS as a payload and have one of them start up your > installed linux. > > I can send you a compiled image tomorrow, if you like. > > To compile one your self: > > 1: make sure that you have all the tools mentioned here: > http://www.coreboot.org/Development_Guidelines#Required_Toolchain > (you can stop when you get to "Coding Guidelines") > > 2: follow this guide. > http://www.coreboot.org/Build_HOWTO > pick SeaBIOS as your payload, it's a safe bet for starters. > > Before you flash your motherboard you should consider getting a second > flashrom-chip that you can safely flash, this way if things doesn't work > you can get your motherboard back to life by placing back the original > flashrom-chip. > The chip you will need is an Intel 82802AB, it can be found on some > other mother boards, i don't know if it is still possible to order it. > It will look some thing like this: > http://flashrom.org/File:Plcc32_in_socket.jpg > > -Anders > > tor, 22 07 2010 kl. 16:27 +0300, skrev Alan Grossi: > > Good Day Friend. > > > > My name is ALAN GROSSI, I'm a fan of Linux. > > > > I have the Motherboard P6IWP-Fe and now I'm getting to know the Linux > > BIOS project. > > > > I would like your help to configure and use this motherboard. > > > > Perhaps a bios ready. > > > > Sorry for the inconvenience. > > > > Thanks already. > > > > > > > > > > > > ______________________________________________________________________ > > O INTERNET EXPLORER 8 AJUDA VOC? A FICAR LONGE DOS V?RUS. DESCUBRA > > COMO. > > -------------------------------------------------------------------------------- LEVE SEU MESSENGER PARA ONDE VOC? ESTIVER PELO SEU CELULAR. CLIQUE E VEJA COMO FAZER. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot.rom Type: application/octet-stream Size: 524288 bytes Desc: not available URL: From corey.osgood at gmail.com Sat Jul 24 16:34:32 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Sat, 24 Jul 2010 10:34:32 -0400 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: On Sat, Jul 24, 2010 at 2:03 AM, ali hagigat wrote: > My motherboard will be Kontron, 986LCD-M/mITX. Good grief. That board is already supported! http://www.coreboot.org/Kontron_986LCD-M_mITX -Corey > > I have not yet received it but very soon will have it. I am studying the > technical info but answering my questions boosts my progress. > > I am not planing to make a product for sale and trying to expand my > knowledge about BIOS and PC. I have a good time to spend for this project > but seems to have to learn many new things first and deal with some PDFs > every day. > > > On Wed, Jul 21, 2010 at 5:53 PM, Corey Osgood > wrote: >> >> I think I just need to clarify a couple things: >> >> On Wed, Jul 21, 2010 at 8:19 AM, Corey Osgood >> wrote: >> > On Wed, Jul 21, 2010 at 8:06 AM, ali hagigat >> > wrote: >> >> My first impression from the BIOS open source project was an effort to >> >> expand knowledge not to earn money!! >> >> There are lots of reasons open-source projects thrive. Most of them >> involve money. Why are you working with coreboot? Is it (just a guess) >> because you're developing a product to sell? >> >> >> >> >> If any one wants to earn money he will find a technical job, will get >> >> involved in deadlines of the project, will tolerate the pressure and >> >> stress >> >> of a challenging and rewarding work. >> >> Yeah, paying people to teach? What a ridiculous idea! >> >> >> >> >> I thought we were here to help each other to understand the details of >> >> the >> >> science and technology involved and become ready to invent something >> >> new or >> >> to become ready for the projects in the market. >> >> And if you come on here with a *technical* issue, e.g. need a hand >> initiating an HT link, memory controller, ide device, kernel errors, >> etc, then the people on here will bend over backwards to help you out. >> On the other hand, documentation exists for a reason, because we don't >> have time to explain every line of code to every person who comes >> along. >> >> >> >> >> Though spending money for this case seems contrary to the first >> >> purposes of >> >> the project but money might be paid to responsible and eligible >> >> technical >> >> people. Who you recommend and where are those? >> >> http://www.coreboot.org/Products >> http://www.google.com/search?q=coreboot+professional+development >> >> >> >> >> I am ready to develop code for Coreboot but my knowledge is not enough >> >> and I >> >> suspect the knowledge of many users of this mailing list to be enough >> >> for >> >> it!! >> >> I really don't think that's the case. Read the mailing list archives, >> how many questions do you see like yours? >> >> Alright, because I'm just plain too damn nice to leave it at this, if >> you're still interested, what board/chipset are you working on? I'll >> get you pointed in the right direction. I'm not going to explain how >> every piece of coreboot works, but you really don't need to know to >> write a working port. >> >> -Corey >> >> > >> > Look dude, I'm getting tired of this nonsense. All the info you need >> > is in the wiki and the documentation. How do I know? coreboot is one >> > of the few projects I've gotten involved in. I'm not a professional >> > developer, not even a great programmer. I don't build CPUs for a >> > living, hell I don't even pretend to fully comprehend how everything >> > works. Yet when I started with this project, I found all the info I >> > needed to get started. And I've worked my way through to port a couple >> > 440bx boards, the i810 chipset, and the cn700 chipset (albiet that one >> > was left a little incomplete due to the untimely death of my cn700 >> > board). If you're not willing to make the effort to find *basic* info, >> > why the heck should we waste our time spoon feeding it to you? Because >> > if you're not willing to make that little effort, you're probably not >> > going to put in the effort to actually write the code, make it work, >> > and contribute it back to the project. >> > >> > So, to reiterate carl-daniel's points: >> > 1. Put forth the effort yourself to learn about the project >> > 2. Pay someone to make it worth their while to spend their time >> > educating you, rather then working on projects of their own, or >> > 3. GTFO! >> > >> > -Corey >> > >> >> >> >> On Wed, Jul 21, 2010 at 3:56 PM, Carl-Daniel Hailfinger >> >> wrote: >> >>> >> >>> Hi, >> >>> >> >>> let me explain a few things. >> >>> >> >>> On 21.07.2010 12:16, ali hagigat wrote: >> >>> > The reason some of you do not like to answer is not lack of time. It >> >>> > is >> >>> > because you do not want other people know about the details of the >> >>> > project, >> >>> > >> >>> >> >>> We will tell you about the details of our project if you are friendly >> >>> and if you read the documentation. >> >>> >> >>> >> >>> > Rudolf, answering my questions take you not more than a few minutes >> >>> > of >> >>> > your >> >>> > time and it is not a waste of time. Answering technical questions >> >>> > are >> >>> > not a >> >>> > waste of time, never, as it is a kind of practice and helps people >> >>> > keep >> >>> > their knowledge updated or refreshed. I did not ask you about >> >>> > economics, >> >>> > politics and the subjects unrelated to computer science, how can i >> >>> > waste >> >>> > your time? It is something you can benefit from if you think about >> >>> > it >> >>> > unless >> >>> > you have other reasons (that I am aware of!!) >> >>> > >> >>> >> >>> We do not benefit from explaining things to you. >> >>> You have shown an unwillingness to learn independently, so the project >> >>> does not benefit from explaining things to you either. >> >>> BUT... if you pay some of us _enough_ money, they will treat you as a >> >>> customer and explain things to you even if you are unwilling to do any >> >>> work yourself. >> >>> >> >>> Even if you promised to help us with developing coreboot, we would not >> >>> benefit until the amount of development done by you saves other >> >>> developers more time than they lose explaining things to you. We do >> >>> not >> >>> know you, and we have no way to make sure if you really intend to help >> >>> or if you're just trolling. Your behaviour so far is pretty close to >> >>> trolling. >> >>> >> >>> >> >>> > I asked some questions to understand the overall framework of the >> >>> > work >> >>> > without going into the details. I knew about the wiki site of >> >>> > Coreboot >> >>> > before, how could i register at this mailing list while I found it >> >>> > by >> >>> > Coreboot site!!? >> >>> > >> >>> >> >>> Apparently you found the wiki, but you're unwilling or unable to read >> >>> and understand the main contents, and focused on the mailing list >> >>> instructions instead. >> >>> >> >>> >> >>> > Go read wiki or the source code are the solutions I knew myself, i >> >>> > have >> >>> > the >> >>> > source and the Internet connection... >> >>> > >> >>> >> >>> And why don't you do that? >> >>> >> >>> You have three choices: >> >>> 1. Be friendly. Read the source/documentation. We'll explain the rest. >> >>> 2. Pay someone to explain this in private. >> >>> 3. Leave. >> >>> >> >>> >> >>> Regards, >> >>> Carl-Daniel >> >> >> >> >> >> -- >> >> coreboot mailing list: coreboot at coreboot.org >> >> http://www.coreboot.org/mailman/listinfo/coreboot >> >> >> > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From anders at jenbo.dk Sun Jul 25 02:41:20 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 25 Jul 2010 02:41:20 +0200 Subject: [coreboot] compiling coreboot In-Reply-To: References: <4c45b70c.0e11df0a.7c73.fffff47bSMTPIN_ADDED@mx.google.com> <4C46D96E.4080407@gmx.net> Message-ID: <4C4B8830.5070209@jenbo.dk> On 21-07-2010 14:06, ali hagigat wrote: > My first impression from the BIOS open source project was an effort to > expand knowledge not to earn money!! No the project is not about making money. If you pay some one to help you learn it, it would be a private deal between you and that person, not you and "coreboot". I don't even know how to start a hallo world program in C, still I was able to port 2 boards, improve memory initilization for the 440BX chipset. My first mail to this list was to aske if my board was supported, my secound was sending the patch for the 440BX chip. So all the needed info to get started is clearly out there, you just have to want to read and understand it. The information that you will find on the wiki is probably more complete and more indebted then what you will get by asking some one as it has been thought threw a couple of times. You won't really be learning that much about the PC BIOS from Coreboot, so if that is your goal you should probably look in to SeaBIOS or send emails to eurosupport at phoenix.com - Anders From anders at jenbo.dk Sun Jul 25 02:48:51 2010 From: anders at jenbo.dk (Anders Jenbo) Date: Sun, 25 Jul 2010 02:48:51 +0200 Subject: [coreboot] ASUS K8V-MX In-Reply-To: <20100722141105.83200@gmx.com> References: <20100722141105.83200@gmx.com> Message-ID: <4C4B89F3.7080401@jenbo.dk> Hi The VT8237R is supported The K8M800 isn't but the K8M890 is and would probably be a good starting point for building support for the K8M800 if you can find the datasheet for it. We also need to know what SuporIO you have, you can find this by running superiotool. - Anders On 22-07-2010 16:02, phenon at gmx.com wrote: > Hello everyone... > I have an ASUS K8V-MX that I'd like to test coreboot on. > It has VIA's K8M800 / VT8237R as the chipset duo, > and an Athlon 64 3000+ 2GHz 754 CPU (ADA3000AIK4BX). > > The board link: > http://www.asus.com/product.aspx?P_ID=dJ2XP7zr8tzeYbLp > > Is it doable? I'm a first timer with coreboot... > > Cheers :) > > From rminnich at gmail.com Sun Jul 25 02:30:03 2010 From: rminnich at gmail.com (ron minnich) Date: Sat, 24 Jul 2010 17:30:03 -0700 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: <4C484F00.9070600@settoplinux.org> References: <4C484F00.9070600@settoplinux.org> Message-ID: I like to give a demo of a build, just so people can see the Kconfig interface and how quickly it goes. I'm been told EFI takes *hours* to build, for example. Coreboot is a nice contrast. ron From joe at settoplinux.org Sun Jul 25 07:23:48 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 25 Jul 2010 01:23:48 -0400 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: References: <4C484F00.9070600@settoplinux.org> Message-ID: <4C4BCA64.6080208@settoplinux.org> On 07/24/2010 01:12 AM, ali hagigat wrote: > You can talk about the Makefile too. How Coreboot is built in a typical > scenario and by what tools. > > You mean Kconfig and crossgcc? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From joe at settoplinux.org Sun Jul 25 07:28:48 2010 From: joe at settoplinux.org (Joseph Smith) Date: Sun, 25 Jul 2010 01:28:48 -0400 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: References: <4C484F00.9070600@settoplinux.org> Message-ID: <4C4BCB90.6050002@settoplinux.org> On 07/24/2010 08:30 PM, ron minnich wrote: > I like to give a demo of a build, just so people can see the Kconfig > interface and how quickly it goes. > > I'm been told EFI takes *hours* to build, for example. Coreboot is a > nice contrast. > Ok, good idea. I am also bringing some boards for a live demo :-) By the way Ron, is there a page on the wiki or somewhere that gives a little history I can use? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From rminnich at gmail.com Sun Jul 25 07:26:27 2010 From: rminnich at gmail.com (ron minnich) Date: Sat, 24 Jul 2010 22:26:27 -0700 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: <4C4BCA64.6080208@settoplinux.org> References: <4C484F00.9070600@settoplinux.org> <4C4BCA64.6080208@settoplinux.org> Message-ID: On Sat, Jul 24, 2010 at 10:23 PM, Joseph Smith wrote: > On 07/24/2010 01:12 AM, ali hagigat wrote: >> >> You can talk about the Makefile too. How Coreboot is built in a typical >> scenario and by what tools. >> >> > You mean Kconfig and crossgcc? well, usually, I just do a make kconfig pick a mainboard, drop out of Kconfig, type make And then explain that this simple config/build process takes tens of minutes to *hours* on many other firmware/BIOS systems. ron From patrick at georgi-clan.de Sun Jul 25 08:19:52 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 25 Jul 2010 08:19:52 +0200 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: References: <4C484F00.9070600@settoplinux.org> Message-ID: <4C4BD788.3020506@georgi-clan.de> Am 25.07.2010 02:30, schrieb ron minnich: > I'm been told EFI takes *hours* to build, for example. Coreboot is a > nice contrast. "Hours" is probably an exaggeration - but Tiano definitely takes longer than coreboot: 15-30 Minutes versus a couple of seconds. With Tiano you get a full OS with an object model, dynamic linker, drivers and filesystems, and that comes at a price (longer build time) - whether you need it or not ;-) Patrick From Amit.Maoz at nuvoton.com Sun Jul 25 08:00:47 2010 From: Amit.Maoz at nuvoton.com (Amit.Maoz at nuvoton.com) Date: Sun, 25 Jul 2010 09:00:47 +0300 Subject: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) In-Reply-To: <20100723124940.5387.qmail@stuge.se> References: <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> <4C48CE3F.9050805@gmx.net> <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> <8F2A7B0931C16B4C99DDA3B283A436301401DAFF@ntilml01.nuvoton.com> <20100723124940.5387.qmail@stuge.se> Message-ID: <8F2A7B0931C16B4C99DDA3B283A4363014053429@ntilml01.nuvoton.com> Hi Peter Thanks for the comments , this is all new for me and I did not know about the "Signed-off-by", so thanks for pointing that out. Regarding the footer there is nothing much I can do since I'm not adding it. I assume that it is added automatically by the Nuvoton mail server. Amit Maoz Advanced PC Division Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel Phone : +972-9-9702266 Fax : +972-9-9702001 Email : Amit.Maoz at nuvoton.com -----Original Message----- From: Peter Stuge [mailto:peter at stuge.se] Sent: Friday, July 23, 2010 3:50 PM To: IS30 Amit Maoz; David Hendricks; coreboot at coreboot.org Subject: Re: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright) Hi Amit, David, list, Amit.Maoz at nuvoton.com wrote: > This is the same patch as before (2010/07/14) just with an updated > copyright notice. Thank you for the contribution from Nuvoton, Amit! I'm sorry about this belated feedback, but better late than never.. Like Carl-Daniel I am very happy that this work was committed, and I would like to point out a few things to keep in mind, should you wish to contribute further to the project. It's important that the copyright notice is correct, thank you for fixing this! Another thing that is also important is the Signed-off-by: which in this case came from David who created the patch. Please have a look at http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure for the details about Signed-off-by. The point of the notice is to demonstrate that whoever sent us this patch really was allowed to, and really intended to, publish this code under the license used for coreboot. If one person is sending a patch that was developed by another person, this becomes particularly important. The patch should then have Signed-off-by: from both the person who wrote it, and the person who is sending it. Another thing that could be considered related to this is the email footer in your email, Amit. I know that you did not add it, but it is still somewhat problematic when sending patches to an open source project: > The privileged confidential information contained in this email is > intended for use only by the addressees as indicated by the > original sender of this email. The email footer strongly and directly contradicts a Signed-off-by:. A Signed-off-by: with your name says that you can release this patch under the open source license that coreboot uses, but the email footer says that this email is privileged and confidential. > If you are not the addressee indicated in this email or are not > responsible for delivery of the email to such a person, please > kindly reply to the sender indicating this fact and delete all > copies of it from your computer and network server immediately. > Your cooperation is highly appreciated. It is advised that any > unauthorized use of confidential information of Nuvoton is strictly > prohibited; and any information in this email irrelevant to the > official business of Nuvoton shall be deemed as neither given nor > endorsed by Nuvoton. We all know what little good these email footers do, but at the very least I think it would be wise to not introduce this contradiction for contributions to the project. It would be very good if you could make sure to send any patches in the future without such an email footer. David Hendricks wrote: > Thanks for sending the patch out, Amit! > > Since I wrote this particular patch, I'll go ahead and do the sign-off on > it: > Signed-off by: David Hendricks (dhendrix at google.com) Good stuff. Like Carl-Daniel I'm happy to see it go in! Thanks for sending the Signed-off-by: - otherwise the patch might not have been taken care of. Carl-Daniel Hailfinger wrote: > Acked-by: Carl-Daniel Hailfinger > and committed in r5667. Thanks to Carl-Daniel for ack and commit! I would've done it today otherwise. :) //Peter =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. From rminnich at gmail.com Sun Jul 25 17:04:20 2010 From: rminnich at gmail.com (ron minnich) Date: Sun, 25 Jul 2010 08:04:20 -0700 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: <4C4BD788.3020506@georgi-clan.de> References: <4C484F00.9070600@settoplinux.org> <4C4BD788.3020506@georgi-clan.de> Message-ID: On Sat, Jul 24, 2010 at 11:19 PM, Patrick Georgi wrote: > "Hours" is probably an exaggeration - but Tiano definitely takes longer > than coreboot: 15-30 Minutes versus a couple of seconds. > With Tiano you get a full OS with an object model, dynamic linker, > drivers and filesystems, and that comes at a price (longer build time) - > whether you need it or not ;-) Is Tiano smaller or larger than Linux at this point? ron From svn at coreboot.org Sun Jul 25 17:11:41 2010 From: svn at coreboot.org (coreboot) Date: Sun, 25 Jul 2010 15:11:41 -0000 Subject: [coreboot] #154: Flashing BIOSes from Fujitsu/Siemens is not supported In-Reply-To: <059.4093bb4ceb9998b5db17ea6e3fd78167@coreboot.org> References: <059.4093bb4ceb9998b5db17ea6e3fd78167@coreboot.org> Message-ID: <074.9a4cac3de3f2a0f97a2201951895528a@coreboot.org> #154: Flashing BIOSes from Fujitsu/Siemens is not supported -----------------------------------------------------------+---------------- Reporter: johannesobermayr@? | Owner: hailfinger Type: enhancement | Status: new Priority: trivial | Milestone: Component: flashrom (please use trac on flashrom.org) | Resolution: Keywords: | Dependencies: Patch Status: there is no patch | -----------------------------------------------------------+---------------- Comment (by johannesobermayr@?): First I wrote to Fujitsu and asked whether they want support by answering your questions here. Their answer was: they need an ID of my system. So I wrote to them: I do not believe that they support a 10 year old system, I do not have the ID by hand (system was 250 km away) and mentioned that my question was not a direct support request for a specific system. I also mentioned they can also benefit when supporting flashrom or coreboot by providing some information (may even by NDA). But as usual: I have not got an answer since then (~ 1.5 months). So I can only dream: A day is coming all "bad" companies falling down from their high horse and providing their specifications. Just for info: You can download a BIOS update file for a current System here: http://support.ts.fujitsu.com/download/ShowDescription.asp?SoftwareGUID=B64CBE64-D709-4F9A-9976-D2B2615438C0 May it has the same structure and reverse engineering is worth a try ... Thanks in advance. -- Ticket URL: coreboot From patrick at georgi-clan.de Sun Jul 25 19:01:20 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Sun, 25 Jul 2010 19:01:20 +0200 Subject: [coreboot] CentraLUG meeting, 2 August In-Reply-To: References: <4C484F00.9070600@settoplinux.org> <4C4BD788.3020506@georgi-clan.de> Message-ID: <4C4C6DE0.3060505@georgi-clan.de> Am 25.07.2010 17:04, schrieb ron minnich: > Is Tiano smaller or larger than Linux at this point? It's hard to beat Linux in bloat: smaller Patrick From kai_sch at gmx.net Sun Jul 25 23:53:56 2010 From: kai_sch at gmx.net (kai_sch at gmx.net) Date: Sun, 25 Jul 2010 23:53:56 +0200 Subject: [coreboot] Asus M8A-VM Message-ID: <20100725215356.53800@gmx.net> Hello everybody, I attended Peters talks on 25c3 and 26c3 (thanks! they were great) and finally found some time to play around with coreboot. Luckily I have a spare Asus M8A-VM (AMD690G). The board is listed as supported, but it is not in trunk/src/mainboard/asus. So what is the best way forward? I started to collect the files for a /m8a-vm directory from the kontron kt690 and adjusted them partially with snippets from a Gigabyte board and the Asus m8v-vm. Is that the right way to start or is there still a fileset for my board in the repo and I am just to thick to find it? If there is nothing available I have two questions: - How do I get the devicetree.cb file right? It looks like the lspci output with some extras. (e.g. the Kontron file contains the SuperIO, which is not listed in my lspci) - I try to get romstage.c working by copy&pasting and guessing. Is there a more systematic approach that I am missing? Ciao Kai -- GRATIS f?r alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01 From kai_sch at gmx.net Mon Jul 26 00:36:39 2010 From: kai_sch at gmx.net (kai_sch at gmx.net) Date: Mon, 26 Jul 2010 00:36:39 +0200 Subject: [coreboot] Asus M8A-VM In-Reply-To: <20100725215356.53800@gmx.net> References: <20100725215356.53800@gmx.net> Message-ID: <20100725223639.274640@gmx.net> Of course I menat the M2A-VM. Searching the mailing list basically answered my questions. I found the posting from Carl-Daniel Hailfinger that contains the necessary patches. Ciao Kai -------- Original-Nachricht -------- > Datum: Sun, 25 Jul 2010 23:53:56 +0200 > Von: kai_sch at gmx.net > An: coreboot at coreboot.org > Betreff: [coreboot] Asus M8A-VM > Hello everybody, > > I attended Peters talks on 25c3 and 26c3 (thanks! they were great) and > finally found some time to play around with coreboot. Luckily I have a spare > Asus M8A-VM (AMD690G). > > The board is listed as supported, but it is not in > trunk/src/mainboard/asus. So what is the best way forward? > > I started to collect the files for a /m8a-vm directory from the kontron > kt690 and adjusted them partially with snippets from a Gigabyte board and the > Asus m8v-vm. > > Is that the right way to start or is there still a fileset for my board in > the repo and I am just to thick to find it? > > If there is nothing available I have two questions: > - How do I get the devicetree.cb file right? It looks like the lspci > output with some extras. (e.g. the Kontron file contains the SuperIO, which is > not listed in my lspci) > - I try to get romstage.c working by copy&pasting and guessing. Is there a > more systematic approach that I am missing? > > Ciao > > Kai > > > > > -- > GRATIS f?r alle GMX-Mitglieder: Die maxdome Movie-FLAT! > Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01 > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- GMX DSL: Internet-, Telefon- und Handy-Flat ab 19,99 EUR/mtl. Bis zu 150 EUR Startguthaben inklusive! http://portal.gmx.net/de/go/dsl From hagigatali at gmail.com Mon Jul 26 11:58:08 2010 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 26 Jul 2010 14:28:08 +0430 Subject: [coreboot] Coreboot Makefile Message-ID: I wonder if any body can say what is the major effect of INNER_SCANBUILD symbol in making the project? From patrick at georgi-clan.de Mon Jul 26 12:00:04 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 26 Jul 2010 12:00:04 +0200 Subject: [coreboot] Coreboot Makefile In-Reply-To: References: Message-ID: <4C4D5CA4.8030002@georgi-clan.de> Am 26.07.2010 11:58, schrieb ali hagigat: > I wonder if any body can say what is the major effect of > INNER_SCANBUILD symbol in making the project? It's used when building coreboot under scanbuild (part of clang), which does static analysis of the code. Unless you want to tweak that particular piece of the build system, you don't have to care about it. Patrick From hagigatali at gmail.com Mon Jul 26 12:09:32 2010 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 26 Jul 2010 14:39:32 +0430 Subject: [coreboot] Coreboot Makefile In-Reply-To: <4C4D5CA4.8030002@georgi-clan.de> References: <4C4D5CA4.8030002@georgi-clan.de> Message-ID: Thank you very much for the reply. What is the name of the RPM of scanbuild or clang for Fedora, Linux? clang is the name of the package? On 7/26/10, Patrick Georgi wrote: > Am 26.07.2010 11:58, schrieb ali hagigat: >> I wonder if any body can say what is the major effect of >> INNER_SCANBUILD symbol in making the project? > It's used when building coreboot under scanbuild (part of clang), which > does static analysis of the code. > > Unless you want to tweak that particular piece of the build system, you > don't have to care about it. > > > Patrick > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From patrick at georgi-clan.de Mon Jul 26 12:16:17 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 26 Jul 2010 12:16:17 +0200 Subject: [coreboot] Coreboot Makefile In-Reply-To: References: <4C4D5CA4.8030002@georgi-clan.de> Message-ID: <4C4D6071.6080906@georgi-clan.de> Am 26.07.2010 12:09, schrieb ali hagigat: > Thank you very much for the reply. What is the name of the RPM of > scanbuild or clang for Fedora, Linux? clang is the name of the > package? Your previous question was good, it was about something specific to coreboot, even though you could try to decide which topics are important to your work and which aren't. The question (and its answer) most likely didn't help you in the slightest. However this question has nothing to do with coreboot. Research it yourself, if you're really interested. And before you start to whine that I hold back information and write this-and-that many lines of meta discussion instead of answering your question: I have no idea about rpm or fedora and don't use linux for coreboot development. Therefore the answer to that question is of no value to me, and I won't waste my time just to help you avoiding doing work yourself. Patrick From vitplister at gmail.com Mon Jul 26 12:32:12 2010 From: vitplister at gmail.com (Mattias Mattsson) Date: Mon, 26 Jul 2010 12:32:12 +0200 Subject: [coreboot] [PATCH] Add id for ITE IT8707F In-Reply-To: <20100724001545.GA7185@vargen> References: <20100724001545.GA7185@vargen> Message-ID: Hi, As requested on IRC, here's some additional info. Unfortunately I was unable to find any specs or a datasheet for IT8707F. What I did find was this (old) note from the lm-sensors project wiki: "ITE IT8707F: (2003-08-23) ITE won't release a datasheet, but says the sensor part is identical to IT8712F." ( http://www.lm-sensors.org/wiki/Devices?version=308 ) Attached is output from superiotool (with patch) detecting the chip on an Asus P4SC-E board. Thanks, -mattias -------------- next part -------------- superiotool r5667 Found ITE IT8707F (id=0x8707, rev=0x0) at 0x2e From svn at coreboot.org Mon Jul 26 16:00:01 2010 From: svn at coreboot.org (coreboot tracker) Date: Mon, 26 Jul 2010 16:00:01 +0200 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From mylesgw at gmail.com Mon Jul 26 18:57:18 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 10:57:18 -0600 Subject: [coreboot] Broken include paths Message-ID: There are a couple of boards that don't compile for me with crossgcc. Here's a representative error: src/mainboard/asus/a8v-e_se/mptable.c:23:54: error: src/include/../../../southbridge/via/vt8237r/vt8237r.h: Permission denied The problem is that the compiler is looking for the file ../../../southbridge... starting from src/include, since it was specified with <> There are many ways to fix it, but I'm not sure which one is the correct (most future-proof) way. Here are three of the possible fixes: 1. Use "" so the path is relative to the file. Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn/src/mainboard/asus/a8v-e_se/mptable.c (revision 5667) +++ svn/src/mainboard/asus/a8v-e_se/mptable.c (working copy) @@ -20,8 +20,8 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" static void *smp_write_config_table(void *v) { 2. Make the path valid from src/include Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn/src/mainboard/asus/a8v-e_se/mptable.c (revision 5667) +++ svn/src/mainboard/asus/a8v-e_se/mptable.c (working copy) @@ -20,8 +20,8 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include <../southbridge/via/vt8237r/vt8237r.h> +#include <../southbridge/via/k8t890/k8t890.h> static void *smp_write_config_table(void *v) { 3. Just use the path Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn.orig/src/mainboard/asus/a8v-e_se/mptable.c +++ svn/src/mainboard/asus/a8v-e_se/mptable.c @@ -20,8 +20,8 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include +#include static void *smp_write_config_table(void *v) { They all compile for me. Thanks, Myles From peter at stuge.se Mon Jul 26 19:09:01 2010 From: peter at stuge.se (Peter Stuge) Date: Mon, 26 Jul 2010 19:09:01 +0200 Subject: [coreboot] Broken include paths In-Reply-To: References: Message-ID: <20100726170901.14678.qmail@stuge.se> Myles Watson wrote: > There are many ways to fix it, but I'm not sure which one is the > correct (most future-proof) way. .. > 3. Just use the path I think this is *by far* the cleanest approach! //Peter From mylesgw at gmail.com Mon Jul 26 19:28:27 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 11:28:27 -0600 Subject: [coreboot] Broken include paths In-Reply-To: <20100726170901.14678.qmail@stuge.se> References: <20100726170901.14678.qmail@stuge.se> Message-ID: On Mon, Jul 26, 2010 at 11:09 AM, Peter Stuge wrote: > Myles Watson wrote: >> There are many ways to fix it, but I'm not sure which one is the >> correct (most future-proof) way. > .. >> 3. Just use the path > > I think this is *by far* the cleanest approach! I agree that it looks the best. I'm worried that it introduces ambiguity. #include Could look in src/path/file.h or src/include/path/file.h and others Is that what we want? Should we remove -I$(src) from the command line in the long term? from src/arch/i386/Makefile.bootblock.inc: $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ It seems like it could be simpler. I also don't understand the order. Thanks, Myles From peter at stuge.se Mon Jul 26 20:01:31 2010 From: peter at stuge.se (Peter Stuge) Date: Mon, 26 Jul 2010 20:01:31 +0200 Subject: [coreboot] Broken include paths In-Reply-To: References: <20100726170901.14678.qmail@stuge.se> Message-ID: <20100726180131.22915.qmail@stuge.se> Myles Watson wrote: > >> 3. Just use the path > > > > I think this is *by far* the cleanest approach! > > I agree that it looks the best. I'm worried that it introduces > ambiguity. > > #include > > Could look in src/path/file.h or src/include/path/file.h and others > > Is that what we want? Should we remove -I$(src) from the command line > in the long term? I'm not sure that I feel good about .h files outside include/ being referenced from other parts of the code. They should probably be moved to include/ if they are needed in more than one place.. > from src/arch/i386/Makefile.bootblock.inc: > > $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include > -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include > $(obj)/config.h -I. -I$(src) $< -o $@ > > It seems like it could be simpler. I think simplifying the codebase will be a continuous effort. > I also don't understand the order. Me neither. And again, why are there include files in src/arch/i386/include instead of include/arch-i386 or something? //Peter From patrick at georgi-clan.de Mon Jul 26 20:57:02 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 26 Jul 2010 20:57:02 +0200 Subject: [coreboot] Broken include paths In-Reply-To: <20100726180131.22915.qmail@stuge.se> References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> Message-ID: <4C4DDA7E.5090109@georgi-clan.de> Am 26.07.2010 20:01, schrieb Peter Stuge: > I'm not sure that I feel good about .h files outside include/ being > referenced from other parts of the code. They should probably be > moved to include/ if they are needed in more than one place.. Mainboards need to include chipset specific information, and I'd like to avoid moving all that into include/ if possible. >> I also don't understand the order. > Me neither. And again, why are there include files in > src/arch/i386/include instead of include/arch-i386 or something? It was partially inherited from newconfig, partially "what works". And I guess that was how it was handled throughout newconfig's lifecycle, too. Patrick From mylesgw at gmail.com Mon Jul 26 20:59:40 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 12:59:40 -0600 Subject: [coreboot] Broken include paths In-Reply-To: <4C4DDA7E.5090109@georgi-clan.de> References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> <4C4DDA7E.5090109@georgi-clan.de> Message-ID: On Mon, Jul 26, 2010 at 12:57 PM, Patrick Georgi wrote: > Am 26.07.2010 20:01, schrieb Peter Stuge: >> I'm not sure that I feel good about .h files outside include/ being >> referenced from other parts of the code. They should probably be >> moved to include/ if they are needed in more than one place.. > Mainboards need to include chipset specific information, and I'd like to > avoid moving all that into include/ if possible. I think that's a reasonable exception to the rule. Some of that code could move to the chipsets, but not all of it. Thanks, Myles From mylesgw at gmail.com Mon Jul 26 21:17:03 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 13:17:03 -0600 Subject: [coreboot] Broken include paths In-Reply-To: <20100726180131.22915.qmail@stuge.se> References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> Message-ID: On Mon, Jul 26, 2010 at 12:01 PM, Peter Stuge wrote: > Myles Watson wrote: >> >> 3. Just use the path >> > >> > I think this is *by far* the cleanest approach! >> >> I agree that it looks the best. ?I'm worried that it introduces >> ambiguity. >> >> #include >> >> Could look in src/path/file.h or src/include/path/file.h and others >> >> Is that what we want? ?Should we remove -I$(src) from the command line >> in the long term? It won't be, but I think it should only be used for including .c files for romcc. > I'm not sure that I feel good about .h files outside include/ being > referenced from other parts of the code. They should probably be > moved to include/ if they are needed in more than one place.. So I guess option 1 is the best. It makes it obvious (and ugly) when that rule is ignored. > >> from src/arch/i386/Makefile.bootblock.inc: >> >> $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include >> -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include >> $(obj)/config.h -I. -I$(src) $< -o $@ I forgot about all of our included .c files. That's the reason for -I$(src). > And again, why are there include files in > src/arch/i386/include instead of include/arch-i386 or something? Linux does it that way. It keeps all of the architecture-specific code and includes under arch/ include_path.diff: fix the ones that are broken for me. include_path2.diff: fix the ones that look identical but work anyway. include_path3.diff: fix <../path/file.h> to be "../../../path/file.h" to make it obvious that they're not in src/include Abuild tested. Signed-off-by: Myles Watson Thanks, Myles -------------- next part -------------- A non-text attachment was scrubbed... Name: include_path.diff Type: text/x-diff Size: 2331 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: include_path2.diff Type: text/x-diff Size: 8227 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: include_path3.diff Type: text/x-diff Size: 5190 bytes Desc: not available URL: From peter at stuge.se Mon Jul 26 21:22:40 2010 From: peter at stuge.se (Peter Stuge) Date: Mon, 26 Jul 2010 21:22:40 +0200 Subject: [coreboot] Broken include paths In-Reply-To: <4C4DDA7E.5090109@georgi-clan.de> References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> <4C4DDA7E.5090109@georgi-clan.de> <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> <4C4DDA7E.5090109@georgi-clan.de> Message-ID: <20100726192240.1828.qmail@stuge.se> Patrick Georgi wrote: > > .h files outside include/ > > They should probably be moved to include/ > > Mainboards need to include chipset specific information, and I'd > like to avoid moving all that into include/ if possible. Why not do it? Myles Watson wrote: > I think that's a reasonable exception to the rule. Why have an exception at all? > Some of that code could move to the chipsets, but not all of it. Hmm, can you clarify? //Peter From mylesgw at gmail.com Mon Jul 26 21:28:09 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 13:28:09 -0600 Subject: [coreboot] Broken include paths In-Reply-To: <20100726192240.1828.qmail@stuge.se> References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> <4C4DDA7E.5090109@georgi-clan.de> <20100726192240.1828.qmail@stuge.se> Message-ID: On Mon, Jul 26, 2010 at 1:22 PM, Peter Stuge wrote: > Patrick Georgi wrote: >> > .h files outside include/ >> > They should probably be moved to include/ >> >> Mainboards need to include chipset specific information, and I'd >> like to avoid moving all that into include/ if possible. > > Why not do it? It's used in multiple places, but only two or three usually. > Myles Watson wrote: >> I think that's a reasonable exception to the rule. > > Why have an exception at all? So src/include/ doesn't get cluttered. >> Some of that code could move to the chipsets, but not all of it. > > Hmm, can you clarify? I was thinking of some of the ACPI code, that is not mainboard-dependent but chipset-dependent. That's been slowly moving to the chipset directories. Some of the mainboard initialization code calls functions depending on what's on the board. That won't be moved. Thanks, Myles From stefan.reinauer at coresystems.de Mon Jul 26 21:57:24 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Mon, 26 Jul 2010 21:57:24 +0200 Subject: [coreboot] Broken include paths In-Reply-To: References: <20100726170901.14678.qmail@stuge.se> <20100726180131.22915.qmail@stuge.se> <4C4DDA7E.5090109@georgi-clan.de> <20100726192240.1828.qmail@stuge.se> Message-ID: <4C4DE8A4.9080505@coresystems.de> On 7/26/10 9:28 PM, Myles Watson wrote: > I was thinking of some of the ACPI code, that is not > mainboard-dependent but chipset-dependent. That's been slowly moving > to the chipset directories. > If we can get rid of exceptions by cleaning more code up in this way we should certainly do it. Stefan From njacobs8 at hetnet.nl Mon Jul 26 22:07:20 2010 From: njacobs8 at hetnet.nl (Nils) Date: Mon, 26 Jul 2010 22:07:20 +0200 Subject: [coreboot] Broken include paths Message-ID: <201007262207.21127.njacobs8@hetnet.nl> Myles wrote: >Linux does it that way. It keeps all of the architecture-specific >code and includes under arch/ > >include_path.diff: fix the ones that are broken for me. >include_path2.diff: fix the ones that look identical but work anyway. >include_path3.diff: fix <../path/file.h> to be "../../../path/file.h" >to make it obvious that they're not in src/include > >Abuild tested. > >Signed-off-by: Myles Watson I like that. Acked-by: Nils Jacobs Thanks,Nils. From svn at coreboot.org Mon Jul 26 23:45:11 2010 From: svn at coreboot.org (repository service) Date: Mon, 26 Jul 2010 23:45:11 +0200 Subject: [coreboot] [commit] r5668 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/tilapia_fam10 mainboar... Message-ID: Author: myles Date: Mon Jul 26 23:45:11 2010 New Revision: 5668 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5668 Log: Make include paths more consistent. Fixes compilation errors for me. Signed-off-by: Myles Watson Acked-by: Nils Jacobs Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/dbm690t/fadt.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany/fadt.c trunk/src/mainboard/amd/mahogany_fam10/fadt.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/pistachio/fadt.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/tilapia_fam10/fadt.c trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asrock/939a785gmh/fadt.c trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/kontron/kt690/fadt.c trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim5690/fadt.c trunk/src/mainboard/technexion/tim5690/speaker.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/fadt.c trunk/src/mainboard/tyan/s2891/acpi_tables.c trunk/src/mainboard/tyan/s2892/acpi_tables.c trunk/src/mainboard/tyan/s2895/acpi_tables.c trunk/src/mainboard/via/epia-m700/acpi_tables.c trunk/src/mainboard/via/epia-m700/fadt.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/northbridge/via/vx800/examples/chipset_init.c Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/amd/dbm690t/fadt.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/dbm690t/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/amd/mahogany/fadt.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/mahogany_fam10/fadt.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany_fam10/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/pistachio/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/amd/pistachio/fadt.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/pistachio/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -16,7 +16,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include "mb_sysconf.h" Modified: trunk/src/mainboard/amd/tilapia_fam10/fadt.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/tilapia_fam10/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/asrock/939a785gmh/fadt.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asrock/939a785gmh/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -28,8 +28,8 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Mon Jul 26 23:45:11 2010 (r5668) @@ -20,8 +20,8 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" static void *smp_write_config_table(void *v) { Modified: trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -28,9 +28,9 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include #include Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -16,7 +16,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include "mb_sysconf.h" Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/kontron/kt690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/kontron/kt690/fadt.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/kontron/kt690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include #include #include -//#include <../../../northbridge/amd/amdfam10/amdfam10_acpi.h> +//#include "../../../northbridge/amd/amdfam10/amdfam10_acpi.h" #include #include #include Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/technexion/tim5690/fadt.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/technexion/tim5690/speaker.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/speaker.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/speaker.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" #include #endif /* __PRE_RAM__ */ Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include #include Modified: trunk/src/mainboard/technexion/tim8690/fadt.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim8690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include #include #include -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/tyan/s2891/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2891/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/tyan/s2892/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2892/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/tyan/s2895/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2895/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include #include #include -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/via/epia-m700/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/epia-m700/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -33,7 +33,7 @@ #include #include #include -#include <../../../northbridge/via/vx800/vx800.h> +#include "../../../northbridge/via/vx800/vx800.h" extern const unsigned char AmlCode_dsdt[]; extern const unsigned char AmlCode_ssdt[]; Modified: trunk/src/mainboard/via/epia-m700/fadt.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/epia-m700/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -21,7 +21,7 @@ #include #include -#include <../../../northbridge/via/vx800/vx800.h> +#include "../../../northbridge/via/vx800/vx800.h" void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/pc2500e/mptable.c Mon Jul 26 23:45:11 2010 (r5668) @@ -27,7 +27,7 @@ #include #include #include -#include <../../../southbridge/via/vt8237r/vt8237r.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" #define bus_isa 2 Modified: trunk/src/northbridge/via/vx800/examples/chipset_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/chipset_init.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/northbridge/via/vx800/examples/chipset_init.c Mon Jul 26 23:45:11 2010 (r5668) @@ -21,7 +21,7 @@ #if CONFIG_HAVE_ACPI_RESUME == 1 #include #endif -#include <../northbridge/via/vx800/vx800.h> +#include "../vx800.h" #include #include "pci_rawops.h" From mylesgw at gmail.com Mon Jul 26 23:45:55 2010 From: mylesgw at gmail.com (Myles Watson) Date: Mon, 26 Jul 2010 15:45:55 -0600 Subject: [coreboot] Broken include paths In-Reply-To: <201007262207.21127.njacobs8@hetnet.nl> References: <201007262207.21127.njacobs8@hetnet.nl> Message-ID: >>include_path.diff: fix the ones that are broken for me. >>include_path2.diff: fix the ones that look identical but work anyway. >>include_path3.diff: fix <../path/file.h> to be "../../../path/file.h" >>to make it obvious that they're not in src/include >> >>Abuild tested. >> >>Signed-off-by: Myles Watson > > I like that. > > Acked-by: Nils Jacobs Rev 5668. Thanks, Myles From svn at coreboot.org Tue Jul 27 01:46:25 2010 From: svn at coreboot.org (repository service) Date: Tue, 27 Jul 2010 01:46:25 +0200 Subject: [coreboot] [commit] r5669 - in trunk/src: cpu/amd/model_gx2 include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/olpc/btest mainboard/olpc/rev_a mainboard/wyse/s50 northbridge/amd/gx2 s... Message-ID: Author: linux_junkie Date: Tue Jul 27 01:46:25 2010 New Revision: 5669 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5669 Log: This patch converts the Geode GX2 boards to CAR. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith Modified: trunk/src/cpu/amd/model_gx2/Kconfig trunk/src/cpu/amd/model_gx2/Makefile.inc trunk/src/cpu/amd/model_gx2/cpureginit.c trunk/src/cpu/amd/model_gx2/syspreinit.c trunk/src/include/cpu/amd/gx2def.h trunk/src/mainboard/amd/rumba/Kconfig trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/lippert/frontrunner/Kconfig trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/olpc/btest/Kconfig trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/Kconfig trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/amd/gx2/pll_reset.c trunk/src/northbridge/amd/gx2/raminit.c trunk/src/northbridge/amd/gx2/raminit.h trunk/src/southbridge/amd/cs5535/chipsetinit.c trunk/src/southbridge/amd/cs5535/cs5535.h trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Modified: trunk/src/cpu/amd/model_gx2/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_gx2/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -22,12 +22,12 @@ config DCACHE_RAM_BASE hex - default 0xc0000 + default 0xc8000 depends on CPU_AMD_GX2 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x04000 depends on CPU_AMD_GX2 config GEODE_VSA Modified: trunk/src/cpu/amd/model_gx2/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/model_gx2/Makefile.inc Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/Makefile.inc Tue Jul 27 01:46:25 2010 (r5669) @@ -2,5 +2,8 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm + driver-y += model_gx2_init.o obj-y += cpubug.o + +cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -1,81 +1,9 @@ - -/* ***************************************************************************/ -/* **/ -/* * BIST */ -/* **/ -/* * GX2 BISTs need to be run before BTB or caches are enabled.*/ -/* * BIST result left in registers on failure to be checked with FS2.*/ -/* **/ -/* ***************************************************************************/ -static void -BIST(void){ - int msrnum; - msr_t msr; - - /* DM*/ - msrnum = CPU_DM_CONFIG0; - msr = rdmsr(msrnum); - msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; - wrmsr(msrnum, msr); - - msr.lo = 0x00000003F; - msr.hi = 0x000000000; - msrnum = CPU_DM_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - msr.lo &= 0x0F3FF0000; - if (msr.lo != 0xfeff0000) - goto BISTFail; - - msrnum = CPU_DM_CONFIG0; - msr = rdmsr(msrnum); - msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET; - wrmsr(msrnum, msr); - - /* FPU*/ - msr.lo = 0x000000131; - msr.hi = 0; - msrnum = CPU_FP_UROM_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/ - inb(0x80); /* IO delay*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - while ((msr.lo&0x884) != 0x884) - msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/ - if ((msr.lo&0x642) != 0x642) - goto BISTFail; - - msr.lo = msr.hi = 0; /* clear FPU BIST bits*/ - msrnum = CPU_FP_UROM_BIST; - wrmsr(msrnum, msr); - - - /* BTB*/ - msr.lo = 0x000000303; - msr.hi = 0x000000000; - msrnum = CPU_PF_BTBRMA_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - if ((msr.lo & 0x3030) != 0x3030) - goto BISTFail; - - return; - -BISTFail: - print_err("BIST failed!\n"); - while(1); -} /* ***************************************************************************/ /* * cpuRegInit*/ /* ***************************************************************************/ -void -cpuRegInit (void){ +void cpuRegInit (void) +{ int msrnum; msr_t msr; /* Turn on BTM for early debug based on setup. */ @@ -197,16 +125,6 @@ msr.lo |= 0x08; wrmsr(msrnum, msr); - -/* */ -/* BIST*/ -/* */ - /*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/ - { -// BIST(); - } - - /* */ /* Enable BTB*/ /* */ @@ -260,45 +178,3 @@ } #endif } - - - - -/* ***************************************************************************/ -/* **/ -/* * MTestPinCheckBX*/ -/* **/ -/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/ -/* * This version is called when there isn't a stack available*/ -/* **/ -/* ***************************************************************************/ -static void -MTestPinCheckBX (void){ - int msrnum; - msr_t msr; - - /*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/ - /* return ; */ - /* } */ - - /* Turn on MTEST*/ - msrnum = MC_CFCLK_DBUG; - msr = rdmsr(msrnum); - msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET; - wrmsr(msrnum, msr); - - msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/; - msr = rdmsr(msrnum); - msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT; - if (msr.lo & 1) { - msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/ - msr = rdmsr(msrnum); - msr.lo |= CFCLK_LOWER_SDCLK_SET; - msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET; - wrmsr(msrnum, msr); - } - - /* Lock the cache down here.*/ - __asm__("wbinvd\n"); - -} Modified: trunk/src/cpu/amd/model_gx2/syspreinit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/syspreinit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/syspreinit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -7,17 +7,17 @@ /* * Destroys: Al,*/ /* **/ /* ***************************************************************************/ -static void -StartTimer1(void) +static void StartTimer1(void) { outb(0x56, 0x43); outb(0x12, 0x41); } -void -SystemPreInit(void) +void SystemPreInit(void) { /* they want a jump ... */ - __asm__("jmp .+2\ninvd\njmp.+2\n"); +#ifndef CONFIG_USE_DCACHE_RAM + __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); +#endif StartTimer1(); } Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/include/cpu/amd/gx2def.h Tue Jul 27 01:46:25 2010 (r5669) @@ -435,14 +435,15 @@ #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) -#define VIP_BIST (MSR_VIP + 0x2005) +#define VIP_BIST (MSR_VIP + 0x2005) +#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010) /* */ /* AES GLIU1 port 6*/ /* */ #define AES_GLD_MSR_CAP (MSR_AES + 0x2000) #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) #define AES_GLD_MSR_PM (MSR_AES + 0x2004) -#define AES_CONTROL (MSR_AES + 0x2006) +#define AES_CONTROL (MSR_AES + 0x2006) /* more fun stuff */ #define BM 1 /* Base Mask - map power of 2 size aligned region*/ #define BMO 2 /* BM with an offset*/ @@ -695,9 +696,10 @@ #if !defined(__ROMCC__) && !defined(ASSEMBLY) #if defined(__PRE_RAM__) -#else -void cpubug(void); +void cpuRegInit(void); +void SystemPreInit(void); #endif +void cpubug(void); #endif #endif /* CPU_AMD_GX2DEF_H */ Modified: trunk/src/mainboard/amd/rumba/Kconfig ============================================================================== --- trunk/src/mainboard/amd/rumba/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/amd/rumba/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -23,8 +23,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/amd/rumba/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include #include #include -#include #include #include #include "lib/ramtest.c" @@ -99,22 +98,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - /* total physical memory */ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - /* traditional memory 0kB-512kB, 512kB-1MB */ - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); +#include "cpu/amd/model_lx/msrinit.c" - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - - /* put code in northbridge[init].c here */ -} - -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -122,13 +108,15 @@ SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); cs5536_early_setup(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/lippert/frontrunner/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/lippert/frontrunner/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include #include #include -#include #include #include #include "lib/ramtest.c" @@ -10,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include "southbridge/amd/cs5535/cs5535.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -46,31 +46,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040); - __builtin_wrmsr(0x10000027, 0xfff00000, 0xff); - __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f); - __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000); - - __builtin_wrmsr(0x10000080, 0x3, 0x0); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); - __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef); - __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f); - __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000); - - __builtin_wrmsr(0x50002001, 0x27, 0x0); - __builtin_wrmsr(0x4c002001, 0x1, 0x0); -} +#include "cpu/amd/model_lx/msrinit.c" -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -85,6 +63,10 @@ cs5535_early_setup(); print_err("done cs5535 early\n"); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); print_err("done pll_reset\n"); Modified: trunk/src/mainboard/olpc/btest/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/btest/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/btest/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/btest/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include #include #include -#include #include #include #include "lib/ramtest.c" @@ -132,16 +131,7 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); -} +#include "cpu/amd/model_lx/msrinit.c" static void gpio_init(void) { @@ -155,7 +145,7 @@ outl(m, GPIOL_EVENTS_ENABLE); } -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -175,6 +165,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/olpc/rev_a/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/rev_a/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/rev_a/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include #include #include -#include #include #include #include "lib/ramtest.c" @@ -132,16 +131,7 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); -} +#include "cpu/amd/model_lx/msrinit.c" static void gpio_init(void) { @@ -155,7 +145,7 @@ outl(m, GPIOL_EVENTS_ENABLE); } -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -175,6 +165,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/s50/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/wyse/s50/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -23,8 +23,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/wyse/s50/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include "lib/ramtest.c" @@ -122,32 +121,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" +#include "cpu/amd/model_lx/msrinit.c" -static void msr_init(void) -{ - /* Setup access to cache under 1MB. - __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect. - * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Serialize, Cache Disable. - * SysTop: 0x000A0 - * System Memory Properties: (Write Back) */ - - __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */ - __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */ - __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */ - - /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ - __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ - __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ - __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ - __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ - __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ - __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ - - /* put code in northbridge[init].c here */ -} - -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -166,6 +142,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/northbridge/amd/gx2/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/gx2/pll_reset.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/pll_reset.c Tue Jul 27 01:46:25 2010 (r5669) @@ -4,6 +4,7 @@ #define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ #define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#if 0 static unsigned int calibrate_tsc(void) { /* Set the Gate high, disable speaker */ @@ -64,6 +65,7 @@ print_err("bad_ctc\n"); return 0; } +#endif /* spll_raw_clk = SYSREF * FbDIV, * GLIU Clock = spll_raw_clk / MDIV Modified: trunk/src/northbridge/amd/gx2/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/raminit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -102,17 +102,14 @@ msr.lo = 0x8ea0ad6a; wrmsr(0x4c00000f, msr); - /* Fixes from Jordan Crouse of AMD. */ - - /* make sure there is nothing stale in the cache */ - __asm__("wbinvd\n"); - - print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ + /* Note: The descriptor needs to be enabled to point at memory */ volatile unsigned long *ptr; - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } + print_info("RAM DLL lock\n"); + } Modified: trunk/src/northbridge/amd/gx2/raminit.h ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/raminit.h Tue Jul 27 01:46:25 2010 (r5669) @@ -7,4 +7,6 @@ uint16_t channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif /* RAMINIT_H */ Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -13,8 +13,6 @@ #include #include #include "southbridge/amd/cs5535/cs5535.h" -// This code uses some cs5536 includes because cs5535 includes are empty: -#include "southbridge/amd/cs5536/cs5536.h" /* the structs in this file only set msr.lo. But ... that may not always be true */ Modified: trunk/src/southbridge/amd/cs5535/cs5535.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535.h Tue Jul 27 01:46:25 2010 (r5669) @@ -1,4 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #ifndef _CS5535_H #define _CS5535_H +/* SouthBridge Equates */ +#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ +#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ +#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */ +#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */ + +#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */ +#define SMBUS_IO_BASE 0x6000 +#define GPIO_IO_BASE 0x6100 +#define MFGPT_IO_BASE 0x6200 +#define ACPI_IO_BASE 0x9C00 +#define PMS_IO_BASE 0x9D00 + +/* Cs5536 as follows. */ +/* SB_GLIU */ +/* port0 - GLIU */ +/* port1 - GLPCI */ +/* port2 - USB Controller #2 */ +/* port3 - ATA-5 Controller */ +/* port4 - MDD */ +/* port5 - AC97 */ +/* port6 - USB Controller #1 */ +/* port7 - GLCP */ + +#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ +#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ +#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ +#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ +#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ +#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ +#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ +#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ + +/* GLIU */ +#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04) + +/* USB1 */ +#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01) +#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04) + +/* USB2 */ +#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01) +#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04) + +/* ATA */ +#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01) +#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03) +#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04) + +/* AC97 */ +#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01) +#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04) + +/* GLPCI */ +#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04) +#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10) +#define GLPCI_CRTL_PPIDE_SET (1 << 17) + +/* GLCP */ +#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04) + +/* MDD */ +#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01) +#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04) +#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B) +#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C) +#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D) +#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E) +#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F) +#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010) +#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011) +#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012) +#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013) +#define MDD_PIN_OPT (MSR_SB_MDD + 0x015) +#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018) + +/* GPIO */ +#define GPIOL_2_SET (1 << 2) + +/* GPIO LOW Bank Bit Registers */ +#define GPIOL_INPUT_ENABLE (0x20) +#define GPIOL_IN_AUX1_SELECT (0x34) + +/* FLASH device macros */ +#define FLASH_TYPE_NONE 0 /* No flash device installed */ +#define FLASH_TYPE_NAND 1 /* NAND device */ + +#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ + +/* Flash Memory Mask values */ +#define FLASH_MEM_4K 0xFFFFF000 + +#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) +void cs5535_disable_internal_uart(void); +#else +void chipsetinit(void); #endif +#endif + +#endif /* _CS5535_H */ Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Tue Jul 27 01:46:25 2010 (r5669) @@ -8,9 +8,6 @@ * */ -#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */ -#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */ - /** * @brief Setup PCI IDSEL for CS5535 * @@ -51,46 +48,33 @@ } } -static int cs5535_setup_iobase(void) +static void cs5535_setup_iobase(void) { msr_t msr; - /* setup LBAR for SMBus controller */ - __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001); + msr.hi = 0x0000f001; + msr.lo = SMBUS_IO_BASE; + wrmsr(MDD_LBAR_SMB, msr); + /* setup LBAR for GPIO */ - __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001); + msr.hi = 0x0000f001; + msr.lo = GPIO_IO_BASE; + wrmsr(MDD_LBAR_GPIO, msr); + /* setup LBAR for MFGPT */ - __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001); - /* setup LBAR for ACPI */ - __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001); - /* setup LBAR for PM Support */ - __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001); -} + msr.hi = 0x0000f001; + msr.lo = MFGPT_IO_BASE; + wrmsr(MDD_LBAR_MFGPT, msr); -static void cs5535_setup_power_bottun(void) -{ - /* not implemented yet */ -#if 0 - pwrBtn_setup: - ; - ; Power Button Setup - ; - ;mov eax, 0C0020000h ; 4 seconds + lock - mov eax, 040020000h ; 4 seconds no lock - mov dx, PMLogic_BASE + 40h - out dx, eax - - ; setup GPIO24, it is the external signal for 5535 vsb_work_aux - ; which controls all voltage rails except Vstandby & Vmem. - ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - ; If GPIO24 is not enabled then soft-off will not work. - mov dx, GPIOH_OUT_AUX1_SELECT - mov eax, GPIOH_24_SET - out dx, eax - mov dx, GPIOH_OUTPUT_ENABLE - out dx, eax + /* setup LBAR for ACPI */ + msr.hi = 0x0000f001; + msr.lo = ACPI_IO_BASE; + wrmsr(MDD_LBAR_ACPI, msr); -#endif + /* setup LBAR for PM Support */ + msr.hi = 0x0000f001; + msr.lo = PMS_IO_BASE; + wrmsr(MDD_LBAR_PMS, msr); } static void cs5535_setup_gpio(void) @@ -115,27 +99,8 @@ //outl(val, 0x6100 + 0x34); } -static void cs5535_disable_internal_uart(void) +void cs5535_disable_internal_uart(void) { - /* not implemented yet */ -#if 0 - ; The UARTs default to enabled. - ; Disable and reset them and configure them later. (SIO init) - mov ecx, MDD_UART1_CONF - RDMSR - mov eax, 1h ; reset - WRMSR - mov eax, 0h ; disabled - WRMSR - - mov ecx, MDD_UART2_CONF - RDMSR - mov eax, 1h ; reset - WRMSR - mov eax, 0h ; disabled - WRMSR - -#endif } static void cs5535_setup_cis_mode(void) @@ -143,19 +108,21 @@ msr_t msr; /* setup CPU interface serial to mode C on both sides */ - msr = __builtin_rdmsr(0x51000010); + msr = rdmsr(GLPCI_SB_CTRL); msr.lo &= ~0x18; msr.lo |= 0x10; - __builtin_wrmsr(0x51000010, msr.lo, msr.hi); + wrmsr(GLPCI_SB_CTRL, msr); //Only do this if we are building for 5535 - __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000); + msr.lo = 0x2; + msr.hi = 0x0; + wrmsr(VIP_GIO_MSR_SEL, msr); } static void dummy(void) { } -static int cs5535_early_setup(void) +static void cs5535_early_setup(void) { msr_t msr; Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c Tue Jul 27 01:46:25 2010 (r5669) @@ -3,7 +3,7 @@ #define SMBUS_IO_BASE 0x6000 /* initialization for SMBus Controller */ -static int cs5535_enable_smbus(void) +static void cs5535_enable_smbus(void) { unsigned char val; @@ -20,26 +20,3 @@ val |= (0xEF | SMB_ADD_SAEN); outb(val, SMBUS_IO_BASE + SMB_ADD); } - -static int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1); -} - -#if 0 -static int smbus_recv_byte(unsigned device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static int smbus_send_byte(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - - -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} -#endif Modified: trunk/src/southbridge/amd/cs5535/cs5535_smbus.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Tue Jul 27 01:46:25 2010 (r5669) @@ -44,137 +44,3 @@ #define SMBUS_STATUS_MASK 0xfbff #define SMBUS_IO_BASE 0x6000 - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -/* generate a smbus start condition */ -static int smbus_start_condition(unsigned smbus_io_base) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* issue a START condition */ - val = inb(smbus_io_base + SMB_CTRL1); - outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1); - - /* check for bus conflict */ - val = inb(smbus_io_base + SMB_STS); - if ((val & SMB_STS_BER) != 0) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_check_stop_condition(unsigned smbus_io_base) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_CTRL1); - if ((val & SMB_CTRL1_STOP) == 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_stop_condition(unsigned smbus_io_base) -{ - unsigned char val; - val = inb(smbus_io_base + SMB_CTRL1); - outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1); -} - -static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* send the slave address */ - outb(device, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_send_command(unsigned smbus_io_base, unsigned char command) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* send the command */ - outb(command, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) -{ - unsigned char val, val1; - - smbus_check_stop_condition(smbus_io_base); - - smbus_start_condition(smbus_io_base); - - smbus_send_slave_address(smbus_io_base, device); - - smbus_send_command(smbus_io_base, address); - - smbus_start_condition(smbus_io_base); - - smbus_send_slave_address(smbus_io_base, device | 0x01); - - /* send NACK to slave */ - val = inb(smbus_io_base + SMB_CTRL1); - outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); - - val = inb(smbus_io_base + SMB_SDA); - - //smbus_stop_condition(smbus_io_base); - - return val; -} From joe at settoplinux.org Tue Jul 27 01:47:43 2010 From: joe at settoplinux.org (Joseph Smith) Date: Mon, 26 Jul 2010 19:47:43 -0400 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR In-Reply-To: <201007212320.54287.njacobs8@hetnet.nl> References: <201007212320.54287.njacobs8@hetnet.nl> Message-ID: <4C4E1E9F.3030402@settoplinux.org> On 07/21/2010 05:20 PM, Nils wrote: > This patch converts the Geode GX2 boards to CAR. > It reduces the boot time with ~35 seconds in "Stage: loading > fallback/coreboot_ram". > After the conversion GCC gave a lot of build warnings in the old ROMCC code > (especially in the southbridge CS5535 code used by the Lippert Frontrunner > board) which i had to fix. > It is ABUILD tested and boot tested on my Wyse S50. > > Signed-off-by: Nils Jacobs > Acked-by: Joseph Smith > > V2: Add newline at end of file src/cpu/amd/model_gx2/Makefile.inc.(thanks to > Peter for spotting this) > Remove unused code in src/southbridge/amd/cs5535/ . > Thanks Nils, r5669. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From svn at coreboot.org Tue Jul 27 02:00:27 2010 From: svn at coreboot.org (repository service) Date: Tue, 27 Jul 2010 02:00:27 +0200 Subject: [coreboot] build service results for r5669 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "linux_junkie" checked in revision 5669 to the coreboot repository. This caused the following changes: Change Log: This patch converts the Geode GX2 boards to CAR. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith Build Log: Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=rumba&vendor=amd&num=2 Compilation of lippert:frontrunner has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=frontrunner&vendor=lippert&num=2 Compilation of olpc:btest has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=btest&vendor=olpc&num=2 Compilation of olpc:rev_a has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=rev_a&vendor=olpc&num=2 Compilation of wyse:s50 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=s50&vendor=wyse&num=2 If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From caibaiyin.pku at gmail.com Tue Jul 27 01:33:43 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Tue, 27 Jul 2010 07:33:43 +0800 Subject: [coreboot] xcompile patch for libpayload Message-ID: hi all, since the xcompile file is generated for different compiler, i think it should be included under the PHONY distclean, am i right? Signed-off-by Cai Bai Yin -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: xcompile.patch Type: text/x-patch Size: 471 bytes Desc: not available URL: From svn at coreboot.org Tue Jul 27 02:30:42 2010 From: svn at coreboot.org (repository service) Date: Tue, 27 Jul 2010 02:30:42 +0200 Subject: [coreboot] [commit] r5670 - trunk/src/cpu/amd/model_gx2 Message-ID: Author: stuge Date: Tue Jul 27 02:30:42 2010 New Revision: 5670 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5670 Log: Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669 Part of converting GX2 to use CAR. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith Acked-by: Peter Stuge Added: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Added: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Tue Jul 27 02:30:42 2010 (r5670) @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) + +#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */ +#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ +#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ +#include +/*************************************************************************** +/** +/** DCacheSetup +/** +/** Setup data cache for use as RAM for a stack. +/** +/** Max. size data cache =0x4000 (16KB) +/** +/***************************************************************************/ +DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx + + invd + /* set cache properties */ + movl $CPU_RCONF_DEFAULT, %ecx + rdmsr + movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ + wrmsr + + /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */ + movl $CPU_DM_CONFIG0, %ecx + rdmsr + andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ + wrmsr + + /* Get cleaned up. */ + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* remember, there is NO stack yet... */ + + /* Tell cache we want to fill WAY 0 starting at the top */ + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_INDEX, %ecx + wrmsr + + /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ + movl $GX2_STACK_BASE, %ebp /* init to start address */ + orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ + + /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ + movl $GX2_NUM_CACHELINES, %edi +DCacheSetupFillWay: + + /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ + /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ + movw $0x04, %si + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_DATA, %ecx +DCacheSetup_quadWordLoop: + wrmsr + decw %si + jnz DCacheSetup_quadWordLoop + + /* Set the tag for this line,need to do this for every new cache line to validate it! */ + /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ + xorl %edx, %edx + movl %ebp, %eax + movl $CPU_DC_TAG, %ecx + wrmsr + + /* switch to next line */ + /* lines are in Bits8:2 */ + /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */ + wrmsr + + decl %edi + jnz DCacheSetupFillWay + + /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ + addl $GX2_CACHEWAY_SIZE, %ebp + cmpl $GX2_STACK_END, %ebp + jge leave_DCacheSetup + movl $GX2_NUM_CACHELINES, %edi + + /* switch to next way */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x01, %eax + andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */ + wrmsr + + jmp DCacheSetupFillWay + +leave_DCacheSetup: + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ + /* Memory reads and writes will all hit in the cache. */ + /* Cache updates and memory write-backs will not occur ! */ + movl %cr0, %eax + orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ + movl %eax, %cr0 + + /* Now point sp to the cached stack. */ + /* The stack will be fully functional at this location. No system memory is required at all ! */ + /* set up the stack pointer */ + movl $GX2_STACK_END, %eax + movl %eax, %esp + + /* test the stack*/ + movl $0x0F0F05A5A, %edx + pushl %edx + popl %ecx + cmpl %ecx, %edx + je DCacheSetupGood + + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad +DCacheSetupGood: + /* Go do early init and memory setup */ + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main +done_cache_as_ram_main: + + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi + + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) /* post 11 */ + + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP + */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) /* post fail ee */ + hlt + jmp .Lhlt + From peter at stuge.se Tue Jul 27 02:31:26 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 27 Jul 2010 02:31:26 +0200 Subject: [coreboot] build service results for r5669 In-Reply-To: References: Message-ID: <20100727003126.15371.qmail@stuge.se> repository service wrote: > Compilation of amd:rumba has been broken > Compilation of lippert:frontrunner has been broken > Compilation of olpc:btest has been broken > Compilation of olpc:rev_a has been broken > Compilation of wyse:s50 has been broken It seems that src/cpu/amd/model_gx2/cache_as_ram.inc wasn't added, I just committed it in r5670. //Peter From peter at stuge.se Tue Jul 27 02:35:59 2010 From: peter at stuge.se (Peter Stuge) Date: Tue, 27 Jul 2010 02:35:59 +0200 Subject: [coreboot] xcompile patch for libpayload In-Reply-To: References: Message-ID: <20100727003559.16067.qmail@stuge.se> baiyin cai wrote: > hi all, > since the xcompile file is generated for different compiler, i think it > should be included under the PHONY distclean, am i right? I think that makes good sense, but I hope to hear also from more people. > Signed-off-by Cai Bai Yin Acked-by: Peter Stuge If there's no disagreement I can commit a little later. //Peter From corey.osgood at gmail.com Tue Jul 27 02:37:27 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Mon, 26 Jul 2010 17:37:27 -0700 Subject: [coreboot] #167: Support for new ION2 (Intel NM10 chipset) In-Reply-To: References: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> Message-ID: For some reason I can't update the ticket, it keeps giving me a reCAPTCHA error but I don't see a recaptcha box. Anyways, here's a link to the board I'm working on: http://www.zotacusa.com/zotac-nm10-b-e-atom-d510-1-66-ghz-dual-core-mini-itx-wifi-intel-motherboard-283.html The package I bought (from Newegg) has the built-in NM-10 video onboard, and also includes a PCI-E 1x ION graphics card. I will try to get both working. On Wed, Jul 21, 2010 at 4:38 AM, Corey Osgood wrote: > This is my current project, Intel Atom D410/510 cpu and NM10 > southbridge support. There's 2 different IONs, one is a full chipset, > the other is just a graphics chip. Supporting the graphics chip/card > isn't very difficult, just load the vendor bios, it's the chipset that > we can't do without any docs. > > niklas, do you own the Asus board you linked to? > > -Corey > > On Wed, Jul 21, 2010 at 5:18 AM, Anders Jenbo wrote: >> It looks to m? like it is only a grafic card ?n that board. If that is the >> case then yes you should be able to port the board to corboot using the >> intel docs. But you will still need the nvidia x.org driver in the end. >> >> Mvh Anders >> >> Den 21/07/2010 kl. 08.52 skrev "coreboot" : >> >>> #167: Support for new ION2 (Intel NM10 chipset) >>> >>> --------------------------------------+------------------------------------- >>> ? Reporter: ?niklas.lonn@? ? ? ? ? ?| ? ? ? ? ?Owner: ?stepan@? >>> ? ? ? Type: ?defect ? ? ? ? ? ? ? ? | ? ? ? ? Status: ?new >>> ? Priority: ?major ? ? ? ? ? ? ? ? ?| ? ? ?Milestone: >>> ?Component: ?coreboot ? ? ? ? ? ? ? | ? ? ? Keywords: >>> ?NM10,ION2,Intel,Asus >>> Dependencies: ? ? ? ? ? ? ? ? ? ? ? ? | ? Patch Status: ?there is no patch >>> >>> --------------------------------------+------------------------------------- >>> I have read that the ION platform is not supported because nVidia doesn't >>> release the datasheets in public, however, a new ION2 platform is >>> availabl, having an Intel NM10 north/south-bridge combo with open datashet >>> at: >>> >>> http://www.intel.com/products/Internet_Device/Chipsets/NM10/NM10-technicaldocuments.htm >>> >>> The motherboard of my interest is this one (Probably many others too): >>> http://www.asus.com/product.aspx?P_ID=iIZKMXSj0jZKiebE&templete=2 >>> >>> -- >>> Ticket URL: >>> coreboot >>> >>> -- >>> coreboot mailing list: coreboot at coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > From svn at coreboot.org Tue Jul 27 02:44:50 2010 From: svn at coreboot.org (repository service) Date: Tue, 27 Jul 2010 02:44:50 +0200 Subject: [coreboot] build service results for r5670 Message-ID: Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 5670 to the coreboot repository. This caused the following changes: Change Log: Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669 Part of converting GX2 to use CAR. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith Acked-by: Peter Stuge Build Log: Compilation of amd:rumba has been fixed Compilation of lippert:frontrunner has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of wyse:s50 has been fixed If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system From wangqingpei at gmail.com Tue Jul 27 10:20:22 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 27 Jul 2010 16:20:22 +0800 Subject: [coreboot] Gigabyte SuperIO problems Message-ID: hi all, since it's old topic, but i would like to arise this again. I am trying to port coreboot to two gigabyte mainboard. both of them have the same superIO ITE8718, one of the board is GA-MA78GM-UD2H . it is an 780+700+DDR2 mainboard, which is much similar with AMD Mahogany. The confusing things now is after the ITE8718 init, it continues reboot. This caused me thinking about the difference of ITE8718 between MA78GM and mahogany. Gigabyte may did some special hardware(or register)configuration to ITE8718. Is there any one who tried to port coreboot to Gigabyte dual bios mainboards? Vadim: I found your mail in flashrom mail list, it seems that you had the experience about the gigabyte dual bios things. Have you have any suggestion about my problems? -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From Zheng.Bao at amd.com Tue Jul 27 11:01:35 2010 From: Zheng.Bao at amd.com (Bao, Zheng) Date: Tue, 27 Jul 2010 17:01:35 +0800 Subject: [coreboot] Gigabyte SuperIO problems In-Reply-To: References: Message-ID: I noticed that ite871x has watchdog. You can try to kill the watchdog like the what it8712 does. Zheng ________________________________ From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Qing Pei Wang Sent: Tuesday, July 27, 2010 4:20 PM To: Coreboot; vadimgirlin at gmail.com; Marc Jones Subject: [coreboot] Gigabyte SuperIO problems hi all, since it's old topic, but i would like to arise this again. I am trying to port coreboot to two gigabyte mainboard. both of them have the same superIO ITE8718, one of the board is GA-MA78GM-UD2H . it is an 780+700+DDR2 mainboard, which is much similar with AMD Mahogany. The confusing things now is after the ITE8718 init, it continues reboot. This caused me thinking about the difference of ITE8718 between MA78GM and mahogany. Gigabyte may did some special hardware(or register)configuration to ITE8718. Is there any one who tried to port coreboot to Gigabyte dual bios mainboards? Vadim: I found your mail in flashrom mail list, it seems that you had the experience about the gigabyte dual bios things. Have you have any suggestion about my problems? -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From joe at settoplinux.org Tue Jul 27 15:06:48 2010 From: joe at settoplinux.org (Joseph Smith) Date: Tue, 27 Jul 2010 09:06:48 -0400 Subject: [coreboot] #167: Support for new ION2 (Intel NM10 chipset) In-Reply-To: References: <057.376a9e18964294ac84a6d7db3bb28174@coreboot.org> Message-ID: <309e88f2f3fd320e97d5db131bd3c078@imap.1and1.com> On Mon, 26 Jul 2010 17:37:27 -0700, Corey Osgood wrote: > Anyways, here's a > link to the board I'm working on: > > http://www.zotacusa.com/zotac-nm10-b-e-atom-d510-1-66-ghz-dual-core-mini-itx-wifi-intel-motherboard-283.html > > The package I bought (from Newegg) has the built-in NM-10 video > onboard, and also includes a PCI-E 1x ION graphics card. I will try to > get both working. > Sweet! Good Luck Corey :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From wangqingpei at gmail.com Tue Jul 27 15:11:43 2010 From: wangqingpei at gmail.com (Qing Pei Wang) Date: Tue, 27 Jul 2010 21:11:43 +0800 Subject: [coreboot] xcompile patch for libpayload In-Reply-To: <20100727003559.16067.qmail@stuge.se> References: <20100727003559.16067.qmail@stuge.se> Message-ID: i agree it seems pretty good... On Tue, Jul 27, 2010 at 8:35 AM, Peter Stuge wrote: > baiyin cai wrote: > > hi all, > > since the xcompile file is generated for different compiler, i think > it > > should be included under the PHONY distclean, am i right? > > I think that makes good sense, but I hope to hear also from more > people. > > > > Signed-off-by Cai Bai Yin > > Acked-by: Peter Stuge > > If there's no disagreement I can commit a little later. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- Wang Qing Pei Phone: 86+13426369984 -------------- next part -------------- An HTML attachment was scrubbed... URL: From njacobs8 at hetnet.nl Tue Jul 27 22:05:52 2010 From: njacobs8 at hetnet.nl (Nils) Date: Tue, 27 Jul 2010 22:05:52 +0200 Subject: [coreboot] [PATCH] Convert Geode GX2 boards to CAR Message-ID: <201007272205.52614.njacobs8@hetnet.nl> Hi Joseph and Peter, Thanks for commiting my patch. Now i can dig up the next patch. Thanks,Nils. From njacobs8 at hetnet.nl Wed Jul 28 01:15:19 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 28 Jul 2010 01:15:19 +0200 Subject: [coreboot] [PATCH] Geode GX2 post code patch Message-ID: <201007280115.19769.njacobs8@hetnet.nl> This patch lets Geode GX2 use geode_post_code.h just like LX and cleans up gx2def.h and geode_post_code.h a little. It is abuild tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs Acked-by: Nils Jacobs (trivial) As this is a trivial patch and i didn`t wanted to put a burden on the already overloaded review team i acked it myself. Now i "just" need somebody with SVN access to commit it. ;) Thanks,Nils. -------------- next part -------------- A non-text attachment was scrubbed... Name: 5670_post_code.patch Type: text/x-patch Size: 20205 bytes Desc: not available URL: From svn at coreboot.org Wed Jul 28 02:27:09 2010 From: svn at coreboot.org (repository service) Date: Wed, 28 Jul 2010 02:27:09 +0200 Subject: [coreboot] [commit] r5671 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/olpc/btest mainboard/olpc/rev_a mainboard/wyse/s50 southbridge/amd/cs5535 Message-ID: Author: stuge Date: Wed Jul 28 02:27:09 2010 New Revision: 5671 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5671 Log: Let Geode GX2 use geode_post_code.h just like Geode LX Also clean up gx2def.h and geode_post_code.h a little. abuild tested and boot tested on a Wyse S50. Signed-off-by: Nils Jacobs Acked-by: Nils Jacobs Acked-by: Peter Stuge Modified: trunk/src/include/cpu/amd/geode_post_code.h trunk/src/include/cpu/amd/gx2def.h trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/southbridge/amd/cs5535/chipsetinit.c Modified: trunk/src/include/cpu/amd/geode_post_code.h ============================================================================== --- trunk/src/include/cpu/amd/geode_post_code.h Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/include/cpu/amd/geode_post_code.h Wed Jul 28 02:27:09 2010 (r5671) @@ -18,77 +18,70 @@ */ /* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ +#define POST_Output_Port (0x080) /* port to write post codes to*/ -#define POST_preSioInit (0x000) -#define POST_clockInit (0x001) -#define POST_CPURegInit (0x002) -#define POST_UNREAL (0x003) -#define POST_CPUMemRegInit (0x004) -#define POST_CPUTest (0x005) -#define POST_memSetup (0x006) -#define POST_memSetUpStack (0x007) -#define POST_memTest (0x008) -#define POST_shadowRom (0x009) -#define POST_memRAMoptimize (0x00A) -#define POST_cacheInit (0x00B) +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) #define POST_northBridgeInit (0x00C) -#define POST_chipsetInit (0x00D) -#define POST_sioTest (0x00E) -#define POST_pcATjunk (0x00F) - - -#define POST_intTable (0x010) -#define POST_memInfo (0x011) -#define POST_romCopy (0x012) -#define POST_PLLCheck (0x013) -#define POST_keyboardInit (0x014) -#define POST_cpuCacheOff (0x015) -#define POST_BDAInit (0x016) -#define POST_pciScan (0x017) -#define POST_optionRomInit (0x018) -#define POST_ResetLimits (0x019) -#define POST_summary_screen (0x01A) -#define POST_Boot (0x01B) -#define POST_SystemPreInit (0x01C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) + +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) #define POST_ClearRebootFlag (0x01D) -#define POST_GLIUInit (0x01E) -#define POST_BootFailed (0x01F) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) - -#define POST_CPU_ID (0x020) -#define POST_COUNTERBROKEN (0x021) -#define POST_DIFF_DIMMS (0x022) +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) #define POST_WIGGLE_MEM_LINES (0x023) -#define POST_NO_GLIU_DESC (0x024) -#define POST_CPU_LCD_CHECK (0x025) -#define POST_CPU_LCD_PASS (0x026) -#define POST_CPU_LCD_FAIL (0x027) -#define POST_CPU_STEPPING (0x028) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) #define POST_CPU_DM_BIST_FAILURE (0x029) -#define POST_CPU_FLAGS (0x02A) -#define POST_CHIPSET_ID (0x02b) -#define POST_CHIPSET_ID_PASS (0x02c) -#define POST_CHIPSET_ID_FAIL (0x02d) -#define POST_CPU_ID_GOOD (0x02E) -#define POST_CPU_ID_FAIL (0x02F) - - +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02B) +#define POST_CHIPSET_ID_PASS (0x02C) +#define POST_CHIPSET_ID_FAIL (0x02D) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) /* PCI config*/ -#define P80_PCICFG (0x030) - +#define P80_PCICFG (0x030) /* PCI io*/ -#define P80_PCIIO (0x040) - +#define P80_PCIIO (0x040) /* PCI memory*/ -#define P80_PCIMEM (0x050) - +#define P80_PCIMEM (0x050) /* SIO*/ -#define P80_SIO (0x060) +#define P80_SIO (0x060) /* Memory Setp*/ #define P80_MEM_SETUP (0x070) @@ -102,32 +95,30 @@ #define ERROR_NO_DIMMS (0x077) #define ERROR_DIFF_DIMMS (0x078) #define ERROR_BAD_LATENCY (0x079) -#define ERROR_SET_PAGE (0x07a) -#define ERROR_DENSITY_DIMM (0x07b) -#define ERROR_UNSUPPORTED_DIMM (0x07c) -#define ERROR_BANK_SET (0x07d) +#define ERROR_SET_PAGE (0x07A) +#define ERROR_DENSITY_DIMM (0x07B) +#define ERROR_UNSUPPORTED_DIMM (0x07C) +#define ERROR_BANK_SET (0x07D) #define POST_MEM_SETUP_GOOD (0x07E) #define POST_MEM_SETUP_FAIL (0x07F) - -#define POST_UserPreInit (0x080) -#define POST_UserPostInit (0x081) +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) #define POST_Equipment_check (0x082) -#define POST_InitNVRAMBX (0x083) -#define POST_NoPIRTable (0x084) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) #define POST_ChipsetFingerPrintPass (0x085) #define POST_ChipsetFingerPrintFail (0x086) -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) #define POST_CPU_FPU_BIST_FAILURE (0x089) -#define POST_CPU_BTB_BIST_FAILURE (0x08a) -#define POST_CPU_EX_BIST_FAILURE (0x08b) -#define POST_Chipset_PI_Test_Fail (0x08c) -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) -#define POST_BIT_CLK_Fail (0x08e) +#define POST_CPU_BTB_BIST_FAILURE (0x08A) +#define POST_CPU_EX_BIST_FAILURE (0x08B) +#define POST_Chipset_PI_Test_Fail (0x08C) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) +#define POST_BIT_CLK_Fail (0x08E) - -#define POST_STACK_SETUP (0x090) +#define POST_STACK_SETUP (0x090) #define POST_CPU_PF_BIST_FAILURE (0x091) #define POST_CPU_L2_BIST_FAILURE (0x092) #define POST_CPU_GLCP_BIST_FAILURE (0x093) @@ -137,61 +128,55 @@ #define POST_STACK_SETUP_PASS (0x09E) #define POST_STACK_SETUP_FAIL (0x09F) - -#define POST_PLL_INIT (0x0A0) -#define POST_PLL_MANUAL (0x0A1) -#define POST_PLL_STRAP (0x0A2) -#define POST_PLL_RESET_FAIL (0x0A3) -#define POST_PLL_PCI_FAIL (0x0A4) -#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) #define POST_PLL_CPU_VER_FAIL (0x0A6) - #define POST_MEM_TESTMEM (0x0B0) #define POST_MEM_TESTMEM1 (0x0B1) #define POST_MEM_TESTMEM2 (0x0B2) #define POST_MEM_TESTMEM3 (0x0B3) #define POST_MEM_TESTMEM4 (0x0B4) -#define POST_MEM_TESTMEM_PASS (0x0BE) -#define POST_MEM_TESTMEM_FAIL (0x0BF) - +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) #define POST_SECUROM_SECBOOT_START (0x0C0) #define POST_SECUROM_BOOTSRCSETUP (0x0C1) #define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) #define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) #define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) #define POST_SECUROM_PLATFORMSETUP (0x0C9) #define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL (0x0CD) - -#define POST_RCONFInitError (0x0CE) -#define POST_CacheInitError (0x0CF) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) #define POST_ROM_PREUNCOMPRESS (0x0D0) -#define POST_ROM_UNCOMPRESS (0x0D1) -#define POST_ROM_SMM_INIT (0x0D2) -#define POST_ROM_VID_BIOS (0x0D3) -#define POST_ROM_LCDINIT (0x0D4) -#define POST_ROM_SPLASH (0x0D5) -#define POST_ROM_HDDINIT (0x0D6) -#define POST_ROM_SYS_INIT (0x0D7) -#define POST_ROM_DMM_INIT (0x0D8) -#define POST_ROM_TVINIT (0x0D9) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) #define POST_ROM_POSTUNCOMPRESS (0x0DE) - -#define P80_CHIPSET_INIT (0x0E0) -#define POST_PreChipsetInit (0x0E1) +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) #define POST_LateChipsetInit (0x0E2) -#define POST_NORTHB_INIT (0x0E8) - +#define POST_NORTHB_INIT (0x0E8) -#define POST_INTR_SEG_JUMP (0x0F0) +#define POST_INTR_SEG_JUMP (0x0F0) Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/include/cpu/amd/gx2def.h Wed Jul 28 02:27:09 2010 (r5671) @@ -503,187 +503,6 @@ #define CHIPSET_DEV_NUM 15 #define IDSEL_BASE 11 // bit 11 = device 1 - -/* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ - -#define POST_preSioInit (0x000) /* geode.asm*/ -#define POST_clockInit (0x001) /* geode.asm*/ -#define POST_CPURegInit (0x002) /* geode.asm*/ -#define POST_UNREAL (0x003) /* geode.asm*/ -#define POST_CPUMemRegInit (0x004) /* geode.asm*/ -#define POST_CPUTest (0x005) /* geode.asm*/ -#define POST_memSetup (0x006) /* geode.asm*/ -#define POST_memSetUpStack (0x007) /* geode.asm*/ -#define POST_memTest (0x008) /* geode.asm*/ -#define POST_shadowRom (0x009) /* geode.asm*/ -#define POST_memRAMoptimize (0x00A) /* geode.asm*/ -#define POST_cacheInit (0x00B) /* geode.asm*/ -#define POST_northBridgeInit (0x00C) /* geode.asm*/ -#define POST_chipsetInit (0x00D) /* geode.asm*/ -#define POST_sioTest (0x00E) /* geode.asm*/ -#define POST_pcATjunk (0x00F) /* geode.asm*/ - - -#define POST_intTable (0x010) /* geode.asm*/ -#define POST_memInfo (0x011) /* geode.asm*/ -#define POST_romCopy (0x012) /* geode.asm*/ -#define POST_PLLCheck (0x013) /* geode.asm*/ -#define POST_keyboardInit (0x014) /* geode.asm*/ -#define POST_cpuCacheOff (0x015) /* geode.asm*/ -#define POST_BDAInit (0x016) /* geode.asm*/ -#define POST_pciScan (0x017) /* geode.asm*/ -#define POST_optionRomInit (0x018) /* geode.asm*/ -#define POST_ResetLimits (0x019) /* geode.asm*/ -#define POST_summary_screen (0x01A) /* geode.asm*/ -#define POST_Boot (0x01B) /* geode.asm*/ -#define POST_SystemPreInit (0x01C) /* geode.asm*/ -#define POST_ClearRebootFlag (0x01D) /* geode.asm*/ -#define POST_GLIUInit (0x01E) /* geode.asm*/ -#define POST_BootFailed (0x01F) /* geode.asm*/ - - -#define POST_CPU_ID (0x020) /* cpucpuid.asm*/ -#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ -#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ -#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ -#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ -#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ -#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ -#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ -#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ -#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ -#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ -#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ -#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ -#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ -#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ -#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ - - - -/* PCI config*/ -#define P80_PCICFG (0x030) /* pcispace.asm*/ - - -/* PCI io*/ -#define P80_PCIIO (0x040) /* pcispace.asm*/ - - -/* PCI memory*/ -#define P80_PCIMEM (0x050) /* pcispace.asm*/ - - -/* SIO*/ -#define P80_SIO (0x060) /* *sio.asm*/ - -/* Memory Setp*/ -#define P80_MEM_SETUP (0x070) /* docboot meminit*/ -#define POST_MEM_SETUP (0x070) /* memsize.asm*/ -#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ -#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ -#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ -#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ -#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ -#define POST_MEM_ENABLE (0x076) /* memsize.asm*/ -#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ -#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ -#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ -#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ -#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ -#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ -#define ERROR_BANK_SET (0x07d) /* memsize.asm*/ -#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ -#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ - - -#define POST_UserPreInit (0x080) /* geode.asm*/ -#define POST_UserPostInit (0x081) /* geode.asm*/ -#define POST_Equipment_check (0x082) /* geode.asm*/ -#define POST_InitNVRAMBX (0x083) /* geode.asm*/ -#define POST_NoPIRTable (0x084) /* pci.asm*/ -#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ -#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ -#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ -#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ -#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ -#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ -#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ - - -#define POST_STACK_SETUP (0x090) /* memstack.asm*/ -#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ -#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ -#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ -#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ -#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ -#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ -#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ -#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ - - -#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ -#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ -#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ -#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ -#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ -#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ -#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ - - -#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ -#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ -#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ -#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ -#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ -#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ -#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ - - -#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ -#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ -#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ -#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ -#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ - -#define POST_RCONFInitError (0x0CE) /* cache.asm*/ -#define POST_CacheInitError (0x0CF) /* cache.asm*/ - - -#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ -#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ -#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ -#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ -#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ -#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ -#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ -#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ -#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ -#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ -#define POST_ROM_POSTUNCOMPRESS (0x0DE) - - -#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ -#define POST_PreChipsetInit (0x0E1) /* geode.asm*/ -#define POST_LateChipsetInit (0x0E2) /* geode.asm*/ -#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ - - -#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ - - /* */ /* SB LBAR IO + MEMORY MAP*/ /* */ Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/amd/rumba/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include #include "southbridge/amd/cs5535/cs5535.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/olpc/btest/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/wyse/s50/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include +#include #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Wed Jul 28 02:27:09 2010 (r5671) @@ -10,6 +10,7 @@ #include "chip.h" #include "northbridge/amd/gx2/northbridge.h" #include +#include #include #include #include "southbridge/amd/cs5535/cs5535.h" From peter at stuge.se Wed Jul 28 02:27:26 2010 From: peter at stuge.se (Peter Stuge) Date: Wed, 28 Jul 2010 02:27:26 +0200 Subject: [coreboot] [PATCH] Geode GX2 post code patch In-Reply-To: <201007280115.19769.njacobs8@hetnet.nl> References: <201007280115.19769.njacobs8@hetnet.nl> Message-ID: <20100728002726.19984.qmail@stuge.se> Nils wrote: > This patch lets Geode GX2 use geode_post_code.h just like LX r5671 From caibaiyin.pku at gmail.com Wed Jul 28 06:47:16 2010 From: caibaiyin.pku at gmail.com (baiyin cai) Date: Wed, 28 Jul 2010 12:47:16 +0800 Subject: [coreboot] xcompile patch for libpayload In-Reply-To: References: <20100727003559.16067.qmail@stuge.se> Message-ID: hi all, i added another fix into this patch. besides of the xcoompile patch, it resolved the bug of filo+libpayload building. the bug is if libpayload is installed before filo load "make -C ../libpayload/Makefile DEST=**", it would not install correctly. Signed-off-by Cai Bai Yin 2010/7/27 Qing Pei Wang > i agree it seems pretty good... > > > On Tue, Jul 27, 2010 at 8:35 AM, Peter Stuge wrote: > >> baiyin cai wrote: >> > hi all, >> > since the xcompile file is generated for different compiler, i think >> it >> > should be included under the PHONY distclean, am i right? >> >> I think that makes good sense, but I hope to hear also from more >> people. >> >> >> > Signed-off-by Cai Bai Yin >> >> Acked-by: Peter Stuge >> >> If there's no disagreement I can commit a little later. >> >> >> //Peter >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > Wang Qing Pei > Phone: 86+13426369984 > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: xcompile-install.patch Type: application/octet-stream Size: 622 bytes Desc: not available URL: From njacobs8 at hetnet.nl Wed Jul 28 22:04:57 2010 From: njacobs8 at hetnet.nl (Nils) Date: Wed, 28 Jul 2010 22:04:57 +0200 Subject: [coreboot] [PATCH] Geode GX2 post code patch Message-ID: <201007282204.57758.njacobs8@hetnet.nl> Hi Peter, Peter wrote: >r5671 Thanks for committing the patch. Nils. From svn at coreboot.org Thu Jul 29 02:08:22 2010 From: svn at coreboot.org (repository service) Date: Thu, 29 Jul 2010 02:08:22 +0200 Subject: [coreboot] [commit] r5672 - trunk/payloads/libpayload Message-ID: Author: mjones Date: Thu Jul 29 02:08:21 2010 New Revision: 5672 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5672 Log: Resolved the bug of filo+libpayload building. The bug is if libpayload is installed before filo load "make -C ../libpayload/Makefile DEST=**", it would not install correctly. Also, distclean removes .xcompile now. Signed-off-by: Cai Bai Yin Acked-by: Peter Stuge Acked-by: Marc Jones Modified: trunk/payloads/libpayload/Makefile Modified: trunk/payloads/libpayload/Makefile ============================================================================== --- trunk/payloads/libpayload/Makefile Wed Jul 28 02:27:09 2010 (r5671) +++ trunk/payloads/libpayload/Makefile Thu Jul 29 02:08:21 2010 (r5672) @@ -163,7 +163,7 @@ distclean: clean $(Q)rm -rf build # should be $(obj) ? - $(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* + $(Q)rm -f .config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig* # This include must come _before_ the pattern rules below! # Order _does_ matter for pattern rules. @@ -182,5 +182,5 @@ endif -.PHONY: $(PHONY) prepare clean distclean doxygen doxy +.PHONY: $(PHONY) prepare install clean distclean doxygen doxy From marcj303 at gmail.com Thu Jul 29 02:09:24 2010 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 28 Jul 2010 18:09:24 -0600 Subject: [coreboot] xcompile patch for libpayload In-Reply-To: References: <20100727003559.16067.qmail@stuge.se> Message-ID: On Tue, Jul 27, 2010 at 10:47 PM, baiyin cai wrote: > hi all, > ?? i added another fix into this patch. > besides of the xcoompile patch, it resolved the bug of filo+libpayload > building. > the bug is if libpayload is installed before filo load "make -C > ../libpayload/Makefile DEST=**", it would not > install correctly. > > Signed-off-by Cai Bai Yin > > > 2010/7/27 Qing Pei Wang >> >> i agree it seems pretty good... >> >> On Tue, Jul 27, 2010 at 8:35 AM, Peter Stuge wrote: >>> >>> baiyin cai wrote: >>> > hi all, >>> > ? ?since the xcompile file is generated for different compiler, i think >>> > it >>> > should be included under the PHONY distclean, am i right? >>> >>> I think that makes good sense, but I hope to hear also from more >>> people. >>> >>> >>> > Signed-off-by Cai Bai Yin >>> >>> Acked-by: Peter Stuge >>> >>> If there's no disagreement I can commit a little later. >>> >>> >>> //Peter Acked-by: Marc Jones r5672 -- http://se-eng.com From corey.osgood at gmail.com Thu Jul 29 09:08:33 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 29 Jul 2010 03:08:33 -0400 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 Message-ID: Patch attached. -Corey -------------- next part -------------- A non-text attachment was scrubbed... Name: atom.diff Type: text/x-patch Size: 5363 bytes Desc: not available URL: From paulepanter at users.sourceforge.net Thu Jul 29 09:36:10 2010 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Thu, 29 Jul 2010 09:36:10 +0200 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: References: Message-ID: <1280388970.3873.8.camel@mattotaupa> Am Donnerstag, den 29.07.2010, 03:08 -0400 schrieb Corey Osgood: > Add support for the Intel Atom D400/500- and N400-series integrated > northbridge. Also add support for the very similar Q963/965 > northbridge. > Tested: > D510: confirmed working, with MCHBAR enable code > Q965: writes to bit 0 to enable MCHBAR access are ignored, all other > functions work > > Untested: > D410/D525/N400: should be the same northbridge Maybe add a link to the datasheets to the commit message. > Signed-off-by: Corey Osgood Acked-by: Paul Menzel If you want to you could add full stops add the end of sentences. [?] > Index: memory.c > =================================================================== > --- memory.c (revision 5670) > +++ memory.c (working copy) > @@ -47,6 +47,32 @@ > mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; > mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; > break; > + case PCI_DEVICE_ID_INTEL_Q965: > + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: > + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: > + mchbar_phys = pci_read_long(nb, 0x48); > + > + /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. > + * If it isn't, try to set it. This may fail, because there is > + * some bit that locks that bit, and isn't in the public > + * datasheets. > + */ > + > + if(!(mchbar_phys & 1)) > + { > + printf("Access to the MCHBAR is currently disabled, "\ > + "attempting to enable\n"); Full stop at the end of the sentence. > + mchbar_phys |= 0x1; > + pci_write_long(nb, 0x48, mchbar_phys); > + mchbar_phys = pci_read_long(nb, 0x48); > + if(pci_read_long(nb, 0x48) & 1) > + printf("Enabled successfully\n"); Dito. > + else > + printf("Enable FAILED!\n"); > + } > + mchbar_phys &= 0xfffffffe; > + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; > + break; > case PCI_DEVICE_ID_INTEL_82443LX: > case PCI_DEVICE_ID_INTEL_82443BX: > case PCI_DEVICE_ID_INTEL_82810: [?] -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From stefan.reinauer at coresystems.de Thu Jul 29 17:47:12 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 29 Jul 2010 17:47:12 +0200 Subject: [coreboot] [PATCH] fix potential smm security hole Message-ID: <4C51A280.4040104@coresystems.de> This patch resulted from a security review of coreboot's SMM handler. Feedback appreciated. Regards, Stefan -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: smm_update.diff URL: From joe at settoplinux.org Thu Jul 29 17:55:03 2010 From: joe at settoplinux.org (Joseph Smith) Date: Thu, 29 Jul 2010 11:55:03 -0400 Subject: [coreboot] [PATCH] fix potential smm security hole In-Reply-To: <4C51A280.4040104@coresystems.de> References: <4C51A280.4040104@coresystems.de> Message-ID: <67ee5feb36ffe92544b65648e92a06c8@imap.1and1.com> On Thu, 29 Jul 2010 17:47:12 +0200, Stefan Reinauer wrote: > This patch resulted from a security review of coreboot's SMM handler. > Feedback appreciated. > > Regards, > Stefan Hello Stefan, I thought the SMM Handler already lived at 0xa0000 instead of TSEG or HSEG. I don't really understand where the security hole is? Can you explain a little more in depth? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org From patrick at georgi-clan.de Thu Jul 29 18:01:37 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Thu, 29 Jul 2010 18:01:37 +0200 Subject: [coreboot] [PATCH] fix potential smm security hole In-Reply-To: <4C51A280.4040104@coresystems.de> References: <4C51A280.4040104@coresystems.de> Message-ID: <4C51A5E1.2060804@georgi-clan.de> Am 29.07.2010 17:47, schrieb Stefan Reinauer: > This patch resulted from a security review of coreboot's SMM handler. > Feedback appreciated. Nice patch! Acked-by: Patrick Georgi From juhe at iki.fi Thu Jul 29 18:02:04 2010 From: juhe at iki.fi (Juhana Helovuo) Date: Thu, 29 Jul 2010 19:02:04 +0300 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> <1279477333.9331.32.camel@bart> Message-ID: <1280419325.3642.24.camel@bart> Hello All, Thanks for the tip, Corey. I commented out the call to isa_dma_init(). Now there is both progress and new problems: Progress: * Coreboot runs to completion, loads a payload from CBFS, and jumps to execute it. * I managed to extract the VGA BIOS image, and add it to CBFS. It works, i.e. initializes the display, and I can see the coreboot log on VGA also. Problems: * So far no success with payloads. ** SeaBIOS gives no output at all. ** GRUB 2 only clears screen, prints "Welcome to GRUB" on VGA, and then freezes. ** Both payload images are tested to work with coreboot on QEMU. In QEMU they give sane output and try to load OS. * There is a suspicious keyboard timeout message in the log. Clearly something is out of place, but I cannot immediately figure out what to do next. Any suggestions? Best regards, Juhana Helovuo On Sun, 2010-07-18 at 15:41 -0400, Corey Osgood wrote: > The file that you're looking for is src/pc80/isa-dma.c. I suspect that > isa dma init isn't actually shutting the system down, just resetting > whatever COM you're getting serial output from. Either comment out > that dma port, or try re-initializing the serial console after doing > isa_dma_init(). > > -Corey > > On Sun, Jul 18, 2010 at 2:22 PM, Juhana Helovuo wrote: > > On Thu, 2010-06-17 at 07:31 -0600, Myles Watson wrote: > >> > Yes, here it is attached. It is copied and modified from AMD Tilapia > >> > mainboard, because that seemed to be a close relative. > >> Thanks. > >> > >> > Meanwhile, I added call to it8712f_kill_watchdog() , like Rudolf Marek > >> > suggested. That changed the behavior so that the machine no longer > >> > reboots in the middle of iterating through PCI busses and devices, but > >> > instead it seems to go on iterating infinitely, or presumably until > >> > malloc runs out of memory. > >> OK > > > > Hello again, > > > > Infinitely looping PCI scan in pci_device.c was resolved: > > > > I added the following lines to the beginning of pci_scan_bus: > > > > // Maximum sane devfn is 0xFF > > if (max_devfn > 0xff) { > > printk(BIOS_DEBUG, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n"); > > max_devfn=0xff; > > } > > > > And then the relevant part of the log is: > > > > PCI: pci_scan_bus for bus 00 > > PCI: pci_scan_bus limits devfn 0 - devfn ffffffff > > PCI: pci_scan_bus upper limit too big. Using 0xff. > > POST: 0x24 > > > > It seems that the scan loop was not infinite after all, but just tried > > to enumerate devices from 0 to 0xffffffff, which seemed like inifinity. > > I could not find out who calls pci_scan_bus, nor where does the too > > large upper limit come from. > > > > > > Now the boot process goes through bus probing and starts enabling > > devices. This goes on until it is time to enable to LPC controller, > > which I suppose is the bridge to the IT8712F Super I/O -chip. At that > > point the boot process freezes, or at least there is no more serial > > output. I added some debug printouts as follows: > > > > [src/southbridge/amd/sb700/sb700_lpc.c] > > > > static void lpc_init(device_t dev) > > { > > u8 byte; > > u32 dword; > > device_t sm_dev; > > > > printk(BIOS_DEBUG, "sb700 entering lpc_init\n"); > > /* Enable the LPC Controller */ > > sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); > > dword = pci_read_config32(sm_dev, 0x64); > > dword |= 1 << 20; > > pci_write_config32(sm_dev, 0x64, dword); > > > > /* Initialize isa dma */ > > printk(BIOS_DEBUG, "sb700 initializing isa dma\n"); > > isa_dma_init(); > > printk(BIOS_DEBUG, "sb700 isa dma initialized\n"); > > > > /* Enable DMA transaction on the LPC bus */ > > byte = pci_read_config8(dev, 0x40); > > byte |= (1 << 2); > > pci_write_config8(dev, 0x40, byte); > > printk(BIOS_DEBUG, "sb700 DMA enabled on LPC bus\n"); > > > > /* Disable the timeout mechanism on LPC */ > > byte = pci_read_config8(dev, 0x48); > > byte &= ~(1 << 7); > > pci_write_config8(dev, 0x48, byte); > > printk(BIOS_DEBUG, "sb700 LPC Timeout disabled\n"); > > > > /* Disable LPC MSI Capability */ > > byte = pci_read_config8(dev, 0x78); > > byte &= ~(1 << 1); > > pci_write_config8(dev, 0x78, byte); > > printk(BIOS_DEBUG, "sb700 exiting lpc_init\n"); > > } > > > > And the resulting end of boot log is: > > > > [...cut...] > > PCI: 00:14.1 init > > Check CBFS header at fffffd2e > > magic is 4f524243 > > Found CBFS header at fffffd2e > > Check fallback/romstage > > CBFS: follow chain: fff00000 + 38 + 14769 + align -> fff147c0 > > Check fallback/coreboot_ram > > CBFS: follow chain: fff147c0 + 38 + ddc2 + align -> fff225c0 > > Check fallback/payload > > CBFS: follow chain: fff225c0 + 38 + 22483 + align -> fff44a80 > > Check > > CBFS: follow chain: fff44a80 + 28 + bb286 + align -> fffffd40 > > CBFS: Could not find file pci1002,439c.rom > > PCI: 00:14.2 init > > base = 0xd4200000 > > codec_mask = 05 > > 2(th) codec viddid: ffffffff > > 0(th) codec viddid: ffffffff > > PCI: 00:14.3 init > > sb700 entering lpc_init > > sb700 initializing isa dma > > [log ends here] > > > > PCI tree with the factory BIOS is: > > > > # lspci -tvnn > > -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] > > +-01.0-[0000:01]--+-05.0 ATI Technologies Inc Device [1002:9710] > > | \-05.1 ATI Technologies Inc Device [1002:970f] > > +-0a.0-[0000:02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > > +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [IDE mode] [1002:4390] > > +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > > +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > > +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > > +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > > +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > > +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > > +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > > +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] > > +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > > +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] > > +-14.4-[0000:03]-- > > +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] > > +-18.0 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] > > +-18.1 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] > > +-18.2 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] > > +-18.3 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] > > \-18.4 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] > > > > > > So it seems that something goes wrong inside isa_dma_init(); > > > > Now I am not sure what I could try next. As the LPC is needed for Super > > I/O access, it seems like it cannot be just left out, and configuring > > the LPC controller to "off" will also kill the serial port. > > > > Any suggestions? > > > > Best regards, > > Juhana Helovuo > > > > > > -- > > coreboot mailing list: coreboot at coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot-asus-m4a785-m-debug-3.log Type: text/x-log Size: 83591 bytes Desc: not available URL: From mylesgw at gmail.com Thu Jul 29 18:18:19 2010 From: mylesgw at gmail.com (Myles Watson) Date: Thu, 29 Jul 2010 10:18:19 -0600 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: <1280419325.3642.24.camel@bart> References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> <1279477333.9331.32.camel@bart> <1280419325.3642.24.camel@bart> Message-ID: <824F215F44D947479B50E9EDF6151A0C@chimp> > Clearly something is out of place, but I cannot immediately figure out > what to do next. Any suggestions? Your UMA is conflicting with your Coreboot tables. It is at least part of the problem. uma_memory_start=0x70000000, uma_memory_size=0x10000000 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000006fffffff: RAM 3. 0000000070000000-000000007fffffff: RESERVED Wrote coreboot table at: 7fffe000 - 7fffe8bc checksum 3af4 Since your UMA is 0x70000000-0x7fffffff, your Coreboot tables should end up at 6fffe000, not 7fffe000. Thanks, Myles From avg at icyb.net.ua Thu Jul 29 19:14:50 2010 From: avg at icyb.net.ua (Andriy Gapon) Date: Thu, 29 Jul 2010 20:14:50 +0300 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: <1280419325.3642.24.camel@bart> References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> <1279477333.9331.32.camel@bart> <1280419325.3642.24.camel@bart> Message-ID: <4C51B70A.4040908@icyb.net.ua> Juhana Helovuo said the following: > Meanwhile, I added call to it8712f_kill_watchdog() , like Rudolf Marek > suggested. BTW, if it's not too hard, could you please share what value that register (IT8712F_CONFIG_REG_WATCHDOG) has before being reset to zero in it8712f_kill_watchdog? Thanks! -- Andriy Gapon From stefan.reinauer at coresystems.de Thu Jul 29 20:00:22 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 29 Jul 2010 20:00:22 +0200 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: References: Message-ID: <4C51C1B6.2050206@coresystems.de> On 7/29/10 9:08 AM, Corey Osgood wrote: > Add support for the Intel Atom D400/500- and N400-series integrated > northbridge. Also add support for the very similar Q963/965 northbridge. > Tested: > D510: confirmed working, with MCHBAR enable code > Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work > > Untested: > D410/D525/N400: should be the same northbridge > > Signed-off-by: Corey Osgood > Great! Got to try this on my Pineview ref board. Acked-by: Stefan Reinauer Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From rminnich at gmail.com Thu Jul 29 20:10:49 2010 From: rminnich at gmail.com (ron minnich) Date: Thu, 29 Jul 2010 11:10:49 -0700 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: <4C51C1B6.2050206@coresystems.de> References: <4C51C1B6.2050206@coresystems.de> Message-ID: Is there a good ref. board to buy to try it out? ron From stefan.reinauer at coresystems.de Thu Jul 29 21:12:34 2010 From: stefan.reinauer at coresystems.de (Stefan Reinauer) Date: Thu, 29 Jul 2010 21:12:34 +0200 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: References: <4C51C1B6.2050206@coresystems.de> Message-ID: <4C51D2A2.1030005@coresystems.de> On 7/29/10 8:10 PM, ron minnich wrote: > Is there a good ref. board to buy to try it out? > > ron > The Intel Seed Board Program is a good place to get them if you have an Intel NDA. http://edc.intel.com/Platforms/Seed-Board-Program/ I got the Advantech AIMB-212 N450 Board. The board is nice, got no comparison though. Stefan -- coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. Tel.: +49 761 7668825 ? Fax: +49 761 7664613 Email: info at coresystems.de ? http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg ? HRB 7656 Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 From svn at coreboot.org Thu Jul 29 21:25:31 2010 From: svn at coreboot.org (repository service) Date: Thu, 29 Jul 2010 21:25:31 +0200 Subject: [coreboot] [commit] r5673 - trunk/util/inteltool Message-ID: Author: cozzie Date: Thu Jul 29 21:25:31 2010 New Revision: 5673 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5673 Log: Add support for the Intel Atom D400/500- and N400-series integrated northbridge. Also add support for the very similar Q963/965 northbridge. Tested: D510: confirmed working, with MCHBAR enable code Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work Untested: D410/D525/N400: should be the same northbridge Signed-off-by: Corey Osgood Acked-by: Paul Menzel Acked-by: Stefan Reinauer Modified: trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/inteltool.c Thu Jul 29 21:25:31 2010 (r5673) @@ -41,12 +41,15 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/inteltool.h Thu Jul 29 21:25:31 2010 (r5673) @@ -62,6 +62,7 @@ #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 @@ -69,6 +70,10 @@ #define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 + +/* untested, but almost identical to D-series */ +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/memory.c Thu Jul 29 21:25:31 2010 (r5673) @@ -47,6 +47,31 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + mchbar_phys = pci_read_long(nb, 0x48); + + /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. + * If it isn't, try to set it. This may fail, because there is + * some bit that locks that bit, and isn't in the public + * datasheets. + */ + + if(!(mchbar_phys & 1)) + { + printf("Access to the MCHBAR is currently disabled, "\ + "attempting to enable.\n"); + mchbar_phys |= 0x1; + pci_write_long(nb, 0x48, mchbar_phys); + if(pci_read_long(nb, 0x48) & 1) + printf("Enabled successfully.\n"); + else + printf("Enable FAILED!\n"); + } + mchbar_phys &= 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/pcie.c Thu Jul 29 21:25:31 2010 (r5673) @@ -40,10 +40,13 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -94,10 +97,13 @@ dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; @@ -149,10 +155,13 @@ pciexbar_reg = pci_read_long(nb, 0x48); break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; From corey.osgood at gmail.com Thu Jul 29 21:27:15 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 29 Jul 2010 15:27:15 -0400 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: <4C51D2A2.1030005@coresystems.de> References: <4C51C1B6.2050206@coresystems.de> <4C51D2A2.1030005@coresystems.de> Message-ID: Committed, r5673, with a couple minor changes (remove an unnecessary read, add full stops). Thanks, Corey On Thu, Jul 29, 2010 at 3:12 PM, Stefan Reinauer wrote: > ?On 7/29/10 8:10 PM, ron minnich wrote: >> Is there a good ref. board to buy to try it out? >> >> ron >> > The Intel Seed Board Program is a good place to get them if you have an > Intel NDA. > http://edc.intel.com/Platforms/Seed-Board-Program/ > I got the Advantech AIMB-212 N450 Board. The board is nice, got no > comparison though. > > Stefan > > -- > coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br. > ? ? ?Tel.: +49 761 7668825 ? Fax: +49 761 7664613 > Email: info at coresystems.de ?? http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg ? HRB 7656 > Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866 > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From rminnich at gmail.com Thu Jul 29 22:32:07 2010 From: rminnich at gmail.com (ron minnich) Date: Thu, 29 Jul 2010 13:32:07 -0700 Subject: [coreboot] good pci card for COM1? Message-ID: Anybody got a good line on a PCI card that would implement COM1? We have this Intel smackover DX58SO mainboard that has no serial :-) thanks ron From corey.osgood at gmail.com Fri Jul 30 00:33:41 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 29 Jul 2010 15:33:41 -0700 Subject: [coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965 In-Reply-To: References: <4C51C1B6.2050206@coresystems.de> Message-ID: On Thu, Jul 29, 2010 at 11:10 AM, ron minnich wrote: > Is there a good ref. board to buy to try it out? The Zotan NM-10 DTX board has 2 PCI-E ports (one x16 one x1), a mini-PCI-E, 2 DDR2 slots, a serial header, and socketed SPI flash, which is why I chose it. Oh, and everyone on the Zotac forums complains about the buggy stock BIOS :) -Corey From corey.osgood at gmail.com Fri Jul 30 02:22:30 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Thu, 29 Jul 2010 20:22:30 -0400 Subject: [coreboot] [PATCH][inteltool] Add support for NM10 and ICH8 Message-ID: Patch attached. -Corey -------------- next part -------------- A non-text attachment was scrubbed... Name: nm10.diff Type: text/x-patch Size: 3241 bytes Desc: not available URL: From cristi.magherusan at net.utcluj.ro Fri Jul 30 10:58:11 2010 From: cristi.magherusan at net.utcluj.ro (Cristi Magherusan) Date: Fri, 30 Jul 2010 11:58:11 +0300 (EEST) Subject: [coreboot] good pci card for COM1? In-Reply-To: References: Message-ID: <31308.86.122.13.126.1280480291.squirrel@intranet.utcluj.ro> Hi Ron, ?n Joi, Iulie 29, 2010 23:32, ron minnich a scris: > Anybody got a good line on a PCI card that would implement COM1? We > have this Intel smackover DX58SO mainboard that has no serial :-) > > thanks > > ron > There are plenty such boards, but they might need a driver so YMMV. http://shop.ebay.com/?_from=R40&_trksid=p3907.m570.l1313&_nkw=pci+serial&_sacat=See-All-Categories For better speed, I recommend you the netconsole implemented by ruik for RTL8029AS. Such a card costs even less and is already supported by coreboot. http://cgi.ebay.com/RTL8029AS-based-PCI-Network-Card-/290454379625 Ruik has 20 or so and willing to ship them, but I think getting this card will be cheaper and faster than shipping from Czech Republic. Regards, Cristi -- Cristian Magherusan-Stanciu, System Engineer, Nokia Romania. From juhe at iki.fi Fri Jul 30 12:51:53 2010 From: juhe at iki.fi (Juhana Helovuo) Date: Fri, 30 Jul 2010 13:51:53 +0300 Subject: [coreboot] Porting to Asus M4A785-M In-Reply-To: <4C51B70A.4040908@icyb.net.ua> References: <1276453504.27968.52.camel@bart> <4C188515.3000409@iki.fi> <1276718131.3866.4.camel@bart> <1276780021.3607.8.camel@bart> <3C92B942FD2F45A78D16F334E642629B@chimp> <1279477333.9331.32.camel@bart> <1280419325.3642.24.camel@bart> <4C51B70A.4040908@icyb.net.ua> Message-ID: <1280487113.3642.33.camel@bart> On Thu, 2010-07-29 at 20:14 +0300, Andriy Gapon wrote: > Juhana Helovuo said the following: > > Meanwhile, I added call to it8712f_kill_watchdog() , like Rudolf Marek > > suggested. > > BTW, if it's not too hard, could you please share what value that register > (IT8712F_CONFIG_REG_WATCHDOG) has before being reset to zero in it8712f_kill_watchdog? > Thanks! > Ok, but I am not sure how one is supposed to read the Super I/O registers, since there is only a write routine. I made an educated guess and wrote a read routine as follows: Added in superio/ite/it8712f/it8712f_early_serial.c : static uint8_t it8712f_sio_read(uint8_t ldn, uint8_t index) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); outb(index, SIO_BASE); return inb(SIO_DATA); } uint8_t it8712f_kill_watchdog(void) { uint8_t prev_config; it8712f_enter_conf(); prev_config = it8712f_sio_read(0x07, IT8712F_CONFIG_REG_WATCHDOG); /* Kill the Watchdog */ it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); return prev_config; } Then in mainboard/asus/m4a785-m/romstage.c : it8712f_enable_serial(0, CONFIG_TTYS0_BASE); watchdog_prev_config = it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */ uart_init(); [...] printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); printk(BIOS_DEBUG, "Super I/O Watchdog was killed. Previous WD config was %02x\n",watchdog_prev_config); The result is: coreboot-4.0-r5631M Fri Jul 30 21:27:07 EEST 2010 starting... BSP Family_Model: 00100f62 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 Super I/O Watchdog was killed. Previous WD config was 30 Hope this makes sense, Juhana Helovuo From austinro at msu.edu Fri Jul 30 19:35:33 2010 From: austinro at msu.edu (austinro at msu.edu) Date: Fri, 30 Jul 2010 13:35:33 -0400 Subject: [coreboot] coreboot halts at "doing early_mtrr" Message-ID: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> Hi. I have a Jetway 7F4K1G5S-LF board I'm trying to get working. When I build coreboot using the J7f24 target, it doesn't get past "doing early_mtrr". I added a few print statements (and included console.h) to try to track it down, and in "include/cpu/x86/cache.h" in disable_cache it will print the statement before write_cr0(cr0); but not the one after it. I don't know what to try next. I'm doing this on a 32-bit sidux box, with gcc 4.4.4. Any ideas? Thanks, Rob Austin From patrick at georgi-clan.de Fri Jul 30 21:27:46 2010 From: patrick at georgi-clan.de (Patrick Georgi) Date: Fri, 30 Jul 2010 21:27:46 +0200 Subject: [coreboot] coreboot halts at "doing early_mtrr" In-Reply-To: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> References: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> Message-ID: <4C5327B2.50205@georgi-clan.de> Am 30.07.2010 19:35, schrieb austinro at msu.edu: > I have a Jetway 7F4K1G5S-LF board I'm trying to get working. Just to make things clear - that's a Via C7 board, yes? > Any ideas? We moved the C7 boards over to CAR (cache as RAM), but couldn't test all of them (due to availability etc). Disabling cache before RAM is available (and all data structures, esp. the stack are moved to RAM) makes the system hang. >From looking at the board's romstage.c, it seems that early_mtrr_init is ran before RAM init, but after CAR enable. Do you get further after disabling early_mtrr_init (which disables caching to activate the new MTRR config) completely? Regards, Patrick From austinro at msu.edu Fri Jul 30 23:20:32 2010 From: austinro at msu.edu (austinro at msu.edu) Date: Fri, 30 Jul 2010 17:20:32 -0400 Subject: [coreboot] coreboot halts at "doing early_mtrr" In-Reply-To: <4C5327B2.50205@georgi-clan.de> References: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> <4C5327B2.50205@georgi-clan.de> Message-ID: <20100730172032.21174yr20hesct28@mail.msu.edu> Quoting Patrick Georgi : > Am 30.07.2010 19:35, schrieb austinro at msu.edu: >> I have a Jetway 7F4K1G5S-LF board I'm trying to get working. > Just to make things clear - that's a Via C7 board, yes? Yes. >> Any ideas? > We moved the C7 boards over to CAR (cache as RAM), but couldn't test all > of them (due to availability etc). Disabling cache before RAM is > available (and all data structures, esp. the stack are moved to RAM) > makes the system hang. > > From looking at the board's romstage.c, it seems that early_mtrr_init is > ran before RAM init, but after CAR enable. > > Do you get further after disabling early_mtrr_init (which disables > caching to activate the new MTRR config) completely? Commenting out the call to early_mtrr_init() lets coreboot run to completion. That's odd. I assumed the call to "write_cr0(cr0)" in cache.h was responsible somehow, since that was where it stopped when "early_mtrr_init" called "disable_cache", but I left the print statements in disable_cache, and they were all printed repeatedly this time, so "write_cr0" only causes a problem when called early (during "early_mtrr_init")? ... Tried it again and with memtest as the payload and it doesn't see any memory. Memtest pops up on the screen : L1 cache: 64K L2 cache: 128K L3 cache: none Memory : 0K (That last one is a zero K). Hmmm. (Thanks Patrick!) From corey.osgood at gmail.com Sat Jul 31 01:29:56 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Fri, 30 Jul 2010 16:29:56 -0700 Subject: [coreboot] coreboot halts at "doing early_mtrr" In-Reply-To: <20100730172032.21174yr20hesct28@mail.msu.edu> References: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> <4C5327B2.50205@georgi-clan.de> <20100730172032.21174yr20hesct28@mail.msu.edu> Message-ID: On Fri, Jul 30, 2010 at 2:20 PM, wrote: > Quoting Patrick Georgi : > >> Am 30.07.2010 19:35, schrieb austinro at msu.edu: >>> >>> I have a Jetway 7F4K1G5S-LF board I'm trying to get working. >> >> Just to make things clear - that's a Via C7 board, yes? > > Yes. > >>> Any ideas? >> >> We moved the C7 boards over to CAR (cache as RAM), but couldn't test all >> of them (due to availability etc). Disabling cache before RAM is >> available (and all data structures, esp. the stack are moved to RAM) >> makes the system hang. >> >> From looking at the board's romstage.c, it seems that early_mtrr_init is >> ran before RAM init, but after CAR enable. >> >> Do you get further after disabling early_mtrr_init (which disables >> caching to activate the new MTRR config) completely? > > Commenting out the call to early_mtrr_init() lets coreboot run to > completion. > > That's odd. ?I assumed the call to "write_cr0(cr0)" in cache.h was > responsible somehow, since that was where it stopped when "early_mtrr_init" > called "disable_cache", but I left the print statements in disable_cache, > and they were all printed repeatedly this time, so "write_cr0" only causes a > problem when called early (during "early_mtrr_init")? > > ... > > Tried it again and with memtest as the payload and it doesn't see any > memory. ?Memtest pops up on the screen : > L1 cache: 64K > L2 cache: 128K > L3 cache: none > Memory : ? ?0K > (That last one is a zero K). > > Hmmm. Can you send me a boot log, with output level set to DEBUG or SPEW level? Thanks, Corey From austinro at msu.edu Sat Jul 31 06:14:47 2010 From: austinro at msu.edu (austinro at msu.edu) Date: Sat, 31 Jul 2010 00:14:47 -0400 Subject: [coreboot] coreboot halts at "doing early_mtrr" In-Reply-To: References: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> <4C5327B2.50205@georgi-clan.de> <20100730172032.21174yr20hesct28@mail.msu.edu> Message-ID: <20100731001447.36341y4qgv80r587@mail.msu.edu> Quoting Corey Osgood : > Just to clarify, I'm the guy who originally wrote support for the > CN700/VT8237R and J7F2 port, and I've got a little time right now that > I can check the log out to see what's going on, so the sooner you can > get that to me, the better ;) > > -Corey > > On Fri, Jul 30, 2010 at 4:29 PM, Corey Osgood wrote: >> On Fri, Jul 30, 2010 at 2:20 PM, ? wrote: >>> Quoting Patrick Georgi : >>> >>>> Am 30.07.2010 19:35, schrieb austinro at msu.edu: >>>>> >>>>> I have a Jetway 7F4K1G5S-LF board I'm trying to get working. >>>> >>>> Just to make things clear - that's a Via C7 board, yes? >>> >>> Yes. >>> >>>>> Any ideas? >>>> >>>> We moved the C7 boards over to CAR (cache as RAM), but couldn't test all >>>> of them (due to availability etc). Disabling cache before RAM is >>>> available (and all data structures, esp. the stack are moved to RAM) >>>> makes the system hang. >>>> >>>> From looking at the board's romstage.c, it seems that early_mtrr_init is >>>> ran before RAM init, but after CAR enable. >>>> >>>> Do you get further after disabling early_mtrr_init (which disables >>>> caching to activate the new MTRR config) completely? >>> >>> Commenting out the call to early_mtrr_init() lets coreboot run to >>> completion. >>> >>> That's odd. ?I assumed the call to "write_cr0(cr0)" in cache.h was >>> responsible somehow, since that was where it stopped when "early_mtrr_init" >>> called "disable_cache", but I left the print statements in disable_cache, >>> and they were all printed repeatedly this time, so "write_cr0" >>> only causes a >>> problem when called early (during "early_mtrr_init")? >>> >>> ... >>> >>> Tried it again and with memtest as the payload and it doesn't see any >>> memory. ?Memtest pops up on the screen : >>> L1 cache: 64K >>> L2 cache: 128K >>> L3 cache: none >>> Memory : ? ?0K >>> (That last one is a zero K). >>> >>> Hmmm. >> >> Can you send me a boot log, with output level set to DEBUG or SPEW level? >> >> Thanks, >> Corey >> > > Okay, I set it to debug, this is what I got: PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device In cn700 enable_dev for device PCI_DOMAIN: 0000. Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled In cn700 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 In cn700 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0314] ops PCI: 00:00.0 [1106/0314] enabled In cn700 enable_dev for device PCI: 00:00.1. PCI: 00:00.1 [1106/1314] enabled In cn700 enable_dev for device PCI: 00:00.2. PCI: 00:00.2 [1106/2314] enabled In cn700 enable_dev for device PCI: 00:00.3. PCI: 00:00.3 [1106/3208] ops PCI: 00:00.3 [1106/3208] enabled In cn700 enable_dev for device PCI: 00:00.4. PCI: 00:00.4 [1106/4314] enabled In cn700 enable_dev for device PCI: 00:00.7. PCI: 00:00.7 [1106/7314] enabled In cn700 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b198] bus ops PCI: 00:01.0 [1106/b198] enabled malloc Enter, size 68, free_mem_ptr 00020000 malloc 00020000 PCI: 00:09.0 [10ec/8167] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. malloc Enter, size 68, free_mem_ptr 00020044 malloc 00020044 PCI: 00:0b.0 [10ec/8167] enabled PCI: 00:0f.0 [1106/3149] ops PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled malloc Enter, size 68, free_mem_ptr 00020088 malloc 00020088 PCI: 00:10.5 [1106/d104] enabled PCI: 00:11.0 [1106/3227] bus ops PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 000200cc malloc 000200cc PCI: pci_scan_bus for bus 01 POST: 0x24 malloc Enter, size 68, free_mem_ptr 000200e4 malloc 000200e4 PCI: 01:00.0 [1106/3344] ops PCI: 01:00.0 [1106/3344] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 malloc Enter, size 2560, free_mem_ptr 00020128 malloc 00020128 malloc Enter, size 68, free_mem_ptr 00020b28 malloc 00020b28 malloc Enter, size 68, free_mem_ptr 00020b6c malloc 00020b6c malloc Enter, size 68, free_mem_ptr 00020bb0 malloc 00020bb0 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.4 enabled PNP: 002e.6 enabled PNP: 002e.a enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PNP: 002e.b missing read_resources PCI: 00:11.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde0 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde4 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde8 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indec PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in4 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:10.5 PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0b.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 24 * [0x800 - 0x8ff] io PCI: 00:11.5 10 * [0xc00 - 0xcff] io PCI: 00:12.0 10 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: 0 le PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:09.0 30 * [0x0 - 0x1ffff] mem PCI: 00:0b.0 30 * [0x20000 - 0x3ffff] mem PCI: 00:09.0 14 * [0x40000 - 0x400ff] mem PCI: 00:0b.0 14 * [0x40100 - 0x401ff] mem PCI: 00:10.4 10 * [0x40200 - 0x402ff] mem PCI: 00:10.5 10 * [0x40300 - 0x403ff] mem PCI: 00:12.0 14 * [0x40400 - 0x404ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 40500 size: 40500 align: 17 gran:e avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:10.5 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.1 skipping PNP: 002e.1 at 74 fixed resource, size=0! constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b skipping PNP: 002e.b at 60 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.a constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b8 align:8 gran:0 limif Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0b.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 24 * [0x1800 - 0x18ff] io Assigned: PCI: 00:11.5 10 * [0x1c00 - 0x1cff] io Assigned: PCI: 00:12.0 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b8 size: 14b8 align: 8 grae PCI_DOMAIN: 0000 allocate_resources_mem: base:feba0000 size:40500 align:17 granf Assigned: PCI: 00:09.0 30 * [0xfeba0000 - 0xfebbffff] mem Assigned: PCI: 00:0b.0 30 * [0xfebc0000 - 0xfebdffff] mem Assigned: PCI: 00:09.0 14 * [0xfebe0000 - 0xfebe00ff] mem Assigned: PCI: 00:0b.0 14 * [0xfebe0100 - 0xfebe01ff] mem Assigned: PCI: 00:10.4 10 * [0xfebe0200 - 0xfebe02ff] mem Assigned: PCI: 00:10.5 10 * [0xfebe0300 - 0xfebe03ff] mem Assigned: PCI: 00:12.0 14 * [0xfebe0400 - 0xfebe04ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: febe0500 size: 40500 align:e Root Device assign_resources, bus 0 link: 0 Entering cn700 pci_domain_set_resources. Entering find_pci_tolm Leaving find_pci_tolm tomk is 0x100000 tom: 40000000, high_tables_base: 3dff0000, high_tables_size: 10000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00febe0000 - 0x00febe00ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00feba0000 - 0x00febbffff] size 0x00020000 gran 0x11 romem PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0b.0 14 <- [0x00febe0100 - 0x00febe01ff] size 0x00000100 gran 0x08 mem PCI: 00:0b.0 30 <- [0x00febc0000 - 0x00febdffff] size 0x00020000 gran 0x11 romem PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00febe0200 - 0x00febe02ff] size 0x00000100 gran 0x08 mem PCI: 00:10.5 10 <- [0x00febe0300 - 0x00febe03ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.b missing set_resources ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.5 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febe0400 - 0x00febe04ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14b8 align 8 gran 0 limit ffff flags0 PCI_DOMAIN: 0000 resource base feba0000 size 40500 align 17 gran 0 limit febf0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000a PCI_DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 flab PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:09.0 resource base febe0000 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:09.0 resource base feba0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:0b.0 resource base febe0100 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:0b.0 resource base febc0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 600000 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 600004 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 600008 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 6004 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.4 PCI: 00:10.4 resource base febe0200 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:10.5 PCI: 00:10.5 resource base febe0300 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags e0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 PCI: 00:12.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 resource base febe0400 size 100 align 8 gran 8 limit febfffff f4 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:00.1 subsystem <- 00/00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 subsystem <- 00/00 PCI: 00:00.2 cmd <- 06 PCI: 00:00.4 subsystem <- 00/00 PCI: 00:00.4 cmd <- 06 PCI: 00:00.7 subsystem <- 00/00 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 00:09.0 cmd <- 03 PCI: 00:0b.0 cmd <- 03 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 81 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:10.5 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 done. Initializing devices... APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 6d0 CPU: family 06, model 0d, stepping 00 Detected VIA Model D C7 Enabling improved C7 clock and voltage. Voltage: 956mV (min 956mV; max 1004mV) CPU multiplier: 8x (min 8x; max 15x) msr.lo = 8000810 new msr.lo = 810 Current voltage: 956mV Current CPU multiplier: 8x POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 512MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 768MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 896MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 960MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Enabling AGP. PCI: 00:00.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,1314.rom PCI: 00:00.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,2314.rom PCI: 00:00.3 init PCI: 00:00.4 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106 coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 starting... In romstage.c:main() After reset status: 0040 Waiting for SMBus to warm upDIMM 0050 OFFSET 0002 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0008 After reset status: 0040 .Done doing early_mtrr Enabling mainboard devices DIMM 0050 OFFSET 0005 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0000 After reset status: 0040 DIMM 0050 OFFSET 001f After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0001 After reset status: 0040 DIMM 0050 OFFSET 0011 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0008 After reset status: 0040 DIMM 0050 OFFSET 0004 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 000a After reset status: 0040 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 4: Mode register set RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation Leaving romstage.c:main() Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x4000 (131072 bytes), entry @ 0x4000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 booting... POST: 0x40 Calibrating delay loop... end 545df619, start f5df60c 32-bit delta 1104 calibrate_tsc 32-bit result is 1104 clocks_per_usec: 1104 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device In cn700 enable_dev for device PCI_DOMAIN: 0000. Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled In cn700 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 In cn700 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0314] ops PCI: 00:00.0 [1106/0314] enabled In cn700 enable_dev for device PCI: 00:00.1. PCI: 00:00.1 [1106/1314] enabled In cn700 enable_dev for device PCI: 00:00.2. PCI: 00:00.2 [1106/2314] enabled In cn700 enable_dev for device PCI: 00:00.3. PCI: 00:00.3 [1106/3208] ops PCI: 00:00.3 [1106/3208] enabled In cn700 enable_dev for device PCI: 00:00.4. PCI: 00:00.4 [1106/4314] enabled In cn700 enable_dev for device PCI: 00:00.7. PCI: 00:00.7 [1106/7314] enabled In cn700 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b198] bus ops PCI: 00:01.0 [1106/b198] enabled malloc Enter, size 68, free_mem_ptr 00020000 malloc 00020000 PCI: 00:09.0 [10ec/8167] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. malloc Enter, size 68, free_mem_ptr 00020044 malloc 00020044 PCI: 00:0b.0 [10ec/8167] enabled PCI: 00:0f.0 [1106/3149] ops PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled malloc Enter, size 68, free_mem_ptr 00020088 malloc 00020088 PCI: 00:10.5 [1106/d104] enabled PCI: 00:11.0 [1106/3227] bus ops PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 000200cc malloc 000200cc PCI: pci_scan_bus for bus 01 POST: 0x24 malloc Enter, size 68, free_mem_ptr 000200e4 malloc 000200e4 PCI: 01:00.0 [1106/3344] ops PCI: 01:00.0 [1106/3344] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 malloc Enter, size 2560, free_mem_ptr 00020128 malloc 00020128 malloc Enter, size 68, free_mem_ptr 00020b28 malloc 00020b28 malloc Enter, size 68, free_mem_ptr 00020b6c malloc 00020b6c malloc Enter, size 68, free_mem_ptr 00020bb0 malloc 00020bb0 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.4 enabled PNP: 002e.6 enabled PNP: 002e.a enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PNP: 002e.b missing read_resources PCI: 00:11.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde0 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde4 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde8 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indec PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in4 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:10.5 PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0b.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 24 * [0x800 - 0x8ff] io PCI: 00:11.5 10 * [0xc00 - 0xcff] io PCI: 00:12.0 10 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: 0 le PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:09.0 30 * [0x0 - 0x1ffff] mem PCI: 00:0b.0 30 * [0x20000 - 0x3ffff] mem PCI: 00:09.0 14 * [0x40000 - 0x400ff] mem PCI: 00:0b.0 14 * [0x40100 - 0x401ff] mem PCI: 00:10.4 10 * [0x40200 - 0x402ff] mem PCI: 00:10.5 10 * [0x40300 - 0x403ff] mem PCI: 00:12.0 14 * [0x40400 - 0x404ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 40500 size: 40500 align: 17 gran:e avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:10.5 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.1 skipping PNP: 002e.1 at 74 fixed resource, size=0! constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b skipping PNP: 002e.b at 60 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.a constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b8 align:8 gran:0 limif Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0b.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 24 * [0x1800 - 0x18ff] io Assigned: PCI: 00:11.5 10 * [0x1c00 - 0x1cff] io Assigned: PCI: 00:12.0 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b8 size: 14b8 align: 8 grae PCI_DOMAIN: 0000 allocate_resources_mem: base:feba0000 size:40500 align:17 granf Assigned: PCI: 00:09.0 30 * [0xfeba0000 - 0xfebbffff] mem Assigned: PCI: 00:0b.0 30 * [0xfebc0000 - 0xfebdffff] mem Assigned: PCI: 00:09.0 14 * [0xfebe0000 - 0xfebe00ff] mem Assigned: PCI: 00:0b.0 14 * [0xfebe0100 - 0xfebe01ff] mem Assigned: PCI: 00:10.4 10 * [0xfebe0200 - 0xfebe02ff] mem Assigned: PCI: 00:10.5 10 * [0xfebe0300 - 0xfebe03ff] mem Assigned: PCI: 00:12.0 14 * [0xfebe0400 - 0xfebe04ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: febe0500 size: 40500 align:e Root Device assign_resources, bus 0 link: 0 Entering cn700 pci_domain_set_resources. Entering find_pci_tolm Leaving find_pci_tolm tomk is 0x100000 tom: 40000000, high_tables_base: 3dff0000, high_tables_size: 10000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00febe0000 - 0x00febe00ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00feba0000 - 0x00febbffff] size 0x00020000 gran 0x11 romem PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0b.0 14 <- [0x00febe0100 - 0x00febe01ff] size 0x00000100 gran 0x08 mem PCI: 00:0b.0 30 <- [0x00febc0000 - 0x00febdffff] size 0x00020000 gran 0x11 romem PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00febe0200 - 0x00febe02ff] size 0x00000100 gran 0x08 mem PCI: 00:10.5 10 <- [0x00febe0300 - 0x00febe03ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.b missing set_resources ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.5 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febe0400 - 0x00febe04ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14b8 align 8 gran 0 limit ffff flags0 PCI_DOMAIN: 0000 resource base feba0000 size 40500 align 17 gran 0 limit febf0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000a PCI_DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 flab PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:09.0 resource base febe0000 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:09.0 resource base feba0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:0b.0 resource base febe0100 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:0b.0 resource base febc0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 600000 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 600004 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 600008 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 6004 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.4 PCI: 00:10.4 resource base febe0200 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:10.5 PCI: 00:10.5 resource base febe0300 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags e0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 PCI: 00:12.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 resource base febe0400 size 100 align 8 gran 8 limit febfffff f4 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:00.1 subsystem <- 00/00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 subsystem <- 00/00 PCI: 00:00.2 cmd <- 06 PCI: 00:00.4 subsystem <- 00/00 PCI: 00:00.4 cmd <- 06 PCI: 00:00.7 subsystem <- 00/00 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 00:09.0 cmd <- 03 PCI: 00:0b.0 cmd <- 03 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 81 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:10.5 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 done. Initializing devices... APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 6d0 CPU: family 06, model 0d, stepping 00 Detected VIA Model D C7 Enabling improved C7 clock and voltage. Voltage: 956mV (min 956mV; max 1004mV) CPU multiplier: 8x (min 8x; max 15x) msr.lo = 8000810 new msr.lo = 810 Current voltage: 956mV Current CPU multiplier: 8x POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 512MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 768MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 896MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 960MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Enabling AGP. PCI: 00:00.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,1314.rom PCI: 00:00.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,2314.rom PCI: 00:00.3 init PCI: 00:00.4 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,4314.rom PCI: 00:00.7 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,7314.rom PCI: 00:01.0 init Setting up AGP bridge device PCI: 00:09.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci10ec,8167.rom On card, rom address for PCI: 00:09.0 = feba0000 PCI Expansion ROM, signature 0xfefe, INIT size 0x1fc00, data ptr 0xfefe Incorrect Expansion ROM Header Signature fefe PCI: 00:0b.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci10ec,8167.rom On card, rom address for PCI: 00:0b.0 = febc0000 PCI Expansion ROM, signature 0xfefe, INIT size 0x1fc00, data ptr 0xfefe Incorrect Expansion ROM Header Signature fefe PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0x4f Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:10.5 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,d104.rom PCI: 00:11.0 init Entering vt8237r_init. RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 Keyboard init... No PS/2 keyboard detected. Leaving vt8237r_init. PCI: 00:11.5 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,3059.rom PCI: 01:00.0 init Initializing VGA... Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom In cbfs, rom address for PCI: 01:00.0 = fff8c6b8 PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0044 PCI ROM Image, Vendor 1106, Device 3344, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff8c6b8 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 606 bytes Calling Option ROM... oprom: INT# 0x15 oprom: eax: 00005f0b ebx: 00010100 ecx: 00000044 edx: 00000110 oprom: ebp: 0001feb0 esp: 00000fc4 edi: 00000044 esi: 0000b32b oprom: ip: d14c cs: c000 flags: 00000006 via_cn700_int15_handler Unknown INT15 function 5f0b! int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f01 ebx: 00010100 ecx: 00000044 edx: 00000110 oprom: ebp: 0001feb0 esp: 00000faa edi: 00000044 esi: 0000b32b oprom: ip: d07c cs: c000 flags: 00000002 via_cn700_int15_handler oprom: INT# 0x15 oprom: eax: 00005f02 ebx: 00010001 ecx: 00000000 edx: 000003c2 oprom: ebp: 0001feb0 esp: 00000fd8 edi: 00000044 esi: 00000001 oprom: ip: d0af cs: c000 flags: 00000002 via_cn700_int15_handler oprom: INT# 0x15 oprom: eax: 00005f18 ebx: 00010200 ecx: 00000044 edx: 000003c2 oprom: ebp: 0001feb0 esp: 00000fde edi: 00000044 esi: 00000000 oprom: ip: d23f cs: c000 flags: 00000006 via_cn700_int15_handler ... Option ROM returned. PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.4 init PNP: 002e.6 init PNP: 002e.a init Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:10.5: enabled 1 PCI: 01:00.0: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.a: enabled 1 POST: 0x89 Initializing CBMEM area to 0x3dff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 3dff0200...ok High Tables Base is 3dff0000. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x3dff0400... done. PIRQ table: 192 bytes. POST: 0x9d Multiboot Information structure has been written. POST: 0x9d Adding CBMEM entry as no. 3 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum addf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3dff1400 rom_table_end = 0x3dff1400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3dff1400 to 0x3e000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000003dfeffff: RAM 3. 000000003dff0000-000000003dffffff: CONFIGURATION TABLES Wrote coreboot table at: 3dff1400 - 3dff15a8 checksum dd80 coreboot table: 424 bytes. POST: 0x9e 0. FREE SPACE 3dff3400 0000cc00 1. GDT 3dff0200 00000200 2. IRQ TABLE 3dff0400 00001000 3. COREBOOT 3dff1400 00002000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload Got a payload Loading segment from rom address 0xfff883f8 parameter section (skipped) Loading segment from rom address 0xfff88414 data (compression=0) malloc Enter, size 36, free_mem_ptr 00020bf4 malloc 00020bf4 New segment dstaddr 0x0 memsize 0x24 srcaddr 0xfff884be filesize 0x24 (cleaned up) New segment addr 0x0 size 0x24 offset 0xfff884be filesize 0x24 Loading segment from rom address 0xfff88430 data (compression=1) malloc Enter, size 36, free_mem_ptr 00020c18 malloc 00020c18 New segment dstaddr 0x100000 memsize 0x36d10 srcaddr 0xfff884e2 filesize 0x41b (cleaned up) New segment addr 0x100000 size 0x36d10 offset 0xfff884e2 filesizb Loading segment from rom address 0xfff8844c Entry Point 0x00100000 Payload is overwriting Coreboot tables. coreinfo 0.1 CPU Information qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq Vendor: IDT Processor: VIA C7 Processor 1500MHz Family: 6 Model: D Stepping: 0 CPU Speed: 800 Mhz Features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge cmov pat clflsh acpi mmx fxsr sse sse2 tm pbe F1: System F2: Firmware 06/30/2010 - 23:04:52 From corey.osgood at gmail.com Sat Jul 31 07:17:52 2010 From: corey.osgood at gmail.com (Corey Osgood) Date: Sat, 31 Jul 2010 01:17:52 -0400 Subject: [coreboot] coreboot halts at "doing early_mtrr" In-Reply-To: <20100731001447.36341y4qgv80r587@mail.msu.edu> References: <20100730133533.17208p1m5b2aon6t@mail.msu.edu> <4C5327B2.50205@georgi-clan.de> <20100730172032.21174yr20hesct28@mail.msu.edu> <20100731001447.36341y4qgv80r587@mail.msu.edu> Message-ID: On Sat, Jul 31, 2010 at 12:14 AM, wrote: > Quoting Corey Osgood : > >> Just to clarify, I'm the guy who originally wrote support for the >> CN700/VT8237R and J7F2 port, and I've got a little time right now that >> I can check the log out to see what's going on, so the sooner you can >> get that to me, the better ;) >> >> -Corey >> >> On Fri, Jul 30, 2010 at 4:29 PM, Corey Osgood >> wrote: >>> >>> On Fri, Jul 30, 2010 at 2:20 PM, ? wrote: >>>> >>>> Quoting Patrick Georgi : >>>> >>>>> Am 30.07.2010 19:35, schrieb austinro at msu.edu: >>>>>> >>>>>> I have a Jetway 7F4K1G5S-LF board I'm trying to get working. >>>>> >>>>> Just to make things clear - that's a Via C7 board, yes? >>>> >>>> Yes. >>>> >>>>>> Any ideas? >>>>> >>>>> We moved the C7 boards over to CAR (cache as RAM), but couldn't test >>>>> all >>>>> of them (due to availability etc). Disabling cache before RAM is >>>>> available (and all data structures, esp. the stack are moved to RAM) >>>>> makes the system hang. >>>>> >>>>> From looking at the board's romstage.c, it seems that early_mtrr_init >>>>> is >>>>> ran before RAM init, but after CAR enable. >>>>> >>>>> Do you get further after disabling early_mtrr_init (which disables >>>>> caching to activate the new MTRR config) completely? >>>> >>>> Commenting out the call to early_mtrr_init() lets coreboot run to >>>> completion. >>>> >>>> That's odd. ?I assumed the call to "write_cr0(cr0)" in cache.h was >>>> responsible somehow, since that was where it stopped when >>>> "early_mtrr_init" >>>> called "disable_cache", but I left the print statements in >>>> disable_cache, >>>> and they were all printed repeatedly this time, so "write_cr0" only >>>> causes a >>>> problem when called early (during "early_mtrr_init")? >>>> >>>> ... >>>> >>>> Tried it again and with memtest as the payload and it doesn't see any >>>> memory. ?Memtest pops up on the screen : >>>> L1 cache: 64K >>>> L2 cache: 128K >>>> L3 cache: none >>>> Memory : ? ?0K >>>> (That last one is a zero K). >>>> >>>> Hmmm. >>> >>> Can you send me a boot log, with output level set to DEBUG or SPEW level? >>> >>> Thanks, >>> Corey >>> >> >> > > Okay, I set it to debug, this is what I got: > Weird...is this maybe part of another log? Tomorrow I'll make a patch to get some more debugging info, but right now it's time for me to hit the sack. -Corey > > PCI: 00:0a.0: enabled 1 > PCI: 00:0f.0: enabled 1 > PCI: 00:0f.1: enabled 1 > PCI: 00:10.0: enabled 1 > PCI: 00:10.1: enabled 1 > PCI: 00:10.2: enabled 1 > PCI: 00:10.3: enabled 1 > PCI: 00:10.4: enabled 1 > PCI: 00:11.0: enabled 1 > PNP: 002e.0: enabled 0 > PNP: 002e.1: enabled 1 > PNP: 002e.2: enabled 1 > PNP: 002e.3: enabled 1 > PNP: 002e.b: enabled 1 > PCI: 00:11.5: enabled 1 > PCI: 00:12.0: enabled 1 > APIC_CLUSTER: 0: enabled 1 > APIC: 00: enabled 1 > Compare with tree... > Root Device: enabled 1 > ?PCI_DOMAIN: 0000: enabled 1 > ?PCI: 00:00.0: enabled 1 > ?PCI: 00:00.1: enabled 1 > ?PCI: 00:00.2: enabled 1 > ?PCI: 00:00.3: enabled 1 > ?PCI: 00:00.4: enabled 1 > ?PCI: 00:00.7: enabled 1 > ?PCI: 00:01.0: enabled 1 > ?PCI: 00:0a.0: enabled 1 > ?PCI: 00:0f.0: enabled 1 > ?PCI: 00:0f.1: enabled 1 > ?PCI: 00:10.0: enabled 1 > ?PCI: 00:10.1: enabled 1 > ?PCI: 00:10.2: enabled 1 > ?PCI: 00:10.3: enabled 1 > ?PCI: 00:10.4: enabled 1 > ?PCI: 00:11.0: enabled 1 > ? PNP: 002e.0: enabled 0 > ? PNP: 002e.1: enabled 1 > ? PNP: 002e.2: enabled 1 > ? PNP: 002e.3: enabled 1 > ? PNP: 002e.b: enabled 1 > ?PCI: 00:11.5: enabled 1 > ?PCI: 00:12.0: enabled 1 > ?APIC_CLUSTER: 0: enabled 1 > ?APIC: 00: enabled 1 > scan_static_bus for Root Device > In cn700 enable_dev for device PCI_DOMAIN: 0000. > Finding PCI configuration type. > PCI: Using configuration type 1 > POST: 0x5f > PCI_DOMAIN: 0000 enabled > In cn700 enable_dev for device APIC_CLUSTER: 0. > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > POST: 0x24 > In cn700 enable_dev for device PCI: 00:00.0. > PCI: 00:00.0 [1106/0314] ops > PCI: 00:00.0 [1106/0314] enabled > In cn700 enable_dev for device PCI: 00:00.1. > PCI: 00:00.1 [1106/1314] enabled > In cn700 enable_dev for device PCI: 00:00.2. > PCI: 00:00.2 [1106/2314] enabled > In cn700 enable_dev for device PCI: 00:00.3. > PCI: 00:00.3 [1106/3208] ops > PCI: 00:00.3 [1106/3208] enabled > In cn700 enable_dev for device PCI: 00:00.4. > PCI: 00:00.4 [1106/4314] enabled > In cn700 enable_dev for device PCI: 00:00.7. > PCI: 00:00.7 [1106/7314] enabled > In cn700 enable_dev for device PCI: 00:01.0. > PCI: 00:01.0 [1106/b198] bus ops > PCI: 00:01.0 [1106/b198] enabled > malloc Enter, size 68, free_mem_ptr 00020000 > malloc 00020000 > PCI: 00:09.0 [10ec/8167] enabled > PCI: Static device PCI: 00:0a.0 not found, disabling it. > malloc Enter, size 68, free_mem_ptr 00020044 > malloc 00020044 > PCI: 00:0b.0 [10ec/8167] enabled > PCI: 00:0f.0 [1106/3149] ops > PCI: 00:0f.0 [1106/3149] enabled > PCI: 00:0f.1 [1106/0571] ops > PCI: 00:0f.1 [1106/0571] enabled > PCI: 00:10.0 [1106/3038] ops > PCI: 00:10.0 [1106/3038] enabled > PCI: 00:10.1 [1106/3038] ops > PCI: 00:10.1 [1106/3038] enabled > PCI: 00:10.2 [1106/3038] ops > PCI: 00:10.2 [1106/3038] enabled > PCI: 00:10.3 [1106/3038] ops > PCI: 00:10.3 [1106/3038] enabled > PCI: 00:10.4 [1106/3104] ops > PCI: 00:10.4 [1106/3104] enabled > malloc Enter, size 68, free_mem_ptr 00020088 > malloc 00020088 > PCI: 00:10.5 [1106/d104] enabled > PCI: 00:11.0 [1106/3227] bus ops > PCI: 00:11.0 [1106/3227] enabled > PCI: 00:11.5 [1106/3059] enabled > PCI: 00:12.0 [1106/3065] ops > PCI: 00:12.0 [1106/3065] enabled > POST: 0x25 > do_pci_scan_bridge for PCI: 00:01.0 > malloc Enter, size 24, free_mem_ptr 000200cc > malloc 000200cc > PCI: pci_scan_bus for bus 01 > POST: 0x24 > malloc Enter, size 68, free_mem_ptr 000200e4 > malloc 000200e4 > PCI: 01:00.0 [1106/3344] ops > PCI: 01:00.0 [1106/3344] enabled > POST: 0x25 > PCI: pci_scan_bus returning with max=001 > POST: 0x55 > do_pci_scan_bridge returns max 1 > scan_static_bus for PCI: 00:11.0 > malloc Enter, size 2560, free_mem_ptr 00020128 > malloc 00020128 > malloc Enter, size 68, free_mem_ptr 00020b28 > malloc 00020b28 > malloc Enter, size 68, free_mem_ptr 00020b6c > malloc 00020b6c > malloc Enter, size 68, free_mem_ptr 00020bb0 > malloc 00020bb0 > PNP: 002e.0 disabled > PNP: 002e.1 enabled > PNP: 002e.2 enabled > PNP: 002e.3 enabled > PNP: 002e.b enabled > PNP: 002e.4 enabled > PNP: 002e.6 enabled > PNP: 002e.a enabled > scan_static_bus for PCI: 00:11.0 done > PCI: pci_scan_bus returning with max=001 > POST: 0x55 > scan_static_bus for Root Device done > done > POST: 0x66 > Setting up VGA for PCI: 01:00.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > Allocating resources... > Reading resources... > Root Device read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > PCI: 00:01.0 read_resources bus 1 link: 0 > PCI: 00:01.0 read_resources bus 1 link: 0 done > PCI: 00:11.0 read_resources bus 0 link: 0 > PNP: 002e.b missing read_resources > PCI: 00:11.0 read_resources bus 0 link: 0 done > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done > APIC_CLUSTER: 0 read_resources bus 0 link: 0 > APIC: 00 missing read_resources > APIC_CLUSTER: 0 read_resources bus 0 link: 0 done > Root Device read_resources bus 0 link: 0 done > Done reading resources. > Show resources in subtree (Root Device)...After reading. > ?Root Device child on link 0 PCI_DOMAIN: 0000 > ?PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 > ?PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags > 400400 > ?PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags > 40 > ? PCI: 00:00.0 > ? PCI: 00:00.1 > ? PCI: 00:00.2 > ? PCI: 00:00.3 > ? PCI: 00:00.4 > ? PCI: 00:00.7 > ? PCI: 00:01.0 child on link 0 PCI: 01:00.0 > ? ?PCI: 01:00.0 > ? ?PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff > f0 > ? ?PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff > f4 > ? ?PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > fla0 > ? PCI: 00:09.0 > ? PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ? PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff > flag0 > ? PCI: 00:0a.0 > ? PCI: 00:0b.0 > ? PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ? PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff > flag0 > ? PCI: 00:0f.0 > ? PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 > inde0 > ? PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 > inde4 > ? PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 > inde8 > ? PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 > indec > ? PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > ind0 > ? PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in4 > ? PCI: 00:0f.1 > ? PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > ind0 > ? PCI: 00:10.0 > ? PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.1 > ? PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.2 > ? PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.3 > ? PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.4 > ? PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 > ? PCI: 00:10.5 > ? PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 > ? PCI: 00:11.0 child on link 0 PNP: 002e.0 > ? PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags > e00008 > ? PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags > e000013 > ? PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags > e00000 > ? PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff > f4 > ? PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c00001 > ? ?PNP: 002e.0 > ? ?PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 > in4 > ? ?PNP: 002e.1 > ? ?PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 > in4 > ? ?PNP: 002e.2 > ? ?PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.3 > ? ?PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index > 74 > ? ?PNP: 002e.b > ? ?PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags > c00001000 > ? ?PNP: 002e.4 > ? ?PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 > index0 > ? ?PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.6 > ? ?PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.a > ? PCI: 00:11.5 > ? PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:12.0 > ? PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ?APIC_CLUSTER: 0 child on link 0 APIC: 00 > ? APIC: 00 > PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 > limit: f > PCI: 00:09.0 10 * ?[0x0 - 0xff] io > PCI: 00:0b.0 10 * ?[0x400 - 0x4ff] io > PCI: 00:0f.0 24 * ?[0x800 - 0x8ff] io > PCI: 00:11.5 10 * ?[0xc00 - 0xcff] io > PCI: 00:12.0 10 * ?[0x1000 - 0x10ff] io > PCI: 00:10.0 20 * ?[0x1400 - 0x141f] io > PCI: 00:10.1 20 * ?[0x1420 - 0x143f] io > PCI: 00:10.2 20 * ?[0x1440 - 0x145f] io > PCI: 00:10.3 20 * ?[0x1460 - 0x147f] io > PCI: 00:0f.0 20 * ?[0x1480 - 0x148f] io > PCI: 00:0f.1 20 * ?[0x1490 - 0x149f] io > PCI: 00:0f.0 10 * ?[0x14a0 - 0x14a7] io > PCI: 00:0f.0 18 * ?[0x14a8 - 0x14af] io > PCI: 00:0f.0 14 * ?[0x14b0 - 0x14b3] io > PCI: 00:0f.0 1c * ?[0x14b4 - 0x14b7] io > PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: > 0 le > PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 > limit:f > PCI: 00:09.0 30 * ?[0x0 - 0x1ffff] mem > PCI: 00:0b.0 30 * ?[0x20000 - 0x3ffff] mem > PCI: 00:09.0 14 * ?[0x40000 - 0x400ff] mem > PCI: 00:0b.0 14 * ?[0x40100 - 0x401ff] mem > PCI: 00:10.4 10 * ?[0x40200 - 0x402ff] mem > PCI: 00:10.5 10 * ?[0x40300 - 0x403ff] mem > PCI: 00:12.0 14 * ?[0x40400 - 0x404ff] mem > PCI_DOMAIN: 0000 compute_resources_mem: base: 40500 size: 40500 align: 17 > gran:e > avoid_fixed_resources: PCI_DOMAIN: 0000 > avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff > avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff > constrain_resources: PCI_DOMAIN: 0000 > constrain_resources: PCI: 00:00.0 > constrain_resources: PCI: 00:00.1 > constrain_resources: PCI: 00:00.2 > constrain_resources: PCI: 00:00.3 > constrain_resources: PCI: 00:00.4 > constrain_resources: PCI: 00:00.7 > constrain_resources: PCI: 00:01.0 > constrain_resources: PCI: 01:00.0 > constrain_resources: PCI: 00:09.0 > constrain_resources: PCI: 00:0b.0 > constrain_resources: PCI: 00:0f.0 > constrain_resources: PCI: 00:0f.1 > constrain_resources: PCI: 00:10.0 > constrain_resources: PCI: 00:10.1 > constrain_resources: PCI: 00:10.2 > constrain_resources: PCI: 00:10.3 > constrain_resources: PCI: 00:10.4 > constrain_resources: PCI: 00:10.5 > constrain_resources: PCI: 00:11.0 > constrain_resources: PNP: 002e.1 > skipping PNP: 002e.1 at 74 fixed resource, size=0! > constrain_resources: PNP: 002e.2 > constrain_resources: PNP: 002e.3 > constrain_resources: PNP: 002e.b > skipping PNP: 002e.b at 60 fixed resource, size=0! > constrain_resources: PNP: 002e.4 > constrain_resources: PNP: 002e.6 > constrain_resources: PNP: 002e.a > constrain_resources: PCI: 00:11.5 > constrain_resources: PCI: 00:12.0 > avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff > ? ? ? ?lim->base 00001000 lim->limit 0000ffff > avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff > ? ? ? ?lim->base 00000000 lim->limit febfffff > Setting resources... > PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b8 align:8 gran:0 > limif > Assigned: PCI: 00:09.0 10 * ?[0x1000 - 0x10ff] io > Assigned: PCI: 00:0b.0 10 * ?[0x1400 - 0x14ff] io > Assigned: PCI: 00:0f.0 24 * ?[0x1800 - 0x18ff] io > Assigned: PCI: 00:11.5 10 * ?[0x1c00 - 0x1cff] io > Assigned: PCI: 00:12.0 10 * ?[0x2000 - 0x20ff] io > Assigned: PCI: 00:10.0 20 * ?[0x2400 - 0x241f] io > Assigned: PCI: 00:10.1 20 * ?[0x2420 - 0x243f] io > Assigned: PCI: 00:10.2 20 * ?[0x2440 - 0x245f] io > Assigned: PCI: 00:10.3 20 * ?[0x2460 - 0x247f] io > Assigned: PCI: 00:0f.0 20 * ?[0x2480 - 0x248f] io > Assigned: PCI: 00:0f.1 20 * ?[0x2490 - 0x249f] io > Assigned: PCI: 00:0f.0 10 * ?[0x24a0 - 0x24a7] io > Assigned: PCI: 00:0f.0 18 * ?[0x24a8 - 0x24af] io > Assigned: PCI: 00:0f.0 14 * ?[0x24b0 - 0x24b3] io > Assigned: PCI: 00:0f.0 1c * ?[0x24b4 - 0x24b7] io > PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b8 size: 14b8 align: 8 > grae > PCI_DOMAIN: 0000 allocate_resources_mem: base:feba0000 size:40500 align:17 > granf > Assigned: PCI: 00:09.0 30 * ?[0xfeba0000 - 0xfebbffff] mem > Assigned: PCI: 00:0b.0 30 * ?[0xfebc0000 - 0xfebdffff] mem > Assigned: PCI: 00:09.0 14 * ?[0xfebe0000 - 0xfebe00ff] mem > Assigned: PCI: 00:0b.0 14 * ?[0xfebe0100 - 0xfebe01ff] mem > Assigned: PCI: 00:10.4 10 * ?[0xfebe0200 - 0xfebe02ff] mem > Assigned: PCI: 00:10.5 10 * ?[0xfebe0300 - 0xfebe03ff] mem > Assigned: PCI: 00:12.0 14 * ?[0xfebe0400 - 0xfebe04ff] mem > PCI_DOMAIN: 0000 allocate_resources_mem: next_base: febe0500 size: 40500 > align:e > Root Device assign_resources, bus 0 link: 0 > Entering cn700 pci_domain_set_resources. > Entering find_pci_tolm > Leaving find_pci_tolm > tomk is 0x100000 > tom: 40000000, high_tables_base: 3dff0000, high_tables_size: 10000 > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 > io > PCI: 00:09.0 14 <- [0x00febe0000 - 0x00febe00ff] size 0x00000100 gran 0x08 > mem > PCI: 00:09.0 30 <- [0x00feba0000 - 0x00febbffff] size 0x00020000 gran 0x11 > romem > PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 > io > PCI: 00:0b.0 14 <- [0x00febe0100 - 0x00febe01ff] size 0x00000100 gran 0x08 > mem > PCI: 00:0b.0 30 <- [0x00febc0000 - 0x00febdffff] size 0x00020000 gran 0x11 > romem > PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 > io > PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 > io > PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 > io > PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 > io > PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 > io > PCI: 00:0f.0 24 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 > io > PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 > io > PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 > io > PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 > io > PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 > io > PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 > io > PCI: 00:10.4 10 <- [0x00febe0200 - 0x00febe02ff] size 0x00000100 gran 0x08 > mem > PCI: 00:10.5 10 <- [0x00febe0300 - 0x00febe03ff] size 0x00000100 gran 0x08 > mem > PCI: 00:11.0 assign_resources, bus 0 link: 0 > PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io > PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 > irq > PNP: 002e.1 74 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 > drq > PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io > PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 > irq > PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io > PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 > irq > ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned > PNP: 002e.b missing set_resources > ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned > ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned > ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned > PCI: 00:11.0 assign_resources, bus 0 link: 0 > PCI: 00:11.5 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 > io > PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 > io > PCI: 00:12.0 14 <- [0x00febe0400 - 0x00febe04ff] size 0x00000100 gran 0x08 > mem > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > Root Device assign_resources, bus 0 link: 0 > Done setting resources. > Show resources in subtree (Root Device)...After assigning values. > ?Root Device child on link 0 PCI_DOMAIN: 0000 > ?PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 > ?PCI_DOMAIN: 0000 resource base 1000 size 14b8 align 8 gran 0 limit ffff > flags0 > ?PCI_DOMAIN: 0000 resource base feba0000 size 40500 align 17 gran 0 limit > febf0 > ?PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags > e000a > ?PCI_DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 > flab > ? PCI: 00:00.0 > ? PCI: 00:00.1 > ? PCI: 00:00.2 > ? PCI: 00:00.3 > ? PCI: 00:00.4 > ? PCI: 00:00.7 > ? PCI: 00:01.0 child on link 0 PCI: 01:00.0 > ? ?PCI: 01:00.0 > ? ?PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff > f0 > ? ?PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff > f4 > ? ?PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > fla0 > ? PCI: 00:09.0 > ? PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags > 6000 > ? PCI: 00:09.0 resource base febe0000 size 100 align 8 gran 8 limit febfffff > f4 > ? PCI: 00:09.0 resource base feba0000 size 20000 align 17 gran 17 limit > febfff0 > ? PCI: 00:0a.0 > ? PCI: 00:0b.0 > ? PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags > 6000 > ? PCI: 00:0b.0 resource base febe0100 size 100 align 8 gran 8 limit febfffff > f4 > ? PCI: 00:0b.0 resource base febc0000 size 20000 align 17 gran 17 limit > febfff0 > ? PCI: 00:0f.0 > ? PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags > 600000 > ? PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags > 600004 > ? PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags > 600008 > ? PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags > 60000c > ? PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags > 60000 > ? PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags > 6004 > ? PCI: 00:0f.1 > ? PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags > 60000 > ? PCI: 00:10.0 > ? PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags > 60000 > ? PCI: 00:10.1 > ? PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags > 60000 > ? PCI: 00:10.2 > ? PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags > 60000 > ? PCI: 00:10.3 > ? PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags > 60000 > ? PCI: 00:10.4 > ? PCI: 00:10.4 resource base febe0200 size 100 align 8 gran 8 limit febfffff > f0 > ? PCI: 00:10.5 > ? PCI: 00:10.5 resource base febe0300 size 100 align 8 gran 8 limit febfffff > f0 > ? PCI: 00:11.0 child on link 0 PNP: 002e.0 > ? PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags > e00008 > ? PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags > e000013 > ? PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags > e00000 > ? PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff > f4 > ? PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c00001 > ? ?PNP: 002e.0 > ? ?PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 > in4 > ? ?PNP: 002e.1 > ? ?PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags > e0000100 > ? ?PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 > in0 > ? ?PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags e0000800 > in4 > ? ?PNP: 002e.2 > ? ?PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags > e0000100 > ? ?PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 > in0 > ? ?PNP: 002e.3 > ? ?PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags > e0000100 > ? ?PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 > in0 > ? ?PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index > 74 > ? ?PNP: 002e.b > ? ?PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags > c00001000 > ? ?PNP: 002e.4 > ? ?PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 > index0 > ? ?PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.6 > ? ?PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.a > ? PCI: 00:11.5 > ? PCI: 00:11.5 resource base 1c00 size 100 align 8 gran 8 limit ffff flags > 6000 > ? PCI: 00:12.0 > ? PCI: 00:12.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags > 6000 > ? PCI: 00:12.0 resource base febe0400 size 100 align 8 gran 8 limit febfffff > f4 > ?APIC_CLUSTER: 0 child on link 0 APIC: 00 > ? APIC: 00 > Done allocating resources. > POST: 0x88 > Enabling resources... > PCI: 00:00.0 cmd <- 06 > PCI: 00:00.1 subsystem <- 00/00 > PCI: 00:00.1 cmd <- 06 > PCI: 00:00.2 subsystem <- 00/00 > PCI: 00:00.2 cmd <- 06 > PCI: 00:00.4 subsystem <- 00/00 > PCI: 00:00.4 cmd <- 06 > PCI: 00:00.7 subsystem <- 00/00 > PCI: 00:00.7 cmd <- 06 > PCI: 00:01.0 bridge ctrl <- 000b > PCI: 00:01.0 cmd <- 07 > PCI: 00:09.0 cmd <- 03 > PCI: 00:0b.0 cmd <- 03 > PCI: 00:0f.0 cmd <- 01 > PCI: 00:0f.1 cmd <- 81 > PCI: 00:10.0 cmd <- 01 > PCI: 00:10.1 cmd <- 01 > PCI: 00:10.2 cmd <- 01 > PCI: 00:10.3 cmd <- 01 > PCI: 00:10.4 cmd <- 02 > PCI: 00:10.5 cmd <- 02 > PCI: 00:11.0 cmd <- 07 > PCI: 00:11.5 subsystem <- 00/00 > PCI: 00:11.5 cmd <- 01 > PCI: 00:12.0 cmd <- 83 > PCI: 01:00.0 cmd <- 03 > done. > Initializing devices... > APIC_CLUSTER: 0 init > Initializing CPU #0 > CPU: vendor Centaur device 6d0 > CPU: family 06, model 0d, stepping 00 > Detected VIA Model D C7 > Enabling improved C7 clock and voltage. > Voltage: 956mV (min 956mV; max 1004mV) > CPU multiplier: 8x (min 8x; max 15x) > ?msr.lo = 8000810 > ?new msr.lo = 810 > Current voltage: 956mV > Current CPU multiplier: 8x > POST: 0x60 > Enabling cache > > Setting fixed MTRRs(0-88) Type: UC > Setting fixed MTRRs(0-16) Type: WB > Setting fixed MTRRs(24-88) Type: WB > DONE fixed MTRRs > call enable_fixed_mtrr() > Setting variable MTRR 0, base: ? ?0MB, range: ?512MB, type WB > ADDRESS_MASK_HIGH=0xf > Setting variable MTRR 1, base: ?512MB, range: ?256MB, type WB > ADDRESS_MASK_HIGH=0xf > Setting variable MTRR 2, base: ?768MB, range: ?128MB, type WB > ADDRESS_MASK_HIGH=0xf > Setting variable MTRR 3, base: ?896MB, range: ? 64MB, type WB > ADDRESS_MASK_HIGH=0xf > Setting variable MTRR 4, base: ?960MB, range: ? 32MB, type WB > ADDRESS_MASK_HIGH=0xf > Zero-sized MTRR range @0KB > DONE variable MTRRs > Clear out the extra MTRR's > call enable_var_mtrr() > Leave x86_setup_var_mtrrs > POST: 0x6a > > MTRR check > Fixed MTRRs ? : Enabled > Variable MTRRs: Enabled > > POST: 0x93 > Setting up local apic... apic_id: 0x00 done. > POST: 0x9b > CPU #0 initialized > PCI: 00:00.0 init > Enabling AGP. > PCI: 00:00.1 init > Check CBFS header at fffeffe0 > magic is 4f524243 > Found CBFS header at fffeffe0 > Check fallback/coreboot_ram > CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 > Check fallback/payload > CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 > Check pci1106,3344.rom > CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 > Check > CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 > CBFS: ?Could not find file pci1106,1314.rom > PCI: 00:00.2 init > Check CBFS header at fffeffe0 > magic is 4f524243 > Found CBFS header at fffeffe0 > Check fallback/coreboot_ram > CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 > Check fallback/payload > CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 > Check pci1106,3344.rom > CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 > Check > CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 > CBFS: ?Could not find file pci1106,2314.rom > PCI: 00:00.3 init > PCI: 00:00.4 init > Check CBFS header at fffeffe0 > magic is 4f524243 > Found CBFS header at fffeffe0 > Check fallback/coreboot_ram > CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 > Check fallback/payload > CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 > Check pci1106 > > coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 starting... > In romstage.c:main() > After reset status: 0040 > Waiting for SMBus to warm upDIMM 0050 OFFSET 0002 > After reset status: 0040 > Waiting until SMBus ready > Waiting until SMBus ready > Read: 0008 > After reset status: 0040 > .Done > doing early_mtrr > Enabling mainboard devices > DIMM 0050 OFFSET 0005 > After reset status: 0040 > Waiting until SMBus ready > Waiting until SMBus ready > Read: 0000 > After reset status: 0040 > DIMM 0050 OFFSET 001f > After reset status: 0040 > Waiting until SMBus ready > Waiting until SMBus ready > Read: 0001 > After reset status: 0040 > DIMM 0050 OFFSET 0011 > After reset status: 0040 > Waiting until SMBus ready > Waiting until SMBus ready > Read: 0008 > After reset status: 0040 > DIMM 0050 OFFSET 0004 > After reset status: 0040 > Waiting until SMBus ready > Waiting until SMBus ready > Read: 000a > After reset status: 0040 > RAM Enable 1: Apply NOP > RAM Enable 2: Precharge all > RAM Enable 4: Mode register set > RAM Enable 2: Precharge all > RAM Enable 3: CBR > RAM Enable 4: Mode register set > RAM Enable 5: Normal operation > Leaving romstage.c:main() > Loading stage image. > Check CBFS header at fffeffe0 > magic is 4f524243 > Found CBFS header at fffeffe0 > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x4000 (131072 bytes), entry @ 0x4000 > Stage: done loading. > Jumping to image. > POST: 0x80 > POST: 0x39 > coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 booting... > POST: 0x40 > Calibrating delay loop... > end 545df619, start f5df60c > 32-bit delta 1104 > calibrate_tsc 32-bit result is 1104 > clocks_per_usec: 1104 > Enumerating buses... > Show all devs...Before Device Enumeration. > Root Device: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:00.1: enabled 1 > PCI: 00:00.2: enabled 1 > PCI: 00:00.3: enabled 1 > PCI: 00:00.4: enabled 1 > PCI: 00:00.7: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:0a.0: enabled 1 > PCI: 00:0f.0: enabled 1 > PCI: 00:0f.1: enabled 1 > PCI: 00:10.0: enabled 1 > PCI: 00:10.1: enabled 1 > PCI: 00:10.2: enabled 1 > PCI: 00:10.3: enabled 1 > PCI: 00:10.4: enabled 1 > PCI: 00:11.0: enabled 1 > PNP: 002e.0: enabled 0 > PNP: 002e.1: enabled 1 > PNP: 002e.2: enabled 1 > PNP: 002e.3: enabled 1 > PNP: 002e.b: enabled 1 > PCI: 00:11.5: enabled 1 > PCI: 00:12.0: enabled 1 > APIC_CLUSTER: 0: enabled 1 > APIC: 00: enabled 1 > Compare with tree... > Root Device: enabled 1 > ?PCI_DOMAIN: 0000: enabled 1 > ?PCI: 00:00.0: enabled 1 > ?PCI: 00:00.1: enabled 1 > ?PCI: 00:00.2: enabled 1 > ?PCI: 00:00.3: enabled 1 > ?PCI: 00:00.4: enabled 1 > ?PCI: 00:00.7: enabled 1 > ?PCI: 00:01.0: enabled 1 > ?PCI: 00:0a.0: enabled 1 > ?PCI: 00:0f.0: enabled 1 > ?PCI: 00:0f.1: enabled 1 > ?PCI: 00:10.0: enabled 1 > ?PCI: 00:10.1: enabled 1 > ?PCI: 00:10.2: enabled 1 > ?PCI: 00:10.3: enabled 1 > ?PCI: 00:10.4: enabled 1 > ?PCI: 00:11.0: enabled 1 > ? PNP: 002e.0: enabled 0 > ? PNP: 002e.1: enabled 1 > ? PNP: 002e.2: enabled 1 > ? PNP: 002e.3: enabled 1 > ? PNP: 002e.b: enabled 1 > ?PCI: 00:11.5: enabled 1 > ?PCI: 00:12.0: enabled 1 > ?APIC_CLUSTER: 0: enabled 1 > ?APIC: 00: enabled 1 > scan_static_bus for Root Device > In cn700 enable_dev for device PCI_DOMAIN: 0000. > Finding PCI configuration type. > PCI: Using configuration type 1 > POST: 0x5f > PCI_DOMAIN: 0000 enabled > In cn700 enable_dev for device APIC_CLUSTER: 0. > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > POST: 0x24 > In cn700 enable_dev for device PCI: 00:00.0. > PCI: 00:00.0 [1106/0314] ops > PCI: 00:00.0 [1106/0314] enabled > In cn700 enable_dev for device PCI: 00:00.1. > PCI: 00:00.1 [1106/1314] enabled > In cn700 enable_dev for device PCI: 00:00.2. > PCI: 00:00.2 [1106/2314] enabled > In cn700 enable_dev for device PCI: 00:00.3. > PCI: 00:00.3 [1106/3208] ops > PCI: 00:00.3 [1106/3208] enabled > In cn700 enable_dev for device PCI: 00:00.4. > PCI: 00:00.4 [1106/4314] enabled > In cn700 enable_dev for device PCI: 00:00.7. > PCI: 00:00.7 [1106/7314] enabled > In cn700 enable_dev for device PCI: 00:01.0. > PCI: 00:01.0 [1106/b198] bus ops > PCI: 00:01.0 [1106/b198] enabled > malloc Enter, size 68, free_mem_ptr 00020000 > malloc 00020000 > PCI: 00:09.0 [10ec/8167] enabled > PCI: Static device PCI: 00:0a.0 not found, disabling it. > malloc Enter, size 68, free_mem_ptr 00020044 > malloc 00020044 > PCI: 00:0b.0 [10ec/8167] enabled > PCI: 00:0f.0 [1106/3149] ops > PCI: 00:0f.0 [1106/3149] enabled > PCI: 00:0f.1 [1106/0571] ops > PCI: 00:0f.1 [1106/0571] enabled > PCI: 00:10.0 [1106/3038] ops > PCI: 00:10.0 [1106/3038] enabled > PCI: 00:10.1 [1106/3038] ops > PCI: 00:10.1 [1106/3038] enabled > PCI: 00:10.2 [1106/3038] ops > PCI: 00:10.2 [1106/3038] enabled > PCI: 00:10.3 [1106/3038] ops > PCI: 00:10.3 [1106/3038] enabled > PCI: 00:10.4 [1106/3104] ops > PCI: 00:10.4 [1106/3104] enabled > malloc Enter, size 68, free_mem_ptr 00020088 > malloc 00020088 > PCI: 00:10.5 [1106/d104] enabled > PCI: 00:11.0 [1106/3227] bus ops > PCI: 00:11.0 [1106/3227] enabled > PCI: 00:11.5 [1106/3059] enabled > PCI: 00:12.0 [1106/3065] ops > PCI: 00:12.0 [1106/3065] enabled > POST: 0x25 > do_pci_scan_bridge for PCI: 00:01.0 > malloc Enter, size 24, free_mem_ptr 000200cc > malloc 000200cc > PCI: pci_scan_bus for bus 01 > POST: 0x24 > malloc Enter, size 68, free_mem_ptr 000200e4 > malloc 000200e4 > PCI: 01:00.0 [1106/3344] ops > PCI: 01:00.0 [1106/3344] enabled > POST: 0x25 > PCI: pci_scan_bus returning with max=001 > POST: 0x55 > do_pci_scan_bridge returns max 1 > scan_static_bus for PCI: 00:11.0 > malloc Enter, size 2560, free_mem_ptr 00020128 > malloc 00020128 > malloc Enter, size 68, free_mem_ptr 00020b28 > malloc 00020b28 > malloc Enter, size 68, free_mem_ptr 00020b6c > malloc 00020b6c > malloc Enter, size 68, free_mem_ptr 00020bb0 > malloc 00020bb0 > PNP: 002e.0 disabled > PNP: 002e.1 enabled > PNP: 002e.2 enabled > PNP: 002e.3 enabled > PNP: 002e.b enabled > PNP: 002e.4 enabled > PNP: 002e.6 enabled > PNP: 002e.a enabled > scan_static_bus for PCI: 00:11.0 done > PCI: pci_scan_bus returning with max=001 > POST: 0x55 > scan_static_bus for Root Device done > done > POST: 0x66 > Setting up VGA for PCI: 01:00.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > Allocating resources... > Reading resources... > Root Device read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > PCI: 00:01.0 read_resources bus 1 link: 0 > PCI: 00:01.0 read_resources bus 1 link: 0 done > PCI: 00:11.0 read_resources bus 0 link: 0 > PNP: 002e.b missing read_resources > PCI: 00:11.0 read_resources bus 0 link: 0 done > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done > APIC_CLUSTER: 0 read_resources bus 0 link: 0 > APIC: 00 missing read_resources > APIC_CLUSTER: 0 read_resources bus 0 link: 0 done > Root Device read_resources bus 0 link: 0 done > Done reading resources. > Show resources in subtree (Root Device)...After reading. > ?Root Device child on link 0 PCI_DOMAIN: 0000 > ?PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 > ?PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags > 400400 > ?PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags > 40 > ? PCI: 00:00.0 > ? PCI: 00:00.1 > ? PCI: 00:00.2 > ? PCI: 00:00.3 > ? PCI: 00:00.4 > ? PCI: 00:00.7 > ? PCI: 00:01.0 child on link 0 PCI: 01:00.0 > ? ?PCI: 01:00.0 > ? ?PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff > f0 > ? ?PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff > f4 > ? ?PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > fla0 > ? PCI: 00:09.0 > ? PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ? PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff > flag0 > ? PCI: 00:0a.0 > ? PCI: 00:0b.0 > ? PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ? PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff > flag0 > ? PCI: 00:0f.0 > ? PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 > inde0 > ? PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 > inde4 > ? PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 > inde8 > ? PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 > indec > ? PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > ind0 > ? PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in4 > ? PCI: 00:0f.1 > ? PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > ind0 > ? PCI: 00:10.0 > ? PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.1 > ? PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.2 > ? PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.3 > ? PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 > ind0 > ? PCI: 00:10.4 > ? PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 > ? PCI: 00:10.5 > ? PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 > ? PCI: 00:11.0 child on link 0 PNP: 002e.0 > ? PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags > e00008 > ? PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags > e000013 > ? PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags > e00000 > ? PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff > f4 > ? PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c00001 > ? ?PNP: 002e.0 > ? ?PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 > in4 > ? ?PNP: 002e.1 > ? ?PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 > in4 > ? ?PNP: 002e.2 > ? ?PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.3 > ? ?PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags > c0000100 > ? ?PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 > in0 > ? ?PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index > 74 > ? ?PNP: 002e.b > ? ?PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags > c00001000 > ? ?PNP: 002e.4 > ? ?PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 > index0 > ? ?PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.6 > ? ?PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index > 70 > ? ?PNP: 002e.a > ? PCI: 00:11.5 > ? PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:12.0 > ? PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > in0 > ? PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 204 > ?APIC_CLUSTER: 0 child on link 0 APIC: 00 > ? APIC: 00 > PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 > limit: f > PCI: 00:09.0 10 * ?[0x0 - 0xff] io > PCI: 00:0b.0 10 * ?[0x400 - 0x4ff] io > PCI: 00:0f.0 24 * ?[0x800 - 0x8ff] io > PCI: 00:11.5 10 * ?[0xc00 - 0xcff] io > PCI: 00:12.0 10 * ?[0x1000 - 0x10ff] io > PCI: 00:10.0 20 * ?[0x1400 - 0x141f] io > PCI: 00:10.1 20 * ?[0x1420 - 0x143f] io > PCI: 00:10.2 20 * ?[0x1440 - 0x145f] io > PCI: 00:10.3 20 * ?[0x1460 - 0x147f] io > PCI: 00:0f.0 20 * ?[0x1480 - 0x148f] io > PCI: 00:0f.1 20 * ?[0x1490 - 0x149f] io > PCI: 00:0f.0 10 * ?[0x14a0 - 0x14a7] io > PCI: 00:0f.0 18 * ?[0x14a8 - 0x14af] io > PCI: 00:0f.0 14 * ?[0x14b0 - 0x14b3] io > PCI: 00:0f.0 1c * ?[0x14b4 - 0x14b7] io > PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: > 0 le > PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 > limit:f > PCI: 00:09.0 30 * ?[0x0 - 0x1ffff] mem > PCI: 00:0b.0 30 * ?[0x20000 - 0x3ffff] mem > PCI: 00:09.0 14 * ?[0x40000 - 0x400ff] mem > PCI: 00:0b.0 14 * ?[0x40100 - 0x401ff] mem > PCI: 00:10.4 10 * ?[0x40200 - 0x402ff] mem > PCI: 00:10.5 10 * ?