[coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets
joe at settoplinux.org
Tue Jul 6 16:34:12 CEST 2010
On Tue, 6 Jul 2010 16:50:21 +0300, "r. ozgur doruk"
<r.ozgur.doruk at gmail.com> wrote:
> I have Pentium4 laptop motherboard of which BIOS chip is soldered out by
> some guys and it doesn't read newly programmed bios chip (a SST49lf080a)
> far as I understand since it even does not beep. And no harddisk signal,
> video and so on. In order to diagnose I have written a VHDL code (citing
> Andy Green's Milksop experiment) and then program my code on a Xilinx
> and connect it to the LPC debug board connector on the motherboard which
> the signals LAD0 - 3, LRST, LFRAME, LCLK. The job of my VHDL code is to
> convert the LPC protocol to a parallel address and data combination so
> I can at least trace what the motherboard responds. When I do that, if I
> give a long sync to the motherboard after the first address is received
> the PLD I understand that the motherboard starts to fetch the flash codes
> from the adress 0xFFFFFFD0. In fact this conforms to the script written
> the current coreboot developer as the SIS 966 has a firmware trap in the
> memory region starting from 0xFFFFFFD0. When I operate the system giving
> ready sync after each address reception to the PLD the system runs until
> showing 0xFFFFFFDF and the value stays in the CPLD address output busses.
> The same thing is observed when the board is operated without the CPU in
> I operate the mainboard without the CPU using a small hack connecting one
> the VID pins to the ground, thermal diode output to the vcc core, sckocc
> the ground and thermtrip to the vcc core. By that board thinks that CPU
> The interesting thing is that, when I measure the powergood and the reset
> inputs to the processor (by plugging the wires to the wholes as no
> is there). After the PLD address output is 0xFFFFFFDF both RESET and
> POWERGOOD inputs become active so I think that the
> mechanism is alive. I also measured all of the processor socket holes one
> one and found no problematic conditions on the socket contacts.
> The processor is heating up when operated without the heat sink and I
> noticed that thermtrip mechanism is also working as it shutdown after a
> value of temperature. Because of that I think that the processor is
> defective but again I can not be sure about that because of this firmware
> trap feature of the chipsets I mention. So are those firmware traps in
> SIS chipsets are effective on the boot process of the processor? Or any
> other reasons?
> Can I hear about your ideas?
> Thanks for all considerations
Very cool idea.
I think SerialICE debugging may be alot easier, give you better results,
and alot more information.
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