[coreboot] 3 questions about coreboot

Stefan Reinauer stefan.reinauer at coresystems.de
Wed Jul 7 11:46:41 CEST 2010

 On 7/7/10 6:42 AM, ali hagigat wrote:
> My chipset is Intel Core2Due/945/ICH7.
> I have 3 questions.
> First question:
> I wonder how PCI memory read cycles can read an instruction from
> F000:FFF0 right after reset which is the first instruction of BIOS.
x86 CPUs are designed like that. Go read the Intel®64 and IA-32
Architectures Software Developer's Manuals:

> Does Coreboot writes into PCI configuration space of Device 31 of
> ICH7-south bridge(LPC controller)? before initializing the
> configuration space of Device 0 of 82945(which is memory controller)?
What do you mean by "initializing the configuration space of Device 0 of
82945" ?

Generally, a lot of work happens before RAM is initialized. Go read the
source code for further details.

> I mean the hardware immediately accesses BIOS chip after reset but at
> some point all memory read/write cycles are claimed by 945 and memory
> controller?
No, that assumption is not true.

> Second question:
> What is the code flow of Coreboot? Where does
> it start? and how it contines?
It starts with the reset vector, which is in the "bootblock". That
bootblock loads further modules.

> Third question:
> Inside src/mainboard/kontron/986lcd-
> m/acpi we have some asl files.
> What language they have been written in? Like superio.asl

The language is called ACPI Control Message Source Language (short:
ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and


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