[coreboot] 3 questions about coreboot
hagigatali at gmail.com
Fri Jul 9 09:07:51 CEST 2010
Ok, thank you all for the replies, links and diagrams. But there are
still some ambiguities in memory read/write after reset which is done
by BIOS chip and then the memory controller !!
Immediately after reset all memory read/write cycles are claimed by
BIOS chip ultimately. The first question is that: Is memory controller
enabled after reset before writing to its configuration space? If it
is enabled, how it does not claim for memory addresses after reset?
If it is not enabled and we enable the memory controller by writing to
its configuration registers how we introduce the memory address range
used by BIOS chip here? Because the memory controller should not claim
the memory address range of the BIOS chip.
I had a general look at the configuration registers of the memory
controller, there is no register or registers to set this range of
address!! Besides there is no enable bit or something similar!!
These questions are repeated for BIOS chip and the PCI device
connected to it. Do we have to write to their configuration registers
to specify a specific range of address? Otherwise both memory
controller and the PCI device connected to the BIOS chip will claim
for that address!! Because they are being situated at the same PCI
On 7/7/10, FENG Yu Ning <fengyuning1984 at gmail.com> wrote:
> Peter Stuge wrote:
>> See http://stuge.se/pc2010.png for a sketch of the components in a
>> contemporary PC.
> Great drawing, Peter.
> ali, I would like to add some detail.
> The picture mentioned by Peter show an architecture that is closer to
> the AMD ones, in which memory controller is integrated into the CPU.
> The 945 architecture has memory controller in the northbridge.
> The bridge chips have logic deciding if the coming address access
> should be responsed by it, or should be routed to somewhere else.
> As in 945, when an address comes from CPU, the northbridge
> decides whether the address access means a memory access,
> a configuration to the chip itself, or to other devices that connects
> to it. In the case of first instruction address, the northbridge will
> pass that request to southbridge.
> Read the chipset manual for more information. Some effort is
> is needed to extract what you want from the text.
> By the way, since my knowledge is still of the single core age
> and I know little about architectures other than Intel x86, my
> explanation may not be accurate. I think someone in the list
> will correct me if that was the case.
> coreboot mailing list: coreboot at coreboot.org
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