[coreboot] 3 questions about coreboot
Eric W. Biederman
ebiederm at xmission.com
Sat Jul 17 22:23:09 CEST 2010
ali hagigat <hagigatali at gmail.com> writes:
> Ok, thank you all for the replies, links and diagrams. But there are
> still some ambiguities in memory read/write after reset which is done
> by BIOS chip and then the memory controller !!
> Immediately after reset all memory read/write cycles are claimed by
> BIOS chip ultimately. The first question is that: Is memory controller
> enabled after reset before writing to its configuration space? If it
> is enabled, how it does not claim for memory addresses after reset?
> If it is not enabled and we enable the memory controller by writing to
> its configuration registers how we introduce the memory address range
> used by BIOS chip here? Because the memory controller should not claim
> the memory address range of the BIOS chip.
> I had a general look at the configuration registers of the memory
> controller, there is no register or registers to set this range of
> address!! Besides there is no enable bit or something similar!!
> These questions are repeated for BIOS chip and the PCI device
> connected to it. Do we have to write to their configuration registers
> to specify a specific range of address? Otherwise both memory
> controller and the PCI device connected to the BIOS chip will claim
> for that address!! Because they are being situated at the same PCI
If you really want to understand this I recommend picking a board
that has a good coreboot port and getting the manuals of all of the
parts and following the code through.
Making things work in coreboot tends to be like attaching the mains to
the breaker box, turn the power on at the breaker, and the flipping
the light switch all to turn on a little light. It is very rarely as
simple as going to the destination devices and looking at it.
More information about the coreboot