[coreboot] AMD CAR quiz question

[Stefan Reinauer]

On 6/6/10 5:42 PM, Rudolf Marek wrote:
> I think it is mostly because there is memory init done by APs. Is this
> true for
> some board?
Afaik it's "ECC clearing" which is implemented several times in the
tree, including stage2.
It needs no PCI access nor console output, though... and parallelizing
the burden of PCI config space writes is not where the speedup lives.


Stefan