[coreboot] [h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting
Joe Korty
joe.korty at ccur.com
Thu Jun 10 15:38:05 CEST 2010
Hi,
As a learning experience, I've been trying to port coreboot to the
supermicro h8dme-2 w/ AMD K10. I've had not much luck either in the
learning or the porting. In any case I've got coreboot up to where it
is out of car and has started to clear memory, at which point it hangs.
I presume this is because I failed to properly set up each socket's
memory controller.
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
I started with the h8dmr_fam10 port since the h8dmr is identical, spec-wise,
to the h8dme except that it has half the number of dimm slots. Also there
is both K8 and K10 versions of coreboot for the h8dmr which in principle
makes the study of the differences a good way to learn coreboot internals.
In any case I have not been able to find where the info in spd_addr.h comes
from, so I have not been able to make it correct for my board. How does one
construct this table? In general, how does one construct devicetree.cb and
the other tables from scratch?
Is there an apprenticeship program somewhere, perhaps at some conference?
How do people in general get their coreboot skill-set jump-started?
Regards,
Joe
-------------- next part --------------
coreboot-4.0-r5628M Thu Jun 10 08:46:40 EDT 2010 starting...
Coreboot configured for H8DME-2 with K10 AMD processors
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1041, current patch id = 0x00000000
microcode: rev id (1062) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 1004
data: 04 00 00 01
AMD_CB_ManualBUIDSwapList()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 02 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
cpuSetAMDPCI 01 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f24
F3xD8: 03001615
F3xDC: 00005322
Prep FID/VID Node:01
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f24
F3xD8: 03001615
F3xDC: 00005322
setup_remote_node: 01 done
Start node 01 done.
core0 started: core0: --- { APICID = 04 NODEID = 01 COREID = 00} ---
c0mi1
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or AP stage 1: ap_apicid = 2
readback = 2010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 3
readback = 3010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 4
readback = 4010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 5
readback = 5010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 6
readback = 6010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 7
readback = 7010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c3310f26
FID Change Node:01, F3xD4: c3310f26
End FIDVIDMSR 0xc0010071 0x30b000a3 0x38035040
mcp55_num:01
...WARM RESET...
coreboot-4.0-r5628M Thu Jun 10 08:46:40 EDT 2010 starting...
Coreboot configured for H8DME-2 with K10 AMD processors
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1041, current patch id = 0x00000000
microcode: rev id (1062) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 1004
data: 04 00 00 01
AMD_CB_ManualBUIDSwapList()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 02 ff
Exit amd_ht_init()
cpuSetAMDPCI 00 done
cpuSetAMDPCI 01 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f26
F3xD8: 03001615
F3xDC: 00005322
Prep FID/VID Node:01
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f26
F3xD8: 03001615
F3xDC: 00005322
setup_remote_node: 01 done
Start node 01 done.
core0 started: 01
start_other_cores()
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fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
Node: 01 base: 00 limit: 7fffff BottomIO: e00000
Copy dram map from Node 0 to Node 01
raminit_amdmct end:
v_esp=000cbee8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
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