[coreboot] [h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting

Joe Korty joe.korty at ccur.com
Thu Jun 10 23:31:18 CEST 2010

On Thu, Jun 10, 2010 at 05:21:44PM -0400, Arne Georg Gleditsch wrote:
> Joe Korty <joe.korty at ccur.com> writes:
> > I've looked more closely; I first see a warm reset (which is normal) followed
> > by an infinite series of soft resets (which are new).  Here is the first part
> > of the log, containing the warm reset and two of thesoft resets.
> >
> > Still digesting this new development, myself.....
> >
> [..]
> > raminit_amdmct()
> > raminit_amdmct begin:
> >  Node: 01  base: 00  limit: 7fffff  BottomIO: e00000
> Looks like coreboot only finds memory on node 01.  Not sure if that's
> supposed to work or not, but I'd be surprised if it did.  I assume you
> have memory installed on node 00 as well?  You mentioned spd earlier,

FYI, the K8 version of the h8dme-2 (which works) has this comment in it.
This comment isn't in the h8dmr version (K8 or K10) nor in the h8qme
K10 version.  I wonder how the K8 version initializes the node 00 bank?
Whatever that is, I think I need it here also.


... from src/mainboard/supermicro/h8dme/romstage.c:

/* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
#define RC0 (2<<8)
#define RC1 (1<<8)

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
   don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
   memory on each CPU must be an exact match.
        static const uint16_t spd_addr[] = {

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