[coreboot] [PATCH] Convert Geode GX2 boards to CAR

[Peter Stuge]

Nils wrote:
> This patch converts the Geode GX2 boards to CAR.

Thanks! Looks good!


> Signed-off-by: Nils Jacobs <njacobs8 at hetnet.nl>


> +++ src/southbridge/amd/cs5535/cs5535_early_setup.c	(working copy)
..
> +static void cs5535_setup_iobase(void)
>  {
>  	msr_t msr;
> +	/* setup LBAR for SMBus controller */
> +	msr.hi = 0x0000f001;
> +	msr.lo = SMBUS_IO_BASE;
> +	wrmsr(MDD_LBAR_SMB, msr);

I'd really like if these weren't just #defines, but configured on a
slightly higher level. Maybe devicetree.cb - is there something there
that could fit well?


> -static void cs5535_setup_power_bottun(void)
> -{
>  	/* not implemented yet */
>  #if 0
> +static void cs5535_setup_power_button(void)
> +{

If noone is using it then maybe drop the code? Why #if 0 anyway,
linker should just not include it if not called?

I know that Ron needed some power button code for ALIX.1C.

> +++ src/southbridge/amd/cs5535/cs5535_smbus.h	(working copy)
> @@ -45,6 +45,7 @@
>  
>  #define SMBUS_IO_BASE 0x6000
>  
> +#if 0
>  static void smbus_delay(void)

Same here, why keep it?


> +++ src/southbridge/amd/cs5535/cs5535_early_smbus.c	(working copy)
..
> @@ -21,12 +21,12 @@
>  	outb(val, SMBUS_IO_BASE + SMB_ADD);
>  }
>  
> +#if 0
>  static int smbus_read_byte(unsigned device, unsigned address)
>  {
>          return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
>  }
>  
> -#if 0
>  static int smbus_recv_byte(unsigned device)
>  {

And here?


> +++ src/cpu/amd/model_gx2/Makefile.inc	(working copy)
..
> \ No newline at end of file

Please add one.


> +++ src/cpu/amd/model_gx2/cpureginit.c	(working copy)
..
> -BIST(void){

Hmm? I guess report_bist_failure(bist); does some of the same, but I
guess it does not check the MSRs?


> +void cpuRegInit (void)
..
> -	/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
> -	{
> -//		BIST();
> -	}

Hehe, it was never called. Do you know why? Is the code wrong?


> -MTestPinCheckBX (void){

Also never called? Ok.


> +++ src/cpu/amd/model_gx2/cache_as_ram.inc	(revision 0)
..
> +	post_code(0xc5)
> +DCacheSetupBad:
> +	hlt		/* issues */
> +	jmp DCacheSetupBad

Should this maybe fail more loudly than a POST code, which can be
disbled completely. Would be nice to say something on serial.


> +++ src/mainboard/wyse/s50/romstage.c	(working copy)
..
> -static void msr_init(void)
> +void main(unsigned long bist)
>  {
> -	/* Setup access to cache under 1MB.
> -	__builtin_wrmsr(CPU_RCONF_DEFAULT,  0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect.
> -								      * RomBase: 0xFFFC0
> -								      * SysTop to RomBase Properties: Write Serialize, Cache Disable.
> -								      * SysTop: 0x000A0
> -								      * System Memory Properties:  (Write Back) */
> -
> -	__builtin_wrmsr(CPU_RCONF_A0_BF,  0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */
> -	__builtin_wrmsr(CPU_RCONF_C0_DF,  0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */
> -	__builtin_wrmsr(CPU_RCONF_E0_FF,  0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */
> -	
> -	/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
> -	__builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /*	0x00000-0x7FFFF */
> -	__builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /*	0x80000-0x9FFFF */
> -	__builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /*	0xC0000-0xFFFFF */
> -	__builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /*	0x00000-0x7FFFF */
> -	__builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /*	0x80000-0x9FFFF */
> -	__builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /*	0xC0000-0xFFFFF */
> -
> -	/* put code in northbridge[init].c here */
> -}

Where is this setup done now? Was it identical for all boards?


These are all fairly minor, but I hope you can answer them. Then I'll
be happy to ack.


//Peter